| blob | 8354e26389296f23bfd49a80235e2c547b05d867 |
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
12 ;; version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ;; for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;
24 ;; See constraints.md for a description of constraints specific to s390.
25 ;;
27 ;; Special formats used for outputting 390 instructions.
28 ;;
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
39 ;;
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
49 ;;
50 ;; We have a special constraint for pattern matching.
51 ;;
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
53 ;;
55 ;;
56 ;; UNSPEC usage
57 ;;
59 (define_c_enum "unspec" [
60 ; Miscellaneous
61 UNSPEC_ROUND
62 UNSPEC_ICM
63 UNSPEC_TIE
65 ; Convert CC into a str comparison result and copy it into an
66 ; integer register
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
71 UNSPEC_CC_TO_INT
73 ; GOT/PLT and lt-relative accesses
74 UNSPEC_LTREL_OFFSET
75 UNSPEC_LTREL_BASE
76 UNSPEC_POOL_OFFSET
77 UNSPEC_GOTENT
78 UNSPEC_GOT
79 UNSPEC_GOTOFF
80 UNSPEC_PLT
81 UNSPEC_PLTOFF
83 ; Literal pool
84 UNSPEC_RELOAD_BASE
85 UNSPEC_MAIN_BASE
86 UNSPEC_LTREF
87 UNSPEC_INSN
88 UNSPEC_EXECUTE
90 ; Atomic Support
91 UNSPEC_MB
92 UNSPEC_MOVA
94 ; TLS relocation specifiers
95 UNSPEC_TLSGD
96 UNSPEC_TLSLDM
97 UNSPEC_NTPOFF
98 UNSPEC_DTPOFF
99 UNSPEC_GOTNTPOFF
100 UNSPEC_INDNTPOFF
102 ; TLS support
103 UNSPEC_TLSLDM_NTPOFF
104 UNSPEC_TLS_LOAD
106 ; String Functions
107 UNSPEC_SRST
108 UNSPEC_MVST
110 ; Stack Smashing Protector
111 UNSPEC_SP_SET
112 UNSPEC_SP_TEST
114 ; Test Data Class (TDC)
115 UNSPEC_TDC_INSN
117 ; Population Count
118 UNSPEC_POPCNT
119 UNSPEC_COPYSIGN
121 ; Load FP Integer
122 UNSPEC_FPINT_FLOOR
123 UNSPEC_FPINT_BTRUNC
124 UNSPEC_FPINT_ROUND
125 UNSPEC_FPINT_CEIL
126 UNSPEC_FPINT_NEARBYINT
127 UNSPEC_FPINT_RINT
128 ])
130 ;;
131 ;; UNSPEC_VOLATILE usage
132 ;;
134 (define_c_enum "unspecv" [
135 ; Blockage
136 UNSPECV_BLOCKAGE
138 ; TPF Support
139 UNSPECV_TPF_PROLOGUE
140 UNSPECV_TPF_EPILOGUE
142 ; Literal pool
143 UNSPECV_POOL
144 UNSPECV_POOL_SECTION
145 UNSPECV_POOL_ALIGN
146 UNSPECV_POOL_ENTRY
147 UNSPECV_MAIN_POOL
149 ; TLS support
150 UNSPECV_SET_TP
152 ; Atomic Support
153 UNSPECV_CAS
154 UNSPECV_ATOMIC_OP
156 ; Transactional Execution support
157 UNSPECV_TBEGIN
158 UNSPECV_TBEGINC
159 UNSPECV_TEND
160 UNSPECV_TABORT
161 UNSPECV_ETND
162 UNSPECV_NTSTG
163 UNSPECV_PPA
164 ])
166 ;;
167 ;; Registers
168 ;;
170 ; Registers with special meaning
172 (define_constants
173 [
174 ; Sibling call register.
175 (SIBCALL_REGNUM 1)
176 ; Literal pool base register.
177 (BASE_REGNUM 13)
178 ; Return address register.
179 (RETURN_REGNUM 14)
180 ; Condition code register.
181 (CC_REGNUM 33)
182 ; Thread local storage pointer register.
183 (TP_REGNUM 36)
184 ])
186 ; Hardware register names
188 (define_constants
189 [
190 ; General purpose registers
191 (GPR0_REGNUM 0)
192 ; Floating point registers.
193 (FPR0_REGNUM 16)
194 (FPR1_REGNUM 20)
195 (FPR2_REGNUM 17)
196 (FPR3_REGNUM 21)
197 (FPR4_REGNUM 18)
198 (FPR5_REGNUM 22)
199 (FPR6_REGNUM 19)
200 (FPR7_REGNUM 23)
201 (FPR8_REGNUM 24)
202 (FPR9_REGNUM 28)
203 (FPR10_REGNUM 25)
204 (FPR11_REGNUM 29)
205 (FPR12_REGNUM 26)
206 (FPR13_REGNUM 30)
207 (FPR14_REGNUM 27)
208 (FPR15_REGNUM 31)
209 ])
211 ;;
212 ;; PFPO GPR0 argument format
213 ;;
215 (define_constants
216 [
217 ; PFPO operation type
218 (PFPO_CONVERT 0x1000000)
219 ; PFPO operand types
220 (PFPO_OP_TYPE_SF 0x5)
221 (PFPO_OP_TYPE_DF 0x6)
222 (PFPO_OP_TYPE_TF 0x7)
223 (PFPO_OP_TYPE_SD 0x8)
224 (PFPO_OP_TYPE_DD 0x9)
225 (PFPO_OP_TYPE_TD 0xa)
226 ; Bitposition of operand types
227 (PFPO_OP0_TYPE_SHIFT 16)
228 (PFPO_OP1_TYPE_SHIFT 8)
229 ])
231 ; Immediate operands for tbegin and tbeginc
232 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
233 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
235 ;; Instruction operand type as used in the Principles of Operation.
236 ;; Used to determine defaults for length and other attribute values.
238 (define_attr "op_type"
239 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
240 (const_string "NN"))
242 ;; Instruction type attribute used for scheduling.
244 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
245 cs,vs,store,sem,idiv,
246 imulhi,imulsi,imuldi,
247 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
248 floadtf,floaddf,floadsf,fstoredf,fstoresf,
249 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
250 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
251 fmadddf,fmaddsf,
252 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
253 itoftf, itofdf, itofsf, itofdd, itoftd,
254 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
255 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
256 ftoidfp, other"
257 (cond [(eq_attr "op_type" "NN") (const_string "other")
258 (eq_attr "op_type" "SS") (const_string "cs")]
259 (const_string "integer")))
261 ;; Another attribute used for scheduling purposes:
262 ;; agen: Instruction uses the address generation unit
263 ;; reg: Instruction does not use the agen unit
265 (define_attr "atype" "agen,reg"
266 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
267 (const_string "reg")
268 (const_string "agen")))
270 ;; Properties concerning Z10 execution grouping and value forwarding.
271 ;; z10_super: instruction is superscalar.
272 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
273 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
274 ;; target register. It can forward this value to a second instruction that reads
275 ;; the same register if that second instruction is issued in the same group.
276 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
277 ;; instruction in the S pipe writes to the register, then the T instruction
278 ;; can immediately read the new value.
279 ;; z10_fr: union of Z10_fwd and z10_rec.
280 ;; z10_c: second operand of instruction is a register and read with complemented bits.
281 ;;
282 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
285 (define_attr "z10prop" "none,
286 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
287 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
288 z10_rec,
289 z10_fr, z10_fr_A3, z10_fr_E1,
290 z10_c"
291 (const_string "none"))
293 ;; Properties concerning Z196 decoding
294 ;; z196_alone: must group alone
295 ;; z196_end: ends a group
296 ;; z196_cracked: instruction is cracked or expanded
297 (define_attr "z196prop" "none,
298 z196_alone, z196_ends,
299 z196_cracked"
300 (const_string "none"))
302 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
304 ;; Length in bytes.
306 (define_attr "length" ""
307 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
308 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
309 (const_int 6)))
312 ;; Processor type. This attribute must exactly match the processor_type
313 ;; enumeration in s390.h. The current machine description does not
314 ;; distinguish between g5 and g6, but there are differences between the two
315 ;; CPUs could in theory be modeled.
317 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
318 (const (symbol_ref "s390_tune_attr")))
320 (define_attr "cpu_facility"
321 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12"
322 (const_string "standard"))
324 (define_attr "enabled" ""
325 (cond [(eq_attr "cpu_facility" "standard")
326 (const_int 1)
328 (and (eq_attr "cpu_facility" "ieee")
329 (match_test "TARGET_CPU_IEEE_FLOAT"))
330 (const_int 1)
332 (and (eq_attr "cpu_facility" "zarch")
333 (match_test "TARGET_ZARCH"))
334 (const_int 1)
336 (and (eq_attr "cpu_facility" "longdisp")
337 (match_test "TARGET_LONG_DISPLACEMENT"))
338 (const_int 1)
340 (and (eq_attr "cpu_facility" "extimm")
341 (match_test "TARGET_EXTIMM"))
342 (const_int 1)
344 (and (eq_attr "cpu_facility" "dfp")
345 (match_test "TARGET_DFP"))
346 (const_int 1)
348 (and (eq_attr "cpu_facility" "cpu_zarch")
349 (match_test "TARGET_CPU_ZARCH"))
350 (const_int 1)
352 (and (eq_attr "cpu_facility" "z10")
353 (match_test "TARGET_Z10"))
354 (const_int 1)
356 (and (eq_attr "cpu_facility" "z196")
357 (match_test "TARGET_Z196"))
358 (const_int 1)
360 (and (eq_attr "cpu_facility" "zEC12")
361 (match_test "TARGET_ZEC12"))
362 (const_int 1)]
363 (const_int 0)))
365 ;; Pipeline description for z900. For lack of anything better,
366 ;; this description is also used for the g5 and g6.
367 (include "2064.md")
369 ;; Pipeline description for z990, z9-109 and z9-ec.
370 (include "2084.md")
372 ;; Pipeline description for z10
373 (include "2097.md")
375 ;; Pipeline description for z196
376 (include "2817.md")
378 ;; Pipeline description for zEC12
379 (include "2827.md")
381 ;; Predicates
382 (include "predicates.md")
384 ;; Constraint definitions
385 (include "constraints.md")
387 ;; Other includes
388 (include "tpf.md")
390 ;; Iterators
392 ;; These mode iterators allow floating point patterns to be generated from the
393 ;; same template.
394 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
395 (SD "TARGET_HARD_DFP")])
396 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
397 (define_mode_iterator FPALL [TF DF SF TD DD SD])
398 (define_mode_iterator BFP [TF DF SF])
399 (define_mode_iterator DFP [TD DD])
400 (define_mode_iterator DFP_ALL [TD DD SD])
401 (define_mode_iterator DSF [DF SF])
402 (define_mode_iterator SD_SF [SF SD])
403 (define_mode_iterator DD_DF [DF DD])
404 (define_mode_iterator TD_TF [TF TD])
406 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
407 ;; from the same template.
408 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
409 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
410 (define_mode_iterator DSI [DI SI])
411 (define_mode_iterator TDI [TI DI])
413 ;; These mode iterators allow :P to be used for patterns that operate on
414 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
415 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
417 ;; These macros refer to the actual word_mode of the configuration.
418 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
419 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
420 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
422 ;; Used by the umul pattern to express modes having half the size.
423 (define_mode_attr DWH [(TI "DI") (DI "SI")])
424 (define_mode_attr dwh [(TI "di") (DI "si")])
426 ;; This mode iterator allows the QI and HI patterns to be defined from
427 ;; the same template.
428 (define_mode_iterator HQI [HI QI])
430 ;; This mode iterator allows the integer patterns to be defined from the
431 ;; same template.
432 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
433 (define_mode_iterator INTALL [TI DI SI HI QI])
434 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
436 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
437 ;; the same template.
438 (define_code_iterator SHIFT [ashift lshiftrt])
440 ;; This iterator allows r[ox]sbg to be defined with the same template
441 (define_code_iterator IXOR [ior xor])
443 ;; This iterator is used to expand the patterns for the nearest
444 ;; integer functions.
445 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
446 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
447 UNSPEC_FPINT_NEARBYINT])
448 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
449 (UNSPEC_FPINT_BTRUNC "btrunc")
450 (UNSPEC_FPINT_ROUND "round")
451 (UNSPEC_FPINT_CEIL "ceil")
452 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
453 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
454 (UNSPEC_FPINT_BTRUNC "5")
455 (UNSPEC_FPINT_ROUND "1")
456 (UNSPEC_FPINT_CEIL "6")
457 (UNSPEC_FPINT_NEARBYINT "0")])
459 ;; This iterator and attribute allow to combine most atomic operations.
460 (define_code_iterator ATOMIC [and ior xor plus minus mult])
461 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
462 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
463 (plus "add") (minus "sub") (mult "nand")])
464 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
466 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
467 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
468 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
470 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
471 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
472 ;; SDmode.
473 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
475 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
476 ;; Likewise for "<RXe>".
477 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
478 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
480 ;; The decimal floating point variants of add, sub, div and mul support 3
481 ;; fp register operands. The following attributes allow to merge the bfp and
482 ;; dfp variants in a single insn definition.
484 ;; This attribute is used to set op_type accordingly.
485 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
486 (DD "RRR") (SD "RRR")])
488 ;; This attribute is used in the operand constraint list in order to have the
489 ;; first and the second operand match for bfp modes.
490 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
492 ;; This attribute is used in the operand list of the instruction to have an
493 ;; additional operand for the dfp instructions.
494 (define_mode_attr op1 [(TF "") (DF "") (SF "")
495 (TD "%1,") (DD "%1,") (SD "%1,")])
498 ;; This attribute is used in the operand constraint list
499 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
500 ;; TFmode values are represented by a fp register pair. Since the
501 ;; sign bit instructions only handle single source and target fp registers
502 ;; these instructions can only be used for TFmode values if the source and
503 ;; target operand uses the same fp register.
504 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
506 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
507 ;; This is used to disable the memory alternative in TFmode patterns.
508 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
510 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
511 ;; within instruction mnemonics.
512 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
514 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
515 ;; modes and to an empty string for bfp modes.
516 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
518 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
519 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
520 ;; version only operates on one register.
521 (define_mode_attr d0 [(DI "d") (SI "0")])
523 ;; In combination with d0 this allows to combine instructions of which the 31bit
524 ;; version only operates on one register. The DImode version needs an additional
525 ;; register for the assembler output.
526 (define_mode_attr 1 [(DI "%1,") (SI "")])
528 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
529 ;; 'ashift' and "srdl" in 'lshiftrt'.
530 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
532 ;; In SHIFT templates, this attribute holds the correct standard name for the
533 ;; pattern itself and the corresponding function calls.
534 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
536 ;; This attribute handles differences in the instruction 'type' and will result
537 ;; in "RRE" for DImode and "RR" for SImode.
538 (define_mode_attr E [(DI "E") (SI "")])
540 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
541 ;; to result in "RXY" for DImode and "RX" for SImode.
542 (define_mode_attr Y [(DI "Y") (SI "")])
544 ;; This attribute handles differences in the instruction 'type' and will result
545 ;; in "RSE" for TImode and "RS" for DImode.
546 (define_mode_attr TE [(TI "E") (DI "")])
548 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
549 ;; and "lcr" in SImode.
550 (define_mode_attr g [(DI "g") (SI "")])
552 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
553 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
554 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
555 ;; variant for long displacements.
556 (define_mode_attr y [(DI "g") (SI "y")])
558 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
559 ;; and "cds" in DImode.
560 (define_mode_attr tg [(TI "g") (DI "")])
562 ;; In TDI templates, a string like "c<d>sg".
563 (define_mode_attr td [(TI "d") (DI "")])
565 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
566 ;; and "cfdbr" in SImode.
567 (define_mode_attr gf [(DI "g") (SI "f")])
569 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
570 ;; and sllk for SI. This way it is possible to merge the new z196 SI
571 ;; 3 operands shift instructions into the existing patterns.
572 (define_mode_attr gk [(DI "g") (SI "k")])
574 ;; ICM mask required to load MODE value into the lowest subreg
575 ;; of a SImode register.
576 (define_mode_attr icm_lo [(HI "3") (QI "1")])
578 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
579 ;; HImode and "llgc" in QImode.
580 (define_mode_attr hc [(HI "h") (QI "c")])
582 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
583 ;; in SImode.
584 (define_mode_attr DBL [(DI "TI") (SI "DI")])
586 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
587 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
588 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
590 ;; Maximum unsigned integer that fits in MODE.
591 (define_mode_attr max_uint [(HI "65535") (QI "255")])
593 ;; Start and end field computations for RISBG et al.
594 (define_mode_attr bfstart [(DI "s") (SI "t")])
595 (define_mode_attr bfend [(DI "e") (SI "f")])
597 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
598 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
600 ;;
601 ;;- Compare instructions.
602 ;;
604 ; Test-under-Mask instructions
606 (define_insn "*tmqi_mem"
607 [(set (reg CC_REGNUM)
608 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
609 (match_operand:QI 1 "immediate_operand" "n,n"))
610 (match_operand:QI 2 "immediate_operand" "n,n")))]
611 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
612 "@
613 tm\t%S0,%b1
614 tmy\t%S0,%b1"
615 [(set_attr "op_type" "SI,SIY")
616 (set_attr "z10prop" "z10_super,z10_super")])
618 (define_insn "*tmdi_reg"
619 [(set (reg CC_REGNUM)
620 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
621 (match_operand:DI 1 "immediate_operand"
622 "N0HD0,N1HD0,N2HD0,N3HD0"))
623 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
624 "TARGET_ZARCH
625 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
626 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
627 "@
628 tmhh\t%0,%i1
629 tmhl\t%0,%i1
630 tmlh\t%0,%i1
631 tmll\t%0,%i1"
632 [(set_attr "op_type" "RI")
633 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
635 (define_insn "*tmsi_reg"
636 [(set (reg CC_REGNUM)
637 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
638 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
639 (match_operand:SI 2 "immediate_operand" "n,n")))]
640 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
641 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
642 "@
643 tmh\t%0,%i1
644 tml\t%0,%i1"
645 [(set_attr "op_type" "RI")
646 (set_attr "z10prop" "z10_super,z10_super")])
648 (define_insn "*tm<mode>_full"
649 [(set (reg CC_REGNUM)
650 (compare (match_operand:HQI 0 "register_operand" "d")
651 (match_operand:HQI 1 "immediate_operand" "n")))]
652 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
653 "tml\t%0,<max_uint>"
654 [(set_attr "op_type" "RI")
655 (set_attr "z10prop" "z10_super")])
658 ;
659 ; Load-and-Test instructions
660 ;
662 ; tst(di|si) instruction pattern(s).
664 (define_insn "*tstdi_sign"
665 [(set (reg CC_REGNUM)
666 (compare
667 (ashiftrt:DI
668 (ashift:DI
669 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
670 (const_int 32)) (const_int 32))
671 (match_operand:DI 1 "const0_operand" "")))
672 (set (match_operand:DI 2 "register_operand" "=d,d")
673 (sign_extend:DI (match_dup 0)))]
674 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
675 "ltgfr\t%2,%0
676 ltgf\t%2,%0"
677 [(set_attr "op_type" "RRE,RXY")
678 (set_attr "cpu_facility" "*,z10")
679 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
681 ; ltr, lt, ltgr, ltg
682 (define_insn "*tst<mode>_extimm"
683 [(set (reg CC_REGNUM)
684 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
685 (match_operand:GPR 1 "const0_operand" "")))
686 (set (match_operand:GPR 2 "register_operand" "=d,d")
687 (match_dup 0))]
688 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
689 "@
690 lt<g>r\t%2,%0
691 lt<g>\t%2,%0"
692 [(set_attr "op_type" "RR<E>,RXY")
693 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
695 ; ltr, lt, ltgr, ltg
696 (define_insn "*tst<mode>_cconly_extimm"
697 [(set (reg CC_REGNUM)
698 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
699 (match_operand:GPR 1 "const0_operand" "")))
700 (clobber (match_scratch:GPR 2 "=X,d"))]
701 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
702 "@
703 lt<g>r\t%0,%0
704 lt<g>\t%2,%0"
705 [(set_attr "op_type" "RR<E>,RXY")
706 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
708 (define_insn "*tstdi"
709 [(set (reg CC_REGNUM)
710 (compare (match_operand:DI 0 "register_operand" "d")
711 (match_operand:DI 1 "const0_operand" "")))
712 (set (match_operand:DI 2 "register_operand" "=d")
713 (match_dup 0))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
715 "ltgr\t%2,%0"
716 [(set_attr "op_type" "RRE")
717 (set_attr "z10prop" "z10_fr_E1")])
719 (define_insn "*tstsi"
720 [(set (reg CC_REGNUM)
721 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
722 (match_operand:SI 1 "const0_operand" "")))
723 (set (match_operand:SI 2 "register_operand" "=d,d,d")
724 (match_dup 0))]
725 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
726 "@
727 ltr\t%2,%0
728 icm\t%2,15,%S0
729 icmy\t%2,15,%S0"
730 [(set_attr "op_type" "RR,RS,RSY")
731 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
733 (define_insn "*tstsi_cconly"
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
736 (match_operand:SI 1 "const0_operand" "")))
737 (clobber (match_scratch:SI 2 "=X,d,d"))]
738 "s390_match_ccmode(insn, CCSmode)"
739 "@
740 ltr\t%0,%0
741 icm\t%2,15,%S0
742 icmy\t%2,15,%S0"
743 [(set_attr "op_type" "RR,RS,RSY")
744 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
746 (define_insn "*tstdi_cconly_31"
747 [(set (reg CC_REGNUM)
748 (compare (match_operand:DI 0 "register_operand" "d")
749 (match_operand:DI 1 "const0_operand" "")))]
750 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
751 "srda\t%0,0"
752 [(set_attr "op_type" "RS")
753 (set_attr "atype" "reg")])
755 ; ltr, ltgr
756 (define_insn "*tst<mode>_cconly2"
757 [(set (reg CC_REGNUM)
758 (compare (match_operand:GPR 0 "register_operand" "d")
759 (match_operand:GPR 1 "const0_operand" "")))]
760 "s390_match_ccmode(insn, CCSmode)"
761 "lt<g>r\t%0,%0"
762 [(set_attr "op_type" "RR<E>")
763 (set_attr "z10prop" "z10_fr_E1")])
765 ; tst(hi|qi) instruction pattern(s).
767 (define_insn "*tst<mode>CCT"
768 [(set (reg CC_REGNUM)
769 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
770 (match_operand:HQI 1 "const0_operand" "")))
771 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
772 (match_dup 0))]
773 "s390_match_ccmode(insn, CCTmode)"
774 "@
775 icm\t%2,<icm_lo>,%S0
776 icmy\t%2,<icm_lo>,%S0
777 tml\t%0,<max_uint>"
778 [(set_attr "op_type" "RS,RSY,RI")
779 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
781 (define_insn "*tsthiCCT_cconly"
782 [(set (reg CC_REGNUM)
783 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
784 (match_operand:HI 1 "const0_operand" "")))
785 (clobber (match_scratch:HI 2 "=d,d,X"))]
786 "s390_match_ccmode(insn, CCTmode)"
787 "@
788 icm\t%2,3,%S0
789 icmy\t%2,3,%S0
790 tml\t%0,65535"
791 [(set_attr "op_type" "RS,RSY,RI")
792 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
794 (define_insn "*tstqiCCT_cconly"
795 [(set (reg CC_REGNUM)
796 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
797 (match_operand:QI 1 "const0_operand" "")))]
798 "s390_match_ccmode(insn, CCTmode)"
799 "@
800 cli\t%S0,0
801 cliy\t%S0,0
802 tml\t%0,255"
803 [(set_attr "op_type" "SI,SIY,RI")
804 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
806 (define_insn "*tst<mode>"
807 [(set (reg CC_REGNUM)
808 (compare (match_operand:HQI 0 "s_operand" "Q,S")
809 (match_operand:HQI 1 "const0_operand" "")))
810 (set (match_operand:HQI 2 "register_operand" "=d,d")
811 (match_dup 0))]
812 "s390_match_ccmode(insn, CCSmode)"
813 "@
814 icm\t%2,<icm_lo>,%S0
815 icmy\t%2,<icm_lo>,%S0"
816 [(set_attr "op_type" "RS,RSY")
817 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
819 (define_insn "*tst<mode>_cconly"
820 [(set (reg CC_REGNUM)
821 (compare (match_operand:HQI 0 "s_operand" "Q,S")
822 (match_operand:HQI 1 "const0_operand" "")))
823 (clobber (match_scratch:HQI 2 "=d,d"))]
824 "s390_match_ccmode(insn, CCSmode)"
825 "@
826 icm\t%2,<icm_lo>,%S0
827 icmy\t%2,<icm_lo>,%S0"
828 [(set_attr "op_type" "RS,RSY")
829 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
832 ; Compare (equality) instructions
834 (define_insn "*cmpdi_cct"
835 [(set (reg CC_REGNUM)
836 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
837 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
838 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
839 "@
840 cgr\t%0,%1
841 cghi\t%0,%h1
842 cgfi\t%0,%1
843 cg\t%0,%1
844 #"
845 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
846 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
848 (define_insn "*cmpsi_cct"
849 [(set (reg CC_REGNUM)
850 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
851 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
852 "s390_match_ccmode (insn, CCTmode)"
853 "@
854 cr\t%0,%1
855 chi\t%0,%h1
856 cfi\t%0,%1
857 c\t%0,%1
858 cy\t%0,%1
859 #"
860 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
861 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
863 ; Compare (signed) instructions
865 (define_insn "*cmpdi_ccs_sign"
866 [(set (reg CC_REGNUM)
867 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
868 "d,RT,b"))
869 (match_operand:DI 0 "register_operand" "d, d,d")))]
870 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
871 "@
872 cgfr\t%0,%1
873 cgf\t%0,%1
874 cgfrl\t%0,%1"
875 [(set_attr "op_type" "RRE,RXY,RIL")
876 (set_attr "z10prop" "z10_c,*,*")
877 (set_attr "type" "*,*,larl")])
881 (define_insn "*cmpsi_ccs_sign"
882 [(set (reg CC_REGNUM)
883 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
884 (match_operand:SI 0 "register_operand" "d,d,d")))]
885 "s390_match_ccmode(insn, CCSRmode)"
886 "@
887 ch\t%0,%1
888 chy\t%0,%1
889 chrl\t%0,%1"
890 [(set_attr "op_type" "RX,RXY,RIL")
891 (set_attr "cpu_facility" "*,*,z10")
892 (set_attr "type" "*,*,larl")
893 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
895 (define_insn "*cmphi_ccs_z10"
896 [(set (reg CC_REGNUM)
897 (compare (match_operand:HI 0 "s_operand" "Q")
898 (match_operand:HI 1 "immediate_operand" "K")))]
899 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
900 "chhsi\t%0,%1"
901 [(set_attr "op_type" "SIL")
902 (set_attr "z196prop" "z196_cracked")])
904 (define_insn "*cmpdi_ccs_signhi_rl"
905 [(set (reg CC_REGNUM)
906 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
907 (match_operand:GPR 0 "register_operand" "d,d")))]
908 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
909 "@
910 cgh\t%0,%1
911 cghrl\t%0,%1"
912 [(set_attr "op_type" "RXY,RIL")
913 (set_attr "type" "*,larl")])
915 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
916 (define_insn "*cmp<mode>_ccs"
917 [(set (reg CC_REGNUM)
918 (compare (match_operand:GPR 0 "nonimmediate_operand"
919 "d,d,Q, d,d,d,d")
920 (match_operand:GPR 1 "general_operand"
921 "d,K,K,Os,R,T,b")))]
922 "s390_match_ccmode(insn, CCSmode)"
923 "@
924 c<g>r\t%0,%1
925 c<g>hi\t%0,%h1
926 c<g>hsi\t%0,%h1
927 c<g>fi\t%0,%1
928 c<g>\t%0,%1
929 c<y>\t%0,%1
930 c<g>rl\t%0,%1"
931 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
932 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
933 (set_attr "type" "*,*,*,*,*,*,larl")
934 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
937 ; Compare (unsigned) instructions
939 (define_insn "*cmpsi_ccu_zerohi_rlsi"
940 [(set (reg CC_REGNUM)
941 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
942 "larl_operand" "X")))
943 (match_operand:SI 0 "register_operand" "d")))]
944 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
945 "clhrl\t%0,%1"
946 [(set_attr "op_type" "RIL")
947 (set_attr "type" "larl")
948 (set_attr "z10prop" "z10_super")])
950 ; clhrl, clghrl
951 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
952 [(set (reg CC_REGNUM)
953 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
954 "larl_operand" "X")))
955 (match_operand:GPR 0 "register_operand" "d")))]
956 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
957 "cl<g>hrl\t%0,%1"
958 [(set_attr "op_type" "RIL")
959 (set_attr "type" "larl")
960 (set_attr "z10prop" "z10_super")])
962 (define_insn "*cmpdi_ccu_zero"
963 [(set (reg CC_REGNUM)
964 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
965 "d,RT,b"))
966 (match_operand:DI 0 "register_operand" "d, d,d")))]
967 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
968 "@
969 clgfr\t%0,%1
970 clgf\t%0,%1
971 clgfrl\t%0,%1"
972 [(set_attr "op_type" "RRE,RXY,RIL")
973 (set_attr "cpu_facility" "*,*,z10")
974 (set_attr "type" "*,*,larl")
975 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
977 (define_insn "*cmpdi_ccu"
978 [(set (reg CC_REGNUM)
979 (compare (match_operand:DI 0 "nonimmediate_operand"
980 "d, d,d,Q, d, Q,BQ")
981 (match_operand:DI 1 "general_operand"
982 "d,Op,b,D,RT,BQ,Q")))]
983 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
984 "@
985 clgr\t%0,%1
986 clgfi\t%0,%1
987 clgrl\t%0,%1
988 clghsi\t%0,%x1
989 clg\t%0,%1
990 #
991 #"
992 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
993 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
994 (set_attr "type" "*,*,larl,*,*,*,*")
995 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
997 (define_insn "*cmpsi_ccu"
998 [(set (reg CC_REGNUM)
999 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1000 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1001 "s390_match_ccmode (insn, CCUmode)"
1002 "@
1003 clr\t%0,%1
1004 clfi\t%0,%o1
1005 clrl\t%0,%1
1006 clfhsi\t%0,%x1
1007 cl\t%0,%1
1008 cly\t%0,%1
1009 #
1010 #"
1011 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1012 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1013 (set_attr "type" "*,*,larl,*,*,*,*,*")
1014 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1016 (define_insn "*cmphi_ccu"
1017 [(set (reg CC_REGNUM)
1018 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1019 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1020 "s390_match_ccmode (insn, CCUmode)
1021 && !register_operand (operands[1], HImode)"
1022 "@
1023 clm\t%0,3,%S1
1024 clmy\t%0,3,%S1
1025 clhhsi\t%0,%1
1026 #
1027 #"
1028 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1029 (set_attr "cpu_facility" "*,*,z10,*,*")
1030 (set_attr "z10prop" "*,*,z10_super,*,*")])
1032 (define_insn "*cmpqi_ccu"
1033 [(set (reg CC_REGNUM)
1034 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1035 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1036 "s390_match_ccmode (insn, CCUmode)
1037 && !register_operand (operands[1], QImode)"
1038 "@
1039 clm\t%0,1,%S1
1040 clmy\t%0,1,%S1
1041 cli\t%S0,%b1
1042 cliy\t%S0,%b1
1043 #
1044 #"
1045 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1046 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1049 ; Block compare (CLC) instruction patterns.
1051 (define_insn "*clc"
1052 [(set (reg CC_REGNUM)
1053 (compare (match_operand:BLK 0 "memory_operand" "Q")
1054 (match_operand:BLK 1 "memory_operand" "Q")))
1055 (use (match_operand 2 "const_int_operand" "n"))]
1056 "s390_match_ccmode (insn, CCUmode)
1057 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1058 "clc\t%O0(%2,%R0),%S1"
1059 [(set_attr "op_type" "SS")])
1061 (define_split
1062 [(set (reg CC_REGNUM)
1063 (compare (match_operand 0 "memory_operand" "")
1064 (match_operand 1 "memory_operand" "")))]
1065 "reload_completed
1066 && s390_match_ccmode (insn, CCUmode)
1067 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1068 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1069 [(parallel
1070 [(set (match_dup 0) (match_dup 1))
1071 (use (match_dup 2))])]
1072 {
1073 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1074 operands[0] = adjust_address (operands[0], BLKmode, 0);
1075 operands[1] = adjust_address (operands[1], BLKmode, 0);
1077 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1078 operands[0], operands[1]);
1079 operands[0] = SET_DEST (PATTERN (curr_insn));
1080 })
1083 ; (TF|DF|SF|TD|DD|SD) instructions
1085 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1086 (define_insn "*cmp<mode>_ccs_0"
1087 [(set (reg CC_REGNUM)
1088 (compare (match_operand:FP 0 "register_operand" "f")
1089 (match_operand:FP 1 "const0_operand" "")))]
1090 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1091 "lt<xde><bt>r\t%0,%0"
1092 [(set_attr "op_type" "RRE")
1093 (set_attr "type" "fsimp<mode>")])
1095 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1096 (define_insn "*cmp<mode>_ccs"
1097 [(set (reg CC_REGNUM)
1098 (compare (match_operand:FP 0 "register_operand" "f,f")
1099 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1100 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1101 "@
1102 c<xde><bt>r\t%0,%1
1103 c<xde>b\t%0,%1"
1104 [(set_attr "op_type" "RRE,RXE")
1105 (set_attr "type" "fsimp<mode>")])
1108 ; Compare and Branch instructions
1110 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1111 ; The following instructions do a complementary access of their second
1112 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1113 (define_insn "*cmp_and_br_signed_<mode>"
1114 [(set (pc)
1115 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1116 [(match_operand:GPR 1 "register_operand" "d,d")
1117 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1118 (label_ref (match_operand 3 "" ""))
1119 (pc)))
1120 (clobber (reg:CC CC_REGNUM))]
1121 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1122 {
1123 if (get_attr_length (insn) == 6)
1124 return which_alternative ?
1125 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1126 else
1127 return which_alternative ?
1128 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1129 }
1130 [(set_attr "op_type" "RIE")
1131 (set_attr "type" "branch")
1132 (set_attr "z10prop" "z10_super_c,z10_super")
1133 (set (attr "length")
1134 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1135 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1136 ; 10 byte for cgr/jg
1138 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1139 ; The following instructions do a complementary access of their second
1140 ; operand (z10 only): clrj, clgrj, clr, clgr
1141 (define_insn "*cmp_and_br_unsigned_<mode>"
1142 [(set (pc)
1143 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1144 [(match_operand:GPR 1 "register_operand" "d,d")
1145 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1146 (label_ref (match_operand 3 "" ""))
1147 (pc)))
1148 (clobber (reg:CC CC_REGNUM))]
1149 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1150 {
1151 if (get_attr_length (insn) == 6)
1152 return which_alternative ?
1153 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1154 else
1155 return which_alternative ?
1156 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1157 }
1158 [(set_attr "op_type" "RIE")
1159 (set_attr "type" "branch")
1160 (set_attr "z10prop" "z10_super_c,z10_super")
1161 (set (attr "length")
1162 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1163 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1164 ; 10 byte for clgr/jg
1166 ; And now the same two patterns as above but with a negated CC mask.
1168 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1169 ; The following instructions do a complementary access of their second
1170 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1171 (define_insn "*icmp_and_br_signed_<mode>"
1172 [(set (pc)
1173 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1174 [(match_operand:GPR 1 "register_operand" "d,d")
1175 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1176 (pc)
1177 (label_ref (match_operand 3 "" ""))))
1178 (clobber (reg:CC CC_REGNUM))]
1179 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1180 {
1181 if (get_attr_length (insn) == 6)
1182 return which_alternative ?
1183 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1184 else
1185 return which_alternative ?
1186 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1187 }
1188 [(set_attr "op_type" "RIE")
1189 (set_attr "type" "branch")
1190 (set_attr "z10prop" "z10_super_c,z10_super")
1191 (set (attr "length")
1192 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1193 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1194 ; 10 byte for cgr/jg
1196 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1197 ; The following instructions do a complementary access of their second
1198 ; operand (z10 only): clrj, clgrj, clr, clgr
1199 (define_insn "*icmp_and_br_unsigned_<mode>"
1200 [(set (pc)
1201 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1202 [(match_operand:GPR 1 "register_operand" "d,d")
1203 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1204 (pc)
1205 (label_ref (match_operand 3 "" ""))))
1206 (clobber (reg:CC CC_REGNUM))]
1207 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1208 {
1209 if (get_attr_length (insn) == 6)
1210 return which_alternative ?
1211 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1212 else
1213 return which_alternative ?
1214 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1215 }
1216 [(set_attr "op_type" "RIE")
1217 (set_attr "type" "branch")
1218 (set_attr "z10prop" "z10_super_c,z10_super")
1219 (set (attr "length")
1220 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1221 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1222 ; 10 byte for clgr/jg
1224 ;;
1225 ;;- Move instructions.
1226 ;;
1228 ;
1229 ; movti instruction pattern(s).
1230 ;
1232 (define_insn "movti"
1233 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1234 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1235 "TARGET_ZARCH"
1236 "@
1237 lmg\t%0,%N0,%S1
1238 stmg\t%1,%N1,%S0
1239 #
1240 #"
1241 [(set_attr "op_type" "RSY,RSY,*,*")
1242 (set_attr "type" "lm,stm,*,*")])
1244 (define_split
1245 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1246 (match_operand:TI 1 "general_operand" ""))]
1247 "TARGET_ZARCH && reload_completed
1248 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1249 [(set (match_dup 2) (match_dup 4))
1250 (set (match_dup 3) (match_dup 5))]
1251 {
1252 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1253 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1254 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1255 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1256 })
1258 (define_split
1259 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1260 (match_operand:TI 1 "general_operand" ""))]
1261 "TARGET_ZARCH && reload_completed
1262 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1263 [(set (match_dup 2) (match_dup 4))
1264 (set (match_dup 3) (match_dup 5))]
1265 {
1266 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1267 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1268 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1269 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1270 })
1272 (define_split
1273 [(set (match_operand:TI 0 "register_operand" "")
1274 (match_operand:TI 1 "memory_operand" ""))]
1275 "TARGET_ZARCH && reload_completed
1276 && !s_operand (operands[1], VOIDmode)"
1277 [(set (match_dup 0) (match_dup 1))]
1278 {
1279 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1280 addr = gen_lowpart (Pmode, addr);
1281 s390_load_address (addr, XEXP (operands[1], 0));
1282 operands[1] = replace_equiv_address (operands[1], addr);
1283 })
1286 ;
1287 ; Patterns used for secondary reloads
1288 ;
1290 ; z10 provides move instructions accepting larl memory operands.
1291 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1292 ; These patterns are also used for unaligned SI and DI accesses.
1294 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1295 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1296 (match_operand:INTALL 1 "register_operand" "=d")
1297 (match_operand:P 2 "register_operand" "=&a")])]
1298 "TARGET_Z10"
1299 {
1300 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1301 DONE;
1302 })
1304 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1305 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1306 (match_operand:INTALL 1 "memory_operand" "")
1307 (match_operand:P 2 "register_operand" "=a")])]
1308 "TARGET_Z10"
1309 {
1310 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1311 DONE;
1312 })
1314 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1315 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1316 (match_operand:FPALL 1 "register_operand" "=d")
1317 (match_operand:P 2 "register_operand" "=&a")])]
1318 "TARGET_Z10"
1319 {
1320 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1321 DONE;
1322 })
1324 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1325 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1326 (match_operand:FPALL 1 "memory_operand" "")
1327 (match_operand:P 2 "register_operand" "=a")])]
1328 "TARGET_Z10"
1329 {
1330 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1331 DONE;
1332 })
1334 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1335 [(parallel [(match_operand:P 0 "register_operand" "=d")
1336 (match_operand:P 1 "larl_operand" "")
1337 (match_operand:P 2 "register_operand" "=a")])]
1338 "TARGET_Z10"
1339 {
1340 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1341 DONE;
1342 })
1344 ; Handles loading a PLUS (load address) expression
1346 (define_expand "reload<mode>_plus"
1347 [(parallel [(match_operand:P 0 "register_operand" "=a")
1348 (match_operand:P 1 "s390_plus_operand" "")
1349 (match_operand:P 2 "register_operand" "=&a")])]
1350 ""
1351 {
1352 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1353 DONE;
1354 })
1356 ; Handles assessing a non-offsetable memory address
1358 (define_expand "reload<mode>_nonoffmem_in"
1359 [(parallel [(match_operand 0 "register_operand" "")
1360 (match_operand 1 "" "")
1361 (match_operand:P 2 "register_operand" "=&a")])]
1362 ""
1363 {
1364 gcc_assert (MEM_P (operands[1]));
1365 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1366 operands[1] = replace_equiv_address (operands[1], operands[2]);
1367 emit_move_insn (operands[0], operands[1]);
1368 DONE;
1369 })
1371 (define_expand "reload<mode>_nonoffmem_out"
1372 [(parallel [(match_operand 0 "" "")
1373 (match_operand 1 "register_operand" "")
1374 (match_operand:P 2 "register_operand" "=&a")])]
1375 ""
1376 {
1377 gcc_assert (MEM_P (operands[0]));
1378 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1379 operands[0] = replace_equiv_address (operands[0], operands[2]);
1380 emit_move_insn (operands[0], operands[1]);
1381 DONE;
1382 })
1384 (define_expand "reload<mode>_PIC_addr"
1385 [(parallel [(match_operand 0 "register_operand" "=d")
1386 (match_operand 1 "larl_operand" "")
1387 (match_operand:P 2 "register_operand" "=a")])]
1388 ""
1389 {
1390 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1391 emit_move_insn (operands[0], new_rtx);
1392 })
1394 ;
1395 ; movdi instruction pattern(s).
1396 ;
1398 (define_expand "movdi"
1399 [(set (match_operand:DI 0 "general_operand" "")
1400 (match_operand:DI 1 "general_operand" ""))]
1401 ""
1402 {
1403 /* Handle symbolic constants. */
1404 if (TARGET_64BIT
1405 && (SYMBOLIC_CONST (operands[1])
1406 || (GET_CODE (operands[1]) == PLUS
1407 && XEXP (operands[1], 0) == pic_offset_table_rtx
1408 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1409 emit_symbolic_move (operands);
1410 })
1412 (define_insn "*movdi_larl"
1413 [(set (match_operand:DI 0 "register_operand" "=d")
1414 (match_operand:DI 1 "larl_operand" "X"))]
1415 "TARGET_64BIT
1416 && !FP_REG_P (operands[0])"
1417 "larl\t%0,%1"
1418 [(set_attr "op_type" "RIL")
1419 (set_attr "type" "larl")
1420 (set_attr "z10prop" "z10_super_A1")])
1422 (define_insn "*movdi_64"
1423 [(set (match_operand:DI 0 "nonimmediate_operand"
1424 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1425 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1426 (match_operand:DI 1 "general_operand"
1427 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1428 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1429 "TARGET_ZARCH"
1430 "@
1431 lghi\t%0,%h1
1432 llihh\t%0,%i1
1433 llihl\t%0,%i1
1434 llilh\t%0,%i1
1435 llill\t%0,%i1
1436 lgfi\t%0,%1
1437 llihf\t%0,%k1
1438 llilf\t%0,%k1
1439 ldgr\t%0,%1
1440 lgdr\t%0,%1
1441 lay\t%0,%a1
1442 lgrl\t%0,%1
1443 lgr\t%0,%1
1444 lg\t%0,%1
1445 stg\t%1,%0
1446 ldr\t%0,%1
1447 ld\t%0,%1
1448 ldy\t%0,%1
1449 std\t%1,%0
1450 stdy\t%1,%0
1451 stgrl\t%1,%0
1452 mvghi\t%0,%1
1453 #
1454 #
1455 stam\t%1,%N1,%S0
1456 lam\t%0,%N0,%S1"
1457 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1458 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1459 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1460 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1461 *,*")
1462 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1463 z10,*,*,*,*,*,longdisp,*,longdisp,
1464 z10,z10,*,*,*,*")
1465 (set_attr "z10prop" "z10_fwd_A1,
1466 z10_fwd_E1,
1467 z10_fwd_E1,
1468 z10_fwd_E1,
1469 z10_fwd_E1,
1470 z10_fwd_A1,
1471 z10_fwd_E1,
1472 z10_fwd_E1,
1473 *,
1474 *,
1475 z10_fwd_A1,
1476 z10_fwd_A3,
1477 z10_fr_E1,
1478 z10_fwd_A3,
1479 z10_rec,
1480 *,
1481 *,
1482 *,
1483 *,
1484 *,
1485 z10_rec,
1486 z10_super,
1487 *,
1488 *,
1489 *,
1490 *")
1491 ])
1493 (define_split
1494 [(set (match_operand:DI 0 "register_operand" "")
1495 (match_operand:DI 1 "register_operand" ""))]
1496 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1497 [(set (match_dup 2) (match_dup 3))
1498 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1499 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1500 "operands[2] = gen_lowpart (SImode, operands[0]);
1501 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1503 (define_split
1504 [(set (match_operand:DI 0 "register_operand" "")
1505 (match_operand:DI 1 "register_operand" ""))]
1506 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1507 && dead_or_set_p (insn, operands[1])"
1508 [(set (match_dup 3) (match_dup 2))
1509 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1510 (set (match_dup 4) (match_dup 2))]
1511 "operands[2] = gen_lowpart (SImode, operands[1]);
1512 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1514 (define_split
1515 [(set (match_operand:DI 0 "register_operand" "")
1516 (match_operand:DI 1 "register_operand" ""))]
1517 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1518 && !dead_or_set_p (insn, operands[1])"
1519 [(set (match_dup 3) (match_dup 2))
1520 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1521 (set (match_dup 4) (match_dup 2))
1522 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1523 "operands[2] = gen_lowpart (SImode, operands[1]);
1524 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1526 (define_insn "*movdi_31"
1527 [(set (match_operand:DI 0 "nonimmediate_operand"
1528 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1529 (match_operand:DI 1 "general_operand"
1530 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1531 "!TARGET_ZARCH"
1532 "@
1533 lm\t%0,%N0,%S1
1534 lmy\t%0,%N0,%S1
1535 stm\t%1,%N1,%S0
1536 stmy\t%1,%N1,%S0
1537 #
1538 #
1539 ldr\t%0,%1
1540 ld\t%0,%1
1541 ldy\t%0,%1
1542 std\t%1,%0
1543 stdy\t%1,%0
1544 #"
1545 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1546 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1547 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1549 ; For a load from a symbol ref we can use one of the target registers
1550 ; together with larl to load the address.
1551 (define_split
1552 [(set (match_operand:DI 0 "register_operand" "")
1553 (match_operand:DI 1 "memory_operand" ""))]
1554 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1555 && larl_operand (XEXP (operands[1], 0), SImode)"
1556 [(set (match_dup 2) (match_dup 3))
1557 (set (match_dup 0) (match_dup 1))]
1558 {
1559 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1560 operands[3] = XEXP (operands[1], 0);
1561 operands[1] = replace_equiv_address (operands[1], operands[2]);
1562 })
1564 (define_split
1565 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1566 (match_operand:DI 1 "general_operand" ""))]
1567 "!TARGET_ZARCH && reload_completed
1568 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1569 [(set (match_dup 2) (match_dup 4))
1570 (set (match_dup 3) (match_dup 5))]
1571 {
1572 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1573 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1574 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1575 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1576 })
1578 (define_split
1579 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1580 (match_operand:DI 1 "general_operand" ""))]
1581 "!TARGET_ZARCH && reload_completed
1582 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1583 [(set (match_dup 2) (match_dup 4))
1584 (set (match_dup 3) (match_dup 5))]
1585 {
1586 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1587 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1588 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1589 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1590 })
1592 (define_split
1593 [(set (match_operand:DI 0 "register_operand" "")
1594 (match_operand:DI 1 "memory_operand" ""))]
1595 "!TARGET_ZARCH && reload_completed
1596 && !FP_REG_P (operands[0])
1597 && !s_operand (operands[1], VOIDmode)"
1598 [(set (match_dup 0) (match_dup 1))]
1599 {
1600 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1601 s390_load_address (addr, XEXP (operands[1], 0));
1602 operands[1] = replace_equiv_address (operands[1], addr);
1603 })
1605 (define_peephole2
1606 [(set (match_operand:DI 0 "register_operand" "")
1607 (mem:DI (match_operand 1 "address_operand" "")))]
1608 "TARGET_ZARCH
1609 && !FP_REG_P (operands[0])
1610 && GET_CODE (operands[1]) == SYMBOL_REF
1611 && CONSTANT_POOL_ADDRESS_P (operands[1])
1612 && get_pool_mode (operands[1]) == DImode
1613 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1614 [(set (match_dup 0) (match_dup 2))]
1615 "operands[2] = get_pool_constant (operands[1]);")
1617 (define_insn "*la_64"
1618 [(set (match_operand:DI 0 "register_operand" "=d,d")
1619 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1620 "TARGET_64BIT"
1621 "@
1622 la\t%0,%a1
1623 lay\t%0,%a1"
1624 [(set_attr "op_type" "RX,RXY")
1625 (set_attr "type" "la")
1626 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1628 (define_peephole2
1629 [(parallel
1630 [(set (match_operand:DI 0 "register_operand" "")
1631 (match_operand:QI 1 "address_operand" ""))
1632 (clobber (reg:CC CC_REGNUM))])]
1633 "TARGET_64BIT
1634 && preferred_la_operand_p (operands[1], const0_rtx)"
1635 [(set (match_dup 0) (match_dup 1))]
1636 "")
1638 (define_peephole2
1639 [(set (match_operand:DI 0 "register_operand" "")
1640 (match_operand:DI 1 "register_operand" ""))
1641 (parallel
1642 [(set (match_dup 0)
1643 (plus:DI (match_dup 0)
1644 (match_operand:DI 2 "nonmemory_operand" "")))
1645 (clobber (reg:CC CC_REGNUM))])]
1646 "TARGET_64BIT
1647 && !reg_overlap_mentioned_p (operands[0], operands[2])
1648 && preferred_la_operand_p (operands[1], operands[2])"
1649 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1650 "")
1652 ;
1653 ; movsi instruction pattern(s).
1654 ;
1656 (define_expand "movsi"
1657 [(set (match_operand:SI 0 "general_operand" "")
1658 (match_operand:SI 1 "general_operand" ""))]
1659 ""
1660 {
1661 /* Handle symbolic constants. */
1662 if (!TARGET_64BIT
1663 && (SYMBOLIC_CONST (operands[1])
1664 || (GET_CODE (operands[1]) == PLUS
1665 && XEXP (operands[1], 0) == pic_offset_table_rtx
1666 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1667 emit_symbolic_move (operands);
1668 })
1670 (define_insn "*movsi_larl"
1671 [(set (match_operand:SI 0 "register_operand" "=d")
1672 (match_operand:SI 1 "larl_operand" "X"))]
1673 "!TARGET_64BIT && TARGET_CPU_ZARCH
1674 && !FP_REG_P (operands[0])"
1675 "larl\t%0,%1"
1676 [(set_attr "op_type" "RIL")
1677 (set_attr "type" "larl")
1678 (set_attr "z10prop" "z10_fwd_A1")])
1680 (define_insn "*movsi_zarch"
1681 [(set (match_operand:SI 0 "nonimmediate_operand"
1682 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1683 (match_operand:SI 1 "general_operand"
1684 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1685 "TARGET_ZARCH"
1686 "@
1687 lhi\t%0,%h1
1688 llilh\t%0,%i1
1689 llill\t%0,%i1
1690 iilf\t%0,%o1
1691 lay\t%0,%a1
1692 lrl\t%0,%1
1693 lr\t%0,%1
1694 l\t%0,%1
1695 ly\t%0,%1
1696 st\t%1,%0
1697 sty\t%1,%0
1698 ler\t%0,%1
1699 le\t%0,%1
1700 ley\t%0,%1
1701 ste\t%1,%0
1702 stey\t%1,%0
1703 ear\t%0,%1
1704 sar\t%0,%1
1705 stam\t%1,%1,%S0
1706 strl\t%1,%0
1707 mvhi\t%0,%1
1708 lam\t%0,%0,%S1"
1709 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1710 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1711 (set_attr "type" "*,
1712 *,
1713 *,
1714 *,
1715 la,
1716 larl,
1717 lr,
1718 load,
1719 load,
1720 store,
1721 store,
1722 floadsf,
1723 floadsf,
1724 floadsf,
1725 fstoresf,
1726 fstoresf,
1727 *,
1728 *,
1729 *,
1730 larl,
1731 *,
1732 *")
1733 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1734 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1735 (set_attr "z10prop" "z10_fwd_A1,
1736 z10_fwd_E1,
1737 z10_fwd_E1,
1738 z10_fwd_A1,
1739 z10_fwd_A1,
1740 z10_fwd_A3,
1741 z10_fr_E1,
1742 z10_fwd_A3,
1743 z10_fwd_A3,
1744 z10_rec,
1745 z10_rec,
1746 *,
1747 *,
1748 *,
1749 *,
1750 *,
1751 z10_super_E1,
1752 z10_super,
1753 *,
1754 z10_rec,
1755 z10_super,
1756 *")])
1758 (define_insn "*movsi_esa"
1759 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1760 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1761 "!TARGET_ZARCH"
1762 "@
1763 lhi\t%0,%h1
1764 lr\t%0,%1
1765 l\t%0,%1
1766 st\t%1,%0
1767 ler\t%0,%1
1768 le\t%0,%1
1769 ste\t%1,%0
1770 ear\t%0,%1
1771 sar\t%0,%1
1772 stam\t%1,%1,%S0
1773 lam\t%0,%0,%S1"
1774 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1775 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1776 (set_attr "z10prop" "z10_fwd_A1,
1777 z10_fr_E1,
1778 z10_fwd_A3,
1779 z10_rec,
1780 *,
1781 *,
1782 *,
1783 z10_super_E1,
1784 z10_super,
1785 *,
1786 *")
1787 ])
1789 (define_peephole2
1790 [(set (match_operand:SI 0 "register_operand" "")
1791 (mem:SI (match_operand 1 "address_operand" "")))]
1792 "!FP_REG_P (operands[0])
1793 && GET_CODE (operands[1]) == SYMBOL_REF
1794 && CONSTANT_POOL_ADDRESS_P (operands[1])
1795 && get_pool_mode (operands[1]) == SImode
1796 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1797 [(set (match_dup 0) (match_dup 2))]
1798 "operands[2] = get_pool_constant (operands[1]);")
1800 (define_insn "*la_31"
1801 [(set (match_operand:SI 0 "register_operand" "=d,d")
1802 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1803 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1804 "@
1805 la\t%0,%a1
1806 lay\t%0,%a1"
1807 [(set_attr "op_type" "RX,RXY")
1808 (set_attr "type" "la")
1809 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1811 (define_peephole2
1812 [(parallel
1813 [(set (match_operand:SI 0 "register_operand" "")
1814 (match_operand:QI 1 "address_operand" ""))
1815 (clobber (reg:CC CC_REGNUM))])]
1816 "!TARGET_64BIT
1817 && preferred_la_operand_p (operands[1], const0_rtx)"
1818 [(set (match_dup 0) (match_dup 1))]
1819 "")
1821 (define_peephole2
1822 [(set (match_operand:SI 0 "register_operand" "")
1823 (match_operand:SI 1 "register_operand" ""))
1824 (parallel
1825 [(set (match_dup 0)
1826 (plus:SI (match_dup 0)
1827 (match_operand:SI 2 "nonmemory_operand" "")))
1828 (clobber (reg:CC CC_REGNUM))])]
1829 "!TARGET_64BIT
1830 && !reg_overlap_mentioned_p (operands[0], operands[2])
1831 && preferred_la_operand_p (operands[1], operands[2])"
1832 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1833 "")
1835 (define_insn "*la_31_and"
1836 [(set (match_operand:SI 0 "register_operand" "=d,d")
1837 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1838 (const_int 2147483647)))]
1839 "!TARGET_64BIT"
1840 "@
1841 la\t%0,%a1
1842 lay\t%0,%a1"
1843 [(set_attr "op_type" "RX,RXY")
1844 (set_attr "type" "la")
1845 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1847 (define_insn_and_split "*la_31_and_cc"
1848 [(set (match_operand:SI 0 "register_operand" "=d")
1849 (and:SI (match_operand:QI 1 "address_operand" "p")
1850 (const_int 2147483647)))
1851 (clobber (reg:CC CC_REGNUM))]
1852 "!TARGET_64BIT"
1853 "#"
1854 "&& reload_completed"
1855 [(set (match_dup 0)
1856 (and:SI (match_dup 1) (const_int 2147483647)))]
1857 ""
1858 [(set_attr "op_type" "RX")
1859 (set_attr "type" "la")])
1861 (define_insn "force_la_31"
1862 [(set (match_operand:SI 0 "register_operand" "=d,d")
1863 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1864 (use (const_int 0))]
1865 "!TARGET_64BIT"
1866 "@
1867 la\t%0,%a1
1868 lay\t%0,%a1"
1869 [(set_attr "op_type" "RX")
1870 (set_attr "type" "la")
1871 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1873 ;
1874 ; movhi instruction pattern(s).
1875 ;
1877 (define_expand "movhi"
1878 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1879 (match_operand:HI 1 "general_operand" ""))]
1880 ""
1881 {
1882 /* Make it explicit that loading a register from memory
1883 always sign-extends (at least) to SImode. */
1884 if (optimize && can_create_pseudo_p ()
1885 && register_operand (operands[0], VOIDmode)
1886 && GET_CODE (operands[1]) == MEM)
1887 {
1888 rtx tmp = gen_reg_rtx (SImode);
1889 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1890 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1891 operands[1] = gen_lowpart (HImode, tmp);
1892 }
1893 })
1895 (define_insn "*movhi"
1896 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1897 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1898 ""
1899 "@
1900 lr\t%0,%1
1901 lhi\t%0,%h1
1902 lh\t%0,%1
1903 lhy\t%0,%1
1904 lhrl\t%0,%1
1905 sth\t%1,%0
1906 sthy\t%1,%0
1907 sthrl\t%1,%0
1908 mvhhi\t%0,%1"
1909 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1910 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1911 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1912 (set_attr "z10prop" "z10_fr_E1,
1913 z10_fwd_A1,
1914 z10_super_E1,
1915 z10_super_E1,
1916 z10_super_E1,
1917 z10_rec,
1918 z10_rec,
1919 z10_rec,
1920 z10_super")])
1922 (define_peephole2
1923 [(set (match_operand:HI 0 "register_operand" "")
1924 (mem:HI (match_operand 1 "address_operand" "")))]
1925 "GET_CODE (operands[1]) == SYMBOL_REF
1926 && CONSTANT_POOL_ADDRESS_P (operands[1])
1927 && get_pool_mode (operands[1]) == HImode
1928 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1929 [(set (match_dup 0) (match_dup 2))]
1930 "operands[2] = get_pool_constant (operands[1]);")
1932 ;
1933 ; movqi instruction pattern(s).
1934 ;
1936 (define_expand "movqi"
1937 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1938 (match_operand:QI 1 "general_operand" ""))]
1939 ""
1940 {
1941 /* On z/Architecture, zero-extending from memory to register
1942 is just as fast as a QImode load. */
1943 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1944 && register_operand (operands[0], VOIDmode)
1945 && GET_CODE (operands[1]) == MEM)
1946 {
1947 rtx tmp = gen_reg_rtx (DImode);
1948 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1949 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1950 operands[1] = gen_lowpart (QImode, tmp);
1951 }
1952 })
1954 (define_insn "*movqi"
1955 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1956 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1957 ""
1958 "@
1959 lr\t%0,%1
1960 lhi\t%0,%b1
1961 ic\t%0,%1
1962 icy\t%0,%1
1963 stc\t%1,%0
1964 stcy\t%1,%0
1965 mvi\t%S0,%b1
1966 mviy\t%S0,%b1
1967 #"
1968 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1969 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1970 (set_attr "z10prop" "z10_fr_E1,
1971 z10_fwd_A1,
1972 z10_super_E1,
1973 z10_super_E1,
1974 z10_rec,
1975 z10_rec,
1976 z10_super,
1977 z10_super,
1978 *")])
1980 (define_peephole2
1981 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1982 (mem:QI (match_operand 1 "address_operand" "")))]
1983 "GET_CODE (operands[1]) == SYMBOL_REF
1984 && CONSTANT_POOL_ADDRESS_P (operands[1])
1985 && get_pool_mode (operands[1]) == QImode
1986 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1987 [(set (match_dup 0) (match_dup 2))]
1988 "operands[2] = get_pool_constant (operands[1]);")
1990 ;
1991 ; movstrictqi instruction pattern(s).
1992 ;
1994 (define_insn "*movstrictqi"
1995 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1996 (match_operand:QI 1 "memory_operand" "R,T"))]
1997 ""
1998 "@
1999 ic\t%0,%1
2000 icy\t%0,%1"
2001 [(set_attr "op_type" "RX,RXY")
2002 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2004 ;
2005 ; movstricthi instruction pattern(s).
2006 ;
2008 (define_insn "*movstricthi"
2009 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2010 (match_operand:HI 1 "memory_operand" "Q,S"))
2011 (clobber (reg:CC CC_REGNUM))]
2012 ""
2013 "@
2014 icm\t%0,3,%S1
2015 icmy\t%0,3,%S1"
2016 [(set_attr "op_type" "RS,RSY")
2017 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2019 ;
2020 ; movstrictsi instruction pattern(s).
2021 ;
2023 (define_insn "movstrictsi"
2024 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2025 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2026 "TARGET_ZARCH"
2027 "@
2028 lr\t%0,%1
2029 l\t%0,%1
2030 ly\t%0,%1
2031 ear\t%0,%1"
2032 [(set_attr "op_type" "RR,RX,RXY,RRE")
2033 (set_attr "type" "lr,load,load,*")
2034 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2036 ;
2037 ; mov(tf|td) instruction pattern(s).
2038 ;
2040 (define_expand "mov<mode>"
2041 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2042 (match_operand:TD_TF 1 "general_operand" ""))]
2043 ""
2044 "")
2046 (define_insn "*mov<mode>_64"
2047 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2048 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2049 "TARGET_ZARCH"
2050 "@
2051 lzxr\t%0
2052 lxr\t%0,%1
2053 #
2054 #
2055 lmg\t%0,%N0,%S1
2056 stmg\t%1,%N1,%S0
2057 #
2058 #"
2059 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2060 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2061 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2063 (define_insn "*mov<mode>_31"
2064 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2065 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2066 "!TARGET_ZARCH"
2067 "@
2068 lzxr\t%0
2069 lxr\t%0,%1
2070 #
2071 #"
2072 [(set_attr "op_type" "RRE,RRE,*,*")
2073 (set_attr "type" "fsimptf,fsimptf,*,*")
2074 (set_attr "cpu_facility" "z196,*,*,*")])
2076 ; TFmode in GPRs splitters
2078 (define_split
2079 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2080 (match_operand:TD_TF 1 "general_operand" ""))]
2081 "TARGET_ZARCH && reload_completed
2082 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2083 [(set (match_dup 2) (match_dup 4))
2084 (set (match_dup 3) (match_dup 5))]
2085 {
2086 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2087 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2088 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2089 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2090 })
2092 (define_split
2093 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2094 (match_operand:TD_TF 1 "general_operand" ""))]
2095 "TARGET_ZARCH && reload_completed
2096 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2097 [(set (match_dup 2) (match_dup 4))
2098 (set (match_dup 3) (match_dup 5))]
2099 {
2100 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2101 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2102 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2103 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2104 })
2106 (define_split
2107 [(set (match_operand:TD_TF 0 "register_operand" "")
2108 (match_operand:TD_TF 1 "memory_operand" ""))]
2109 "TARGET_ZARCH && reload_completed
2110 && !FP_REG_P (operands[0])
2111 && !s_operand (operands[1], VOIDmode)"
2112 [(set (match_dup 0) (match_dup 1))]
2113 {
2114 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2115 addr = gen_lowpart (Pmode, addr);
2116 s390_load_address (addr, XEXP (operands[1], 0));
2117 operands[1] = replace_equiv_address (operands[1], addr);
2118 })
2120 ; TFmode in BFPs splitters
2122 (define_split
2123 [(set (match_operand:TD_TF 0 "register_operand" "")
2124 (match_operand:TD_TF 1 "memory_operand" ""))]
2125 "reload_completed && offsettable_memref_p (operands[1])
2126 && FP_REG_P (operands[0])"
2127 [(set (match_dup 2) (match_dup 4))
2128 (set (match_dup 3) (match_dup 5))]
2129 {
2130 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2131 <MODE>mode, 0);
2132 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2133 <MODE>mode, 8);
2134 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2135 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2136 })
2138 (define_split
2139 [(set (match_operand:TD_TF 0 "memory_operand" "")
2140 (match_operand:TD_TF 1 "register_operand" ""))]
2141 "reload_completed && offsettable_memref_p (operands[0])
2142 && FP_REG_P (operands[1])"
2143 [(set (match_dup 2) (match_dup 4))
2144 (set (match_dup 3) (match_dup 5))]
2145 {
2146 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2147 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2148 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2149 <MODE>mode, 0);
2150 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2151 <MODE>mode, 8);
2152 })
2154 ;
2155 ; mov(df|dd) instruction pattern(s).
2156 ;
2158 (define_expand "mov<mode>"
2159 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2160 (match_operand:DD_DF 1 "general_operand" ""))]
2161 ""
2162 "")
2164 (define_insn "*mov<mode>_64dfp"
2165 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2166 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2167 (match_operand:DD_DF 1 "general_operand"
2168 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2169 "TARGET_DFP"
2170 "@
2171 lzdr\t%0
2172 ldr\t%0,%1
2173 ldgr\t%0,%1
2174 lgdr\t%0,%1
2175 ld\t%0,%1
2176 ldy\t%0,%1
2177 std\t%1,%0
2178 stdy\t%1,%0
2179 lghi\t%0,0
2180 lgr\t%0,%1
2181 lg\t%0,%1
2182 stg\t%1,%0"
2183 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2184 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2185 fstoredf,fstoredf,*,lr,load,store")
2186 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2187 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2189 (define_insn "*mov<mode>_64"
2190 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2191 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2192 "TARGET_ZARCH"
2193 "@
2194 lzdr\t%0
2195 ldr\t%0,%1
2196 ld\t%0,%1
2197 ldy\t%0,%1
2198 std\t%1,%0
2199 stdy\t%1,%0
2200 lghi\t%0,0
2201 lgr\t%0,%1
2202 lg\t%0,%1
2203 stg\t%1,%0"
2204 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2205 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2206 fstore<mode>,fstore<mode>,*,lr,load,store")
2207 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2208 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2210 (define_insn "*mov<mode>_31"
2211 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2212 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2213 (match_operand:DD_DF 1 "general_operand"
2214 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2215 "!TARGET_ZARCH"
2216 "@
2217 lzdr\t%0
2218 ldr\t%0,%1
2219 ld\t%0,%1
2220 ldy\t%0,%1
2221 std\t%1,%0
2222 stdy\t%1,%0
2223 lm\t%0,%N0,%S1
2224 lmy\t%0,%N0,%S1
2225 stm\t%1,%N1,%S0
2226 stmy\t%1,%N1,%S0
2227 #
2228 #"
2229 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2230 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2231 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2232 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2234 (define_split
2235 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2236 (match_operand:DD_DF 1 "general_operand" ""))]
2237 "!TARGET_ZARCH && reload_completed
2238 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2239 [(set (match_dup 2) (match_dup 4))
2240 (set (match_dup 3) (match_dup 5))]
2241 {
2242 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2243 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2244 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2245 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2246 })
2248 (define_split
2249 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2250 (match_operand:DD_DF 1 "general_operand" ""))]
2251 "!TARGET_ZARCH && reload_completed
2252 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2253 [(set (match_dup 2) (match_dup 4))
2254 (set (match_dup 3) (match_dup 5))]
2255 {
2256 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2257 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2258 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2259 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2260 })
2262 (define_split
2263 [(set (match_operand:DD_DF 0 "register_operand" "")
2264 (match_operand:DD_DF 1 "memory_operand" ""))]
2265 "!TARGET_ZARCH && reload_completed
2266 && !FP_REG_P (operands[0])
2267 && !s_operand (operands[1], VOIDmode)"
2268 [(set (match_dup 0) (match_dup 1))]
2269 {
2270 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2271 s390_load_address (addr, XEXP (operands[1], 0));
2272 operands[1] = replace_equiv_address (operands[1], addr);
2273 })
2275 ;
2276 ; mov(sf|sd) instruction pattern(s).
2277 ;
2279 (define_insn "mov<mode>"
2280 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2281 "=f,f,f,f,R,T,d,d,d,d,R,T")
2282 (match_operand:SD_SF 1 "general_operand"
2283 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2284 ""
2285 "@
2286 lzer\t%0
2287 ler\t%0,%1
2288 le\t%0,%1
2289 ley\t%0,%1
2290 ste\t%1,%0
2291 stey\t%1,%0
2292 lhi\t%0,0
2293 lr\t%0,%1
2294 l\t%0,%1
2295 ly\t%0,%1
2296 st\t%1,%0
2297 sty\t%1,%0"
2298 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2299 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2300 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2301 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2302 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2304 ;
2305 ; movcc instruction pattern
2306 ;
2308 (define_insn "movcc"
2309 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2310 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2311 ""
2312 "@
2313 lr\t%0,%1
2314 tmh\t%1,12288
2315 ipm\t%0
2316 l\t%0,%1
2317 ly\t%0,%1
2318 st\t%1,%0
2319 sty\t%1,%0"
2320 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2321 (set_attr "type" "lr,*,*,load,load,store,store")
2322 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2323 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2325 ;
2326 ; Block move (MVC) patterns.
2327 ;
2329 (define_insn "*mvc"
2330 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2331 (match_operand:BLK 1 "memory_operand" "Q"))
2332 (use (match_operand 2 "const_int_operand" "n"))]
2333 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2334 "mvc\t%O0(%2,%R0),%S1"
2335 [(set_attr "op_type" "SS")])
2337 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2338 ; order to have it implemented with mvc.
2340 (define_split
2341 [(set (match_operand:QI 0 "memory_operand" "")
2342 (match_operand:QI 1 "memory_operand" ""))]
2343 "reload_completed"
2344 [(parallel
2345 [(set (match_dup 0) (match_dup 1))
2346 (use (const_int 1))])]
2347 {
2348 operands[0] = adjust_address (operands[0], BLKmode, 0);
2349 operands[1] = adjust_address (operands[1], BLKmode, 0);
2350 })
2353 (define_peephole2
2354 [(parallel
2355 [(set (match_operand:BLK 0 "memory_operand" "")
2356 (match_operand:BLK 1 "memory_operand" ""))
2357 (use (match_operand 2 "const_int_operand" ""))])
2358 (parallel
2359 [(set (match_operand:BLK 3 "memory_operand" "")
2360 (match_operand:BLK 4 "memory_operand" ""))
2361 (use (match_operand 5 "const_int_operand" ""))])]
2362 "s390_offset_p (operands[0], operands[3], operands[2])
2363 && s390_offset_p (operands[1], operands[4], operands[2])
2364 && !s390_overlap_p (operands[0], operands[1],
2365 INTVAL (operands[2]) + INTVAL (operands[5]))
2366 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2367 [(parallel
2368 [(set (match_dup 6) (match_dup 7))
2369 (use (match_dup 8))])]
2370 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2371 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2372 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2375 ;
2376 ; load_multiple pattern(s).
2377 ;
2378 ; ??? Due to reload problems with replacing registers inside match_parallel
2379 ; we currently support load_multiple/store_multiple only after reload.
2380 ;
2382 (define_expand "load_multiple"
2383 [(match_par_dup 3 [(set (match_operand 0 "" "")
2384 (match_operand 1 "" ""))
2385 (use (match_operand 2 "" ""))])]
2386 "reload_completed"
2387 {
2388 enum machine_mode mode;
2389 int regno;
2390 int count;
2391 rtx from;
2392 int i, off;
2394 /* Support only loading a constant number of fixed-point registers from
2395 memory and only bother with this if more than two */
2396 if (GET_CODE (operands[2]) != CONST_INT
2397 || INTVAL (operands[2]) < 2
2398 || INTVAL (operands[2]) > 16
2399 || GET_CODE (operands[1]) != MEM
2400 || GET_CODE (operands[0]) != REG
2401 || REGNO (operands[0]) >= 16)
2402 FAIL;
2404 count = INTVAL (operands[2]);
2405 regno = REGNO (operands[0]);
2406 mode = GET_MODE (operands[0]);
2407 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2408 FAIL;
2410 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2411 if (!can_create_pseudo_p ())
2412 {
2413 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2414 {
2415 from = XEXP (operands[1], 0);
2416 off = 0;
2417 }
2418 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2419 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2420 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2421 {
2422 from = XEXP (XEXP (operands[1], 0), 0);
2423 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2424 }
2425 else
2426 FAIL;
2427 }
2428 else
2429 {
2430 from = force_reg (Pmode, XEXP (operands[1], 0));
2431 off = 0;
2432 }
2434 for (i = 0; i < count; i++)
2435 XVECEXP (operands[3], 0, i)
2436 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2437 change_address (operands[1], mode,
2438 plus_constant (Pmode, from,
2439 off + i * GET_MODE_SIZE (mode))));
2440 })
2442 (define_insn "*load_multiple_di"
2443 [(match_parallel 0 "load_multiple_operation"
2444 [(set (match_operand:DI 1 "register_operand" "=r")
2445 (match_operand:DI 2 "s_operand" "QS"))])]
2446 "reload_completed && TARGET_ZARCH"
2447 {
2448 int words = XVECLEN (operands[0], 0);
2449 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2450 return "lmg\t%1,%0,%S2";
2451 }
2452 [(set_attr "op_type" "RSY")
2453 (set_attr "type" "lm")])
2455 (define_insn "*load_multiple_si"
2456 [(match_parallel 0 "load_multiple_operation"
2457 [(set (match_operand:SI 1 "register_operand" "=r,r")
2458 (match_operand:SI 2 "s_operand" "Q,S"))])]
2459 "reload_completed"
2460 {
2461 int words = XVECLEN (operands[0], 0);
2462 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2463 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2464 }
2465 [(set_attr "op_type" "RS,RSY")
2466 (set_attr "type" "lm")])
2468 ;
2469 ; store multiple pattern(s).
2470 ;
2472 (define_expand "store_multiple"
2473 [(match_par_dup 3 [(set (match_operand 0 "" "")
2474 (match_operand 1 "" ""))
2475 (use (match_operand 2 "" ""))])]
2476 "reload_completed"
2477 {
2478 enum machine_mode mode;
2479 int regno;
2480 int count;
2481 rtx to;
2482 int i, off;
2484 /* Support only storing a constant number of fixed-point registers to
2485 memory and only bother with this if more than two. */
2486 if (GET_CODE (operands[2]) != CONST_INT
2487 || INTVAL (operands[2]) < 2
2488 || INTVAL (operands[2]) > 16
2489 || GET_CODE (operands[0]) != MEM
2490 || GET_CODE (operands[1]) != REG
2491 || REGNO (operands[1]) >= 16)
2492 FAIL;
2494 count = INTVAL (operands[2]);
2495 regno = REGNO (operands[1]);
2496 mode = GET_MODE (operands[1]);
2497 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2498 FAIL;
2500 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2502 if (!can_create_pseudo_p ())
2503 {
2504 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2505 {
2506 to = XEXP (operands[0], 0);
2507 off = 0;
2508 }
2509 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2510 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2511 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2512 {
2513 to = XEXP (XEXP (operands[0], 0), 0);
2514 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2515 }
2516 else
2517 FAIL;
2518 }
2519 else
2520 {
2521 to = force_reg (Pmode, XEXP (operands[0], 0));
2522 off = 0;
2523 }
2525 for (i = 0; i < count; i++)
2526 XVECEXP (operands[3], 0, i)
2527 = gen_rtx_SET (VOIDmode,
2528 change_address (operands[0], mode,
2529 plus_constant (Pmode, to,
2530 off + i * GET_MODE_SIZE (mode))),
2531 gen_rtx_REG (mode, regno + i));
2532 })
2534 (define_insn "*store_multiple_di"
2535 [(match_parallel 0 "store_multiple_operation"
2536 [(set (match_operand:DI 1 "s_operand" "=QS")
2537 (match_operand:DI 2 "register_operand" "r"))])]
2538 "reload_completed && TARGET_ZARCH"
2539 {
2540 int words = XVECLEN (operands[0], 0);
2541 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2542 return "stmg\t%2,%0,%S1";
2543 }
2544 [(set_attr "op_type" "RSY")
2545 (set_attr "type" "stm")])
2548 (define_insn "*store_multiple_si"
2549 [(match_parallel 0 "store_multiple_operation"
2550 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2551 (match_operand:SI 2 "register_operand" "r,r"))])]
2552 "reload_completed"
2553 {
2554 int words = XVECLEN (operands[0], 0);
2555 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2556 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2557 }
2558 [(set_attr "op_type" "RS,RSY")
2559 (set_attr "type" "stm")])
2561 ;;
2562 ;; String instructions.
2563 ;;
2565 (define_insn "*execute_rl"
2566 [(match_parallel 0 "execute_operation"
2567 [(unspec [(match_operand 1 "register_operand" "a")
2568 (match_operand 2 "" "")
2569 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2570 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2571 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2572 "exrl\t%1,%3"
2573 [(set_attr "op_type" "RIL")
2574 (set_attr "type" "cs")])
2576 (define_insn "*execute"
2577 [(match_parallel 0 "execute_operation"
2578 [(unspec [(match_operand 1 "register_operand" "a")
2579 (match_operand:BLK 2 "memory_operand" "R")
2580 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2581 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2582 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2583 "ex\t%1,%2"
2584 [(set_attr "op_type" "RX")
2585 (set_attr "type" "cs")])
2588 ;
2589 ; strlenM instruction pattern(s).
2590 ;
2592 (define_expand "strlen<mode>"
2593 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2594 (parallel
2595 [(set (match_dup 4)
2596 (unspec:P [(const_int 0)
2597 (match_operand:BLK 1 "memory_operand" "")
2598 (reg:SI 0)
2599 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2600 (clobber (scratch:P))
2601 (clobber (reg:CC CC_REGNUM))])
2602 (parallel
2603 [(set (match_operand:P 0 "register_operand" "")
2604 (minus:P (match_dup 4) (match_dup 5)))
2605 (clobber (reg:CC CC_REGNUM))])]
2606 ""
2607 {
2608 operands[4] = gen_reg_rtx (Pmode);
2609 operands[5] = gen_reg_rtx (Pmode);
2610 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2611 operands[1] = replace_equiv_address (operands[1], operands[5]);
2612 })
2614 (define_insn "*strlen<mode>"
2615 [(set (match_operand:P 0 "register_operand" "=a")
2616 (unspec:P [(match_operand:P 2 "general_operand" "0")
2617 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2618 (reg:SI 0)
2619 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2620 (clobber (match_scratch:P 1 "=a"))
2621 (clobber (reg:CC CC_REGNUM))]
2622 ""
2623 "srst\t%0,%1\;jo\t.-4"
2624 [(set_attr "length" "8")
2625 (set_attr "type" "vs")])
2627 ;
2628 ; cmpstrM instruction pattern(s).
2629 ;
2631 (define_expand "cmpstrsi"
2632 [(set (reg:SI 0) (const_int 0))
2633 (parallel
2634 [(clobber (match_operand 3 "" ""))
2635 (clobber (match_dup 4))
2636 (set (reg:CCU CC_REGNUM)
2637 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2638 (match_operand:BLK 2 "memory_operand" "")))
2639 (use (reg:SI 0))])
2640 (parallel
2641 [(set (match_operand:SI 0 "register_operand" "=d")
2642 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2643 (clobber (reg:CC CC_REGNUM))])]
2644 ""
2645 {
2646 /* As the result of CMPINT is inverted compared to what we need,
2647 we have to swap the operands. */
2648 rtx op1 = operands[2];
2649 rtx op2 = operands[1];
2650 rtx addr1 = gen_reg_rtx (Pmode);
2651 rtx addr2 = gen_reg_rtx (Pmode);
2653 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2654 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2655 operands[1] = replace_equiv_address_nv (op1, addr1);
2656 operands[2] = replace_equiv_address_nv (op2, addr2);
2657 operands[3] = addr1;
2658 operands[4] = addr2;
2659 })
2661 (define_insn "*cmpstr<mode>"
2662 [(clobber (match_operand:P 0 "register_operand" "=d"))
2663 (clobber (match_operand:P 1 "register_operand" "=d"))
2664 (set (reg:CCU CC_REGNUM)
2665 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2666 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2667 (use (reg:SI 0))]
2668 ""
2669 "clst\t%0,%1\;jo\t.-4"
2670 [(set_attr "length" "8")
2671 (set_attr "type" "vs")])
2673 ;
2674 ; movstr instruction pattern.
2675 ;
2677 (define_expand "movstr"
2678 [(set (reg:SI 0) (const_int 0))
2679 (parallel
2680 [(clobber (match_dup 3))
2681 (set (match_operand:BLK 1 "memory_operand" "")
2682 (match_operand:BLK 2 "memory_operand" ""))
2683 (set (match_operand 0 "register_operand" "")
2684 (unspec [(match_dup 1)
2685 (match_dup 2)
2686 (reg:SI 0)] UNSPEC_MVST))
2687 (clobber (reg:CC CC_REGNUM))])]
2688 ""
2689 {
2690 rtx addr1 = gen_reg_rtx (Pmode);
2691 rtx addr2 = gen_reg_rtx (Pmode);
2693 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2694 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2695 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2696 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2697 operands[3] = addr2;
2698 })
2700 (define_insn "*movstr"
2701 [(clobber (match_operand:P 2 "register_operand" "=d"))
2702 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2703 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2704 (set (match_operand:P 0 "register_operand" "=d")
2705 (unspec [(mem:BLK (match_dup 1))
2706 (mem:BLK (match_dup 3))
2707 (reg:SI 0)] UNSPEC_MVST))
2708 (clobber (reg:CC CC_REGNUM))]
2709 ""
2710 "mvst\t%1,%2\;jo\t.-4"
2711 [(set_attr "length" "8")
2712 (set_attr "type" "vs")])
2715 ;
2716 ; movmemM instruction pattern(s).
2717 ;
2719 (define_expand "movmem<mode>"
2720 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2721 (match_operand:BLK 1 "memory_operand" "")) ; source
2722 (use (match_operand:GPR 2 "general_operand" "")) ; count
2723 (match_operand 3 "" "")]
2724 ""
2725 {
2726 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2727 DONE;
2728 else
2729 FAIL;
2730 })
2732 ; Move a block that is up to 256 bytes in length.
2733 ; The block length is taken as (operands[2] % 256) + 1.
2735 (define_expand "movmem_short"
2736 [(parallel
2737 [(set (match_operand:BLK 0 "memory_operand" "")
2738 (match_operand:BLK 1 "memory_operand" ""))
2739 (use (match_operand 2 "nonmemory_operand" ""))
2740 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2741 (clobber (match_dup 3))])]
2742 ""
2743 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2745 (define_insn "*movmem_short"
2746 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2747 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2748 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2749 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2750 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2751 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2752 "#"
2753 [(set_attr "type" "cs")
2754 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2756 (define_split
2757 [(set (match_operand:BLK 0 "memory_operand" "")
2758 (match_operand:BLK 1 "memory_operand" ""))
2759 (use (match_operand 2 "const_int_operand" ""))
2760 (use (match_operand 3 "immediate_operand" ""))
2761 (clobber (scratch))]
2762 "reload_completed"
2763 [(parallel
2764 [(set (match_dup 0) (match_dup 1))
2765 (use (match_dup 2))])]
2766 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2768 (define_split
2769 [(set (match_operand:BLK 0 "memory_operand" "")
2770 (match_operand:BLK 1 "memory_operand" ""))
2771 (use (match_operand 2 "register_operand" ""))
2772 (use (match_operand 3 "memory_operand" ""))
2773 (clobber (scratch))]
2774 "reload_completed"
2775 [(parallel
2776 [(unspec [(match_dup 2) (match_dup 3)
2777 (const_int 0)] UNSPEC_EXECUTE)
2778 (set (match_dup 0) (match_dup 1))
2779 (use (const_int 1))])]
2780 "")
2782 (define_split
2783 [(set (match_operand:BLK 0 "memory_operand" "")
2784 (match_operand:BLK 1 "memory_operand" ""))
2785 (use (match_operand 2 "register_operand" ""))
2786 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2787 (clobber (scratch))]
2788 "TARGET_Z10 && reload_completed"
2789 [(parallel
2790 [(unspec [(match_dup 2) (const_int 0)
2791 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2792 (set (match_dup 0) (match_dup 1))
2793 (use (const_int 1))])]
2794 "operands[3] = gen_label_rtx ();")
2796 (define_split
2797 [(set (match_operand:BLK 0 "memory_operand" "")
2798 (match_operand:BLK 1 "memory_operand" ""))
2799 (use (match_operand 2 "register_operand" ""))
2800 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2801 (clobber (match_operand 3 "register_operand" ""))]
2802 "reload_completed && TARGET_CPU_ZARCH"
2803 [(set (match_dup 3) (label_ref (match_dup 4)))
2804 (parallel
2805 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2806 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2807 (set (match_dup 0) (match_dup 1))
2808 (use (const_int 1))])]
2809 "operands[4] = gen_label_rtx ();")
2811 ; Move a block of arbitrary length.
2813 (define_expand "movmem_long"
2814 [(parallel
2815 [(clobber (match_dup 2))
2816 (clobber (match_dup 3))
2817 (set (match_operand:BLK 0 "memory_operand" "")
2818 (match_operand:BLK 1 "memory_operand" ""))
2819 (use (match_operand 2 "general_operand" ""))
2820 (use (match_dup 3))
2821 (clobber (reg:CC CC_REGNUM))])]
2822 ""
2823 {
2824 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2825 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2826 rtx reg0 = gen_reg_rtx (dreg_mode);
2827 rtx reg1 = gen_reg_rtx (dreg_mode);
2828 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2829 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2830 rtx len0 = gen_lowpart (Pmode, reg0);
2831 rtx len1 = gen_lowpart (Pmode, reg1);
2833 emit_clobber (reg0);
2834 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2835 emit_move_insn (len0, operands[2]);
2837 emit_clobber (reg1);
2838 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2839 emit_move_insn (len1, operands[2]);
2841 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2842 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2843 operands[2] = reg0;
2844 operands[3] = reg1;
2845 })
2847 (define_insn "*movmem_long"
2848 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2849 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2850 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2851 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2852 (use (match_dup 2))
2853 (use (match_dup 3))
2854 (clobber (reg:CC CC_REGNUM))]
2855 "TARGET_64BIT || !TARGET_ZARCH"
2856 "mvcle\t%0,%1,0\;jo\t.-4"
2857 [(set_attr "length" "8")
2858 (set_attr "type" "vs")])
2860 (define_insn "*movmem_long_31z"
2861 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2862 (clobber (match_operand:TI 1 "register_operand" "=d"))
2863 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2864 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2865 (use (match_dup 2))
2866 (use (match_dup 3))
2867 (clobber (reg:CC CC_REGNUM))]
2868 "!TARGET_64BIT && TARGET_ZARCH"
2869 "mvcle\t%0,%1,0\;jo\t.-4"
2870 [(set_attr "length" "8")
2871 (set_attr "type" "vs")])
2874 ;
2875 ; Test data class.
2876 ;
2878 (define_expand "signbit<mode>2"
2879 [(set (reg:CCZ CC_REGNUM)
2880 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2881 (match_dup 2)]
2882 UNSPEC_TDC_INSN))
2883 (set (match_operand:SI 0 "register_operand" "=d")
2884 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2885 "TARGET_HARD_FLOAT"
2886 {
2887 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2888 })
2890 (define_expand "isinf<mode>2"
2891 [(set (reg:CCZ CC_REGNUM)
2892 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2893 (match_dup 2)]
2894 UNSPEC_TDC_INSN))
2895 (set (match_operand:SI 0 "register_operand" "=d")
2896 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2897 "TARGET_HARD_FLOAT"
2898 {
2899 operands[2] = GEN_INT (S390_TDC_INFINITY);
2900 })
2902 (define_insn_and_split "*cc_to_int"
2903 [(set (match_operand:SI 0 "register_operand" "=d")
2904 (unspec:SI [(match_operand 1 "register_operand" "0")]
2905 UNSPEC_CC_TO_INT))]
2906 "operands != NULL"
2907 "#"
2908 "reload_completed"
2909 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2911 ; This insn is used to generate all variants of the Test Data Class
2912 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2913 ; is the register to be tested and the second one is the bit mask
2914 ; specifying the required test(s).
2915 ;
2916 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2917 (define_insn "*TDC_insn_<mode>"
2918 [(set (reg:CCZ CC_REGNUM)
2919 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2920 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2921 "TARGET_HARD_FLOAT"
2922 "t<_d>c<xde><bt>\t%0,%1"
2923 [(set_attr "op_type" "RXE")
2924 (set_attr "type" "fsimp<mode>")])
2928 ;
2929 ; setmemM instruction pattern(s).
2930 ;
2932 (define_expand "setmem<mode>"
2933 [(set (match_operand:BLK 0 "memory_operand" "")
2934 (match_operand:QI 2 "general_operand" ""))
2935 (use (match_operand:GPR 1 "general_operand" ""))
2936 (match_operand 3 "" "")]
2937 ""
2938 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2940 ; Clear a block that is up to 256 bytes in length.
2941 ; The block length is taken as (operands[1] % 256) + 1.
2943 (define_expand "clrmem_short"
2944 [(parallel
2945 [(set (match_operand:BLK 0 "memory_operand" "")
2946 (const_int 0))
2947 (use (match_operand 1 "nonmemory_operand" ""))
2948 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2949 (clobber (match_dup 2))
2950 (clobber (reg:CC CC_REGNUM))])]
2951 ""
2952 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2954 (define_insn "*clrmem_short"
2955 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2956 (const_int 0))
2957 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2958 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2959 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2960 (clobber (reg:CC CC_REGNUM))]
2961 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2962 "#"
2963 [(set_attr "type" "cs")
2964 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2966 (define_split
2967 [(set (match_operand:BLK 0 "memory_operand" "")
2968 (const_int 0))
2969 (use (match_operand 1 "const_int_operand" ""))
2970 (use (match_operand 2 "immediate_operand" ""))
2971 (clobber (scratch))
2972 (clobber (reg:CC CC_REGNUM))]
2973 "reload_completed"
2974 [(parallel
2975 [(set (match_dup 0) (const_int 0))
2976 (use (match_dup 1))
2977 (clobber (reg:CC CC_REGNUM))])]
2978 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2980 (define_split
2981 [(set (match_operand:BLK 0 "memory_operand" "")
2982 (const_int 0))
2983 (use (match_operand 1 "register_operand" ""))
2984 (use (match_operand 2 "memory_operand" ""))
2985 (clobber (scratch))
2986 (clobber (reg:CC CC_REGNUM))]
2987 "reload_completed"
2988 [(parallel
2989 [(unspec [(match_dup 1) (match_dup 2)
2990 (const_int 0)] UNSPEC_EXECUTE)
2991 (set (match_dup 0) (const_int 0))
2992 (use (const_int 1))
2993 (clobber (reg:CC CC_REGNUM))])]
2994 "")
2996 (define_split
2997 [(set (match_operand:BLK 0 "memory_operand" "")
2998 (const_int 0))
2999 (use (match_operand 1 "register_operand" ""))
3000 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3001 (clobber (scratch))
3002 (clobber (reg:CC CC_REGNUM))]
3003 "TARGET_Z10 && reload_completed"
3004 [(parallel
3005 [(unspec [(match_dup 1) (const_int 0)
3006 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3007 (set (match_dup 0) (const_int 0))
3008 (use (const_int 1))
3009 (clobber (reg:CC CC_REGNUM))])]
3010 "operands[3] = gen_label_rtx ();")
3012 (define_split
3013 [(set (match_operand:BLK 0 "memory_operand" "")
3014 (const_int 0))
3015 (use (match_operand 1 "register_operand" ""))
3016 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3017 (clobber (match_operand 2 "register_operand" ""))
3018 (clobber (reg:CC CC_REGNUM))]
3019 "reload_completed && TARGET_CPU_ZARCH"
3020 [(set (match_dup 2) (label_ref (match_dup 3)))
3021 (parallel
3022 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3023 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3024 (set (match_dup 0) (const_int 0))
3025 (use (const_int 1))
3026 (clobber (reg:CC CC_REGNUM))])]
3027 "operands[3] = gen_label_rtx ();")
3029 ; Initialize a block of arbitrary length with (operands[2] % 256).
3031 (define_expand "setmem_long"
3032 [(parallel
3033 [(clobber (match_dup 1))
3034 (set (match_operand:BLK 0 "memory_operand" "")
3035 (match_operand 2 "shift_count_or_setmem_operand" ""))
3036 (use (match_operand 1 "general_operand" ""))
3037 (use (match_dup 3))
3038 (clobber (reg:CC CC_REGNUM))])]
3039 ""
3040 {
3041 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3042 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3043 rtx reg0 = gen_reg_rtx (dreg_mode);
3044 rtx reg1 = gen_reg_rtx (dreg_mode);
3045 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3046 rtx len0 = gen_lowpart (Pmode, reg0);
3048 emit_clobber (reg0);
3049 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3050 emit_move_insn (len0, operands[1]);
3052 emit_move_insn (reg1, const0_rtx);
3054 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3055 operands[1] = reg0;
3056 operands[3] = reg1;
3057 })
3059 (define_insn "*setmem_long"
3060 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3061 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3062 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3063 (use (match_dup 3))
3064 (use (match_operand:<DBL> 1 "register_operand" "d"))
3065 (clobber (reg:CC CC_REGNUM))]
3066 "TARGET_64BIT || !TARGET_ZARCH"
3067 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3068 [(set_attr "length" "8")
3069 (set_attr "type" "vs")])
3071 (define_insn "*setmem_long_and"
3072 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3073 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3074 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3075 (match_operand 4 "const_int_operand" "n")))
3076 (use (match_dup 3))
3077 (use (match_operand:<DBL> 1 "register_operand" "d"))
3078 (clobber (reg:CC CC_REGNUM))]
3079 "(TARGET_64BIT || !TARGET_ZARCH) &&
3080 (INTVAL (operands[4]) & 255) == 255"
3081 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3082 [(set_attr "length" "8")
3083 (set_attr "type" "vs")])
3085 (define_insn "*setmem_long_31z"
3086 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3087 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3088 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3089 (use (match_dup 3))
3090 (use (match_operand:TI 1 "register_operand" "d"))
3091 (clobber (reg:CC CC_REGNUM))]
3092 "!TARGET_64BIT && TARGET_ZARCH"
3093 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3094 [(set_attr "length" "8")
3095 (set_attr "type" "vs")])
3097 ;
3098 ; cmpmemM instruction pattern(s).
3099 ;
3101 (define_expand "cmpmemsi"
3102 [(set (match_operand:SI 0 "register_operand" "")
3103 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3104 (match_operand:BLK 2 "memory_operand" "") ) )
3105 (use (match_operand:SI 3 "general_operand" ""))
3106 (use (match_operand:SI 4 "" ""))]
3107 ""
3108 {
3109 if (s390_expand_cmpmem (operands[0], operands[1],
3110 operands[2], operands[3]))
3111 DONE;
3112 else
3113 FAIL;
3114 })
3116 ; Compare a block that is up to 256 bytes in length.
3117 ; The block length is taken as (operands[2] % 256) + 1.
3119 (define_expand "cmpmem_short"
3120 [(parallel
3121 [(set (reg:CCU CC_REGNUM)
3122 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3123 (match_operand:BLK 1 "memory_operand" "")))
3124 (use (match_operand 2 "nonmemory_operand" ""))
3125 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3126 (clobber (match_dup 3))])]
3127 ""
3128 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3130 (define_insn "*cmpmem_short"
3131 [(set (reg:CCU CC_REGNUM)
3132 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3133 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3134 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3135 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3136 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3137 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3138 "#"
3139 [(set_attr "type" "cs")
3140 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3142 (define_split
3143 [(set (reg:CCU CC_REGNUM)
3144 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3145 (match_operand:BLK 1 "memory_operand" "")))
3146 (use (match_operand 2 "const_int_operand" ""))
3147 (use (match_operand 3 "immediate_operand" ""))
3148 (clobber (scratch))]
3149 "reload_completed"
3150 [(parallel
3151 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3152 (use (match_dup 2))])]
3153 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3155 (define_split
3156 [(set (reg:CCU CC_REGNUM)
3157 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3158 (match_operand:BLK 1 "memory_operand" "")))
3159 (use (match_operand 2 "register_operand" ""))
3160 (use (match_operand 3 "memory_operand" ""))
3161 (clobber (scratch))]
3162 "reload_completed"
3163 [(parallel
3164 [(unspec [(match_dup 2) (match_dup 3)
3165 (const_int 0)] UNSPEC_EXECUTE)
3166 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3167 (use (const_int 1))])]
3168 "")
3170 (define_split
3171 [(set (reg:CCU CC_REGNUM)
3172 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3173 (match_operand:BLK 1 "memory_operand" "")))
3174 (use (match_operand 2 "register_operand" ""))
3175 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3176 (clobber (scratch))]
3177 "TARGET_Z10 && reload_completed"
3178 [(parallel
3179 [(unspec [(match_dup 2) (const_int 0)
3180 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3181 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3182 (use (const_int 1))])]
3183 "operands[4] = gen_label_rtx ();")
3185 (define_split
3186 [(set (reg:CCU CC_REGNUM)
3187 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3188 (match_operand:BLK 1 "memory_operand" "")))
3189 (use (match_operand 2 "register_operand" ""))
3190 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3191 (clobber (match_operand 3 "register_operand" ""))]
3192 "reload_completed && TARGET_CPU_ZARCH"
3193 [(set (match_dup 3) (label_ref (match_dup 4)))
3194 (parallel
3195 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3196 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3197 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3198 (use (const_int 1))])]
3199 "operands[4] = gen_label_rtx ();")
3201 ; Compare a block of arbitrary length.
3203 (define_expand "cmpmem_long"
3204 [(parallel
3205 [(clobber (match_dup 2))
3206 (clobber (match_dup 3))
3207 (set (reg:CCU CC_REGNUM)
3208 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3209 (match_operand:BLK 1 "memory_operand" "")))
3210 (use (match_operand 2 "general_operand" ""))
3211 (use (match_dup 3))])]
3212 ""
3213 {
3214 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3215 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3216 rtx reg0 = gen_reg_rtx (dreg_mode);
3217 rtx reg1 = gen_reg_rtx (dreg_mode);
3218 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3219 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3220 rtx len0 = gen_lowpart (Pmode, reg0);
3221 rtx len1 = gen_lowpart (Pmode, reg1);
3223 emit_clobber (reg0);
3224 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3225 emit_move_insn (len0, operands[2]);
3227 emit_clobber (reg1);
3228 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3229 emit_move_insn (len1, operands[2]);
3231 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3232 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3233 operands[2] = reg0;
3234 operands[3] = reg1;
3235 })
3237 (define_insn "*cmpmem_long"
3238 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3239 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3240 (set (reg:CCU CC_REGNUM)
3241 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3242 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3243 (use (match_dup 2))
3244 (use (match_dup 3))]
3245 "TARGET_64BIT || !TARGET_ZARCH"
3246 "clcle\t%0,%1,0\;jo\t.-4"
3247 [(set_attr "length" "8")
3248 (set_attr "type" "vs")])
3250 (define_insn "*cmpmem_long_31z"
3251 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3252 (clobber (match_operand:TI 1 "register_operand" "=d"))
3253 (set (reg:CCU CC_REGNUM)
3254 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3255 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3256 (use (match_dup 2))
3257 (use (match_dup 3))]
3258 "!TARGET_64BIT && TARGET_ZARCH"
3259 "clcle\t%0,%1,0\;jo\t.-4"
3260 [(set_attr "op_type" "NN")
3261 (set_attr "type" "vs")
3262 (set_attr "length" "8")])
3264 ; Convert CCUmode condition code to integer.
3265 ; Result is zero if EQ, positive if LTU, negative if GTU.
3267 (define_insn_and_split "cmpint"
3268 [(set (match_operand:SI 0 "register_operand" "=d")
3269 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3270 UNSPEC_STRCMPCC_TO_INT))
3271 (clobber (reg:CC CC_REGNUM))]
3272 ""
3273 "#"
3274 "reload_completed"
3275 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3276 (parallel
3277 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3278 (clobber (reg:CC CC_REGNUM))])])
3280 (define_insn_and_split "*cmpint_cc"
3281 [(set (reg CC_REGNUM)
3282 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3283 UNSPEC_STRCMPCC_TO_INT)
3284 (const_int 0)))
3285 (set (match_operand:SI 0 "register_operand" "=d")
3286 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3287 "s390_match_ccmode (insn, CCSmode)"
3288 "#"
3289 "&& reload_completed"
3290 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3291 (parallel
3292 [(set (match_dup 2) (match_dup 3))
3293 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3294 {
3295 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3296 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3297 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3298 })
3300 (define_insn_and_split "*cmpint_sign"
3301 [(set (match_operand:DI 0 "register_operand" "=d")
3302 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3303 UNSPEC_STRCMPCC_TO_INT)))
3304 (clobber (reg:CC CC_REGNUM))]
3305 "TARGET_ZARCH"
3306 "#"
3307 "&& reload_completed"
3308 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3309 (parallel
3310 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3311 (clobber (reg:CC CC_REGNUM))])])
3313 (define_insn_and_split "*cmpint_sign_cc"
3314 [(set (reg CC_REGNUM)
3315 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3316 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3317 UNSPEC_STRCMPCC_TO_INT) 0)
3318 (const_int 32)) (const_int 32))
3319 (const_int 0)))
3320 (set (match_operand:DI 0 "register_operand" "=d")
3321 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3322 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3323 "#"
3324 "&& reload_completed"
3325 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3326 (parallel
3327 [(set (match_dup 2) (match_dup 3))
3328 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3329 {
3330 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3331 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3332 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3333 })
3336 ;;
3337 ;;- Conversion instructions.
3338 ;;
3340 (define_insn "*sethighpartsi"
3341 [(set (match_operand:SI 0 "register_operand" "=d,d")
3342 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3343 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3344 (clobber (reg:CC CC_REGNUM))]
3345 ""
3346 "@
3347 icm\t%0,%2,%S1
3348 icmy\t%0,%2,%S1"
3349 [(set_attr "op_type" "RS,RSY")
3350 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3352 (define_insn "*sethighpartdi_64"
3353 [(set (match_operand:DI 0 "register_operand" "=d")
3354 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3355 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3356 (clobber (reg:CC CC_REGNUM))]
3357 "TARGET_ZARCH"
3358 "icmh\t%0,%2,%S1"
3359 [(set_attr "op_type" "RSY")
3360 (set_attr "z10prop" "z10_super")])
3362 (define_insn "*sethighpartdi_31"
3363 [(set (match_operand:DI 0 "register_operand" "=d,d")
3364 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3365 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3366 (clobber (reg:CC CC_REGNUM))]
3367 "!TARGET_ZARCH"
3368 "@
3369 icm\t%0,%2,%S1
3370 icmy\t%0,%2,%S1"
3371 [(set_attr "op_type" "RS,RSY")
3372 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3374 ;
3375 ; extv instruction patterns
3376 ;
3378 ; FIXME: This expander needs to be converted from DI to GPR as well
3379 ; after resolving some issues with it.
3381 (define_expand "extzv"
3382 [(parallel
3383 [(set (match_operand:DI 0 "register_operand" "=d")
3384 (zero_extract:DI
3385 (match_operand:DI 1 "register_operand" "d")
3386 (match_operand 2 "const_int_operand" "") ; size
3387 (match_operand 3 "const_int_operand" ""))) ; start
3388 (clobber (reg:CC CC_REGNUM))])]
3389 "TARGET_Z10"
3390 {
3391 /* Starting with zEC12 there is risbgn not clobbering CC. */
3392 if (TARGET_ZEC12)
3393 {
3394 emit_move_insn (operands[0],
3395 gen_rtx_ZERO_EXTRACT (DImode,
3396 operands[1],
3397 operands[2],
3398 operands[3]));
3399 DONE;
3400 }
3401 })
3403 (define_insn "*extzv<mode>_zEC12"
3404 [(set (match_operand:GPR 0 "register_operand" "=d")
3405 (zero_extract:GPR
3406 (match_operand:GPR 1 "register_operand" "d")
3407 (match_operand 2 "const_int_operand" "") ; size
3408 (match_operand 3 "const_int_operand" "")))] ; start]
3409 "TARGET_ZEC12"
3410 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3411 [(set_attr "op_type" "RIE")])
3413 (define_insn "*extzv<mode>_z10"
3414 [(set (match_operand:GPR 0 "register_operand" "=d")
3415 (zero_extract:GPR
3416 (match_operand:GPR 1 "register_operand" "d")
3417 (match_operand 2 "const_int_operand" "") ; size
3418 (match_operand 3 "const_int_operand" ""))) ; start
3419 (clobber (reg:CC CC_REGNUM))]
3420 "TARGET_Z10"
3421 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3422 [(set_attr "op_type" "RIE")
3423 (set_attr "z10prop" "z10_super_E1")])
3425 (define_insn_and_split "*pre_z10_extzv<mode>"
3426 [(set (match_operand:GPR 0 "register_operand" "=d")
3427 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3428 (match_operand 2 "nonzero_shift_count_operand" "")
3429 (const_int 0)))
3430 (clobber (reg:CC CC_REGNUM))]
3431 "!TARGET_Z10"
3432 "#"
3433 "&& reload_completed"
3434 [(parallel
3435 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3436 (clobber (reg:CC CC_REGNUM))])
3437 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3438 {
3439 int bitsize = INTVAL (operands[2]);
3440 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3441 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3443 operands[1] = adjust_address (operands[1], BLKmode, 0);
3444 set_mem_size (operands[1], size);
3445 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3446 operands[3] = GEN_INT (mask);
3447 })
3449 (define_insn_and_split "*pre_z10_extv<mode>"
3450 [(set (match_operand:GPR 0 "register_operand" "=d")
3451 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3452 (match_operand 2 "nonzero_shift_count_operand" "")
3453 (const_int 0)))
3454 (clobber (reg:CC CC_REGNUM))]
3455 ""
3456 "#"
3457 "&& reload_completed"
3458 [(parallel
3459 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3460 (clobber (reg:CC CC_REGNUM))])
3461 (parallel
3462 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3463 (clobber (reg:CC CC_REGNUM))])]
3464 {
3465 int bitsize = INTVAL (operands[2]);
3466 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3467 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3469 operands[1] = adjust_address (operands[1], BLKmode, 0);
3470 set_mem_size (operands[1], size);
3471 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3472 operands[3] = GEN_INT (mask);
3473 })
3475 ;
3476 ; insv instruction patterns
3477 ;
3479 (define_expand "insv"
3480 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3481 (match_operand 1 "const_int_operand" "")
3482 (match_operand 2 "const_int_operand" ""))
3483 (match_operand 3 "general_operand" ""))]
3484 ""
3485 {
3486 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3487 DONE;
3488 FAIL;
3489 })
3492 ; The normal RTL expansion will never generate a zero_extract where
3493 ; the location operand isn't word mode. However, we do this in the
3494 ; back-end when generating atomic operations. See s390_two_part_insv.
3495 (define_insn "*insv<mode>_zEC12"
3496 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3497 (match_operand 1 "const_int_operand" "I") ; size
3498 (match_operand 2 "const_int_operand" "I")) ; pos
3499 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3500 "TARGET_ZEC12
3501 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3502 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3503 [(set_attr "op_type" "RIE")])
3505 (define_insn "*insv<mode>_z10"
3506 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3507 (match_operand 1 "const_int_operand" "I") ; size
3508 (match_operand 2 "const_int_operand" "I")) ; pos
3509 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3510 (clobber (reg:CC CC_REGNUM))]
3511 "TARGET_Z10
3512 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3513 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3514 [(set_attr "op_type" "RIE")
3515 (set_attr "z10prop" "z10_super_E1")])
3517 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3518 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3519 (define_insn "*insv<mode>_zEC12_noshift"
3520 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3521 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3522 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3523 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3524 (match_operand:GPR 4 "const_int_operand" ""))))]
3525 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3526 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3527 [(set_attr "op_type" "RIE")])
3529 (define_insn "*insv<mode>_z10_noshift"
3530 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3531 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3532 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3533 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3534 (match_operand:GPR 4 "const_int_operand" ""))))
3535 (clobber (reg:CC CC_REGNUM))]
3536 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3537 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3538 [(set_attr "op_type" "RIE")
3539 (set_attr "z10prop" "z10_super_E1")])
3541 (define_insn "*r<noxa>sbg_<mode>_noshift"
3542 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3543 (IXOR:GPR
3544 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3545 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3546 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3547 (clobber (reg:CC CC_REGNUM))]
3548 "TARGET_Z10"
3549 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3550 [(set_attr "op_type" "RIE")])
3552 (define_insn "*r<noxa>sbg_di_rotl"
3553 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3554 (IXOR:DI
3555 (and:DI
3556 (rotate:DI
3557 (match_operand:DI 1 "nonimmediate_operand" "d")
3558 (match_operand:DI 3 "const_int_operand" ""))
3559 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3560 (match_operand:DI 4 "nonimmediate_operand" "0")))
3561 (clobber (reg:CC CC_REGNUM))]
3562 "TARGET_Z10"
3563 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3564 [(set_attr "op_type" "RIE")])
3566 (define_insn "*r<noxa>sbg_<mode>_srl"
3567 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3568 (IXOR:GPR
3569 (and:GPR
3570 (lshiftrt:GPR
3571 (match_operand:GPR 1 "nonimmediate_operand" "d")
3572 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3573 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3574 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3575 (clobber (reg:CC CC_REGNUM))]
3576 "TARGET_Z10
3577 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3578 INTVAL (operands[2]))"
3579 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3580 [(set_attr "op_type" "RIE")])
3582 (define_insn "*r<noxa>sbg_<mode>_sll"
3583 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3584 (IXOR:GPR
3585 (and:GPR
3586 (ashift:GPR
3587 (match_operand:GPR 1 "nonimmediate_operand" "d")
3588 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3589 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3590 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3591 (clobber (reg:CC CC_REGNUM))]
3592 "TARGET_Z10
3593 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3594 INTVAL (operands[2]))"
3595 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3596 [(set_attr "op_type" "RIE")])
3598 ;; These two are generated by combine for s.bf &= val.
3599 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3600 ;; shifts and ands, which results in some truly awful patterns
3601 ;; including subregs of operations. Rather unnecessisarily, IMO.
3602 ;; Instead of
3603 ;;
3604 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3605 ;; (const_int 24 [0x18])
3606 ;; (const_int 0 [0]))
3607 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3608 ;; (const_int 40 [0x28])) 4)
3609 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3610 ;;
3611 ;; we should instead generate
3612 ;;
3613 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3614 ;; (const_int 24 [0x18])
3615 ;; (const_int 0 [0]))
3616 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3617 ;; (const_int 40 [0x28]))
3618 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3619 ;;
3620 ;; by noticing that we can push down the outer paradoxical subreg
3621 ;; into the operation.
3623 (define_insn "*insv_rnsbg_noshift"
3624 [(set (zero_extract:DI
3625 (match_operand:DI 0 "nonimmediate_operand" "+d")
3626 (match_operand 1 "const_int_operand" "")
3627 (match_operand 2 "const_int_operand" ""))
3628 (and:DI
3629 (match_dup 0)
3630 (match_operand:DI 3 "nonimmediate_operand" "d")))
3631 (clobber (reg:CC CC_REGNUM))]
3632 "TARGET_Z10
3633 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3634 "rnsbg\t%0,%3,%2,63,0"
3635 [(set_attr "op_type" "RIE")])
3637 (define_insn "*insv_rnsbg_srl"
3638 [(set (zero_extract:DI
3639 (match_operand:DI 0 "nonimmediate_operand" "+d")
3640 (match_operand 1 "const_int_operand" "")
3641 (match_operand 2 "const_int_operand" ""))
3642 (and:DI
3643 (lshiftrt:DI
3644 (match_dup 0)
3645 (match_operand 3 "const_int_operand" ""))
3646 (match_operand:DI 4 "nonimmediate_operand" "d")))
3647 (clobber (reg:CC CC_REGNUM))]
3648 "TARGET_Z10
3649 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3650 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3651 [(set_attr "op_type" "RIE")])
3653 (define_insn "*insv<mode>_mem_reg"
3654 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3655 (match_operand 1 "const_int_operand" "n,n")
3656 (const_int 0))
3657 (match_operand:W 2 "register_operand" "d,d"))]
3658 "INTVAL (operands[1]) > 0
3659 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3660 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3661 {
3662 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3664 operands[1] = GEN_INT ((1ul << size) - 1);
3665 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3666 : "stcmy\t%2,%1,%S0";
3667 }
3668 [(set_attr "op_type" "RS,RSY")
3669 (set_attr "z10prop" "z10_super,z10_super")])
3671 (define_insn "*insvdi_mem_reghigh"
3672 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3673 (match_operand 1 "const_int_operand" "n")
3674 (const_int 0))
3675 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3676 (const_int 32)))]
3677 "TARGET_ZARCH
3678 && INTVAL (operands[1]) > 0
3679 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3680 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3681 {
3682 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3684 operands[1] = GEN_INT ((1ul << size) - 1);
3685 return "stcmh\t%2,%1,%S0";
3686 }
3687 [(set_attr "op_type" "RSY")
3688 (set_attr "z10prop" "z10_super")])
3690 (define_insn "*insvdi_reg_imm"
3691 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3692 (const_int 16)
3693 (match_operand 1 "const_int_operand" "n"))
3694 (match_operand:DI 2 "const_int_operand" "n"))]
3695 "TARGET_ZARCH
3696 && INTVAL (operands[1]) >= 0
3697 && INTVAL (operands[1]) < BITS_PER_WORD
3698 && INTVAL (operands[1]) % 16 == 0"
3699 {
3700 switch (BITS_PER_WORD - INTVAL (operands[1]))
3701 {
3702 case 64: return "iihh\t%0,%x2"; break;
3703 case 48: return "iihl\t%0,%x2"; break;
3704 case 32: return "iilh\t%0,%x2"; break;
3705 case 16: return "iill\t%0,%x2"; break;
3706 default: gcc_unreachable();
3707 }
3708 }
3709 [(set_attr "op_type" "RI")
3710 (set_attr "z10prop" "z10_super_E1")])
3712 ; Update the left-most 32 bit of a DI.
3713 (define_insn "*insv_h_di_reg_extimm"
3714 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3715 (const_int 32)
3716 (const_int 0))
3717 (match_operand:DI 1 "const_int_operand" "n"))]
3718 "TARGET_EXTIMM"
3719 "iihf\t%0,%o1"
3720 [(set_attr "op_type" "RIL")
3721 (set_attr "z10prop" "z10_fwd_E1")])
3723 ; Update the right-most 32 bit of a DI.
3724 (define_insn "*insv_l_di_reg_extimm"
3725 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3726 (const_int 32)
3727 (const_int 32))
3728 (match_operand:DI 1 "const_int_operand" "n"))]
3729 "TARGET_EXTIMM"
3730 "iilf\t%0,%o1"
3731 [(set_attr "op_type" "RIL")
3732 (set_attr "z10prop" "z10_fwd_A1")])
3734 ;
3735 ; extendsidi2 instruction pattern(s).
3736 ;
3738 (define_expand "extendsidi2"
3739 [(set (match_operand:DI 0 "register_operand" "")
3740 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3741 ""
3742 {
3743 if (!TARGET_ZARCH)
3744 {
3745 emit_clobber (operands[0]);
3746 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3747 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3748 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3749 DONE;
3750 }
3751 })
3753 (define_insn "*extendsidi2"
3754 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3755 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3756 "TARGET_ZARCH"
3757 "@
3758 lgfr\t%0,%1
3759 lgf\t%0,%1
3760 lgfrl\t%0,%1"
3761 [(set_attr "op_type" "RRE,RXY,RIL")
3762 (set_attr "type" "*,*,larl")
3763 (set_attr "cpu_facility" "*,*,z10")
3764 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3766 ;
3767 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3768 ;
3770 (define_expand "extend<HQI:mode><DSI:mode>2"
3771 [(set (match_operand:DSI 0 "register_operand" "")
3772 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3773 ""
3774 {
3775 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3776 {
3777 rtx tmp = gen_reg_rtx (SImode);
3778 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3779 emit_insn (gen_extendsidi2 (operands[0], tmp));
3780 DONE;
3781 }
3782 else if (!TARGET_EXTIMM)
3783 {
3784 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3786 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3787 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3788 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3789 DONE;
3790 }
3791 })
3793 ;
3794 ; extendhidi2 instruction pattern(s).
3795 ;
3797 (define_insn "*extendhidi2_extimm"
3798 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3799 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3800 "TARGET_ZARCH && TARGET_EXTIMM"
3801 "@
3802 lghr\t%0,%1
3803 lgh\t%0,%1
3804 lghrl\t%0,%1"
3805 [(set_attr "op_type" "RRE,RXY,RIL")
3806 (set_attr "type" "*,*,larl")
3807 (set_attr "cpu_facility" "extimm,extimm,z10")
3808 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3810 (define_insn "*extendhidi2"
3811 [(set (match_operand:DI 0 "register_operand" "=d")
3812 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3813 "TARGET_ZARCH"
3814 "lgh\t%0,%1"
3815 [(set_attr "op_type" "RXY")
3816 (set_attr "z10prop" "z10_super_E1")])
3818 ;
3819 ; extendhisi2 instruction pattern(s).
3820 ;
3822 (define_insn "*extendhisi2_extimm"
3823 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3824 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3825 "TARGET_EXTIMM"
3826 "@
3827 lhr\t%0,%1
3828 lh\t%0,%1
3829 lhy\t%0,%1
3830 lhrl\t%0,%1"
3831 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3832 (set_attr "type" "*,*,*,larl")
3833 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3834 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3836 (define_insn "*extendhisi2"
3837 [(set (match_operand:SI 0 "register_operand" "=d,d")
3838 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3839 "!TARGET_EXTIMM"
3840 "@
3841 lh\t%0,%1
3842 lhy\t%0,%1"
3843 [(set_attr "op_type" "RX,RXY")
3844 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3846 ;
3847 ; extendqi(si|di)2 instruction pattern(s).
3848 ;
3850 ; lbr, lgbr, lb, lgb
3851 (define_insn "*extendqi<mode>2_extimm"
3852 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3853 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3854 "TARGET_EXTIMM"
3855 "@
3856 l<g>br\t%0,%1
3857 l<g>b\t%0,%1"
3858 [(set_attr "op_type" "RRE,RXY")
3859 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3861 ; lb, lgb
3862 (define_insn "*extendqi<mode>2"
3863 [(set (match_operand:GPR 0 "register_operand" "=d")
3864 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3865 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3866 "l<g>b\t%0,%1"
3867 [(set_attr "op_type" "RXY")
3868 (set_attr "z10prop" "z10_super_E1")])
3870 (define_insn_and_split "*extendqi<mode>2_short_displ"
3871 [(set (match_operand:GPR 0 "register_operand" "=d")
3872 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3873 (clobber (reg:CC CC_REGNUM))]
3874 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3875 "#"
3876 "&& reload_completed"
3877 [(parallel
3878 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3879 (clobber (reg:CC CC_REGNUM))])
3880 (parallel
3881 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3882 (clobber (reg:CC CC_REGNUM))])]
3883 {
3884 operands[1] = adjust_address (operands[1], BLKmode, 0);
3885 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3886 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3887 })
3889 ;
3890 ; zero_extendsidi2 instruction pattern(s).
3891 ;
3893 (define_expand "zero_extendsidi2"
3894 [(set (match_operand:DI 0 "register_operand" "")
3895 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3896 ""
3897 {
3898 if (!TARGET_ZARCH)
3899 {
3900 emit_clobber (operands[0]);
3901 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3902 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3903 DONE;
3904 }
3905 })
3907 (define_insn "*zero_extendsidi2"
3908 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3909 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3910 "TARGET_ZARCH"
3911 "@
3912 llgfr\t%0,%1
3913 llgf\t%0,%1
3914 llgfrl\t%0,%1"
3915 [(set_attr "op_type" "RRE,RXY,RIL")
3916 (set_attr "type" "*,*,larl")
3917 (set_attr "cpu_facility" "*,*,z10")
3918 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3920 ;
3921 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3922 ;
3924 (define_insn "*llgt_sidi"
3925 [(set (match_operand:DI 0 "register_operand" "=d")
3926 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3927 (const_int 2147483647)))]
3928 "TARGET_ZARCH"
3929 "llgt\t%0,%1"
3930 [(set_attr "op_type" "RXE")
3931 (set_attr "z10prop" "z10_super_E1")])
3933 (define_insn_and_split "*llgt_sidi_split"
3934 [(set (match_operand:DI 0 "register_operand" "=d")
3935 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3936 (const_int 2147483647)))
3937 (clobber (reg:CC CC_REGNUM))]
3938 "TARGET_ZARCH"
3939 "#"
3940 "&& reload_completed"
3941 [(set (match_dup 0)
3942 (and:DI (subreg:DI (match_dup 1) 0)
3943 (const_int 2147483647)))]
3944 "")
3946 (define_insn "*llgt_sisi"
3947 [(set (match_operand:SI 0 "register_operand" "=d,d")
3948 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3949 (const_int 2147483647)))]
3950 "TARGET_ZARCH"
3951 "@
3952 llgtr\t%0,%1
3953 llgt\t%0,%1"
3954 [(set_attr "op_type" "RRE,RXE")
3955 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3957 (define_insn "*llgt_didi"
3958 [(set (match_operand:DI 0 "register_operand" "=d,d")
3959 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3960 (const_int 2147483647)))]
3961 "TARGET_ZARCH"
3962 "@
3963 llgtr\t%0,%1
3964 llgt\t%0,%N1"
3965 [(set_attr "op_type" "RRE,RXE")
3966 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3968 (define_split
3969 [(set (match_operand:DSI 0 "register_operand" "")
3970 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3971 (const_int 2147483647)))
3972 (clobber (reg:CC CC_REGNUM))]
3973 "TARGET_ZARCH && reload_completed"
3974 [(set (match_dup 0)
3975 (and:DSI (match_dup 1)
3976 (const_int 2147483647)))]
3977 "")
3979 ;
3980 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3981 ;
3983 (define_expand "zero_extend<mode>di2"
3984 [(set (match_operand:DI 0 "register_operand" "")
3985 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3986 ""
3987 {
3988 if (!TARGET_ZARCH)
3989 {
3990 rtx tmp = gen_reg_rtx (SImode);
3991 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3992 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3993 DONE;
3994 }
3995 else if (!TARGET_EXTIMM)
3996 {
3997 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
3998 operands[1] = gen_lowpart (DImode, operands[1]);
3999 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4000 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4001 DONE;
4002 }
4003 })
4005 (define_expand "zero_extend<mode>si2"
4006 [(set (match_operand:SI 0 "register_operand" "")
4007 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4008 ""
4009 {
4010 if (!TARGET_EXTIMM)
4011 {
4012 operands[1] = gen_lowpart (SImode, operands[1]);
4013 emit_insn (gen_andsi3 (operands[0], operands[1],
4014 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4015 DONE;
4016 }
4017 })
4019 ; llhrl, llghrl
4020 (define_insn "*zero_extendhi<mode>2_z10"
4021 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4022 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4023 "TARGET_Z10"
4024 "@
4025 ll<g>hr\t%0,%1
4026 ll<g>h\t%0,%1
4027 ll<g>hrl\t%0,%1"
4028 [(set_attr "op_type" "RXY,RRE,RIL")
4029 (set_attr "type" "*,*,larl")
4030 (set_attr "cpu_facility" "*,*,z10")
4031 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4033 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4034 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4035 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4036 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4037 "TARGET_EXTIMM"
4038 "@
4039 ll<g><hc>r\t%0,%1
4040 ll<g><hc>\t%0,%1"
4041 [(set_attr "op_type" "RRE,RXY")
4042 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4044 ; llgh, llgc
4045 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4046 [(set (match_operand:GPR 0 "register_operand" "=d")
4047 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4048 "TARGET_ZARCH && !TARGET_EXTIMM"
4049 "llg<hc>\t%0,%1"
4050 [(set_attr "op_type" "RXY")
4051 (set_attr "z10prop" "z10_fwd_A3")])
4053 (define_insn_and_split "*zero_extendhisi2_31"
4054 [(set (match_operand:SI 0 "register_operand" "=&d")
4055 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4056 (clobber (reg:CC CC_REGNUM))]
4057 "!TARGET_ZARCH"
4058 "#"
4059 "&& reload_completed"
4060 [(set (match_dup 0) (const_int 0))
4061 (parallel
4062 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4063 (clobber (reg:CC CC_REGNUM))])]
4064 "operands[2] = gen_lowpart (HImode, operands[0]);")
4066 (define_insn_and_split "*zero_extendqisi2_31"
4067 [(set (match_operand:SI 0 "register_operand" "=&d")
4068 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4069 "!TARGET_ZARCH"
4070 "#"
4071 "&& reload_completed"
4072 [(set (match_dup 0) (const_int 0))
4073 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4074 "operands[2] = gen_lowpart (QImode, operands[0]);")
4076 ;
4077 ; zero_extendqihi2 instruction pattern(s).
4078 ;
4080 (define_expand "zero_extendqihi2"
4081 [(set (match_operand:HI 0 "register_operand" "")
4082 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4083 "TARGET_ZARCH && !TARGET_EXTIMM"
4084 {
4085 operands[1] = gen_lowpart (HImode, operands[1]);
4086 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4087 DONE;
4088 })
4090 (define_insn "*zero_extendqihi2_64"
4091 [(set (match_operand:HI 0 "register_operand" "=d")
4092 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4093 "TARGET_ZARCH && !TARGET_EXTIMM"
4094 "llgc\t%0,%1"
4095 [(set_attr "op_type" "RXY")
4096 (set_attr "z10prop" "z10_fwd_A3")])
4098 (define_insn_and_split "*zero_extendqihi2_31"
4099 [(set (match_operand:HI 0 "register_operand" "=&d")
4100 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4101 "!TARGET_ZARCH"
4102 "#"
4103 "&& reload_completed"
4104 [(set (match_dup 0) (const_int 0))
4105 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4106 "operands[2] = gen_lowpart (QImode, operands[0]);")
4108 ;
4109 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4110 ;
4112 (define_expand "fixuns_truncdddi2"
4113 [(parallel
4114 [(set (match_operand:DI 0 "register_operand" "")
4115 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4116 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4117 (clobber (reg:CC CC_REGNUM))])]
4119 "TARGET_HARD_DFP"
4120 {
4121 if (!TARGET_Z196)
4122 {
4123 rtx label1 = gen_label_rtx ();
4124 rtx label2 = gen_label_rtx ();
4125 rtx temp = gen_reg_rtx (TDmode);
4126 REAL_VALUE_TYPE cmp, sub;
4128 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4129 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4131 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4132 solution is doing the check and the subtraction in TD mode and using a
4133 TD -> DI convert afterwards. */
4134 emit_insn (gen_extendddtd2 (temp, operands[1]));
4135 temp = force_reg (TDmode, temp);
4136 emit_cmp_and_jump_insns (temp,
4137 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4138 LT, NULL_RTX, VOIDmode, 0, label1);
4139 emit_insn (gen_subtd3 (temp, temp,
4140 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4141 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4142 emit_jump (label2);
4144 emit_label (label1);
4145 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4146 emit_label (label2);
4147 DONE;
4148 }
4149 })
4151 (define_expand "fixuns_trunctddi2"
4152 [(parallel
4153 [(set (match_operand:DI 0 "register_operand" "")
4154 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4155 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4156 (clobber (reg:CC CC_REGNUM))])]
4158 "TARGET_HARD_DFP"
4159 {
4160 if (!TARGET_Z196)
4161 {
4162 rtx label1 = gen_label_rtx ();
4163 rtx label2 = gen_label_rtx ();
4164 rtx temp = gen_reg_rtx (TDmode);
4165 REAL_VALUE_TYPE cmp, sub;
4167 operands[1] = force_reg (TDmode, operands[1]);
4168 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4169 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4171 emit_cmp_and_jump_insns (operands[1],
4172 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4173 LT, NULL_RTX, VOIDmode, 0, label1);
4174 emit_insn (gen_subtd3 (temp, operands[1],
4175 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4176 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4177 emit_jump (label2);
4179 emit_label (label1);
4180 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4181 emit_label (label2);
4182 DONE;
4183 }
4184 })
4186 ;
4187 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4188 ; instruction pattern(s).
4189 ;
4191 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4192 [(parallel
4193 [(set (match_operand:GPR 0 "register_operand" "")
4194 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4195 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4196 (clobber (reg:CC CC_REGNUM))])]
4197 "TARGET_HARD_FLOAT"
4198 {
4199 if (!TARGET_Z196)
4200 {
4201 rtx label1 = gen_label_rtx ();
4202 rtx label2 = gen_label_rtx ();
4203 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4204 REAL_VALUE_TYPE cmp, sub;
4206 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4207 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4208 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4210 emit_cmp_and_jump_insns (operands[1],
4211 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4212 LT, NULL_RTX, VOIDmode, 0, label1);
4213 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4214 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4215 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4216 GEN_INT (7)));
4217 emit_jump (label2);
4219 emit_label (label1);
4220 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4221 operands[1], GEN_INT (5)));
4222 emit_label (label2);
4223 DONE;
4224 }
4225 })
4227 ; fixuns_trunc(td|dd)si2 expander
4228 (define_expand "fixuns_trunc<mode>si2"
4229 [(parallel
4230 [(set (match_operand:SI 0 "register_operand" "")
4231 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4232 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4233 (clobber (reg:CC CC_REGNUM))])]
4234 "TARGET_Z196 && TARGET_HARD_DFP"
4235 "")
4237 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4239 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4240 ; clfdtr, clfxtr, clgdtr, clgxtr
4241 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4242 [(set (match_operand:GPR 0 "register_operand" "=r")
4243 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4244 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4245 (clobber (reg:CC CC_REGNUM))]
4246 "TARGET_Z196"
4247 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4248 [(set_attr "op_type" "RRF")
4249 (set_attr "type" "ftoi")])
4251 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4252 [(set (match_operand:GPR 0 "register_operand" "")
4253 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4254 "TARGET_HARD_FLOAT"
4255 {
4256 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4257 GEN_INT (5)));
4258 DONE;
4259 })
4261 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4262 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4263 [(set (match_operand:GPR 0 "register_operand" "=d")
4264 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4265 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4266 (clobber (reg:CC CC_REGNUM))]
4267 "TARGET_HARD_FLOAT"
4268 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4269 [(set_attr "op_type" "RRE")
4270 (set_attr "type" "ftoi")])
4273 ;
4274 ; fix_trunc(td|dd)di2 instruction pattern(s).
4275 ;
4277 (define_expand "fix_trunc<mode>di2"
4278 [(set (match_operand:DI 0 "register_operand" "")
4279 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4280 "TARGET_ZARCH && TARGET_HARD_DFP"
4281 {
4282 operands[1] = force_reg (<MODE>mode, operands[1]);
4283 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4284 GEN_INT (9)));
4285 DONE;
4286 })
4288 ; cgxtr, cgdtr
4289 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4290 [(set (match_operand:DI 0 "register_operand" "=d")
4291 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4292 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4293 (clobber (reg:CC CC_REGNUM))]
4294 "TARGET_ZARCH && TARGET_HARD_DFP"
4295 "cg<DFP:xde>tr\t%0,%h2,%1"
4296 [(set_attr "op_type" "RRF")
4297 (set_attr "type" "ftoidfp")])
4300 ;
4301 ; fix_trunctf(si|di)2 instruction pattern(s).
4302 ;
4304 (define_expand "fix_trunctf<mode>2"
4305 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4306 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4307 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4308 (clobber (reg:CC CC_REGNUM))])]
4309 "TARGET_HARD_FLOAT"
4310 "")
4313 ;
4314 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4315 ;
4317 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4318 (define_insn "floatdi<mode>2"
4319 [(set (match_operand:FP 0 "register_operand" "=f")
4320 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4321 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4322 "c<xde>g<bt>r\t%0,%1"
4323 [(set_attr "op_type" "RRE")
4324 (set_attr "type" "itof<mode>" )])
4326 ; cxfbr, cdfbr, cefbr
4327 (define_insn "floatsi<mode>2"
4328 [(set (match_operand:BFP 0 "register_operand" "=f")
4329 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4330 "TARGET_HARD_FLOAT"
4331 "c<xde>fbr\t%0,%1"
4332 [(set_attr "op_type" "RRE")
4333 (set_attr "type" "itof<mode>" )])
4335 ; cxftr, cdftr
4336 (define_insn "floatsi<mode>2"
4337 [(set (match_operand:DFP 0 "register_operand" "=f")
4338 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4339 "TARGET_Z196 && TARGET_HARD_FLOAT"
4340 "c<xde>ftr\t%0,0,%1,0"
4341 [(set_attr "op_type" "RRE")
4342 (set_attr "type" "itof<mode>" )])
4344 ;
4345 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4346 ;
4348 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4349 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4350 (define_insn "floatuns<GPR:mode><FP:mode>2"
4351 [(set (match_operand:FP 0 "register_operand" "=f")
4352 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4353 "TARGET_Z196 && TARGET_HARD_FLOAT"
4354 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4355 [(set_attr "op_type" "RRE")
4356 (set_attr "type" "itof<FP:mode>" )])
4358 ;
4359 ; truncdfsf2 instruction pattern(s).
4360 ;
4362 (define_insn "truncdfsf2"
4363 [(set (match_operand:SF 0 "register_operand" "=f")
4364 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4365 "TARGET_HARD_FLOAT"
4366 "ledbr\t%0,%1"
4367 [(set_attr "op_type" "RRE")
4368 (set_attr "type" "ftruncdf")])
4370 ;
4371 ; trunctf(df|sf)2 instruction pattern(s).
4372 ;
4374 ; ldxbr, lexbr
4375 (define_insn "trunctf<mode>2"
4376 [(set (match_operand:DSF 0 "register_operand" "=f")
4377 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4378 (clobber (match_scratch:TF 2 "=f"))]
4379 "TARGET_HARD_FLOAT"
4380 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4381 [(set_attr "length" "6")
4382 (set_attr "type" "ftrunctf")])
4384 ;
4385 ; trunctddd2 and truncddsd2 instruction pattern(s).
4386 ;
4388 (define_insn "trunctddd2"
4389 [(set (match_operand:DD 0 "register_operand" "=f")
4390 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4391 (clobber (match_scratch:TD 2 "=f"))]
4392 "TARGET_HARD_DFP"
4393 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4394 [(set_attr "length" "6")
4395 (set_attr "type" "ftruncdd")])
4397 (define_insn "truncddsd2"
4398 [(set (match_operand:SD 0 "register_operand" "=f")
4399 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4400 "TARGET_HARD_DFP"
4401 "ledtr\t%0,0,%1,0"
4402 [(set_attr "op_type" "RRF")
4403 (set_attr "type" "ftruncsd")])
4405 ;
4406 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4407 ;
4409 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4410 (define_insn "extend<DSF:mode><BFP:mode>2"
4411 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4412 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4413 "TARGET_HARD_FLOAT
4414 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4415 "@
4416 l<BFP:xde><DSF:xde>br\t%0,%1
4417 l<BFP:xde><DSF:xde>b\t%0,%1"
4418 [(set_attr "op_type" "RRE,RXE")
4419 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4421 ;
4422 ; extendddtd2 and extendsddd2 instruction pattern(s).
4423 ;
4425 (define_insn "extendddtd2"
4426 [(set (match_operand:TD 0 "register_operand" "=f")
4427 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4428 "TARGET_HARD_DFP"
4429 "lxdtr\t%0,%1,0"
4430 [(set_attr "op_type" "RRF")
4431 (set_attr "type" "fsimptf")])
4433 (define_insn "extendsddd2"
4434 [(set (match_operand:DD 0 "register_operand" "=f")
4435 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4436 "TARGET_HARD_DFP"
4437 "ldetr\t%0,%1,0"
4438 [(set_attr "op_type" "RRF")
4439 (set_attr "type" "fsimptf")])
4441 ; Binary Floating Point - load fp integer
4443 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4444 ; For all of them the inexact exceptions are suppressed.
4446 ; fiebra, fidbra, fixbra
4447 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4448 [(set (match_operand:BFP 0 "register_operand" "=f")
4449 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4450 FPINT))]
4451 "TARGET_Z196"
4452 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4453 [(set_attr "op_type" "RRF")
4454 (set_attr "type" "fsimp<BFP:mode>")])
4456 ; rint is supposed to raise an inexact exception so we can use the
4457 ; older instructions.
4459 ; fiebr, fidbr, fixbr
4460 (define_insn "rint<BFP:mode>2"
4461 [(set (match_operand:BFP 0 "register_operand" "=f")
4462 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4463 UNSPEC_FPINT_RINT))]
4464 ""
4465 "fi<BFP:xde>br\t%0,0,%1"
4466 [(set_attr "op_type" "RRF")
4467 (set_attr "type" "fsimp<BFP:mode>")])
4470 ; Decimal Floating Point - load fp integer
4472 ; fidtr, fixtr
4473 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4474 [(set (match_operand:DFP 0 "register_operand" "=f")
4475 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4476 FPINT))]
4477 "TARGET_HARD_DFP"
4478 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4479 [(set_attr "op_type" "RRF")
4480 (set_attr "type" "fsimp<DFP:mode>")])
4482 ; fidtr, fixtr
4483 (define_insn "rint<DFP:mode>2"
4484 [(set (match_operand:DFP 0 "register_operand" "=f")
4485 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4486 UNSPEC_FPINT_RINT))]
4487 "TARGET_HARD_DFP"
4488 "fi<DFP:xde>tr\t%0,0,%1,0"
4489 [(set_attr "op_type" "RRF")
4490 (set_attr "type" "fsimp<DFP:mode>")])
4492 ;
4493 ; Binary <-> Decimal floating point trunc patterns
4494 ;
4496 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4497 [(set (reg:DFP_ALL FPR0_REGNUM)
4498 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4499 (use (reg:SI GPR0_REGNUM))
4500 (clobber (reg:CC CC_REGNUM))]
4501 "TARGET_HARD_DFP"
4502 "pfpo")
4504 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4505 [(set (reg:BFP FPR0_REGNUM)
4506 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4507 (use (reg:SI GPR0_REGNUM))
4508 (clobber (reg:CC CC_REGNUM))]
4509 "TARGET_HARD_DFP"
4510 "pfpo")
4512 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4513 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4514 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4515 (parallel
4516 [(set (reg:DFP_ALL FPR0_REGNUM)
4517 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4518 (use (reg:SI GPR0_REGNUM))
4519 (clobber (reg:CC CC_REGNUM))])
4520 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4521 (reg:DFP_ALL FPR0_REGNUM))]
4522 "TARGET_HARD_DFP
4523 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4524 {
4525 HOST_WIDE_INT flags;
4527 flags = (PFPO_CONVERT |
4528 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4529 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4531 operands[2] = GEN_INT (flags);
4532 })
4534 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4535 [(set (reg:DFP_ALL FPR4_REGNUM)
4536 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4537 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4538 (parallel
4539 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4540 (use (reg:SI GPR0_REGNUM))
4541 (clobber (reg:CC CC_REGNUM))])
4542 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4543 "TARGET_HARD_DFP
4544 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4545 {
4546 HOST_WIDE_INT flags;
4548 flags = (PFPO_CONVERT |
4549 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4550 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4552 operands[2] = GEN_INT (flags);
4553 })
4555 ;
4556 ; Binary <-> Decimal floating point extend patterns
4557 ;
4559 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4560 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4561 (use (reg:SI GPR0_REGNUM))
4562 (clobber (reg:CC CC_REGNUM))]
4563 "TARGET_HARD_DFP"
4564 "pfpo")
4566 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4567 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4568 (use (reg:SI GPR0_REGNUM))
4569 (clobber (reg:CC CC_REGNUM))]
4570 "TARGET_HARD_DFP"
4571 "pfpo")
4573 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4574 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4575 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4576 (parallel
4577 [(set (reg:DFP_ALL FPR0_REGNUM)
4578 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4579 (use (reg:SI GPR0_REGNUM))
4580 (clobber (reg:CC CC_REGNUM))])
4581 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4582 (reg:DFP_ALL FPR0_REGNUM))]
4583 "TARGET_HARD_DFP
4584 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4585 {
4586 HOST_WIDE_INT flags;
4588 flags = (PFPO_CONVERT |
4589 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4590 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4592 operands[2] = GEN_INT (flags);
4593 })
4595 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4596 [(set (reg:DFP_ALL FPR4_REGNUM)
4597 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4598 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4599 (parallel
4600 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4601 (use (reg:SI GPR0_REGNUM))
4602 (clobber (reg:CC CC_REGNUM))])
4603 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4604 "TARGET_HARD_DFP
4605 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4606 {
4607 HOST_WIDE_INT flags;
4609 flags = (PFPO_CONVERT |
4610 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4611 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4613 operands[2] = GEN_INT (flags);
4614 })
4617 ;;
4618 ;; ARITHMETIC OPERATIONS
4619 ;;
4620 ; arithmetic operations set the ConditionCode,
4621 ; because of unpredictable Bits in Register for Halfword and Byte
4622 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4624 ;;
4625 ;;- Add instructions.
4626 ;;
4628 ;
4629 ; addti3 instruction pattern(s).
4630 ;
4632 (define_insn_and_split "addti3"
4633 [(set (match_operand:TI 0 "register_operand" "=&d")
4634 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4635 (match_operand:TI 2 "general_operand" "do") ) )
4636 (clobber (reg:CC CC_REGNUM))]
4637 "TARGET_ZARCH"
4638 "#"
4639 "&& reload_completed"
4640 [(parallel
4641 [(set (reg:CCL1 CC_REGNUM)
4642 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4643 (match_dup 7)))
4644 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4645 (parallel
4646 [(set (match_dup 3) (plus:DI
4647 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4648 (match_dup 4)) (match_dup 5)))
4649 (clobber (reg:CC CC_REGNUM))])]
4650 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4651 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4652 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4653 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4654 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4655 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4657 ;
4658 ; adddi3 instruction pattern(s).
4659 ;
4661 (define_expand "adddi3"
4662 [(parallel
4663 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4664 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4665 (match_operand:DI 2 "general_operand" "")))
4666 (clobber (reg:CC CC_REGNUM))])]
4667 ""
4668 "")
4670 (define_insn "*adddi3_sign"
4671 [(set (match_operand:DI 0 "register_operand" "=d,d")
4672 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4673 (match_operand:DI 1 "register_operand" "0,0")))
4674 (clobber (reg:CC CC_REGNUM))]
4675 "TARGET_ZARCH"
4676 "@
4677 agfr\t%0,%2
4678 agf\t%0,%2"
4679 [(set_attr "op_type" "RRE,RXY")
4680 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4682 (define_insn "*adddi3_zero_cc"
4683 [(set (reg CC_REGNUM)
4684 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4685 (match_operand:DI 1 "register_operand" "0,0"))
4686 (const_int 0)))
4687 (set (match_operand:DI 0 "register_operand" "=d,d")
4688 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4689 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4690 "@
4691 algfr\t%0,%2
4692 algf\t%0,%2"
4693 [(set_attr "op_type" "RRE,RXY")
4694 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4696 (define_insn "*adddi3_zero_cconly"
4697 [(set (reg CC_REGNUM)
4698 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4699 (match_operand:DI 1 "register_operand" "0,0"))
4700 (const_int 0)))
4701 (clobber (match_scratch:DI 0 "=d,d"))]
4702 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4703 "@
4704 algfr\t%0,%2
4705 algf\t%0,%2"
4706 [(set_attr "op_type" "RRE,RXY")
4707 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4709 (define_insn "*adddi3_zero"
4710 [(set (match_operand:DI 0 "register_operand" "=d,d")
4711 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4712 (match_operand:DI 1 "register_operand" "0,0")))
4713 (clobber (reg:CC CC_REGNUM))]
4714 "TARGET_ZARCH"
4715 "@
4716 algfr\t%0,%2
4717 algf\t%0,%2"
4718 [(set_attr "op_type" "RRE,RXY")
4719 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4721 (define_insn_and_split "*adddi3_31z"
4722 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4723 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4724 (match_operand:DI 2 "general_operand" "do") ) )
4725 (clobber (reg:CC CC_REGNUM))]
4726 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4727 "#"
4728 "&& reload_completed"
4729 [(parallel
4730 [(set (reg:CCL1 CC_REGNUM)
4731 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4732 (match_dup 7)))
4733 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4734 (parallel
4735 [(set (match_dup 3) (plus:SI
4736 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4737 (match_dup 4)) (match_dup 5)))
4738 (clobber (reg:CC CC_REGNUM))])]
4739 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4740 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4741 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4742 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4743 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4744 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4746 (define_insn_and_split "*adddi3_31"
4747 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4748 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4749 (match_operand:DI 2 "general_operand" "do") ) )
4750 (clobber (reg:CC CC_REGNUM))]
4751 "!TARGET_CPU_ZARCH"
4752 "#"
4753 "&& reload_completed"
4754 [(parallel
4755 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4756 (clobber (reg:CC CC_REGNUM))])
4757 (parallel
4758 [(set (reg:CCL1 CC_REGNUM)
4759 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4760 (match_dup 7)))
4761 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4762 (set (pc)
4763 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4764 (pc)
4765 (label_ref (match_dup 9))))
4766 (parallel
4767 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4768 (clobber (reg:CC CC_REGNUM))])
4769 (match_dup 9)]
4770 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4771 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4772 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4773 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4774 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4775 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4776 operands[9] = gen_label_rtx ();")
4778 ;
4779 ; addsi3 instruction pattern(s).
4780 ;
4782 (define_expand "addsi3"
4783 [(parallel
4784 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4785 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4786 (match_operand:SI 2 "general_operand" "")))
4787 (clobber (reg:CC CC_REGNUM))])]
4788 ""
4789 "")
4791 (define_insn "*addsi3_sign"
4792 [(set (match_operand:SI 0 "register_operand" "=d,d")
4793 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4794 (match_operand:SI 1 "register_operand" "0,0")))
4795 (clobber (reg:CC CC_REGNUM))]
4796 ""
4797 "@
4798 ah\t%0,%2
4799 ahy\t%0,%2"
4800 [(set_attr "op_type" "RX,RXY")
4801 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4803 ;
4804 ; add(di|si)3 instruction pattern(s).
4805 ;
4807 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4808 (define_insn "*add<mode>3"
4809 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4810 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4811 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4812 (clobber (reg:CC CC_REGNUM))]
4813 ""
4814 "@
4815 a<g>r\t%0,%2
4816 a<g>rk\t%0,%1,%2
4817 a<g>hi\t%0,%h2
4818 a<g>hik\t%0,%1,%h2
4819 al<g>fi\t%0,%2
4820 sl<g>fi\t%0,%n2
4821 a<g>\t%0,%2
4822 a<y>\t%0,%2
4823 a<g>si\t%0,%c2"
4824 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4825 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4826 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4827 z10_super_E1,z10_super_E1,z10_super_E1")])
4829 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4830 (define_insn "*add<mode>3_carry1_cc"
4831 [(set (reg CC_REGNUM)
4832 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4833 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4834 (match_dup 1)))
4835 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4836 (plus:GPR (match_dup 1) (match_dup 2)))]
4837 "s390_match_ccmode (insn, CCL1mode)"
4838 "@
4839 al<g>r\t%0,%2
4840 al<g>rk\t%0,%1,%2
4841 al<g>fi\t%0,%2
4842 sl<g>fi\t%0,%n2
4843 al<g>hsik\t%0,%1,%h2
4844 al<g>\t%0,%2
4845 al<y>\t%0,%2
4846 al<g>si\t%0,%c2"
4847 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4848 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4849 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4850 z10_super_E1,z10_super_E1,z10_super_E1")])
4852 ; alr, al, aly, algr, alg, alrk, algrk
4853 (define_insn "*add<mode>3_carry1_cconly"
4854 [(set (reg CC_REGNUM)
4855 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4856 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4857 (match_dup 1)))
4858 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4859 "s390_match_ccmode (insn, CCL1mode)"
4860 "@
4861 al<g>r\t%0,%2
4862 al<g>rk\t%0,%1,%2
4863 al<g>\t%0,%2
4864 al<y>\t%0,%2"
4865 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4866 (set_attr "cpu_facility" "*,z196,*,*")
4867 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4869 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4870 (define_insn "*add<mode>3_carry2_cc"
4871 [(set (reg CC_REGNUM)
4872 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4873 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4874 (match_dup 2)))
4875 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4876 (plus:GPR (match_dup 1) (match_dup 2)))]
4877 "s390_match_ccmode (insn, CCL1mode)"
4878 "@
4879 al<g>r\t%0,%2
4880 al<g>rk\t%0,%1,%2
4881 al<g>fi\t%0,%2
4882 sl<g>fi\t%0,%n2
4883 al<g>hsik\t%0,%1,%h2
4884 al<g>\t%0,%2
4885 al<y>\t%0,%2
4886 al<g>si\t%0,%c2"
4887 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4888 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4889 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4890 z10_super_E1,z10_super_E1,z10_super_E1")])
4892 ; alr, al, aly, algr, alg, alrk, algrk
4893 (define_insn "*add<mode>3_carry2_cconly"
4894 [(set (reg CC_REGNUM)
4895 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4896 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4897 (match_dup 2)))
4898 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4899 "s390_match_ccmode (insn, CCL1mode)"
4900 "@
4901 al<g>r\t%0,%2
4902 al<g>rk\t%0,%1,%2
4903 al<g>\t%0,%2
4904 al<y>\t%0,%2"
4905 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4906 (set_attr "cpu_facility" "*,z196,*,*")
4907 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4909 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4910 (define_insn "*add<mode>3_cc"
4911 [(set (reg CC_REGNUM)
4912 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4913 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4914 (const_int 0)))
4915 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4916 (plus:GPR (match_dup 1) (match_dup 2)))]
4917 "s390_match_ccmode (insn, CCLmode)"
4918 "@
4919 al<g>r\t%0,%2
4920 al<g>rk\t%0,%1,%2
4921 al<g>fi\t%0,%2
4922 sl<g>fi\t%0,%n2
4923 al<g>hsik\t%0,%1,%h2
4924 al<g>\t%0,%2
4925 al<y>\t%0,%2
4926 al<g>si\t%0,%c2"
4927 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4928 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4929 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4930 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4932 ; alr, al, aly, algr, alg, alrk, algrk
4933 (define_insn "*add<mode>3_cconly"
4934 [(set (reg CC_REGNUM)
4935 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4936 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4937 (const_int 0)))
4938 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4939 "s390_match_ccmode (insn, CCLmode)"
4940 "@
4941 al<g>r\t%0,%2
4942 al<g>rk\t%0,%1,%2
4943 al<g>\t%0,%2
4944 al<y>\t%0,%2"
4945 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4946 (set_attr "cpu_facility" "*,z196,*,*")
4947 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4949 ; alr, al, aly, algr, alg, alrk, algrk
4950 (define_insn "*add<mode>3_cconly2"
4951 [(set (reg CC_REGNUM)
4952 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4953 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4954 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4955 "s390_match_ccmode(insn, CCLmode)"
4956 "@
4957 al<g>r\t%0,%2
4958 al<g>rk\t%0,%1,%2
4959 al<g>\t%0,%2
4960 al<y>\t%0,%2"
4961 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4962 (set_attr "cpu_facility" "*,z196,*,*")
4963 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4965 ; ahi, afi, aghi, agfi, asi, agsi
4966 (define_insn "*add<mode>3_imm_cc"
4967 [(set (reg CC_REGNUM)
4968 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4969 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4970 (const_int 0)))
4971 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4972 (plus:GPR (match_dup 1) (match_dup 2)))]
4973 "s390_match_ccmode (insn, CCAmode)
4974 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4975 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4976 /* Avoid INT32_MIN on 32 bit. */
4977 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
4978 "@
4979 a<g>hi\t%0,%h2
4980 a<g>hik\t%0,%1,%h2
4981 a<g>fi\t%0,%2
4982 a<g>si\t%0,%c2"
4983 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4984 (set_attr "cpu_facility" "*,z196,extimm,z10")
4985 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4987 ;
4988 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4989 ;
4991 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4992 (define_insn "add<mode>3"
4993 [(set (match_operand:FP 0 "register_operand" "=f, f")
4994 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4995 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4996 (clobber (reg:CC CC_REGNUM))]
4997 "TARGET_HARD_FLOAT"
4998 "@
4999 a<xde><bt>r\t%0,<op1>%2
5000 a<xde>b\t%0,%2"
5001 [(set_attr "op_type" "<RRer>,RXE")
5002 (set_attr "type" "fsimp<mode>")])
5004 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5005 (define_insn "*add<mode>3_cc"
5006 [(set (reg CC_REGNUM)
5007 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5008 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5009 (match_operand:FP 3 "const0_operand" "")))
5010 (set (match_operand:FP 0 "register_operand" "=f,f")
5011 (plus:FP (match_dup 1) (match_dup 2)))]
5012 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5013 "@
5014 a<xde><bt>r\t%0,<op1>%2
5015 a<xde>b\t%0,%2"
5016 [(set_attr "op_type" "<RRer>,RXE")
5017 (set_attr "type" "fsimp<mode>")])
5019 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5020 (define_insn "*add<mode>3_cconly"
5021 [(set (reg CC_REGNUM)
5022 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5023 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5024 (match_operand:FP 3 "const0_operand" "")))
5025 (clobber (match_scratch:FP 0 "=f,f"))]
5026 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5027 "@
5028 a<xde><bt>r\t%0,<op1>%2
5029 a<xde>b\t%0,%2"
5030 [(set_attr "op_type" "<RRer>,RXE")
5031 (set_attr "type" "fsimp<mode>")])
5034 ;;
5035 ;;- Subtract instructions.
5036 ;;
5038 ;
5039 ; subti3 instruction pattern(s).
5040 ;
5042 (define_insn_and_split "subti3"
5043 [(set (match_operand:TI 0 "register_operand" "=&d")
5044 (minus:TI (match_operand:TI 1 "register_operand" "0")
5045 (match_operand:TI 2 "general_operand" "do") ) )
5046 (clobber (reg:CC CC_REGNUM))]
5047 "TARGET_ZARCH"
5048 "#"
5049 "&& reload_completed"
5050 [(parallel
5051 [(set (reg:CCL2 CC_REGNUM)
5052 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5053 (match_dup 7)))
5054 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5055 (parallel
5056 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5057 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5058 (clobber (reg:CC CC_REGNUM))])]
5059 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5060 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5061 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5062 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5063 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5064 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
5066 ;
5067 ; subdi3 instruction pattern(s).
5068 ;
5070 (define_expand "subdi3"
5071 [(parallel
5072 [(set (match_operand:DI 0 "register_operand" "")
5073 (minus:DI (match_operand:DI 1 "register_operand" "")
5074 (match_operand:DI 2 "general_operand" "")))
5075 (clobber (reg:CC CC_REGNUM))])]
5076 ""
5077 "")
5079 (define_insn "*subdi3_sign"
5080 [(set (match_operand:DI 0 "register_operand" "=d,d")
5081 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5082 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5083 (clobber (reg:CC CC_REGNUM))]
5084 "TARGET_ZARCH"
5085 "@
5086 sgfr\t%0,%2
5087 sgf\t%0,%2"
5088 [(set_attr "op_type" "RRE,RXY")
5089 (set_attr "z10prop" "z10_c,*")
5090 (set_attr "z196prop" "z196_cracked")])
5092 (define_insn "*subdi3_zero_cc"
5093 [(set (reg CC_REGNUM)
5094 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5095 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5096 (const_int 0)))
5097 (set (match_operand:DI 0 "register_operand" "=d,d")
5098 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5099 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5100 "@
5101 slgfr\t%0,%2
5102 slgf\t%0,%2"
5103 [(set_attr "op_type" "RRE,RXY")
5104 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5106 (define_insn "*subdi3_zero_cconly"
5107 [(set (reg CC_REGNUM)
5108 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5109 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5110 (const_int 0)))
5111 (clobber (match_scratch:DI 0 "=d,d"))]
5112 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5113 "@
5114 slgfr\t%0,%2
5115 slgf\t%0,%2"
5116 [(set_attr "op_type" "RRE,RXY")
5117 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5119 (define_insn "*subdi3_zero"
5120 [(set (match_operand:DI 0 "register_operand" "=d,d")
5121 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5122 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5123 (clobber (reg:CC CC_REGNUM))]
5124 "TARGET_ZARCH"
5125 "@
5126 slgfr\t%0,%2
5127 slgf\t%0,%2"
5128 [(set_attr "op_type" "RRE,RXY")
5129 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5131 (define_insn_and_split "*subdi3_31z"
5132 [(set (match_operand:DI 0 "register_operand" "=&d")
5133 (minus:DI (match_operand:DI 1 "register_operand" "0")
5134 (match_operand:DI 2 "general_operand" "do") ) )
5135 (clobber (reg:CC CC_REGNUM))]
5136 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5137 "#"
5138 "&& reload_completed"
5139 [(parallel
5140 [(set (reg:CCL2 CC_REGNUM)
5141 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5142 (match_dup 7)))
5143 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5144 (parallel
5145 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5146 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5147 (clobber (reg:CC CC_REGNUM))])]
5148 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5149 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5150 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5151 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5152 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5153 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5155 (define_insn_and_split "*subdi3_31"
5156 [(set (match_operand:DI 0 "register_operand" "=&d")
5157 (minus:DI (match_operand:DI 1 "register_operand" "0")
5158 (match_operand:DI 2 "general_operand" "do") ) )
5159 (clobber (reg:CC CC_REGNUM))]
5160 "!TARGET_CPU_ZARCH"
5161 "#"
5162 "&& reload_completed"
5163 [(parallel
5164 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5165 (clobber (reg:CC CC_REGNUM))])
5166 (parallel
5167 [(set (reg:CCL2 CC_REGNUM)
5168 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5169 (match_dup 7)))
5170 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5171 (set (pc)
5172 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5173 (pc)
5174 (label_ref (match_dup 9))))
5175 (parallel
5176 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5177 (clobber (reg:CC CC_REGNUM))])
5178 (match_dup 9)]
5179 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5180 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5181 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5182 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5183 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5184 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5185 operands[9] = gen_label_rtx ();")
5187 ;
5188 ; subsi3 instruction pattern(s).
5189 ;
5191 (define_expand "subsi3"
5192 [(parallel
5193 [(set (match_operand:SI 0 "register_operand" "")
5194 (minus:SI (match_operand:SI 1 "register_operand" "")
5195 (match_operand:SI 2 "general_operand" "")))
5196 (clobber (reg:CC CC_REGNUM))])]
5197 ""
5198 "")
5200 (define_insn "*subsi3_sign"
5201 [(set (match_operand:SI 0 "register_operand" "=d,d")
5202 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5203 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5204 (clobber (reg:CC CC_REGNUM))]
5205 ""
5206 "@
5207 sh\t%0,%2
5208 shy\t%0,%2"
5209 [(set_attr "op_type" "RX,RXY")
5210 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5212 ;
5213 ; sub(di|si)3 instruction pattern(s).
5214 ;
5216 ; sr, s, sy, sgr, sg, srk, sgrk
5217 (define_insn "*sub<mode>3"
5218 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5219 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5220 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5221 (clobber (reg:CC CC_REGNUM))]
5222 ""
5223 "@
5224 s<g>r\t%0,%2
5225 s<g>rk\t%0,%1,%2
5226 s<g>\t%0,%2
5227 s<y>\t%0,%2"
5228 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5229 (set_attr "cpu_facility" "*,z196,*,*")
5230 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5232 ; slr, sl, sly, slgr, slg, slrk, slgrk
5233 (define_insn "*sub<mode>3_borrow_cc"
5234 [(set (reg CC_REGNUM)
5235 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5236 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5237 (match_dup 1)))
5238 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5239 (minus:GPR (match_dup 1) (match_dup 2)))]
5240 "s390_match_ccmode (insn, CCL2mode)"
5241 "@
5242 sl<g>r\t%0,%2
5243 sl<g>rk\t%0,%1,%2
5244 sl<g>\t%0,%2
5245 sl<y>\t%0,%2"
5246 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5247 (set_attr "cpu_facility" "*,z196,*,*")
5248 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5250 ; slr, sl, sly, slgr, slg, slrk, slgrk
5251 (define_insn "*sub<mode>3_borrow_cconly"
5252 [(set (reg CC_REGNUM)
5253 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5254 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5255 (match_dup 1)))
5256 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5257 "s390_match_ccmode (insn, CCL2mode)"
5258 "@
5259 sl<g>r\t%0,%2
5260 sl<g>rk\t%0,%1,%2
5261 sl<g>\t%0,%2
5262 sl<y>\t%0,%2"
5263 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5264 (set_attr "cpu_facility" "*,z196,*,*")
5265 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5267 ; slr, sl, sly, slgr, slg, slrk, slgrk
5268 (define_insn "*sub<mode>3_cc"
5269 [(set (reg CC_REGNUM)
5270 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5271 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5272 (const_int 0)))
5273 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5274 (minus:GPR (match_dup 1) (match_dup 2)))]
5275 "s390_match_ccmode (insn, CCLmode)"
5276 "@
5277 sl<g>r\t%0,%2
5278 sl<g>rk\t%0,%1,%2
5279 sl<g>\t%0,%2
5280 sl<y>\t%0,%2"
5281 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5282 (set_attr "cpu_facility" "*,z196,*,*")
5283 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5285 ; slr, sl, sly, slgr, slg, slrk, slgrk
5286 (define_insn "*sub<mode>3_cc2"
5287 [(set (reg CC_REGNUM)
5288 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5289 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5290 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5291 (minus:GPR (match_dup 1) (match_dup 2)))]
5292 "s390_match_ccmode (insn, CCL3mode)"
5293 "@
5294 sl<g>r\t%0,%2
5295 sl<g>rk\t%0,%1,%2
5296 sl<g>\t%0,%2
5297 sl<y>\t%0,%2"
5298 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5299 (set_attr "cpu_facility" "*,z196,*,*")
5300 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5302 ; slr, sl, sly, slgr, slg, slrk, slgrk
5303 (define_insn "*sub<mode>3_cconly"
5304 [(set (reg CC_REGNUM)
5305 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5306 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5307 (const_int 0)))
5308 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5309 "s390_match_ccmode (insn, CCLmode)"
5310 "@
5311 sl<g>r\t%0,%2
5312 sl<g>rk\t%0,%1,%2
5313 sl<g>\t%0,%2
5314 sl<y>\t%0,%2"
5315 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5316 (set_attr "cpu_facility" "*,z196,*,*")
5317 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5320 ; slr, sl, sly, slgr, slg, slrk, slgrk
5321 (define_insn "*sub<mode>3_cconly2"
5322 [(set (reg CC_REGNUM)
5323 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5324 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5325 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5326 "s390_match_ccmode (insn, CCL3mode)"
5327 "@
5328 sl<g>r\t%0,%2
5329 sl<g>rk\t%0,%1,%2
5330 sl<g>\t%0,%2
5331 sl<y>\t%0,%2"
5332 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5333 (set_attr "cpu_facility" "*,z196,*,*")
5334 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5337 ;
5338 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5339 ;
5341 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5342 (define_insn "sub<mode>3"
5343 [(set (match_operand:FP 0 "register_operand" "=f, f")
5344 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5345 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5346 (clobber (reg:CC CC_REGNUM))]
5347 "TARGET_HARD_FLOAT"
5348 "@
5349 s<xde><bt>r\t%0,<op1>%2
5350 s<xde>b\t%0,%2"
5351 [(set_attr "op_type" "<RRer>,RXE")
5352 (set_attr "type" "fsimp<mode>")])
5354 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5355 (define_insn "*sub<mode>3_cc"
5356 [(set (reg CC_REGNUM)
5357 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5358 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5359 (match_operand:FP 3 "const0_operand" "")))
5360 (set (match_operand:FP 0 "register_operand" "=f,f")
5361 (minus:FP (match_dup 1) (match_dup 2)))]
5362 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5363 "@
5364 s<xde><bt>r\t%0,<op1>%2
5365 s<xde>b\t%0,%2"
5366 [(set_attr "op_type" "<RRer>,RXE")
5367 (set_attr "type" "fsimp<mode>")])
5369 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5370 (define_insn "*sub<mode>3_cconly"
5371 [(set (reg CC_REGNUM)
5372 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5373 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5374 (match_operand:FP 3 "const0_operand" "")))
5375 (clobber (match_scratch:FP 0 "=f,f"))]
5376 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5377 "@
5378 s<xde><bt>r\t%0,<op1>%2
5379 s<xde>b\t%0,%2"
5380 [(set_attr "op_type" "<RRer>,RXE")
5381 (set_attr "type" "fsimp<mode>")])
5384 ;;
5385 ;;- Conditional add/subtract instructions.
5386 ;;
5388 ;
5389 ; add(di|si)cc instruction pattern(s).
5390 ;
5392 ; the following 4 patterns are used when the result of an add with
5393 ; carry is checked for an overflow condition
5395 ; op1 + op2 + c < op1
5397 ; alcr, alc, alcgr, alcg
5398 (define_insn "*add<mode>3_alc_carry1_cc"
5399 [(set (reg CC_REGNUM)
5400 (compare
5401 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5402 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5403 (match_operand:GPR 2 "general_operand" "d,RT"))
5404 (match_dup 1)))
5405 (set (match_operand:GPR 0 "register_operand" "=d,d")
5406 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5407 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5408 "@
5409 alc<g>r\t%0,%2
5410 alc<g>\t%0,%2"
5411 [(set_attr "op_type" "RRE,RXY")
5412 (set_attr "z196prop" "z196_alone,z196_alone")])
5414 ; alcr, alc, alcgr, alcg
5415 (define_insn "*add<mode>3_alc_carry1_cconly"
5416 [(set (reg CC_REGNUM)
5417 (compare
5418 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5419 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5420 (match_operand:GPR 2 "general_operand" "d,RT"))
5421 (match_dup 1)))
5422 (clobber (match_scratch:GPR 0 "=d,d"))]
5423 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5424 "@
5425 alc<g>r\t%0,%2
5426 alc<g>\t%0,%2"
5427 [(set_attr "op_type" "RRE,RXY")
5428 (set_attr "z196prop" "z196_alone,z196_alone")])
5430 ; op1 + op2 + c < op2
5432 ; alcr, alc, alcgr, alcg
5433 (define_insn "*add<mode>3_alc_carry2_cc"
5434 [(set (reg CC_REGNUM)
5435 (compare
5436 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5437 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5438 (match_operand:GPR 2 "general_operand" "d,RT"))
5439 (match_dup 2)))
5440 (set (match_operand:GPR 0 "register_operand" "=d,d")
5441 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5442 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5443 "@
5444 alc<g>r\t%0,%2
5445 alc<g>\t%0,%2"
5446 [(set_attr "op_type" "RRE,RXY")])
5448 ; alcr, alc, alcgr, alcg
5449 (define_insn "*add<mode>3_alc_carry2_cconly"
5450 [(set (reg CC_REGNUM)
5451 (compare
5452 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5453 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5454 (match_operand:GPR 2 "general_operand" "d,RT"))
5455 (match_dup 2)))
5456 (clobber (match_scratch:GPR 0 "=d,d"))]
5457 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5458 "@
5459 alc<g>r\t%0,%2
5460 alc<g>\t%0,%2"
5461 [(set_attr "op_type" "RRE,RXY")])
5463 ; alcr, alc, alcgr, alcg
5464 (define_insn "*add<mode>3_alc_cc"
5465 [(set (reg CC_REGNUM)
5466 (compare
5467 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5468 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5469 (match_operand:GPR 2 "general_operand" "d,RT"))
5470 (const_int 0)))
5471 (set (match_operand:GPR 0 "register_operand" "=d,d")
5472 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5473 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5474 "@
5475 alc<g>r\t%0,%2
5476 alc<g>\t%0,%2"
5477 [(set_attr "op_type" "RRE,RXY")])
5479 ; alcr, alc, alcgr, alcg
5480 (define_insn "*add<mode>3_alc"
5481 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5482 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5483 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5484 (match_operand:GPR 2 "general_operand" "d,RT")))
5485 (clobber (reg:CC CC_REGNUM))]
5486 "TARGET_CPU_ZARCH"
5487 "@
5488 alc<g>r\t%0,%2
5489 alc<g>\t%0,%2"
5490 [(set_attr "op_type" "RRE,RXY")])
5492 ; slbr, slb, slbgr, slbg
5493 (define_insn "*sub<mode>3_slb_cc"
5494 [(set (reg CC_REGNUM)
5495 (compare
5496 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5497 (match_operand:GPR 2 "general_operand" "d,RT"))
5498 (match_operand:GPR 3 "s390_slb_comparison" ""))
5499 (const_int 0)))
5500 (set (match_operand:GPR 0 "register_operand" "=d,d")
5501 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5502 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5503 "@
5504 slb<g>r\t%0,%2
5505 slb<g>\t%0,%2"
5506 [(set_attr "op_type" "RRE,RXY")
5507 (set_attr "z10prop" "z10_c,*")])
5509 ; slbr, slb, slbgr, slbg
5510 (define_insn "*sub<mode>3_slb"
5511 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5512 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5513 (match_operand:GPR 2 "general_operand" "d,RT"))
5514 (match_operand:GPR 3 "s390_slb_comparison" "")))
5515 (clobber (reg:CC CC_REGNUM))]
5516 "TARGET_CPU_ZARCH"
5517 "@
5518 slb<g>r\t%0,%2
5519 slb<g>\t%0,%2"
5520 [(set_attr "op_type" "RRE,RXY")
5521 (set_attr "z10prop" "z10_c,*")])
5523 (define_expand "add<mode>cc"
5524 [(match_operand:GPR 0 "register_operand" "")
5525 (match_operand 1 "comparison_operator" "")
5526 (match_operand:GPR 2 "register_operand" "")
5527 (match_operand:GPR 3 "const_int_operand" "")]
5528 "TARGET_CPU_ZARCH"
5529 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5530 XEXP (operands[1], 0), XEXP (operands[1], 1),
5531 operands[0], operands[2],
5532 operands[3])) FAIL; DONE;")
5534 ;
5535 ; scond instruction pattern(s).
5536 ;
5538 (define_insn_and_split "*scond<mode>"
5539 [(set (match_operand:GPR 0 "register_operand" "=&d")
5540 (match_operand:GPR 1 "s390_alc_comparison" ""))
5541 (clobber (reg:CC CC_REGNUM))]
5542 "TARGET_CPU_ZARCH"
5543 "#"
5544 "&& reload_completed"
5545 [(set (match_dup 0) (const_int 0))
5546 (parallel
5547 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5548 (match_dup 0)))
5549 (clobber (reg:CC CC_REGNUM))])]
5550 "")
5552 (define_insn_and_split "*scond<mode>_neg"
5553 [(set (match_operand:GPR 0 "register_operand" "=&d")
5554 (match_operand:GPR 1 "s390_slb_comparison" ""))
5555 (clobber (reg:CC CC_REGNUM))]
5556 "TARGET_CPU_ZARCH"
5557 "#"
5558 "&& reload_completed"
5559 [(set (match_dup 0) (const_int 0))
5560 (parallel
5561 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5562 (match_dup 1)))
5563 (clobber (reg:CC CC_REGNUM))])
5564 (parallel
5565 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5566 (clobber (reg:CC CC_REGNUM))])]
5567 "")
5570 (define_expand "cstore<mode>4"
5571 [(set (match_operand:SI 0 "register_operand" "")
5572 (match_operator:SI 1 "s390_scond_operator"
5573 [(match_operand:GPR 2 "register_operand" "")
5574 (match_operand:GPR 3 "general_operand" "")]))]
5575 "TARGET_CPU_ZARCH"
5576 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5577 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5579 (define_expand "cstorecc4"
5580 [(parallel
5581 [(set (match_operand:SI 0 "register_operand" "")
5582 (match_operator:SI 1 "s390_eqne_operator"
5583 [(match_operand:CCZ1 2 "register_operand")
5584 (match_operand 3 "const0_operand")]))
5585 (clobber (reg:CC CC_REGNUM))])]
5586 ""
5587 "emit_insn (gen_sne (operands[0], operands[2]));
5588 if (GET_CODE (operands[1]) == EQ)
5589 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5590 DONE;")
5592 (define_insn_and_split "sne"
5593 [(set (match_operand:SI 0 "register_operand" "=d")
5594 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5595 (const_int 0)))
5596 (clobber (reg:CC CC_REGNUM))]
5597 ""
5598 "#"
5599 "reload_completed"
5600 [(parallel
5601 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5602 (clobber (reg:CC CC_REGNUM))])])
5605 ;;
5606 ;; - Conditional move instructions (introduced with z196)
5607 ;;
5609 (define_expand "mov<mode>cc"
5610 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5611 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5612 (match_operand:GPR 2 "nonimmediate_operand" "")
5613 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5614 "TARGET_Z196"
5615 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5616 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5618 ; locr, loc, stoc, locgr, locg, stocg
5619 (define_insn_and_split "*mov<mode>cc"
5620 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5621 (if_then_else:GPR
5622 (match_operator 1 "s390_comparison"
5623 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5624 (match_operand 5 "const_int_operand" "")])
5625 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5626 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5627 "TARGET_Z196"
5628 "@
5629 loc<g>r%C1\t%0,%3
5630 loc<g>r%D1\t%0,%4
5631 loc<g>%C1\t%0,%3
5632 loc<g>%D1\t%0,%4
5633 stoc<g>%C1\t%3,%0
5634 stoc<g>%D1\t%4,%0
5635 #"
5636 "&& reload_completed
5637 && MEM_P (operands[3]) && MEM_P (operands[4])"
5638 [(set (match_dup 0)
5639 (if_then_else:GPR
5640 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5641 (match_dup 3)
5642 (match_dup 0)))
5643 (set (match_dup 0)
5644 (if_then_else:GPR
5645 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5646 (match_dup 0)
5647 (match_dup 4)))]
5648 ""
5649 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5651 ;;
5652 ;;- Multiply instructions.
5653 ;;
5655 ;
5656 ; muldi3 instruction pattern(s).
5657 ;
5659 (define_insn "*muldi3_sign"
5660 [(set (match_operand:DI 0 "register_operand" "=d,d")
5661 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5662 (match_operand:DI 1 "register_operand" "0,0")))]
5663 "TARGET_ZARCH"
5664 "@
5665 msgfr\t%0,%2
5666 msgf\t%0,%2"
5667 [(set_attr "op_type" "RRE,RXY")
5668 (set_attr "type" "imuldi")])
5670 (define_insn "muldi3"
5671 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5672 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5673 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5674 "TARGET_ZARCH"
5675 "@
5676 msgr\t%0,%2
5677 mghi\t%0,%h2
5678 msg\t%0,%2
5679 msgfi\t%0,%2"
5680 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5681 (set_attr "type" "imuldi")
5682 (set_attr "cpu_facility" "*,*,*,z10")])
5684 ;
5685 ; mulsi3 instruction pattern(s).
5686 ;
5688 (define_insn "*mulsi3_sign"
5689 [(set (match_operand:SI 0 "register_operand" "=d,d")
5690 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5691 (match_operand:SI 1 "register_operand" "0,0")))]
5692 ""
5693 "@
5694 mh\t%0,%2
5695 mhy\t%0,%2"
5696 [(set_attr "op_type" "RX,RXY")
5697 (set_attr "type" "imulhi")
5698 (set_attr "cpu_facility" "*,z10")])
5700 (define_insn "mulsi3"
5701 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5702 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5703 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5704 ""
5705 "@
5706 msr\t%0,%2
5707 mhi\t%0,%h2
5708 ms\t%0,%2
5709 msy\t%0,%2
5710 msfi\t%0,%2"
5711 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5712 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5713 (set_attr "cpu_facility" "*,*,*,*,z10")])
5715 ;
5716 ; mulsidi3 instruction pattern(s).
5717 ;
5719 (define_insn "mulsidi3"
5720 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5721 (mult:DI (sign_extend:DI
5722 (match_operand:SI 1 "register_operand" "%0,0,0"))
5723 (sign_extend:DI
5724 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5725 "!TARGET_ZARCH"
5726 "@
5727 mr\t%0,%2
5728 m\t%0,%2
5729 mfy\t%0,%2"
5730 [(set_attr "op_type" "RR,RX,RXY")
5731 (set_attr "type" "imulsi")
5732 (set_attr "cpu_facility" "*,*,z10")])
5734 ;
5735 ; umul instruction pattern(s).
5736 ;
5738 ; mlr, ml, mlgr, mlg
5739 (define_insn "umul<dwh><mode>3"
5740 [(set (match_operand:DW 0 "register_operand" "=d, d")
5741 (mult:DW (zero_extend:DW
5742 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5743 (zero_extend:DW
5744 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5745 "TARGET_CPU_ZARCH"
5746 "@
5747 ml<tg>r\t%0,%2
5748 ml<tg>\t%0,%2"
5749 [(set_attr "op_type" "RRE,RXY")
5750 (set_attr "type" "imul<dwh>")])
5752 ;
5753 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5754 ;
5756 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5757 (define_insn "mul<mode>3"
5758 [(set (match_operand:FP 0 "register_operand" "=f,f")
5759 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5760 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5761 "TARGET_HARD_FLOAT"
5762 "@
5763 m<xdee><bt>r\t%0,<op1>%2
5764 m<xdee>b\t%0,%2"
5765 [(set_attr "op_type" "<RRer>,RXE")
5766 (set_attr "type" "fmul<mode>")])
5768 ; madbr, maebr, maxb, madb, maeb
5769 (define_insn "fma<mode>4"
5770 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5771 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5772 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5773 (match_operand:DSF 3 "register_operand" "0,0")))]
5774 "TARGET_HARD_FLOAT"
5775 "@
5776 ma<xde>br\t%0,%1,%2
5777 ma<xde>b\t%0,%1,%2"
5778 [(set_attr "op_type" "RRE,RXE")
5779 (set_attr "type" "fmadd<mode>")])
5781 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5782 (define_insn "fms<mode>4"
5783 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5784 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5785 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5786 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5787 "TARGET_HARD_FLOAT"
5788 "@
5789 ms<xde>br\t%0,%1,%2
5790 ms<xde>b\t%0,%1,%2"
5791 [(set_attr "op_type" "RRE,RXE")
5792 (set_attr "type" "fmadd<mode>")])
5794 ;;
5795 ;;- Divide and modulo instructions.
5796 ;;
5798 ;
5799 ; divmoddi4 instruction pattern(s).
5800 ;
5802 (define_expand "divmoddi4"
5803 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5804 (div:DI (match_operand:DI 1 "register_operand" "")
5805 (match_operand:DI 2 "general_operand" "")))
5806 (set (match_operand:DI 3 "general_operand" "")
5807 (mod:DI (match_dup 1) (match_dup 2)))])
5808 (clobber (match_dup 4))]
5809 "TARGET_ZARCH"
5810 {
5811 rtx insn, div_equal, mod_equal;
5813 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5814 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5816 operands[4] = gen_reg_rtx(TImode);
5817 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5819 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5820 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5822 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5823 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5825 DONE;
5826 })
5828 (define_insn "divmodtidi3"
5829 [(set (match_operand:TI 0 "register_operand" "=d,d")
5830 (ior:TI
5831 (ashift:TI
5832 (zero_extend:TI
5833 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5834 (match_operand:DI 2 "general_operand" "d,RT")))
5835 (const_int 64))
5836 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5837 "TARGET_ZARCH"
5838 "@
5839 dsgr\t%0,%2
5840 dsg\t%0,%2"
5841 [(set_attr "op_type" "RRE,RXY")
5842 (set_attr "type" "idiv")])
5844 (define_insn "divmodtisi3"
5845 [(set (match_operand:TI 0 "register_operand" "=d,d")
5846 (ior:TI
5847 (ashift:TI
5848 (zero_extend:TI
5849 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5850 (sign_extend:DI
5851 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5852 (const_int 64))
5853 (zero_extend:TI
5854 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5855 "TARGET_ZARCH"
5856 "@
5857 dsgfr\t%0,%2
5858 dsgf\t%0,%2"
5859 [(set_attr "op_type" "RRE,RXY")
5860 (set_attr "type" "idiv")])
5862 ;
5863 ; udivmoddi4 instruction pattern(s).
5864 ;
5866 (define_expand "udivmoddi4"
5867 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5868 (udiv:DI (match_operand:DI 1 "general_operand" "")
5869 (match_operand:DI 2 "nonimmediate_operand" "")))
5870 (set (match_operand:DI 3 "general_operand" "")
5871 (umod:DI (match_dup 1) (match_dup 2)))])
5872 (clobber (match_dup 4))]
5873 "TARGET_ZARCH"
5874 {
5875 rtx insn, div_equal, mod_equal, equal;
5877 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5878 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5879 equal = gen_rtx_IOR (TImode,
5880 gen_rtx_ASHIFT (TImode,
5881 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5882 GEN_INT (64)),
5883 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5885 operands[4] = gen_reg_rtx(TImode);
5886 emit_clobber (operands[4]);
5887 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5888 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5890 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5891 set_unique_reg_note (insn, REG_EQUAL, equal);
5893 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5894 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5896 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5897 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5899 DONE;
5900 })
5902 (define_insn "udivmodtidi3"
5903 [(set (match_operand:TI 0 "register_operand" "=d,d")
5904 (ior:TI
5905 (ashift:TI
5906 (zero_extend:TI
5907 (truncate:DI
5908 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5909 (zero_extend:TI
5910 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5911 (const_int 64))
5912 (zero_extend:TI
5913 (truncate:DI
5914 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5915 "TARGET_ZARCH"
5916 "@
5917 dlgr\t%0,%2
5918 dlg\t%0,%2"
5919 [(set_attr "op_type" "RRE,RXY")
5920 (set_attr "type" "idiv")])
5922 ;
5923 ; divmodsi4 instruction pattern(s).
5924 ;
5926 (define_expand "divmodsi4"
5927 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5928 (div:SI (match_operand:SI 1 "general_operand" "")
5929 (match_operand:SI 2 "nonimmediate_operand" "")))
5930 (set (match_operand:SI 3 "general_operand" "")
5931 (mod:SI (match_dup 1) (match_dup 2)))])
5932 (clobber (match_dup 4))]
5933 "!TARGET_ZARCH"
5934 {
5935 rtx insn, div_equal, mod_equal, equal;
5937 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5938 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5939 equal = gen_rtx_IOR (DImode,
5940 gen_rtx_ASHIFT (DImode,
5941 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5942 GEN_INT (32)),
5943 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5945 operands[4] = gen_reg_rtx(DImode);
5946 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5948 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5949 set_unique_reg_note (insn, REG_EQUAL, equal);
5951 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5952 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5954 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5955 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5957 DONE;
5958 })
5960 (define_insn "divmoddisi3"
5961 [(set (match_operand:DI 0 "register_operand" "=d,d")
5962 (ior:DI
5963 (ashift:DI
5964 (zero_extend:DI
5965 (truncate:SI
5966 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5967 (sign_extend:DI
5968 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5969 (const_int 32))
5970 (zero_extend:DI
5971 (truncate:SI
5972 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5973 "!TARGET_ZARCH"
5974 "@
5975 dr\t%0,%2
5976 d\t%0,%2"
5977 [(set_attr "op_type" "RR,RX")
5978 (set_attr "type" "idiv")])
5980 ;
5981 ; udivsi3 and umodsi3 instruction pattern(s).
5982 ;
5984 (define_expand "udivmodsi4"
5985 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5986 (udiv:SI (match_operand:SI 1 "general_operand" "")
5987 (match_operand:SI 2 "nonimmediate_operand" "")))
5988 (set (match_operand:SI 3 "general_operand" "")
5989 (umod:SI (match_dup 1) (match_dup 2)))])
5990 (clobber (match_dup 4))]
5991 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5992 {
5993 rtx insn, div_equal, mod_equal, equal;
5995 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5996 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5997 equal = gen_rtx_IOR (DImode,
5998 gen_rtx_ASHIFT (DImode,
5999 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6000 GEN_INT (32)),
6001 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6003 operands[4] = gen_reg_rtx(DImode);
6004 emit_clobber (operands[4]);
6005 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6006 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6008 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6009 set_unique_reg_note (insn, REG_EQUAL, equal);
6011 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6012 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6014 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6015 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6017 DONE;
6018 })
6020 (define_insn "udivmoddisi3"
6021 [(set (match_operand:DI 0 "register_operand" "=d,d")
6022 (ior:DI
6023 (ashift:DI
6024 (zero_extend:DI
6025 (truncate:SI
6026 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6027 (zero_extend:DI
6028 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6029 (const_int 32))
6030 (zero_extend:DI
6031 (truncate:SI
6032 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6033 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6034 "@
6035 dlr\t%0,%2
6036 dl\t%0,%2"
6037 [(set_attr "op_type" "RRE,RXY")
6038 (set_attr "type" "idiv")])
6040 (define_expand "udivsi3"
6041 [(set (match_operand:SI 0 "register_operand" "=d")
6042 (udiv:SI (match_operand:SI 1 "general_operand" "")
6043 (match_operand:SI 2 "general_operand" "")))
6044 (clobber (match_dup 3))]
6045 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6046 {
6047 rtx insn, udiv_equal, umod_equal, equal;
6049 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6050 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6051 equal = gen_rtx_IOR (DImode,
6052 gen_rtx_ASHIFT (DImode,
6053 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6054 GEN_INT (32)),
6055 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6057 operands[3] = gen_reg_rtx (DImode);
6059 if (CONSTANT_P (operands[2]))
6060 {
6061 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6062 {
6063 rtx label1 = gen_label_rtx ();
6065 operands[1] = make_safe_from (operands[1], operands[0]);
6066 emit_move_insn (operands[0], const0_rtx);
6067 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6068 SImode, 1, label1);
6069 emit_move_insn (operands[0], const1_rtx);
6070 emit_label (label1);
6071 }
6072 else
6073 {
6074 operands[2] = force_reg (SImode, operands[2]);
6075 operands[2] = make_safe_from (operands[2], operands[0]);
6077 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6078 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6079 operands[2]));
6080 set_unique_reg_note (insn, REG_EQUAL, equal);
6082 insn = emit_move_insn (operands[0],
6083 gen_lowpart (SImode, operands[3]));
6084 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6085 }
6086 }
6087 else
6088 {
6089 rtx label1 = gen_label_rtx ();
6090 rtx label2 = gen_label_rtx ();
6091 rtx label3 = gen_label_rtx ();
6093 operands[1] = force_reg (SImode, operands[1]);
6094 operands[1] = make_safe_from (operands[1], operands[0]);
6095 operands[2] = force_reg (SImode, operands[2]);
6096 operands[2] = make_safe_from (operands[2], operands[0]);
6098 emit_move_insn (operands[0], const0_rtx);
6099 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6100 SImode, 1, label3);
6101 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6102 SImode, 0, label2);
6103 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6104 SImode, 0, label1);
6105 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6106 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6107 operands[2]));
6108 set_unique_reg_note (insn, REG_EQUAL, equal);
6110 insn = emit_move_insn (operands[0],
6111 gen_lowpart (SImode, operands[3]));
6112 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6114 emit_jump (label3);
6115 emit_label (label1);
6116 emit_move_insn (operands[0], operands[1]);
6117 emit_jump (label3);
6118 emit_label (label2);
6119 emit_move_insn (operands[0], const1_rtx);
6120 emit_label (label3);
6121 }
6122 emit_move_insn (operands[0], operands[0]);
6123 DONE;
6124 })
6126 (define_expand "umodsi3"
6127 [(set (match_operand:SI 0 "register_operand" "=d")
6128 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6129 (match_operand:SI 2 "nonimmediate_operand" "")))
6130 (clobber (match_dup 3))]
6131 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6132 {
6133 rtx insn, udiv_equal, umod_equal, equal;
6135 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6136 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6137 equal = gen_rtx_IOR (DImode,
6138 gen_rtx_ASHIFT (DImode,
6139 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6140 GEN_INT (32)),
6141 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6143 operands[3] = gen_reg_rtx (DImode);
6145 if (CONSTANT_P (operands[2]))
6146 {
6147 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6148 {
6149 rtx label1 = gen_label_rtx ();
6151 operands[1] = make_safe_from (operands[1], operands[0]);
6152 emit_move_insn (operands[0], operands[1]);
6153 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6154 SImode, 1, label1);
6155 emit_insn (gen_abssi2 (operands[0], operands[2]));
6156 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6157 emit_label (label1);
6158 }
6159 else
6160 {
6161 operands[2] = force_reg (SImode, operands[2]);
6162 operands[2] = make_safe_from (operands[2], operands[0]);
6164 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6165 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6166 operands[2]));
6167 set_unique_reg_note (insn, REG_EQUAL, equal);
6169 insn = emit_move_insn (operands[0],
6170 gen_highpart (SImode, operands[3]));
6171 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6172 }
6173 }
6174 else
6175 {
6176 rtx label1 = gen_label_rtx ();
6177 rtx label2 = gen_label_rtx ();
6178 rtx label3 = gen_label_rtx ();
6180 operands[1] = force_reg (SImode, operands[1]);
6181 operands[1] = make_safe_from (operands[1], operands[0]);
6182 operands[2] = force_reg (SImode, operands[2]);
6183 operands[2] = make_safe_from (operands[2], operands[0]);
6185 emit_move_insn(operands[0], operands[1]);
6186 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6187 SImode, 1, label3);
6188 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6189 SImode, 0, label2);
6190 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6191 SImode, 0, label1);
6192 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6193 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6194 operands[2]));
6195 set_unique_reg_note (insn, REG_EQUAL, equal);
6197 insn = emit_move_insn (operands[0],
6198 gen_highpart (SImode, operands[3]));
6199 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6201 emit_jump (label3);
6202 emit_label (label1);
6203 emit_move_insn (operands[0], const0_rtx);
6204 emit_jump (label3);
6205 emit_label (label2);
6206 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6207 emit_label (label3);
6208 }
6209 DONE;
6210 })
6212 ;
6213 ; div(df|sf)3 instruction pattern(s).
6214 ;
6216 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6217 (define_insn "div<mode>3"
6218 [(set (match_operand:FP 0 "register_operand" "=f,f")
6219 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6220 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6221 "TARGET_HARD_FLOAT"
6222 "@
6223 d<xde><bt>r\t%0,<op1>%2
6224 d<xde>b\t%0,%2"
6225 [(set_attr "op_type" "<RRer>,RXE")
6226 (set_attr "type" "fdiv<mode>")])
6229 ;;
6230 ;;- And instructions.
6231 ;;
6233 (define_expand "and<mode>3"
6234 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6235 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6236 (match_operand:INT 2 "general_operand" "")))
6237 (clobber (reg:CC CC_REGNUM))]
6238 ""
6239 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6241 ;
6242 ; anddi3 instruction pattern(s).
6243 ;
6245 (define_insn "*anddi3_cc"
6246 [(set (reg CC_REGNUM)
6247 (compare
6248 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6249 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6250 (const_int 0)))
6251 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6252 (and:DI (match_dup 1) (match_dup 2)))]
6253 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6254 "@
6255 ngr\t%0,%2
6256 ngrk\t%0,%1,%2
6257 ng\t%0,%2
6258 risbg\t%0,%1,%s2,128+%e2,0"
6259 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6260 (set_attr "cpu_facility" "*,z196,*,z10")
6261 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6263 (define_insn "*anddi3_cconly"
6264 [(set (reg CC_REGNUM)
6265 (compare
6266 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6267 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6268 (const_int 0)))
6269 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6270 "TARGET_ZARCH
6271 && s390_match_ccmode(insn, CCTmode)
6272 /* Do not steal TM patterns. */
6273 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6274 "@
6275 ngr\t%0,%2
6276 ngrk\t%0,%1,%2
6277 ng\t%0,%2
6278 risbg\t%0,%1,%s2,128+%e2,0"
6279 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6280 (set_attr "cpu_facility" "*,z196,*,z10")
6281 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6283 (define_insn "*anddi3"
6284 [(set (match_operand:DI 0 "nonimmediate_operand"
6285 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6286 (and:DI
6287 (match_operand:DI 1 "nonimmediate_operand"
6288 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6289 (match_operand:DI 2 "general_operand"
6290 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6291 (clobber (reg:CC CC_REGNUM))]
6292 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6293 "@
6294 #
6295 #
6296 nihh\t%0,%j2
6297 nihl\t%0,%j2
6298 nilh\t%0,%j2
6299 nill\t%0,%j2
6300 nihf\t%0,%m2
6301 nilf\t%0,%m2
6302 ngr\t%0,%2
6303 ngrk\t%0,%1,%2
6304 ng\t%0,%2
6305 risbg\t%0,%1,%s2,128+%e2,0
6306 #
6307 #"
6308 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6309 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6310 (set_attr "z10prop" "*,
6311 *,
6312 z10_super_E1,
6313 z10_super_E1,
6314 z10_super_E1,
6315 z10_super_E1,
6316 z10_super_E1,
6317 z10_super_E1,
6318 z10_super_E1,
6319 *,
6320 z10_super_E1,
6321 z10_super_E1,
6322 *,
6323 *")])
6325 (define_split
6326 [(set (match_operand:DI 0 "s_operand" "")
6327 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6328 (clobber (reg:CC CC_REGNUM))]
6329 "reload_completed"
6330 [(parallel
6331 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6332 (clobber (reg:CC CC_REGNUM))])]
6333 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6335 ;; These two are what combine generates for (ashift (zero_extract)).
6336 (define_insn "*extzv_<mode>_srl"
6337 [(set (match_operand:GPR 0 "register_operand" "=d")
6338 (and:GPR (lshiftrt:GPR
6339 (match_operand:GPR 1 "register_operand" "d")
6340 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6341 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6342 (clobber (reg:CC CC_REGNUM))]
6343 "TARGET_Z10
6344 /* Note that even for the SImode pattern, the rotate is always DImode. */
6345 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6346 INTVAL (operands[3]))"
6347 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6348 [(set_attr "op_type" "RIE")
6349 (set_attr "z10prop" "z10_super_E1")])
6351 (define_insn "*extzv_<mode>_sll"
6352 [(set (match_operand:GPR 0 "register_operand" "=d")
6353 (and:GPR (ashift:GPR
6354 (match_operand:GPR 1 "register_operand" "d")
6355 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6356 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6357 (clobber (reg:CC CC_REGNUM))]
6358 "TARGET_Z10
6359 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6360 INTVAL (operands[3]))"
6361 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6362 [(set_attr "op_type" "RIE")
6363 (set_attr "z10prop" "z10_super_E1")])
6366 ;
6367 ; andsi3 instruction pattern(s).
6368 ;
6370 (define_insn "*andsi3_cc"
6371 [(set (reg CC_REGNUM)
6372 (compare
6373 (and:SI
6374 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6375 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6376 (const_int 0)))
6377 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6378 (and:SI (match_dup 1) (match_dup 2)))]
6379 "s390_match_ccmode(insn, CCTmode)"
6380 "@
6381 nilf\t%0,%o2
6382 nr\t%0,%2
6383 nrk\t%0,%1,%2
6384 n\t%0,%2
6385 ny\t%0,%2
6386 risbg\t%0,%1,%t2,128+%f2,0"
6387 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6388 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6389 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6390 z10_super_E1,z10_super_E1,z10_super_E1")])
6392 (define_insn "*andsi3_cconly"
6393 [(set (reg CC_REGNUM)
6394 (compare
6395 (and:SI
6396 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6397 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6398 (const_int 0)))
6399 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6400 "s390_match_ccmode(insn, CCTmode)
6401 /* Do not steal TM patterns. */
6402 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6403 "@
6404 nilf\t%0,%o2
6405 nr\t%0,%2
6406 nrk\t%0,%1,%2
6407 n\t%0,%2
6408 ny\t%0,%2
6409 risbg\t%0,%1,%t2,128+%f2,0"
6410 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6411 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6412 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6413 z10_super_E1,z10_super_E1,z10_super_E1")])
6415 (define_insn "*andsi3_zarch"
6416 [(set (match_operand:SI 0 "nonimmediate_operand"
6417 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6418 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6419 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6420 (match_operand:SI 2 "general_operand"
6421 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6422 (clobber (reg:CC CC_REGNUM))]
6423 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6424 "@
6425 #
6426 #
6427 nilh\t%0,%j2
6428 nill\t%0,%j2
6429 nilf\t%0,%o2
6430 nr\t%0,%2
6431 nrk\t%0,%1,%2
6432 n\t%0,%2
6433 ny\t%0,%2
6434 risbg\t%0,%1,%t2,128+%f2,0
6435 #
6436 #"
6437 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6438 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6439 (set_attr "z10prop" "*,
6440 *,
6441 z10_super_E1,
6442 z10_super_E1,
6443 z10_super_E1,
6444 z10_super_E1,
6445 *,
6446 z10_super_E1,
6447 z10_super_E1,
6448 z10_super_E1,
6449 *,
6450 *")])
6452 (define_insn "*andsi3_esa"
6453 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6454 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6455 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6456 (clobber (reg:CC CC_REGNUM))]
6457 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6458 "@
6459 nr\t%0,%2
6460 n\t%0,%2
6461 #
6462 #"
6463 [(set_attr "op_type" "RR,RX,SI,SS")
6464 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6467 (define_split
6468 [(set (match_operand:SI 0 "s_operand" "")
6469 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6470 (clobber (reg:CC CC_REGNUM))]
6471 "reload_completed"
6472 [(parallel
6473 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6474 (clobber (reg:CC CC_REGNUM))])]
6475 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6477 ;
6478 ; andhi3 instruction pattern(s).
6479 ;
6481 (define_insn "*andhi3_zarch"
6482 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6483 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6484 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6485 (clobber (reg:CC CC_REGNUM))]
6486 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6487 "@
6488 nr\t%0,%2
6489 nrk\t%0,%1,%2
6490 nill\t%0,%x2
6491 #
6492 #"
6493 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6494 (set_attr "cpu_facility" "*,z196,*,*,*")
6495 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6496 ])
6498 (define_insn "*andhi3_esa"
6499 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6500 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6501 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6502 (clobber (reg:CC CC_REGNUM))]
6503 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6504 "@
6505 nr\t%0,%2
6506 #
6507 #"
6508 [(set_attr "op_type" "RR,SI,SS")
6509 (set_attr "z10prop" "z10_super_E1,*,*")
6510 ])
6512 (define_split
6513 [(set (match_operand:HI 0 "s_operand" "")
6514 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6515 (clobber (reg:CC CC_REGNUM))]
6516 "reload_completed"
6517 [(parallel
6518 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6519 (clobber (reg:CC CC_REGNUM))])]
6520 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6522 ;
6523 ; andqi3 instruction pattern(s).
6524 ;
6526 (define_insn "*andqi3_zarch"
6527 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6528 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6529 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6530 (clobber (reg:CC CC_REGNUM))]
6531 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6532 "@
6533 nr\t%0,%2
6534 nrk\t%0,%1,%2
6535 nill\t%0,%b2
6536 ni\t%S0,%b2
6537 niy\t%S0,%b2
6538 #"
6539 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6540 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6541 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6543 (define_insn "*andqi3_esa"
6544 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6545 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6546 (match_operand:QI 2 "general_operand" "d,n,Q")))
6547 (clobber (reg:CC CC_REGNUM))]
6548 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6549 "@
6550 nr\t%0,%2
6551 ni\t%S0,%b2
6552 #"
6553 [(set_attr "op_type" "RR,SI,SS")
6554 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6556 ;
6557 ; Block and (NC) patterns.
6558 ;
6560 (define_insn "*nc"
6561 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6562 (and:BLK (match_dup 0)
6563 (match_operand:BLK 1 "memory_operand" "Q")))
6564 (use (match_operand 2 "const_int_operand" "n"))
6565 (clobber (reg:CC CC_REGNUM))]
6566 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6567 "nc\t%O0(%2,%R0),%S1"
6568 [(set_attr "op_type" "SS")
6569 (set_attr "z196prop" "z196_cracked")])
6571 (define_split
6572 [(set (match_operand 0 "memory_operand" "")
6573 (and (match_dup 0)
6574 (match_operand 1 "memory_operand" "")))
6575 (clobber (reg:CC CC_REGNUM))]
6576 "reload_completed
6577 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6578 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6579 [(parallel
6580 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6581 (use (match_dup 2))
6582 (clobber (reg:CC CC_REGNUM))])]
6583 {
6584 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6585 operands[0] = adjust_address (operands[0], BLKmode, 0);
6586 operands[1] = adjust_address (operands[1], BLKmode, 0);
6587 })
6589 (define_peephole2
6590 [(parallel
6591 [(set (match_operand:BLK 0 "memory_operand" "")
6592 (and:BLK (match_dup 0)
6593 (match_operand:BLK 1 "memory_operand" "")))
6594 (use (match_operand 2 "const_int_operand" ""))
6595 (clobber (reg:CC CC_REGNUM))])
6596 (parallel
6597 [(set (match_operand:BLK 3 "memory_operand" "")
6598 (and:BLK (match_dup 3)
6599 (match_operand:BLK 4 "memory_operand" "")))
6600 (use (match_operand 5 "const_int_operand" ""))
6601 (clobber (reg:CC CC_REGNUM))])]
6602 "s390_offset_p (operands[0], operands[3], operands[2])
6603 && s390_offset_p (operands[1], operands[4], operands[2])
6604 && !s390_overlap_p (operands[0], operands[1],
6605 INTVAL (operands[2]) + INTVAL (operands[5]))
6606 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6607 [(parallel
6608 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6609 (use (match_dup 8))
6610 (clobber (reg:CC CC_REGNUM))])]
6611 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6612 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6613 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6616 ;;
6617 ;;- Bit set (inclusive or) instructions.
6618 ;;
6620 (define_expand "ior<mode>3"
6621 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6622 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6623 (match_operand:INT 2 "general_operand" "")))
6624 (clobber (reg:CC CC_REGNUM))]
6625 ""
6626 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6628 ;
6629 ; iordi3 instruction pattern(s).
6630 ;
6632 (define_insn "*iordi3_cc"
6633 [(set (reg CC_REGNUM)
6634 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6635 (match_operand:DI 2 "general_operand" " d,d,RT"))
6636 (const_int 0)))
6637 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6638 (ior:DI (match_dup 1) (match_dup 2)))]
6639 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6640 "@
6641 ogr\t%0,%2
6642 ogrk\t%0,%1,%2
6643 og\t%0,%2"
6644 [(set_attr "op_type" "RRE,RRF,RXY")
6645 (set_attr "cpu_facility" "*,z196,*")
6646 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6648 (define_insn "*iordi3_cconly"
6649 [(set (reg CC_REGNUM)
6650 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6651 (match_operand:DI 2 "general_operand" " d,d,RT"))
6652 (const_int 0)))
6653 (clobber (match_scratch:DI 0 "=d,d,d"))]
6654 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6655 "@
6656 ogr\t%0,%2
6657 ogrk\t%0,%1,%2
6658 og\t%0,%2"
6659 [(set_attr "op_type" "RRE,RRF,RXY")
6660 (set_attr "cpu_facility" "*,z196,*")
6661 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6663 (define_insn "*iordi3"
6664 [(set (match_operand:DI 0 "nonimmediate_operand"
6665 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6666 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6667 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6668 (match_operand:DI 2 "general_operand"
6669 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6670 (clobber (reg:CC CC_REGNUM))]
6671 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6672 "@
6673 oihh\t%0,%i2
6674 oihl\t%0,%i2
6675 oilh\t%0,%i2
6676 oill\t%0,%i2
6677 oihf\t%0,%k2
6678 oilf\t%0,%k2
6679 ogr\t%0,%2
6680 ogrk\t%0,%1,%2
6681 og\t%0,%2
6682 #
6683 #"
6684 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6685 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6686 (set_attr "z10prop" "z10_super_E1,
6687 z10_super_E1,
6688 z10_super_E1,
6689 z10_super_E1,
6690 z10_super_E1,
6691 z10_super_E1,
6692 z10_super_E1,
6693 *,
6694 z10_super_E1,
6695 *,
6696 *")])
6698 (define_split
6699 [(set (match_operand:DI 0 "s_operand" "")
6700 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6701 (clobber (reg:CC CC_REGNUM))]
6702 "reload_completed"
6703 [(parallel
6704 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6705 (clobber (reg:CC CC_REGNUM))])]
6706 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6708 ;
6709 ; iorsi3 instruction pattern(s).
6710 ;
6712 (define_insn "*iorsi3_cc"
6713 [(set (reg CC_REGNUM)
6714 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6715 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6716 (const_int 0)))
6717 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6718 (ior:SI (match_dup 1) (match_dup 2)))]
6719 "s390_match_ccmode(insn, CCTmode)"
6720 "@
6721 oilf\t%0,%o2
6722 or\t%0,%2
6723 ork\t%0,%1,%2
6724 o\t%0,%2
6725 oy\t%0,%2"
6726 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6727 (set_attr "cpu_facility" "*,*,z196,*,*")
6728 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6730 (define_insn "*iorsi3_cconly"
6731 [(set (reg CC_REGNUM)
6732 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6733 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6734 (const_int 0)))
6735 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6736 "s390_match_ccmode(insn, CCTmode)"
6737 "@
6738 oilf\t%0,%o2
6739 or\t%0,%2
6740 ork\t%0,%1,%2
6741 o\t%0,%2
6742 oy\t%0,%2"
6743 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6744 (set_attr "cpu_facility" "*,*,z196,*,*")
6745 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6747 (define_insn "*iorsi3_zarch"
6748 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6749 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6750 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6751 (clobber (reg:CC CC_REGNUM))]
6752 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6753 "@
6754 oilh\t%0,%i2
6755 oill\t%0,%i2
6756 oilf\t%0,%o2
6757 or\t%0,%2
6758 ork\t%0,%1,%2
6759 o\t%0,%2
6760 oy\t%0,%2
6761 #
6762 #"
6763 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6764 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6765 (set_attr "z10prop" "z10_super_E1,
6766 z10_super_E1,
6767 z10_super_E1,
6768 z10_super_E1,
6769 *,
6770 z10_super_E1,
6771 z10_super_E1,
6772 *,
6773 *")])
6775 (define_insn "*iorsi3_esa"
6776 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6777 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6778 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6779 (clobber (reg:CC CC_REGNUM))]
6780 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6781 "@
6782 or\t%0,%2
6783 o\t%0,%2
6784 #
6785 #"
6786 [(set_attr "op_type" "RR,RX,SI,SS")
6787 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6789 (define_split
6790 [(set (match_operand:SI 0 "s_operand" "")
6791 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6792 (clobber (reg:CC CC_REGNUM))]
6793 "reload_completed"
6794 [(parallel
6795 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6796 (clobber (reg:CC CC_REGNUM))])]
6797 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6799 ;
6800 ; iorhi3 instruction pattern(s).
6801 ;
6803 (define_insn "*iorhi3_zarch"
6804 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6805 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6806 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6807 (clobber (reg:CC CC_REGNUM))]
6808 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6809 "@
6810 or\t%0,%2
6811 ork\t%0,%1,%2
6812 oill\t%0,%x2
6813 #
6814 #"
6815 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6816 (set_attr "cpu_facility" "*,z196,*,*,*")
6817 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6819 (define_insn "*iorhi3_esa"
6820 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6821 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6822 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6823 (clobber (reg:CC CC_REGNUM))]
6824 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6825 "@
6826 or\t%0,%2
6827 #
6828 #"
6829 [(set_attr "op_type" "RR,SI,SS")
6830 (set_attr "z10prop" "z10_super_E1,*,*")])
6832 (define_split
6833 [(set (match_operand:HI 0 "s_operand" "")
6834 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6835 (clobber (reg:CC CC_REGNUM))]
6836 "reload_completed"
6837 [(parallel
6838 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6839 (clobber (reg:CC CC_REGNUM))])]
6840 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6842 ;
6843 ; iorqi3 instruction pattern(s).
6844 ;
6846 (define_insn "*iorqi3_zarch"
6847 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6848 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6849 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6850 (clobber (reg:CC CC_REGNUM))]
6851 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6852 "@
6853 or\t%0,%2
6854 ork\t%0,%1,%2
6855 oill\t%0,%b2
6856 oi\t%S0,%b2
6857 oiy\t%S0,%b2
6858 #"
6859 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6860 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6861 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6862 z10_super,z10_super,*")])
6864 (define_insn "*iorqi3_esa"
6865 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6866 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6867 (match_operand:QI 2 "general_operand" "d,n,Q")))
6868 (clobber (reg:CC CC_REGNUM))]
6869 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6870 "@
6871 or\t%0,%2
6872 oi\t%S0,%b2
6873 #"
6874 [(set_attr "op_type" "RR,SI,SS")
6875 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6877 ;
6878 ; Block inclusive or (OC) patterns.
6879 ;
6881 (define_insn "*oc"
6882 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6883 (ior:BLK (match_dup 0)
6884 (match_operand:BLK 1 "memory_operand" "Q")))
6885 (use (match_operand 2 "const_int_operand" "n"))
6886 (clobber (reg:CC CC_REGNUM))]
6887 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6888 "oc\t%O0(%2,%R0),%S1"
6889 [(set_attr "op_type" "SS")
6890 (set_attr "z196prop" "z196_cracked")])
6892 (define_split
6893 [(set (match_operand 0 "memory_operand" "")
6894 (ior (match_dup 0)
6895 (match_operand 1 "memory_operand" "")))
6896 (clobber (reg:CC CC_REGNUM))]
6897 "reload_completed
6898 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6899 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6900 [(parallel
6901 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6902 (use (match_dup 2))
6903 (clobber (reg:CC CC_REGNUM))])]
6904 {
6905 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6906 operands[0] = adjust_address (operands[0], BLKmode, 0);
6907 operands[1] = adjust_address (operands[1], BLKmode, 0);
6908 })
6910 (define_peephole2
6911 [(parallel
6912 [(set (match_operand:BLK 0 "memory_operand" "")
6913 (ior:BLK (match_dup 0)
6914 (match_operand:BLK 1 "memory_operand" "")))
6915 (use (match_operand 2 "const_int_operand" ""))
6916 (clobber (reg:CC CC_REGNUM))])
6917 (parallel
6918 [(set (match_operand:BLK 3 "memory_operand" "")
6919 (ior:BLK (match_dup 3)
6920 (match_operand:BLK 4 "memory_operand" "")))
6921 (use (match_operand 5 "const_int_operand" ""))
6922 (clobber (reg:CC CC_REGNUM))])]
6923 "s390_offset_p (operands[0], operands[3], operands[2])
6924 && s390_offset_p (operands[1], operands[4], operands[2])
6925 && !s390_overlap_p (operands[0], operands[1],
6926 INTVAL (operands[2]) + INTVAL (operands[5]))
6927 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6928 [(parallel
6929 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6930 (use (match_dup 8))
6931 (clobber (reg:CC CC_REGNUM))])]
6932 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6933 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6934 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6937 ;;
6938 ;;- Xor instructions.
6939 ;;
6941 (define_expand "xor<mode>3"
6942 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6943 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6944 (match_operand:INT 2 "general_operand" "")))
6945 (clobber (reg:CC CC_REGNUM))]
6946 ""
6947 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6949 ;
6950 ; xordi3 instruction pattern(s).
6951 ;
6953 (define_insn "*xordi3_cc"
6954 [(set (reg CC_REGNUM)
6955 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6956 (match_operand:DI 2 "general_operand" " d,d,RT"))
6957 (const_int 0)))
6958 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6959 (xor:DI (match_dup 1) (match_dup 2)))]
6960 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6961 "@
6962 xgr\t%0,%2
6963 xgrk\t%0,%1,%2
6964 xg\t%0,%2"
6965 [(set_attr "op_type" "RRE,RRF,RXY")
6966 (set_attr "cpu_facility" "*,z196,*")
6967 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6969 (define_insn "*xordi3_cconly"
6970 [(set (reg CC_REGNUM)
6971 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6972 (match_operand:DI 2 "general_operand" " d,d,RT"))
6973 (const_int 0)))
6974 (clobber (match_scratch:DI 0 "=d,d, d"))]
6975 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6976 "@
6977 xgr\t%0,%2
6978 xgrk\t%0,%1,%2
6979 xg\t%0,%2"
6980 [(set_attr "op_type" "RRE,RRF,RXY")
6981 (set_attr "cpu_facility" "*,z196,*")
6982 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6984 (define_insn "*xordi3"
6985 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6986 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6987 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6988 (clobber (reg:CC CC_REGNUM))]
6989 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6990 "@
6991 xihf\t%0,%k2
6992 xilf\t%0,%k2
6993 xgr\t%0,%2
6994 xgrk\t%0,%1,%2
6995 xg\t%0,%2
6996 #
6997 #"
6998 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6999 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7000 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7001 *,z10_super_E1,*,*")])
7003 (define_split
7004 [(set (match_operand:DI 0 "s_operand" "")
7005 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7006 (clobber (reg:CC CC_REGNUM))]
7007 "reload_completed"
7008 [(parallel
7009 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7010 (clobber (reg:CC CC_REGNUM))])]
7011 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7013 ;
7014 ; xorsi3 instruction pattern(s).
7015 ;
7017 (define_insn "*xorsi3_cc"
7018 [(set (reg CC_REGNUM)
7019 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7020 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7021 (const_int 0)))
7022 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7023 (xor:SI (match_dup 1) (match_dup 2)))]
7024 "s390_match_ccmode(insn, CCTmode)"
7025 "@
7026 xilf\t%0,%o2
7027 xr\t%0,%2
7028 xrk\t%0,%1,%2
7029 x\t%0,%2
7030 xy\t%0,%2"
7031 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7032 (set_attr "cpu_facility" "*,*,z196,*,*")
7033 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7034 z10_super_E1,z10_super_E1")])
7036 (define_insn "*xorsi3_cconly"
7037 [(set (reg CC_REGNUM)
7038 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7039 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7040 (const_int 0)))
7041 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7042 "s390_match_ccmode(insn, CCTmode)"
7043 "@
7044 xilf\t%0,%o2
7045 xr\t%0,%2
7046 xrk\t%0,%1,%2
7047 x\t%0,%2
7048 xy\t%0,%2"
7049 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7050 (set_attr "cpu_facility" "*,*,z196,*,*")
7051 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7052 z10_super_E1,z10_super_E1")])
7054 (define_insn "*xorsi3"
7055 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7056 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7057 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7058 (clobber (reg:CC CC_REGNUM))]
7059 "s390_logical_operator_ok_p (operands)"
7060 "@
7061 xilf\t%0,%o2
7062 xr\t%0,%2
7063 xrk\t%0,%1,%2
7064 x\t%0,%2
7065 xy\t%0,%2
7066 #
7067 #"
7068 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7069 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7070 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7071 z10_super_E1,z10_super_E1,*,*")])
7073 (define_split
7074 [(set (match_operand:SI 0 "s_operand" "")
7075 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7076 (clobber (reg:CC CC_REGNUM))]
7077 "reload_completed"
7078 [(parallel
7079 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7080 (clobber (reg:CC CC_REGNUM))])]
7081 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7083 ;
7084 ; xorhi3 instruction pattern(s).
7085 ;
7087 (define_insn "*xorhi3"
7088 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7089 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7090 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7091 (clobber (reg:CC CC_REGNUM))]
7092 "s390_logical_operator_ok_p (operands)"
7093 "@
7094 xilf\t%0,%x2
7095 xr\t%0,%2
7096 xrk\t%0,%1,%2
7097 #
7098 #"
7099 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7100 (set_attr "cpu_facility" "*,*,z196,*,*")
7101 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7103 (define_split
7104 [(set (match_operand:HI 0 "s_operand" "")
7105 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7106 (clobber (reg:CC CC_REGNUM))]
7107 "reload_completed"
7108 [(parallel
7109 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7110 (clobber (reg:CC CC_REGNUM))])]
7111 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7113 ;
7114 ; xorqi3 instruction pattern(s).
7115 ;
7117 (define_insn "*xorqi3"
7118 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7119 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7120 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7121 (clobber (reg:CC CC_REGNUM))]
7122 "s390_logical_operator_ok_p (operands)"
7123 "@
7124 xilf\t%0,%b2
7125 xr\t%0,%2
7126 xrk\t%0,%1,%2
7127 xi\t%S0,%b2
7128 xiy\t%S0,%b2
7129 #"
7130 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7131 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7132 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7135 ;
7136 ; Block exclusive or (XC) patterns.
7137 ;
7139 (define_insn "*xc"
7140 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7141 (xor:BLK (match_dup 0)
7142 (match_operand:BLK 1 "memory_operand" "Q")))
7143 (use (match_operand 2 "const_int_operand" "n"))
7144 (clobber (reg:CC CC_REGNUM))]
7145 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7146 "xc\t%O0(%2,%R0),%S1"
7147 [(set_attr "op_type" "SS")])
7149 (define_split
7150 [(set (match_operand 0 "memory_operand" "")
7151 (xor (match_dup 0)
7152 (match_operand 1 "memory_operand" "")))
7153 (clobber (reg:CC CC_REGNUM))]
7154 "reload_completed
7155 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7156 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7157 [(parallel
7158 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7159 (use (match_dup 2))
7160 (clobber (reg:CC CC_REGNUM))])]
7161 {
7162 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7163 operands[0] = adjust_address (operands[0], BLKmode, 0);
7164 operands[1] = adjust_address (operands[1], BLKmode, 0);
7165 })
7167 (define_peephole2
7168 [(parallel
7169 [(set (match_operand:BLK 0 "memory_operand" "")
7170 (xor:BLK (match_dup 0)
7171 (match_operand:BLK 1 "memory_operand" "")))
7172 (use (match_operand 2 "const_int_operand" ""))
7173 (clobber (reg:CC CC_REGNUM))])
7174 (parallel
7175 [(set (match_operand:BLK 3 "memory_operand" "")
7176 (xor:BLK (match_dup 3)
7177 (match_operand:BLK 4 "memory_operand" "")))
7178 (use (match_operand 5 "const_int_operand" ""))
7179 (clobber (reg:CC CC_REGNUM))])]
7180 "s390_offset_p (operands[0], operands[3], operands[2])
7181 && s390_offset_p (operands[1], operands[4], operands[2])
7182 && !s390_overlap_p (operands[0], operands[1],
7183 INTVAL (operands[2]) + INTVAL (operands[5]))
7184 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7185 [(parallel
7186 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7187 (use (match_dup 8))
7188 (clobber (reg:CC CC_REGNUM))])]
7189 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7190 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7191 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7193 ;
7194 ; Block xor (XC) patterns with src == dest.
7195 ;
7197 (define_insn "*xc_zero"
7198 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7199 (const_int 0))
7200 (use (match_operand 1 "const_int_operand" "n"))
7201 (clobber (reg:CC CC_REGNUM))]
7202 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7203 "xc\t%O0(%1,%R0),%S0"
7204 [(set_attr "op_type" "SS")
7205 (set_attr "z196prop" "z196_cracked")])
7207 (define_peephole2
7208 [(parallel
7209 [(set (match_operand:BLK 0 "memory_operand" "")
7210 (const_int 0))
7211 (use (match_operand 1 "const_int_operand" ""))
7212 (clobber (reg:CC CC_REGNUM))])
7213 (parallel
7214 [(set (match_operand:BLK 2 "memory_operand" "")
7215 (const_int 0))
7216 (use (match_operand 3 "const_int_operand" ""))
7217 (clobber (reg:CC CC_REGNUM))])]
7218 "s390_offset_p (operands[0], operands[2], operands[1])
7219 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7220 [(parallel
7221 [(set (match_dup 4) (const_int 0))
7222 (use (match_dup 5))
7223 (clobber (reg:CC CC_REGNUM))])]
7224 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7225 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7228 ;;
7229 ;;- Negate instructions.
7230 ;;
7232 ;
7233 ; neg(di|si)2 instruction pattern(s).
7234 ;
7236 (define_expand "neg<mode>2"
7237 [(parallel
7238 [(set (match_operand:DSI 0 "register_operand" "=d")
7239 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7240 (clobber (reg:CC CC_REGNUM))])]
7241 ""
7242 "")
7244 (define_insn "*negdi2_sign_cc"
7245 [(set (reg CC_REGNUM)
7246 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7247 (match_operand:SI 1 "register_operand" "d") 0)
7248 (const_int 32)) (const_int 32)))
7249 (const_int 0)))
7250 (set (match_operand:DI 0 "register_operand" "=d")
7251 (neg:DI (sign_extend:DI (match_dup 1))))]
7252 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7253 "lcgfr\t%0,%1"
7254 [(set_attr "op_type" "RRE")
7255 (set_attr "z10prop" "z10_c")])
7257 (define_insn "*negdi2_sign"
7258 [(set (match_operand:DI 0 "register_operand" "=d")
7259 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7260 (clobber (reg:CC CC_REGNUM))]
7261 "TARGET_ZARCH"
7262 "lcgfr\t%0,%1"
7263 [(set_attr "op_type" "RRE")
7264 (set_attr "z10prop" "z10_c")])
7266 ; lcr, lcgr
7267 (define_insn "*neg<mode>2_cc"
7268 [(set (reg CC_REGNUM)
7269 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7270 (const_int 0)))
7271 (set (match_operand:GPR 0 "register_operand" "=d")
7272 (neg:GPR (match_dup 1)))]
7273 "s390_match_ccmode (insn, CCAmode)"
7274 "lc<g>r\t%0,%1"
7275 [(set_attr "op_type" "RR<E>")
7276 (set_attr "z10prop" "z10_super_c_E1")])
7278 ; lcr, lcgr
7279 (define_insn "*neg<mode>2_cconly"
7280 [(set (reg CC_REGNUM)
7281 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7282 (const_int 0)))
7283 (clobber (match_scratch:GPR 0 "=d"))]
7284 "s390_match_ccmode (insn, CCAmode)"
7285 "lc<g>r\t%0,%1"
7286 [(set_attr "op_type" "RR<E>")
7287 (set_attr "z10prop" "z10_super_c_E1")])
7289 ; lcr, lcgr
7290 (define_insn "*neg<mode>2"
7291 [(set (match_operand:GPR 0 "register_operand" "=d")
7292 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7293 (clobber (reg:CC CC_REGNUM))]
7294 ""
7295 "lc<g>r\t%0,%1"
7296 [(set_attr "op_type" "RR<E>")
7297 (set_attr "z10prop" "z10_super_c_E1")])
7299 (define_insn_and_split "*negdi2_31"
7300 [(set (match_operand:DI 0 "register_operand" "=d")
7301 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7302 (clobber (reg:CC CC_REGNUM))]
7303 "!TARGET_ZARCH"
7304 "#"
7305 "&& reload_completed"
7306 [(parallel
7307 [(set (match_dup 2) (neg:SI (match_dup 3)))
7308 (clobber (reg:CC CC_REGNUM))])
7309 (parallel
7310 [(set (reg:CCAP CC_REGNUM)
7311 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7312 (set (match_dup 4) (neg:SI (match_dup 5)))])
7313 (set (pc)
7314 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7315 (pc)
7316 (label_ref (match_dup 6))))
7317 (parallel
7318 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7319 (clobber (reg:CC CC_REGNUM))])
7320 (match_dup 6)]
7321 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7322 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7323 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7324 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7325 operands[6] = gen_label_rtx ();")
7327 ;
7328 ; neg(df|sf)2 instruction pattern(s).
7329 ;
7331 (define_expand "neg<mode>2"
7332 [(parallel
7333 [(set (match_operand:BFP 0 "register_operand" "=f")
7334 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7335 (clobber (reg:CC CC_REGNUM))])]
7336 "TARGET_HARD_FLOAT"
7337 "")
7339 ; lcxbr, lcdbr, lcebr
7340 (define_insn "*neg<mode>2_cc"
7341 [(set (reg CC_REGNUM)
7342 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7343 (match_operand:BFP 2 "const0_operand" "")))
7344 (set (match_operand:BFP 0 "register_operand" "=f")
7345 (neg:BFP (match_dup 1)))]
7346 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7347 "lc<xde>br\t%0,%1"
7348 [(set_attr "op_type" "RRE")
7349 (set_attr "type" "fsimp<mode>")])
7351 ; lcxbr, lcdbr, lcebr
7352 (define_insn "*neg<mode>2_cconly"
7353 [(set (reg CC_REGNUM)
7354 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7355 (match_operand:BFP 2 "const0_operand" "")))
7356 (clobber (match_scratch:BFP 0 "=f"))]
7357 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7358 "lc<xde>br\t%0,%1"
7359 [(set_attr "op_type" "RRE")
7360 (set_attr "type" "fsimp<mode>")])
7362 ; lcdfr
7363 (define_insn "*neg<mode>2_nocc"
7364 [(set (match_operand:FP 0 "register_operand" "=f")
7365 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7366 "TARGET_DFP"
7367 "lcdfr\t%0,%1"
7368 [(set_attr "op_type" "RRE")
7369 (set_attr "type" "fsimp<mode>")])
7371 ; lcxbr, lcdbr, lcebr
7372 (define_insn "*neg<mode>2"
7373 [(set (match_operand:BFP 0 "register_operand" "=f")
7374 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7375 (clobber (reg:CC CC_REGNUM))]
7376 "TARGET_HARD_FLOAT"
7377 "lc<xde>br\t%0,%1"
7378 [(set_attr "op_type" "RRE")
7379 (set_attr "type" "fsimp<mode>")])
7382 ;;
7383 ;;- Absolute value instructions.
7384 ;;
7386 ;
7387 ; abs(di|si)2 instruction pattern(s).
7388 ;
7390 (define_insn "*absdi2_sign_cc"
7391 [(set (reg CC_REGNUM)
7392 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7393 (match_operand:SI 1 "register_operand" "d") 0)
7394 (const_int 32)) (const_int 32)))
7395 (const_int 0)))
7396 (set (match_operand:DI 0 "register_operand" "=d")
7397 (abs:DI (sign_extend:DI (match_dup 1))))]
7398 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7399 "lpgfr\t%0,%1"
7400 [(set_attr "op_type" "RRE")
7401 (set_attr "z10prop" "z10_c")])
7403 (define_insn "*absdi2_sign"
7404 [(set (match_operand:DI 0 "register_operand" "=d")
7405 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7406 (clobber (reg:CC CC_REGNUM))]
7407 "TARGET_ZARCH"
7408 "lpgfr\t%0,%1"
7409 [(set_attr "op_type" "RRE")
7410 (set_attr "z10prop" "z10_c")])
7412 ; lpr, lpgr
7413 (define_insn "*abs<mode>2_cc"
7414 [(set (reg CC_REGNUM)
7415 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7416 (const_int 0)))
7417 (set (match_operand:GPR 0 "register_operand" "=d")
7418 (abs:GPR (match_dup 1)))]
7419 "s390_match_ccmode (insn, CCAmode)"
7420 "lp<g>r\t%0,%1"
7421 [(set_attr "op_type" "RR<E>")
7422 (set_attr "z10prop" "z10_c")])
7424 ; lpr, lpgr
7425 (define_insn "*abs<mode>2_cconly"
7426 [(set (reg CC_REGNUM)
7427 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7428 (const_int 0)))
7429 (clobber (match_scratch:GPR 0 "=d"))]
7430 "s390_match_ccmode (insn, CCAmode)"
7431 "lp<g>r\t%0,%1"
7432 [(set_attr "op_type" "RR<E>")
7433 (set_attr "z10prop" "z10_c")])
7435 ; lpr, lpgr
7436 (define_insn "abs<mode>2"
7437 [(set (match_operand:GPR 0 "register_operand" "=d")
7438 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7439 (clobber (reg:CC CC_REGNUM))]
7440 ""
7441 "lp<g>r\t%0,%1"
7442 [(set_attr "op_type" "RR<E>")
7443 (set_attr "z10prop" "z10_c")])
7445 ;
7446 ; abs(df|sf)2 instruction pattern(s).
7447 ;
7449 (define_expand "abs<mode>2"
7450 [(parallel
7451 [(set (match_operand:BFP 0 "register_operand" "=f")
7452 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7453 (clobber (reg:CC CC_REGNUM))])]
7454 "TARGET_HARD_FLOAT"
7455 "")
7457 ; lpxbr, lpdbr, lpebr
7458 (define_insn "*abs<mode>2_cc"
7459 [(set (reg CC_REGNUM)
7460 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7461 (match_operand:BFP 2 "const0_operand" "")))
7462 (set (match_operand:BFP 0 "register_operand" "=f")
7463 (abs:BFP (match_dup 1)))]
7464 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7465 "lp<xde>br\t%0,%1"
7466 [(set_attr "op_type" "RRE")
7467 (set_attr "type" "fsimp<mode>")])
7469 ; lpxbr, lpdbr, lpebr
7470 (define_insn "*abs<mode>2_cconly"
7471 [(set (reg CC_REGNUM)
7472 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7473 (match_operand:BFP 2 "const0_operand" "")))
7474 (clobber (match_scratch:BFP 0 "=f"))]
7475 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7476 "lp<xde>br\t%0,%1"
7477 [(set_attr "op_type" "RRE")
7478 (set_attr "type" "fsimp<mode>")])
7480 ; lpdfr
7481 (define_insn "*abs<mode>2_nocc"
7482 [(set (match_operand:FP 0 "register_operand" "=f")
7483 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7484 "TARGET_DFP"
7485 "lpdfr\t%0,%1"
7486 [(set_attr "op_type" "RRE")
7487 (set_attr "type" "fsimp<mode>")])
7489 ; lpxbr, lpdbr, lpebr
7490 (define_insn "*abs<mode>2"
7491 [(set (match_operand:BFP 0 "register_operand" "=f")
7492 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7493 (clobber (reg:CC CC_REGNUM))]
7494 "TARGET_HARD_FLOAT"
7495 "lp<xde>br\t%0,%1"
7496 [(set_attr "op_type" "RRE")
7497 (set_attr "type" "fsimp<mode>")])
7500 ;;
7501 ;;- Negated absolute value instructions
7502 ;;
7504 ;
7505 ; Integer
7506 ;
7508 (define_insn "*negabsdi2_sign_cc"
7509 [(set (reg CC_REGNUM)
7510 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7511 (match_operand:SI 1 "register_operand" "d") 0)
7512 (const_int 32)) (const_int 32))))
7513 (const_int 0)))
7514 (set (match_operand:DI 0 "register_operand" "=d")
7515 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7516 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7517 "lngfr\t%0,%1"
7518 [(set_attr "op_type" "RRE")
7519 (set_attr "z10prop" "z10_c")])
7521 (define_insn "*negabsdi2_sign"
7522 [(set (match_operand:DI 0 "register_operand" "=d")
7523 (neg:DI (abs:DI (sign_extend:DI
7524 (match_operand:SI 1 "register_operand" "d")))))
7525 (clobber (reg:CC CC_REGNUM))]
7526 "TARGET_ZARCH"
7527 "lngfr\t%0,%1"
7528 [(set_attr "op_type" "RRE")
7529 (set_attr "z10prop" "z10_c")])
7531 ; lnr, lngr
7532 (define_insn "*negabs<mode>2_cc"
7533 [(set (reg CC_REGNUM)
7534 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7535 (const_int 0)))
7536 (set (match_operand:GPR 0 "register_operand" "=d")
7537 (neg:GPR (abs:GPR (match_dup 1))))]
7538 "s390_match_ccmode (insn, CCAmode)"
7539 "ln<g>r\t%0,%1"
7540 [(set_attr "op_type" "RR<E>")
7541 (set_attr "z10prop" "z10_c")])
7543 ; lnr, lngr
7544 (define_insn "*negabs<mode>2_cconly"
7545 [(set (reg CC_REGNUM)
7546 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7547 (const_int 0)))
7548 (clobber (match_scratch:GPR 0 "=d"))]
7549 "s390_match_ccmode (insn, CCAmode)"
7550 "ln<g>r\t%0,%1"
7551 [(set_attr "op_type" "RR<E>")
7552 (set_attr "z10prop" "z10_c")])
7554 ; lnr, lngr
7555 (define_insn "*negabs<mode>2"
7556 [(set (match_operand:GPR 0 "register_operand" "=d")
7557 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7558 (clobber (reg:CC CC_REGNUM))]
7559 ""
7560 "ln<g>r\t%0,%1"
7561 [(set_attr "op_type" "RR<E>")
7562 (set_attr "z10prop" "z10_c")])
7564 ;
7565 ; Floating point
7566 ;
7568 ; lnxbr, lndbr, lnebr
7569 (define_insn "*negabs<mode>2_cc"
7570 [(set (reg CC_REGNUM)
7571 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7572 (match_operand:BFP 2 "const0_operand" "")))
7573 (set (match_operand:BFP 0 "register_operand" "=f")
7574 (neg:BFP (abs:BFP (match_dup 1))))]
7575 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7576 "ln<xde>br\t%0,%1"
7577 [(set_attr "op_type" "RRE")
7578 (set_attr "type" "fsimp<mode>")])
7580 ; lnxbr, lndbr, lnebr
7581 (define_insn "*negabs<mode>2_cconly"
7582 [(set (reg CC_REGNUM)
7583 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7584 (match_operand:BFP 2 "const0_operand" "")))
7585 (clobber (match_scratch:BFP 0 "=f"))]
7586 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7587 "ln<xde>br\t%0,%1"
7588 [(set_attr "op_type" "RRE")
7589 (set_attr "type" "fsimp<mode>")])
7591 ; lndfr
7592 (define_insn "*negabs<mode>2_nocc"
7593 [(set (match_operand:FP 0 "register_operand" "=f")
7594 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7595 "TARGET_DFP"
7596 "lndfr\t%0,%1"
7597 [(set_attr "op_type" "RRE")
7598 (set_attr "type" "fsimp<mode>")])
7600 ; lnxbr, lndbr, lnebr
7601 (define_insn "*negabs<mode>2"
7602 [(set (match_operand:BFP 0 "register_operand" "=f")
7603 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7604 (clobber (reg:CC CC_REGNUM))]
7605 "TARGET_HARD_FLOAT"
7606 "ln<xde>br\t%0,%1"
7607 [(set_attr "op_type" "RRE")
7608 (set_attr "type" "fsimp<mode>")])
7610 ;;
7611 ;;- Square root instructions.
7612 ;;
7614 ;
7615 ; sqrt(df|sf)2 instruction pattern(s).
7616 ;
7618 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7619 (define_insn "sqrt<mode>2"
7620 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7621 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7622 "TARGET_HARD_FLOAT"
7623 "@
7624 sq<xde>br\t%0,%1
7625 sq<xde>b\t%0,%1"
7626 [(set_attr "op_type" "RRE,RXE")
7627 (set_attr "type" "fsqrt<mode>")])
7630 ;;
7631 ;;- One complement instructions.
7632 ;;
7634 ;
7635 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7636 ;
7638 (define_expand "one_cmpl<mode>2"
7639 [(parallel
7640 [(set (match_operand:INT 0 "register_operand" "")
7641 (xor:INT (match_operand:INT 1 "register_operand" "")
7642 (const_int -1)))
7643 (clobber (reg:CC CC_REGNUM))])]
7644 ""
7645 "")
7648 ;;
7649 ;; Find leftmost bit instructions.
7650 ;;
7652 (define_expand "clzdi2"
7653 [(set (match_operand:DI 0 "register_operand" "=d")
7654 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7655 "TARGET_EXTIMM && TARGET_ZARCH"
7656 {
7657 rtx insn, clz_equal;
7658 rtx wide_reg = gen_reg_rtx (TImode);
7659 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7661 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7663 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7665 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7666 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7668 DONE;
7669 })
7671 (define_insn "clztidi2"
7672 [(set (match_operand:TI 0 "register_operand" "=d")
7673 (ior:TI
7674 (ashift:TI
7675 (zero_extend:TI
7676 (xor:DI (match_operand:DI 1 "register_operand" "d")
7677 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7678 (subreg:SI (clz:DI (match_dup 1)) 4))))
7680 (const_int 64))
7681 (zero_extend:TI (clz:DI (match_dup 1)))))
7682 (clobber (reg:CC CC_REGNUM))]
7683 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7684 == (unsigned HOST_WIDE_INT) 1 << 63
7685 && TARGET_EXTIMM && TARGET_ZARCH"
7686 "flogr\t%0,%1"
7687 [(set_attr "op_type" "RRE")])
7690 ;;
7691 ;;- Rotate instructions.
7692 ;;
7694 ;
7695 ; rotl(di|si)3 instruction pattern(s).
7696 ;
7698 ; rll, rllg
7699 (define_insn "rotl<mode>3"
7700 [(set (match_operand:GPR 0 "register_operand" "=d")
7701 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7702 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7703 "TARGET_CPU_ZARCH"
7704 "rll<g>\t%0,%1,%Y2"
7705 [(set_attr "op_type" "RSE")
7706 (set_attr "atype" "reg")
7707 (set_attr "z10prop" "z10_super_E1")])
7709 ; rll, rllg
7710 (define_insn "*rotl<mode>3_and"
7711 [(set (match_operand:GPR 0 "register_operand" "=d")
7712 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7713 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7714 (match_operand:SI 3 "const_int_operand" "n"))))]
7715 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7716 "rll<g>\t%0,%1,%Y2"
7717 [(set_attr "op_type" "RSE")
7718 (set_attr "atype" "reg")
7719 (set_attr "z10prop" "z10_super_E1")])
7722 ;;
7723 ;;- Shift instructions.
7724 ;;
7726 ;
7727 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7728 ; Left shifts and logical right shifts
7730 (define_expand "<shift><mode>3"
7731 [(set (match_operand:DSI 0 "register_operand" "")
7732 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7733 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7734 ""
7735 "")
7737 ; sldl, srdl
7738 (define_insn "*<shift>di3_31"
7739 [(set (match_operand:DI 0 "register_operand" "=d")
7740 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7741 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7742 "!TARGET_ZARCH"
7743 "s<lr>dl\t%0,%Y2"
7744 [(set_attr "op_type" "RS")
7745 (set_attr "atype" "reg")
7746 (set_attr "z196prop" "z196_cracked")])
7748 ; sll, srl, sllg, srlg, sllk, srlk
7749 (define_insn "*<shift><mode>3"
7750 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7751 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7752 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7753 ""
7754 "@
7755 s<lr>l<g>\t%0,<1>%Y2
7756 s<lr>l<gk>\t%0,%1,%Y2"
7757 [(set_attr "op_type" "RS<E>,RSY")
7758 (set_attr "atype" "reg,reg")
7759 (set_attr "cpu_facility" "*,z196")
7760 (set_attr "z10prop" "z10_super_E1,*")])
7762 ; sldl, srdl
7763 (define_insn "*<shift>di3_31_and"
7764 [(set (match_operand:DI 0 "register_operand" "=d")
7765 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7766 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7767 (match_operand:SI 3 "const_int_operand" "n"))))]
7768 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7769 "s<lr>dl\t%0,%Y2"
7770 [(set_attr "op_type" "RS")
7771 (set_attr "atype" "reg")])
7773 ; sll, srl, sllg, srlg, sllk, srlk
7774 (define_insn "*<shift><mode>3_and"
7775 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7776 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7777 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7778 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7779 "(INTVAL (operands[3]) & 63) == 63"
7780 "@
7781 s<lr>l<g>\t%0,<1>%Y2
7782 s<lr>l<gk>\t%0,%1,%Y2"
7783 [(set_attr "op_type" "RS<E>,RSY")
7784 (set_attr "atype" "reg,reg")
7785 (set_attr "cpu_facility" "*,z196")
7786 (set_attr "z10prop" "z10_super_E1,*")])
7788 ;
7789 ; ashr(di|si)3 instruction pattern(s).
7790 ; Arithmetic right shifts
7792 (define_expand "ashr<mode>3"
7793 [(parallel
7794 [(set (match_operand:DSI 0 "register_operand" "")
7795 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7796 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7797 (clobber (reg:CC CC_REGNUM))])]
7798 ""
7799 "")
7801 (define_insn "*ashrdi3_cc_31"
7802 [(set (reg CC_REGNUM)
7803 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7804 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7805 (const_int 0)))
7806 (set (match_operand:DI 0 "register_operand" "=d")
7807 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7808 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7809 "srda\t%0,%Y2"
7810 [(set_attr "op_type" "RS")
7811 (set_attr "atype" "reg")])
7813 (define_insn "*ashrdi3_cconly_31"
7814 [(set (reg CC_REGNUM)
7815 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7816 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7817 (const_int 0)))
7818 (clobber (match_scratch:DI 0 "=d"))]
7819 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7820 "srda\t%0,%Y2"
7821 [(set_attr "op_type" "RS")
7822 (set_attr "atype" "reg")])
7824 (define_insn "*ashrdi3_31"
7825 [(set (match_operand:DI 0 "register_operand" "=d")
7826 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7827 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7828 (clobber (reg:CC CC_REGNUM))]
7829 "!TARGET_ZARCH"
7830 "srda\t%0,%Y2"
7831 [(set_attr "op_type" "RS")
7832 (set_attr "atype" "reg")])
7834 ; sra, srag, srak
7835 (define_insn "*ashr<mode>3_cc"
7836 [(set (reg CC_REGNUM)
7837 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7838 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7839 (const_int 0)))
7840 (set (match_operand:GPR 0 "register_operand" "=d,d")
7841 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7842 "s390_match_ccmode(insn, CCSmode)"
7843 "@
7844 sra<g>\t%0,<1>%Y2
7845 sra<gk>\t%0,%1,%Y2"
7846 [(set_attr "op_type" "RS<E>,RSY")
7847 (set_attr "atype" "reg,reg")
7848 (set_attr "cpu_facility" "*,z196")
7849 (set_attr "z10prop" "z10_super_E1,*")])
7851 ; sra, srag, srak
7852 (define_insn "*ashr<mode>3_cconly"
7853 [(set (reg CC_REGNUM)
7854 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7855 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7856 (const_int 0)))
7857 (clobber (match_scratch:GPR 0 "=d,d"))]
7858 "s390_match_ccmode(insn, CCSmode)"
7859 "@
7860 sra<g>\t%0,<1>%Y2
7861 sra<gk>\t%0,%1,%Y2"
7862 [(set_attr "op_type" "RS<E>,RSY")
7863 (set_attr "atype" "reg,reg")
7864 (set_attr "cpu_facility" "*,z196")
7865 (set_attr "z10prop" "z10_super_E1,*")])
7867 ; sra, srag
7868 (define_insn "*ashr<mode>3"
7869 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7870 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7871 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7872 (clobber (reg:CC CC_REGNUM))]
7873 ""
7874 "@
7875 sra<g>\t%0,<1>%Y2
7876 sra<gk>\t%0,%1,%Y2"
7877 [(set_attr "op_type" "RS<E>,RSY")
7878 (set_attr "atype" "reg,reg")
7879 (set_attr "cpu_facility" "*,z196")
7880 (set_attr "z10prop" "z10_super_E1,*")])
7883 ; shift pattern with implicit ANDs
7885 (define_insn "*ashrdi3_cc_31_and"
7886 [(set (reg CC_REGNUM)
7887 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7888 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7889 (match_operand:SI 3 "const_int_operand" "n")))
7890 (const_int 0)))
7891 (set (match_operand:DI 0 "register_operand" "=d")
7892 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7893 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7894 && (INTVAL (operands[3]) & 63) == 63"
7895 "srda\t%0,%Y2"
7896 [(set_attr "op_type" "RS")
7897 (set_attr "atype" "reg")])
7899 (define_insn "*ashrdi3_cconly_31_and"
7900 [(set (reg CC_REGNUM)
7901 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7902 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7903 (match_operand:SI 3 "const_int_operand" "n")))
7904 (const_int 0)))
7905 (clobber (match_scratch:DI 0 "=d"))]
7906 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7907 && (INTVAL (operands[3]) & 63) == 63"
7908 "srda\t%0,%Y2"
7909 [(set_attr "op_type" "RS")
7910 (set_attr "atype" "reg")])
7912 (define_insn "*ashrdi3_31_and"
7913 [(set (match_operand:DI 0 "register_operand" "=d")
7914 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7915 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7916 (match_operand:SI 3 "const_int_operand" "n"))))
7917 (clobber (reg:CC CC_REGNUM))]
7918 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7919 "srda\t%0,%Y2"
7920 [(set_attr "op_type" "RS")
7921 (set_attr "atype" "reg")])
7923 ; sra, srag, srak
7924 (define_insn "*ashr<mode>3_cc_and"
7925 [(set (reg CC_REGNUM)
7926 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7927 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7928 (match_operand:SI 3 "const_int_operand" "n,n")))
7929 (const_int 0)))
7930 (set (match_operand:GPR 0 "register_operand" "=d,d")
7931 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7932 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7933 "@
7934 sra<g>\t%0,<1>%Y2
7935 sra<gk>\t%0,%1,%Y2"
7936 [(set_attr "op_type" "RS<E>,RSY")
7937 (set_attr "atype" "reg,reg")
7938 (set_attr "cpu_facility" "*,z196")
7939 (set_attr "z10prop" "z10_super_E1,*")])
7941 ; sra, srag, srak
7942 (define_insn "*ashr<mode>3_cconly_and"
7943 [(set (reg CC_REGNUM)
7944 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7945 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7946 (match_operand:SI 3 "const_int_operand" "n,n")))
7947 (const_int 0)))
7948 (clobber (match_scratch:GPR 0 "=d,d"))]
7949 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7950 "@
7951 sra<g>\t%0,<1>%Y2
7952 sra<gk>\t%0,%1,%Y2"
7953 [(set_attr "op_type" "RS<E>,RSY")
7954 (set_attr "atype" "reg,reg")
7955 (set_attr "cpu_facility" "*,z196")
7956 (set_attr "z10prop" "z10_super_E1,*")])
7958 ; sra, srag, srak
7959 (define_insn "*ashr<mode>3_and"
7960 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7961 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7962 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7963 (match_operand:SI 3 "const_int_operand" "n,n"))))
7964 (clobber (reg:CC CC_REGNUM))]
7965 "(INTVAL (operands[3]) & 63) == 63"
7966 "@
7967 sra<g>\t%0,<1>%Y2
7968 sra<gk>\t%0,%1,%Y2"
7969 [(set_attr "op_type" "RS<E>,RSY")
7970 (set_attr "atype" "reg,reg")
7971 (set_attr "cpu_facility" "*,z196")
7972 (set_attr "z10prop" "z10_super_E1,*")])
7975 ;;
7976 ;; Branch instruction patterns.
7977 ;;
7979 (define_expand "cbranch<mode>4"
7980 [(set (pc)
7981 (if_then_else (match_operator 0 "comparison_operator"
7982 [(match_operand:GPR 1 "register_operand" "")
7983 (match_operand:GPR 2 "general_operand" "")])
7984 (label_ref (match_operand 3 "" ""))
7985 (pc)))]
7986 ""
7987 "s390_emit_jump (operands[3],
7988 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7989 DONE;")
7991 (define_expand "cbranch<mode>4"
7992 [(set (pc)
7993 (if_then_else (match_operator 0 "comparison_operator"
7994 [(match_operand:FP 1 "register_operand" "")
7995 (match_operand:FP 2 "general_operand" "")])
7996 (label_ref (match_operand 3 "" ""))
7997 (pc)))]
7998 "TARGET_HARD_FLOAT"
7999 "s390_emit_jump (operands[3],
8000 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8001 DONE;")
8003 (define_expand "cbranchcc4"
8004 [(set (pc)
8005 (if_then_else (match_operator 0 "s390_eqne_operator"
8006 [(match_operand 1 "cc_reg_operand" "")
8007 (match_operand 2 "const0_operand" "")])
8008 (label_ref (match_operand 3 "" ""))
8009 (pc)))]
8010 "TARGET_HARD_FLOAT"
8011 "s390_emit_jump (operands[3],
8012 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8013 DONE;")
8017 ;;
8018 ;;- Conditional jump instructions.
8019 ;;
8021 (define_insn "*cjump_64"
8022 [(set (pc)
8023 (if_then_else
8024 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8025 (match_operand 2 "const_int_operand" "")])
8026 (label_ref (match_operand 0 "" ""))
8027 (pc)))]
8028 "TARGET_CPU_ZARCH"
8029 {
8030 if (get_attr_length (insn) == 4)
8031 return "j%C1\t%l0";
8032 else
8033 return "jg%C1\t%l0";
8034 }
8035 [(set_attr "op_type" "RI")
8036 (set_attr "type" "branch")
8037 (set (attr "length")
8038 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8039 (const_int 4) (const_int 6)))])
8041 (define_insn "*cjump_31"
8042 [(set (pc)
8043 (if_then_else
8044 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8045 (match_operand 2 "const_int_operand" "")])
8046 (label_ref (match_operand 0 "" ""))
8047 (pc)))]
8048 "!TARGET_CPU_ZARCH"
8049 {
8050 gcc_assert (get_attr_length (insn) == 4);
8051 return "j%C1\t%l0";
8052 }
8053 [(set_attr "op_type" "RI")
8054 (set_attr "type" "branch")
8055 (set (attr "length")
8056 (if_then_else (not (match_test "flag_pic"))
8057 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8058 (const_int 4) (const_int 6))
8059 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8060 (const_int 4) (const_int 8))))])
8062 (define_insn "*cjump_long"
8063 [(set (pc)
8064 (if_then_else
8065 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8066 (match_operand 0 "address_operand" "ZQZR")
8067 (pc)))]
8068 ""
8069 {
8070 if (get_attr_op_type (insn) == OP_TYPE_RR)
8071 return "b%C1r\t%0";
8072 else
8073 return "b%C1\t%a0";
8074 }
8075 [(set (attr "op_type")
8076 (if_then_else (match_operand 0 "register_operand" "")
8077 (const_string "RR") (const_string "RX")))
8078 (set_attr "type" "branch")
8079 (set_attr "atype" "agen")])
8082 ;;
8083 ;;- Negated conditional jump instructions.
8084 ;;
8086 (define_insn "*icjump_64"
8087 [(set (pc)
8088 (if_then_else
8089 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8090 (pc)
8091 (label_ref (match_operand 0 "" ""))))]
8092 "TARGET_CPU_ZARCH"
8093 {
8094 if (get_attr_length (insn) == 4)
8095 return "j%D1\t%l0";
8096 else
8097 return "jg%D1\t%l0";
8098 }
8099 [(set_attr "op_type" "RI")
8100 (set_attr "type" "branch")
8101 (set (attr "length")
8102 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8103 (const_int 4) (const_int 6)))])
8105 (define_insn "*icjump_31"
8106 [(set (pc)
8107 (if_then_else
8108 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8109 (pc)
8110 (label_ref (match_operand 0 "" ""))))]
8111 "!TARGET_CPU_ZARCH"
8112 {
8113 gcc_assert (get_attr_length (insn) == 4);
8114 return "j%D1\t%l0";
8115 }
8116 [(set_attr "op_type" "RI")
8117 (set_attr "type" "branch")
8118 (set (attr "length")
8119 (if_then_else (not (match_test "flag_pic"))
8120 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8121 (const_int 4) (const_int 6))
8122 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8123 (const_int 4) (const_int 8))))])
8125 (define_insn "*icjump_long"
8126 [(set (pc)
8127 (if_then_else
8128 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8129 (pc)
8130 (match_operand 0 "address_operand" "ZQZR")))]
8131 ""
8132 {
8133 if (get_attr_op_type (insn) == OP_TYPE_RR)
8134 return "b%D1r\t%0";
8135 else
8136 return "b%D1\t%a0";
8137 }
8138 [(set (attr "op_type")
8139 (if_then_else (match_operand 0 "register_operand" "")
8140 (const_string "RR") (const_string "RX")))
8141 (set_attr "type" "branch")
8142 (set_attr "atype" "agen")])
8144 ;;
8145 ;;- Trap instructions.
8146 ;;
8148 (define_insn "trap"
8149 [(trap_if (const_int 1) (const_int 0))]
8150 ""
8151 "j\t.+2"
8152 [(set_attr "op_type" "RI")
8153 (set_attr "type" "branch")])
8155 (define_expand "ctrap<mode>4"
8156 [(trap_if (match_operator 0 "comparison_operator"
8157 [(match_operand:GPR 1 "register_operand" "")
8158 (match_operand:GPR 2 "general_operand" "")])
8159 (match_operand 3 "const0_operand" ""))]
8160 ""
8161 {
8162 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8163 operands[1], operands[2]);
8164 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8165 DONE;
8166 })
8168 (define_expand "ctrap<mode>4"
8169 [(trap_if (match_operator 0 "comparison_operator"
8170 [(match_operand:FP 1 "register_operand" "")
8171 (match_operand:FP 2 "general_operand" "")])
8172 (match_operand 3 "const0_operand" ""))]
8173 ""
8174 {
8175 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8176 operands[1], operands[2]);
8177 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8178 DONE;
8179 })
8181 (define_insn "condtrap"
8182 [(trap_if (match_operator 0 "s390_comparison"
8183 [(match_operand 1 "cc_reg_operand" "c")
8184 (const_int 0)])
8185 (const_int 0))]
8186 ""
8187 "j%C0\t.+2";
8188 [(set_attr "op_type" "RI")
8189 (set_attr "type" "branch")])
8191 ; crt, cgrt, cit, cgit
8192 (define_insn "*cmp_and_trap_signed_int<mode>"
8193 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8194 [(match_operand:GPR 1 "register_operand" "d,d")
8195 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8196 (const_int 0))]
8197 "TARGET_Z10"
8198 "@
8199 c<g>rt%C0\t%1,%2
8200 c<g>it%C0\t%1,%h2"
8201 [(set_attr "op_type" "RRF,RIE")
8202 (set_attr "type" "branch")
8203 (set_attr "z10prop" "z10_super_c,z10_super")])
8205 ; clrt, clgrt, clfit, clgit, clt, clgt
8206 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8207 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8208 [(match_operand:GPR 1 "register_operand" "d,d, d")
8209 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8210 (const_int 0))]
8211 "TARGET_Z10"
8212 "@
8213 cl<g>rt%C0\t%1,%2
8214 cl<gf>it%C0\t%1,%x2
8215 cl<g>t%C0\t%1,%2"
8216 [(set_attr "op_type" "RRF,RIE,RSY")
8217 (set_attr "type" "branch")
8218 (set_attr "z10prop" "z10_super_c,z10_super,*")
8219 (set_attr "cpu_facility" "z10,z10,zEC12")])
8221 ; lat, lgat
8222 (define_insn "*load_and_trap<mode>"
8223 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8224 (const_int 0))
8225 (const_int 0))
8226 (set (match_operand:GPR 1 "register_operand" "=d")
8227 (match_dup 0))]
8228 "TARGET_ZEC12"
8229 "l<g>at\t%1,%0"
8230 [(set_attr "op_type" "RXY")])
8233 ;;
8234 ;;- Loop instructions.
8235 ;;
8236 ;; This is all complicated by the fact that since this is a jump insn
8237 ;; we must handle our own output reloads.
8239 ;; branch on index
8241 ; This splitter will be matched by combine and has to add the 2 moves
8242 ; necessary to load the compare and the increment values into a
8243 ; register pair as needed by brxle.
8245 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8246 [(set (pc)
8247 (if_then_else
8248 (match_operator 6 "s390_brx_operator"
8249 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8250 (match_operand:GPR 2 "general_operand" ""))
8251 (match_operand:GPR 3 "register_operand" "")])
8252 (label_ref (match_operand 0 "" ""))
8253 (pc)))
8254 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8255 (plus:GPR (match_dup 1) (match_dup 2)))
8256 (clobber (match_scratch:GPR 5 ""))]
8257 "TARGET_CPU_ZARCH"
8258 "#"
8259 "!reload_completed && !reload_in_progress"
8260 [(set (match_dup 7) (match_dup 2)) ; the increment
8261 (set (match_dup 8) (match_dup 3)) ; the comparison value
8262 (parallel [(set (pc)
8263 (if_then_else
8264 (match_op_dup 6
8265 [(plus:GPR (match_dup 1) (match_dup 7))
8266 (match_dup 8)])
8267 (label_ref (match_dup 0))
8268 (pc)))
8269 (set (match_dup 4)
8270 (plus:GPR (match_dup 1) (match_dup 7)))
8271 (clobber (match_dup 5))
8272 (clobber (reg:CC CC_REGNUM))])]
8273 {
8274 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8275 operands[7] = gen_lowpart (<GPR:MODE>mode,
8276 gen_highpart (word_mode, dreg));
8277 operands[8] = gen_lowpart (<GPR:MODE>mode,
8278 gen_lowpart (word_mode, dreg));
8279 })
8281 ; brxlg, brxhg
8283 (define_insn_and_split "*brxg_64bit"
8284 [(set (pc)
8285 (if_then_else
8286 (match_operator 5 "s390_brx_operator"
8287 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8288 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8289 (subreg:DI (match_dup 2) 8)])
8290 (label_ref (match_operand 0 "" ""))
8291 (pc)))
8292 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8293 (plus:DI (match_dup 1)
8294 (subreg:DI (match_dup 2) 0)))
8295 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8296 (clobber (reg:CC CC_REGNUM))]
8297 "TARGET_ZARCH"
8298 {
8299 if (which_alternative != 0)
8300 return "#";
8301 else if (get_attr_length (insn) == 6)
8302 return "brx%E5g\t%1,%2,%l0";
8303 else
8304 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8305 }
8306 "&& reload_completed
8307 && (!REG_P (operands[3])
8308 || !rtx_equal_p (operands[1], operands[3]))"
8309 [(set (match_dup 4) (match_dup 1))
8310 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8311 (clobber (reg:CC CC_REGNUM))])
8312 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8313 (set (match_dup 3) (match_dup 4))
8314 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8315 (label_ref (match_dup 0))
8316 (pc)))]
8317 ""
8318 [(set_attr "op_type" "RIE")
8319 (set_attr "type" "branch")
8320 (set (attr "length")
8321 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8322 (const_int 6) (const_int 16)))])
8324 ; brxle, brxh
8326 (define_insn_and_split "*brx_64bit"
8327 [(set (pc)
8328 (if_then_else
8329 (match_operator 5 "s390_brx_operator"
8330 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8331 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8332 (subreg:SI (match_dup 2) 12)])
8333 (label_ref (match_operand 0 "" ""))
8334 (pc)))
8335 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8336 (plus:SI (match_dup 1)
8337 (subreg:SI (match_dup 2) 4)))
8338 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8339 (clobber (reg:CC CC_REGNUM))]
8340 "TARGET_ZARCH"
8341 {
8342 if (which_alternative != 0)
8343 return "#";
8344 else if (get_attr_length (insn) == 6)
8345 return "brx%C5\t%1,%2,%l0";
8346 else
8347 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8348 }
8349 "&& reload_completed
8350 && (!REG_P (operands[3])
8351 || !rtx_equal_p (operands[1], operands[3]))"
8352 [(set (match_dup 4) (match_dup 1))
8353 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8354 (clobber (reg:CC CC_REGNUM))])
8355 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8356 (set (match_dup 3) (match_dup 4))
8357 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8358 (label_ref (match_dup 0))
8359 (pc)))]
8360 ""
8361 [(set_attr "op_type" "RSI")
8362 (set_attr "type" "branch")
8363 (set (attr "length")
8364 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8365 (const_int 6) (const_int 14)))])
8367 ; brxle, brxh
8369 (define_insn_and_split "*brx_31bit"
8370 [(set (pc)
8371 (if_then_else
8372 (match_operator 5 "s390_brx_operator"
8373 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8374 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8375 (subreg:SI (match_dup 2) 4)])
8376 (label_ref (match_operand 0 "" ""))
8377 (pc)))
8378 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8379 (plus:SI (match_dup 1)
8380 (subreg:SI (match_dup 2) 0)))
8381 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8382 (clobber (reg:CC CC_REGNUM))]
8383 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8384 {
8385 if (which_alternative != 0)
8386 return "#";
8387 else if (get_attr_length (insn) == 6)
8388 return "brx%C5\t%1,%2,%l0";
8389 else
8390 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8391 }
8392 "&& reload_completed
8393 && (!REG_P (operands[3])
8394 || !rtx_equal_p (operands[1], operands[3]))"
8395 [(set (match_dup 4) (match_dup 1))
8396 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8397 (clobber (reg:CC CC_REGNUM))])
8398 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8399 (set (match_dup 3) (match_dup 4))
8400 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8401 (label_ref (match_dup 0))
8402 (pc)))]
8403 ""
8404 [(set_attr "op_type" "RSI")
8405 (set_attr "type" "branch")
8406 (set (attr "length")
8407 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8408 (const_int 6) (const_int 14)))])
8411 ;; branch on count
8413 (define_expand "doloop_end"
8414 [(use (match_operand 0 "" "")) ; loop pseudo
8415 (use (match_operand 1 "" ""))] ; label
8416 ""
8417 {
8418 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8419 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8420 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8421 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8422 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8423 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8424 else
8425 FAIL;
8427 DONE;
8428 })
8430 (define_insn_and_split "doloop_si64"
8431 [(set (pc)
8432 (if_then_else
8433 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8434 (const_int 1))
8435 (label_ref (match_operand 0 "" ""))
8436 (pc)))
8437 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8438 (plus:SI (match_dup 1) (const_int -1)))
8439 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8440 (clobber (reg:CC CC_REGNUM))]
8441 "TARGET_CPU_ZARCH"
8442 {
8443 if (which_alternative != 0)
8444 return "#";
8445 else if (get_attr_length (insn) == 4)
8446 return "brct\t%1,%l0";
8447 else
8448 return "ahi\t%1,-1\;jgne\t%l0";
8449 }
8450 "&& reload_completed
8451 && (! REG_P (operands[2])
8452 || ! rtx_equal_p (operands[1], operands[2]))"
8453 [(set (match_dup 3) (match_dup 1))
8454 (parallel [(set (reg:CCAN CC_REGNUM)
8455 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8456 (const_int 0)))
8457 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8458 (set (match_dup 2) (match_dup 3))
8459 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8460 (label_ref (match_dup 0))
8461 (pc)))]
8462 ""
8463 [(set_attr "op_type" "RI")
8464 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8465 ; hurt us in the (rare) case of ahi.
8466 (set_attr "z10prop" "z10_super_E1")
8467 (set_attr "type" "branch")
8468 (set (attr "length")
8469 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8470 (const_int 4) (const_int 10)))])
8472 (define_insn_and_split "doloop_si31"
8473 [(set (pc)
8474 (if_then_else
8475 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8476 (const_int 1))
8477 (label_ref (match_operand 0 "" ""))
8478 (pc)))
8479 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8480 (plus:SI (match_dup 1) (const_int -1)))
8481 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8482 (clobber (reg:CC CC_REGNUM))]
8483 "!TARGET_CPU_ZARCH"
8484 {
8485 if (which_alternative != 0)
8486 return "#";
8487 else if (get_attr_length (insn) == 4)
8488 return "brct\t%1,%l0";
8489 else
8490 gcc_unreachable ();
8491 }
8492 "&& reload_completed
8493 && (! REG_P (operands[2])
8494 || ! rtx_equal_p (operands[1], operands[2]))"
8495 [(set (match_dup 3) (match_dup 1))
8496 (parallel [(set (reg:CCAN CC_REGNUM)
8497 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8498 (const_int 0)))
8499 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8500 (set (match_dup 2) (match_dup 3))
8501 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8502 (label_ref (match_dup 0))
8503 (pc)))]
8504 ""
8505 [(set_attr "op_type" "RI")
8506 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8507 ; hurt us in the (rare) case of ahi.
8508 (set_attr "z10prop" "z10_super_E1")
8509 (set_attr "type" "branch")
8510 (set (attr "length")
8511 (if_then_else (not (match_test "flag_pic"))
8512 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8513 (const_int 4) (const_int 6))
8514 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8515 (const_int 4) (const_int 8))))])
8517 (define_insn "*doloop_si_long"
8518 [(set (pc)
8519 (if_then_else
8520 (ne (match_operand:SI 1 "register_operand" "d")
8521 (const_int 1))
8522 (match_operand 0 "address_operand" "ZQZR")
8523 (pc)))
8524 (set (match_operand:SI 2 "register_operand" "=1")
8525 (plus:SI (match_dup 1) (const_int -1)))
8526 (clobber (match_scratch:SI 3 "=X"))
8527 (clobber (reg:CC CC_REGNUM))]
8528 "!TARGET_CPU_ZARCH"
8529 {
8530 if (get_attr_op_type (insn) == OP_TYPE_RR)
8531 return "bctr\t%1,%0";
8532 else
8533 return "bct\t%1,%a0";
8534 }
8535 [(set (attr "op_type")
8536 (if_then_else (match_operand 0 "register_operand" "")
8537 (const_string "RR") (const_string "RX")))
8538 (set_attr "type" "branch")
8539 (set_attr "atype" "agen")
8540 (set_attr "z10prop" "z10_c")
8541 (set_attr "z196prop" "z196_cracked")])
8543 (define_insn_and_split "doloop_di"
8544 [(set (pc)
8545 (if_then_else
8546 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8547 (const_int 1))
8548 (label_ref (match_operand 0 "" ""))
8549 (pc)))
8550 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8551 (plus:DI (match_dup 1) (const_int -1)))
8552 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8553 (clobber (reg:CC CC_REGNUM))]
8554 "TARGET_ZARCH"
8555 {
8556 if (which_alternative != 0)
8557 return "#";
8558 else if (get_attr_length (insn) == 4)
8559 return "brctg\t%1,%l0";
8560 else
8561 return "aghi\t%1,-1\;jgne\t%l0";
8562 }
8563 "&& reload_completed
8564 && (! REG_P (operands[2])
8565 || ! rtx_equal_p (operands[1], operands[2]))"
8566 [(set (match_dup 3) (match_dup 1))
8567 (parallel [(set (reg:CCAN CC_REGNUM)
8568 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8569 (const_int 0)))
8570 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8571 (set (match_dup 2) (match_dup 3))
8572 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8573 (label_ref (match_dup 0))
8574 (pc)))]
8575 ""
8576 [(set_attr "op_type" "RI")
8577 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8578 ; hurt us in the (rare) case of ahi.
8579 (set_attr "z10prop" "z10_super_E1")
8580 (set_attr "type" "branch")
8581 (set (attr "length")
8582 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8583 (const_int 4) (const_int 10)))])
8585 ;;
8586 ;;- Unconditional jump instructions.
8587 ;;
8589 ;
8590 ; jump instruction pattern(s).
8591 ;
8593 (define_expand "jump"
8594 [(match_operand 0 "" "")]
8595 ""
8596 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8598 (define_insn "*jump64"
8599 [(set (pc) (label_ref (match_operand 0 "" "")))]
8600 "TARGET_CPU_ZARCH"
8601 {
8602 if (get_attr_length (insn) == 4)
8603 return "j\t%l0";
8604 else
8605 return "jg\t%l0";
8606 }
8607 [(set_attr "op_type" "RI")
8608 (set_attr "type" "branch")
8609 (set (attr "length")
8610 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8611 (const_int 4) (const_int 6)))])
8613 (define_insn "*jump31"
8614 [(set (pc) (label_ref (match_operand 0 "" "")))]
8615 "!TARGET_CPU_ZARCH"
8616 {
8617 gcc_assert (get_attr_length (insn) == 4);
8618 return "j\t%l0";
8619 }
8620 [(set_attr "op_type" "RI")
8621 (set_attr "type" "branch")
8622 (set (attr "length")
8623 (if_then_else (not (match_test "flag_pic"))
8624 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8625 (const_int 4) (const_int 6))
8626 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8627 (const_int 4) (const_int 8))))])
8629 ;
8630 ; indirect-jump instruction pattern(s).
8631 ;
8633 (define_insn "indirect_jump"
8634 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8635 ""
8636 {
8637 if (get_attr_op_type (insn) == OP_TYPE_RR)
8638 return "br\t%0";
8639 else
8640 return "b\t%a0";
8641 }
8642 [(set (attr "op_type")
8643 (if_then_else (match_operand 0 "register_operand" "")
8644 (const_string "RR") (const_string "RX")))
8645 (set_attr "type" "branch")
8646 (set_attr "atype" "agen")])
8648 ;
8649 ; casesi instruction pattern(s).
8650 ;
8652 (define_insn "casesi_jump"
8653 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8654 (use (label_ref (match_operand 1 "" "")))]
8655 ""
8656 {
8657 if (get_attr_op_type (insn) == OP_TYPE_RR)
8658 return "br\t%0";
8659 else
8660 return "b\t%a0";
8661 }
8662 [(set (attr "op_type")
8663 (if_then_else (match_operand 0 "register_operand" "")
8664 (const_string "RR") (const_string "RX")))
8665 (set_attr "type" "branch")
8666 (set_attr "atype" "agen")])
8668 (define_expand "casesi"
8669 [(match_operand:SI 0 "general_operand" "")
8670 (match_operand:SI 1 "general_operand" "")
8671 (match_operand:SI 2 "general_operand" "")
8672 (label_ref (match_operand 3 "" ""))
8673 (label_ref (match_operand 4 "" ""))]
8674 ""
8675 {
8676 rtx index = gen_reg_rtx (SImode);
8677 rtx base = gen_reg_rtx (Pmode);
8678 rtx target = gen_reg_rtx (Pmode);
8680 emit_move_insn (index, operands[0]);
8681 emit_insn (gen_subsi3 (index, index, operands[1]));
8682 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8683 operands[4]);
8685 if (Pmode != SImode)
8686 index = convert_to_mode (Pmode, index, 1);
8687 if (GET_CODE (index) != REG)
8688 index = copy_to_mode_reg (Pmode, index);
8690 if (TARGET_64BIT)
8691 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8692 else
8693 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8695 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8697 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8698 emit_move_insn (target, index);
8700 if (flag_pic)
8701 target = gen_rtx_PLUS (Pmode, base, target);
8702 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8704 DONE;
8705 })
8708 ;;
8709 ;;- Jump to subroutine.
8710 ;;
8711 ;;
8713 ;
8714 ; untyped call instruction pattern(s).
8715 ;
8717 ;; Call subroutine returning any type.
8718 (define_expand "untyped_call"
8719 [(parallel [(call (match_operand 0 "" "")
8720 (const_int 0))
8721 (match_operand 1 "" "")
8722 (match_operand 2 "" "")])]
8723 ""
8724 {
8725 int i;
8727 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8729 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8730 {
8731 rtx set = XVECEXP (operands[2], 0, i);
8732 emit_move_insn (SET_DEST (set), SET_SRC (set));
8733 }
8735 /* The optimizer does not know that the call sets the function value
8736 registers we stored in the result block. We avoid problems by
8737 claiming that all hard registers are used and clobbered at this
8738 point. */
8739 emit_insn (gen_blockage ());
8741 DONE;
8742 })
8744 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8745 ;; all of memory. This blocks insns from being moved across this point.
8747 (define_insn "blockage"
8748 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8749 ""
8750 ""
8751 [(set_attr "type" "none")
8752 (set_attr "length" "0")])
8754 ;
8755 ; sibcall patterns
8756 ;
8758 (define_expand "sibcall"
8759 [(call (match_operand 0 "" "")
8760 (match_operand 1 "" ""))]
8761 ""
8762 {
8763 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8764 DONE;
8765 })
8767 (define_insn "*sibcall_br"
8768 [(call (mem:QI (reg SIBCALL_REGNUM))
8769 (match_operand 0 "const_int_operand" "n"))]
8770 "SIBLING_CALL_P (insn)
8771 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8772 "br\t%%r1"
8773 [(set_attr "op_type" "RR")
8774 (set_attr "type" "branch")
8775 (set_attr "atype" "agen")])
8777 (define_insn "*sibcall_brc"
8778 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8779 (match_operand 1 "const_int_operand" "n"))]
8780 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8781 "j\t%0"
8782 [(set_attr "op_type" "RI")
8783 (set_attr "type" "branch")])
8785 (define_insn "*sibcall_brcl"
8786 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8787 (match_operand 1 "const_int_operand" "n"))]
8788 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8789 "jg\t%0"
8790 [(set_attr "op_type" "RIL")
8791 (set_attr "type" "branch")])
8793 ;
8794 ; sibcall_value patterns
8795 ;
8797 (define_expand "sibcall_value"
8798 [(set (match_operand 0 "" "")
8799 (call (match_operand 1 "" "")
8800 (match_operand 2 "" "")))]
8801 ""
8802 {
8803 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8804 DONE;
8805 })
8807 (define_insn "*sibcall_value_br"
8808 [(set (match_operand 0 "" "")
8809 (call (mem:QI (reg SIBCALL_REGNUM))
8810 (match_operand 1 "const_int_operand" "n")))]
8811 "SIBLING_CALL_P (insn)
8812 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8813 "br\t%%r1"
8814 [(set_attr "op_type" "RR")
8815 (set_attr "type" "branch")
8816 (set_attr "atype" "agen")])
8818 (define_insn "*sibcall_value_brc"
8819 [(set (match_operand 0 "" "")
8820 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8821 (match_operand 2 "const_int_operand" "n")))]
8822 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8823 "j\t%1"
8824 [(set_attr "op_type" "RI")
8825 (set_attr "type" "branch")])
8827 (define_insn "*sibcall_value_brcl"
8828 [(set (match_operand 0 "" "")
8829 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8830 (match_operand 2 "const_int_operand" "n")))]
8831 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8832 "jg\t%1"
8833 [(set_attr "op_type" "RIL")
8834 (set_attr "type" "branch")])
8837 ;
8838 ; call instruction pattern(s).
8839 ;
8841 (define_expand "call"
8842 [(call (match_operand 0 "" "")
8843 (match_operand 1 "" ""))
8844 (use (match_operand 2 "" ""))]
8845 ""
8846 {
8847 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8848 gen_rtx_REG (Pmode, RETURN_REGNUM));
8849 DONE;
8850 })
8852 (define_insn "*bras"
8853 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8854 (match_operand 1 "const_int_operand" "n"))
8855 (clobber (match_operand 2 "register_operand" "=r"))]
8856 "!SIBLING_CALL_P (insn)
8857 && TARGET_SMALL_EXEC
8858 && GET_MODE (operands[2]) == Pmode"
8859 "bras\t%2,%0"
8860 [(set_attr "op_type" "RI")
8861 (set_attr "type" "jsr")
8862 (set_attr "z196prop" "z196_cracked")])
8864 (define_insn "*brasl"
8865 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8866 (match_operand 1 "const_int_operand" "n"))
8867 (clobber (match_operand 2 "register_operand" "=r"))]
8868 "!SIBLING_CALL_P (insn)
8869 && TARGET_CPU_ZARCH
8870 && GET_MODE (operands[2]) == Pmode"
8871 "brasl\t%2,%0"
8872 [(set_attr "op_type" "RIL")
8873 (set_attr "type" "jsr")
8874 (set_attr "z196prop" "z196_cracked")])
8876 (define_insn "*basr"
8877 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8878 (match_operand 1 "const_int_operand" "n"))
8879 (clobber (match_operand 2 "register_operand" "=r"))]
8880 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8881 {
8882 if (get_attr_op_type (insn) == OP_TYPE_RR)
8883 return "basr\t%2,%0";
8884 else
8885 return "bas\t%2,%a0";
8886 }
8887 [(set (attr "op_type")
8888 (if_then_else (match_operand 0 "register_operand" "")
8889 (const_string "RR") (const_string "RX")))
8890 (set_attr "type" "jsr")
8891 (set_attr "atype" "agen")
8892 (set_attr "z196prop" "z196_cracked")])
8894 ;
8895 ; call_value instruction pattern(s).
8896 ;
8898 (define_expand "call_value"
8899 [(set (match_operand 0 "" "")
8900 (call (match_operand 1 "" "")
8901 (match_operand 2 "" "")))
8902 (use (match_operand 3 "" ""))]
8903 ""
8904 {
8905 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8906 gen_rtx_REG (Pmode, RETURN_REGNUM));
8907 DONE;
8908 })
8910 (define_insn "*bras_r"
8911 [(set (match_operand 0 "" "")
8912 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8913 (match_operand:SI 2 "const_int_operand" "n")))
8914 (clobber (match_operand 3 "register_operand" "=r"))]
8915 "!SIBLING_CALL_P (insn)
8916 && TARGET_SMALL_EXEC
8917 && GET_MODE (operands[3]) == Pmode"
8918 "bras\t%3,%1"
8919 [(set_attr "op_type" "RI")
8920 (set_attr "type" "jsr")
8921 (set_attr "z196prop" "z196_cracked")])
8923 (define_insn "*brasl_r"
8924 [(set (match_operand 0 "" "")
8925 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8926 (match_operand 2 "const_int_operand" "n")))
8927 (clobber (match_operand 3 "register_operand" "=r"))]
8928 "!SIBLING_CALL_P (insn)
8929 && TARGET_CPU_ZARCH
8930 && GET_MODE (operands[3]) == Pmode"
8931 "brasl\t%3,%1"
8932 [(set_attr "op_type" "RIL")
8933 (set_attr "type" "jsr")
8934 (set_attr "z196prop" "z196_cracked")])
8936 (define_insn "*basr_r"
8937 [(set (match_operand 0 "" "")
8938 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8939 (match_operand 2 "const_int_operand" "n")))
8940 (clobber (match_operand 3 "register_operand" "=r"))]
8941 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8942 {
8943 if (get_attr_op_type (insn) == OP_TYPE_RR)
8944 return "basr\t%3,%1";
8945 else
8946 return "bas\t%3,%a1";
8947 }
8948 [(set (attr "op_type")
8949 (if_then_else (match_operand 1 "register_operand" "")
8950 (const_string "RR") (const_string "RX")))
8951 (set_attr "type" "jsr")
8952 (set_attr "atype" "agen")
8953 (set_attr "z196prop" "z196_cracked")])
8955 ;;
8956 ;;- Thread-local storage support.
8957 ;;
8959 (define_expand "get_thread_pointer<mode>"
8960 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8961 ""
8962 "")
8964 (define_expand "set_thread_pointer<mode>"
8965 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8966 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8967 ""
8968 "")
8970 (define_insn "*set_tp"
8971 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8972 ""
8973 ""
8974 [(set_attr "type" "none")
8975 (set_attr "length" "0")])
8977 (define_insn "*tls_load_64"
8978 [(set (match_operand:DI 0 "register_operand" "=d")
8979 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8980 (match_operand:DI 2 "" "")]
8981 UNSPEC_TLS_LOAD))]
8982 "TARGET_64BIT"
8983 "lg\t%0,%1%J2"
8984 [(set_attr "op_type" "RXE")
8985 (set_attr "z10prop" "z10_fwd_A3")])
8987 (define_insn "*tls_load_31"
8988 [(set (match_operand:SI 0 "register_operand" "=d,d")
8989 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8990 (match_operand:SI 2 "" "")]
8991 UNSPEC_TLS_LOAD))]
8992 "!TARGET_64BIT"
8993 "@
8994 l\t%0,%1%J2
8995 ly\t%0,%1%J2"
8996 [(set_attr "op_type" "RX,RXY")
8997 (set_attr "type" "load")
8998 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9000 (define_insn "*bras_tls"
9001 [(set (match_operand 0 "" "")
9002 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9003 (match_operand 2 "const_int_operand" "n")))
9004 (clobber (match_operand 3 "register_operand" "=r"))
9005 (use (match_operand 4 "" ""))]
9006 "!SIBLING_CALL_P (insn)
9007 && TARGET_SMALL_EXEC
9008 && GET_MODE (operands[3]) == Pmode"
9009 "bras\t%3,%1%J4"
9010 [(set_attr "op_type" "RI")
9011 (set_attr "type" "jsr")
9012 (set_attr "z196prop" "z196_cracked")])
9014 (define_insn "*brasl_tls"
9015 [(set (match_operand 0 "" "")
9016 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9017 (match_operand 2 "const_int_operand" "n")))
9018 (clobber (match_operand 3 "register_operand" "=r"))
9019 (use (match_operand 4 "" ""))]
9020 "!SIBLING_CALL_P (insn)
9021 && TARGET_CPU_ZARCH
9022 && GET_MODE (operands[3]) == Pmode"
9023 "brasl\t%3,%1%J4"
9024 [(set_attr "op_type" "RIL")
9025 (set_attr "type" "jsr")
9026 (set_attr "z196prop" "z196_cracked")])
9028 (define_insn "*basr_tls"
9029 [(set (match_operand 0 "" "")
9030 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9031 (match_operand 2 "const_int_operand" "n")))
9032 (clobber (match_operand 3 "register_operand" "=r"))
9033 (use (match_operand 4 "" ""))]
9034 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9035 {
9036 if (get_attr_op_type (insn) == OP_TYPE_RR)
9037 return "basr\t%3,%1%J4";
9038 else
9039 return "bas\t%3,%a1%J4";
9040 }
9041 [(set (attr "op_type")
9042 (if_then_else (match_operand 1 "register_operand" "")
9043 (const_string "RR") (const_string "RX")))
9044 (set_attr "type" "jsr")
9045 (set_attr "atype" "agen")
9046 (set_attr "z196prop" "z196_cracked")])
9048 ;;
9049 ;;- Atomic operations
9050 ;;
9052 ;
9053 ; memory barrier patterns.
9054 ;
9056 (define_expand "mem_signal_fence"
9057 [(match_operand:SI 0 "const_int_operand")] ;; model
9058 ""
9059 {
9060 /* The s390 memory model is strong enough not to require any
9061 barrier in order to synchronize a thread with itself. */
9062 DONE;
9063 })
9065 (define_expand "mem_thread_fence"
9066 [(match_operand:SI 0 "const_int_operand")] ;; model
9067 ""
9068 {
9069 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9070 enough not to require barriers of any kind. */
9071 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
9072 {
9073 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9074 MEM_VOLATILE_P (mem) = 1;
9075 emit_insn (gen_mem_thread_fence_1 (mem));
9076 }
9077 DONE;
9078 })
9080 ; Although bcr is superscalar on Z10, this variant will never
9081 ; become part of an execution group.
9082 ; With z196 we can make use of the fast-BCR-serialization facility.
9083 ; This allows for a slightly faster sync which is sufficient for our
9084 ; purposes.
9085 (define_insn "mem_thread_fence_1"
9086 [(set (match_operand:BLK 0 "" "")
9087 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9088 ""
9089 {
9090 if (TARGET_Z196)
9091 return "bcr\t14,0";
9092 else
9093 return "bcr\t15,0";
9094 }
9095 [(set_attr "op_type" "RR")
9096 (set_attr "mnemonic" "bcr_flush")
9097 (set_attr "z196prop" "z196_alone")])
9099 ;
9100 ; atomic load/store operations
9101 ;
9103 ; Atomic loads need not examine the memory model at all.
9104 (define_expand "atomic_load<mode>"
9105 [(match_operand:DINT 0 "register_operand") ;; output
9106 (match_operand:DINT 1 "memory_operand") ;; memory
9107 (match_operand:SI 2 "const_int_operand")] ;; model
9108 ""
9109 {
9110 if (<MODE>mode == TImode)
9111 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9112 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9113 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9114 else
9115 emit_move_insn (operands[0], operands[1]);
9116 DONE;
9117 })
9119 ; Different from movdi_31 in that we want no splitters.
9120 (define_insn "atomic_loaddi_1"
9121 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9122 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9123 UNSPEC_MOVA))]
9124 "!TARGET_ZARCH"
9125 "@
9126 lm\t%0,%M0,%S1
9127 lmy\t%0,%M0,%S1
9128 ld\t%0,%1
9129 ldy\t%0,%1"
9130 [(set_attr "op_type" "RS,RSY,RS,RSY")
9131 (set_attr "type" "lm,lm,floaddf,floaddf")])
9133 (define_insn "atomic_loadti_1"
9134 [(set (match_operand:TI 0 "register_operand" "=r")
9135 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9136 UNSPEC_MOVA))]
9137 "TARGET_ZARCH"
9138 "lpq\t%0,%1"
9139 [(set_attr "op_type" "RXY")
9140 (set_attr "type" "other")])
9142 ; Atomic stores must(?) enforce sequential consistency.
9143 (define_expand "atomic_store<mode>"
9144 [(match_operand:DINT 0 "memory_operand") ;; memory
9145 (match_operand:DINT 1 "register_operand") ;; input
9146 (match_operand:SI 2 "const_int_operand")] ;; model
9147 ""
9148 {
9149 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9151 if (<MODE>mode == TImode)
9152 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9153 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9154 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9155 else
9156 emit_move_insn (operands[0], operands[1]);
9157 if (model == MEMMODEL_SEQ_CST)
9158 emit_insn (gen_mem_thread_fence (operands[2]));
9159 DONE;
9160 })
9162 ; Different from movdi_31 in that we want no splitters.
9163 (define_insn "atomic_storedi_1"
9164 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9165 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9166 UNSPEC_MOVA))]
9167 "!TARGET_ZARCH"
9168 "@
9169 stm\t%1,%N1,%S0
9170 stmy\t%1,%N1,%S0
9171 std %1,%0
9172 stdy %1,%0"
9173 [(set_attr "op_type" "RS,RSY,RS,RSY")
9174 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9176 (define_insn "atomic_storeti_1"
9177 [(set (match_operand:TI 0 "memory_operand" "=RT")
9178 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9179 UNSPEC_MOVA))]
9180 "TARGET_ZARCH"
9181 "stpq\t%1,%0"
9182 [(set_attr "op_type" "RXY")
9183 (set_attr "type" "other")])
9185 ;
9186 ; compare and swap patterns.
9187 ;
9189 (define_expand "atomic_compare_and_swap<mode>"
9190 [(match_operand:SI 0 "register_operand") ;; bool success output
9191 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9192 (match_operand:DGPR 2 "memory_operand") ;; memory
9193 (match_operand:DGPR 3 "register_operand") ;; expected intput
9194 (match_operand:DGPR 4 "register_operand") ;; newval intput
9195 (match_operand:SI 5 "const_int_operand") ;; is_weak
9196 (match_operand:SI 6 "const_int_operand") ;; success model
9197 (match_operand:SI 7 "const_int_operand")] ;; failure model
9198 ""
9199 {
9200 rtx cc, cmp, output = operands[1];
9202 if (!register_operand (output, <MODE>mode))
9203 output = gen_reg_rtx (<MODE>mode);
9205 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9206 (output, operands[2], operands[3], operands[4]));
9208 /* We deliberately accept non-register operands in the predicate
9209 to ensure the write back to the output operand happens *before*
9210 the store-flags code below. This makes it easier for combine
9211 to merge the store-flags code with a potential test-and-branch
9212 pattern following (immediately!) afterwards. */
9213 if (output != operands[1])
9214 emit_move_insn (operands[1], output);
9216 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9217 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9218 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9219 DONE;
9220 })
9222 (define_expand "atomic_compare_and_swap<mode>"
9223 [(match_operand:SI 0 "register_operand") ;; bool success output
9224 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9225 (match_operand:HQI 2 "memory_operand") ;; memory
9226 (match_operand:HQI 3 "general_operand") ;; expected intput
9227 (match_operand:HQI 4 "general_operand") ;; newval intput
9228 (match_operand:SI 5 "const_int_operand") ;; is_weak
9229 (match_operand:SI 6 "const_int_operand") ;; success model
9230 (match_operand:SI 7 "const_int_operand")] ;; failure model
9231 ""
9232 {
9233 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9234 operands[3], operands[4], INTVAL (operands[5]));
9235 DONE;
9236 })
9238 (define_expand "atomic_compare_and_swap<mode>_internal"
9239 [(parallel
9240 [(set (match_operand:DGPR 0 "register_operand")
9241 (match_operand:DGPR 1 "memory_operand"))
9242 (set (match_dup 1)
9243 (unspec_volatile:DGPR
9244 [(match_dup 1)
9245 (match_operand:DGPR 2 "register_operand")
9246 (match_operand:DGPR 3 "register_operand")]
9247 UNSPECV_CAS))
9248 (set (reg:CCZ1 CC_REGNUM)
9249 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9250 "")
9252 ; cdsg, csg
9253 (define_insn "*atomic_compare_and_swap<mode>_1"
9254 [(set (match_operand:TDI 0 "register_operand" "=r")
9255 (match_operand:TDI 1 "memory_operand" "+QS"))
9256 (set (match_dup 1)
9257 (unspec_volatile:TDI
9258 [(match_dup 1)
9259 (match_operand:TDI 2 "register_operand" "0")
9260 (match_operand:TDI 3 "register_operand" "r")]
9261 UNSPECV_CAS))
9262 (set (reg:CCZ1 CC_REGNUM)
9263 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9264 "TARGET_ZARCH"
9265 "c<td>sg\t%0,%3,%S1"
9266 [(set_attr "op_type" "RSY")
9267 (set_attr "type" "sem")])
9269 ; cds, cdsy
9270 (define_insn "*atomic_compare_and_swapdi_2"
9271 [(set (match_operand:DI 0 "register_operand" "=r,r")
9272 (match_operand:DI 1 "memory_operand" "+Q,S"))
9273 (set (match_dup 1)
9274 (unspec_volatile:DI
9275 [(match_dup 1)
9276 (match_operand:DI 2 "register_operand" "0,0")
9277 (match_operand:DI 3 "register_operand" "r,r")]
9278 UNSPECV_CAS))
9279 (set (reg:CCZ1 CC_REGNUM)
9280 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9281 "!TARGET_ZARCH"
9282 "@
9283 cds\t%0,%3,%S1
9284 cdsy\t%0,%3,%S1"
9285 [(set_attr "op_type" "RS,RSY")
9286 (set_attr "type" "sem")])
9288 ; cs, csy
9289 (define_insn "*atomic_compare_and_swapsi_3"
9290 [(set (match_operand:SI 0 "register_operand" "=r,r")
9291 (match_operand:SI 1 "memory_operand" "+Q,S"))
9292 (set (match_dup 1)
9293 (unspec_volatile:SI
9294 [(match_dup 1)
9295 (match_operand:SI 2 "register_operand" "0,0")
9296 (match_operand:SI 3 "register_operand" "r,r")]
9297 UNSPECV_CAS))
9298 (set (reg:CCZ1 CC_REGNUM)
9299 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9300 ""
9301 "@
9302 cs\t%0,%3,%S1
9303 csy\t%0,%3,%S1"
9304 [(set_attr "op_type" "RS,RSY")
9305 (set_attr "type" "sem")])
9307 ;
9308 ; Other atomic instruction patterns.
9309 ;
9311 ; z196 load and add, xor, or and and instructions
9313 (define_expand "atomic_fetch_<atomic><mode>"
9314 [(match_operand:GPR 0 "register_operand") ;; val out
9315 (ATOMIC_Z196:GPR
9316 (match_operand:GPR 1 "memory_operand") ;; memory
9317 (match_operand:GPR 2 "register_operand")) ;; val in
9318 (match_operand:SI 3 "const_int_operand")] ;; model
9319 "TARGET_Z196"
9320 {
9321 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9322 (operands[0], operands[1], operands[2]));
9323 DONE;
9324 })
9326 ; lan, lang, lao, laog, lax, laxg, laa, laag
9327 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9328 [(set (match_operand:GPR 0 "register_operand" "=d")
9329 (match_operand:GPR 1 "memory_operand" "+QS"))
9330 (set (match_dup 1)
9331 (unspec_volatile:GPR
9332 [(ATOMIC_Z196:GPR (match_dup 1)
9333 (match_operand:GPR 2 "general_operand" "d"))]
9334 UNSPECV_ATOMIC_OP))
9335 (clobber (reg:CC CC_REGNUM))]
9336 "TARGET_Z196"
9337 "la<noxa><g>\t%0,%2,%1"
9338 [(set_attr "op_type" "RSY")
9339 (set_attr "type" "sem")])
9341 ;; For SImode and larger, the optabs.c code will do just fine in
9342 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9343 ;; better by expanding our own loop.
9345 (define_expand "atomic_<atomic><mode>"
9346 [(ATOMIC:HQI
9347 (match_operand:HQI 0 "memory_operand") ;; memory
9348 (match_operand:HQI 1 "general_operand")) ;; val in
9349 (match_operand:SI 2 "const_int_operand")] ;; model
9350 ""
9351 {
9352 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9353 operands[1], false);
9354 DONE;
9355 })
9357 (define_expand "atomic_fetch_<atomic><mode>"
9358 [(match_operand:HQI 0 "register_operand") ;; val out
9359 (ATOMIC:HQI
9360 (match_operand:HQI 1 "memory_operand") ;; memory
9361 (match_operand:HQI 2 "general_operand")) ;; val in
9362 (match_operand:SI 3 "const_int_operand")] ;; model
9363 ""
9364 {
9365 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9366 operands[2], false);
9367 DONE;
9368 })
9370 (define_expand "atomic_<atomic>_fetch<mode>"
9371 [(match_operand:HQI 0 "register_operand") ;; val out
9372 (ATOMIC:HQI
9373 (match_operand:HQI 1 "memory_operand") ;; memory
9374 (match_operand:HQI 2 "general_operand")) ;; val in
9375 (match_operand:SI 3 "const_int_operand")] ;; model
9376 ""
9377 {
9378 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9379 operands[2], true);
9380 DONE;
9381 })
9383 (define_expand "atomic_exchange<mode>"
9384 [(match_operand:HQI 0 "register_operand") ;; val out
9385 (match_operand:HQI 1 "memory_operand") ;; memory
9386 (match_operand:HQI 2 "general_operand") ;; val in
9387 (match_operand:SI 3 "const_int_operand")] ;; model
9388 ""
9389 {
9390 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9391 operands[2], false);
9392 DONE;
9393 })
9395 ;;
9396 ;;- Miscellaneous instructions.
9397 ;;
9399 ;
9400 ; allocate stack instruction pattern(s).
9401 ;
9403 (define_expand "allocate_stack"
9404 [(match_operand 0 "general_operand" "")
9405 (match_operand 1 "general_operand" "")]
9406 "TARGET_BACKCHAIN"
9407 {
9408 rtx temp = gen_reg_rtx (Pmode);
9410 emit_move_insn (temp, s390_back_chain_rtx ());
9411 anti_adjust_stack (operands[1]);
9412 emit_move_insn (s390_back_chain_rtx (), temp);
9414 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9415 DONE;
9416 })
9419 ;
9420 ; setjmp instruction pattern.
9421 ;
9423 (define_expand "builtin_setjmp_receiver"
9424 [(match_operand 0 "" "")]
9425 "flag_pic"
9426 {
9427 emit_insn (s390_load_got ());
9428 emit_use (pic_offset_table_rtx);
9429 DONE;
9430 })
9432 ;; These patterns say how to save and restore the stack pointer. We need not
9433 ;; save the stack pointer at function level since we are careful to
9434 ;; preserve the backchain. At block level, we have to restore the backchain
9435 ;; when we restore the stack pointer.
9436 ;;
9437 ;; For nonlocal gotos, we must save both the stack pointer and its
9438 ;; backchain and restore both. Note that in the nonlocal case, the
9439 ;; save area is a memory location.
9441 (define_expand "save_stack_function"
9442 [(match_operand 0 "general_operand" "")
9443 (match_operand 1 "general_operand" "")]
9444 ""
9445 "DONE;")
9447 (define_expand "restore_stack_function"
9448 [(match_operand 0 "general_operand" "")
9449 (match_operand 1 "general_operand" "")]
9450 ""
9451 "DONE;")
9453 (define_expand "restore_stack_block"
9454 [(match_operand 0 "register_operand" "")
9455 (match_operand 1 "register_operand" "")]
9456 "TARGET_BACKCHAIN"
9457 {
9458 rtx temp = gen_reg_rtx (Pmode);
9460 emit_move_insn (temp, s390_back_chain_rtx ());
9461 emit_move_insn (operands[0], operands[1]);
9462 emit_move_insn (s390_back_chain_rtx (), temp);
9464 DONE;
9465 })
9467 (define_expand "save_stack_nonlocal"
9468 [(match_operand 0 "memory_operand" "")
9469 (match_operand 1 "register_operand" "")]
9470 ""
9471 {
9472 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9474 /* Copy the backchain to the first word, sp to the second and the
9475 literal pool base to the third. */
9477 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9478 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9479 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9481 if (TARGET_BACKCHAIN)
9482 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9484 emit_move_insn (save_sp, operands[1]);
9485 emit_move_insn (save_bp, base);
9487 DONE;
9488 })
9490 (define_expand "restore_stack_nonlocal"
9491 [(match_operand 0 "register_operand" "")
9492 (match_operand 1 "memory_operand" "")]
9493 ""
9494 {
9495 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9496 rtx temp = NULL_RTX;
9498 /* Restore the backchain from the first word, sp from the second and the
9499 literal pool base from the third. */
9501 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9502 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9503 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9505 if (TARGET_BACKCHAIN)
9506 temp = force_reg (Pmode, save_bc);
9508 emit_move_insn (base, save_bp);
9509 emit_move_insn (operands[0], save_sp);
9511 if (temp)
9512 emit_move_insn (s390_back_chain_rtx (), temp);
9514 emit_use (base);
9515 DONE;
9516 })
9518 (define_expand "exception_receiver"
9519 [(const_int 0)]
9520 ""
9521 {
9522 s390_set_has_landing_pad_p (true);
9523 DONE;
9524 })
9526 ;
9527 ; nop instruction pattern(s).
9528 ;
9530 (define_insn "nop"
9531 [(const_int 0)]
9532 ""
9533 "lr\t0,0"
9534 [(set_attr "op_type" "RR")
9535 (set_attr "z10prop" "z10_fr_E1")])
9537 (define_insn "nop1"
9538 [(const_int 1)]
9539 ""
9540 "lr\t1,1"
9541 [(set_attr "op_type" "RR")])
9544 ;
9545 ; Special literal pool access instruction pattern(s).
9546 ;
9548 (define_insn "*pool_entry"
9549 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9550 UNSPECV_POOL_ENTRY)]
9551 ""
9552 {
9553 enum machine_mode mode = GET_MODE (PATTERN (insn));
9554 unsigned int align = GET_MODE_BITSIZE (mode);
9555 s390_output_pool_entry (operands[0], mode, align);
9556 return "";
9557 }
9558 [(set (attr "length")
9559 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9561 (define_insn "pool_align"
9562 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9563 UNSPECV_POOL_ALIGN)]
9564 ""
9565 ".align\t%0"
9566 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9568 (define_insn "pool_section_start"
9569 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9570 ""
9571 ".section\t.rodata"
9572 [(set_attr "length" "0")])
9574 (define_insn "pool_section_end"
9575 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9576 ""
9577 ".previous"
9578 [(set_attr "length" "0")])
9580 (define_insn "main_base_31_small"
9581 [(set (match_operand 0 "register_operand" "=a")
9582 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9583 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9584 "basr\t%0,0"
9585 [(set_attr "op_type" "RR")
9586 (set_attr "type" "la")
9587 (set_attr "z196prop" "z196_cracked")])
9589 (define_insn "main_base_31_large"
9590 [(set (match_operand 0 "register_operand" "=a")
9591 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9592 (set (pc) (label_ref (match_operand 2 "" "")))]
9593 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9594 "bras\t%0,%2"
9595 [(set_attr "op_type" "RI")
9596 (set_attr "z196prop" "z196_cracked")])
9598 (define_insn "main_base_64"
9599 [(set (match_operand 0 "register_operand" "=a")
9600 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9601 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9602 "larl\t%0,%1"
9603 [(set_attr "op_type" "RIL")
9604 (set_attr "type" "larl")
9605 (set_attr "z10prop" "z10_fwd_A1")])
9607 (define_insn "main_pool"
9608 [(set (match_operand 0 "register_operand" "=a")
9609 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9610 "GET_MODE (operands[0]) == Pmode"
9611 {
9612 gcc_unreachable ();
9613 }
9614 [(set (attr "type")
9615 (if_then_else (match_test "TARGET_CPU_ZARCH")
9616 (const_string "larl") (const_string "la")))])
9618 (define_insn "reload_base_31"
9619 [(set (match_operand 0 "register_operand" "=a")
9620 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9621 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9622 "basr\t%0,0\;la\t%0,%1-.(%0)"
9623 [(set_attr "length" "6")
9624 (set_attr "type" "la")
9625 (set_attr "z196prop" "z196_cracked")])
9627 (define_insn "reload_base_64"
9628 [(set (match_operand 0 "register_operand" "=a")
9629 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9630 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9631 "larl\t%0,%1"
9632 [(set_attr "op_type" "RIL")
9633 (set_attr "type" "larl")
9634 (set_attr "z10prop" "z10_fwd_A1")])
9636 (define_insn "pool"
9637 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9638 ""
9639 {
9640 gcc_unreachable ();
9641 }
9642 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9644 ;;
9645 ;; Insns related to generating the function prologue and epilogue.
9646 ;;
9649 (define_expand "prologue"
9650 [(use (const_int 0))]
9651 ""
9652 "s390_emit_prologue (); DONE;")
9654 (define_expand "epilogue"
9655 [(use (const_int 1))]
9656 ""
9657 "s390_emit_epilogue (false); DONE;")
9659 (define_expand "sibcall_epilogue"
9660 [(use (const_int 0))]
9661 ""
9662 "s390_emit_epilogue (true); DONE;")
9664 (define_insn "*return"
9665 [(return)
9666 (use (match_operand 0 "register_operand" "a"))]
9667 "GET_MODE (operands[0]) == Pmode"
9668 "br\t%0"
9669 [(set_attr "op_type" "RR")
9670 (set_attr "type" "jsr")
9671 (set_attr "atype" "agen")])
9674 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9675 ;; pointer. This is used for compatibility.
9677 (define_expand "ptr_extend"
9678 [(set (match_operand:DI 0 "register_operand" "=r")
9679 (match_operand:SI 1 "register_operand" "r"))]
9680 "TARGET_64BIT"
9681 {
9682 emit_insn (gen_anddi3 (operands[0],
9683 gen_lowpart (DImode, operands[1]),
9684 GEN_INT (0x7fffffff)));
9685 DONE;
9686 })
9688 ;; Instruction definition to expand eh_return macro to support
9689 ;; swapping in special linkage return addresses.
9691 (define_expand "eh_return"
9692 [(use (match_operand 0 "register_operand" ""))]
9693 "TARGET_TPF"
9694 {
9695 s390_emit_tpf_eh_return (operands[0]);
9696 DONE;
9697 })
9699 ;
9700 ; Stack Protector Patterns
9701 ;
9703 (define_expand "stack_protect_set"
9704 [(set (match_operand 0 "memory_operand" "")
9705 (match_operand 1 "memory_operand" ""))]
9706 ""
9707 {
9708 #ifdef TARGET_THREAD_SSP_OFFSET
9709 operands[1]
9710 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9711 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9712 #endif
9713 if (TARGET_64BIT)
9714 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9715 else
9716 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9718 DONE;
9719 })
9721 (define_insn "stack_protect_set<mode>"
9722 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9723 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9724 ""
9725 "mvc\t%O0(%G0,%R0),%S1"
9726 [(set_attr "op_type" "SS")])
9728 (define_expand "stack_protect_test"
9729 [(set (reg:CC CC_REGNUM)
9730 (compare (match_operand 0 "memory_operand" "")
9731 (match_operand 1 "memory_operand" "")))
9732 (match_operand 2 "" "")]
9733 ""
9734 {
9735 rtx cc_reg, test;
9736 #ifdef TARGET_THREAD_SSP_OFFSET
9737 operands[1]
9738 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9739 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9740 #endif
9741 if (TARGET_64BIT)
9742 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9743 else
9744 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9746 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9747 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9748 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9749 DONE;
9750 })
9752 (define_insn "stack_protect_test<mode>"
9753 [(set (reg:CCZ CC_REGNUM)
9754 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9755 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9756 ""
9757 "clc\t%O0(%G0,%R0),%S1"
9758 [(set_attr "op_type" "SS")])
9760 ; This is used in s390_emit_prologue in order to prevent insns
9761 ; adjusting the stack pointer to be moved over insns writing stack
9762 ; slots using a copy of the stack pointer in a different register.
9763 (define_insn "stack_tie"
9764 [(set (match_operand:BLK 0 "memory_operand" "+m")
9765 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9766 ""
9767 ""
9768 [(set_attr "length" "0")])
9771 ;
9772 ; Data prefetch patterns
9773 ;
9775 (define_insn "prefetch"
9776 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9777 (match_operand:SI 1 "const_int_operand" " n,n")
9778 (match_operand:SI 2 "const_int_operand" " n,n"))]
9779 "TARGET_Z10"
9780 {
9781 switch (which_alternative)
9782 {
9783 case 0:
9784 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9785 case 1:
9786 if (larl_operand (operands[0], Pmode))
9787 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9788 default:
9790 /* This might be reached for symbolic operands with an odd
9791 addend. We simply omit the prefetch for such rare cases. */
9793 return "";
9794 }
9795 }
9796 [(set_attr "type" "load,larl")
9797 (set_attr "op_type" "RXY,RIL")
9798 (set_attr "z10prop" "z10_super")
9799 (set_attr "z196prop" "z196_alone")])
9802 ;
9803 ; Byte swap instructions
9804 ;
9806 (define_insn "bswap<mode>2"
9807 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9808 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9809 "TARGET_CPU_ZARCH"
9810 "@
9811 lrv<g>r\t%0,%1
9812 lrv<g>\t%0,%1"
9813 [(set_attr "type" "*,load")
9814 (set_attr "op_type" "RRE,RXY")
9815 (set_attr "z10prop" "z10_super")])
9818 ;
9819 ; Population count instruction
9820 ;
9822 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9823 ; portions and stores the result in the corresponding bytes in op0.
9824 (define_insn "*popcount<mode>"
9825 [(set (match_operand:INT 0 "register_operand" "=d")
9826 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9827 (clobber (reg:CC CC_REGNUM))]
9828 "TARGET_Z196"
9829 "popcnt\t%0,%1"
9830 [(set_attr "op_type" "RRE")])
9832 (define_expand "popcountdi2"
9833 [; popcnt op0, op1
9834 (parallel [(set (match_operand:DI 0 "register_operand" "")
9835 (unspec:DI [(match_operand:DI 1 "register_operand")]
9836 UNSPEC_POPCNT))
9837 (clobber (reg:CC CC_REGNUM))])
9838 ; sllg op2, op0, 32
9839 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9840 ; agr op0, op2
9841 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9842 (clobber (reg:CC CC_REGNUM))])
9843 ; sllg op2, op0, 16
9844 (set (match_dup 2)
9845 (ashift:DI (match_dup 0) (const_int 16)))
9846 ; agr op0, op2
9847 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9848 (clobber (reg:CC CC_REGNUM))])
9849 ; sllg op2, op0, 8
9850 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9851 ; agr op0, op2
9852 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9853 (clobber (reg:CC CC_REGNUM))])
9854 ; srlg op0, op0, 56
9855 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9856 "TARGET_Z196 && TARGET_64BIT"
9857 "operands[2] = gen_reg_rtx (DImode);")
9859 (define_expand "popcountsi2"
9860 [; popcnt op0, op1
9861 (parallel [(set (match_operand:SI 0 "register_operand" "")
9862 (unspec:SI [(match_operand:SI 1 "register_operand")]
9863 UNSPEC_POPCNT))
9864 (clobber (reg:CC CC_REGNUM))])
9865 ; sllk op2, op0, 16
9866 (set (match_dup 2)
9867 (ashift:SI (match_dup 0) (const_int 16)))
9868 ; ar op0, op2
9869 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9870 (clobber (reg:CC CC_REGNUM))])
9871 ; sllk op2, op0, 8
9872 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9873 ; ar op0, op2
9874 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9875 (clobber (reg:CC CC_REGNUM))])
9876 ; srl op0, op0, 24
9877 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9878 "TARGET_Z196"
9879 "operands[2] = gen_reg_rtx (SImode);")
9881 (define_expand "popcounthi2"
9882 [; popcnt op0, op1
9883 (parallel [(set (match_operand:HI 0 "register_operand" "")
9884 (unspec:HI [(match_operand:HI 1 "register_operand")]
9885 UNSPEC_POPCNT))
9886 (clobber (reg:CC CC_REGNUM))])
9887 ; sllk op2, op0, 8
9888 (set (match_dup 2)
9889 (ashift:SI (match_dup 0) (const_int 8)))
9890 ; ar op0, op2
9891 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9892 (clobber (reg:CC CC_REGNUM))])
9893 ; srl op0, op0, 8
9894 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9895 "TARGET_Z196"
9896 "operands[2] = gen_reg_rtx (SImode);")
9898 (define_expand "popcountqi2"
9899 [; popcnt op0, op1
9900 (parallel [(set (match_operand:QI 0 "register_operand" "")
9901 (unspec:QI [(match_operand:QI 1 "register_operand")]
9902 UNSPEC_POPCNT))
9903 (clobber (reg:CC CC_REGNUM))])]
9904 "TARGET_Z196"
9905 "")
9907 ;;
9908 ;;- Copy sign instructions
9909 ;;
9911 (define_insn "copysign<mode>3"
9912 [(set (match_operand:FP 0 "register_operand" "=f")
9913 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9914 (match_operand:FP 2 "register_operand" "f")]
9915 UNSPEC_COPYSIGN))]
9916 "TARGET_Z196"
9917 "cpsdr\t%0,%2,%1"
9918 [(set_attr "op_type" "RRF")
9919 (set_attr "type" "fsimp<mode>")])
9922 ;;
9923 ;;- Transactional execution instructions
9924 ;;
9926 ; This splitter helps combine to make use of CC directly when
9927 ; comparing the integer result of a tbegin builtin with a constant.
9928 ; The unspec is already removed by canonicalize_comparison. So this
9929 ; splitters only job is to turn the PARALLEL into separate insns
9930 ; again. Unfortunately this only works with the very first cc/int
9931 ; compare since combine is not able to deal with data flow across
9932 ; basic block boundaries.
9934 ; It needs to be an insn pattern as well since combine does not apply
9935 ; the splitter directly. Combine would only use it if it actually
9936 ; would reduce the number of instructions.
9937 (define_insn_and_split "*ccraw_to_int"
9938 [(set (pc)
9939 (if_then_else
9940 (match_operator 0 "s390_eqne_operator"
9941 [(reg:CCRAW CC_REGNUM)
9942 (match_operand 1 "const_int_operand" "")])
9943 (label_ref (match_operand 2 "" ""))
9944 (pc)))
9945 (set (match_operand:SI 3 "register_operand" "=d")
9946 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
9947 ""
9948 "#"
9949 ""
9950 [(set (match_dup 3)
9951 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
9952 (set (pc)
9953 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
9954 (label_ref (match_dup 2))
9955 (pc)))]
9956 "")
9958 ; Non-constrained transaction begin
9960 (define_expand "tbegin"
9961 [(match_operand:SI 0 "register_operand" "")
9962 (match_operand:BLK 1 "memory_operand" "")]
9963 "TARGET_HTM"
9964 {
9965 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
9966 DONE;
9967 })
9969 (define_expand "tbegin_nofloat"
9970 [(match_operand:SI 0 "register_operand" "")
9971 (match_operand:BLK 1 "memory_operand" "")]
9972 "TARGET_HTM"
9973 {
9974 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
9975 DONE;
9976 })
9978 (define_expand "tbegin_retry"
9979 [(match_operand:SI 0 "register_operand" "")
9980 (match_operand:BLK 1 "memory_operand" "")
9981 (match_operand:SI 2 "general_operand" "")]
9982 "TARGET_HTM"
9983 {
9984 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
9985 DONE;
9986 })
9988 (define_expand "tbegin_retry_nofloat"
9989 [(match_operand:SI 0 "register_operand" "")
9990 (match_operand:BLK 1 "memory_operand" "")
9991 (match_operand:SI 2 "general_operand" "")]
9992 "TARGET_HTM"
9993 {
9994 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
9995 DONE;
9996 })
9998 (define_insn "tbegin_1"
9999 [(set (reg:CCRAW CC_REGNUM)
10000 (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")
10001 (match_operand 1 "const_int_operand" " D")]
10002 UNSPECV_TBEGIN))
10003 (clobber (reg:DF 16))
10004 (clobber (reg:DF 17))
10005 (clobber (reg:DF 18))
10006 (clobber (reg:DF 19))
10007 (clobber (reg:DF 20))
10008 (clobber (reg:DF 21))
10009 (clobber (reg:DF 22))
10010 (clobber (reg:DF 23))
10011 (clobber (reg:DF 24))
10012 (clobber (reg:DF 25))
10013 (clobber (reg:DF 26))
10014 (clobber (reg:DF 27))
10015 (clobber (reg:DF 28))
10016 (clobber (reg:DF 29))
10017 (clobber (reg:DF 30))
10018 (clobber (reg:DF 31))]
10019 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10020 ; not supposed to be used for immediates (see genpreds.c).
10021 "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"
10022 "tbegin\t%0,%x1"
10023 [(set_attr "op_type" "SIL")])
10025 ; Same as above but without the FPR clobbers
10026 (define_insn "tbegin_nofloat_1"
10027 [(set (reg:CCRAW CC_REGNUM)
10028 (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")
10029 (match_operand 1 "const_int_operand" " D")]
10030 UNSPECV_TBEGIN))]
10031 "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"
10032 "tbegin\t%0,%x1"
10033 [(set_attr "op_type" "SIL")])
10036 ; Constrained transaction begin
10038 (define_expand "tbeginc"
10039 [(set (reg:CCRAW CC_REGNUM)
10040 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10041 UNSPECV_TBEGINC))]
10042 "TARGET_HTM"
10043 "")
10045 (define_insn "*tbeginc_1"
10046 [(set (reg:CCRAW CC_REGNUM)
10047 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10048 UNSPECV_TBEGINC))]
10049 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10050 "tbeginc\t0,%x0"
10051 [(set_attr "op_type" "SIL")])
10053 ; Transaction end
10055 (define_expand "tend"
10056 [(set (reg:CCRAW CC_REGNUM)
10057 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10058 (set (match_operand:SI 0 "register_operand" "")
10059 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10060 "TARGET_HTM"
10061 "")
10063 (define_insn "*tend_1"
10064 [(set (reg:CCRAW CC_REGNUM)
10065 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10066 "TARGET_HTM"
10067 "tend"
10068 [(set_attr "op_type" "S")])
10070 ; Transaction abort
10072 (define_expand "tabort"
10073 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10074 UNSPECV_TABORT)]
10075 "TARGET_HTM && operands != NULL"
10076 {
10077 if (CONST_INT_P (operands[0])
10078 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10079 {
10080 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10081 ". Values in range 0 through 255 are reserved.",
10082 INTVAL (operands[0]));
10083 FAIL;
10084 }
10085 })
10087 (define_insn "*tabort_1"
10088 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10089 UNSPECV_TABORT)]
10090 "TARGET_HTM && operands != NULL"
10091 "tabort\t%Y0"
10092 [(set_attr "op_type" "S")])
10094 ; Transaction extract nesting depth
10096 (define_insn "etnd"
10097 [(set (match_operand:SI 0 "register_operand" "=d")
10098 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10099 "TARGET_HTM"
10100 "etnd\t%0"
10101 [(set_attr "op_type" "RRE")])
10103 ; Non-transactional store
10105 (define_insn "ntstg"
10106 [(set (match_operand:DI 0 "memory_operand" "=RT")
10107 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10108 UNSPECV_NTSTG))]
10109 "TARGET_HTM"
10110 "ntstg\t%1,%0"
10111 [(set_attr "op_type" "RXY")])
10113 ; Transaction perform processor assist
10115 (define_expand "tx_assist"
10116 [(set (match_dup 1) (const_int 0))
10117 (unspec_volatile [(match_operand:SI 0 "register_operand" "")
10118 (match_dup 1)
10119 (const_int 1)]
10120 UNSPECV_PPA)]
10121 "TARGET_HTM"
10122 {
10123 operands[1] = gen_reg_rtx (SImode);
10124 })
10126 (define_insn "*ppa"
10127 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10128 (match_operand:SI 1 "register_operand" "d")
10129 (match_operand 2 "const_int_operand" "I")]
10130 UNSPECV_PPA)]
10131 "TARGET_HTM && INTVAL (operands[2]) < 16"
10132 "ppa\t%0,%1,1"
10133 [(set_attr "op_type" "RRF")])