| blob | 4de7c3a2f6e453703672c339910d314ee730bde4 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2013 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 ])
61 ;;
62 ;; UNSPEC usage
63 ;;
65 (define_c_enum "unspec"
66 [UNSPEC_FRSP ; frsp for POWER machines
67 UNSPEC_PROBE_STACK ; probe stack memory reference
68 UNSPEC_TOCPTR ; address of a word pointing to the TOC
69 UNSPEC_TOC ; address of the TOC (more-or-less)
70 UNSPEC_MOVSI_GOT
71 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
72 UNSPEC_FCTIWZ
73 UNSPEC_FRIM
74 UNSPEC_FRIN
75 UNSPEC_FRIP
76 UNSPEC_FRIZ
77 UNSPEC_LD_MPIC ; load_macho_picbase
78 UNSPEC_RELD_MPIC ; re-load_macho_picbase
79 UNSPEC_MPIC_CORRECT ; macho_correct_pic
80 UNSPEC_TLSGD
81 UNSPEC_TLSLD
82 UNSPEC_MOVESI_FROM_CR
83 UNSPEC_MOVESI_TO_CR
84 UNSPEC_TLSDTPREL
85 UNSPEC_TLSDTPRELHA
86 UNSPEC_TLSDTPRELLO
87 UNSPEC_TLSGOTDTPREL
88 UNSPEC_TLSTPREL
89 UNSPEC_TLSTPRELHA
90 UNSPEC_TLSTPRELLO
91 UNSPEC_TLSGOTTPREL
92 UNSPEC_TLSTLS
93 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
94 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
95 UNSPEC_STFIWX
96 UNSPEC_POPCNTB
97 UNSPEC_FRES
98 UNSPEC_SP_SET
99 UNSPEC_SP_TEST
100 UNSPEC_SYNC
101 UNSPEC_LWSYNC
102 UNSPEC_SYNC_OP
103 UNSPEC_ATOMIC
104 UNSPEC_CMPXCHG
105 UNSPEC_XCHG
106 UNSPEC_AND
107 UNSPEC_DLMZB
108 UNSPEC_DLMZB_CR
109 UNSPEC_DLMZB_STRLEN
110 UNSPEC_RSQRT
111 UNSPEC_TOCREL
112 UNSPEC_MACHOPIC_OFFSET
113 UNSPEC_BPERM
114 UNSPEC_COPYSIGN
115 UNSPEC_PARITY
116 UNSPEC_FCTIW
117 UNSPEC_FCTID
118 UNSPEC_LFIWAX
119 UNSPEC_LFIWZX
120 UNSPEC_FCTIWUZ
121 UNSPEC_GRP_END_NOP
122 UNSPEC_P8V_FMRGOW
123 UNSPEC_P8V_MTVSRWZ
124 UNSPEC_P8V_RELOAD_FROM_GPR
125 UNSPEC_P8V_MTVSRD
126 UNSPEC_P8V_XXPERMDI
127 UNSPEC_P8V_RELOAD_FROM_VSX
128 ])
130 ;;
131 ;; UNSPEC_VOLATILE usage
132 ;;
134 (define_c_enum "unspecv"
135 [UNSPECV_BLOCK
136 UNSPECV_LL ; load-locked
137 UNSPECV_SC ; store-conditional
138 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
139 UNSPECV_EH_RR ; eh_reg_restore
140 UNSPECV_ISYNC ; isync instruction
141 UNSPECV_MFTB ; move from time base
142 UNSPECV_NLGR ; non-local goto receiver
143 ])
145 \f
146 ;; Define an insn type attribute. This is used in function unit delay
147 ;; computations.
148 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"
149 (const_string "integer"))
151 ;; Define floating point instruction sub-types for use with Xfpu.md
152 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
154 ;; Length (in bytes).
155 ; '(pc)' in the following doesn't include the instruction itself; it is
156 ; calculated as if the instruction had zero size.
157 (define_attr "length" ""
158 (if_then_else (eq_attr "type" "branch")
159 (if_then_else (and (ge (minus (match_dup 0) (pc))
160 (const_int -32768))
161 (lt (minus (match_dup 0) (pc))
162 (const_int 32764)))
163 (const_int 4)
164 (const_int 8))
165 (const_int 4)))
167 ;; Processor type -- this attribute must exactly match the processor_type
168 ;; enumeration in rs6000-opts.h.
169 (define_attr "cpu"
170 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
171 ppc750,ppc7400,ppc7450,
172 ppc403,ppc405,ppc440,ppc476,
173 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
174 power4,power5,power6,power7,power8,
175 rs64a,mpccore,cell,ppca2,titan"
176 (const (symbol_ref "rs6000_cpu_attr")))
179 ;; If this instruction is microcoded on the CELL processor
180 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
181 (define_attr "cell_micro" "not,conditional,always"
182 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
183 (const_string "always")
184 (const_string "not")))
186 (automata_option "ndfa")
188 (include "rs64.md")
189 (include "mpc.md")
190 (include "40x.md")
191 (include "440.md")
192 (include "476.md")
193 (include "601.md")
194 (include "603.md")
195 (include "6xx.md")
196 (include "7xx.md")
197 (include "7450.md")
198 (include "8540.md")
199 (include "e300c2c3.md")
200 (include "e500mc.md")
201 (include "e500mc64.md")
202 (include "e5500.md")
203 (include "e6500.md")
204 (include "power4.md")
205 (include "power5.md")
206 (include "power6.md")
207 (include "power7.md")
208 (include "power8.md")
209 (include "cell.md")
210 (include "xfpu.md")
211 (include "a2.md")
212 (include "titan.md")
214 (include "predicates.md")
215 (include "constraints.md")
217 (include "darwin.md")
219 \f
220 ;; Mode iterators
222 ; This mode iterator allows :GPR to be used to indicate the allowable size
223 ; of whole values in GPRs.
224 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
226 ; Any supported integer mode.
227 (define_mode_iterator INT [QI HI SI DI TI PTI])
229 ; Any supported integer mode that fits in one register.
230 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
232 ; extend modes for DImode
233 (define_mode_iterator QHSI [QI HI SI])
235 ; QImode or HImode for small atomic ops
236 (define_mode_iterator QHI [QI HI])
238 ; HImode or SImode for sign extended fusion ops
239 (define_mode_iterator HSI [HI SI])
241 ; SImode or DImode, even if DImode doesn't fit in GPRs.
242 (define_mode_iterator SDI [SI DI])
244 ; The size of a pointer. Also, the size of the value that a record-condition
245 ; (one with a '.') will compare; and the size used for arithmetic carries.
246 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
248 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
249 ; PTImode is GPR only)
250 (define_mode_iterator TI2 [TI PTI])
252 ; Any hardware-supported floating-point mode
253 (define_mode_iterator FP [
254 (SF "TARGET_HARD_FLOAT
255 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
256 (DF "TARGET_HARD_FLOAT
257 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
258 (TF "!TARGET_IEEEQUAD
259 && TARGET_HARD_FLOAT
260 && (TARGET_FPRS || TARGET_E500_DOUBLE)
261 && TARGET_LONG_DOUBLE_128")
262 (DD "TARGET_DFP")
263 (TD "TARGET_DFP")])
265 ; Any fma capable floating-point mode.
266 (define_mode_iterator FMA_F [
267 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
268 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
269 || VECTOR_UNIT_VSX_P (DFmode)")
270 (V2SF "TARGET_PAIRED_FLOAT")
271 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
272 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
273 ])
275 ; Floating point move iterators to combine binary and decimal moves
276 (define_mode_iterator FMOVE32 [SF SD])
277 (define_mode_iterator FMOVE64 [DF DD])
278 (define_mode_iterator FMOVE64X [DI DF DD])
279 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
280 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
282 ; Iterators for 128 bit types for direct move
283 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
284 (V16QI "")
285 (V8HI "")
286 (V4SI "")
287 (V4SF "")
288 (V2DI "")
289 (V2DF "")])
291 ; Whether a floating point move is ok, don't allow SD without hardware FP
292 (define_mode_attr fmove_ok [(SF "")
293 (DF "")
294 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
295 (DD "")])
297 ; Convert REAL_VALUE to the appropriate bits
298 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
299 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
300 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
301 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
303 ; Definitions for load to 32-bit fpr register
304 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
305 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
306 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
307 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
309 ; Definitions for store from 32-bit fpr register
310 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
311 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
312 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
313 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
315 ; Definitions for 32-bit fpr direct move
316 (define_mode_attr f32_dm [(SF "wn") (SD "wm")])
318 ; These modes do not fit in integer registers in 32-bit mode.
319 ; but on e500v2, the gpr are 64 bit registers
320 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
322 ; Iterator for reciprocal estimate instructions
323 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
325 ; Iterator for just SF/DF
326 (define_mode_iterator SFDF [SF DF])
328 ; SF/DF suffix for traditional floating instructions
329 (define_mode_attr Ftrad [(SF "s") (DF "")])
331 ; SF/DF suffix for VSX instructions
332 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
334 ; SF/DF constraint for arithmetic on traditional floating point registers
335 (define_mode_attr Ff [(SF "f") (DF "d")])
337 ; SF/DF constraint for arithmetic on VSX registers
338 (define_mode_attr Fv [(SF "wy") (DF "ws")])
340 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
341 (define_mode_attr Fs [(SF "s") (DF "d")])
343 ; FRE/FRES support
344 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
345 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
347 ; Conditional returns.
348 (define_code_iterator any_return [return simple_return])
349 (define_code_attr return_pred [(return "direct_return ()")
350 (simple_return "1")])
351 (define_code_attr return_str [(return "") (simple_return "simple_")])
353 ; Various instructions that come in SI and DI forms.
354 ; A generic w/d attribute, for things like cmpw/cmpd.
355 (define_mode_attr wd [(QI "b")
356 (HI "h")
357 (SI "w")
358 (DI "d")
359 (V16QI "b")
360 (V8HI "h")
361 (V4SI "w")
362 (V2DI "d")])
364 ; DImode bits
365 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
367 ;; ISEL/ISEL64 target selection
368 (define_mode_attr sel [(SI "") (DI "64")])
370 ;; Suffix for reload patterns
371 (define_mode_attr ptrsize [(SI "32bit")
372 (DI "64bit")])
374 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
375 (DI "TARGET_64BIT")])
377 (define_mode_attr mptrsize [(SI "si")
378 (DI "di")])
380 (define_mode_attr ptrload [(SI "lwz")
381 (DI "ld")])
383 (define_mode_attr ptrm [(SI "m")
384 (DI "Y")])
386 (define_mode_attr rreg [(SF "f")
387 (DF "ws")
388 (V4SF "wf")
389 (V2DF "wd")])
391 (define_mode_attr rreg2 [(SF "f")
392 (DF "d")])
394 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
395 (DF "TARGET_FCFID")])
397 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
398 (DF "TARGET_E500_DOUBLE")])
400 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
401 (DF "TARGET_DOUBLE_FLOAT")])
403 ;; Mode iterator for logical operations on 128-bit types
404 (define_mode_iterator BOOL_128 [TI
405 PTI
406 (V16QI "TARGET_ALTIVEC")
407 (V8HI "TARGET_ALTIVEC")
408 (V4SI "TARGET_ALTIVEC")
409 (V4SF "TARGET_ALTIVEC")
410 (V2DI "TARGET_ALTIVEC")
411 (V2DF "TARGET_ALTIVEC")])
413 ;; For the GPRs we use 3 constraints for register outputs, two that are the
414 ;; same as the output register, and a third where the output register is an
415 ;; early clobber, so we don't have to deal with register overlaps. For the
416 ;; vector types, we prefer to use the vector registers. For TI mode, allow
417 ;; either.
419 ;; Mode attribute for boolean operation register constraints for output
420 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
421 (PTI "&r,r,r")
422 (V16QI "wa,v,&?r,?r,?r")
423 (V8HI "wa,v,&?r,?r,?r")
424 (V4SI "wa,v,&?r,?r,?r")
425 (V4SF "wa,v,&?r,?r,?r")
426 (V2DI "wa,v,&?r,?r,?r")
427 (V2DF "wa,v,&?r,?r,?r")])
429 ;; Mode attribute for boolean operation register constraints for operand1
430 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
431 (PTI "r,0,r")
432 (V16QI "wa,v,r,0,r")
433 (V8HI "wa,v,r,0,r")
434 (V4SI "wa,v,r,0,r")
435 (V4SF "wa,v,r,0,r")
436 (V2DI "wa,v,r,0,r")
437 (V2DF "wa,v,r,0,r")])
439 ;; Mode attribute for boolean operation register constraints for operand2
440 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
441 (PTI "r,r,0")
442 (V16QI "wa,v,r,r,0")
443 (V8HI "wa,v,r,r,0")
444 (V4SI "wa,v,r,r,0")
445 (V4SF "wa,v,r,r,0")
446 (V2DI "wa,v,r,r,0")
447 (V2DF "wa,v,r,r,0")])
449 ;; Mode attribute for boolean operation register constraints for operand1
450 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
451 ;; is used for operand1 or operand2
452 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
453 (PTI "r,0,0")
454 (V16QI "wa,v,r,0,0")
455 (V8HI "wa,v,r,0,0")
456 (V4SI "wa,v,r,0,0")
457 (V4SF "wa,v,r,0,0")
458 (V2DI "wa,v,r,0,0")
459 (V2DF "wa,v,r,0,0")])
461 ;; Mode attribute for the clobber of CC0 for AND expansion.
462 ;; For the 128-bit types, we never do AND immediate, but we need to
463 ;; get the correct number of X's for the number of operands.
464 (define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
465 (PTI "X,X,X")
466 (V16QI "X,X,X,X,X")
467 (V8HI "X,X,X,X,X")
468 (V4SI "X,X,X,X,X")
469 (V4SF "X,X,X,X,X")
470 (V2DI "X,X,X,X,X")
471 (V2DF "X,X,X,X,X")])
473 \f
474 ;; Start with fixed-point load and store insns. Here we put only the more
475 ;; complex forms. Basic data transfer is done later.
477 (define_expand "zero_extend<mode>di2"
478 [(set (match_operand:DI 0 "gpc_reg_operand" "")
479 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
480 "TARGET_POWERPC64"
481 "")
483 (define_insn "*zero_extend<mode>di2_internal1"
484 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
485 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
486 "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
487 "@
488 l<wd>z%U1%X1 %0,%1
489 rldicl %0,%1,0,<dbits>"
490 [(set_attr_alternative "type"
491 [(if_then_else
492 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
493 (const_string "load_ux")
494 (if_then_else
495 (match_test "update_address_mem (operands[1], VOIDmode)")
496 (const_string "load_u")
497 (const_string "load")))
498 (const_string "*")])])
500 (define_insn "*zero_extend<mode>di2_internal2"
501 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
502 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
503 (const_int 0)))
504 (clobber (match_scratch:DI 2 "=r,r"))]
505 "TARGET_64BIT"
506 "@
507 rldicl. %2,%1,0,<dbits>
508 #"
509 [(set_attr "type" "compare")
510 (set_attr "length" "4,8")])
512 (define_split
513 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
514 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
515 (const_int 0)))
516 (clobber (match_scratch:DI 2 ""))]
517 "TARGET_POWERPC64 && reload_completed"
518 [(set (match_dup 2)
519 (zero_extend:DI (match_dup 1)))
520 (set (match_dup 0)
521 (compare:CC (match_dup 2)
522 (const_int 0)))]
523 "")
525 (define_insn "*zero_extend<mode>di2_internal3"
526 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
527 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
528 (const_int 0)))
529 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
530 (zero_extend:DI (match_dup 1)))]
531 "TARGET_64BIT"
532 "@
533 rldicl. %0,%1,0,<dbits>
534 #"
535 [(set_attr "type" "compare")
536 (set_attr "length" "4,8")])
538 (define_split
539 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
540 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
541 (const_int 0)))
542 (set (match_operand:DI 0 "gpc_reg_operand" "")
543 (zero_extend:DI (match_dup 1)))]
544 "TARGET_POWERPC64 && reload_completed"
545 [(set (match_dup 0)
546 (zero_extend:DI (match_dup 1)))
547 (set (match_dup 2)
548 (compare:CC (match_dup 0)
549 (const_int 0)))]
550 "")
552 (define_insn "*zero_extendsidi2_lfiwzx"
553 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
554 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
555 "TARGET_POWERPC64 && TARGET_LFIWZX"
556 "@
557 lwz%U1%X1 %0,%1
558 rldicl %0,%1,0,32
559 mtvsrwz %x0,%1
560 lfiwzx %0,%y1
561 lxsiwzx %x0,%y1"
562 [(set_attr_alternative "type"
563 [(if_then_else
564 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
565 (const_string "load_ux")
566 (if_then_else
567 (match_test "update_address_mem (operands[1], VOIDmode)")
568 (const_string "load_u")
569 (const_string "load")))
570 (const_string "*")
571 (const_string "mffgpr")
572 (const_string "fpload")
573 (const_string "fpload")])])
575 (define_insn "extendqidi2"
576 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
577 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
578 "TARGET_POWERPC64"
579 "extsb %0,%1"
580 [(set_attr "type" "exts")])
582 (define_insn ""
583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
584 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
585 (const_int 0)))
586 (clobber (match_scratch:DI 2 "=r,r"))]
587 "TARGET_64BIT"
588 "@
589 extsb. %2,%1
590 #"
591 [(set_attr "type" "compare")
592 (set_attr "length" "4,8")])
594 (define_split
595 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
596 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
597 (const_int 0)))
598 (clobber (match_scratch:DI 2 ""))]
599 "TARGET_POWERPC64 && reload_completed"
600 [(set (match_dup 2)
601 (sign_extend:DI (match_dup 1)))
602 (set (match_dup 0)
603 (compare:CC (match_dup 2)
604 (const_int 0)))]
605 "")
607 (define_insn ""
608 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
609 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
610 (const_int 0)))
611 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
612 (sign_extend:DI (match_dup 1)))]
613 "TARGET_64BIT"
614 "@
615 extsb. %0,%1
616 #"
617 [(set_attr "type" "compare")
618 (set_attr "length" "4,8")])
620 (define_split
621 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
622 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
623 (const_int 0)))
624 (set (match_operand:DI 0 "gpc_reg_operand" "")
625 (sign_extend:DI (match_dup 1)))]
626 "TARGET_POWERPC64 && reload_completed"
627 [(set (match_dup 0)
628 (sign_extend:DI (match_dup 1)))
629 (set (match_dup 2)
630 (compare:CC (match_dup 0)
631 (const_int 0)))]
632 "")
634 (define_expand "extendhidi2"
635 [(set (match_operand:DI 0 "gpc_reg_operand" "")
636 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
637 "TARGET_POWERPC64"
638 "")
640 (define_insn ""
641 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
642 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
643 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
644 "@
645 lha%U1%X1 %0,%1
646 extsh %0,%1"
647 [(set_attr_alternative "type"
648 [(if_then_else
649 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
650 (const_string "load_ext_ux")
651 (if_then_else
652 (match_test "update_address_mem (operands[1], VOIDmode)")
653 (const_string "load_ext_u")
654 (const_string "load_ext")))
655 (const_string "exts")])])
657 (define_insn ""
658 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
659 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
660 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
661 "extsh %0,%1"
662 [(set_attr "type" "exts")])
664 (define_insn ""
665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
666 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
667 (const_int 0)))
668 (clobber (match_scratch:DI 2 "=r,r"))]
669 "TARGET_64BIT"
670 "@
671 extsh. %2,%1
672 #"
673 [(set_attr "type" "compare")
674 (set_attr "length" "4,8")])
676 (define_split
677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
678 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
679 (const_int 0)))
680 (clobber (match_scratch:DI 2 ""))]
681 "TARGET_POWERPC64 && reload_completed"
682 [(set (match_dup 2)
683 (sign_extend:DI (match_dup 1)))
684 (set (match_dup 0)
685 (compare:CC (match_dup 2)
686 (const_int 0)))]
687 "")
689 (define_insn ""
690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
691 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
692 (const_int 0)))
693 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
694 (sign_extend:DI (match_dup 1)))]
695 "TARGET_64BIT"
696 "@
697 extsh. %0,%1
698 #"
699 [(set_attr "type" "compare")
700 (set_attr "length" "4,8")])
702 (define_split
703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
704 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
705 (const_int 0)))
706 (set (match_operand:DI 0 "gpc_reg_operand" "")
707 (sign_extend:DI (match_dup 1)))]
708 "TARGET_POWERPC64 && reload_completed"
709 [(set (match_dup 0)
710 (sign_extend:DI (match_dup 1)))
711 (set (match_dup 2)
712 (compare:CC (match_dup 0)
713 (const_int 0)))]
714 "")
716 (define_expand "extendsidi2"
717 [(set (match_operand:DI 0 "gpc_reg_operand" "")
718 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
719 "TARGET_POWERPC64"
720 "")
722 (define_insn "*extendsidi2_lfiwax"
723 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
724 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]
725 "TARGET_POWERPC64 && TARGET_LFIWAX"
726 "@
727 lwa%U1%X1 %0,%1
728 extsw %0,%1
729 mtvsrwa %x0,%1
730 lfiwax %0,%y1
731 lxsiwax %x0,%y1"
732 [(set_attr_alternative "type"
733 [(if_then_else
734 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
735 (const_string "load_ext_ux")
736 (if_then_else
737 (match_test "update_address_mem (operands[1], VOIDmode)")
738 (const_string "load_ext_u")
739 (const_string "load_ext")))
740 (const_string "exts")
741 (const_string "mffgpr")
742 (const_string "fpload")
743 (const_string "fpload")])])
745 (define_insn "*extendsidi2_nocell"
746 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
747 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
748 "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
749 "@
750 lwa%U1%X1 %0,%1
751 extsw %0,%1"
752 [(set_attr_alternative "type"
753 [(if_then_else
754 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
755 (const_string "load_ext_ux")
756 (if_then_else
757 (match_test "update_address_mem (operands[1], VOIDmode)")
758 (const_string "load_ext_u")
759 (const_string "load_ext")))
760 (const_string "exts")])])
762 (define_insn "*extendsidi2_nocell"
763 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
764 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
765 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
766 "extsw %0,%1"
767 [(set_attr "type" "exts")])
769 (define_insn ""
770 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
771 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
772 (const_int 0)))
773 (clobber (match_scratch:DI 2 "=r,r"))]
774 "TARGET_64BIT"
775 "@
776 extsw. %2,%1
777 #"
778 [(set_attr "type" "compare")
779 (set_attr "length" "4,8")])
781 (define_split
782 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
783 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
784 (const_int 0)))
785 (clobber (match_scratch:DI 2 ""))]
786 "TARGET_POWERPC64 && reload_completed"
787 [(set (match_dup 2)
788 (sign_extend:DI (match_dup 1)))
789 (set (match_dup 0)
790 (compare:CC (match_dup 2)
791 (const_int 0)))]
792 "")
794 (define_insn ""
795 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
796 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
797 (const_int 0)))
798 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
799 (sign_extend:DI (match_dup 1)))]
800 "TARGET_64BIT"
801 "@
802 extsw. %0,%1
803 #"
804 [(set_attr "type" "compare")
805 (set_attr "length" "4,8")])
807 (define_split
808 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
809 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
810 (const_int 0)))
811 (set (match_operand:DI 0 "gpc_reg_operand" "")
812 (sign_extend:DI (match_dup 1)))]
813 "TARGET_POWERPC64 && reload_completed"
814 [(set (match_dup 0)
815 (sign_extend:DI (match_dup 1)))
816 (set (match_dup 2)
817 (compare:CC (match_dup 0)
818 (const_int 0)))]
819 "")
821 (define_expand "zero_extendqisi2"
822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
823 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
824 ""
825 "")
827 (define_insn ""
828 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
829 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
830 ""
831 "@
832 lbz%U1%X1 %0,%1
833 rlwinm %0,%1,0,0xff"
834 [(set_attr_alternative "type"
835 [(if_then_else
836 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
837 (const_string "load_ux")
838 (if_then_else
839 (match_test "update_address_mem (operands[1], VOIDmode)")
840 (const_string "load_u")
841 (const_string "load")))
842 (const_string "*")])])
844 (define_insn ""
845 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
846 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
847 (const_int 0)))
848 (clobber (match_scratch:SI 2 "=r,r"))]
849 ""
850 "@
851 andi. %2,%1,0xff
852 #"
853 [(set_attr "type" "fast_compare,compare")
854 (set_attr "length" "4,8")])
856 (define_split
857 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
858 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
859 (const_int 0)))
860 (clobber (match_scratch:SI 2 ""))]
861 "reload_completed"
862 [(set (match_dup 2)
863 (zero_extend:SI (match_dup 1)))
864 (set (match_dup 0)
865 (compare:CC (match_dup 2)
866 (const_int 0)))]
867 "")
869 (define_insn ""
870 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
871 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
872 (const_int 0)))
873 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
874 (zero_extend:SI (match_dup 1)))]
875 ""
876 "@
877 andi. %0,%1,0xff
878 #"
879 [(set_attr "type" "fast_compare,compare")
880 (set_attr "length" "4,8")])
882 (define_split
883 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
884 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
885 (const_int 0)))
886 (set (match_operand:SI 0 "gpc_reg_operand" "")
887 (zero_extend:SI (match_dup 1)))]
888 "reload_completed"
889 [(set (match_dup 0)
890 (zero_extend:SI (match_dup 1)))
891 (set (match_dup 2)
892 (compare:CC (match_dup 0)
893 (const_int 0)))]
894 "")
896 (define_insn "extendqisi2"
897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
898 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
899 ""
900 "extsb %0,%1"
901 [(set_attr "type" "exts")])
903 (define_insn ""
904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
905 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
906 (const_int 0)))
907 (clobber (match_scratch:SI 2 "=r,r"))]
908 ""
909 "@
910 extsb. %2,%1
911 #"
912 [(set_attr "type" "compare")
913 (set_attr "length" "4,8")])
915 (define_split
916 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
917 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
918 (const_int 0)))
919 (clobber (match_scratch:SI 2 ""))]
920 "reload_completed"
921 [(set (match_dup 2)
922 (sign_extend:SI (match_dup 1)))
923 (set (match_dup 0)
924 (compare:CC (match_dup 2)
925 (const_int 0)))]
926 "")
928 (define_insn ""
929 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
930 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
931 (const_int 0)))
932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
933 (sign_extend:SI (match_dup 1)))]
934 ""
935 "@
936 extsb. %0,%1
937 #"
938 [(set_attr "type" "compare")
939 (set_attr "length" "4,8")])
941 (define_split
942 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
943 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
944 (const_int 0)))
945 (set (match_operand:SI 0 "gpc_reg_operand" "")
946 (sign_extend:SI (match_dup 1)))]
947 "reload_completed"
948 [(set (match_dup 0)
949 (sign_extend:SI (match_dup 1)))
950 (set (match_dup 2)
951 (compare:CC (match_dup 0)
952 (const_int 0)))]
953 "")
955 (define_insn ""
956 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
957 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
958 ""
959 "@
960 lbz%U1%X1 %0,%1
961 rlwinm %0,%1,0,0xff"
962 [(set_attr_alternative "type"
963 [(if_then_else
964 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
965 (const_string "load_ux")
966 (if_then_else
967 (match_test "update_address_mem (operands[1], VOIDmode)")
968 (const_string "load_u")
969 (const_string "load")))
970 (const_string "*")])])
972 (define_insn ""
973 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
974 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
975 (const_int 0)))
976 (clobber (match_scratch:HI 2 "=r,r"))]
977 ""
978 "@
979 andi. %2,%1,0xff
980 #"
981 [(set_attr "type" "fast_compare,compare")
982 (set_attr "length" "4,8")])
984 (define_split
985 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
986 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
987 (const_int 0)))
988 (clobber (match_scratch:HI 2 ""))]
989 "reload_completed"
990 [(set (match_dup 2)
991 (zero_extend:HI (match_dup 1)))
992 (set (match_dup 0)
993 (compare:CC (match_dup 2)
994 (const_int 0)))]
995 "")
997 (define_insn ""
998 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
999 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1000 (const_int 0)))
1001 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1002 (zero_extend:HI (match_dup 1)))]
1003 ""
1004 "@
1005 andi. %0,%1,0xff
1006 #"
1007 [(set_attr "type" "fast_compare,compare")
1008 (set_attr "length" "4,8")])
1010 (define_split
1011 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1012 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1013 (const_int 0)))
1014 (set (match_operand:HI 0 "gpc_reg_operand" "")
1015 (zero_extend:HI (match_dup 1)))]
1016 "reload_completed"
1017 [(set (match_dup 0)
1018 (zero_extend:HI (match_dup 1)))
1019 (set (match_dup 2)
1020 (compare:CC (match_dup 0)
1021 (const_int 0)))]
1022 "")
1024 (define_insn "extendqihi2"
1025 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1026 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1027 ""
1028 "extsb %0,%1"
1029 [(set_attr "type" "exts")])
1031 (define_insn ""
1032 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1033 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1034 (const_int 0)))
1035 (clobber (match_scratch:HI 2 "=r,r"))]
1036 ""
1037 "@
1038 extsb. %2,%1
1039 #"
1040 [(set_attr "type" "compare")
1041 (set_attr "length" "4,8")])
1043 (define_split
1044 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1045 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1046 (const_int 0)))
1047 (clobber (match_scratch:HI 2 ""))]
1048 "reload_completed"
1049 [(set (match_dup 2)
1050 (sign_extend:HI (match_dup 1)))
1051 (set (match_dup 0)
1052 (compare:CC (match_dup 2)
1053 (const_int 0)))]
1054 "")
1056 (define_insn ""
1057 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1058 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1059 (const_int 0)))
1060 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1061 (sign_extend:HI (match_dup 1)))]
1062 ""
1063 "@
1064 extsb. %0,%1
1065 #"
1066 [(set_attr "type" "compare")
1067 (set_attr "length" "4,8")])
1069 (define_split
1070 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1071 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1072 (const_int 0)))
1073 (set (match_operand:HI 0 "gpc_reg_operand" "")
1074 (sign_extend:HI (match_dup 1)))]
1075 "reload_completed"
1076 [(set (match_dup 0)
1077 (sign_extend:HI (match_dup 1)))
1078 (set (match_dup 2)
1079 (compare:CC (match_dup 0)
1080 (const_int 0)))]
1081 "")
1083 (define_expand "zero_extendhisi2"
1084 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1085 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1086 ""
1087 "")
1089 (define_insn ""
1090 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1091 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1092 ""
1093 "@
1094 lhz%U1%X1 %0,%1
1095 rlwinm %0,%1,0,0xffff"
1096 [(set_attr_alternative "type"
1097 [(if_then_else
1098 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1099 (const_string "load_ux")
1100 (if_then_else
1101 (match_test "update_address_mem (operands[1], VOIDmode)")
1102 (const_string "load_u")
1103 (const_string "load")))
1104 (const_string "*")])])
1106 (define_insn ""
1107 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1108 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1109 (const_int 0)))
1110 (clobber (match_scratch:SI 2 "=r,r"))]
1111 ""
1112 "@
1113 andi. %2,%1,0xffff
1114 #"
1115 [(set_attr "type" "fast_compare,compare")
1116 (set_attr "length" "4,8")])
1118 (define_split
1119 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1120 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1121 (const_int 0)))
1122 (clobber (match_scratch:SI 2 ""))]
1123 "reload_completed"
1124 [(set (match_dup 2)
1125 (zero_extend:SI (match_dup 1)))
1126 (set (match_dup 0)
1127 (compare:CC (match_dup 2)
1128 (const_int 0)))]
1129 "")
1131 (define_insn ""
1132 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1133 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1134 (const_int 0)))
1135 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1136 (zero_extend:SI (match_dup 1)))]
1137 ""
1138 "@
1139 andi. %0,%1,0xffff
1140 #"
1141 [(set_attr "type" "fast_compare,compare")
1142 (set_attr "length" "4,8")])
1144 (define_split
1145 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1146 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1147 (const_int 0)))
1148 (set (match_operand:SI 0 "gpc_reg_operand" "")
1149 (zero_extend:SI (match_dup 1)))]
1150 "reload_completed"
1151 [(set (match_dup 0)
1152 (zero_extend:SI (match_dup 1)))
1153 (set (match_dup 2)
1154 (compare:CC (match_dup 0)
1155 (const_int 0)))]
1156 "")
1158 (define_expand "extendhisi2"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1160 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1161 ""
1162 "")
1164 (define_insn ""
1165 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1166 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1167 "rs6000_gen_cell_microcode"
1168 "@
1169 lha%U1%X1 %0,%1
1170 extsh %0,%1"
1171 [(set_attr_alternative "type"
1172 [(if_then_else
1173 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1174 (const_string "load_ext_ux")
1175 (if_then_else
1176 (match_test "update_address_mem (operands[1], VOIDmode)")
1177 (const_string "load_ext_u")
1178 (const_string "load_ext")))
1179 (const_string "exts")])])
1181 (define_insn ""
1182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1183 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1184 "!rs6000_gen_cell_microcode"
1185 "extsh %0,%1"
1186 [(set_attr "type" "exts")])
1188 (define_insn ""
1189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1190 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1191 (const_int 0)))
1192 (clobber (match_scratch:SI 2 "=r,r"))]
1193 ""
1194 "@
1195 extsh. %2,%1
1196 #"
1197 [(set_attr "type" "compare")
1198 (set_attr "length" "4,8")])
1200 (define_split
1201 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1202 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1203 (const_int 0)))
1204 (clobber (match_scratch:SI 2 ""))]
1205 "reload_completed"
1206 [(set (match_dup 2)
1207 (sign_extend:SI (match_dup 1)))
1208 (set (match_dup 0)
1209 (compare:CC (match_dup 2)
1210 (const_int 0)))]
1211 "")
1213 (define_insn ""
1214 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1215 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1216 (const_int 0)))
1217 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1218 (sign_extend:SI (match_dup 1)))]
1219 ""
1220 "@
1221 extsh. %0,%1
1222 #"
1223 [(set_attr "type" "compare")
1224 (set_attr "length" "4,8")])
1226 (define_split
1227 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1228 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1229 (const_int 0)))
1230 (set (match_operand:SI 0 "gpc_reg_operand" "")
1231 (sign_extend:SI (match_dup 1)))]
1232 "reload_completed"
1233 [(set (match_dup 0)
1234 (sign_extend:SI (match_dup 1)))
1235 (set (match_dup 2)
1236 (compare:CC (match_dup 0)
1237 (const_int 0)))]
1238 "")
1239 \f
1240 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1242 (define_insn "*macchwc"
1243 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1244 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1245 (match_operand:SI 2 "gpc_reg_operand" "r")
1246 (const_int 16))
1247 (sign_extend:SI
1248 (match_operand:HI 1 "gpc_reg_operand" "r")))
1249 (match_operand:SI 4 "gpc_reg_operand" "0"))
1250 (const_int 0)))
1251 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1252 (plus:SI (mult:SI (ashiftrt:SI
1253 (match_dup 2)
1254 (const_int 16))
1255 (sign_extend:SI
1256 (match_dup 1)))
1257 (match_dup 4)))]
1258 "TARGET_MULHW"
1259 "macchw. %0,%1,%2"
1260 [(set_attr "type" "imul3")])
1262 (define_insn "*macchw"
1263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1264 (plus:SI (mult:SI (ashiftrt:SI
1265 (match_operand:SI 2 "gpc_reg_operand" "r")
1266 (const_int 16))
1267 (sign_extend:SI
1268 (match_operand:HI 1 "gpc_reg_operand" "r")))
1269 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1270 "TARGET_MULHW"
1271 "macchw %0,%1,%2"
1272 [(set_attr "type" "imul3")])
1274 (define_insn "*macchwuc"
1275 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1276 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1277 (match_operand:SI 2 "gpc_reg_operand" "r")
1278 (const_int 16))
1279 (zero_extend:SI
1280 (match_operand:HI 1 "gpc_reg_operand" "r")))
1281 (match_operand:SI 4 "gpc_reg_operand" "0"))
1282 (const_int 0)))
1283 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1284 (plus:SI (mult:SI (lshiftrt:SI
1285 (match_dup 2)
1286 (const_int 16))
1287 (zero_extend:SI
1288 (match_dup 1)))
1289 (match_dup 4)))]
1290 "TARGET_MULHW"
1291 "macchwu. %0,%1,%2"
1292 [(set_attr "type" "imul3")])
1294 (define_insn "*macchwu"
1295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1296 (plus:SI (mult:SI (lshiftrt:SI
1297 (match_operand:SI 2 "gpc_reg_operand" "r")
1298 (const_int 16))
1299 (zero_extend:SI
1300 (match_operand:HI 1 "gpc_reg_operand" "r")))
1301 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1302 "TARGET_MULHW"
1303 "macchwu %0,%1,%2"
1304 [(set_attr "type" "imul3")])
1306 (define_insn "*machhwc"
1307 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1308 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1309 (match_operand:SI 1 "gpc_reg_operand" "%r")
1310 (const_int 16))
1311 (ashiftrt:SI
1312 (match_operand:SI 2 "gpc_reg_operand" "r")
1313 (const_int 16)))
1314 (match_operand:SI 4 "gpc_reg_operand" "0"))
1315 (const_int 0)))
1316 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1317 (plus:SI (mult:SI (ashiftrt:SI
1318 (match_dup 1)
1319 (const_int 16))
1320 (ashiftrt:SI
1321 (match_dup 2)
1322 (const_int 16)))
1323 (match_dup 4)))]
1324 "TARGET_MULHW"
1325 "machhw. %0,%1,%2"
1326 [(set_attr "type" "imul3")])
1328 (define_insn "*machhw"
1329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1330 (plus:SI (mult:SI (ashiftrt:SI
1331 (match_operand:SI 1 "gpc_reg_operand" "%r")
1332 (const_int 16))
1333 (ashiftrt:SI
1334 (match_operand:SI 2 "gpc_reg_operand" "r")
1335 (const_int 16)))
1336 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1337 "TARGET_MULHW"
1338 "machhw %0,%1,%2"
1339 [(set_attr "type" "imul3")])
1341 (define_insn "*machhwuc"
1342 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1343 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1344 (match_operand:SI 1 "gpc_reg_operand" "%r")
1345 (const_int 16))
1346 (lshiftrt:SI
1347 (match_operand:SI 2 "gpc_reg_operand" "r")
1348 (const_int 16)))
1349 (match_operand:SI 4 "gpc_reg_operand" "0"))
1350 (const_int 0)))
1351 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1352 (plus:SI (mult:SI (lshiftrt:SI
1353 (match_dup 1)
1354 (const_int 16))
1355 (lshiftrt:SI
1356 (match_dup 2)
1357 (const_int 16)))
1358 (match_dup 4)))]
1359 "TARGET_MULHW"
1360 "machhwu. %0,%1,%2"
1361 [(set_attr "type" "imul3")])
1363 (define_insn "*machhwu"
1364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1365 (plus:SI (mult:SI (lshiftrt:SI
1366 (match_operand:SI 1 "gpc_reg_operand" "%r")
1367 (const_int 16))
1368 (lshiftrt:SI
1369 (match_operand:SI 2 "gpc_reg_operand" "r")
1370 (const_int 16)))
1371 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1372 "TARGET_MULHW"
1373 "machhwu %0,%1,%2"
1374 [(set_attr "type" "imul3")])
1376 (define_insn "*maclhwc"
1377 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1378 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1379 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1380 (sign_extend:SI
1381 (match_operand:HI 2 "gpc_reg_operand" "r")))
1382 (match_operand:SI 4 "gpc_reg_operand" "0"))
1383 (const_int 0)))
1384 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1385 (plus:SI (mult:SI (sign_extend:SI
1386 (match_dup 1))
1387 (sign_extend:SI
1388 (match_dup 2)))
1389 (match_dup 4)))]
1390 "TARGET_MULHW"
1391 "maclhw. %0,%1,%2"
1392 [(set_attr "type" "imul3")])
1394 (define_insn "*maclhw"
1395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (plus:SI (mult:SI (sign_extend:SI
1397 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1398 (sign_extend:SI
1399 (match_operand:HI 2 "gpc_reg_operand" "r")))
1400 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1401 "TARGET_MULHW"
1402 "maclhw %0,%1,%2"
1403 [(set_attr "type" "imul3")])
1405 (define_insn "*maclhwuc"
1406 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1407 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1408 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1409 (zero_extend:SI
1410 (match_operand:HI 2 "gpc_reg_operand" "r")))
1411 (match_operand:SI 4 "gpc_reg_operand" "0"))
1412 (const_int 0)))
1413 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1414 (plus:SI (mult:SI (zero_extend:SI
1415 (match_dup 1))
1416 (zero_extend:SI
1417 (match_dup 2)))
1418 (match_dup 4)))]
1419 "TARGET_MULHW"
1420 "maclhwu. %0,%1,%2"
1421 [(set_attr "type" "imul3")])
1423 (define_insn "*maclhwu"
1424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1425 (plus:SI (mult:SI (zero_extend:SI
1426 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1427 (zero_extend:SI
1428 (match_operand:HI 2 "gpc_reg_operand" "r")))
1429 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1430 "TARGET_MULHW"
1431 "maclhwu %0,%1,%2"
1432 [(set_attr "type" "imul3")])
1434 (define_insn "*nmacchwc"
1435 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1436 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1437 (mult:SI (ashiftrt:SI
1438 (match_operand:SI 2 "gpc_reg_operand" "r")
1439 (const_int 16))
1440 (sign_extend:SI
1441 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1442 (const_int 0)))
1443 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1444 (minus:SI (match_dup 4)
1445 (mult:SI (ashiftrt:SI
1446 (match_dup 2)
1447 (const_int 16))
1448 (sign_extend:SI
1449 (match_dup 1)))))]
1450 "TARGET_MULHW"
1451 "nmacchw. %0,%1,%2"
1452 [(set_attr "type" "imul3")])
1454 (define_insn "*nmacchw"
1455 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1456 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1457 (mult:SI (ashiftrt:SI
1458 (match_operand:SI 2 "gpc_reg_operand" "r")
1459 (const_int 16))
1460 (sign_extend:SI
1461 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1462 "TARGET_MULHW"
1463 "nmacchw %0,%1,%2"
1464 [(set_attr "type" "imul3")])
1466 (define_insn "*nmachhwc"
1467 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1468 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1469 (mult:SI (ashiftrt:SI
1470 (match_operand:SI 1 "gpc_reg_operand" "%r")
1471 (const_int 16))
1472 (ashiftrt:SI
1473 (match_operand:SI 2 "gpc_reg_operand" "r")
1474 (const_int 16))))
1475 (const_int 0)))
1476 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1477 (minus:SI (match_dup 4)
1478 (mult:SI (ashiftrt:SI
1479 (match_dup 1)
1480 (const_int 16))
1481 (ashiftrt:SI
1482 (match_dup 2)
1483 (const_int 16)))))]
1484 "TARGET_MULHW"
1485 "nmachhw. %0,%1,%2"
1486 [(set_attr "type" "imul3")])
1488 (define_insn "*nmachhw"
1489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1490 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1491 (mult:SI (ashiftrt:SI
1492 (match_operand:SI 1 "gpc_reg_operand" "%r")
1493 (const_int 16))
1494 (ashiftrt:SI
1495 (match_operand:SI 2 "gpc_reg_operand" "r")
1496 (const_int 16)))))]
1497 "TARGET_MULHW"
1498 "nmachhw %0,%1,%2"
1499 [(set_attr "type" "imul3")])
1501 (define_insn "*nmaclhwc"
1502 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1503 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1504 (mult:SI (sign_extend:SI
1505 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1506 (sign_extend:SI
1507 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1508 (const_int 0)))
1509 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1510 (minus:SI (match_dup 4)
1511 (mult:SI (sign_extend:SI
1512 (match_dup 1))
1513 (sign_extend:SI
1514 (match_dup 2)))))]
1515 "TARGET_MULHW"
1516 "nmaclhw. %0,%1,%2"
1517 [(set_attr "type" "imul3")])
1519 (define_insn "*nmaclhw"
1520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1521 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1522 (mult:SI (sign_extend:SI
1523 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1524 (sign_extend:SI
1525 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1526 "TARGET_MULHW"
1527 "nmaclhw %0,%1,%2"
1528 [(set_attr "type" "imul3")])
1530 (define_insn "*mulchwc"
1531 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1532 (compare:CC (mult:SI (ashiftrt:SI
1533 (match_operand:SI 2 "gpc_reg_operand" "r")
1534 (const_int 16))
1535 (sign_extend:SI
1536 (match_operand:HI 1 "gpc_reg_operand" "r")))
1537 (const_int 0)))
1538 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1539 (mult:SI (ashiftrt:SI
1540 (match_dup 2)
1541 (const_int 16))
1542 (sign_extend:SI
1543 (match_dup 1))))]
1544 "TARGET_MULHW"
1545 "mulchw. %0,%1,%2"
1546 [(set_attr "type" "imul3")])
1548 (define_insn "*mulchw"
1549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1550 (mult:SI (ashiftrt:SI
1551 (match_operand:SI 2 "gpc_reg_operand" "r")
1552 (const_int 16))
1553 (sign_extend:SI
1554 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1555 "TARGET_MULHW"
1556 "mulchw %0,%1,%2"
1557 [(set_attr "type" "imul3")])
1559 (define_insn "*mulchwuc"
1560 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1561 (compare:CC (mult:SI (lshiftrt:SI
1562 (match_operand:SI 2 "gpc_reg_operand" "r")
1563 (const_int 16))
1564 (zero_extend:SI
1565 (match_operand:HI 1 "gpc_reg_operand" "r")))
1566 (const_int 0)))
1567 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1568 (mult:SI (lshiftrt:SI
1569 (match_dup 2)
1570 (const_int 16))
1571 (zero_extend:SI
1572 (match_dup 1))))]
1573 "TARGET_MULHW"
1574 "mulchwu. %0,%1,%2"
1575 [(set_attr "type" "imul3")])
1577 (define_insn "*mulchwu"
1578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1579 (mult:SI (lshiftrt:SI
1580 (match_operand:SI 2 "gpc_reg_operand" "r")
1581 (const_int 16))
1582 (zero_extend:SI
1583 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1584 "TARGET_MULHW"
1585 "mulchwu %0,%1,%2"
1586 [(set_attr "type" "imul3")])
1588 (define_insn "*mulhhwc"
1589 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1590 (compare:CC (mult:SI (ashiftrt:SI
1591 (match_operand:SI 1 "gpc_reg_operand" "%r")
1592 (const_int 16))
1593 (ashiftrt:SI
1594 (match_operand:SI 2 "gpc_reg_operand" "r")
1595 (const_int 16)))
1596 (const_int 0)))
1597 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1598 (mult:SI (ashiftrt:SI
1599 (match_dup 1)
1600 (const_int 16))
1601 (ashiftrt:SI
1602 (match_dup 2)
1603 (const_int 16))))]
1604 "TARGET_MULHW"
1605 "mulhhw. %0,%1,%2"
1606 [(set_attr "type" "imul3")])
1608 (define_insn "*mulhhw"
1609 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1610 (mult:SI (ashiftrt:SI
1611 (match_operand:SI 1 "gpc_reg_operand" "%r")
1612 (const_int 16))
1613 (ashiftrt:SI
1614 (match_operand:SI 2 "gpc_reg_operand" "r")
1615 (const_int 16))))]
1616 "TARGET_MULHW"
1617 "mulhhw %0,%1,%2"
1618 [(set_attr "type" "imul3")])
1620 (define_insn "*mulhhwuc"
1621 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1622 (compare:CC (mult:SI (lshiftrt:SI
1623 (match_operand:SI 1 "gpc_reg_operand" "%r")
1624 (const_int 16))
1625 (lshiftrt:SI
1626 (match_operand:SI 2 "gpc_reg_operand" "r")
1627 (const_int 16)))
1628 (const_int 0)))
1629 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1630 (mult:SI (lshiftrt:SI
1631 (match_dup 1)
1632 (const_int 16))
1633 (lshiftrt:SI
1634 (match_dup 2)
1635 (const_int 16))))]
1636 "TARGET_MULHW"
1637 "mulhhwu. %0,%1,%2"
1638 [(set_attr "type" "imul3")])
1640 (define_insn "*mulhhwu"
1641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1642 (mult:SI (lshiftrt:SI
1643 (match_operand:SI 1 "gpc_reg_operand" "%r")
1644 (const_int 16))
1645 (lshiftrt:SI
1646 (match_operand:SI 2 "gpc_reg_operand" "r")
1647 (const_int 16))))]
1648 "TARGET_MULHW"
1649 "mulhhwu %0,%1,%2"
1650 [(set_attr "type" "imul3")])
1652 (define_insn "*mullhwc"
1653 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1654 (compare:CC (mult:SI (sign_extend:SI
1655 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1656 (sign_extend:SI
1657 (match_operand:HI 2 "gpc_reg_operand" "r")))
1658 (const_int 0)))
1659 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1660 (mult:SI (sign_extend:SI
1661 (match_dup 1))
1662 (sign_extend:SI
1663 (match_dup 2))))]
1664 "TARGET_MULHW"
1665 "mullhw. %0,%1,%2"
1666 [(set_attr "type" "imul3")])
1668 (define_insn "*mullhw"
1669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1670 (mult:SI (sign_extend:SI
1671 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1672 (sign_extend:SI
1673 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1674 "TARGET_MULHW"
1675 "mullhw %0,%1,%2"
1676 [(set_attr "type" "imul3")])
1678 (define_insn "*mullhwuc"
1679 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1680 (compare:CC (mult:SI (zero_extend:SI
1681 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1682 (zero_extend:SI
1683 (match_operand:HI 2 "gpc_reg_operand" "r")))
1684 (const_int 0)))
1685 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1686 (mult:SI (zero_extend:SI
1687 (match_dup 1))
1688 (zero_extend:SI
1689 (match_dup 2))))]
1690 "TARGET_MULHW"
1691 "mullhwu. %0,%1,%2"
1692 [(set_attr "type" "imul3")])
1694 (define_insn "*mullhwu"
1695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1696 (mult:SI (zero_extend:SI
1697 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1698 (zero_extend:SI
1699 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1700 "TARGET_MULHW"
1701 "mullhwu %0,%1,%2"
1702 [(set_attr "type" "imul3")])
1703 \f
1704 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1705 (define_insn "dlmzb"
1706 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1707 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1708 (match_operand:SI 2 "gpc_reg_operand" "r")]
1709 UNSPEC_DLMZB_CR))
1710 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1711 (unspec:SI [(match_dup 1)
1712 (match_dup 2)]
1713 UNSPEC_DLMZB))]
1714 "TARGET_DLMZB"
1715 "dlmzb. %0,%1,%2")
1717 (define_expand "strlensi"
1718 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1719 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1720 (match_operand:QI 2 "const_int_operand" "")
1721 (match_operand 3 "const_int_operand" "")]
1722 UNSPEC_DLMZB_STRLEN))
1723 (clobber (match_scratch:CC 4 "=x"))]
1724 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1725 {
1726 rtx result = operands[0];
1727 rtx src = operands[1];
1728 rtx search_char = operands[2];
1729 rtx align = operands[3];
1730 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1731 rtx loop_label, end_label, mem, cr0, cond;
1732 if (search_char != const0_rtx
1733 || GET_CODE (align) != CONST_INT
1734 || INTVAL (align) < 8)
1735 FAIL;
1736 word1 = gen_reg_rtx (SImode);
1737 word2 = gen_reg_rtx (SImode);
1738 scratch_dlmzb = gen_reg_rtx (SImode);
1739 scratch_string = gen_reg_rtx (Pmode);
1740 loop_label = gen_label_rtx ();
1741 end_label = gen_label_rtx ();
1742 addr = force_reg (Pmode, XEXP (src, 0));
1743 emit_move_insn (scratch_string, addr);
1744 emit_label (loop_label);
1745 mem = change_address (src, SImode, scratch_string);
1746 emit_move_insn (word1, mem);
1747 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1748 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1749 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1750 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1751 emit_jump_insn (gen_rtx_SET (VOIDmode,
1752 pc_rtx,
1753 gen_rtx_IF_THEN_ELSE (VOIDmode,
1754 cond,
1755 gen_rtx_LABEL_REF
1756 (VOIDmode,
1757 end_label),
1758 pc_rtx)));
1759 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1760 emit_jump_insn (gen_rtx_SET (VOIDmode,
1761 pc_rtx,
1762 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1763 emit_barrier ();
1764 emit_label (end_label);
1765 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1766 emit_insn (gen_subsi3 (result, scratch_string, addr));
1767 emit_insn (gen_subsi3 (result, result, const1_rtx));
1768 DONE;
1769 })
1770 \f
1771 ;; Fixed-point arithmetic insns.
1773 (define_expand "add<mode>3"
1774 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1775 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1776 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1777 ""
1778 {
1779 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1780 {
1781 if (non_short_cint_operand (operands[2], DImode))
1782 FAIL;
1783 }
1784 else if (GET_CODE (operands[2]) == CONST_INT
1785 && ! add_operand (operands[2], <MODE>mode))
1786 {
1787 rtx tmp = ((!can_create_pseudo_p ()
1788 || rtx_equal_p (operands[0], operands[1]))
1789 ? operands[0] : gen_reg_rtx (<MODE>mode));
1791 HOST_WIDE_INT val = INTVAL (operands[2]);
1792 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1793 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1795 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1796 FAIL;
1798 /* The ordering here is important for the prolog expander.
1799 When space is allocated from the stack, adding 'low' first may
1800 produce a temporary deallocation (which would be bad). */
1801 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1802 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1803 DONE;
1804 }
1805 })
1807 ;; Discourage ai/addic because of carry but provide it in an alternative
1808 ;; allowing register zero as source.
1809 (define_insn "*add<mode>3_internal1"
1810 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1811 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1812 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1813 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1814 "@
1815 add %0,%1,%2
1816 addi %0,%1,%2
1817 addic %0,%1,%2
1818 addis %0,%1,%v2"
1819 [(set_attr "length" "4,4,4,4")])
1821 (define_insn "addsi3_high"
1822 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1823 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1824 (high:SI (match_operand 2 "" ""))))]
1825 "TARGET_MACHO && !TARGET_64BIT"
1826 "addis %0,%1,ha16(%2)"
1827 [(set_attr "length" "4")])
1829 (define_insn "*add<mode>3_internal2"
1830 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1831 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1832 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1833 (const_int 0)))
1834 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1835 ""
1836 "@
1837 add. %3,%1,%2
1838 addic. %3,%1,%2
1839 #
1840 #"
1841 [(set_attr "type" "fast_compare,compare,compare,compare")
1842 (set_attr "length" "4,4,8,8")])
1844 (define_split
1845 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1846 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1847 (match_operand:GPR 2 "reg_or_short_operand" ""))
1848 (const_int 0)))
1849 (clobber (match_scratch:GPR 3 ""))]
1850 "reload_completed"
1851 [(set (match_dup 3)
1852 (plus:GPR (match_dup 1)
1853 (match_dup 2)))
1854 (set (match_dup 0)
1855 (compare:CC (match_dup 3)
1856 (const_int 0)))]
1857 "")
1859 (define_insn "*add<mode>3_internal3"
1860 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1861 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1862 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1863 (const_int 0)))
1864 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1865 (plus:P (match_dup 1)
1866 (match_dup 2)))]
1867 ""
1868 "@
1869 add. %0,%1,%2
1870 addic. %0,%1,%2
1871 #
1872 #"
1873 [(set_attr "type" "fast_compare,compare,compare,compare")
1874 (set_attr "length" "4,4,8,8")])
1876 (define_split
1877 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1878 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1879 (match_operand:P 2 "reg_or_short_operand" ""))
1880 (const_int 0)))
1881 (set (match_operand:P 0 "gpc_reg_operand" "")
1882 (plus:P (match_dup 1) (match_dup 2)))]
1883 "reload_completed"
1884 [(set (match_dup 0)
1885 (plus:P (match_dup 1)
1886 (match_dup 2)))
1887 (set (match_dup 3)
1888 (compare:CC (match_dup 0)
1889 (const_int 0)))]
1890 "")
1892 ;; Split an add that we can't do in one insn into two insns, each of which
1893 ;; does one 16-bit part. This is used by combine. Note that the low-order
1894 ;; add should be last in case the result gets used in an address.
1896 (define_split
1897 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1898 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1899 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1900 ""
1901 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1902 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1903 {
1904 HOST_WIDE_INT val = INTVAL (operands[2]);
1905 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1906 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1908 operands[4] = GEN_INT (low);
1909 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1910 operands[3] = GEN_INT (rest);
1911 else if (can_create_pseudo_p ())
1912 {
1913 operands[3] = gen_reg_rtx (DImode);
1914 emit_move_insn (operands[3], operands[2]);
1915 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1916 DONE;
1917 }
1918 else
1919 FAIL;
1920 })
1922 (define_expand "one_cmpl<mode>2"
1923 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1924 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1925 ""
1926 {
1927 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1928 {
1929 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
1930 DONE;
1931 }
1932 })
1934 (define_insn "*one_cmpl<mode>2"
1935 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1936 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1937 ""
1938 "nor %0,%1,%1")
1940 (define_insn ""
1941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1942 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1943 (const_int 0)))
1944 (clobber (match_scratch:P 2 "=r,r"))]
1945 ""
1946 "@
1947 nor. %2,%1,%1
1948 #"
1949 [(set_attr "type" "fast_compare,compare")
1950 (set_attr "length" "4,8")])
1952 (define_split
1953 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1954 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1955 (const_int 0)))
1956 (clobber (match_scratch:P 2 ""))]
1957 "reload_completed"
1958 [(set (match_dup 2)
1959 (not:P (match_dup 1)))
1960 (set (match_dup 0)
1961 (compare:CC (match_dup 2)
1962 (const_int 0)))]
1963 "")
1965 (define_insn ""
1966 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1967 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1968 (const_int 0)))
1969 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1970 (not:P (match_dup 1)))]
1971 ""
1972 "@
1973 nor. %0,%1,%1
1974 #"
1975 [(set_attr "type" "fast_compare,compare")
1976 (set_attr "length" "4,8")])
1978 (define_split
1979 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1980 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1981 (const_int 0)))
1982 (set (match_operand:P 0 "gpc_reg_operand" "")
1983 (not:P (match_dup 1)))]
1984 "reload_completed"
1985 [(set (match_dup 0)
1986 (not:P (match_dup 1)))
1987 (set (match_dup 2)
1988 (compare:CC (match_dup 0)
1989 (const_int 0)))]
1990 "")
1992 (define_insn ""
1993 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1994 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1995 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1996 ""
1997 "@
1998 subf %0,%2,%1
1999 subfic %0,%2,%1")
2001 (define_insn ""
2002 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2003 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2004 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2005 (const_int 0)))
2006 (clobber (match_scratch:P 3 "=r,r"))]
2007 ""
2008 "@
2009 subf. %3,%2,%1
2010 #"
2011 [(set_attr "type" "fast_compare")
2012 (set_attr "length" "4,8")])
2014 (define_split
2015 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2016 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2017 (match_operand:P 2 "gpc_reg_operand" ""))
2018 (const_int 0)))
2019 (clobber (match_scratch:P 3 ""))]
2020 "reload_completed"
2021 [(set (match_dup 3)
2022 (minus:P (match_dup 1)
2023 (match_dup 2)))
2024 (set (match_dup 0)
2025 (compare:CC (match_dup 3)
2026 (const_int 0)))]
2027 "")
2029 (define_insn ""
2030 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2031 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2032 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2033 (const_int 0)))
2034 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2035 (minus:P (match_dup 1)
2036 (match_dup 2)))]
2037 ""
2038 "@
2039 subf. %0,%2,%1
2040 #"
2041 [(set_attr "type" "fast_compare")
2042 (set_attr "length" "4,8")])
2044 (define_split
2045 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2046 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2047 (match_operand:P 2 "gpc_reg_operand" ""))
2048 (const_int 0)))
2049 (set (match_operand:P 0 "gpc_reg_operand" "")
2050 (minus:P (match_dup 1)
2051 (match_dup 2)))]
2052 "reload_completed"
2053 [(set (match_dup 0)
2054 (minus:P (match_dup 1)
2055 (match_dup 2)))
2056 (set (match_dup 3)
2057 (compare:CC (match_dup 0)
2058 (const_int 0)))]
2059 "")
2061 (define_expand "sub<mode>3"
2062 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2063 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
2064 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
2065 ""
2066 "
2067 {
2068 if (GET_CODE (operands[2]) == CONST_INT)
2069 {
2070 emit_insn (gen_add<mode>3 (operands[0], operands[1],
2071 negate_rtx (<MODE>mode, operands[2])));
2072 DONE;
2073 }
2074 }")
2076 (define_expand "neg<mode>2"
2077 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2078 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2079 ""
2080 "")
2082 (define_insn "*neg<mode>2_internal"
2083 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2084 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2085 ""
2086 "neg %0,%1")
2088 (define_insn ""
2089 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2090 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2091 (const_int 0)))
2092 (clobber (match_scratch:P 2 "=r,r"))]
2093 ""
2094 "@
2095 neg. %2,%1
2096 #"
2097 [(set_attr "type" "fast_compare")
2098 (set_attr "length" "4,8")])
2100 (define_split
2101 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2102 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2103 (const_int 0)))
2104 (clobber (match_scratch:P 2 ""))]
2105 "reload_completed"
2106 [(set (match_dup 2)
2107 (neg:P (match_dup 1)))
2108 (set (match_dup 0)
2109 (compare:CC (match_dup 2)
2110 (const_int 0)))]
2111 "")
2113 (define_insn ""
2114 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2115 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2116 (const_int 0)))
2117 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2118 (neg:P (match_dup 1)))]
2119 ""
2120 "@
2121 neg. %0,%1
2122 #"
2123 [(set_attr "type" "fast_compare")
2124 (set_attr "length" "4,8")])
2126 (define_split
2127 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2128 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2129 (const_int 0)))
2130 (set (match_operand:P 0 "gpc_reg_operand" "")
2131 (neg:P (match_dup 1)))]
2132 "reload_completed"
2133 [(set (match_dup 0)
2134 (neg:P (match_dup 1)))
2135 (set (match_dup 2)
2136 (compare:CC (match_dup 0)
2137 (const_int 0)))]
2138 "")
2140 (define_insn "clz<mode>2"
2141 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2142 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2143 ""
2144 "cntlz<wd> %0,%1"
2145 [(set_attr "type" "cntlz")])
2147 (define_expand "ctz<mode>2"
2148 [(set (match_dup 2)
2149 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2150 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2151 (match_dup 2)))
2152 (clobber (scratch:CC))])
2153 (set (match_dup 4) (clz:GPR (match_dup 3)))
2154 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2155 (minus:GPR (match_dup 5) (match_dup 4)))]
2156 ""
2157 {
2158 operands[2] = gen_reg_rtx (<MODE>mode);
2159 operands[3] = gen_reg_rtx (<MODE>mode);
2160 operands[4] = gen_reg_rtx (<MODE>mode);
2161 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2162 })
2164 (define_expand "ffs<mode>2"
2165 [(set (match_dup 2)
2166 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2167 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2168 (match_dup 2)))
2169 (clobber (scratch:CC))])
2170 (set (match_dup 4) (clz:GPR (match_dup 3)))
2171 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2172 (minus:GPR (match_dup 5) (match_dup 4)))]
2173 ""
2174 {
2175 operands[2] = gen_reg_rtx (<MODE>mode);
2176 operands[3] = gen_reg_rtx (<MODE>mode);
2177 operands[4] = gen_reg_rtx (<MODE>mode);
2178 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2179 })
2181 (define_insn "popcntb<mode>2"
2182 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2183 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2184 UNSPEC_POPCNTB))]
2185 "TARGET_POPCNTB"
2186 "popcntb %0,%1"
2187 [(set_attr "length" "4")
2188 (set_attr "type" "popcnt")])
2190 (define_insn "popcntd<mode>2"
2191 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2192 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2193 "TARGET_POPCNTD"
2194 "popcnt<wd> %0,%1"
2195 [(set_attr "length" "4")
2196 (set_attr "type" "popcnt")])
2198 (define_expand "popcount<mode>2"
2199 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2200 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2201 "TARGET_POPCNTB || TARGET_POPCNTD"
2202 {
2203 rs6000_emit_popcount (operands[0], operands[1]);
2204 DONE;
2205 })
2207 (define_insn "parity<mode>2_cmpb"
2208 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2209 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2210 "TARGET_CMPB && TARGET_POPCNTB"
2211 "prty<wd> %0,%1"
2212 [(set_attr "length" "4")
2213 (set_attr "type" "popcnt")])
2215 (define_expand "parity<mode>2"
2216 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2217 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2218 "TARGET_POPCNTB"
2219 {
2220 rs6000_emit_parity (operands[0], operands[1]);
2221 DONE;
2222 })
2224 ;; Since the hardware zeros the upper part of the register, save generating the
2225 ;; AND immediate if we are converting to unsigned
2226 (define_insn "*bswaphi2_extenddi"
2227 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2228 (zero_extend:DI
2229 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2230 "TARGET_POWERPC64"
2231 "lhbrx %0,%y1"
2232 [(set_attr "length" "4")
2233 (set_attr "type" "load")])
2235 (define_insn "*bswaphi2_extendsi"
2236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2237 (zero_extend:SI
2238 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2239 ""
2240 "lhbrx %0,%y1"
2241 [(set_attr "length" "4")
2242 (set_attr "type" "load")])
2244 (define_expand "bswaphi2"
2245 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2246 (bswap:HI
2247 (match_operand:HI 1 "reg_or_mem_operand" "")))
2248 (clobber (match_scratch:SI 2 ""))])]
2249 ""
2250 {
2251 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2252 operands[1] = force_reg (HImode, operands[1]);
2253 })
2255 (define_insn "bswaphi2_internal"
2256 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2257 (bswap:HI
2258 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2259 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2260 ""
2261 "@
2262 lhbrx %0,%y1
2263 sthbrx %1,%y0
2264 #"
2265 [(set_attr "length" "4,4,12")
2266 (set_attr "type" "load,store,*")])
2268 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2269 ;; correct for -mlittle as well as -mbig.
2270 (define_split
2271 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2272 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2273 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2274 "reload_completed"
2275 [(set (match_dup 3)
2276 (zero_extract:SI (match_dup 4)
2277 (const_int 8)
2278 (const_int 16)))
2279 (set (match_dup 2)
2280 (and:SI (ashift:SI (match_dup 4)
2281 (const_int 8))
2282 (const_int 65280))) ;; 0xff00
2283 (set (match_dup 3)
2284 (ior:SI (match_dup 3)
2285 (match_dup 2)))]
2286 "
2287 {
2288 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2289 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2290 }")
2292 (define_insn "*bswapsi2_extenddi"
2293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2294 (zero_extend:DI
2295 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2296 "TARGET_POWERPC64"
2297 "lwbrx %0,%y1"
2298 [(set_attr "length" "4")
2299 (set_attr "type" "load")])
2301 (define_expand "bswapsi2"
2302 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2303 (bswap:SI
2304 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2305 ""
2306 {
2307 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2308 operands[1] = force_reg (SImode, operands[1]);
2309 })
2311 (define_insn "*bswapsi2_internal"
2312 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2313 (bswap:SI
2314 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2315 ""
2316 "@
2317 lwbrx %0,%y1
2318 stwbrx %1,%y0
2319 #"
2320 [(set_attr "length" "4,4,12")
2321 (set_attr "type" "load,store,*")])
2323 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2324 ;; zero_extract insns do not change for -mlittle.
2325 (define_split
2326 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2327 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2328 "reload_completed"
2329 [(set (match_dup 0)
2330 (rotate:SI (match_dup 1) (const_int 8)))
2331 (set (zero_extract:SI (match_dup 0)
2332 (const_int 8)
2333 (const_int 0))
2334 (match_dup 1))
2335 (set (zero_extract:SI (match_dup 0)
2336 (const_int 8)
2337 (const_int 16))
2338 (rotate:SI (match_dup 1)
2339 (const_int 16)))]
2340 "")
2342 (define_expand "bswapdi2"
2343 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2344 (bswap:DI
2345 (match_operand:DI 1 "reg_or_mem_operand" "")))
2346 (clobber (match_scratch:DI 2 ""))
2347 (clobber (match_scratch:DI 3 ""))
2348 (clobber (match_scratch:DI 4 ""))])]
2349 ""
2350 {
2351 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2352 operands[1] = force_reg (DImode, operands[1]);
2354 if (!TARGET_POWERPC64)
2355 {
2356 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2357 that uses 64-bit registers needs the same scratch registers as 64-bit
2358 mode. */
2359 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2360 DONE;
2361 }
2362 })
2364 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2365 (define_insn "*bswapdi2_ldbrx"
2366 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2367 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2368 (clobber (match_scratch:DI 2 "=X,X,&r"))
2369 (clobber (match_scratch:DI 3 "=X,X,&r"))
2370 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2371 "TARGET_POWERPC64 && TARGET_LDBRX
2372 && (REG_P (operands[0]) || REG_P (operands[1]))"
2373 "@
2374 ldbrx %0,%y1
2375 stdbrx %1,%y0
2376 #"
2377 [(set_attr "length" "4,4,36")
2378 (set_attr "type" "load,store,*")])
2380 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2381 (define_insn "*bswapdi2_64bit"
2382 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2383 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2384 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2385 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2386 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2387 "TARGET_POWERPC64 && !TARGET_LDBRX
2388 && (REG_P (operands[0]) || REG_P (operands[1]))
2389 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2390 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2391 "#"
2392 [(set_attr "length" "16,12,36")])
2394 (define_split
2395 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2396 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2397 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2398 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2399 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2400 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2401 [(const_int 0)]
2402 "
2403 {
2404 rtx dest = operands[0];
2405 rtx src = operands[1];
2406 rtx op2 = operands[2];
2407 rtx op3 = operands[3];
2408 rtx op4 = operands[4];
2409 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2410 BYTES_BIG_ENDIAN ? 4 : 0);
2411 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2412 BYTES_BIG_ENDIAN ? 4 : 0);
2413 rtx addr1;
2414 rtx addr2;
2415 rtx word_high;
2416 rtx word_low;
2418 addr1 = XEXP (src, 0);
2419 if (GET_CODE (addr1) == PLUS)
2420 {
2421 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2422 if (TARGET_AVOID_XFORM)
2423 {
2424 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2425 addr2 = op2;
2426 }
2427 else
2428 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2429 }
2430 else if (TARGET_AVOID_XFORM)
2431 {
2432 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2433 addr2 = op2;
2434 }
2435 else
2436 {
2437 emit_move_insn (op2, GEN_INT (4));
2438 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2439 }
2441 if (BYTES_BIG_ENDIAN)
2442 {
2443 word_high = change_address (src, SImode, addr1);
2444 word_low = change_address (src, SImode, addr2);
2445 }
2446 else
2447 {
2448 word_high = change_address (src, SImode, addr2);
2449 word_low = change_address (src, SImode, addr1);
2450 }
2452 emit_insn (gen_bswapsi2 (op3_32, word_low));
2453 emit_insn (gen_bswapsi2 (op4_32, word_high));
2454 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2455 emit_insn (gen_iordi3 (dest, dest, op4));
2456 }")
2458 (define_split
2459 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2460 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2461 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2462 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2463 (clobber (match_operand:DI 4 "" ""))]
2464 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2465 [(const_int 0)]
2466 "
2467 {
2468 rtx dest = operands[0];
2469 rtx src = operands[1];
2470 rtx op2 = operands[2];
2471 rtx op3 = operands[3];
2472 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2473 BYTES_BIG_ENDIAN ? 4 : 0);
2474 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2475 BYTES_BIG_ENDIAN ? 4 : 0);
2476 rtx addr1;
2477 rtx addr2;
2478 rtx word_high;
2479 rtx word_low;
2481 addr1 = XEXP (dest, 0);
2482 if (GET_CODE (addr1) == PLUS)
2483 {
2484 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2485 if (TARGET_AVOID_XFORM)
2486 {
2487 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2488 addr2 = op2;
2489 }
2490 else
2491 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2492 }
2493 else if (TARGET_AVOID_XFORM)
2494 {
2495 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2496 addr2 = op2;
2497 }
2498 else
2499 {
2500 emit_move_insn (op2, GEN_INT (4));
2501 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2502 }
2504 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2505 if (BYTES_BIG_ENDIAN)
2506 {
2507 word_high = change_address (dest, SImode, addr1);
2508 word_low = change_address (dest, SImode, addr2);
2509 }
2510 else
2511 {
2512 word_high = change_address (dest, SImode, addr2);
2513 word_low = change_address (dest, SImode, addr1);
2514 }
2515 emit_insn (gen_bswapsi2 (word_high, src_si));
2516 emit_insn (gen_bswapsi2 (word_low, op3_si));
2517 }")
2519 (define_split
2520 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2521 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2522 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2523 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2524 (clobber (match_operand:DI 4 "" ""))]
2525 "TARGET_POWERPC64 && reload_completed"
2526 [(const_int 0)]
2527 "
2528 {
2529 rtx dest = operands[0];
2530 rtx src = operands[1];
2531 rtx op2 = operands[2];
2532 rtx op3 = operands[3];
2533 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2534 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2535 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2536 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2537 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2539 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2540 emit_insn (gen_bswapsi2 (dest_si, src_si));
2541 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2542 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2543 emit_insn (gen_iordi3 (dest, dest, op3));
2544 }")
2546 (define_insn "bswapdi2_32bit"
2547 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2548 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2549 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2550 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2551 "#"
2552 [(set_attr "length" "16,12,36")])
2554 (define_split
2555 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2556 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2557 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2558 "!TARGET_POWERPC64 && reload_completed"
2559 [(const_int 0)]
2560 "
2561 {
2562 rtx dest = operands[0];
2563 rtx src = operands[1];
2564 rtx op2 = operands[2];
2565 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2566 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2567 rtx addr1;
2568 rtx addr2;
2569 rtx word1;
2570 rtx word2;
2572 addr1 = XEXP (src, 0);
2573 if (GET_CODE (addr1) == PLUS)
2574 {
2575 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2576 if (TARGET_AVOID_XFORM)
2577 {
2578 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2579 addr2 = op2;
2580 }
2581 else
2582 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2583 }
2584 else if (TARGET_AVOID_XFORM)
2585 {
2586 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2587 addr2 = op2;
2588 }
2589 else
2590 {
2591 emit_move_insn (op2, GEN_INT (4));
2592 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2593 }
2595 word1 = change_address (src, SImode, addr1);
2596 word2 = change_address (src, SImode, addr2);
2598 emit_insn (gen_bswapsi2 (dest2, word1));
2599 emit_insn (gen_bswapsi2 (dest1, word2));
2600 }")
2602 (define_split
2603 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2604 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2605 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2606 "!TARGET_POWERPC64 && reload_completed"
2607 [(const_int 0)]
2608 "
2609 {
2610 rtx dest = operands[0];
2611 rtx src = operands[1];
2612 rtx op2 = operands[2];
2613 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2614 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2615 rtx addr1;
2616 rtx addr2;
2617 rtx word1;
2618 rtx word2;
2620 addr1 = XEXP (dest, 0);
2621 if (GET_CODE (addr1) == PLUS)
2622 {
2623 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2624 if (TARGET_AVOID_XFORM)
2625 {
2626 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2627 addr2 = op2;
2628 }
2629 else
2630 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2631 }
2632 else if (TARGET_AVOID_XFORM)
2633 {
2634 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2635 addr2 = op2;
2636 }
2637 else
2638 {
2639 emit_move_insn (op2, GEN_INT (4));
2640 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2641 }
2643 word1 = change_address (dest, SImode, addr1);
2644 word2 = change_address (dest, SImode, addr2);
2646 emit_insn (gen_bswapsi2 (word2, src1));
2647 emit_insn (gen_bswapsi2 (word1, src2));
2648 }")
2650 (define_split
2651 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2652 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2653 (clobber (match_operand:SI 2 "" ""))]
2654 "!TARGET_POWERPC64 && reload_completed"
2655 [(const_int 0)]
2656 "
2657 {
2658 rtx dest = operands[0];
2659 rtx src = operands[1];
2660 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2661 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2662 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2663 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2665 emit_insn (gen_bswapsi2 (dest1, src2));
2666 emit_insn (gen_bswapsi2 (dest2, src1));
2667 }")
2669 (define_insn "mulsi3"
2670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2671 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2672 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2673 ""
2674 "@
2675 mullw %0,%1,%2
2676 mulli %0,%1,%2"
2677 [(set (attr "type")
2678 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2679 (const_string "imul3")
2680 (match_operand:SI 2 "short_cint_operand" "")
2681 (const_string "imul2")]
2682 (const_string "imul")))])
2684 (define_insn "*mulsi3_internal1"
2685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2686 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2687 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2688 (const_int 0)))
2689 (clobber (match_scratch:SI 3 "=r,r"))]
2690 "TARGET_32BIT"
2691 "@
2692 mullw. %3,%1,%2
2693 #"
2694 [(set_attr "type" "imul_compare")
2695 (set_attr "length" "4,8")])
2697 (define_split
2698 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2699 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2700 (match_operand:SI 2 "gpc_reg_operand" ""))
2701 (const_int 0)))
2702 (clobber (match_scratch:SI 3 ""))]
2703 "TARGET_32BIT && reload_completed"
2704 [(set (match_dup 3)
2705 (mult:SI (match_dup 1) (match_dup 2)))
2706 (set (match_dup 0)
2707 (compare:CC (match_dup 3)
2708 (const_int 0)))]
2709 "")
2711 (define_insn "*mulsi3_internal2"
2712 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2713 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2714 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2715 (const_int 0)))
2716 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2717 (mult:SI (match_dup 1) (match_dup 2)))]
2718 "TARGET_32BIT"
2719 "@
2720 mullw. %0,%1,%2
2721 #"
2722 [(set_attr "type" "imul_compare")
2723 (set_attr "length" "4,8")])
2725 (define_split
2726 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2727 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2728 (match_operand:SI 2 "gpc_reg_operand" ""))
2729 (const_int 0)))
2730 (set (match_operand:SI 0 "gpc_reg_operand" "")
2731 (mult:SI (match_dup 1) (match_dup 2)))]
2732 "TARGET_32BIT && reload_completed"
2733 [(set (match_dup 0)
2734 (mult:SI (match_dup 1) (match_dup 2)))
2735 (set (match_dup 3)
2736 (compare:CC (match_dup 0)
2737 (const_int 0)))]
2738 "")
2741 (define_insn "udiv<mode>3"
2742 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2743 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2744 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2745 ""
2746 "div<wd>u %0,%1,%2"
2747 [(set (attr "type")
2748 (cond [(match_operand:SI 0 "" "")
2749 (const_string "idiv")]
2750 (const_string "ldiv")))])
2753 ;; For powers of two we can do srai/aze for divide and then adjust for
2754 ;; modulus. If it isn't a power of two, force operands into register and do
2755 ;; a normal divide.
2756 (define_expand "div<mode>3"
2757 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2758 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2759 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2760 ""
2761 {
2762 if (GET_CODE (operands[2]) != CONST_INT
2763 || INTVAL (operands[2]) <= 0
2764 || exact_log2 (INTVAL (operands[2])) < 0)
2765 operands[2] = force_reg (<MODE>mode, operands[2]);
2766 })
2768 (define_insn "*div<mode>3"
2769 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2770 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2771 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2772 ""
2773 "div<wd> %0,%1,%2"
2774 [(set (attr "type")
2775 (cond [(match_operand:SI 0 "" "")
2776 (const_string "idiv")]
2777 (const_string "ldiv")))])
2779 (define_expand "mod<mode>3"
2780 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2781 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2782 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2783 ""
2784 "
2785 {
2786 int i;
2787 rtx temp1;
2788 rtx temp2;
2790 if (GET_CODE (operands[2]) != CONST_INT
2791 || INTVAL (operands[2]) <= 0
2792 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2793 FAIL;
2795 temp1 = gen_reg_rtx (<MODE>mode);
2796 temp2 = gen_reg_rtx (<MODE>mode);
2798 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2799 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2800 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2801 DONE;
2802 }")
2804 (define_insn ""
2805 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2806 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2807 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2808 ""
2809 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2810 [(set_attr "type" "two")
2811 (set_attr "length" "8")])
2813 (define_insn ""
2814 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2815 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2816 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2817 (const_int 0)))
2818 (clobber (match_scratch:P 3 "=r,r"))]
2819 ""
2820 "@
2821 sra<wd>i %3,%1,%p2\;addze. %3,%3
2822 #"
2823 [(set_attr "type" "compare")
2824 (set_attr "length" "8,12")
2825 (set_attr "cell_micro" "not")])
2827 (define_split
2828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2829 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2830 (match_operand:GPR 2 "exact_log2_cint_operand"
2831 ""))
2832 (const_int 0)))
2833 (clobber (match_scratch:GPR 3 ""))]
2834 "reload_completed"
2835 [(set (match_dup 3)
2836 (div:<MODE> (match_dup 1) (match_dup 2)))
2837 (set (match_dup 0)
2838 (compare:CC (match_dup 3)
2839 (const_int 0)))]
2840 "")
2842 (define_insn ""
2843 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2844 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2845 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2846 (const_int 0)))
2847 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2848 (div:P (match_dup 1) (match_dup 2)))]
2849 ""
2850 "@
2851 sra<wd>i %0,%1,%p2\;addze. %0,%0
2852 #"
2853 [(set_attr "type" "compare")
2854 (set_attr "length" "8,12")
2855 (set_attr "cell_micro" "not")])
2857 (define_split
2858 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2859 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2860 (match_operand:GPR 2 "exact_log2_cint_operand"
2861 ""))
2862 (const_int 0)))
2863 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2864 (div:GPR (match_dup 1) (match_dup 2)))]
2865 "reload_completed"
2866 [(set (match_dup 0)
2867 (div:<MODE> (match_dup 1) (match_dup 2)))
2868 (set (match_dup 3)
2869 (compare:CC (match_dup 0)
2870 (const_int 0)))]
2871 "")
2872 \f
2873 ;; Logical instructions
2874 ;; The logical instructions are mostly combined by using match_operator,
2875 ;; but the plain AND insns are somewhat different because there is no
2876 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2877 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2879 (define_expand "andsi3"
2880 [(parallel
2881 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2882 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2883 (match_operand:SI 2 "and_operand" "")))
2884 (clobber (match_scratch:CC 3 ""))])]
2885 ""
2886 "")
2888 (define_insn "andsi3_mc"
2889 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2890 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2891 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2892 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2893 "rs6000_gen_cell_microcode"
2894 "@
2895 and %0,%1,%2
2896 rlwinm %0,%1,0,%m2,%M2
2897 andi. %0,%1,%b2
2898 andis. %0,%1,%u2"
2899 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2901 (define_insn "andsi3_nomc"
2902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2903 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2904 (match_operand:SI 2 "and_operand" "?r,T")))
2905 (clobber (match_scratch:CC 3 "=X,X"))]
2906 "!rs6000_gen_cell_microcode"
2907 "@
2908 and %0,%1,%2
2909 rlwinm %0,%1,0,%m2,%M2")
2911 (define_insn "andsi3_internal0_nomc"
2912 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2913 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2914 (match_operand:SI 2 "and_operand" "?r,T")))]
2915 "!rs6000_gen_cell_microcode"
2916 "@
2917 and %0,%1,%2
2918 rlwinm %0,%1,0,%m2,%M2")
2921 ;; Note to set cr's other than cr0 we do the and immediate and then
2922 ;; the test again -- this avoids a mfcr which on the higher end
2923 ;; machines causes an execution serialization
2925 (define_insn "*andsi3_internal2_mc"
2926 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2927 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2928 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2929 (const_int 0)))
2930 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2931 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2932 "TARGET_32BIT && rs6000_gen_cell_microcode"
2933 "@
2934 and. %3,%1,%2
2935 andi. %3,%1,%b2
2936 andis. %3,%1,%u2
2937 rlwinm. %3,%1,0,%m2,%M2
2938 #
2939 #
2940 #
2941 #"
2942 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2943 compare,compare,compare,compare")
2944 (set_attr "length" "4,4,4,4,8,8,8,8")])
2946 (define_insn "*andsi3_internal3_mc"
2947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2948 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2949 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2950 (const_int 0)))
2951 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2952 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2953 "TARGET_64BIT && rs6000_gen_cell_microcode"
2954 "@
2955 #
2956 andi. %3,%1,%b2
2957 andis. %3,%1,%u2
2958 rlwinm. %3,%1,0,%m2,%M2
2959 #
2960 #
2961 #
2962 #"
2963 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2964 compare,compare,compare")
2965 (set_attr "length" "8,4,4,4,8,8,8,8")])
2967 (define_split
2968 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2969 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2970 (match_operand:GPR 2 "and_operand" ""))
2971 (const_int 0)))
2972 (clobber (match_scratch:GPR 3 ""))
2973 (clobber (match_scratch:CC 4 ""))]
2974 "reload_completed"
2975 [(parallel [(set (match_dup 3)
2976 (and:<MODE> (match_dup 1)
2977 (match_dup 2)))
2978 (clobber (match_dup 4))])
2979 (set (match_dup 0)
2980 (compare:CC (match_dup 3)
2981 (const_int 0)))]
2982 "")
2984 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2985 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2987 (define_split
2988 [(set (match_operand:CC 0 "cc_reg_operand" "")
2989 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2990 (match_operand:SI 2 "gpc_reg_operand" ""))
2991 (const_int 0)))
2992 (clobber (match_scratch:SI 3 ""))
2993 (clobber (match_scratch:CC 4 ""))]
2994 "TARGET_POWERPC64 && reload_completed"
2995 [(parallel [(set (match_dup 3)
2996 (and:SI (match_dup 1)
2997 (match_dup 2)))
2998 (clobber (match_dup 4))])
2999 (set (match_dup 0)
3000 (compare:CC (match_dup 3)
3001 (const_int 0)))]
3002 "")
3004 (define_insn "*andsi3_internal4"
3005 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3006 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3007 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3008 (const_int 0)))
3009 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3010 (and:SI (match_dup 1)
3011 (match_dup 2)))
3012 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3013 "TARGET_32BIT && rs6000_gen_cell_microcode"
3014 "@
3015 and. %0,%1,%2
3016 andi. %0,%1,%b2
3017 andis. %0,%1,%u2
3018 rlwinm. %0,%1,0,%m2,%M2
3019 #
3020 #
3021 #
3022 #"
3023 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3024 compare,compare,compare,compare")
3025 (set_attr "length" "4,4,4,4,8,8,8,8")])
3027 (define_insn "*andsi3_internal5_mc"
3028 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3029 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3030 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3031 (const_int 0)))
3032 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3033 (and:SI (match_dup 1)
3034 (match_dup 2)))
3035 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3036 "TARGET_64BIT && rs6000_gen_cell_microcode"
3037 "@
3038 #
3039 andi. %0,%1,%b2
3040 andis. %0,%1,%u2
3041 rlwinm. %0,%1,0,%m2,%M2
3042 #
3043 #
3044 #
3045 #"
3046 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3047 compare,compare,compare")
3048 (set_attr "length" "8,4,4,4,8,8,8,8")])
3050 (define_split
3051 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3052 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3053 (match_operand:SI 2 "and_operand" ""))
3054 (const_int 0)))
3055 (set (match_operand:SI 0 "gpc_reg_operand" "")
3056 (and:SI (match_dup 1)
3057 (match_dup 2)))
3058 (clobber (match_scratch:CC 4 ""))]
3059 "reload_completed"
3060 [(parallel [(set (match_dup 0)
3061 (and:SI (match_dup 1)
3062 (match_dup 2)))
3063 (clobber (match_dup 4))])
3064 (set (match_dup 3)
3065 (compare:CC (match_dup 0)
3066 (const_int 0)))]
3067 "")
3069 (define_split
3070 [(set (match_operand:CC 3 "cc_reg_operand" "")
3071 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3072 (match_operand:SI 2 "gpc_reg_operand" ""))
3073 (const_int 0)))
3074 (set (match_operand:SI 0 "gpc_reg_operand" "")
3075 (and:SI (match_dup 1)
3076 (match_dup 2)))
3077 (clobber (match_scratch:CC 4 ""))]
3078 "TARGET_POWERPC64 && reload_completed"
3079 [(parallel [(set (match_dup 0)
3080 (and:SI (match_dup 1)
3081 (match_dup 2)))
3082 (clobber (match_dup 4))])
3083 (set (match_dup 3)
3084 (compare:CC (match_dup 0)
3085 (const_int 0)))]
3086 "")
3088 ;; Handle the PowerPC64 rlwinm corner case
3090 (define_insn_and_split "*andsi3_internal6"
3091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3092 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3093 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3094 "TARGET_POWERPC64"
3095 "#"
3096 "TARGET_POWERPC64"
3097 [(set (match_dup 0)
3098 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3099 (match_dup 4)))
3100 (set (match_dup 0)
3101 (rotate:SI (match_dup 0) (match_dup 5)))]
3102 "
3103 {
3104 int mb = extract_MB (operands[2]);
3105 int me = extract_ME (operands[2]);
3106 operands[3] = GEN_INT (me + 1);
3107 operands[5] = GEN_INT (32 - (me + 1));
3108 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3109 }"
3110 [(set_attr "length" "8")])
3112 (define_expand "iorsi3"
3113 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3114 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3115 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3116 ""
3117 "
3118 {
3119 if (GET_CODE (operands[2]) == CONST_INT
3120 && ! logical_operand (operands[2], SImode))
3121 {
3122 HOST_WIDE_INT value = INTVAL (operands[2]);
3123 rtx tmp = ((!can_create_pseudo_p ()
3124 || rtx_equal_p (operands[0], operands[1]))
3125 ? operands[0] : gen_reg_rtx (SImode));
3127 emit_insn (gen_iorsi3 (tmp, operands[1],
3128 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3129 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3130 DONE;
3131 }
3132 }")
3134 (define_expand "xorsi3"
3135 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3136 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3137 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3138 ""
3139 "
3140 {
3141 if (GET_CODE (operands[2]) == CONST_INT
3142 && ! logical_operand (operands[2], SImode))
3143 {
3144 HOST_WIDE_INT value = INTVAL (operands[2]);
3145 rtx tmp = ((!can_create_pseudo_p ()
3146 || rtx_equal_p (operands[0], operands[1]))
3147 ? operands[0] : gen_reg_rtx (SImode));
3149 emit_insn (gen_xorsi3 (tmp, operands[1],
3150 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3151 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3152 DONE;
3153 }
3154 }")
3156 (define_insn "*boolsi3_internal1"
3157 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3158 (match_operator:SI 3 "boolean_or_operator"
3159 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3160 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3161 ""
3162 "@
3163 %q3 %0,%1,%2
3164 %q3i %0,%1,%b2
3165 %q3is %0,%1,%u2")
3167 (define_insn "*boolsi3_internal2"
3168 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3169 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3170 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3171 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3172 (const_int 0)))
3173 (clobber (match_scratch:SI 3 "=r,r"))]
3174 "TARGET_32BIT"
3175 "@
3176 %q4. %3,%1,%2
3177 #"
3178 [(set_attr "type" "fast_compare,compare")
3179 (set_attr "length" "4,8")])
3181 (define_split
3182 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3183 (compare:CC (match_operator:SI 4 "boolean_operator"
3184 [(match_operand:SI 1 "gpc_reg_operand" "")
3185 (match_operand:SI 2 "gpc_reg_operand" "")])
3186 (const_int 0)))
3187 (clobber (match_scratch:SI 3 ""))]
3188 "TARGET_32BIT && reload_completed"
3189 [(set (match_dup 3) (match_dup 4))
3190 (set (match_dup 0)
3191 (compare:CC (match_dup 3)
3192 (const_int 0)))]
3193 "")
3195 (define_insn "*boolsi3_internal3"
3196 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3197 (compare:CC (match_operator:SI 4 "boolean_operator"
3198 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3199 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3200 (const_int 0)))
3201 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3202 (match_dup 4))]
3203 "TARGET_32BIT"
3204 "@
3205 %q4. %0,%1,%2
3206 #"
3207 [(set_attr "type" "fast_compare,compare")
3208 (set_attr "length" "4,8")])
3210 (define_split
3211 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3212 (compare:CC (match_operator:SI 4 "boolean_operator"
3213 [(match_operand:SI 1 "gpc_reg_operand" "")
3214 (match_operand:SI 2 "gpc_reg_operand" "")])
3215 (const_int 0)))
3216 (set (match_operand:SI 0 "gpc_reg_operand" "")
3217 (match_dup 4))]
3218 "TARGET_32BIT && reload_completed"
3219 [(set (match_dup 0) (match_dup 4))
3220 (set (match_dup 3)
3221 (compare:CC (match_dup 0)
3222 (const_int 0)))]
3223 "")
3225 ;; Split a logical operation that we can't do in one insn into two insns,
3226 ;; each of which does one 16-bit part. This is used by combine.
3228 (define_split
3229 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3230 (match_operator:SI 3 "boolean_or_operator"
3231 [(match_operand:SI 1 "gpc_reg_operand" "")
3232 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3233 ""
3234 [(set (match_dup 0) (match_dup 4))
3235 (set (match_dup 0) (match_dup 5))]
3236 "
3237 {
3238 rtx i;
3239 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3240 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3241 operands[1], i);
3242 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3243 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3244 operands[0], i);
3245 }")
3247 (define_insn "*boolcsi3_internal1"
3248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3249 (match_operator:SI 3 "boolean_operator"
3250 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3251 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3252 ""
3253 "%q3 %0,%2,%1")
3255 (define_insn "*boolcsi3_internal2"
3256 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3257 (compare:CC (match_operator:SI 4 "boolean_operator"
3258 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3259 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3260 (const_int 0)))
3261 (clobber (match_scratch:SI 3 "=r,r"))]
3262 "TARGET_32BIT"
3263 "@
3264 %q4. %3,%2,%1
3265 #"
3266 [(set_attr "type" "compare")
3267 (set_attr "length" "4,8")])
3269 (define_split
3270 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3271 (compare:CC (match_operator:SI 4 "boolean_operator"
3272 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3273 (match_operand:SI 2 "gpc_reg_operand" "")])
3274 (const_int 0)))
3275 (clobber (match_scratch:SI 3 ""))]
3276 "TARGET_32BIT && reload_completed"
3277 [(set (match_dup 3) (match_dup 4))
3278 (set (match_dup 0)
3279 (compare:CC (match_dup 3)
3280 (const_int 0)))]
3281 "")
3283 (define_insn "*boolcsi3_internal3"
3284 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3285 (compare:CC (match_operator:SI 4 "boolean_operator"
3286 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3287 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3288 (const_int 0)))
3289 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3290 (match_dup 4))]
3291 "TARGET_32BIT"
3292 "@
3293 %q4. %0,%2,%1
3294 #"
3295 [(set_attr "type" "compare")
3296 (set_attr "length" "4,8")])
3298 (define_split
3299 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3300 (compare:CC (match_operator:SI 4 "boolean_operator"
3301 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3302 (match_operand:SI 2 "gpc_reg_operand" "")])
3303 (const_int 0)))
3304 (set (match_operand:SI 0 "gpc_reg_operand" "")
3305 (match_dup 4))]
3306 "TARGET_32BIT && reload_completed"
3307 [(set (match_dup 0) (match_dup 4))
3308 (set (match_dup 3)
3309 (compare:CC (match_dup 0)
3310 (const_int 0)))]
3311 "")
3313 (define_insn "*boolccsi3_internal1"
3314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3315 (match_operator:SI 3 "boolean_operator"
3316 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3317 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3318 ""
3319 "%q3 %0,%1,%2")
3321 (define_insn "*boolccsi3_internal2"
3322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3323 (compare:CC (match_operator:SI 4 "boolean_operator"
3324 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3325 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3326 (const_int 0)))
3327 (clobber (match_scratch:SI 3 "=r,r"))]
3328 "TARGET_32BIT"
3329 "@
3330 %q4. %3,%1,%2
3331 #"
3332 [(set_attr "type" "fast_compare,compare")
3333 (set_attr "length" "4,8")])
3335 (define_split
3336 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3337 (compare:CC (match_operator:SI 4 "boolean_operator"
3338 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3339 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3340 (const_int 0)))
3341 (clobber (match_scratch:SI 3 ""))]
3342 "TARGET_32BIT && reload_completed"
3343 [(set (match_dup 3) (match_dup 4))
3344 (set (match_dup 0)
3345 (compare:CC (match_dup 3)
3346 (const_int 0)))]
3347 "")
3349 (define_insn "*boolccsi3_internal3"
3350 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3351 (compare:CC (match_operator:SI 4 "boolean_operator"
3352 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3353 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3354 (const_int 0)))
3355 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3356 (match_dup 4))]
3357 "TARGET_32BIT"
3358 "@
3359 %q4. %0,%1,%2
3360 #"
3361 [(set_attr "type" "fast_compare,compare")
3362 (set_attr "length" "4,8")])
3364 (define_split
3365 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3366 (compare:CC (match_operator:SI 4 "boolean_operator"
3367 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3368 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3369 (const_int 0)))
3370 (set (match_operand:SI 0 "gpc_reg_operand" "")
3371 (match_dup 4))]
3372 "TARGET_32BIT && reload_completed"
3373 [(set (match_dup 0) (match_dup 4))
3374 (set (match_dup 3)
3375 (compare:CC (match_dup 0)
3376 (const_int 0)))]
3377 "")
3378 \f
3379 ;; Rotate and shift insns, in all their variants. These support shifts,
3380 ;; field inserts and extracts, and various combinations thereof.
3381 (define_expand "insv"
3382 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3383 (match_operand:SI 1 "const_int_operand" "")
3384 (match_operand:SI 2 "const_int_operand" ""))
3385 (match_operand 3 "gpc_reg_operand" ""))]
3386 ""
3387 "
3388 {
3389 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3390 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3391 compiler if the address of the structure is taken later. Likewise, do
3392 not handle invalid E500 subregs. */
3393 if (GET_CODE (operands[0]) == SUBREG
3394 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3395 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3396 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3397 FAIL;
3399 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3400 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3401 operands[3]));
3402 else
3403 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3404 operands[3]));
3405 DONE;
3406 }")
3408 (define_insn "insvsi_internal"
3409 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3410 (match_operand:SI 1 "const_int_operand" "i")
3411 (match_operand:SI 2 "const_int_operand" "i"))
3412 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3413 ""
3414 "*
3415 {
3416 int start = INTVAL (operands[2]) & 31;
3417 int size = INTVAL (operands[1]) & 31;
3419 operands[4] = GEN_INT (32 - start - size);
3420 operands[1] = GEN_INT (start + size - 1);
3421 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3422 }"
3423 [(set_attr "type" "insert_word")])
3425 (define_insn "*insvsi_internal1"
3426 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3427 (match_operand:SI 1 "const_int_operand" "i")
3428 (match_operand:SI 2 "const_int_operand" "i"))
3429 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3430 (match_operand:SI 4 "const_int_operand" "i")))]
3431 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3432 "*
3433 {
3434 int shift = INTVAL (operands[4]) & 31;
3435 int start = INTVAL (operands[2]) & 31;
3436 int size = INTVAL (operands[1]) & 31;
3438 operands[4] = GEN_INT (shift - start - size);
3439 operands[1] = GEN_INT (start + size - 1);
3440 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3441 }"
3442 [(set_attr "type" "insert_word")])
3444 (define_insn "*insvsi_internal2"
3445 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3446 (match_operand:SI 1 "const_int_operand" "i")
3447 (match_operand:SI 2 "const_int_operand" "i"))
3448 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3449 (match_operand:SI 4 "const_int_operand" "i")))]
3450 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3451 "*
3452 {
3453 int shift = INTVAL (operands[4]) & 31;
3454 int start = INTVAL (operands[2]) & 31;
3455 int size = INTVAL (operands[1]) & 31;
3457 operands[4] = GEN_INT (32 - shift - start - size);
3458 operands[1] = GEN_INT (start + size - 1);
3459 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3460 }"
3461 [(set_attr "type" "insert_word")])
3463 (define_insn "*insvsi_internal3"
3464 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3465 (match_operand:SI 1 "const_int_operand" "i")
3466 (match_operand:SI 2 "const_int_operand" "i"))
3467 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3468 (match_operand:SI 4 "const_int_operand" "i")))]
3469 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3470 "*
3471 {
3472 int shift = INTVAL (operands[4]) & 31;
3473 int start = INTVAL (operands[2]) & 31;
3474 int size = INTVAL (operands[1]) & 31;
3476 operands[4] = GEN_INT (32 - shift - start - size);
3477 operands[1] = GEN_INT (start + size - 1);
3478 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3479 }"
3480 [(set_attr "type" "insert_word")])
3482 (define_insn "*insvsi_internal4"
3483 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3484 (match_operand:SI 1 "const_int_operand" "i")
3485 (match_operand:SI 2 "const_int_operand" "i"))
3486 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3487 (match_operand:SI 4 "const_int_operand" "i")
3488 (match_operand:SI 5 "const_int_operand" "i")))]
3489 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3490 "*
3491 {
3492 int extract_start = INTVAL (operands[5]) & 31;
3493 int extract_size = INTVAL (operands[4]) & 31;
3494 int insert_start = INTVAL (operands[2]) & 31;
3495 int insert_size = INTVAL (operands[1]) & 31;
3497 /* Align extract field with insert field */
3498 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3499 operands[1] = GEN_INT (insert_start + insert_size - 1);
3500 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3501 }"
3502 [(set_attr "type" "insert_word")])
3504 ;; combine patterns for rlwimi
3505 (define_insn "*insvsi_internal5"
3506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3507 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3508 (match_operand:SI 1 "mask_operand" "i"))
3509 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3510 (match_operand:SI 2 "const_int_operand" "i"))
3511 (match_operand:SI 5 "mask_operand" "i"))))]
3512 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3513 "*
3514 {
3515 int me = extract_ME(operands[5]);
3516 int mb = extract_MB(operands[5]);
3517 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3518 operands[2] = GEN_INT(mb);
3519 operands[1] = GEN_INT(me);
3520 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3521 }"
3522 [(set_attr "type" "insert_word")])
3524 (define_insn "*insvsi_internal6"
3525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3526 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3527 (match_operand:SI 2 "const_int_operand" "i"))
3528 (match_operand:SI 5 "mask_operand" "i"))
3529 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3530 (match_operand:SI 1 "mask_operand" "i"))))]
3531 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3532 "*
3533 {
3534 int me = extract_ME(operands[5]);
3535 int mb = extract_MB(operands[5]);
3536 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3537 operands[2] = GEN_INT(mb);
3538 operands[1] = GEN_INT(me);
3539 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3540 }"
3541 [(set_attr "type" "insert_word")])
3543 (define_insn "insvdi_internal"
3544 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3545 (match_operand:SI 1 "const_int_operand" "i")
3546 (match_operand:SI 2 "const_int_operand" "i"))
3547 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3548 "TARGET_POWERPC64"
3549 "*
3550 {
3551 int start = INTVAL (operands[2]) & 63;
3552 int size = INTVAL (operands[1]) & 63;
3554 operands[1] = GEN_INT (64 - start - size);
3555 return \"rldimi %0,%3,%H1,%H2\";
3556 }"
3557 [(set_attr "type" "insert_dword")])
3559 (define_insn "*insvdi_internal2"
3560 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3561 (match_operand:SI 1 "const_int_operand" "i")
3562 (match_operand:SI 2 "const_int_operand" "i"))
3563 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3564 (match_operand:SI 4 "const_int_operand" "i")))]
3565 "TARGET_POWERPC64
3566 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3567 "*
3568 {
3569 int shift = INTVAL (operands[4]) & 63;
3570 int start = (INTVAL (operands[2]) & 63) - 32;
3571 int size = INTVAL (operands[1]) & 63;
3573 operands[4] = GEN_INT (64 - shift - start - size);
3574 operands[2] = GEN_INT (start);
3575 operands[1] = GEN_INT (start + size - 1);
3576 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3577 }")
3579 (define_insn "*insvdi_internal3"
3580 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3581 (match_operand:SI 1 "const_int_operand" "i")
3582 (match_operand:SI 2 "const_int_operand" "i"))
3583 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3584 (match_operand:SI 4 "const_int_operand" "i")))]
3585 "TARGET_POWERPC64
3586 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3587 "*
3588 {
3589 int shift = INTVAL (operands[4]) & 63;
3590 int start = (INTVAL (operands[2]) & 63) - 32;
3591 int size = INTVAL (operands[1]) & 63;
3593 operands[4] = GEN_INT (64 - shift - start - size);
3594 operands[2] = GEN_INT (start);
3595 operands[1] = GEN_INT (start + size - 1);
3596 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3597 }")
3599 (define_expand "extzv"
3600 [(set (match_operand 0 "gpc_reg_operand" "")
3601 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3602 (match_operand:SI 2 "const_int_operand" "")
3603 (match_operand:SI 3 "const_int_operand" "")))]
3604 ""
3605 "
3606 {
3607 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3608 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3609 compiler if the address of the structure is taken later. */
3610 if (GET_CODE (operands[0]) == SUBREG
3611 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3612 FAIL;
3614 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3615 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3616 operands[3]));
3617 else
3618 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3619 operands[3]));
3620 DONE;
3621 }")
3623 (define_insn "extzvsi_internal"
3624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3625 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3626 (match_operand:SI 2 "const_int_operand" "i")
3627 (match_operand:SI 3 "const_int_operand" "i")))]
3628 ""
3629 "*
3630 {
3631 int start = INTVAL (operands[3]) & 31;
3632 int size = INTVAL (operands[2]) & 31;
3634 if (start + size >= 32)
3635 operands[3] = const0_rtx;
3636 else
3637 operands[3] = GEN_INT (start + size);
3638 return \"rlwinm %0,%1,%3,%s2,31\";
3639 }")
3641 (define_insn "*extzvsi_internal1"
3642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3643 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3644 (match_operand:SI 2 "const_int_operand" "i,i")
3645 (match_operand:SI 3 "const_int_operand" "i,i"))
3646 (const_int 0)))
3647 (clobber (match_scratch:SI 4 "=r,r"))]
3648 ""
3649 "*
3650 {
3651 int start = INTVAL (operands[3]) & 31;
3652 int size = INTVAL (operands[2]) & 31;
3654 /* Force split for non-cc0 compare. */
3655 if (which_alternative == 1)
3656 return \"#\";
3658 /* If the bit-field being tested fits in the upper or lower half of a
3659 word, it is possible to use andiu. or andil. to test it. This is
3660 useful because the condition register set-use delay is smaller for
3661 andi[ul]. than for rlinm. This doesn't work when the starting bit
3662 position is 0 because the LT and GT bits may be set wrong. */
3664 if ((start > 0 && start + size <= 16) || start >= 16)
3665 {
3666 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3667 - (1 << (16 - (start & 15) - size))));
3668 if (start < 16)
3669 return \"andis. %4,%1,%3\";
3670 else
3671 return \"andi. %4,%1,%3\";
3672 }
3674 if (start + size >= 32)
3675 operands[3] = const0_rtx;
3676 else
3677 operands[3] = GEN_INT (start + size);
3678 return \"rlwinm. %4,%1,%3,%s2,31\";
3679 }"
3680 [(set_attr "type" "delayed_compare")
3681 (set_attr "length" "4,8")])
3683 (define_split
3684 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3685 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3686 (match_operand:SI 2 "const_int_operand" "")
3687 (match_operand:SI 3 "const_int_operand" ""))
3688 (const_int 0)))
3689 (clobber (match_scratch:SI 4 ""))]
3690 "reload_completed"
3691 [(set (match_dup 4)
3692 (zero_extract:SI (match_dup 1) (match_dup 2)
3693 (match_dup 3)))
3694 (set (match_dup 0)
3695 (compare:CC (match_dup 4)
3696 (const_int 0)))]
3697 "")
3699 (define_insn "*extzvsi_internal2"
3700 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3701 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3702 (match_operand:SI 2 "const_int_operand" "i,i")
3703 (match_operand:SI 3 "const_int_operand" "i,i"))
3704 (const_int 0)))
3705 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3706 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3707 ""
3708 "*
3709 {
3710 int start = INTVAL (operands[3]) & 31;
3711 int size = INTVAL (operands[2]) & 31;
3713 /* Force split for non-cc0 compare. */
3714 if (which_alternative == 1)
3715 return \"#\";
3717 /* Since we are using the output value, we can't ignore any need for
3718 a shift. The bit-field must end at the LSB. */
3719 if (start >= 16 && start + size == 32)
3720 {
3721 operands[3] = GEN_INT ((1 << size) - 1);
3722 return \"andi. %0,%1,%3\";
3723 }
3725 if (start + size >= 32)
3726 operands[3] = const0_rtx;
3727 else
3728 operands[3] = GEN_INT (start + size);
3729 return \"rlwinm. %0,%1,%3,%s2,31\";
3730 }"
3731 [(set_attr "type" "delayed_compare")
3732 (set_attr "length" "4,8")])
3734 (define_split
3735 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3736 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3737 (match_operand:SI 2 "const_int_operand" "")
3738 (match_operand:SI 3 "const_int_operand" ""))
3739 (const_int 0)))
3740 (set (match_operand:SI 0 "gpc_reg_operand" "")
3741 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3742 "reload_completed"
3743 [(set (match_dup 0)
3744 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3745 (set (match_dup 4)
3746 (compare:CC (match_dup 0)
3747 (const_int 0)))]
3748 "")
3750 (define_insn "extzvdi_internal"
3751 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3752 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3753 (match_operand:SI 2 "const_int_operand" "i")
3754 (match_operand:SI 3 "const_int_operand" "i")))]
3755 "TARGET_POWERPC64"
3756 "*
3757 {
3758 int start = INTVAL (operands[3]) & 63;
3759 int size = INTVAL (operands[2]) & 63;
3761 if (start + size >= 64)
3762 operands[3] = const0_rtx;
3763 else
3764 operands[3] = GEN_INT (start + size);
3765 operands[2] = GEN_INT (64 - size);
3766 return \"rldicl %0,%1,%3,%2\";
3767 }")
3769 (define_insn "*extzvdi_internal1"
3770 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3771 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3772 (match_operand:SI 2 "const_int_operand" "i")
3773 (match_operand:SI 3 "const_int_operand" "i"))
3774 (const_int 0)))
3775 (clobber (match_scratch:DI 4 "=r"))]
3776 "TARGET_64BIT && rs6000_gen_cell_microcode"
3777 "*
3778 {
3779 int start = INTVAL (operands[3]) & 63;
3780 int size = INTVAL (operands[2]) & 63;
3782 if (start + size >= 64)
3783 operands[3] = const0_rtx;
3784 else
3785 operands[3] = GEN_INT (start + size);
3786 operands[2] = GEN_INT (64 - size);
3787 return \"rldicl. %4,%1,%3,%2\";
3788 }"
3789 [(set_attr "type" "compare")])
3791 (define_insn "*extzvdi_internal2"
3792 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3793 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3794 (match_operand:SI 2 "const_int_operand" "i")
3795 (match_operand:SI 3 "const_int_operand" "i"))
3796 (const_int 0)))
3797 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3798 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3799 "TARGET_64BIT && rs6000_gen_cell_microcode"
3800 "*
3801 {
3802 int start = INTVAL (operands[3]) & 63;
3803 int size = INTVAL (operands[2]) & 63;
3805 if (start + size >= 64)
3806 operands[3] = const0_rtx;
3807 else
3808 operands[3] = GEN_INT (start + size);
3809 operands[2] = GEN_INT (64 - size);
3810 return \"rldicl. %0,%1,%3,%2\";
3811 }"
3812 [(set_attr "type" "compare")])
3814 (define_insn "rotlsi3"
3815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3816 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3817 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3818 ""
3819 "@
3820 rlwnm %0,%1,%2,0xffffffff
3821 rlwinm %0,%1,%h2,0xffffffff"
3822 [(set_attr "type" "var_shift_rotate,integer")])
3824 (define_insn "*rotlsi3_64"
3825 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3826 (zero_extend:DI
3827 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3828 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3829 "TARGET_64BIT"
3830 "@
3831 rlwnm %0,%1,%2,0xffffffff
3832 rlwinm %0,%1,%h2,0xffffffff"
3833 [(set_attr "type" "var_shift_rotate,integer")])
3835 (define_insn "*rotlsi3_internal2"
3836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3837 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3838 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3839 (const_int 0)))
3840 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3841 ""
3842 "@
3843 rlwnm. %3,%1,%2,0xffffffff
3844 rlwinm. %3,%1,%h2,0xffffffff
3845 #
3846 #"
3847 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3848 (set_attr "length" "4,4,8,8")])
3850 (define_split
3851 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3852 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3853 (match_operand:SI 2 "reg_or_cint_operand" ""))
3854 (const_int 0)))
3855 (clobber (match_scratch:SI 3 ""))]
3856 "reload_completed"
3857 [(set (match_dup 3)
3858 (rotate:SI (match_dup 1) (match_dup 2)))
3859 (set (match_dup 0)
3860 (compare:CC (match_dup 3)
3861 (const_int 0)))]
3862 "")
3864 (define_insn "*rotlsi3_internal3"
3865 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3866 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3867 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3868 (const_int 0)))
3869 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3870 (rotate:SI (match_dup 1) (match_dup 2)))]
3871 ""
3872 "@
3873 rlwnm. %0,%1,%2,0xffffffff
3874 rlwinm. %0,%1,%h2,0xffffffff
3875 #
3876 #"
3877 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3878 (set_attr "length" "4,4,8,8")])
3880 (define_split
3881 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3882 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3883 (match_operand:SI 2 "reg_or_cint_operand" ""))
3884 (const_int 0)))
3885 (set (match_operand:SI 0 "gpc_reg_operand" "")
3886 (rotate:SI (match_dup 1) (match_dup 2)))]
3887 "reload_completed"
3888 [(set (match_dup 0)
3889 (rotate:SI (match_dup 1) (match_dup 2)))
3890 (set (match_dup 3)
3891 (compare:CC (match_dup 0)
3892 (const_int 0)))]
3893 "")
3895 (define_insn "*rotlsi3_internal4"
3896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3897 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3898 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3899 (match_operand:SI 3 "mask_operand" "n,n")))]
3900 ""
3901 "@
3902 rlwnm %0,%1,%2,%m3,%M3
3903 rlwinm %0,%1,%h2,%m3,%M3"
3904 [(set_attr "type" "var_shift_rotate,integer")])
3906 (define_insn "*rotlsi3_internal5"
3907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3908 (compare:CC (and:SI
3909 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3910 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3911 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3912 (const_int 0)))
3913 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3914 ""
3915 "@
3916 rlwnm. %4,%1,%2,%m3,%M3
3917 rlwinm. %4,%1,%h2,%m3,%M3
3918 #
3919 #"
3920 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3921 (set_attr "length" "4,4,8,8")])
3923 (define_split
3924 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3925 (compare:CC (and:SI
3926 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3927 (match_operand:SI 2 "reg_or_cint_operand" ""))
3928 (match_operand:SI 3 "mask_operand" ""))
3929 (const_int 0)))
3930 (clobber (match_scratch:SI 4 ""))]
3931 "reload_completed"
3932 [(set (match_dup 4)
3933 (and:SI (rotate:SI (match_dup 1)
3934 (match_dup 2))
3935 (match_dup 3)))
3936 (set (match_dup 0)
3937 (compare:CC (match_dup 4)
3938 (const_int 0)))]
3939 "")
3941 (define_insn "*rotlsi3_internal6"
3942 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3943 (compare:CC (and:SI
3944 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3945 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3946 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3947 (const_int 0)))
3948 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3949 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3950 ""
3951 "@
3952 rlwnm. %0,%1,%2,%m3,%M3
3953 rlwinm. %0,%1,%h2,%m3,%M3
3954 #
3955 #"
3956 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3957 (set_attr "length" "4,4,8,8")])
3959 (define_split
3960 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3961 (compare:CC (and:SI
3962 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3963 (match_operand:SI 2 "reg_or_cint_operand" ""))
3964 (match_operand:SI 3 "mask_operand" ""))
3965 (const_int 0)))
3966 (set (match_operand:SI 0 "gpc_reg_operand" "")
3967 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3968 "reload_completed"
3969 [(set (match_dup 0)
3970 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3971 (set (match_dup 4)
3972 (compare:CC (match_dup 0)
3973 (const_int 0)))]
3974 "")
3976 (define_insn "*rotlsi3_internal7le"
3977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3978 (zero_extend:SI
3979 (subreg:QI
3980 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3981 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3982 "!BYTES_BIG_ENDIAN"
3983 "rlw%I2nm %0,%1,%h2,0xff"
3984 [(set (attr "cell_micro")
3985 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3986 (const_string "not")
3987 (const_string "always")))])
3989 (define_insn "*rotlsi3_internal7be"
3990 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3991 (zero_extend:SI
3992 (subreg:QI
3993 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3994 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3995 "BYTES_BIG_ENDIAN"
3996 "rlw%I2nm %0,%1,%h2,0xff"
3997 [(set (attr "cell_micro")
3998 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3999 (const_string "not")
4000 (const_string "always")))])
4002 (define_insn "*rotlsi3_internal8le"
4003 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4004 (compare:CC (zero_extend:SI
4005 (subreg:QI
4006 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4007 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4008 (const_int 0)))
4009 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4010 "!BYTES_BIG_ENDIAN"
4011 "@
4012 rlwnm. %3,%1,%2,0xff
4013 rlwinm. %3,%1,%h2,0xff
4014 #
4015 #"
4016 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4017 (set_attr "length" "4,4,8,8")])
4019 (define_insn "*rotlsi3_internal8be"
4020 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4021 (compare:CC (zero_extend:SI
4022 (subreg:QI
4023 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4024 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
4025 (const_int 0)))
4026 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4027 "BYTES_BIG_ENDIAN"
4028 "@
4029 rlwnm. %3,%1,%2,0xff
4030 rlwinm. %3,%1,%h2,0xff
4031 #
4032 #"
4033 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4034 (set_attr "length" "4,4,8,8")])
4036 (define_split
4037 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4038 (compare:CC (zero_extend:SI
4039 (subreg:QI
4040 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4041 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4042 (const_int 0)))
4043 (clobber (match_scratch:SI 3 ""))]
4044 "!BYTES_BIG_ENDIAN && reload_completed"
4045 [(set (match_dup 3)
4046 (zero_extend:SI (subreg:QI
4047 (rotate:SI (match_dup 1)
4048 (match_dup 2)) 0)))
4049 (set (match_dup 0)
4050 (compare:CC (match_dup 3)
4051 (const_int 0)))]
4052 "")
4054 (define_split
4055 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4056 (compare:CC (zero_extend:SI
4057 (subreg:QI
4058 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4059 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4060 (const_int 0)))
4061 (clobber (match_scratch:SI 3 ""))]
4062 "BYTES_BIG_ENDIAN && reload_completed"
4063 [(set (match_dup 3)
4064 (zero_extend:SI (subreg:QI
4065 (rotate:SI (match_dup 1)
4066 (match_dup 2)) 3)))
4067 (set (match_dup 0)
4068 (compare:CC (match_dup 3)
4069 (const_int 0)))]
4070 "")
4072 (define_insn "*rotlsi3_internal9le"
4073 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4074 (compare:CC (zero_extend:SI
4075 (subreg:QI
4076 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4077 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4078 (const_int 0)))
4079 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4080 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4081 "!BYTES_BIG_ENDIAN"
4082 "@
4083 rlwnm. %0,%1,%2,0xff
4084 rlwinm. %0,%1,%h2,0xff
4085 #
4086 #"
4087 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4088 (set_attr "length" "4,4,8,8")])
4090 (define_insn "*rotlsi3_internal9be"
4091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4092 (compare:CC (zero_extend:SI
4093 (subreg:QI
4094 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4095 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
4096 (const_int 0)))
4097 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4098 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4099 "BYTES_BIG_ENDIAN"
4100 "@
4101 rlwnm. %0,%1,%2,0xff
4102 rlwinm. %0,%1,%h2,0xff
4103 #
4104 #"
4105 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4106 (set_attr "length" "4,4,8,8")])
4108 (define_split
4109 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4110 (compare:CC (zero_extend:SI
4111 (subreg:QI
4112 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4113 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4114 (const_int 0)))
4115 (set (match_operand:SI 0 "gpc_reg_operand" "")
4116 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4117 "!BYTES_BIG_ENDIAN && reload_completed"
4118 [(set (match_dup 0)
4119 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4120 (set (match_dup 3)
4121 (compare:CC (match_dup 0)
4122 (const_int 0)))]
4123 "")
4125 (define_split
4126 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4127 (compare:CC (zero_extend:SI
4128 (subreg:QI
4129 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4130 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4131 (const_int 0)))
4132 (set (match_operand:SI 0 "gpc_reg_operand" "")
4133 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4134 "BYTES_BIG_ENDIAN && reload_completed"
4135 [(set (match_dup 0)
4136 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
4137 (set (match_dup 3)
4138 (compare:CC (match_dup 0)
4139 (const_int 0)))]
4140 "")
4142 (define_insn "*rotlsi3_internal10le"
4143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4144 (zero_extend:SI
4145 (subreg:HI
4146 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4148 "!BYTES_BIG_ENDIAN"
4149 "@
4150 rlwnm %0,%1,%2,0xffff
4151 rlwinm %0,%1,%h2,0xffff"
4152 [(set_attr "type" "var_shift_rotate,integer")])
4154 (define_insn "*rotlsi3_internal10be"
4155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4156 (zero_extend:SI
4157 (subreg:HI
4158 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4159 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
4160 "BYTES_BIG_ENDIAN"
4161 "@
4162 rlwnm %0,%1,%2,0xffff
4163 rlwinm %0,%1,%h2,0xffff"
4164 [(set_attr "type" "var_shift_rotate,integer")])
4166 (define_insn "*rotlsi3_internal11le"
4167 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4168 (compare:CC (zero_extend:SI
4169 (subreg:HI
4170 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4171 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4172 (const_int 0)))
4173 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4174 "!BYTES_BIG_ENDIAN"
4175 "@
4176 rlwnm. %3,%1,%2,0xffff
4177 rlwinm. %3,%1,%h2,0xffff
4178 #
4179 #"
4180 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4181 (set_attr "length" "4,4,8,8")])
4183 (define_insn "*rotlsi3_internal11be"
4184 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4185 (compare:CC (zero_extend:SI
4186 (subreg:HI
4187 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4188 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4189 (const_int 0)))
4190 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4191 "BYTES_BIG_ENDIAN"
4192 "@
4193 rlwnm. %3,%1,%2,0xffff
4194 rlwinm. %3,%1,%h2,0xffff
4195 #
4196 #"
4197 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4198 (set_attr "length" "4,4,8,8")])
4200 (define_split
4201 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4202 (compare:CC (zero_extend:SI
4203 (subreg:HI
4204 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4205 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4206 (const_int 0)))
4207 (clobber (match_scratch:SI 3 ""))]
4208 "!BYTES_BIG_ENDIAN && reload_completed"
4209 [(set (match_dup 3)
4210 (zero_extend:SI (subreg:HI
4211 (rotate:SI (match_dup 1)
4212 (match_dup 2)) 0)))
4213 (set (match_dup 0)
4214 (compare:CC (match_dup 3)
4215 (const_int 0)))]
4216 "")
4218 (define_split
4219 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4220 (compare:CC (zero_extend:SI
4221 (subreg:HI
4222 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4223 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4224 (const_int 0)))
4225 (clobber (match_scratch:SI 3 ""))]
4226 "BYTES_BIG_ENDIAN && reload_completed"
4227 [(set (match_dup 3)
4228 (zero_extend:SI (subreg:HI
4229 (rotate:SI (match_dup 1)
4230 (match_dup 2)) 2)))
4231 (set (match_dup 0)
4232 (compare:CC (match_dup 3)
4233 (const_int 0)))]
4234 "")
4236 (define_insn "*rotlsi3_internal12le"
4237 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4238 (compare:CC (zero_extend:SI
4239 (subreg:HI
4240 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4241 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4242 (const_int 0)))
4243 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4244 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4245 "!BYTES_BIG_ENDIAN"
4246 "@
4247 rlwnm. %0,%1,%2,0xffff
4248 rlwinm. %0,%1,%h2,0xffff
4249 #
4250 #"
4251 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4252 (set_attr "length" "4,4,8,8")])
4254 (define_insn "*rotlsi3_internal12be"
4255 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4256 (compare:CC (zero_extend:SI
4257 (subreg:HI
4258 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4259 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4260 (const_int 0)))
4261 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4262 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4263 "BYTES_BIG_ENDIAN"
4264 "@
4265 rlwnm. %0,%1,%2,0xffff
4266 rlwinm. %0,%1,%h2,0xffff
4267 #
4268 #"
4269 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4270 (set_attr "length" "4,4,8,8")])
4272 (define_split
4273 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4274 (compare:CC (zero_extend:SI
4275 (subreg:HI
4276 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4277 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4278 (const_int 0)))
4279 (set (match_operand:SI 0 "gpc_reg_operand" "")
4280 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4281 "!BYTES_BIG_ENDIAN && reload_completed"
4282 [(set (match_dup 0)
4283 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4284 (set (match_dup 3)
4285 (compare:CC (match_dup 0)
4286 (const_int 0)))]
4287 "")
4289 (define_split
4290 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4291 (compare:CC (zero_extend:SI
4292 (subreg:HI
4293 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4294 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4295 (const_int 0)))
4296 (set (match_operand:SI 0 "gpc_reg_operand" "")
4297 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4298 "BYTES_BIG_ENDIAN && reload_completed"
4299 [(set (match_dup 0)
4300 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4301 (set (match_dup 3)
4302 (compare:CC (match_dup 0)
4303 (const_int 0)))]
4304 "")
4306 (define_insn "ashlsi3"
4307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4308 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4309 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4310 ""
4311 "@
4312 slw %0,%1,%2
4313 slwi %0,%1,%h2"
4314 [(set_attr "type" "var_shift_rotate,shift")])
4316 (define_insn "*ashlsi3_64"
4317 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4318 (zero_extend:DI
4319 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4320 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4321 "TARGET_POWERPC64"
4322 "@
4323 slw %0,%1,%2
4324 slwi %0,%1,%h2"
4325 [(set_attr "type" "var_shift_rotate,shift")])
4327 (define_insn ""
4328 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4329 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4330 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4331 (const_int 0)))
4332 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4333 "TARGET_32BIT"
4334 "@
4335 slw. %3,%1,%2
4336 slwi. %3,%1,%h2
4337 #
4338 #"
4339 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4340 (set_attr "length" "4,4,8,8")])
4342 (define_split
4343 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4344 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4345 (match_operand:SI 2 "reg_or_cint_operand" ""))
4346 (const_int 0)))
4347 (clobber (match_scratch:SI 3 ""))]
4348 "TARGET_32BIT && reload_completed"
4349 [(set (match_dup 3)
4350 (ashift:SI (match_dup 1) (match_dup 2)))
4351 (set (match_dup 0)
4352 (compare:CC (match_dup 3)
4353 (const_int 0)))]
4354 "")
4356 (define_insn ""
4357 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4358 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4359 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4360 (const_int 0)))
4361 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4362 (ashift:SI (match_dup 1) (match_dup 2)))]
4363 "TARGET_32BIT"
4364 "@
4365 slw. %0,%1,%2
4366 slwi. %0,%1,%h2
4367 #
4368 #"
4369 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4370 (set_attr "length" "4,4,8,8")])
4372 (define_split
4373 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4374 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4375 (match_operand:SI 2 "reg_or_cint_operand" ""))
4376 (const_int 0)))
4377 (set (match_operand:SI 0 "gpc_reg_operand" "")
4378 (ashift:SI (match_dup 1) (match_dup 2)))]
4379 "TARGET_32BIT && reload_completed"
4380 [(set (match_dup 0)
4381 (ashift:SI (match_dup 1) (match_dup 2)))
4382 (set (match_dup 3)
4383 (compare:CC (match_dup 0)
4384 (const_int 0)))]
4385 "")
4387 (define_insn "rlwinm"
4388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4389 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4390 (match_operand:SI 2 "const_int_operand" "i"))
4391 (match_operand:SI 3 "mask_operand" "n")))]
4392 "includes_lshift_p (operands[2], operands[3])"
4393 "rlwinm %0,%1,%h2,%m3,%M3")
4395 (define_insn ""
4396 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4397 (compare:CC
4398 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4399 (match_operand:SI 2 "const_int_operand" "i,i"))
4400 (match_operand:SI 3 "mask_operand" "n,n"))
4401 (const_int 0)))
4402 (clobber (match_scratch:SI 4 "=r,r"))]
4403 "includes_lshift_p (operands[2], operands[3])"
4404 "@
4405 rlwinm. %4,%1,%h2,%m3,%M3
4406 #"
4407 [(set_attr "type" "delayed_compare")
4408 (set_attr "length" "4,8")])
4410 (define_split
4411 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4412 (compare:CC
4413 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4414 (match_operand:SI 2 "const_int_operand" ""))
4415 (match_operand:SI 3 "mask_operand" ""))
4416 (const_int 0)))
4417 (clobber (match_scratch:SI 4 ""))]
4418 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4419 [(set (match_dup 4)
4420 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4421 (match_dup 3)))
4422 (set (match_dup 0)
4423 (compare:CC (match_dup 4)
4424 (const_int 0)))]
4425 "")
4427 (define_insn ""
4428 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4429 (compare:CC
4430 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4431 (match_operand:SI 2 "const_int_operand" "i,i"))
4432 (match_operand:SI 3 "mask_operand" "n,n"))
4433 (const_int 0)))
4434 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4435 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4436 "includes_lshift_p (operands[2], operands[3])"
4437 "@
4438 rlwinm. %0,%1,%h2,%m3,%M3
4439 #"
4440 [(set_attr "type" "delayed_compare")
4441 (set_attr "length" "4,8")])
4443 (define_split
4444 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4445 (compare:CC
4446 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4447 (match_operand:SI 2 "const_int_operand" ""))
4448 (match_operand:SI 3 "mask_operand" ""))
4449 (const_int 0)))
4450 (set (match_operand:SI 0 "gpc_reg_operand" "")
4451 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4452 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4453 [(set (match_dup 0)
4454 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4455 (set (match_dup 4)
4456 (compare:CC (match_dup 0)
4457 (const_int 0)))]
4458 "")
4460 (define_insn "lshrsi3"
4461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4462 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4463 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4464 ""
4465 "@
4466 mr %0,%1
4467 srw %0,%1,%2
4468 srwi %0,%1,%h2"
4469 [(set_attr "type" "integer,var_shift_rotate,shift")])
4471 (define_insn "*lshrsi3_64"
4472 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4473 (zero_extend:DI
4474 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4475 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4476 "TARGET_POWERPC64"
4477 "@
4478 srw %0,%1,%2
4479 srwi %0,%1,%h2"
4480 [(set_attr "type" "var_shift_rotate,shift")])
4482 (define_insn ""
4483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4484 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4485 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4486 (const_int 0)))
4487 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4488 "TARGET_32BIT"
4489 "@
4490 mr. %1,%1
4491 srw. %3,%1,%2
4492 srwi. %3,%1,%h2
4493 #
4494 #
4495 #"
4496 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4497 (set_attr "length" "4,4,4,8,8,8")])
4499 (define_split
4500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4501 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4502 (match_operand:SI 2 "reg_or_cint_operand" ""))
4503 (const_int 0)))
4504 (clobber (match_scratch:SI 3 ""))]
4505 "TARGET_32BIT && reload_completed"
4506 [(set (match_dup 3)
4507 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4508 (set (match_dup 0)
4509 (compare:CC (match_dup 3)
4510 (const_int 0)))]
4511 "")
4513 (define_insn ""
4514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4515 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4516 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4517 (const_int 0)))
4518 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4519 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4520 "TARGET_32BIT"
4521 "@
4522 mr. %0,%1
4523 srw. %0,%1,%2
4524 srwi. %0,%1,%h2
4525 #
4526 #
4527 #"
4528 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4529 (set_attr "length" "4,4,4,8,8,8")])
4531 (define_split
4532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4533 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4534 (match_operand:SI 2 "reg_or_cint_operand" ""))
4535 (const_int 0)))
4536 (set (match_operand:SI 0 "gpc_reg_operand" "")
4537 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4538 "TARGET_32BIT && reload_completed"
4539 [(set (match_dup 0)
4540 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4541 (set (match_dup 3)
4542 (compare:CC (match_dup 0)
4543 (const_int 0)))]
4544 "")
4546 (define_insn ""
4547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4548 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4549 (match_operand:SI 2 "const_int_operand" "i"))
4550 (match_operand:SI 3 "mask_operand" "n")))]
4551 "includes_rshift_p (operands[2], operands[3])"
4552 "rlwinm %0,%1,%s2,%m3,%M3")
4554 (define_insn ""
4555 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4556 (compare:CC
4557 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4558 (match_operand:SI 2 "const_int_operand" "i,i"))
4559 (match_operand:SI 3 "mask_operand" "n,n"))
4560 (const_int 0)))
4561 (clobber (match_scratch:SI 4 "=r,r"))]
4562 "includes_rshift_p (operands[2], operands[3])"
4563 "@
4564 rlwinm. %4,%1,%s2,%m3,%M3
4565 #"
4566 [(set_attr "type" "delayed_compare")
4567 (set_attr "length" "4,8")])
4569 (define_split
4570 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4571 (compare:CC
4572 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4573 (match_operand:SI 2 "const_int_operand" ""))
4574 (match_operand:SI 3 "mask_operand" ""))
4575 (const_int 0)))
4576 (clobber (match_scratch:SI 4 ""))]
4577 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4578 [(set (match_dup 4)
4579 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4580 (match_dup 3)))
4581 (set (match_dup 0)
4582 (compare:CC (match_dup 4)
4583 (const_int 0)))]
4584 "")
4586 (define_insn ""
4587 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4588 (compare:CC
4589 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4590 (match_operand:SI 2 "const_int_operand" "i,i"))
4591 (match_operand:SI 3 "mask_operand" "n,n"))
4592 (const_int 0)))
4593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4594 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4595 "includes_rshift_p (operands[2], operands[3])"
4596 "@
4597 rlwinm. %0,%1,%s2,%m3,%M3
4598 #"
4599 [(set_attr "type" "delayed_compare")
4600 (set_attr "length" "4,8")])
4602 (define_split
4603 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4604 (compare:CC
4605 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4606 (match_operand:SI 2 "const_int_operand" ""))
4607 (match_operand:SI 3 "mask_operand" ""))
4608 (const_int 0)))
4609 (set (match_operand:SI 0 "gpc_reg_operand" "")
4610 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4611 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4612 [(set (match_dup 0)
4613 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4614 (set (match_dup 4)
4615 (compare:CC (match_dup 0)
4616 (const_int 0)))]
4617 "")
4619 (define_insn "*lshiftrt_internal1le"
4620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4621 (zero_extend:SI
4622 (subreg:QI
4623 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4624 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4625 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4626 "rlwinm %0,%1,%s2,0xff")
4628 (define_insn "*lshiftrt_internal1be"
4629 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4630 (zero_extend:SI
4631 (subreg:QI
4632 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4633 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4634 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4635 "rlwinm %0,%1,%s2,0xff")
4637 (define_insn "*lshiftrt_internal2le"
4638 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4639 (compare:CC
4640 (zero_extend:SI
4641 (subreg:QI
4642 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4643 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4644 (const_int 0)))
4645 (clobber (match_scratch:SI 3 "=r,r"))]
4646 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4647 "@
4648 rlwinm. %3,%1,%s2,0xff
4649 #"
4650 [(set_attr "type" "delayed_compare")
4651 (set_attr "length" "4,8")])
4653 (define_insn "*lshiftrt_internal2be"
4654 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4655 (compare:CC
4656 (zero_extend:SI
4657 (subreg:QI
4658 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4659 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4660 (const_int 0)))
4661 (clobber (match_scratch:SI 3 "=r,r"))]
4662 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4663 "@
4664 rlwinm. %3,%1,%s2,0xff
4665 #"
4666 [(set_attr "type" "delayed_compare")
4667 (set_attr "length" "4,8")])
4669 (define_split
4670 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4671 (compare:CC
4672 (zero_extend:SI
4673 (subreg:QI
4674 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4675 (match_operand:SI 2 "const_int_operand" "")) 0))
4676 (const_int 0)))
4677 (clobber (match_scratch:SI 3 ""))]
4678 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4679 [(set (match_dup 3)
4680 (zero_extend:SI (subreg:QI
4681 (lshiftrt:SI (match_dup 1)
4682 (match_dup 2)) 0)))
4683 (set (match_dup 0)
4684 (compare:CC (match_dup 3)
4685 (const_int 0)))]
4686 "")
4688 (define_split
4689 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4690 (compare:CC
4691 (zero_extend:SI
4692 (subreg:QI
4693 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4694 (match_operand:SI 2 "const_int_operand" "")) 3))
4695 (const_int 0)))
4696 (clobber (match_scratch:SI 3 ""))]
4697 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4698 [(set (match_dup 3)
4699 (zero_extend:SI (subreg:QI
4700 (lshiftrt:SI (match_dup 1)
4701 (match_dup 2)) 3)))
4702 (set (match_dup 0)
4703 (compare:CC (match_dup 3)
4704 (const_int 0)))]
4705 "")
4707 (define_insn "*lshiftrt_internal3le"
4708 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4709 (compare:CC
4710 (zero_extend:SI
4711 (subreg:QI
4712 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4713 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4714 (const_int 0)))
4715 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4716 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4717 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4718 "@
4719 rlwinm. %0,%1,%s2,0xff
4720 #"
4721 [(set_attr "type" "delayed_compare")
4722 (set_attr "length" "4,8")])
4724 (define_insn "*lshiftrt_internal3be"
4725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4726 (compare:CC
4727 (zero_extend:SI
4728 (subreg:QI
4729 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4730 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4731 (const_int 0)))
4732 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4733 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4734 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4735 "@
4736 rlwinm. %0,%1,%s2,0xff
4737 #"
4738 [(set_attr "type" "delayed_compare")
4739 (set_attr "length" "4,8")])
4741 (define_split
4742 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4743 (compare:CC
4744 (zero_extend:SI
4745 (subreg:QI
4746 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4747 (match_operand:SI 2 "const_int_operand" "")) 0))
4748 (const_int 0)))
4749 (set (match_operand:SI 0 "gpc_reg_operand" "")
4750 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4751 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4752 [(set (match_dup 0)
4753 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4754 (set (match_dup 3)
4755 (compare:CC (match_dup 0)
4756 (const_int 0)))]
4757 "")
4759 (define_split
4760 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4761 (compare:CC
4762 (zero_extend:SI
4763 (subreg:QI
4764 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4765 (match_operand:SI 2 "const_int_operand" "")) 3))
4766 (const_int 0)))
4767 (set (match_operand:SI 0 "gpc_reg_operand" "")
4768 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4769 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4770 [(set (match_dup 0)
4771 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4772 (set (match_dup 3)
4773 (compare:CC (match_dup 0)
4774 (const_int 0)))]
4775 "")
4777 (define_insn "*lshiftrt_internal4le"
4778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4779 (zero_extend:SI
4780 (subreg:HI
4781 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4782 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4783 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4784 "rlwinm %0,%1,%s2,0xffff")
4786 (define_insn "*lshiftrt_internal4be"
4787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4788 (zero_extend:SI
4789 (subreg:HI
4790 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4791 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4792 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4793 "rlwinm %0,%1,%s2,0xffff")
4795 (define_insn "*lshiftrt_internal5le"
4796 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4797 (compare:CC
4798 (zero_extend:SI
4799 (subreg:HI
4800 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4801 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4802 (const_int 0)))
4803 (clobber (match_scratch:SI 3 "=r,r"))]
4804 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4805 "@
4806 rlwinm. %3,%1,%s2,0xffff
4807 #"
4808 [(set_attr "type" "delayed_compare")
4809 (set_attr "length" "4,8")])
4811 (define_insn "*lshiftrt_internal5be"
4812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4813 (compare:CC
4814 (zero_extend:SI
4815 (subreg:HI
4816 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4817 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4818 (const_int 0)))
4819 (clobber (match_scratch:SI 3 "=r,r"))]
4820 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4821 "@
4822 rlwinm. %3,%1,%s2,0xffff
4823 #"
4824 [(set_attr "type" "delayed_compare")
4825 (set_attr "length" "4,8")])
4827 (define_split
4828 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4829 (compare:CC
4830 (zero_extend:SI
4831 (subreg:HI
4832 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4833 (match_operand:SI 2 "const_int_operand" "")) 0))
4834 (const_int 0)))
4835 (clobber (match_scratch:SI 3 ""))]
4836 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4837 [(set (match_dup 3)
4838 (zero_extend:SI (subreg:HI
4839 (lshiftrt:SI (match_dup 1)
4840 (match_dup 2)) 0)))
4841 (set (match_dup 0)
4842 (compare:CC (match_dup 3)
4843 (const_int 0)))]
4844 "")
4846 (define_split
4847 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4848 (compare:CC
4849 (zero_extend:SI
4850 (subreg:HI
4851 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4852 (match_operand:SI 2 "const_int_operand" "")) 2))
4853 (const_int 0)))
4854 (clobber (match_scratch:SI 3 ""))]
4855 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4856 [(set (match_dup 3)
4857 (zero_extend:SI (subreg:HI
4858 (lshiftrt:SI (match_dup 1)
4859 (match_dup 2)) 2)))
4860 (set (match_dup 0)
4861 (compare:CC (match_dup 3)
4862 (const_int 0)))]
4863 "")
4865 (define_insn "*lshiftrt_internal5le"
4866 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4867 (compare:CC
4868 (zero_extend:SI
4869 (subreg:HI
4870 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4871 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4872 (const_int 0)))
4873 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4874 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4875 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4876 "@
4877 rlwinm. %0,%1,%s2,0xffff
4878 #"
4879 [(set_attr "type" "delayed_compare")
4880 (set_attr "length" "4,8")])
4882 (define_insn "*lshiftrt_internal5be"
4883 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4884 (compare:CC
4885 (zero_extend:SI
4886 (subreg:HI
4887 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4888 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4889 (const_int 0)))
4890 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4891 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4892 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4893 "@
4894 rlwinm. %0,%1,%s2,0xffff
4895 #"
4896 [(set_attr "type" "delayed_compare")
4897 (set_attr "length" "4,8")])
4899 (define_split
4900 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4901 (compare:CC
4902 (zero_extend:SI
4903 (subreg:HI
4904 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4905 (match_operand:SI 2 "const_int_operand" "")) 0))
4906 (const_int 0)))
4907 (set (match_operand:SI 0 "gpc_reg_operand" "")
4908 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4909 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4910 [(set (match_dup 0)
4911 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4912 (set (match_dup 3)
4913 (compare:CC (match_dup 0)
4914 (const_int 0)))]
4915 "")
4917 (define_split
4918 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4919 (compare:CC
4920 (zero_extend:SI
4921 (subreg:HI
4922 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4923 (match_operand:SI 2 "const_int_operand" "")) 2))
4924 (const_int 0)))
4925 (set (match_operand:SI 0 "gpc_reg_operand" "")
4926 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4927 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4928 [(set (match_dup 0)
4929 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4930 (set (match_dup 3)
4931 (compare:CC (match_dup 0)
4932 (const_int 0)))]
4933 "")
4935 (define_insn "ashrsi3"
4936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4937 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4938 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4939 ""
4940 "@
4941 sraw %0,%1,%2
4942 srawi %0,%1,%h2"
4943 [(set_attr "type" "var_shift_rotate,shift")])
4945 (define_insn "*ashrsi3_64"
4946 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4947 (sign_extend:DI
4948 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4949 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4950 "TARGET_POWERPC64"
4951 "@
4952 sraw %0,%1,%2
4953 srawi %0,%1,%h2"
4954 [(set_attr "type" "var_shift_rotate,shift")])
4956 (define_insn ""
4957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4958 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4959 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4960 (const_int 0)))
4961 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4962 ""
4963 "@
4964 sraw. %3,%1,%2
4965 srawi. %3,%1,%h2
4966 #
4967 #"
4968 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4969 (set_attr "length" "4,4,8,8")])
4971 (define_split
4972 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4973 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4974 (match_operand:SI 2 "reg_or_cint_operand" ""))
4975 (const_int 0)))
4976 (clobber (match_scratch:SI 3 ""))]
4977 "reload_completed"
4978 [(set (match_dup 3)
4979 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4980 (set (match_dup 0)
4981 (compare:CC (match_dup 3)
4982 (const_int 0)))]
4983 "")
4985 (define_insn ""
4986 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4987 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4988 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4989 (const_int 0)))
4990 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4991 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4992 ""
4993 "@
4994 sraw. %0,%1,%2
4995 srawi. %0,%1,%h2
4996 #
4997 #"
4998 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4999 (set_attr "length" "4,4,8,8")])
5000 \f
5001 ;; Builtins to replace a division to generate FRE reciprocal estimate
5002 ;; instructions and the necessary fixup instructions
5003 (define_expand "recip<mode>3"
5004 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5005 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5006 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5007 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5008 {
5009 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5010 DONE;
5011 })
5013 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5014 ;; hardware division. This is only done before register allocation and with
5015 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5016 (define_split
5017 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5018 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5019 (match_operand 2 "gpc_reg_operand" "")))]
5020 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5021 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5022 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5023 [(const_int 0)]
5024 {
5025 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5026 DONE;
5027 })
5029 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5030 ;; appropriate fixup.
5031 (define_expand "rsqrt<mode>2"
5032 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5033 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5034 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5035 {
5036 rs6000_emit_swrsqrt (operands[0], operands[1]);
5037 DONE;
5038 })
5039 \f
5040 (define_split
5041 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5042 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5043 (match_operand:SI 2 "reg_or_cint_operand" ""))
5044 (const_int 0)))
5045 (set (match_operand:SI 0 "gpc_reg_operand" "")
5046 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5047 "reload_completed"
5048 [(set (match_dup 0)
5049 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5050 (set (match_dup 3)
5051 (compare:CC (match_dup 0)
5052 (const_int 0)))]
5053 "")
5055 \f
5056 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
5057 ;; modes here, and also add in conditional vsx/power8-vector support to access
5058 ;; values in the traditional Altivec registers if the appropriate
5059 ;; -mupper-regs-{df,sf} option is enabled.
5061 (define_expand "abs<mode>2"
5062 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5063 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5064 "TARGET_<MODE>_INSN"
5065 "")
5067 (define_insn "*abs<mode>2_fpr"
5068 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5069 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5070 "TARGET_<MODE>_FPR"
5071 "@
5072 fabs %0,%1
5073 xsabsdp %x0,%x1"
5074 [(set_attr "type" "fp")
5075 (set_attr "fp_type" "fp_addsub_<Fs>")])
5077 (define_insn "*nabs<mode>2_fpr"
5078 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5079 (neg:SFDF
5080 (abs:SFDF
5081 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
5082 "TARGET_<MODE>_FPR"
5083 "@
5084 fnabs %0,%1
5085 xsnabsdp %x0,%x1"
5086 [(set_attr "type" "fp")
5087 (set_attr "fp_type" "fp_addsub_<Fs>")])
5089 (define_expand "neg<mode>2"
5090 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5091 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5092 "TARGET_<MODE>_INSN"
5093 "")
5095 (define_insn "*neg<mode>2_fpr"
5096 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5097 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5098 "TARGET_<MODE>_FPR"
5099 "@
5100 fneg %0,%1
5101 xsnegdp %x0,%x1"
5102 [(set_attr "type" "fp")
5103 (set_attr "fp_type" "fp_addsub_<Fs>")])
5105 (define_expand "add<mode>3"
5106 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5107 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5108 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5109 "TARGET_<MODE>_INSN"
5110 "")
5112 (define_insn "*add<mode>3_fpr"
5113 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5114 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5115 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5116 "TARGET_<MODE>_FPR"
5117 "@
5118 fadd<Ftrad> %0,%1,%2
5119 xsadd<Fvsx> %x0,%x1,%x2"
5120 [(set_attr "type" "fp")
5121 (set_attr "fp_type" "fp_addsub_<Fs>")])
5123 (define_expand "sub<mode>3"
5124 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5125 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5126 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5127 "TARGET_<MODE>_INSN"
5128 "")
5130 (define_insn "*sub<mode>3_fpr"
5131 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5132 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5133 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5134 "TARGET_<MODE>_FPR"
5135 "@
5136 fsub<Ftrad> %0,%1,%2
5137 xssub<Fvsx> %x0,%x1,%x2"
5138 [(set_attr "type" "fp")
5139 (set_attr "fp_type" "fp_addsub_<Fs>")])
5141 (define_expand "mul<mode>3"
5142 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5143 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5144 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5145 "TARGET_<MODE>_INSN"
5146 "")
5148 (define_insn "*mul<mode>3_fpr"
5149 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5150 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5151 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5152 "TARGET_<MODE>_FPR"
5153 "@
5154 fmul<Ftrad> %0,%1,%2
5155 xsmul<Fvsx> %x0,%x1,%x2"
5156 [(set_attr "type" "dmul")
5157 (set_attr "fp_type" "fp_mul_<Fs>")])
5159 (define_expand "div<mode>3"
5160 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5161 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5162 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5163 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
5164 "")
5166 (define_insn "*div<mode>3_fpr"
5167 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5168 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5169 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5170 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
5171 "@
5172 fdiv<Ftrad> %0,%1,%2
5173 xsdiv<Fvsx> %x0,%x1,%x2"
5174 [(set_attr "type" "<Fs>div")
5175 (set_attr "fp_type" "fp_div_<Fs>")])
5177 (define_insn "sqrt<mode>2"
5178 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5179 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5180 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
5181 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
5182 "@
5183 fsqrt<Ftrad> %0,%1
5184 xssqrt<Fvsx> %x0,%x1"
5185 [(set_attr "type" "<Fs>sqrt")
5186 (set_attr "fp_type" "fp_sqrt_<Fs>")])
5188 ;; Floating point reciprocal approximation
5189 (define_insn "fre<Fs>"
5190 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5191 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5192 UNSPEC_FRES))]
5193 "TARGET_<FFRE>"
5194 "@
5195 fre<Ftrad> %0,%1
5196 xsre<Fvsx> %x0,%x1"
5197 [(set_attr "type" "fp")])
5199 (define_insn "*rsqrt<mode>2"
5200 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5201 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5202 UNSPEC_RSQRT))]
5203 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5204 "@
5205 frsqrte<Ftrad> %0,%1
5206 xsrsqrte<Fvsx> %x0,%x1"
5207 [(set_attr "type" "fp")])
5209 ;; Floating point comparisons
5210 (define_insn "*cmp<mode>_fpr"
5211 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
5212 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5213 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5214 "TARGET_<MODE>_FPR"
5215 "@
5216 fcmpu %0,%1,%2
5217 xscmpudp %0,%x1,%x2"
5218 [(set_attr "type" "fpcompare")])
5220 ;; Floating point conversions
5221 (define_expand "extendsfdf2"
5222 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5223 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5224 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5225 "")
5227 (define_insn_and_split "*extendsfdf2_fpr"
5228 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
5229 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
5230 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5231 "@
5232 #
5233 fmr %0,%1
5234 lfs%U1%X1 %0,%1
5235 #
5236 xxlor %x0,%x1,%x1
5237 lxsspx %x0,%y1"
5238 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5239 [(const_int 0)]
5240 {
5241 emit_note (NOTE_INSN_DELETED);
5242 DONE;
5243 }
5244 [(set_attr_alternative "type"
5245 [(const_string "fp")
5246 (const_string "fp")
5247 (if_then_else
5248 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
5249 (const_string "fpload_ux")
5250 (if_then_else
5251 (match_test "update_address_mem (operands[1], VOIDmode)")
5252 (const_string "fpload_u")
5253 (const_string "fpload")))
5254 (const_string "fp")
5255 (const_string "vecsimple")
5256 (if_then_else
5257 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
5258 (const_string "fpload_ux")
5259 (if_then_else
5260 (match_test "update_address_mem (operands[1], VOIDmode)")
5261 (const_string "fpload_u")
5262 (const_string "fpload")))])])
5264 (define_expand "truncdfsf2"
5265 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5266 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5267 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5268 "")
5270 (define_insn "*truncdfsf2_fpr"
5271 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5272 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5273 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5274 "frsp %0,%1"
5275 [(set_attr "type" "fp")])
5277 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5278 ;; builtins.c and optabs.c that are not correct for IBM long double
5279 ;; when little-endian.
5280 (define_expand "signbittf2"
5281 [(set (match_dup 2)
5282 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5283 (set (match_dup 3)
5284 (subreg:DI (match_dup 2) 0))
5285 (set (match_dup 4)
5286 (match_dup 5))
5287 (set (match_operand:SI 0 "gpc_reg_operand" "")
5288 (match_dup 6))]
5289 "!TARGET_IEEEQUAD
5290 && TARGET_HARD_FLOAT
5291 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5292 && TARGET_LONG_DOUBLE_128"
5293 {
5294 operands[2] = gen_reg_rtx (DFmode);
5295 operands[3] = gen_reg_rtx (DImode);
5296 if (TARGET_POWERPC64)
5297 {
5298 operands[4] = gen_reg_rtx (DImode);
5299 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5300 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5301 WORDS_BIG_ENDIAN ? 4 : 0);
5302 }
5303 else
5304 {
5305 operands[4] = gen_reg_rtx (SImode);
5306 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5307 WORDS_BIG_ENDIAN ? 0 : 4);
5308 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5309 }
5310 })
5312 (define_expand "copysign<mode>3"
5313 [(set (match_dup 3)
5314 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5315 (set (match_dup 4)
5316 (neg:SFDF (abs:SFDF (match_dup 1))))
5317 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5318 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5319 (match_dup 5))
5320 (match_dup 3)
5321 (match_dup 4)))]
5322 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5323 && ((TARGET_PPC_GFXOPT
5324 && !HONOR_NANS (<MODE>mode)
5325 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5326 || TARGET_CMPB
5327 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5328 {
5329 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5330 {
5331 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5332 operands[2]));
5333 DONE;
5334 }
5336 operands[3] = gen_reg_rtx (<MODE>mode);
5337 operands[4] = gen_reg_rtx (<MODE>mode);
5338 operands[5] = CONST0_RTX (<MODE>mode);
5339 })
5341 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5342 ;; compiler from optimizing -0.0
5343 (define_insn "copysign<mode>3_fcpsgn"
5344 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5345 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5346 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5347 UNSPEC_COPYSIGN))]
5348 "TARGET_<MODE>_FPR && TARGET_CMPB"
5349 "@
5350 fcpsgn %0,%2,%1
5351 xscpsgn<Fvsx> %x0,%x2,%x1"
5352 [(set_attr "type" "fp")])
5354 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5355 ;; fsel instruction and some auxiliary computations. Then we just have a
5356 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5357 ;; combine.
5358 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5359 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5360 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5361 ;; define_splits to make them if made by combine. On VSX machines we have the
5362 ;; min/max instructions.
5363 ;;
5364 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5365 ;; to allow either DF/SF to use only traditional registers.
5367 (define_expand "smax<mode>3"
5368 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5369 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5370 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5371 (match_dup 1)
5372 (match_dup 2)))]
5373 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5374 {
5375 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5376 DONE;
5377 })
5379 (define_insn "*smax<mode>3_vsx"
5380 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5381 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5382 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5383 "TARGET_<MODE>_FPR && TARGET_VSX"
5384 "xsmaxdp %x0,%x1,%x2"
5385 [(set_attr "type" "fp")])
5387 (define_expand "smin<mode>3"
5388 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5389 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5390 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5391 (match_dup 2)
5392 (match_dup 1)))]
5393 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5394 {
5395 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5396 DONE;
5397 })
5399 (define_insn "*smin<mode>3_vsx"
5400 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5401 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5402 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5403 "TARGET_<MODE>_FPR && TARGET_VSX"
5404 "xsmindp %x0,%x1,%x2"
5405 [(set_attr "type" "fp")])
5407 (define_split
5408 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5409 (match_operator:SFDF 3 "min_max_operator"
5410 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5411 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5412 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5413 && !TARGET_VSX"
5414 [(const_int 0)]
5415 {
5416 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5417 operands[2]);
5418 DONE;
5419 })
5421 (define_split
5422 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5423 (match_operator:SF 3 "min_max_operator"
5424 [(match_operand:SF 1 "gpc_reg_operand" "")
5425 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5426 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5427 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5428 [(const_int 0)]
5429 "
5430 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5431 operands[1], operands[2]);
5432 DONE;
5433 }")
5435 (define_expand "mov<mode>cc"
5436 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5437 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5438 (match_operand:GPR 2 "gpc_reg_operand" "")
5439 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5440 "TARGET_ISEL<sel>"
5441 "
5442 {
5443 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5444 DONE;
5445 else
5446 FAIL;
5447 }")
5449 ;; We use the BASE_REGS for the isel input operands because, if rA is
5450 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5451 ;; because we may switch the operands and rB may end up being rA.
5452 ;;
5453 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5454 ;; leave out the mode in operand 4 and use one pattern, but reload can
5455 ;; change the mode underneath our feet and then gets confused trying
5456 ;; to reload the value.
5457 (define_insn "isel_signed_<mode>"
5458 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5459 (if_then_else:GPR
5460 (match_operator 1 "scc_comparison_operator"
5461 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5462 (const_int 0)])
5463 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5464 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5465 "TARGET_ISEL<sel>"
5466 "*
5467 { return output_isel (operands); }"
5468 [(set_attr "type" "isel")
5469 (set_attr "length" "4")])
5471 (define_insn "isel_unsigned_<mode>"
5472 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5473 (if_then_else:GPR
5474 (match_operator 1 "scc_comparison_operator"
5475 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5476 (const_int 0)])
5477 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5478 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5479 "TARGET_ISEL<sel>"
5480 "*
5481 { return output_isel (operands); }"
5482 [(set_attr "type" "isel")
5483 (set_attr "length" "4")])
5485 ;; These patterns can be useful for combine; they let combine know that
5486 ;; isel can handle reversed comparisons so long as the operands are
5487 ;; registers.
5489 (define_insn "*isel_reversed_signed_<mode>"
5490 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5491 (if_then_else:GPR
5492 (match_operator 1 "scc_rev_comparison_operator"
5493 [(match_operand:CC 4 "cc_reg_operand" "y")
5494 (const_int 0)])
5495 (match_operand:GPR 2 "gpc_reg_operand" "b")
5496 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5497 "TARGET_ISEL<sel>"
5498 "*
5499 { return output_isel (operands); }"
5500 [(set_attr "type" "isel")
5501 (set_attr "length" "4")])
5503 (define_insn "*isel_reversed_unsigned_<mode>"
5504 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5505 (if_then_else:GPR
5506 (match_operator 1 "scc_rev_comparison_operator"
5507 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5508 (const_int 0)])
5509 (match_operand:GPR 2 "gpc_reg_operand" "b")
5510 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5511 "TARGET_ISEL<sel>"
5512 "*
5513 { return output_isel (operands); }"
5514 [(set_attr "type" "isel")
5515 (set_attr "length" "4")])
5517 (define_expand "movsfcc"
5518 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5519 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5520 (match_operand:SF 2 "gpc_reg_operand" "")
5521 (match_operand:SF 3 "gpc_reg_operand" "")))]
5522 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5523 "
5524 {
5525 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5526 DONE;
5527 else
5528 FAIL;
5529 }")
5531 (define_insn "*fselsfsf4"
5532 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5533 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5534 (match_operand:SF 4 "zero_fp_constant" "F"))
5535 (match_operand:SF 2 "gpc_reg_operand" "f")
5536 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5537 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5538 "fsel %0,%1,%2,%3"
5539 [(set_attr "type" "fp")])
5541 (define_insn "*fseldfsf4"
5542 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5543 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5544 (match_operand:DF 4 "zero_fp_constant" "F"))
5545 (match_operand:SF 2 "gpc_reg_operand" "f")
5546 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5547 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5548 "fsel %0,%1,%2,%3"
5549 [(set_attr "type" "fp")])
5551 ;; The conditional move instructions allow us to perform max and min
5552 ;; operations even when
5554 (define_split
5555 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5556 (match_operator:DF 3 "min_max_operator"
5557 [(match_operand:DF 1 "gpc_reg_operand" "")
5558 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5559 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5560 && !flag_trapping_math"
5561 [(const_int 0)]
5562 "
5563 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5564 operands[1], operands[2]);
5565 DONE;
5566 }")
5568 (define_expand "movdfcc"
5569 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5570 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5571 (match_operand:DF 2 "gpc_reg_operand" "")
5572 (match_operand:DF 3 "gpc_reg_operand" "")))]
5573 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5574 "
5575 {
5576 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5577 DONE;
5578 else
5579 FAIL;
5580 }")
5582 (define_insn "*fseldfdf4"
5583 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5584 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5585 (match_operand:DF 4 "zero_fp_constant" "F"))
5586 (match_operand:DF 2 "gpc_reg_operand" "d")
5587 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5588 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5589 "fsel %0,%1,%2,%3"
5590 [(set_attr "type" "fp")])
5592 (define_insn "*fselsfdf4"
5593 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5594 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5595 (match_operand:SF 4 "zero_fp_constant" "F"))
5596 (match_operand:DF 2 "gpc_reg_operand" "d")
5597 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5598 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5599 "fsel %0,%1,%2,%3"
5600 [(set_attr "type" "fp")])
5601 \f
5602 ;; Conversions to and from floating-point.
5604 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5605 ; don't want to support putting SImode in FPR registers.
5606 (define_insn "lfiwax"
5607 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5608 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5609 UNSPEC_LFIWAX))]
5610 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5611 "@
5612 lfiwax %0,%y1
5613 lxsiwax %x0,%y1
5614 mtvsrwa %x0,%1"
5615 [(set_attr "type" "fpload,fpload,mffgpr")])
5617 ; This split must be run before register allocation because it allocates the
5618 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5619 ; it earlier to allow for the combiner to merge insns together where it might
5620 ; not be needed and also in case the insns are deleted as dead code.
5622 (define_insn_and_split "floatsi<mode>2_lfiwax"
5623 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5624 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5625 (clobber (match_scratch:DI 2 "=d"))]
5626 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5627 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5628 "#"
5629 ""
5630 [(pc)]
5631 "
5632 {
5633 rtx dest = operands[0];
5634 rtx src = operands[1];
5635 rtx tmp;
5637 if (!MEM_P (src) && TARGET_POWERPC64
5638 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5639 tmp = convert_to_mode (DImode, src, false);
5640 else
5641 {
5642 tmp = operands[2];
5643 if (GET_CODE (tmp) == SCRATCH)
5644 tmp = gen_reg_rtx (DImode);
5645 if (MEM_P (src))
5646 {
5647 src = rs6000_address_for_fpconvert (src);
5648 emit_insn (gen_lfiwax (tmp, src));
5649 }
5650 else
5651 {
5652 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5653 emit_move_insn (stack, src);
5654 emit_insn (gen_lfiwax (tmp, stack));
5655 }
5656 }
5657 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5658 DONE;
5659 }"
5660 [(set_attr "length" "12")
5661 (set_attr "type" "fpload")])
5663 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5664 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5665 (float:SFDF
5666 (sign_extend:DI
5667 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5668 (clobber (match_scratch:DI 2 "=0,d"))]
5669 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5670 && <SI_CONVERT_FP>"
5671 "#"
5672 ""
5673 [(pc)]
5674 "
5675 {
5676 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5677 if (GET_CODE (operands[2]) == SCRATCH)
5678 operands[2] = gen_reg_rtx (DImode);
5679 emit_insn (gen_lfiwax (operands[2], operands[1]));
5680 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5681 DONE;
5682 }"
5683 [(set_attr "length" "8")
5684 (set_attr "type" "fpload")])
5686 (define_insn "lfiwzx"
5687 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5688 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5689 UNSPEC_LFIWZX))]
5690 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5691 "@
5692 lfiwzx %0,%y1
5693 lxsiwzx %x0,%y1
5694 mtvsrwz %x0,%1"
5695 [(set_attr "type" "fpload,fpload,mftgpr")])
5697 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5698 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5699 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5700 (clobber (match_scratch:DI 2 "=d"))]
5701 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5702 && <SI_CONVERT_FP>"
5703 "#"
5704 ""
5705 [(pc)]
5706 "
5707 {
5708 rtx dest = operands[0];
5709 rtx src = operands[1];
5710 rtx tmp;
5712 if (!MEM_P (src) && TARGET_POWERPC64
5713 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5714 tmp = convert_to_mode (DImode, src, true);
5715 else
5716 {
5717 tmp = operands[2];
5718 if (GET_CODE (tmp) == SCRATCH)
5719 tmp = gen_reg_rtx (DImode);
5720 if (MEM_P (src))
5721 {
5722 src = rs6000_address_for_fpconvert (src);
5723 emit_insn (gen_lfiwzx (tmp, src));
5724 }
5725 else
5726 {
5727 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5728 emit_move_insn (stack, src);
5729 emit_insn (gen_lfiwzx (tmp, stack));
5730 }
5731 }
5732 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5733 DONE;
5734 }"
5735 [(set_attr "length" "12")
5736 (set_attr "type" "fpload")])
5738 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5739 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5740 (unsigned_float:SFDF
5741 (zero_extend:DI
5742 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5743 (clobber (match_scratch:DI 2 "=0,d"))]
5744 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5745 && <SI_CONVERT_FP>"
5746 "#"
5747 ""
5748 [(pc)]
5749 "
5750 {
5751 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5752 if (GET_CODE (operands[2]) == SCRATCH)
5753 operands[2] = gen_reg_rtx (DImode);
5754 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5755 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5756 DONE;
5757 }"
5758 [(set_attr "length" "8")
5759 (set_attr "type" "fpload")])
5761 ; For each of these conversions, there is a define_expand, a define_insn
5762 ; with a '#' template, and a define_split (with C code). The idea is
5763 ; to allow constant folding with the template of the define_insn,
5764 ; then to have the insns split later (between sched1 and final).
5766 (define_expand "floatsidf2"
5767 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5768 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5769 (use (match_dup 2))
5770 (use (match_dup 3))
5771 (clobber (match_dup 4))
5772 (clobber (match_dup 5))
5773 (clobber (match_dup 6))])]
5774 "TARGET_HARD_FLOAT
5775 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5776 "
5777 {
5778 if (TARGET_E500_DOUBLE)
5779 {
5780 if (!REG_P (operands[1]))
5781 operands[1] = force_reg (SImode, operands[1]);
5782 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5783 DONE;
5784 }
5785 else if (TARGET_LFIWAX && TARGET_FCFID)
5786 {
5787 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5788 DONE;
5789 }
5790 else if (TARGET_FCFID)
5791 {
5792 rtx dreg = operands[1];
5793 if (!REG_P (dreg))
5794 dreg = force_reg (SImode, dreg);
5795 dreg = convert_to_mode (DImode, dreg, false);
5796 emit_insn (gen_floatdidf2 (operands[0], dreg));
5797 DONE;
5798 }
5800 if (!REG_P (operands[1]))
5801 operands[1] = force_reg (SImode, operands[1]);
5802 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5803 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5804 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5805 operands[5] = gen_reg_rtx (DFmode);
5806 operands[6] = gen_reg_rtx (SImode);
5807 }")
5809 (define_insn_and_split "*floatsidf2_internal"
5810 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5811 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5812 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5813 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5814 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5815 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5816 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5817 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5818 "#"
5819 ""
5820 [(pc)]
5821 "
5822 {
5823 rtx lowword, highword;
5824 gcc_assert (MEM_P (operands[4]));
5825 highword = adjust_address (operands[4], SImode, 0);
5826 lowword = adjust_address (operands[4], SImode, 4);
5827 if (! WORDS_BIG_ENDIAN)
5828 {
5829 rtx tmp;
5830 tmp = highword; highword = lowword; lowword = tmp;
5831 }
5833 emit_insn (gen_xorsi3 (operands[6], operands[1],
5834 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5835 emit_move_insn (lowword, operands[6]);
5836 emit_move_insn (highword, operands[2]);
5837 emit_move_insn (operands[5], operands[4]);
5838 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5839 DONE;
5840 }"
5841 [(set_attr "length" "24")
5842 (set_attr "type" "fp")])
5844 ;; If we don't have a direct conversion to single precision, don't enable this
5845 ;; conversion for 32-bit without fast math, because we don't have the insn to
5846 ;; generate the fixup swizzle to avoid double rounding problems.
5847 (define_expand "floatunssisf2"
5848 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5849 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5850 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5851 && (!TARGET_FPRS
5852 || (TARGET_FPRS
5853 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5854 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5855 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5856 "
5857 {
5858 if (!TARGET_FPRS)
5859 {
5860 if (!REG_P (operands[1]))
5861 operands[1] = force_reg (SImode, operands[1]);
5862 }
5863 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5864 {
5865 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5866 DONE;
5867 }
5868 else
5869 {
5870 rtx dreg = operands[1];
5871 if (!REG_P (dreg))
5872 dreg = force_reg (SImode, dreg);
5873 dreg = convert_to_mode (DImode, dreg, true);
5874 emit_insn (gen_floatdisf2 (operands[0], dreg));
5875 DONE;
5876 }
5877 }")
5879 (define_expand "floatunssidf2"
5880 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5881 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5882 (use (match_dup 2))
5883 (use (match_dup 3))
5884 (clobber (match_dup 4))
5885 (clobber (match_dup 5))])]
5886 "TARGET_HARD_FLOAT
5887 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5888 "
5889 {
5890 if (TARGET_E500_DOUBLE)
5891 {
5892 if (!REG_P (operands[1]))
5893 operands[1] = force_reg (SImode, operands[1]);
5894 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5895 DONE;
5896 }
5897 else if (TARGET_LFIWZX && TARGET_FCFID)
5898 {
5899 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5900 DONE;
5901 }
5902 else if (TARGET_FCFID)
5903 {
5904 rtx dreg = operands[1];
5905 if (!REG_P (dreg))
5906 dreg = force_reg (SImode, dreg);
5907 dreg = convert_to_mode (DImode, dreg, true);
5908 emit_insn (gen_floatdidf2 (operands[0], dreg));
5909 DONE;
5910 }
5912 if (!REG_P (operands[1]))
5913 operands[1] = force_reg (SImode, operands[1]);
5914 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5915 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5916 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5917 operands[5] = gen_reg_rtx (DFmode);
5918 }")
5920 (define_insn_and_split "*floatunssidf2_internal"
5921 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5922 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5923 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5924 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5925 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5926 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5927 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5928 && !(TARGET_FCFID && TARGET_POWERPC64)"
5929 "#"
5930 ""
5931 [(pc)]
5932 "
5933 {
5934 rtx lowword, highword;
5935 gcc_assert (MEM_P (operands[4]));
5936 highword = adjust_address (operands[4], SImode, 0);
5937 lowword = adjust_address (operands[4], SImode, 4);
5938 if (! WORDS_BIG_ENDIAN)
5939 {
5940 rtx tmp;
5941 tmp = highword; highword = lowword; lowword = tmp;
5942 }
5944 emit_move_insn (lowword, operands[1]);
5945 emit_move_insn (highword, operands[2]);
5946 emit_move_insn (operands[5], operands[4]);
5947 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5948 DONE;
5949 }"
5950 [(set_attr "length" "20")
5951 (set_attr "type" "fp")])
5953 (define_expand "fix_trunc<mode>si2"
5954 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5955 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5956 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5957 "
5958 {
5959 if (!<E500_CONVERT>)
5960 {
5961 rtx tmp, stack;
5963 if (TARGET_STFIWX)
5964 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5965 else
5966 {
5967 tmp = gen_reg_rtx (DImode);
5968 stack = rs6000_allocate_stack_temp (DImode, true, false);
5969 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5970 tmp, stack));
5971 }
5972 DONE;
5973 }
5974 }")
5976 ; Like the convert to float patterns, this insn must be split before
5977 ; register allocation so that it can allocate the memory slot if it
5978 ; needed
5979 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5980 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5981 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5982 (clobber (match_scratch:DI 2 "=d"))]
5983 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5984 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5985 && TARGET_STFIWX && can_create_pseudo_p ()"
5986 "#"
5987 ""
5988 [(pc)]
5989 {
5990 rtx dest = operands[0];
5991 rtx src = operands[1];
5992 rtx tmp = operands[2];
5994 if (GET_CODE (tmp) == SCRATCH)
5995 tmp = gen_reg_rtx (DImode);
5997 emit_insn (gen_fctiwz_<mode> (tmp, src));
5998 if (MEM_P (dest))
5999 {
6000 dest = rs6000_address_for_fpconvert (dest);
6001 emit_insn (gen_stfiwx (dest, tmp));
6002 DONE;
6003 }
6004 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6005 {
6006 dest = gen_lowpart (DImode, dest);
6007 emit_move_insn (dest, tmp);
6008 DONE;
6009 }
6010 else
6011 {
6012 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6013 emit_insn (gen_stfiwx (stack, tmp));
6014 emit_move_insn (dest, stack);
6015 DONE;
6016 }
6017 }
6018 [(set_attr "length" "12")
6019 (set_attr "type" "fp")])
6021 (define_insn_and_split "fix_trunc<mode>si2_internal"
6022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6023 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6024 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6025 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6026 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6027 "#"
6028 ""
6029 [(pc)]
6030 "
6031 {
6032 rtx lowword;
6033 gcc_assert (MEM_P (operands[3]));
6034 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6036 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6037 emit_move_insn (operands[3], operands[2]);
6038 emit_move_insn (operands[0], lowword);
6039 DONE;
6040 }"
6041 [(set_attr "length" "16")
6042 (set_attr "type" "fp")])
6044 (define_expand "fix_trunc<mode>di2"
6045 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6046 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6047 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6048 && TARGET_FCFID"
6049 "")
6051 (define_insn "*fix_trunc<mode>di2_fctidz"
6052 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6053 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6054 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6055 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6056 "fctidz %0,%1"
6057 [(set_attr "type" "fp")])
6059 (define_expand "fixuns_trunc<mode>si2"
6060 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6061 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6062 "TARGET_HARD_FLOAT
6063 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6064 || <E500_CONVERT>)"
6065 "
6066 {
6067 if (!<E500_CONVERT>)
6068 {
6069 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6070 DONE;
6071 }
6072 }")
6074 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6075 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6076 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6077 (clobber (match_scratch:DI 2 "=d"))]
6078 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6079 && TARGET_STFIWX && can_create_pseudo_p ()"
6080 "#"
6081 ""
6082 [(pc)]
6083 {
6084 rtx dest = operands[0];
6085 rtx src = operands[1];
6086 rtx tmp = operands[2];
6088 if (GET_CODE (tmp) == SCRATCH)
6089 tmp = gen_reg_rtx (DImode);
6091 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6092 if (MEM_P (dest))
6093 {
6094 dest = rs6000_address_for_fpconvert (dest);
6095 emit_insn (gen_stfiwx (dest, tmp));
6096 DONE;
6097 }
6098 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6099 {
6100 dest = gen_lowpart (DImode, dest);
6101 emit_move_insn (dest, tmp);
6102 DONE;
6103 }
6104 else
6105 {
6106 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6107 emit_insn (gen_stfiwx (stack, tmp));
6108 emit_move_insn (dest, stack);
6109 DONE;
6110 }
6111 }
6112 [(set_attr "length" "12")
6113 (set_attr "type" "fp")])
6115 (define_expand "fixuns_trunc<mode>di2"
6116 [(set (match_operand:DI 0 "register_operand" "")
6117 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6118 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6119 "")
6121 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6122 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6123 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6124 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6125 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6126 "fctiduz %0,%1"
6127 [(set_attr "type" "fp")])
6129 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6130 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6131 ; because the first makes it clear that operand 0 is not live
6132 ; before the instruction.
6133 (define_insn "fctiwz_<mode>"
6134 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6135 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6136 UNSPEC_FCTIWZ))]
6137 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6138 "fctiwz %0,%1"
6139 [(set_attr "type" "fp")])
6141 (define_insn "fctiwuz_<mode>"
6142 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6143 (unspec:DI [(unsigned_fix:SI
6144 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6145 UNSPEC_FCTIWUZ))]
6146 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6147 "fctiwuz %0,%1"
6148 [(set_attr "type" "fp")])
6150 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6151 ;; since the friz instruction does not truncate the value if the floating
6152 ;; point value is < LONG_MIN or > LONG_MAX.
6153 (define_insn "*friz"
6154 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6155 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6156 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6157 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6158 && !flag_trapping_math && TARGET_FRIZ"
6159 "friz %0,%1"
6160 [(set_attr "type" "fp")])
6162 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6163 ;; load to properly sign extend the value, but at least doing a store, load
6164 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6165 ;; if we have 32-bit memory ops
6166 (define_insn_and_split "*round32<mode>2_fprs"
6167 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6168 (float:SFDF
6169 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6170 (clobber (match_scratch:DI 2 "=d"))
6171 (clobber (match_scratch:DI 3 "=d"))]
6172 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6173 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6174 && can_create_pseudo_p ()"
6175 "#"
6176 ""
6177 [(pc)]
6178 {
6179 rtx dest = operands[0];
6180 rtx src = operands[1];
6181 rtx tmp1 = operands[2];
6182 rtx tmp2 = operands[3];
6183 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6185 if (GET_CODE (tmp1) == SCRATCH)
6186 tmp1 = gen_reg_rtx (DImode);
6187 if (GET_CODE (tmp2) == SCRATCH)
6188 tmp2 = gen_reg_rtx (DImode);
6190 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6191 emit_insn (gen_stfiwx (stack, tmp1));
6192 emit_insn (gen_lfiwax (tmp2, stack));
6193 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6194 DONE;
6195 }
6196 [(set_attr "type" "fpload")
6197 (set_attr "length" "16")])
6199 (define_insn_and_split "*roundu32<mode>2_fprs"
6200 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6201 (unsigned_float:SFDF
6202 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6203 (clobber (match_scratch:DI 2 "=d"))
6204 (clobber (match_scratch:DI 3 "=d"))]
6205 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6206 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6207 && can_create_pseudo_p ()"
6208 "#"
6209 ""
6210 [(pc)]
6211 {
6212 rtx dest = operands[0];
6213 rtx src = operands[1];
6214 rtx tmp1 = operands[2];
6215 rtx tmp2 = operands[3];
6216 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6218 if (GET_CODE (tmp1) == SCRATCH)
6219 tmp1 = gen_reg_rtx (DImode);
6220 if (GET_CODE (tmp2) == SCRATCH)
6221 tmp2 = gen_reg_rtx (DImode);
6223 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6224 emit_insn (gen_stfiwx (stack, tmp1));
6225 emit_insn (gen_lfiwzx (tmp2, stack));
6226 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6227 DONE;
6228 }
6229 [(set_attr "type" "fpload")
6230 (set_attr "length" "16")])
6232 ;; No VSX equivalent to fctid
6233 (define_insn "lrint<mode>di2"
6234 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6235 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6236 UNSPEC_FCTID))]
6237 "TARGET_<MODE>_FPR && TARGET_FPRND"
6238 "fctid %0,%1"
6239 [(set_attr "type" "fp")])
6241 (define_insn "btrunc<mode>2"
6242 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6243 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6244 UNSPEC_FRIZ))]
6245 "TARGET_<MODE>_FPR && TARGET_FPRND"
6246 "@
6247 friz %0,%1
6248 xsrdpiz %x0,%x1"
6249 [(set_attr "type" "fp")
6250 (set_attr "fp_type" "fp_addsub_<Fs>")])
6252 (define_insn "ceil<mode>2"
6253 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6254 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6255 UNSPEC_FRIP))]
6256 "TARGET_<MODE>_FPR && TARGET_FPRND"
6257 "@
6258 frip %0,%1
6259 xsrdpip %x0,%x1"
6260 [(set_attr "type" "fp")
6261 (set_attr "fp_type" "fp_addsub_<Fs>")])
6263 (define_insn "floor<mode>2"
6264 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6265 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6266 UNSPEC_FRIM))]
6267 "TARGET_<MODE>_FPR && TARGET_FPRND"
6268 "@
6269 frim %0,%1
6270 xsrdpim %x0,%x1"
6271 [(set_attr "type" "fp")
6272 (set_attr "fp_type" "fp_addsub_<Fs>")])
6274 ;; No VSX equivalent to frin
6275 (define_insn "round<mode>2"
6276 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6277 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6278 UNSPEC_FRIN))]
6279 "TARGET_<MODE>_FPR && TARGET_FPRND"
6280 "frin %0,%1"
6281 [(set_attr "type" "fp")
6282 (set_attr "fp_type" "fp_addsub_<Fs>")])
6284 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6285 (define_insn "stfiwx"
6286 [(set (match_operand:SI 0 "memory_operand" "=Z")
6287 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6288 UNSPEC_STFIWX))]
6289 "TARGET_PPC_GFXOPT"
6290 "stfiwx %1,%y0"
6291 [(set_attr "type" "fpstore")])
6293 ;; If we don't have a direct conversion to single precision, don't enable this
6294 ;; conversion for 32-bit without fast math, because we don't have the insn to
6295 ;; generate the fixup swizzle to avoid double rounding problems.
6296 (define_expand "floatsisf2"
6297 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6298 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6299 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6300 && (!TARGET_FPRS
6301 || (TARGET_FPRS
6302 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6303 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6304 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6305 "
6306 {
6307 if (!TARGET_FPRS)
6308 {
6309 if (!REG_P (operands[1]))
6310 operands[1] = force_reg (SImode, operands[1]);
6311 }
6312 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6313 {
6314 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6315 DONE;
6316 }
6317 else if (TARGET_FCFID && TARGET_LFIWAX)
6318 {
6319 rtx dfreg = gen_reg_rtx (DFmode);
6320 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6321 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6322 DONE;
6323 }
6324 else
6325 {
6326 rtx dreg = operands[1];
6327 if (!REG_P (dreg))
6328 dreg = force_reg (SImode, dreg);
6329 dreg = convert_to_mode (DImode, dreg, false);
6330 emit_insn (gen_floatdisf2 (operands[0], dreg));
6331 DONE;
6332 }
6333 }")
6335 (define_expand "floatdidf2"
6336 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6337 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6338 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6339 "")
6341 (define_insn "*floatdidf2_fpr"
6342 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6343 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6344 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6345 && !VECTOR_UNIT_VSX_P (DFmode)"
6346 "fcfid %0,%1"
6347 [(set_attr "type" "fp")])
6349 ; Allow the combiner to merge source memory operands to the conversion so that
6350 ; the optimizer/register allocator doesn't try to load the value too early in a
6351 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6352 ; hit. We will split after reload to avoid the trip through the GPRs
6354 (define_insn_and_split "*floatdidf2_mem"
6355 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6356 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6357 (clobber (match_scratch:DI 2 "=d"))]
6358 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6359 "#"
6360 "&& reload_completed"
6361 [(set (match_dup 2) (match_dup 1))
6362 (set (match_dup 0) (float:DF (match_dup 2)))]
6363 ""
6364 [(set_attr "length" "8")
6365 (set_attr "type" "fpload")])
6367 (define_expand "floatunsdidf2"
6368 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6369 (unsigned_float:DF
6370 (match_operand:DI 1 "gpc_reg_operand" "")))]
6371 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6372 "")
6374 (define_insn "*floatunsdidf2_fcfidu"
6375 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6376 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6377 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6378 "fcfidu %0,%1"
6379 [(set_attr "type" "fp")
6380 (set_attr "length" "4")])
6382 (define_insn_and_split "*floatunsdidf2_mem"
6383 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6384 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6385 (clobber (match_scratch:DI 2 "=d"))]
6386 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6387 "#"
6388 "&& reload_completed"
6389 [(set (match_dup 2) (match_dup 1))
6390 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6391 ""
6392 [(set_attr "length" "8")
6393 (set_attr "type" "fpload")])
6395 (define_expand "floatdisf2"
6396 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6397 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6398 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6399 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6400 "
6401 {
6402 if (!TARGET_FCFIDS)
6403 {
6404 rtx val = operands[1];
6405 if (!flag_unsafe_math_optimizations)
6406 {
6407 rtx label = gen_label_rtx ();
6408 val = gen_reg_rtx (DImode);
6409 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6410 emit_label (label);
6411 }
6412 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6413 DONE;
6414 }
6415 }")
6417 (define_insn "floatdisf2_fcfids"
6418 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6419 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6420 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6421 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6422 "fcfids %0,%1"
6423 [(set_attr "type" "fp")])
6425 (define_insn_and_split "*floatdisf2_mem"
6426 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6427 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6428 (clobber (match_scratch:DI 2 "=f"))]
6429 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6430 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6431 "#"
6432 "&& reload_completed"
6433 [(pc)]
6434 "
6435 {
6436 emit_move_insn (operands[2], operands[1]);
6437 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6438 DONE;
6439 }"
6440 [(set_attr "length" "8")])
6442 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6443 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6444 ;; from double rounding.
6445 ;; Instead of creating a new cpu type for two FP operations, just use fp
6446 (define_insn_and_split "floatdisf2_internal1"
6447 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6448 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6449 (clobber (match_scratch:DF 2 "=d"))]
6450 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6451 "#"
6452 "&& reload_completed"
6453 [(set (match_dup 2)
6454 (float:DF (match_dup 1)))
6455 (set (match_dup 0)
6456 (float_truncate:SF (match_dup 2)))]
6457 ""
6458 [(set_attr "length" "8")
6459 (set_attr "type" "fp")])
6461 ;; Twiddles bits to avoid double rounding.
6462 ;; Bits that might be truncated when converting to DFmode are replaced
6463 ;; by a bit that won't be lost at that stage, but is below the SFmode
6464 ;; rounding position.
6465 (define_expand "floatdisf2_internal2"
6466 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6467 (const_int 53)))
6468 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6469 (const_int 2047)))
6470 (clobber (scratch:CC))])
6471 (set (match_dup 3) (plus:DI (match_dup 3)
6472 (const_int 1)))
6473 (set (match_dup 0) (plus:DI (match_dup 0)
6474 (const_int 2047)))
6475 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6476 (const_int 2)))
6477 (set (match_dup 0) (ior:DI (match_dup 0)
6478 (match_dup 1)))
6479 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6480 (const_int -2048)))
6481 (clobber (scratch:CC))])
6482 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6483 (label_ref (match_operand:DI 2 "" ""))
6484 (pc)))
6485 (set (match_dup 0) (match_dup 1))]
6486 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6487 "
6488 {
6489 operands[3] = gen_reg_rtx (DImode);
6490 operands[4] = gen_reg_rtx (CCUNSmode);
6491 }")
6493 (define_expand "floatunsdisf2"
6494 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6495 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6496 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6497 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6498 "")
6500 (define_insn "floatunsdisf2_fcfidus"
6501 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6502 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6503 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6504 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6505 "fcfidus %0,%1"
6506 [(set_attr "type" "fp")])
6508 (define_insn_and_split "*floatunsdisf2_mem"
6509 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6510 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6511 (clobber (match_scratch:DI 2 "=f"))]
6512 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6513 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6514 "#"
6515 "&& reload_completed"
6516 [(pc)]
6517 "
6518 {
6519 emit_move_insn (operands[2], operands[1]);
6520 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6521 DONE;
6522 }"
6523 [(set_attr "length" "8")
6524 (set_attr "type" "fpload")])
6525 \f
6526 ;; Define the DImode operations that can be done in a small number
6527 ;; of instructions. The & constraints are to prevent the register
6528 ;; allocator from allocating registers that overlap with the inputs
6529 ;; (for example, having an input in 7,8 and an output in 6,7). We
6530 ;; also allow for the output being the same as one of the inputs.
6532 (define_insn "*adddi3_noppc64"
6533 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6534 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6535 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6536 "! TARGET_POWERPC64"
6537 "*
6538 {
6539 if (WORDS_BIG_ENDIAN)
6540 return (GET_CODE (operands[2])) != CONST_INT
6541 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6542 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6543 else
6544 return (GET_CODE (operands[2])) != CONST_INT
6545 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6546 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6547 }"
6548 [(set_attr "type" "two")
6549 (set_attr "length" "8")])
6551 (define_insn "*subdi3_noppc64"
6552 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6553 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6554 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6555 "! TARGET_POWERPC64"
6556 "*
6557 {
6558 if (WORDS_BIG_ENDIAN)
6559 return (GET_CODE (operands[1]) != CONST_INT)
6560 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6561 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6562 else
6563 return (GET_CODE (operands[1]) != CONST_INT)
6564 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6565 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6566 }"
6567 [(set_attr "type" "two")
6568 (set_attr "length" "8")])
6570 (define_insn "*negdi2_noppc64"
6571 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6572 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6573 "! TARGET_POWERPC64"
6574 "*
6575 {
6576 return (WORDS_BIG_ENDIAN)
6577 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6578 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6579 }"
6580 [(set_attr "type" "two")
6581 (set_attr "length" "8")])
6583 (define_insn "mulsidi3"
6584 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6585 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6586 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6587 "! TARGET_POWERPC64"
6588 {
6589 return (WORDS_BIG_ENDIAN)
6590 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6591 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6592 }
6593 [(set_attr "type" "imul")
6594 (set_attr "length" "8")])
6596 (define_split
6597 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6598 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6599 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6600 "! TARGET_POWERPC64 && reload_completed"
6601 [(set (match_dup 3)
6602 (truncate:SI
6603 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6604 (sign_extend:DI (match_dup 2)))
6605 (const_int 32))))
6606 (set (match_dup 4)
6607 (mult:SI (match_dup 1)
6608 (match_dup 2)))]
6609 "
6610 {
6611 int endian = (WORDS_BIG_ENDIAN == 0);
6612 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6613 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6614 }")
6616 (define_insn "umulsidi3"
6617 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6618 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6619 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6620 "! TARGET_POWERPC64"
6621 "*
6622 {
6623 return (WORDS_BIG_ENDIAN)
6624 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6625 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6626 }"
6627 [(set_attr "type" "imul")
6628 (set_attr "length" "8")])
6630 (define_split
6631 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6632 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6633 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6634 "! TARGET_POWERPC64 && reload_completed"
6635 [(set (match_dup 3)
6636 (truncate:SI
6637 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6638 (zero_extend:DI (match_dup 2)))
6639 (const_int 32))))
6640 (set (match_dup 4)
6641 (mult:SI (match_dup 1)
6642 (match_dup 2)))]
6643 "
6644 {
6645 int endian = (WORDS_BIG_ENDIAN == 0);
6646 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6647 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6648 }")
6650 (define_insn "smulsi3_highpart"
6651 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6652 (truncate:SI
6653 (lshiftrt:DI (mult:DI (sign_extend:DI
6654 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6655 (sign_extend:DI
6656 (match_operand:SI 2 "gpc_reg_operand" "r")))
6657 (const_int 32))))]
6658 ""
6659 "mulhw %0,%1,%2"
6660 [(set_attr "type" "imul")])
6662 (define_insn "umulsi3_highpart"
6663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6664 (truncate:SI
6665 (lshiftrt:DI (mult:DI (zero_extend:DI
6666 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6667 (zero_extend:DI
6668 (match_operand:SI 2 "gpc_reg_operand" "r")))
6669 (const_int 32))))]
6670 ""
6671 "mulhwu %0,%1,%2"
6672 [(set_attr "type" "imul")])
6674 ;; Shift by a variable amount is too complex to be worth open-coding. We
6675 ;; just handle shifts by constants.
6676 (define_insn "ashrdi3_no_power"
6677 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6678 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6679 (match_operand:SI 2 "const_int_operand" "M,i")))]
6680 "!TARGET_POWERPC64"
6681 "*
6682 {
6683 switch (which_alternative)
6684 {
6685 default:
6686 gcc_unreachable ();
6687 case 0:
6688 if (WORDS_BIG_ENDIAN)
6689 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6690 else
6691 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6692 case 1:
6693 if (WORDS_BIG_ENDIAN)
6694 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6695 else
6696 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6697 }
6698 }"
6699 [(set_attr "type" "two,three")
6700 (set_attr "length" "8,12")])
6702 (define_insn "*ashrdisi3_noppc64be"
6703 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6704 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6705 (const_int 32)) 4))]
6706 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6707 "*
6708 {
6709 if (REGNO (operands[0]) == REGNO (operands[1]))
6710 return \"\";
6711 else
6712 return \"mr %0,%1\";
6713 }"
6714 [(set_attr "length" "4")])
6716 \f
6717 ;; PowerPC64 DImode operations.
6719 (define_insn "muldi3"
6720 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6721 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6722 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6723 "TARGET_POWERPC64"
6724 "@
6725 mulld %0,%1,%2
6726 mulli %0,%1,%2"
6727 [(set (attr "type")
6728 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6729 (const_string "imul3")
6730 (match_operand:SI 2 "short_cint_operand" "")
6731 (const_string "imul2")]
6732 (const_string "lmul")))])
6734 (define_insn "*muldi3_internal1"
6735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6736 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6737 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6738 (const_int 0)))
6739 (clobber (match_scratch:DI 3 "=r,r"))]
6740 "TARGET_POWERPC64"
6741 "@
6742 mulld. %3,%1,%2
6743 #"
6744 [(set_attr "type" "lmul_compare")
6745 (set_attr "length" "4,8")])
6747 (define_split
6748 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6749 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6750 (match_operand:DI 2 "gpc_reg_operand" ""))
6751 (const_int 0)))
6752 (clobber (match_scratch:DI 3 ""))]
6753 "TARGET_POWERPC64 && reload_completed"
6754 [(set (match_dup 3)
6755 (mult:DI (match_dup 1) (match_dup 2)))
6756 (set (match_dup 0)
6757 (compare:CC (match_dup 3)
6758 (const_int 0)))]
6759 "")
6761 (define_insn "*muldi3_internal2"
6762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6763 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6764 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6765 (const_int 0)))
6766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6767 (mult:DI (match_dup 1) (match_dup 2)))]
6768 "TARGET_POWERPC64"
6769 "@
6770 mulld. %0,%1,%2
6771 #"
6772 [(set_attr "type" "lmul_compare")
6773 (set_attr "length" "4,8")])
6775 (define_split
6776 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6777 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6778 (match_operand:DI 2 "gpc_reg_operand" ""))
6779 (const_int 0)))
6780 (set (match_operand:DI 0 "gpc_reg_operand" "")
6781 (mult:DI (match_dup 1) (match_dup 2)))]
6782 "TARGET_POWERPC64 && reload_completed"
6783 [(set (match_dup 0)
6784 (mult:DI (match_dup 1) (match_dup 2)))
6785 (set (match_dup 3)
6786 (compare:CC (match_dup 0)
6787 (const_int 0)))]
6788 "")
6790 (define_insn "smuldi3_highpart"
6791 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6792 (truncate:DI
6793 (lshiftrt:TI (mult:TI (sign_extend:TI
6794 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6795 (sign_extend:TI
6796 (match_operand:DI 2 "gpc_reg_operand" "r")))
6797 (const_int 64))))]
6798 "TARGET_POWERPC64"
6799 "mulhd %0,%1,%2"
6800 [(set_attr "type" "lmul")])
6802 (define_insn "umuldi3_highpart"
6803 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6804 (truncate:DI
6805 (lshiftrt:TI (mult:TI (zero_extend:TI
6806 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6807 (zero_extend:TI
6808 (match_operand:DI 2 "gpc_reg_operand" "r")))
6809 (const_int 64))))]
6810 "TARGET_POWERPC64"
6811 "mulhdu %0,%1,%2"
6812 [(set_attr "type" "lmul")])
6814 (define_expand "mulditi3"
6815 [(set (match_operand:TI 0 "gpc_reg_operand")
6816 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6817 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6818 "TARGET_POWERPC64"
6819 {
6820 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6821 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6822 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
6823 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6824 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6825 DONE;
6826 })
6828 (define_expand "umulditi3"
6829 [(set (match_operand:TI 0 "gpc_reg_operand")
6830 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6831 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6832 "TARGET_POWERPC64"
6833 {
6834 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6835 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6836 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
6837 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6838 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6839 DONE;
6840 })
6842 (define_insn "rotldi3"
6843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6844 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6845 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6846 "TARGET_POWERPC64"
6847 "@
6848 rldcl %0,%1,%2,0
6849 rldicl %0,%1,%H2,0"
6850 [(set_attr "type" "var_shift_rotate,integer")])
6852 (define_insn "*rotldi3_internal2"
6853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6854 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6855 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6856 (const_int 0)))
6857 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6858 "TARGET_64BIT"
6859 "@
6860 rldcl. %3,%1,%2,0
6861 rldicl. %3,%1,%H2,0
6862 #
6863 #"
6864 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6865 (set_attr "length" "4,4,8,8")])
6867 (define_split
6868 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6869 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6870 (match_operand:DI 2 "reg_or_cint_operand" ""))
6871 (const_int 0)))
6872 (clobber (match_scratch:DI 3 ""))]
6873 "TARGET_POWERPC64 && reload_completed"
6874 [(set (match_dup 3)
6875 (rotate:DI (match_dup 1) (match_dup 2)))
6876 (set (match_dup 0)
6877 (compare:CC (match_dup 3)
6878 (const_int 0)))]
6879 "")
6881 (define_insn "*rotldi3_internal3"
6882 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6883 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6884 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6885 (const_int 0)))
6886 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6887 (rotate:DI (match_dup 1) (match_dup 2)))]
6888 "TARGET_64BIT"
6889 "@
6890 rldcl. %0,%1,%2,0
6891 rldicl. %0,%1,%H2,0
6892 #
6893 #"
6894 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6895 (set_attr "length" "4,4,8,8")])
6897 (define_split
6898 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6899 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6900 (match_operand:DI 2 "reg_or_cint_operand" ""))
6901 (const_int 0)))
6902 (set (match_operand:DI 0 "gpc_reg_operand" "")
6903 (rotate:DI (match_dup 1) (match_dup 2)))]
6904 "TARGET_POWERPC64 && reload_completed"
6905 [(set (match_dup 0)
6906 (rotate:DI (match_dup 1) (match_dup 2)))
6907 (set (match_dup 3)
6908 (compare:CC (match_dup 0)
6909 (const_int 0)))]
6910 "")
6912 (define_insn "*rotldi3_internal4"
6913 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6914 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6915 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6916 (match_operand:DI 3 "mask64_operand" "n,n")))]
6917 "TARGET_POWERPC64"
6918 "@
6919 rldc%B3 %0,%1,%2,%S3
6920 rldic%B3 %0,%1,%H2,%S3"
6921 [(set_attr "type" "var_shift_rotate,integer")])
6923 (define_insn "*rotldi3_internal5"
6924 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6925 (compare:CC (and:DI
6926 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6927 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6928 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6929 (const_int 0)))
6930 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6931 "TARGET_64BIT"
6932 "@
6933 rldc%B3. %4,%1,%2,%S3
6934 rldic%B3. %4,%1,%H2,%S3
6935 #
6936 #"
6937 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6938 (set_attr "length" "4,4,8,8")])
6940 (define_split
6941 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6942 (compare:CC (and:DI
6943 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6944 (match_operand:DI 2 "reg_or_cint_operand" ""))
6945 (match_operand:DI 3 "mask64_operand" ""))
6946 (const_int 0)))
6947 (clobber (match_scratch:DI 4 ""))]
6948 "TARGET_POWERPC64 && reload_completed"
6949 [(set (match_dup 4)
6950 (and:DI (rotate:DI (match_dup 1)
6951 (match_dup 2))
6952 (match_dup 3)))
6953 (set (match_dup 0)
6954 (compare:CC (match_dup 4)
6955 (const_int 0)))]
6956 "")
6958 (define_insn "*rotldi3_internal6"
6959 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6960 (compare:CC (and:DI
6961 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6962 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6963 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6964 (const_int 0)))
6965 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6966 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6967 "TARGET_64BIT"
6968 "@
6969 rldc%B3. %0,%1,%2,%S3
6970 rldic%B3. %0,%1,%H2,%S3
6971 #
6972 #"
6973 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6974 (set_attr "length" "4,4,8,8")])
6976 (define_split
6977 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6978 (compare:CC (and:DI
6979 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6980 (match_operand:DI 2 "reg_or_cint_operand" ""))
6981 (match_operand:DI 3 "mask64_operand" ""))
6982 (const_int 0)))
6983 (set (match_operand:DI 0 "gpc_reg_operand" "")
6984 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6985 "TARGET_POWERPC64 && reload_completed"
6986 [(set (match_dup 0)
6987 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6988 (set (match_dup 4)
6989 (compare:CC (match_dup 0)
6990 (const_int 0)))]
6991 "")
6993 (define_insn "*rotldi3_internal7le"
6994 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6995 (zero_extend:DI
6996 (subreg:QI
6997 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6998 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6999 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7000 "@
7001 rldcl %0,%1,%2,56
7002 rldicl %0,%1,%H2,56"
7003 [(set_attr "type" "var_shift_rotate,integer")])
7005 (define_insn "*rotldi3_internal7be"
7006 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7007 (zero_extend:DI
7008 (subreg:QI
7009 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7010 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
7011 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7012 "@
7013 rldcl %0,%1,%2,56
7014 rldicl %0,%1,%H2,56"
7015 [(set_attr "type" "var_shift_rotate,integer")])
7017 (define_insn "*rotldi3_internal8le"
7018 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7019 (compare:CC (zero_extend:DI
7020 (subreg:QI
7021 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7022 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7023 (const_int 0)))
7024 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7025 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7026 "@
7027 rldcl. %3,%1,%2,56
7028 rldicl. %3,%1,%H2,56
7029 #
7030 #"
7031 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7032 (set_attr "length" "4,4,8,8")])
7034 (define_insn "*rotldi3_internal8be"
7035 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7036 (compare:CC (zero_extend:DI
7037 (subreg:QI
7038 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7039 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7040 (const_int 0)))
7041 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7042 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7043 "@
7044 rldcl. %3,%1,%2,56
7045 rldicl. %3,%1,%H2,56
7046 #
7047 #"
7048 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7049 (set_attr "length" "4,4,8,8")])
7051 (define_split
7052 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7053 (compare:CC (zero_extend:DI
7054 (subreg:QI
7055 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7056 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7057 (const_int 0)))
7058 (clobber (match_scratch:DI 3 ""))]
7059 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7060 [(set (match_dup 3)
7061 (zero_extend:DI (subreg:QI
7062 (rotate:DI (match_dup 1)
7063 (match_dup 2)) 0)))
7064 (set (match_dup 0)
7065 (compare:CC (match_dup 3)
7066 (const_int 0)))]
7067 "")
7069 (define_split
7070 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7071 (compare:CC (zero_extend:DI
7072 (subreg:QI
7073 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7074 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7075 (const_int 0)))
7076 (clobber (match_scratch:DI 3 ""))]
7077 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7078 [(set (match_dup 3)
7079 (zero_extend:DI (subreg:QI
7080 (rotate:DI (match_dup 1)
7081 (match_dup 2)) 7)))
7082 (set (match_dup 0)
7083 (compare:CC (match_dup 3)
7084 (const_int 0)))]
7085 "")
7087 (define_insn "*rotldi3_internal9le"
7088 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7089 (compare:CC (zero_extend:DI
7090 (subreg:QI
7091 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7092 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7093 (const_int 0)))
7094 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7095 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7096 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7097 "@
7098 rldcl. %0,%1,%2,56
7099 rldicl. %0,%1,%H2,56
7100 #
7101 #"
7102 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7103 (set_attr "length" "4,4,8,8")])
7105 (define_insn "*rotldi3_internal9be"
7106 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7107 (compare:CC (zero_extend:DI
7108 (subreg:QI
7109 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7110 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7111 (const_int 0)))
7112 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7113 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7114 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7115 "@
7116 rldcl. %0,%1,%2,56
7117 rldicl. %0,%1,%H2,56
7118 #
7119 #"
7120 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7121 (set_attr "length" "4,4,8,8")])
7123 (define_split
7124 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7125 (compare:CC (zero_extend:DI
7126 (subreg:QI
7127 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7128 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7129 (const_int 0)))
7130 (set (match_operand:DI 0 "gpc_reg_operand" "")
7131 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7132 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7133 [(set (match_dup 0)
7134 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7135 (set (match_dup 3)
7136 (compare:CC (match_dup 0)
7137 (const_int 0)))]
7138 "")
7140 (define_split
7141 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7142 (compare:CC (zero_extend:DI
7143 (subreg:QI
7144 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7145 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7146 (const_int 0)))
7147 (set (match_operand:DI 0 "gpc_reg_operand" "")
7148 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7149 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7150 [(set (match_dup 0)
7151 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7152 (set (match_dup 3)
7153 (compare:CC (match_dup 0)
7154 (const_int 0)))]
7155 "")
7157 (define_insn "*rotldi3_internal10le"
7158 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7159 (zero_extend:DI
7160 (subreg:HI
7161 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7162 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7163 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7164 "@
7165 rldcl %0,%1,%2,48
7166 rldicl %0,%1,%H2,48"
7167 [(set_attr "type" "var_shift_rotate,integer")])
7169 (define_insn "*rotldi3_internal10be"
7170 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7171 (zero_extend:DI
7172 (subreg:HI
7173 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7174 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
7175 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7176 "@
7177 rldcl %0,%1,%2,48
7178 rldicl %0,%1,%H2,48"
7179 [(set_attr "type" "var_shift_rotate,integer")])
7181 (define_insn "*rotldi3_internal11le"
7182 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7183 (compare:CC (zero_extend:DI
7184 (subreg:HI
7185 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7186 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7187 (const_int 0)))
7188 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7189 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7190 "@
7191 rldcl. %3,%1,%2,48
7192 rldicl. %3,%1,%H2,48
7193 #
7194 #"
7195 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7196 (set_attr "length" "4,4,8,8")])
7198 (define_insn "*rotldi3_internal11be"
7199 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7200 (compare:CC (zero_extend:DI
7201 (subreg:HI
7202 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7203 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7204 (const_int 0)))
7205 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7206 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7207 "@
7208 rldcl. %3,%1,%2,48
7209 rldicl. %3,%1,%H2,48
7210 #
7211 #"
7212 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7213 (set_attr "length" "4,4,8,8")])
7215 (define_split
7216 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7217 (compare:CC (zero_extend:DI
7218 (subreg:HI
7219 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7220 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7221 (const_int 0)))
7222 (clobber (match_scratch:DI 3 ""))]
7223 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7224 [(set (match_dup 3)
7225 (zero_extend:DI (subreg:HI
7226 (rotate:DI (match_dup 1)
7227 (match_dup 2)) 0)))
7228 (set (match_dup 0)
7229 (compare:CC (match_dup 3)
7230 (const_int 0)))]
7231 "")
7233 (define_split
7234 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7235 (compare:CC (zero_extend:DI
7236 (subreg:HI
7237 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7238 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7239 (const_int 0)))
7240 (clobber (match_scratch:DI 3 ""))]
7241 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7242 [(set (match_dup 3)
7243 (zero_extend:DI (subreg:HI
7244 (rotate:DI (match_dup 1)
7245 (match_dup 2)) 6)))
7246 (set (match_dup 0)
7247 (compare:CC (match_dup 3)
7248 (const_int 0)))]
7249 "")
7251 (define_insn "*rotldi3_internal12le"
7252 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7253 (compare:CC (zero_extend:DI
7254 (subreg:HI
7255 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7256 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7257 (const_int 0)))
7258 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7259 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7260 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7261 "@
7262 rldcl. %0,%1,%2,48
7263 rldicl. %0,%1,%H2,48
7264 #
7265 #"
7266 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7267 (set_attr "length" "4,4,8,8")])
7269 (define_insn "*rotldi3_internal12be"
7270 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7271 (compare:CC (zero_extend:DI
7272 (subreg:HI
7273 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7274 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7275 (const_int 0)))
7276 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7277 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7278 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7279 "@
7280 rldcl. %0,%1,%2,48
7281 rldicl. %0,%1,%H2,48
7282 #
7283 #"
7284 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7285 (set_attr "length" "4,4,8,8")])
7287 (define_split
7288 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7289 (compare:CC (zero_extend:DI
7290 (subreg:HI
7291 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7292 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7293 (const_int 0)))
7294 (set (match_operand:DI 0 "gpc_reg_operand" "")
7295 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7296 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7297 [(set (match_dup 0)
7298 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7299 (set (match_dup 3)
7300 (compare:CC (match_dup 0)
7301 (const_int 0)))]
7302 "")
7304 (define_split
7305 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7306 (compare:CC (zero_extend:DI
7307 (subreg:HI
7308 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7309 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7310 (const_int 0)))
7311 (set (match_operand:DI 0 "gpc_reg_operand" "")
7312 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7313 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7314 [(set (match_dup 0)
7315 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7316 (set (match_dup 3)
7317 (compare:CC (match_dup 0)
7318 (const_int 0)))]
7319 "")
7321 (define_insn "*rotldi3_internal13le"
7322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7323 (zero_extend:DI
7324 (subreg:SI
7325 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7326 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7327 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7328 "@
7329 rldcl %0,%1,%2,32
7330 rldicl %0,%1,%H2,32"
7331 [(set_attr "type" "var_shift_rotate,integer")])
7333 (define_insn "*rotldi3_internal13be"
7334 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7335 (zero_extend:DI
7336 (subreg:SI
7337 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7338 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
7339 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7340 "@
7341 rldcl %0,%1,%2,32
7342 rldicl %0,%1,%H2,32"
7343 [(set_attr "type" "var_shift_rotate,integer")])
7345 (define_insn "*rotldi3_internal14le"
7346 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7347 (compare:CC (zero_extend:DI
7348 (subreg:SI
7349 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7350 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7351 (const_int 0)))
7352 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7353 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7354 "@
7355 rldcl. %3,%1,%2,32
7356 rldicl. %3,%1,%H2,32
7357 #
7358 #"
7359 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7360 (set_attr "length" "4,4,8,8")])
7362 (define_insn "*rotldi3_internal14be"
7363 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7364 (compare:CC (zero_extend:DI
7365 (subreg:SI
7366 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7367 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7368 (const_int 0)))
7369 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7370 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7371 "@
7372 rldcl. %3,%1,%2,32
7373 rldicl. %3,%1,%H2,32
7374 #
7375 #"
7376 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7377 (set_attr "length" "4,4,8,8")])
7379 (define_split
7380 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7381 (compare:CC (zero_extend:DI
7382 (subreg:SI
7383 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7384 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7385 (const_int 0)))
7386 (clobber (match_scratch:DI 3 ""))]
7387 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7388 [(set (match_dup 3)
7389 (zero_extend:DI (subreg:SI
7390 (rotate:DI (match_dup 1)
7391 (match_dup 2)) 0)))
7392 (set (match_dup 0)
7393 (compare:CC (match_dup 3)
7394 (const_int 0)))]
7395 "")
7397 (define_split
7398 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7399 (compare:CC (zero_extend:DI
7400 (subreg:SI
7401 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7402 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7403 (const_int 0)))
7404 (clobber (match_scratch:DI 3 ""))]
7405 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7406 [(set (match_dup 3)
7407 (zero_extend:DI (subreg:SI
7408 (rotate:DI (match_dup 1)
7409 (match_dup 2)) 4)))
7410 (set (match_dup 0)
7411 (compare:CC (match_dup 3)
7412 (const_int 0)))]
7413 "")
7415 (define_insn "*rotldi3_internal15le"
7416 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7417 (compare:CC (zero_extend:DI
7418 (subreg:SI
7419 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7420 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7421 (const_int 0)))
7422 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7423 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7424 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7425 "@
7426 rldcl. %0,%1,%2,32
7427 rldicl. %0,%1,%H2,32
7428 #
7429 #"
7430 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7431 (set_attr "length" "4,4,8,8")])
7433 (define_insn "*rotldi3_internal15be"
7434 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7435 (compare:CC (zero_extend:DI
7436 (subreg:SI
7437 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7438 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7439 (const_int 0)))
7440 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7441 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7442 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7443 "@
7444 rldcl. %0,%1,%2,32
7445 rldicl. %0,%1,%H2,32
7446 #
7447 #"
7448 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7449 (set_attr "length" "4,4,8,8")])
7451 (define_split
7452 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7453 (compare:CC (zero_extend:DI
7454 (subreg:SI
7455 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7456 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7457 (const_int 0)))
7458 (set (match_operand:DI 0 "gpc_reg_operand" "")
7459 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7460 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7461 [(set (match_dup 0)
7462 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7463 (set (match_dup 3)
7464 (compare:CC (match_dup 0)
7465 (const_int 0)))]
7466 "")
7468 (define_split
7469 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7470 (compare:CC (zero_extend:DI
7471 (subreg:SI
7472 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7473 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7474 (const_int 0)))
7475 (set (match_operand:DI 0 "gpc_reg_operand" "")
7476 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7477 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7478 [(set (match_dup 0)
7479 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7480 (set (match_dup 3)
7481 (compare:CC (match_dup 0)
7482 (const_int 0)))]
7483 "")
7485 (define_expand "ashldi3"
7486 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7487 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7488 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7489 "TARGET_POWERPC64"
7490 "")
7492 (define_insn "*ashldi3_internal1"
7493 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7494 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7495 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7496 "TARGET_POWERPC64"
7497 "@
7498 sld %0,%1,%2
7499 sldi %0,%1,%H2"
7500 [(set_attr "type" "var_shift_rotate,shift")])
7502 (define_insn "*ashldi3_internal2"
7503 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7504 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7505 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7506 (const_int 0)))
7507 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7508 "TARGET_64BIT"
7509 "@
7510 sld. %3,%1,%2
7511 sldi. %3,%1,%H2
7512 #
7513 #"
7514 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7515 (set_attr "length" "4,4,8,8")])
7517 (define_split
7518 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7519 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7520 (match_operand:SI 2 "reg_or_cint_operand" ""))
7521 (const_int 0)))
7522 (clobber (match_scratch:DI 3 ""))]
7523 "TARGET_POWERPC64 && reload_completed"
7524 [(set (match_dup 3)
7525 (ashift:DI (match_dup 1) (match_dup 2)))
7526 (set (match_dup 0)
7527 (compare:CC (match_dup 3)
7528 (const_int 0)))]
7529 "")
7531 (define_insn "*ashldi3_internal3"
7532 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7533 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7534 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7535 (const_int 0)))
7536 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7537 (ashift:DI (match_dup 1) (match_dup 2)))]
7538 "TARGET_64BIT"
7539 "@
7540 sld. %0,%1,%2
7541 sldi. %0,%1,%H2
7542 #
7543 #"
7544 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7545 (set_attr "length" "4,4,8,8")])
7547 (define_split
7548 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7549 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7550 (match_operand:SI 2 "reg_or_cint_operand" ""))
7551 (const_int 0)))
7552 (set (match_operand:DI 0 "gpc_reg_operand" "")
7553 (ashift:DI (match_dup 1) (match_dup 2)))]
7554 "TARGET_POWERPC64 && reload_completed"
7555 [(set (match_dup 0)
7556 (ashift:DI (match_dup 1) (match_dup 2)))
7557 (set (match_dup 3)
7558 (compare:CC (match_dup 0)
7559 (const_int 0)))]
7560 "")
7562 (define_insn "*ashldi3_internal4"
7563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7564 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7565 (match_operand:SI 2 "const_int_operand" "i"))
7566 (match_operand:DI 3 "const_int_operand" "n")))]
7567 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7568 "rldic %0,%1,%H2,%W3")
7570 (define_insn "ashldi3_internal5"
7571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7572 (compare:CC
7573 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7574 (match_operand:SI 2 "const_int_operand" "i,i"))
7575 (match_operand:DI 3 "const_int_operand" "n,n"))
7576 (const_int 0)))
7577 (clobber (match_scratch:DI 4 "=r,r"))]
7578 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7579 "@
7580 rldic. %4,%1,%H2,%W3
7581 #"
7582 [(set_attr "type" "compare")
7583 (set_attr "length" "4,8")])
7585 (define_split
7586 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7587 (compare:CC
7588 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7589 (match_operand:SI 2 "const_int_operand" ""))
7590 (match_operand:DI 3 "const_int_operand" ""))
7591 (const_int 0)))
7592 (clobber (match_scratch:DI 4 ""))]
7593 "TARGET_POWERPC64 && reload_completed
7594 && includes_rldic_lshift_p (operands[2], operands[3])"
7595 [(set (match_dup 4)
7596 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7597 (match_dup 3)))
7598 (set (match_dup 0)
7599 (compare:CC (match_dup 4)
7600 (const_int 0)))]
7601 "")
7603 (define_insn "*ashldi3_internal6"
7604 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7605 (compare:CC
7606 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7607 (match_operand:SI 2 "const_int_operand" "i,i"))
7608 (match_operand:DI 3 "const_int_operand" "n,n"))
7609 (const_int 0)))
7610 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7611 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7612 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7613 "@
7614 rldic. %0,%1,%H2,%W3
7615 #"
7616 [(set_attr "type" "compare")
7617 (set_attr "length" "4,8")])
7619 (define_split
7620 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7621 (compare:CC
7622 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7623 (match_operand:SI 2 "const_int_operand" ""))
7624 (match_operand:DI 3 "const_int_operand" ""))
7625 (const_int 0)))
7626 (set (match_operand:DI 0 "gpc_reg_operand" "")
7627 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7628 "TARGET_POWERPC64 && reload_completed
7629 && includes_rldic_lshift_p (operands[2], operands[3])"
7630 [(set (match_dup 0)
7631 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7632 (match_dup 3)))
7633 (set (match_dup 4)
7634 (compare:CC (match_dup 0)
7635 (const_int 0)))]
7636 "")
7638 (define_insn "*ashldi3_internal7"
7639 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7640 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7641 (match_operand:SI 2 "const_int_operand" "i"))
7642 (match_operand:DI 3 "mask64_operand" "n")))]
7643 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7644 "rldicr %0,%1,%H2,%S3")
7646 (define_insn "ashldi3_internal8"
7647 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7648 (compare:CC
7649 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7650 (match_operand:SI 2 "const_int_operand" "i,i"))
7651 (match_operand:DI 3 "mask64_operand" "n,n"))
7652 (const_int 0)))
7653 (clobber (match_scratch:DI 4 "=r,r"))]
7654 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7655 "@
7656 rldicr. %4,%1,%H2,%S3
7657 #"
7658 [(set_attr "type" "compare")
7659 (set_attr "length" "4,8")])
7661 (define_split
7662 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7663 (compare:CC
7664 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7665 (match_operand:SI 2 "const_int_operand" ""))
7666 (match_operand:DI 3 "mask64_operand" ""))
7667 (const_int 0)))
7668 (clobber (match_scratch:DI 4 ""))]
7669 "TARGET_POWERPC64 && reload_completed
7670 && includes_rldicr_lshift_p (operands[2], operands[3])"
7671 [(set (match_dup 4)
7672 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7673 (match_dup 3)))
7674 (set (match_dup 0)
7675 (compare:CC (match_dup 4)
7676 (const_int 0)))]
7677 "")
7679 (define_insn "*ashldi3_internal9"
7680 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7681 (compare:CC
7682 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7683 (match_operand:SI 2 "const_int_operand" "i,i"))
7684 (match_operand:DI 3 "mask64_operand" "n,n"))
7685 (const_int 0)))
7686 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7687 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7688 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7689 "@
7690 rldicr. %0,%1,%H2,%S3
7691 #"
7692 [(set_attr "type" "compare")
7693 (set_attr "length" "4,8")])
7695 (define_split
7696 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7697 (compare:CC
7698 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7699 (match_operand:SI 2 "const_int_operand" ""))
7700 (match_operand:DI 3 "mask64_operand" ""))
7701 (const_int 0)))
7702 (set (match_operand:DI 0 "gpc_reg_operand" "")
7703 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7704 "TARGET_POWERPC64 && reload_completed
7705 && includes_rldicr_lshift_p (operands[2], operands[3])"
7706 [(set (match_dup 0)
7707 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7708 (match_dup 3)))
7709 (set (match_dup 4)
7710 (compare:CC (match_dup 0)
7711 (const_int 0)))]
7712 "")
7714 (define_expand "lshrdi3"
7715 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7716 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7717 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7718 "TARGET_POWERPC64"
7719 "")
7721 (define_insn "*lshrdi3_internal1"
7722 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7723 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7724 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7725 "TARGET_POWERPC64"
7726 "@
7727 srd %0,%1,%2
7728 srdi %0,%1,%H2"
7729 [(set_attr "type" "var_shift_rotate,shift")])
7731 (define_insn "*lshrdi3_internal2"
7732 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7733 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7734 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7735 (const_int 0)))
7736 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7737 "TARGET_64BIT "
7738 "@
7739 srd. %3,%1,%2
7740 srdi. %3,%1,%H2
7741 #
7742 #"
7743 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7744 (set_attr "length" "4,4,8,8")])
7746 (define_split
7747 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7748 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7749 (match_operand:SI 2 "reg_or_cint_operand" ""))
7750 (const_int 0)))
7751 (clobber (match_scratch:DI 3 ""))]
7752 "TARGET_POWERPC64 && reload_completed"
7753 [(set (match_dup 3)
7754 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7755 (set (match_dup 0)
7756 (compare:CC (match_dup 3)
7757 (const_int 0)))]
7758 "")
7760 (define_insn "*lshrdi3_internal3"
7761 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7762 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7763 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7764 (const_int 0)))
7765 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7766 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7767 "TARGET_64BIT"
7768 "@
7769 srd. %0,%1,%2
7770 srdi. %0,%1,%H2
7771 #
7772 #"
7773 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7774 (set_attr "length" "4,4,8,8")])
7776 (define_split
7777 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7778 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7779 (match_operand:SI 2 "reg_or_cint_operand" ""))
7780 (const_int 0)))
7781 (set (match_operand:DI 0 "gpc_reg_operand" "")
7782 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7783 "TARGET_POWERPC64 && reload_completed"
7784 [(set (match_dup 0)
7785 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7786 (set (match_dup 3)
7787 (compare:CC (match_dup 0)
7788 (const_int 0)))]
7789 "")
7791 (define_expand "ashrdi3"
7792 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7793 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7794 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7795 ""
7796 "
7797 {
7798 if (TARGET_POWERPC64)
7799 ;
7800 else if (GET_CODE (operands[2]) == CONST_INT)
7801 {
7802 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7803 DONE;
7804 }
7805 else
7806 FAIL;
7807 }")
7809 (define_insn "*ashrdi3_internal1"
7810 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7811 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7812 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7813 "TARGET_POWERPC64"
7814 "@
7815 srad %0,%1,%2
7816 sradi %0,%1,%H2"
7817 [(set_attr "type" "var_shift_rotate,shift")])
7819 (define_insn "*ashrdi3_internal2"
7820 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7821 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7822 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7823 (const_int 0)))
7824 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7825 "TARGET_64BIT"
7826 "@
7827 srad. %3,%1,%2
7828 sradi. %3,%1,%H2
7829 #
7830 #"
7831 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7832 (set_attr "length" "4,4,8,8")])
7834 (define_split
7835 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7836 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7837 (match_operand:SI 2 "reg_or_cint_operand" ""))
7838 (const_int 0)))
7839 (clobber (match_scratch:DI 3 ""))]
7840 "TARGET_POWERPC64 && reload_completed"
7841 [(set (match_dup 3)
7842 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7843 (set (match_dup 0)
7844 (compare:CC (match_dup 3)
7845 (const_int 0)))]
7846 "")
7848 (define_insn "*ashrdi3_internal3"
7849 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7850 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7851 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7852 (const_int 0)))
7853 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7854 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7855 "TARGET_64BIT"
7856 "@
7857 srad. %0,%1,%2
7858 sradi. %0,%1,%H2
7859 #
7860 #"
7861 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7862 (set_attr "length" "4,4,8,8")])
7864 (define_split
7865 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7866 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7867 (match_operand:SI 2 "reg_or_cint_operand" ""))
7868 (const_int 0)))
7869 (set (match_operand:DI 0 "gpc_reg_operand" "")
7870 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7871 "TARGET_POWERPC64 && reload_completed"
7872 [(set (match_dup 0)
7873 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7874 (set (match_dup 3)
7875 (compare:CC (match_dup 0)
7876 (const_int 0)))]
7877 "")
7879 (define_expand "anddi3"
7880 [(parallel
7881 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7882 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7883 (match_operand:DI 2 "reg_or_cint_operand" "")))
7884 (clobber (match_scratch:CC 3 ""))])]
7885 ""
7886 {
7887 if (!TARGET_POWERPC64)
7888 {
7889 rtx cc = gen_rtx_SCRATCH (CCmode);
7890 rs6000_split_logical (operands, AND, false, false, false, cc);
7891 DONE;
7892 }
7893 else if (!and64_2_operand (operands[2], DImode))
7894 operands[2] = force_reg (DImode, operands[2]);
7895 })
7897 (define_insn "anddi3_mc"
7898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7899 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7900 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7901 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7902 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7903 "@
7904 and %0,%1,%2
7905 rldic%B2 %0,%1,0,%S2
7906 rlwinm %0,%1,0,%m2,%M2
7907 andi. %0,%1,%b2
7908 andis. %0,%1,%u2
7909 #"
7910 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7911 (set_attr "length" "4,4,4,4,4,8")])
7913 (define_insn "anddi3_nomc"
7914 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7915 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7916 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7917 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7918 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7919 "@
7920 and %0,%1,%2
7921 rldic%B2 %0,%1,0,%S2
7922 rlwinm %0,%1,0,%m2,%M2
7923 #"
7924 [(set_attr "length" "4,4,4,8")])
7926 (define_split
7927 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7928 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7929 (match_operand:DI 2 "mask64_2_operand" "")))
7930 (clobber (match_scratch:CC 3 ""))]
7931 "TARGET_POWERPC64
7932 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7933 && !mask_operand (operands[2], DImode)
7934 && !mask64_operand (operands[2], DImode)"
7935 [(set (match_dup 0)
7936 (and:DI (rotate:DI (match_dup 1)
7937 (match_dup 4))
7938 (match_dup 5)))
7939 (set (match_dup 0)
7940 (and:DI (rotate:DI (match_dup 0)
7941 (match_dup 6))
7942 (match_dup 7)))]
7943 {
7944 build_mask64_2_operands (operands[2], &operands[4]);
7945 })
7947 (define_insn "*anddi3_internal2_mc"
7948 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7949 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7950 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7951 (const_int 0)))
7952 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7953 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7954 "TARGET_64BIT && rs6000_gen_cell_microcode"
7955 "@
7956 and. %3,%1,%2
7957 rldic%B2. %3,%1,0,%S2
7958 rlwinm. %3,%1,0,%m2,%M2
7959 andi. %3,%1,%b2
7960 andis. %3,%1,%u2
7961 #
7962 #
7963 #
7964 #
7965 #
7966 #
7967 #"
7968 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7969 fast_compare,compare,compare,compare,compare,compare,\
7970 compare,compare")
7971 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7973 (define_split
7974 [(set (match_operand:CC 0 "cc_reg_operand" "")
7975 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7976 (match_operand:DI 2 "mask64_2_operand" ""))
7977 (const_int 0)))
7978 (clobber (match_scratch:DI 3 ""))
7979 (clobber (match_scratch:CC 4 ""))]
7980 "TARGET_64BIT && reload_completed
7981 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7982 && !mask_operand (operands[2], DImode)
7983 && !mask64_operand (operands[2], DImode)"
7984 [(set (match_dup 3)
7985 (and:DI (rotate:DI (match_dup 1)
7986 (match_dup 5))
7987 (match_dup 6)))
7988 (parallel [(set (match_dup 0)
7989 (compare:CC (and:DI (rotate:DI (match_dup 3)
7990 (match_dup 7))
7991 (match_dup 8))
7992 (const_int 0)))
7993 (clobber (match_dup 3))])]
7994 "
7995 {
7996 build_mask64_2_operands (operands[2], &operands[5]);
7997 }")
7999 (define_insn "*anddi3_internal3_mc"
8000 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8001 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8002 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8003 (const_int 0)))
8004 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8005 (and:DI (match_dup 1) (match_dup 2)))
8006 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8007 "TARGET_64BIT && rs6000_gen_cell_microcode"
8008 "@
8009 and. %0,%1,%2
8010 rldic%B2. %0,%1,0,%S2
8011 rlwinm. %0,%1,0,%m2,%M2
8012 andi. %0,%1,%b2
8013 andis. %0,%1,%u2
8014 #
8015 #
8016 #
8017 #
8018 #
8019 #
8020 #"
8021 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8022 fast_compare,compare,compare,compare,compare,compare,\
8023 compare,compare")
8024 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8026 (define_split
8027 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8028 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8029 (match_operand:DI 2 "and64_2_operand" ""))
8030 (const_int 0)))
8031 (set (match_operand:DI 0 "gpc_reg_operand" "")
8032 (and:DI (match_dup 1) (match_dup 2)))
8033 (clobber (match_scratch:CC 4 ""))]
8034 "TARGET_64BIT && reload_completed"
8035 [(parallel [(set (match_dup 0)
8036 (and:DI (match_dup 1) (match_dup 2)))
8037 (clobber (match_dup 4))])
8038 (set (match_dup 3)
8039 (compare:CC (match_dup 0)
8040 (const_int 0)))]
8041 "")
8043 (define_split
8044 [(set (match_operand:CC 3 "cc_reg_operand" "")
8045 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8046 (match_operand:DI 2 "mask64_2_operand" ""))
8047 (const_int 0)))
8048 (set (match_operand:DI 0 "gpc_reg_operand" "")
8049 (and:DI (match_dup 1) (match_dup 2)))
8050 (clobber (match_scratch:CC 4 ""))]
8051 "TARGET_64BIT && reload_completed
8052 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8053 && !mask_operand (operands[2], DImode)
8054 && !mask64_operand (operands[2], DImode)"
8055 [(set (match_dup 0)
8056 (and:DI (rotate:DI (match_dup 1)
8057 (match_dup 5))
8058 (match_dup 6)))
8059 (parallel [(set (match_dup 3)
8060 (compare:CC (and:DI (rotate:DI (match_dup 0)
8061 (match_dup 7))
8062 (match_dup 8))
8063 (const_int 0)))
8064 (set (match_dup 0)
8065 (and:DI (rotate:DI (match_dup 0)
8066 (match_dup 7))
8067 (match_dup 8)))])]
8068 "
8069 {
8070 build_mask64_2_operands (operands[2], &operands[5]);
8071 }")
8073 (define_expand "iordi3"
8074 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8075 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8076 (match_operand:DI 2 "reg_or_cint_operand" "")))]
8077 ""
8078 {
8079 if (!TARGET_POWERPC64)
8080 {
8081 rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
8082 DONE;
8083 }
8084 else if (!reg_or_logical_cint_operand (operands[2], DImode))
8085 operands[2] = force_reg (DImode, operands[2]);
8086 else if (non_logical_cint_operand (operands[2], DImode))
8087 {
8088 HOST_WIDE_INT value;
8089 rtx tmp = ((!can_create_pseudo_p ()
8090 || rtx_equal_p (operands[0], operands[1]))
8091 ? operands[0] : gen_reg_rtx (DImode));
8093 value = INTVAL (operands[2]);
8094 emit_insn (gen_iordi3 (tmp, operands[1],
8095 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8097 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8098 DONE;
8099 }
8100 })
8102 (define_expand "xordi3"
8103 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8104 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8105 (match_operand:DI 2 "reg_or_cint_operand" "")))]
8106 ""
8107 {
8108 if (!TARGET_POWERPC64)
8109 {
8110 rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
8111 DONE;
8112 }
8113 else if (!reg_or_logical_cint_operand (operands[2], DImode))
8114 operands[2] = force_reg (DImode, operands[2]);
8115 if (non_logical_cint_operand (operands[2], DImode))
8116 {
8117 HOST_WIDE_INT value;
8118 rtx tmp = ((!can_create_pseudo_p ()
8119 || rtx_equal_p (operands[0], operands[1]))
8120 ? operands[0] : gen_reg_rtx (DImode));
8122 value = INTVAL (operands[2]);
8123 emit_insn (gen_xordi3 (tmp, operands[1],
8124 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8126 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8127 DONE;
8128 }
8129 })
8131 (define_insn "*booldi3_internal1"
8132 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8133 (match_operator:DI 3 "boolean_or_operator"
8134 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8135 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8136 "TARGET_POWERPC64"
8137 "@
8138 %q3 %0,%1,%2
8139 %q3i %0,%1,%b2
8140 %q3is %0,%1,%u2")
8142 (define_insn "*booldi3_internal2"
8143 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8144 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8145 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8146 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8147 (const_int 0)))
8148 (clobber (match_scratch:DI 3 "=r,r"))]
8149 "TARGET_64BIT"
8150 "@
8151 %q4. %3,%1,%2
8152 #"
8153 [(set_attr "type" "fast_compare,compare")
8154 (set_attr "length" "4,8")])
8156 (define_split
8157 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8158 (compare:CC (match_operator:DI 4 "boolean_operator"
8159 [(match_operand:DI 1 "gpc_reg_operand" "")
8160 (match_operand:DI 2 "gpc_reg_operand" "")])
8161 (const_int 0)))
8162 (clobber (match_scratch:DI 3 ""))]
8163 "TARGET_POWERPC64 && reload_completed"
8164 [(set (match_dup 3) (match_dup 4))
8165 (set (match_dup 0)
8166 (compare:CC (match_dup 3)
8167 (const_int 0)))]
8168 "")
8170 (define_insn "*booldi3_internal3"
8171 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8172 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8173 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8174 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8175 (const_int 0)))
8176 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8177 (match_dup 4))]
8178 "TARGET_64BIT"
8179 "@
8180 %q4. %0,%1,%2
8181 #"
8182 [(set_attr "type" "fast_compare,compare")
8183 (set_attr "length" "4,8")])
8185 (define_split
8186 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8187 (compare:CC (match_operator:DI 4 "boolean_operator"
8188 [(match_operand:DI 1 "gpc_reg_operand" "")
8189 (match_operand:DI 2 "gpc_reg_operand" "")])
8190 (const_int 0)))
8191 (set (match_operand:DI 0 "gpc_reg_operand" "")
8192 (match_dup 4))]
8193 "TARGET_POWERPC64 && reload_completed"
8194 [(set (match_dup 0) (match_dup 4))
8195 (set (match_dup 3)
8196 (compare:CC (match_dup 0)
8197 (const_int 0)))]
8198 "")
8200 ;; Split a logical operation that we can't do in one insn into two insns,
8201 ;; each of which does one 16-bit part. This is used by combine.
8203 (define_split
8204 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8205 (match_operator:DI 3 "boolean_or_operator"
8206 [(match_operand:DI 1 "gpc_reg_operand" "")
8207 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8208 "TARGET_POWERPC64"
8209 [(set (match_dup 0) (match_dup 4))
8210 (set (match_dup 0) (match_dup 5))]
8211 "
8212 {
8213 rtx i3,i4;
8215 i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
8216 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8217 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8218 operands[1], i3);
8219 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8220 operands[0], i4);
8221 }")
8223 (define_insn "*boolcdi3_internal1"
8224 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8225 (match_operator:DI 3 "boolean_operator"
8226 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8227 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8228 "TARGET_POWERPC64"
8229 "%q3 %0,%2,%1")
8231 (define_insn "*boolcdi3_internal2"
8232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8233 (compare:CC (match_operator:DI 4 "boolean_operator"
8234 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8235 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8236 (const_int 0)))
8237 (clobber (match_scratch:DI 3 "=r,r"))]
8238 "TARGET_64BIT"
8239 "@
8240 %q4. %3,%2,%1
8241 #"
8242 [(set_attr "type" "fast_compare,compare")
8243 (set_attr "length" "4,8")])
8245 (define_split
8246 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8247 (compare:CC (match_operator:DI 4 "boolean_operator"
8248 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8249 (match_operand:DI 2 "gpc_reg_operand" "")])
8250 (const_int 0)))
8251 (clobber (match_scratch:DI 3 ""))]
8252 "TARGET_POWERPC64 && reload_completed"
8253 [(set (match_dup 3) (match_dup 4))
8254 (set (match_dup 0)
8255 (compare:CC (match_dup 3)
8256 (const_int 0)))]
8257 "")
8259 (define_insn "*boolcdi3_internal3"
8260 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8261 (compare:CC (match_operator:DI 4 "boolean_operator"
8262 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8263 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8264 (const_int 0)))
8265 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8266 (match_dup 4))]
8267 "TARGET_64BIT"
8268 "@
8269 %q4. %0,%2,%1
8270 #"
8271 [(set_attr "type" "fast_compare,compare")
8272 (set_attr "length" "4,8")])
8274 (define_split
8275 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8276 (compare:CC (match_operator:DI 4 "boolean_operator"
8277 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8278 (match_operand:DI 2 "gpc_reg_operand" "")])
8279 (const_int 0)))
8280 (set (match_operand:DI 0 "gpc_reg_operand" "")
8281 (match_dup 4))]
8282 "TARGET_POWERPC64 && reload_completed"
8283 [(set (match_dup 0) (match_dup 4))
8284 (set (match_dup 3)
8285 (compare:CC (match_dup 0)
8286 (const_int 0)))]
8287 "")
8289 (define_insn "*boolccdi3_internal1"
8290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8291 (match_operator:DI 3 "boolean_operator"
8292 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8293 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8294 "TARGET_POWERPC64"
8295 "%q3 %0,%1,%2")
8297 (define_insn "*boolccdi3_internal2"
8298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8299 (compare:CC (match_operator:DI 4 "boolean_operator"
8300 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8301 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8302 (const_int 0)))
8303 (clobber (match_scratch:DI 3 "=r,r"))]
8304 "TARGET_64BIT"
8305 "@
8306 %q4. %3,%1,%2
8307 #"
8308 [(set_attr "type" "fast_compare,compare")
8309 (set_attr "length" "4,8")])
8311 (define_split
8312 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8313 (compare:CC (match_operator:DI 4 "boolean_operator"
8314 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8315 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8316 (const_int 0)))
8317 (clobber (match_scratch:DI 3 ""))]
8318 "TARGET_POWERPC64 && reload_completed"
8319 [(set (match_dup 3) (match_dup 4))
8320 (set (match_dup 0)
8321 (compare:CC (match_dup 3)
8322 (const_int 0)))]
8323 "")
8325 (define_insn "*boolccdi3_internal3"
8326 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8327 (compare:CC (match_operator:DI 4 "boolean_operator"
8328 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8329 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8330 (const_int 0)))
8331 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8332 (match_dup 4))]
8333 "TARGET_64BIT"
8334 "@
8335 %q4. %0,%1,%2
8336 #"
8337 [(set_attr "type" "fast_compare,compare")
8338 (set_attr "length" "4,8")])
8340 (define_split
8341 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8342 (compare:CC (match_operator:DI 4 "boolean_operator"
8343 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8344 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8345 (const_int 0)))
8346 (set (match_operand:DI 0 "gpc_reg_operand" "")
8347 (match_dup 4))]
8348 "TARGET_POWERPC64 && reload_completed"
8349 [(set (match_dup 0) (match_dup 4))
8350 (set (match_dup 3)
8351 (compare:CC (match_dup 0)
8352 (const_int 0)))]
8353 "")
8355 ;; Eqv operation.
8356 (define_insn "*eqv<mode>3"
8357 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
8358 (not:GPR
8359 (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
8360 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
8361 ""
8362 "eqv %0,%1,%2"
8363 [(set_attr "type" "integer")
8364 (set_attr "length" "4")])
8366 \f
8367 ;; 128-bit logical operations expanders
8369 (define_expand "and<mode>3"
8370 [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8371 (and:BOOL_128
8372 (match_operand:BOOL_128 1 "vlogical_operand" "")
8373 (match_operand:BOOL_128 2 "vlogical_operand" "")))
8374 (clobber (match_scratch:CC 3 ""))])]
8375 ""
8376 "")
8378 (define_expand "ior<mode>3"
8379 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8380 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8381 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8382 ""
8383 "")
8385 (define_expand "xor<mode>3"
8386 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8387 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8388 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8389 ""
8390 "")
8392 (define_expand "one_cmpl<mode>2"
8393 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8394 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8395 ""
8396 "")
8398 (define_expand "nor<mode>3"
8399 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8400 (and:BOOL_128
8401 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8402 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8403 ""
8404 "")
8406 (define_expand "andc<mode>3"
8407 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8408 (and:BOOL_128
8409 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8410 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8411 ""
8412 "")
8414 ;; Power8 vector logical instructions.
8415 (define_expand "eqv<mode>3"
8416 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8417 (not:BOOL_128
8418 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8419 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8420 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8421 "")
8423 ;; Rewrite nand into canonical form
8424 (define_expand "nand<mode>3"
8425 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8426 (ior:BOOL_128
8427 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8428 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8429 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8430 "")
8432 ;; The canonical form is to have the negated element first, so we need to
8433 ;; reverse arguments.
8434 (define_expand "orc<mode>3"
8435 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8436 (ior:BOOL_128
8437 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8438 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8439 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8440 "")
8442 ;; 128-bit logical operations insns and split operations
8443 (define_insn_and_split "*and<mode>3_internal"
8444 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8445 (and:BOOL_128
8446 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8447 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
8448 (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
8449 ""
8450 {
8451 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8452 return "xxland %x0,%x1,%x2";
8454 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8455 return "vand %0,%1,%2";
8457 return "#";
8458 }
8459 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8460 [(const_int 0)]
8461 {
8462 rs6000_split_logical (operands, AND, false, false, false, operands[3]);
8463 DONE;
8464 }
8465 [(set (attr "type")
8466 (if_then_else
8467 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8468 (const_string "vecsimple")
8469 (const_string "integer")))
8470 (set (attr "length")
8471 (if_then_else
8472 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8473 (const_string "4")
8474 (if_then_else
8475 (match_test "TARGET_POWERPC64")
8476 (const_string "8")
8477 (const_string "16"))))])
8479 ;; 128-bit IOR/XOR
8480 (define_insn_and_split "*bool<mode>3_internal"
8481 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8482 (match_operator:BOOL_128 3 "boolean_or_operator"
8483 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8484 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8485 ""
8486 {
8487 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8488 return "xxl%q3 %x0,%x1,%x2";
8490 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8491 return "v%q3 %0,%1,%2";
8493 return "#";
8494 }
8495 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8496 [(const_int 0)]
8497 {
8498 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
8499 NULL_RTX);
8500 DONE;
8501 }
8502 [(set (attr "type")
8503 (if_then_else
8504 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8505 (const_string "vecsimple")
8506 (const_string "integer")))
8507 (set (attr "length")
8508 (if_then_else
8509 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8510 (const_string "4")
8511 (if_then_else
8512 (match_test "TARGET_POWERPC64")
8513 (const_string "8")
8514 (const_string "16"))))])
8516 ;; 128-bit ANDC/ORC
8517 (define_insn_and_split "*boolc<mode>3_internal1"
8518 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8519 (match_operator:BOOL_128 3 "boolean_operator"
8520 [(not:BOOL_128
8521 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
8522 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8523 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8524 {
8525 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8526 return "xxl%q3 %x0,%x1,%x2";
8528 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8529 return "v%q3 %0,%1,%2";
8531 return "#";
8532 }
8533 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8534 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8535 [(const_int 0)]
8536 {
8537 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8538 NULL_RTX);
8539 DONE;
8540 }
8541 [(set (attr "type")
8542 (if_then_else
8543 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8544 (const_string "vecsimple")
8545 (const_string "integer")))
8546 (set (attr "length")
8547 (if_then_else
8548 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8549 (const_string "4")
8550 (if_then_else
8551 (match_test "TARGET_POWERPC64")
8552 (const_string "8")
8553 (const_string "16"))))])
8555 (define_insn_and_split "*boolc<mode>3_internal2"
8556 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8557 (match_operator:TI2 3 "boolean_operator"
8558 [(not:TI2
8559 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8560 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
8561 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8562 "#"
8563 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8564 [(const_int 0)]
8565 {
8566 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8567 NULL_RTX);
8568 DONE;
8569 }
8570 [(set_attr "type" "integer")
8571 (set (attr "length")
8572 (if_then_else
8573 (match_test "TARGET_POWERPC64")
8574 (const_string "8")
8575 (const_string "16")))])
8577 ;; 128-bit NAND/NOR
8578 (define_insn_and_split "*boolcc<mode>3_internal1"
8579 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8580 (match_operator:BOOL_128 3 "boolean_operator"
8581 [(not:BOOL_128
8582 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
8583 (not:BOOL_128
8584 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
8585 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8586 {
8587 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8588 return "xxl%q3 %x0,%x1,%x2";
8590 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8591 return "v%q3 %0,%1,%2";
8593 return "#";
8594 }
8595 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8596 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8597 [(const_int 0)]
8598 {
8599 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8600 NULL_RTX);
8601 DONE;
8602 }
8603 [(set (attr "type")
8604 (if_then_else
8605 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8606 (const_string "vecsimple")
8607 (const_string "integer")))
8608 (set (attr "length")
8609 (if_then_else
8610 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8611 (const_string "4")
8612 (if_then_else
8613 (match_test "TARGET_POWERPC64")
8614 (const_string "8")
8615 (const_string "16"))))])
8617 (define_insn_and_split "*boolcc<mode>3_internal2"
8618 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8619 (match_operator:TI2 3 "boolean_operator"
8620 [(not:TI2
8621 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8622 (not:TI2
8623 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
8624 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8625 "#"
8626 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8627 [(const_int 0)]
8628 {
8629 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8630 NULL_RTX);
8631 DONE;
8632 }
8633 [(set_attr "type" "integer")
8634 (set (attr "length")
8635 (if_then_else
8636 (match_test "TARGET_POWERPC64")
8637 (const_string "8")
8638 (const_string "16")))])
8641 ;; 128-bit EQV
8642 (define_insn_and_split "*eqv<mode>3_internal1"
8643 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8644 (not:BOOL_128
8645 (xor:BOOL_128
8646 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
8647 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
8648 "TARGET_P8_VECTOR"
8649 {
8650 if (vsx_register_operand (operands[0], <MODE>mode))
8651 return "xxleqv %x0,%x1,%x2";
8653 return "#";
8654 }
8655 "TARGET_P8_VECTOR && reload_completed
8656 && int_reg_operand (operands[0], <MODE>mode)"
8657 [(const_int 0)]
8658 {
8659 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8660 DONE;
8661 }
8662 [(set (attr "type")
8663 (if_then_else
8664 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8665 (const_string "vecsimple")
8666 (const_string "integer")))
8667 (set (attr "length")
8668 (if_then_else
8669 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8670 (const_string "4")
8671 (if_then_else
8672 (match_test "TARGET_POWERPC64")
8673 (const_string "8")
8674 (const_string "16"))))])
8676 (define_insn_and_split "*eqv<mode>3_internal2"
8677 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8678 (not:TI2
8679 (xor:TI2
8680 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
8681 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
8682 "!TARGET_P8_VECTOR"
8683 "#"
8684 "reload_completed && !TARGET_P8_VECTOR"
8685 [(const_int 0)]
8686 {
8687 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8688 DONE;
8689 }
8690 [(set_attr "type" "integer")
8691 (set (attr "length")
8692 (if_then_else
8693 (match_test "TARGET_POWERPC64")
8694 (const_string "8")
8695 (const_string "16")))])
8697 ;; 128-bit one's complement
8698 (define_insn_and_split "*one_cmpl<mode>3_internal"
8699 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8700 (not:BOOL_128
8701 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
8702 ""
8703 {
8704 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8705 return "xxlnor %x0,%x1,%x1";
8707 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8708 return "vnor %0,%1,%1";
8710 return "#";
8711 }
8712 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8713 [(const_int 0)]
8714 {
8715 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
8716 DONE;
8717 }
8718 [(set (attr "type")
8719 (if_then_else
8720 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8721 (const_string "vecsimple")
8722 (const_string "integer")))
8723 (set (attr "length")
8724 (if_then_else
8725 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8726 (const_string "4")
8727 (if_then_else
8728 (match_test "TARGET_POWERPC64")
8729 (const_string "8")
8730 (const_string "16"))))])
8732 \f
8733 ;; Now define ways of moving data around.
8735 ;; Set up a register with a value from the GOT table
8737 (define_expand "movsi_got"
8738 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8739 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8740 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8741 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8742 "
8743 {
8744 if (GET_CODE (operands[1]) == CONST)
8745 {
8746 rtx offset = const0_rtx;
8747 HOST_WIDE_INT value;
8749 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8750 value = INTVAL (offset);
8751 if (value != 0)
8752 {
8753 rtx tmp = (!can_create_pseudo_p ()
8754 ? operands[0]
8755 : gen_reg_rtx (Pmode));
8756 emit_insn (gen_movsi_got (tmp, operands[1]));
8757 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8758 DONE;
8759 }
8760 }
8762 operands[2] = rs6000_got_register (operands[1]);
8763 }")
8765 (define_insn "*movsi_got_internal"
8766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8767 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8768 (match_operand:SI 2 "gpc_reg_operand" "b")]
8769 UNSPEC_MOVSI_GOT))]
8770 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8771 "lwz %0,%a1@got(%2)"
8772 [(set_attr "type" "load")])
8774 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8775 ;; didn't get allocated to a hard register.
8776 (define_split
8777 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8778 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8779 (match_operand:SI 2 "memory_operand" "")]
8780 UNSPEC_MOVSI_GOT))]
8781 "DEFAULT_ABI == ABI_V4
8782 && flag_pic == 1
8783 && (reload_in_progress || reload_completed)"
8784 [(set (match_dup 0) (match_dup 2))
8785 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8786 UNSPEC_MOVSI_GOT))]
8787 "")
8789 ;; For SI, we special-case integers that can't be loaded in one insn. We
8790 ;; do the load 16-bits at a time. We could do this by loading from memory,
8791 ;; and this is even supposed to be faster, but it is simpler not to get
8792 ;; integers in the TOC.
8793 (define_insn "movsi_low"
8794 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8795 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8796 (match_operand 2 "" ""))))]
8797 "TARGET_MACHO && ! TARGET_64BIT"
8798 "lwz %0,lo16(%2)(%1)"
8799 [(set_attr "type" "load")
8800 (set_attr "length" "4")])
8802 (define_insn "*movsi_internal1"
8803 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8804 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8805 "!TARGET_SINGLE_FPU &&
8806 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8807 "@
8808 mr %0,%1
8809 la %0,%a1
8810 lwz%U1%X1 %0,%1
8811 stw%U0%X0 %1,%0
8812 li %0,%1
8813 lis %0,%v1
8814 #
8815 mf%1 %0
8816 mt%0 %1
8817 mt%0 %1
8818 nop"
8819 [(set_attr_alternative "type"
8820 [(const_string "*")
8821 (const_string "*")
8822 (if_then_else
8823 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8824 (const_string "load_ux")
8825 (if_then_else
8826 (match_test "update_address_mem (operands[1], VOIDmode)")
8827 (const_string "load_u")
8828 (const_string "load")))
8829 (if_then_else
8830 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8831 (const_string "store_ux")
8832 (if_then_else
8833 (match_test "update_address_mem (operands[0], VOIDmode)")
8834 (const_string "store_u")
8835 (const_string "store")))
8836 (const_string "*")
8837 (const_string "*")
8838 (const_string "*")
8839 (const_string "mfjmpr")
8840 (const_string "mtjmpr")
8841 (const_string "*")
8842 (const_string "*")])
8844 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
8846 (define_insn "*movsi_internal1_single"
8847 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
8848 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
8849 "TARGET_SINGLE_FPU &&
8850 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8851 "@
8852 mr %0,%1
8853 la %0,%a1
8854 lwz%U1%X1 %0,%1
8855 stw%U0%X0 %1,%0
8856 li %0,%1
8857 lis %0,%v1
8858 #
8859 mf%1 %0
8860 mt%0 %1
8861 mt%0 %1
8862 nop
8863 stfs%U0%X0 %1,%0
8864 lfs%U1%X1 %0,%1"
8865 [(set_attr_alternative "type"
8866 [(const_string "*")
8867 (const_string "*")
8868 (if_then_else
8869 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8870 (const_string "load_ux")
8871 (if_then_else
8872 (match_test "update_address_mem (operands[1], VOIDmode)")
8873 (const_string "load_u")
8874 (const_string "load")))
8875 (if_then_else
8876 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8877 (const_string "store_ux")
8878 (if_then_else
8879 (match_test "update_address_mem (operands[0], VOIDmode)")
8880 (const_string "store_u")
8881 (const_string "store")))
8882 (const_string "*")
8883 (const_string "*")
8884 (const_string "*")
8885 (const_string "mfjmpr")
8886 (const_string "mtjmpr")
8887 (const_string "*")
8888 (const_string "*")
8889 (if_then_else
8890 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8891 (const_string "fpstore_ux")
8892 (if_then_else
8893 (match_test "update_address_mem (operands[0], VOIDmode)")
8894 (const_string "fpstore_u")
8895 (const_string "fpstore")))
8896 (if_then_else
8897 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8898 (const_string "fpload_ux")
8899 (if_then_else
8900 (match_test "update_address_mem (operands[1], VOIDmode)")
8901 (const_string "fpload_u")
8902 (const_string "fpload")))])
8903 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8905 ;; Split a load of a large constant into the appropriate two-insn
8906 ;; sequence.
8908 (define_split
8909 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8910 (match_operand:SI 1 "const_int_operand" ""))]
8911 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8912 && (INTVAL (operands[1]) & 0xffff) != 0"
8913 [(set (match_dup 0)
8914 (match_dup 2))
8915 (set (match_dup 0)
8916 (ior:SI (match_dup 0)
8917 (match_dup 3)))]
8918 "
8919 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8921 if (tem == operands[0])
8922 DONE;
8923 else
8924 FAIL;
8925 }")
8927 (define_insn "*mov<mode>_internal2"
8928 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8929 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8930 (const_int 0)))
8931 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8932 ""
8933 "@
8934 cmp<wd>i %2,%0,0
8935 mr. %0,%1
8936 #"
8937 [(set_attr "type" "cmp,fast_compare,cmp")
8938 (set_attr "length" "4,4,8")])
8940 (define_split
8941 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8942 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8943 (const_int 0)))
8944 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8945 "reload_completed"
8946 [(set (match_dup 0) (match_dup 1))
8947 (set (match_dup 2)
8948 (compare:CC (match_dup 0)
8949 (const_int 0)))]
8950 "")
8951 \f
8952 (define_insn "*movhi_internal"
8953 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8954 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8955 "gpc_reg_operand (operands[0], HImode)
8956 || gpc_reg_operand (operands[1], HImode)"
8957 "@
8958 mr %0,%1
8959 lhz%U1%X1 %0,%1
8960 sth%U0%X0 %1,%0
8961 li %0,%w1
8962 mf%1 %0
8963 mt%0 %1
8964 nop"
8965 [(set_attr_alternative "type"
8966 [(const_string "*")
8967 (if_then_else
8968 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8969 (const_string "load_ux")
8970 (if_then_else
8971 (match_test "update_address_mem (operands[1], VOIDmode)")
8972 (const_string "load_u")
8973 (const_string "load")))
8974 (if_then_else
8975 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8976 (const_string "store_ux")
8977 (if_then_else
8978 (match_test "update_address_mem (operands[0], VOIDmode)")
8979 (const_string "store_u")
8980 (const_string "store")))
8981 (const_string "*")
8982 (const_string "mfjmpr")
8983 (const_string "mtjmpr")
8984 (const_string "*")])])
8986 (define_expand "mov<mode>"
8987 [(set (match_operand:INT 0 "general_operand" "")
8988 (match_operand:INT 1 "any_operand" ""))]
8989 ""
8990 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8992 (define_insn "*movqi_internal"
8993 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8994 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8995 "gpc_reg_operand (operands[0], QImode)
8996 || gpc_reg_operand (operands[1], QImode)"
8997 "@
8998 mr %0,%1
8999 lbz%U1%X1 %0,%1
9000 stb%U0%X0 %1,%0
9001 li %0,%1
9002 mf%1 %0
9003 mt%0 %1
9004 nop"
9005 [(set_attr_alternative "type"
9006 [(const_string "*")
9007 (if_then_else
9008 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9009 (const_string "load_ux")
9010 (if_then_else
9011 (match_test "update_address_mem (operands[1], VOIDmode)")
9012 (const_string "load_u")
9013 (const_string "load")))
9014 (if_then_else
9015 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9016 (const_string "store_ux")
9017 (if_then_else
9018 (match_test "update_address_mem (operands[0], VOIDmode)")
9019 (const_string "store_u")
9020 (const_string "store")))
9021 (const_string "*")
9022 (const_string "mfjmpr")
9023 (const_string "mtjmpr")
9024 (const_string "*")])])
9025 \f
9026 ;; Here is how to move condition codes around. When we store CC data in
9027 ;; an integer register or memory, we store just the high-order 4 bits.
9028 ;; This lets us not shift in the most common case of CR0.
9029 (define_expand "movcc"
9030 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9031 (match_operand:CC 1 "nonimmediate_operand" ""))]
9032 ""
9033 "")
9035 (define_insn "*movcc_internal1"
9036 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
9037 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
9038 "register_operand (operands[0], CCmode)
9039 || register_operand (operands[1], CCmode)"
9040 "@
9041 mcrf %0,%1
9042 mtcrf 128,%1
9043 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
9044 crxor %0,%0,%0
9045 mfcr %0%Q1
9046 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
9047 mr %0,%1
9048 li %0,%1
9049 mf%1 %0
9050 mt%0 %1
9051 lwz%U1%X1 %0,%1
9052 stw%U0%X0 %1,%0"
9053 [(set (attr "type")
9054 (cond [(eq_attr "alternative" "0,3")
9055 (const_string "cr_logical")
9056 (eq_attr "alternative" "1,2")
9057 (const_string "mtcr")
9058 (eq_attr "alternative" "6,7")
9059 (const_string "integer")
9060 (eq_attr "alternative" "8")
9061 (const_string "mfjmpr")
9062 (eq_attr "alternative" "9")
9063 (const_string "mtjmpr")
9064 (eq_attr "alternative" "10")
9065 (if_then_else
9066 (match_test "update_indexed_address_mem (operands[1],
9067 VOIDmode)")
9068 (const_string "load_ux")
9069 (if_then_else
9070 (match_test "update_address_mem (operands[1], VOIDmode)")
9071 (const_string "load_u")
9072 (const_string "load")))
9073 (eq_attr "alternative" "11")
9074 (if_then_else
9075 (match_test "update_indexed_address_mem (operands[0],
9076 VOIDmode)")
9077 (const_string "store_ux")
9078 (if_then_else
9079 (match_test "update_address_mem (operands[0], VOIDmode)")
9080 (const_string "store_u")
9081 (const_string "store")))
9082 (match_test "TARGET_MFCRF")
9083 (const_string "mfcrf")
9084 ]
9085 (const_string "mfcr")))
9086 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
9087 \f
9088 ;; For floating-point, we normally deal with the floating-point registers
9089 ;; unless -msoft-float is used. The sole exception is that parameter passing
9090 ;; can produce floating-point values in fixed-point registers. Unless the
9091 ;; value is a simple constant or already in memory, we deal with this by
9092 ;; allocating memory and copying the value explicitly via that memory location.
9094 ;; Move 32-bit binary/decimal floating point
9095 (define_expand "mov<mode>"
9096 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
9097 (match_operand:FMOVE32 1 "any_operand" ""))]
9098 "<fmove_ok>"
9099 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9101 (define_split
9102 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
9103 (match_operand:FMOVE32 1 "const_double_operand" ""))]
9104 "reload_completed
9105 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9106 || (GET_CODE (operands[0]) == SUBREG
9107 && GET_CODE (SUBREG_REG (operands[0])) == REG
9108 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9109 [(set (match_dup 2) (match_dup 3))]
9110 "
9111 {
9112 long l;
9113 REAL_VALUE_TYPE rv;
9115 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9116 <real_value_to_target> (rv, l);
9118 if (! TARGET_POWERPC64)
9119 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
9120 else
9121 operands[2] = gen_lowpart (SImode, operands[0]);
9123 operands[3] = gen_int_mode (l, SImode);
9124 }")
9126 (define_insn "mov<mode>_hardfloat"
9127 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
9128 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
9129 "(gpc_reg_operand (operands[0], <MODE>mode)
9130 || gpc_reg_operand (operands[1], <MODE>mode))
9131 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9132 "@
9133 mr %0,%1
9134 lwz%U1%X1 %0,%1
9135 stw%U0%X0 %1,%0
9136 fmr %0,%1
9137 xxlor %x0,%x1,%x1
9138 xxlxor %x0,%x0,%x0
9139 <f32_li>
9140 <f32_si>
9141 <f32_lv>
9142 <f32_sv>
9143 mtvsrwz %x0,%1
9144 mfvsrwz %0,%x1
9145 mt%0 %1
9146 mf%1 %0
9147 nop
9148 #
9149 #"
9150 [(set_attr_alternative "type"
9151 [(const_string "*")
9152 (if_then_else
9153 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9154 (const_string "load_ux")
9155 (if_then_else
9156 (match_test "update_address_mem (operands[1], VOIDmode)")
9157 (const_string "load_u")
9158 (const_string "load")))
9159 (if_then_else
9160 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9161 (const_string "store_ux")
9162 (if_then_else
9163 (match_test "update_address_mem (operands[0], VOIDmode)")
9164 (const_string "store_u")
9165 (const_string "store")))
9166 (const_string "fp")
9167 (const_string "vecsimple")
9168 (const_string "vecsimple")
9169 (if_then_else
9170 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9171 (const_string "fpload_ux")
9172 (if_then_else
9173 (match_test "update_address_mem (operands[1], VOIDmode)")
9174 (const_string "fpload_u")
9175 (const_string "fpload")))
9176 (if_then_else
9177 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9178 (const_string "fpstore_ux")
9179 (if_then_else
9180 (match_test "update_address_mem (operands[0], VOIDmode)")
9181 (const_string "fpstore_u")
9182 (const_string "fpstore")))
9183 (const_string "fpload")
9184 (const_string "fpstore")
9185 (const_string "mftgpr")
9186 (const_string "mffgpr")
9187 (const_string "mtjmpr")
9188 (const_string "mfjmpr")
9189 (const_string "*")
9190 (const_string "*")
9191 (const_string "*")])
9192 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
9194 (define_insn "*mov<mode>_softfloat"
9195 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
9196 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
9197 "(gpc_reg_operand (operands[0], <MODE>mode)
9198 || gpc_reg_operand (operands[1], <MODE>mode))
9199 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9200 "@
9201 mr %0,%1
9202 mt%0 %1
9203 mf%1 %0
9204 lwz%U1%X1 %0,%1
9205 stw%U0%X0 %1,%0
9206 li %0,%1
9207 lis %0,%v1
9208 #
9209 #
9210 nop"
9211 [(set_attr_alternative "type"
9212 [(const_string "*")
9213 (const_string "mtjmpr")
9214 (const_string "mfjmpr")
9215 (if_then_else
9216 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9217 (const_string "load_ux")
9218 (if_then_else
9219 (match_test "update_address_mem (operands[1], VOIDmode)")
9220 (const_string "load_u")
9221 (const_string "load")))
9222 (if_then_else
9223 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9224 (const_string "store_ux")
9225 (if_then_else
9226 (match_test "update_address_mem (operands[0], VOIDmode)")
9227 (const_string "store_u")
9228 (const_string "store")))
9229 (const_string "*")
9230 (const_string "*")
9231 (const_string "*")
9232 (const_string "*")
9233 (const_string "*")])
9234 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
9236 \f
9237 ;; Move 64-bit binary/decimal floating point
9238 (define_expand "mov<mode>"
9239 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
9240 (match_operand:FMOVE64 1 "any_operand" ""))]
9241 ""
9242 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9244 (define_split
9245 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9246 (match_operand:FMOVE64 1 "const_int_operand" ""))]
9247 "! TARGET_POWERPC64 && reload_completed
9248 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9249 || (GET_CODE (operands[0]) == SUBREG
9250 && GET_CODE (SUBREG_REG (operands[0])) == REG
9251 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9252 [(set (match_dup 2) (match_dup 4))
9253 (set (match_dup 3) (match_dup 1))]
9254 "
9255 {
9256 int endian = (WORDS_BIG_ENDIAN == 0);
9257 HOST_WIDE_INT value = INTVAL (operands[1]);
9259 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
9260 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
9261 operands[4] = GEN_INT (value >> 32);
9262 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9263 }")
9265 (define_split
9266 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9267 (match_operand:FMOVE64 1 "const_double_operand" ""))]
9268 "! TARGET_POWERPC64 && reload_completed
9269 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9270 || (GET_CODE (operands[0]) == SUBREG
9271 && GET_CODE (SUBREG_REG (operands[0])) == REG
9272 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9273 [(set (match_dup 2) (match_dup 4))
9274 (set (match_dup 3) (match_dup 5))]
9275 "
9276 {
9277 int endian = (WORDS_BIG_ENDIAN == 0);
9278 long l[2];
9279 REAL_VALUE_TYPE rv;
9281 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9282 <real_value_to_target> (rv, l);
9284 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
9285 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
9286 operands[4] = gen_int_mode (l[endian], SImode);
9287 operands[5] = gen_int_mode (l[1 - endian], SImode);
9288 }")
9290 (define_split
9291 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9292 (match_operand:FMOVE64 1 "const_double_operand" ""))]
9293 "TARGET_POWERPC64 && reload_completed
9294 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9295 || (GET_CODE (operands[0]) == SUBREG
9296 && GET_CODE (SUBREG_REG (operands[0])) == REG
9297 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9298 [(set (match_dup 2) (match_dup 3))]
9299 "
9300 {
9301 int endian = (WORDS_BIG_ENDIAN == 0);
9302 long l[2];
9303 REAL_VALUE_TYPE rv;
9304 HOST_WIDE_INT val;
9306 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9307 <real_value_to_target> (rv, l);
9309 operands[2] = gen_lowpart (DImode, operands[0]);
9310 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9311 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9312 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9314 operands[3] = gen_int_mode (val, DImode);
9315 }")
9317 ;; Don't have reload use general registers to load a constant. It is
9318 ;; less efficient than loading the constant into an FP register, since
9319 ;; it will probably be used there.
9321 ;; The move constraints are ordered to prefer floating point registers before
9322 ;; general purpose registers to avoid doing a store and a load to get the value
9323 ;; into a floating point register when it is needed for a floating point
9324 ;; operation. Prefer traditional floating point registers over VSX registers,
9325 ;; since the D-form version of the memory instructions does not need a GPR for
9326 ;; reloading.
9328 (define_insn "*mov<mode>_hardfloat32"
9329 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
9330 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
9331 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9332 && (gpc_reg_operand (operands[0], <MODE>mode)
9333 || gpc_reg_operand (operands[1], <MODE>mode))"
9334 "@
9335 stfd%U0%X0 %1,%0
9336 lfd%U1%X1 %0,%1
9337 fmr %0,%1
9338 lxsd%U1x %x0,%y1
9339 stxsd%U0x %x1,%y0
9340 xxlor %x0,%x1,%x1
9341 xxlxor %x0,%x0,%x0
9342 #
9343 #
9344 #
9345 #
9346 #
9347 #"
9348 [(set_attr_alternative "type"
9349 [(if_then_else
9350 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9351 (const_string "fpstore_ux")
9352 (if_then_else
9353 (match_test "update_address_mem (operands[0], VOIDmode)")
9354 (const_string "fpstore_u")
9355 (const_string "fpstore")))
9356 (if_then_else
9357 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9358 (const_string "fpload_ux")
9359 (if_then_else
9360 (match_test "update_address_mem (operands[1], VOIDmode)")
9361 (const_string "fpload_u")
9362 (const_string "fpload")))
9363 (const_string "fp")
9364 (if_then_else
9365 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9366 (const_string "fpload_ux")
9367 (const_string "fpload"))
9368 (if_then_else
9369 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9370 (const_string "fpstore_ux")
9371 (const_string "fpstore"))
9372 (const_string "vecsimple")
9373 (const_string "vecsimple")
9374 (const_string "store")
9375 (const_string "load")
9376 (const_string "two")
9377 (const_string "fp")
9378 (const_string "fp")
9379 (const_string "*")])
9380 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
9382 (define_insn "*mov<mode>_softfloat32"
9383 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
9384 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
9385 "! TARGET_POWERPC64
9386 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9387 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9388 && (gpc_reg_operand (operands[0], <MODE>mode)
9389 || gpc_reg_operand (operands[1], <MODE>mode))"
9390 "#"
9391 [(set_attr "type" "store,load,two,*,*,*")
9392 (set_attr "length" "8,8,8,8,12,16")])
9394 ; ld/std require word-aligned displacements -> 'Y' constraint.
9395 ; List Y->r and r->Y before r->r for reload.
9396 (define_insn "*mov<mode>_hardfloat64"
9397 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
9398 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
9399 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9400 && (gpc_reg_operand (operands[0], <MODE>mode)
9401 || gpc_reg_operand (operands[1], <MODE>mode))"
9402 "@
9403 stfd%U0%X0 %1,%0
9404 lfd%U1%X1 %0,%1
9405 fmr %0,%1
9406 lxsd%U1x %x0,%y1
9407 stxsd%U0x %x1,%y0
9408 xxlor %x0,%x1,%x1
9409 xxlxor %x0,%x0,%x0
9410 std%U0%X0 %1,%0
9411 ld%U1%X1 %0,%1
9412 mr %0,%1
9413 mt%0 %1
9414 mf%1 %0
9415 nop
9416 #
9417 #
9418 #
9419 mftgpr %0,%1
9420 mffgpr %0,%1
9421 mfvsrd %0,%x1
9422 mtvsrd %x0,%1"
9423 [(set_attr_alternative "type"
9424 [(if_then_else
9425 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9426 (const_string "fpstore_ux")
9427 (if_then_else
9428 (match_test "update_address_mem (operands[0], VOIDmode)")
9429 (const_string "fpstore_u")
9430 (const_string "fpstore")))
9431 (if_then_else
9432 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9433 (const_string "fpload_ux")
9434 (if_then_else
9435 (match_test "update_address_mem (operands[1], VOIDmode)")
9436 (const_string "fpload_u")
9437 (const_string "fpload")))
9438 (const_string "fp")
9439 (if_then_else
9440 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9441 (const_string "fpload_ux")
9442 (const_string "fpload"))
9443 (if_then_else
9444 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9445 (const_string "fpstore_ux")
9446 (const_string "fpstore"))
9447 (const_string "vecsimple")
9448 (const_string "vecsimple")
9449 (if_then_else
9450 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9451 (const_string "store_ux")
9452 (if_then_else
9453 (match_test "update_address_mem (operands[0], VOIDmode)")
9454 (const_string "store_u")
9455 (const_string "store")))
9456 (if_then_else
9457 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9458 (const_string "load_ux")
9459 (if_then_else
9460 (match_test "update_address_mem (operands[1], VOIDmode)")
9461 (const_string "load_u")
9462 (const_string "load")))
9463 (const_string "*")
9464 (const_string "mtjmpr")
9465 (const_string "mfjmpr")
9466 (const_string "*")
9467 (const_string "*")
9468 (const_string "*")
9469 (const_string "*")
9470 (const_string "mftgpr")
9471 (const_string "mffgpr")
9472 (const_string "mftgpr")
9473 (const_string "mffgpr")])
9474 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
9476 (define_insn "*mov<mode>_softfloat64"
9477 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
9478 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
9479 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9480 && (gpc_reg_operand (operands[0], <MODE>mode)
9481 || gpc_reg_operand (operands[1], <MODE>mode))"
9482 "@
9483 std%U0%X0 %1,%0
9484 ld%U1%X1 %0,%1
9485 mr %0,%1
9486 mt%0 %1
9487 mf%1 %0
9488 #
9489 #
9490 #
9491 nop"
9492 [(set_attr_alternative "type"
9493 [(if_then_else
9494 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9495 (const_string "store_ux")
9496 (if_then_else
9497 (match_test "update_address_mem (operands[0], VOIDmode)")
9498 (const_string "store_u")
9499 (const_string "store")))
9500 (if_then_else
9501 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9502 (const_string "load_ux")
9503 (if_then_else
9504 (match_test "update_address_mem (operands[1], VOIDmode)")
9505 (const_string "load_u")
9506 (const_string "load")))
9507 (const_string "*")
9508 (const_string "mtjmpr")
9509 (const_string "mfjmpr")
9510 (const_string "*")
9511 (const_string "*")
9512 (const_string "*")
9513 (const_string "*")])
9514 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9515 \f
9516 (define_expand "mov<mode>"
9517 [(set (match_operand:FMOVE128 0 "general_operand" "")
9518 (match_operand:FMOVE128 1 "any_operand" ""))]
9519 ""
9520 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9522 ;; It's important to list Y->r and r->Y before r->r because otherwise
9523 ;; reload, given m->r, will try to pick r->r and reload it, which
9524 ;; doesn't make progress.
9525 (define_insn_and_split "*mov<mode>_internal"
9526 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9527 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
9528 "TARGET_HARD_FLOAT && TARGET_FPRS
9529 && (gpc_reg_operand (operands[0], <MODE>mode)
9530 || gpc_reg_operand (operands[1], <MODE>mode))"
9531 "#"
9532 "&& reload_completed"
9533 [(pc)]
9534 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9535 [(set_attr "length" "8,8,8,20,20,16")])
9537 (define_insn_and_split "*mov<mode>_softfloat"
9538 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9539 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
9540 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
9541 && (gpc_reg_operand (operands[0], <MODE>mode)
9542 || gpc_reg_operand (operands[1], <MODE>mode))"
9543 "#"
9544 "&& reload_completed"
9545 [(pc)]
9546 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9547 [(set_attr "length" "20,20,16")])
9549 (define_expand "extenddftf2"
9550 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9551 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9552 "!TARGET_IEEEQUAD
9553 && TARGET_HARD_FLOAT
9554 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9555 && TARGET_LONG_DOUBLE_128"
9556 {
9557 if (TARGET_E500_DOUBLE)
9558 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9559 else
9560 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9561 DONE;
9562 })
9564 (define_expand "extenddftf2_fprs"
9565 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9566 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9567 (use (match_dup 2))])]
9568 "!TARGET_IEEEQUAD
9569 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9570 && TARGET_LONG_DOUBLE_128"
9571 {
9572 operands[2] = CONST0_RTX (DFmode);
9573 /* Generate GOT reference early for SVR4 PIC. */
9574 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9575 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9576 })
9578 (define_insn_and_split "*extenddftf2_internal"
9579 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9580 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9581 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9582 "!TARGET_IEEEQUAD
9583 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9584 && TARGET_LONG_DOUBLE_128"
9585 "#"
9586 "&& reload_completed"
9587 [(pc)]
9588 {
9589 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9590 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9591 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9592 operands[1]);
9593 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9594 operands[2]);
9595 DONE;
9596 })
9598 (define_expand "extendsftf2"
9599 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9600 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9601 "!TARGET_IEEEQUAD
9602 && TARGET_HARD_FLOAT
9603 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9604 && TARGET_LONG_DOUBLE_128"
9605 {
9606 rtx tmp = gen_reg_rtx (DFmode);
9607 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9608 emit_insn (gen_extenddftf2 (operands[0], tmp));
9609 DONE;
9610 })
9612 (define_expand "trunctfdf2"
9613 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9614 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9615 "!TARGET_IEEEQUAD
9616 && TARGET_HARD_FLOAT
9617 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9618 && TARGET_LONG_DOUBLE_128"
9619 "")
9621 (define_insn_and_split "trunctfdf2_internal1"
9622 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9623 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9624 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9625 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9626 "@
9627 #
9628 fmr %0,%1"
9629 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9630 [(const_int 0)]
9631 {
9632 emit_note (NOTE_INSN_DELETED);
9633 DONE;
9634 }
9635 [(set_attr "type" "fp")])
9637 (define_insn "trunctfdf2_internal2"
9638 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9639 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9640 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9641 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9642 && TARGET_LONG_DOUBLE_128"
9643 "fadd %0,%1,%L1"
9644 [(set_attr "type" "fp")
9645 (set_attr "fp_type" "fp_addsub_d")])
9647 (define_expand "trunctfsf2"
9648 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9649 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9650 "!TARGET_IEEEQUAD
9651 && TARGET_HARD_FLOAT
9652 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9653 && TARGET_LONG_DOUBLE_128"
9654 {
9655 if (TARGET_E500_DOUBLE)
9656 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9657 else
9658 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9659 DONE;
9660 })
9662 (define_insn_and_split "trunctfsf2_fprs"
9663 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9664 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9665 (clobber (match_scratch:DF 2 "=d"))]
9666 "!TARGET_IEEEQUAD
9667 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9668 && TARGET_LONG_DOUBLE_128"
9669 "#"
9670 "&& reload_completed"
9671 [(set (match_dup 2)
9672 (float_truncate:DF (match_dup 1)))
9673 (set (match_dup 0)
9674 (float_truncate:SF (match_dup 2)))]
9675 "")
9677 (define_expand "floatsitf2"
9678 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9679 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9680 "!TARGET_IEEEQUAD
9681 && TARGET_HARD_FLOAT
9682 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9683 && TARGET_LONG_DOUBLE_128"
9684 {
9685 rtx tmp = gen_reg_rtx (DFmode);
9686 expand_float (tmp, operands[1], false);
9687 emit_insn (gen_extenddftf2 (operands[0], tmp));
9688 DONE;
9689 })
9691 ; fadd, but rounding towards zero.
9692 ; This is probably not the optimal code sequence.
9693 (define_insn "fix_trunc_helper"
9694 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9695 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9696 UNSPEC_FIX_TRUNC_TF))
9697 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9698 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9699 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9700 [(set_attr "type" "fp")
9701 (set_attr "length" "20")])
9703 (define_expand "fix_trunctfsi2"
9704 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9705 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9706 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9707 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9708 {
9709 if (TARGET_E500_DOUBLE)
9710 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9711 else
9712 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9713 DONE;
9714 })
9716 (define_expand "fix_trunctfsi2_fprs"
9717 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9718 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9719 (clobber (match_dup 2))
9720 (clobber (match_dup 3))
9721 (clobber (match_dup 4))
9722 (clobber (match_dup 5))])]
9723 "!TARGET_IEEEQUAD
9724 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9725 {
9726 operands[2] = gen_reg_rtx (DFmode);
9727 operands[3] = gen_reg_rtx (DFmode);
9728 operands[4] = gen_reg_rtx (DImode);
9729 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9730 })
9732 (define_insn_and_split "*fix_trunctfsi2_internal"
9733 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9734 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9735 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9736 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9737 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9738 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9739 "!TARGET_IEEEQUAD
9740 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9741 "#"
9742 ""
9743 [(pc)]
9744 {
9745 rtx lowword;
9746 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9748 gcc_assert (MEM_P (operands[5]));
9749 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9751 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9752 emit_move_insn (operands[5], operands[4]);
9753 emit_move_insn (operands[0], lowword);
9754 DONE;
9755 })
9757 (define_expand "negtf2"
9758 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9759 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9760 "!TARGET_IEEEQUAD
9761 && TARGET_HARD_FLOAT
9762 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9763 && TARGET_LONG_DOUBLE_128"
9764 "")
9766 (define_insn "negtf2_internal"
9767 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9768 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9769 "!TARGET_IEEEQUAD
9770 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9771 "*
9772 {
9773 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9774 return \"fneg %L0,%L1\;fneg %0,%1\";
9775 else
9776 return \"fneg %0,%1\;fneg %L0,%L1\";
9777 }"
9778 [(set_attr "type" "fp")
9779 (set_attr "length" "8")])
9781 (define_expand "abstf2"
9782 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9783 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9784 "!TARGET_IEEEQUAD
9785 && TARGET_HARD_FLOAT
9786 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9787 && TARGET_LONG_DOUBLE_128"
9788 "
9789 {
9790 rtx label = gen_label_rtx ();
9791 if (TARGET_E500_DOUBLE)
9792 {
9793 if (flag_finite_math_only && !flag_trapping_math)
9794 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9795 else
9796 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9797 }
9798 else
9799 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9800 emit_label (label);
9801 DONE;
9802 }")
9804 (define_expand "abstf2_internal"
9805 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9806 (match_operand:TF 1 "gpc_reg_operand" ""))
9807 (set (match_dup 3) (match_dup 5))
9808 (set (match_dup 5) (abs:DF (match_dup 5)))
9809 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9810 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9811 (label_ref (match_operand 2 "" ""))
9812 (pc)))
9813 (set (match_dup 6) (neg:DF (match_dup 6)))]
9814 "!TARGET_IEEEQUAD
9815 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9816 && TARGET_LONG_DOUBLE_128"
9817 "
9818 {
9819 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9820 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9821 operands[3] = gen_reg_rtx (DFmode);
9822 operands[4] = gen_reg_rtx (CCFPmode);
9823 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9824 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9825 }")
9826 \f
9827 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9828 ;; must have 3 arguments, and scratch register constraint must be a single
9829 ;; constraint.
9831 ;; Reload patterns to support gpr load/store with misaligned mem.
9832 ;; and multiple gpr load/store at offset >= 0xfffc
9833 (define_expand "reload_<mode>_store"
9834 [(parallel [(match_operand 0 "memory_operand" "=m")
9835 (match_operand 1 "gpc_reg_operand" "r")
9836 (match_operand:GPR 2 "register_operand" "=&b")])]
9837 ""
9838 {
9839 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9840 DONE;
9841 })
9843 (define_expand "reload_<mode>_load"
9844 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9845 (match_operand 1 "memory_operand" "m")
9846 (match_operand:GPR 2 "register_operand" "=b")])]
9847 ""
9848 {
9849 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9850 DONE;
9851 })
9853 \f
9854 ;; Power8 merge instructions to allow direct move to/from floating point
9855 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
9856 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
9857 ;; value, since it is allocated in reload and not all of the flow information
9858 ;; is setup for it. We have two patterns to do the two moves between gprs and
9859 ;; fprs. There isn't a dependancy between the two, but we could potentially
9860 ;; schedule other instructions between the two instructions. TFmode is
9861 ;; currently limited to traditional FPR registers. If/when this is changed, we
9862 ;; will need to revist %L to make sure it works with VSX registers, or add an
9863 ;; %x version of %L.
9865 (define_insn "p8_fmrgow_<mode>"
9866 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
9867 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
9868 UNSPEC_P8V_FMRGOW))]
9869 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9870 "fmrgow %0,%1,%L1"
9871 [(set_attr "type" "vecperm")])
9873 (define_insn "p8_mtvsrwz_1"
9874 [(set (match_operand:TF 0 "register_operand" "=d")
9875 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
9876 UNSPEC_P8V_MTVSRWZ))]
9877 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9878 "mtvsrwz %x0,%1"
9879 [(set_attr "type" "mftgpr")])
9881 (define_insn "p8_mtvsrwz_2"
9882 [(set (match_operand:TF 0 "register_operand" "+d")
9883 (unspec:TF [(match_dup 0)
9884 (match_operand:SI 1 "register_operand" "r")]
9885 UNSPEC_P8V_MTVSRWZ))]
9886 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9887 "mtvsrwz %L0,%1"
9888 [(set_attr "type" "mftgpr")])
9890 (define_insn_and_split "reload_fpr_from_gpr<mode>"
9891 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
9892 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
9893 UNSPEC_P8V_RELOAD_FROM_GPR))
9894 (clobber (match_operand:TF 2 "register_operand" "=d"))]
9895 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9896 "#"
9897 "&& reload_completed"
9898 [(const_int 0)]
9899 {
9900 rtx dest = operands[0];
9901 rtx src = operands[1];
9902 rtx tmp = operands[2];
9903 rtx gpr_hi_reg = gen_highpart (SImode, src);
9904 rtx gpr_lo_reg = gen_lowpart (SImode, src);
9906 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
9907 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
9908 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
9909 DONE;
9910 }
9911 [(set_attr "length" "12")
9912 (set_attr "type" "three")])
9914 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
9915 (define_insn "p8_mtvsrd_1"
9916 [(set (match_operand:TF 0 "register_operand" "=ws")
9917 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
9918 UNSPEC_P8V_MTVSRD))]
9919 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9920 "mtvsrd %0,%1"
9921 [(set_attr "type" "mftgpr")])
9923 (define_insn "p8_mtvsrd_2"
9924 [(set (match_operand:TF 0 "register_operand" "+ws")
9925 (unspec:TF [(match_dup 0)
9926 (match_operand:DI 1 "register_operand" "r")]
9927 UNSPEC_P8V_MTVSRD))]
9928 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9929 "mtvsrd %L0,%1"
9930 [(set_attr "type" "mftgpr")])
9932 (define_insn "p8_xxpermdi_<mode>"
9933 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9934 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
9935 UNSPEC_P8V_XXPERMDI))]
9936 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9937 "xxpermdi %x0,%1,%L1,0"
9938 [(set_attr "type" "vecperm")])
9940 (define_insn_and_split "reload_vsx_from_gpr<mode>"
9941 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9942 (unspec:FMOVE128_GPR
9943 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
9944 UNSPEC_P8V_RELOAD_FROM_GPR))
9945 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
9946 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9947 "#"
9948 "&& reload_completed"
9949 [(const_int 0)]
9950 {
9951 rtx dest = operands[0];
9952 rtx src = operands[1];
9953 rtx tmp = operands[2];
9954 rtx gpr_hi_reg = gen_highpart (DImode, src);
9955 rtx gpr_lo_reg = gen_lowpart (DImode, src);
9957 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
9958 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
9959 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
9960 }
9961 [(set_attr "length" "12")
9962 (set_attr "type" "three")])
9964 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
9965 ;; type is stored internally as double precision in the VSX registers, we have
9966 ;; to convert it from the vector format.
9968 (define_insn_and_split "reload_vsx_from_gprsf"
9969 [(set (match_operand:SF 0 "register_operand" "=wa")
9970 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
9971 UNSPEC_P8V_RELOAD_FROM_GPR))
9972 (clobber (match_operand:DI 2 "register_operand" "=r"))]
9973 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
9974 "#"
9975 "&& reload_completed"
9976 [(const_int 0)]
9977 {
9978 rtx op0 = operands[0];
9979 rtx op1 = operands[1];
9980 rtx op2 = operands[2];
9981 rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);
9982 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
9984 /* Move SF value to upper 32-bits for xscvspdpn. */
9985 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
9986 emit_move_insn (op0_di, op2);
9987 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
9988 DONE;
9989 }
9990 [(set_attr "length" "8")
9991 (set_attr "type" "two")])
9993 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
9994 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
9995 ;; and then doing a move of that.
9996 (define_insn "p8_mfvsrd_3_<mode>"
9997 [(set (match_operand:DF 0 "register_operand" "=r")
9998 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9999 UNSPEC_P8V_RELOAD_FROM_VSX))]
10000 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10001 "mfvsrd %0,%x1"
10002 [(set_attr "type" "mftgpr")])
10004 (define_insn_and_split "reload_gpr_from_vsx<mode>"
10005 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
10006 (unspec:FMOVE128_GPR
10007 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
10008 UNSPEC_P8V_RELOAD_FROM_VSX))
10009 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
10010 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10011 "#"
10012 "&& reload_completed"
10013 [(const_int 0)]
10014 {
10015 rtx dest = operands[0];
10016 rtx src = operands[1];
10017 rtx tmp = operands[2];
10018 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
10019 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
10021 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
10022 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
10023 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
10024 }
10025 [(set_attr "length" "12")
10026 (set_attr "type" "three")])
10028 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
10029 ;; type is stored internally as double precision, we have to convert it to the
10030 ;; vector format.
10032 (define_insn_and_split "reload_gpr_from_vsxsf"
10033 [(set (match_operand:SF 0 "register_operand" "=r")
10034 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
10035 UNSPEC_P8V_RELOAD_FROM_VSX))
10036 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
10037 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10038 "#"
10039 "&& reload_completed"
10040 [(const_int 0)]
10041 {
10042 rtx op0 = operands[0];
10043 rtx op1 = operands[1];
10044 rtx op2 = operands[2];
10045 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
10047 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
10048 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
10049 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
10050 DONE;
10051 }
10052 [(set_attr "length" "12")
10053 (set_attr "type" "three")])
10055 (define_insn "p8_mfvsrd_4_disf"
10056 [(set (match_operand:DI 0 "register_operand" "=r")
10057 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
10058 UNSPEC_P8V_RELOAD_FROM_VSX))]
10059 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10060 "mfvsrd %0,%x1"
10061 [(set_attr "type" "mftgpr")])
10063 \f
10064 ;; Next come the multi-word integer load and store and the load and store
10065 ;; multiple insns.
10067 ;; List r->r after r->Y, otherwise reload will try to reload a
10068 ;; non-offsettable address by using r->r which won't make progress.
10069 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
10070 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
10071 (define_insn "*movdi_internal32"
10072 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
10073 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
10074 "! TARGET_POWERPC64
10075 && (gpc_reg_operand (operands[0], DImode)
10076 || gpc_reg_operand (operands[1], DImode))"
10077 "@
10078 #
10079 #
10080 #
10081 stfd%U0%X0 %1,%0
10082 lfd%U1%X1 %0,%1
10083 fmr %0,%1
10084 #"
10085 [(set_attr_alternative "type"
10086 [(const_string "store")
10087 (const_string "load")
10088 (const_string "*")
10089 (if_then_else
10090 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10091 (const_string "fpstore_ux")
10092 (if_then_else
10093 (match_test "update_address_mem (operands[0], VOIDmode)")
10094 (const_string "fpstore_u")
10095 (const_string "fpstore")))
10096 (if_then_else
10097 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10098 (const_string "fpload_ux")
10099 (if_then_else
10100 (match_test "update_address_mem (operands[1], VOIDmode)")
10101 (const_string "fpload_u")
10102 (const_string "fpload")))
10103 (const_string "fp")
10104 (const_string "*")])])
10106 (define_split
10107 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10108 (match_operand:DI 1 "const_int_operand" ""))]
10109 "! TARGET_POWERPC64 && reload_completed
10110 && gpr_or_gpr_p (operands[0], operands[1])
10111 && !direct_move_p (operands[0], operands[1])"
10112 [(set (match_dup 2) (match_dup 4))
10113 (set (match_dup 3) (match_dup 1))]
10114 "
10115 {
10116 HOST_WIDE_INT value = INTVAL (operands[1]);
10117 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10118 DImode);
10119 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10120 DImode);
10121 operands[4] = GEN_INT (value >> 32);
10122 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10123 }")
10125 (define_split
10126 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10127 (match_operand:DIFD 1 "input_operand" ""))]
10128 "reload_completed && !TARGET_POWERPC64
10129 && gpr_or_gpr_p (operands[0], operands[1])
10130 && !direct_move_p (operands[0], operands[1])"
10131 [(pc)]
10132 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10134 (define_insn "*movdi_internal64"
10135 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
10136 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
10137 "TARGET_POWERPC64
10138 && (gpc_reg_operand (operands[0], DImode)
10139 || gpc_reg_operand (operands[1], DImode))"
10140 "@
10141 std%U0%X0 %1,%0
10142 ld%U1%X1 %0,%1
10143 mr %0,%1
10144 li %0,%1
10145 lis %0,%v1
10146 #
10147 stfd%U0%X0 %1,%0
10148 lfd%U1%X1 %0,%1
10149 fmr %0,%1
10150 mf%1 %0
10151 mt%0 %1
10152 nop
10153 mftgpr %0,%1
10154 mffgpr %0,%1
10155 mfvsrd %0,%x1
10156 mtvsrd %x0,%1"
10157 [(set_attr_alternative "type"
10158 [(if_then_else
10159 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10160 (const_string "store_ux")
10161 (if_then_else
10162 (match_test "update_address_mem (operands[0], VOIDmode)")
10163 (const_string "store_u")
10164 (const_string "store")))
10165 (if_then_else
10166 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10167 (const_string "load_ux")
10168 (if_then_else
10169 (match_test "update_address_mem (operands[1], VOIDmode)")
10170 (const_string "load_u")
10171 (const_string "load")))
10172 (const_string "*")
10173 (const_string "*")
10174 (const_string "*")
10175 (const_string "*")
10176 (if_then_else
10177 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10178 (const_string "fpstore_ux")
10179 (if_then_else
10180 (match_test "update_address_mem (operands[0], VOIDmode)")
10181 (const_string "fpstore_u")
10182 (const_string "fpstore")))
10183 (if_then_else
10184 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10185 (const_string "fpload_ux")
10186 (if_then_else
10187 (match_test "update_address_mem (operands[1], VOIDmode)")
10188 (const_string "fpload_u")
10189 (const_string "fpload")))
10190 (const_string "fp")
10191 (const_string "mfjmpr")
10192 (const_string "mtjmpr")
10193 (const_string "*")
10194 (const_string "mftgpr")
10195 (const_string "mffgpr")
10196 (const_string "mftgpr")
10197 (const_string "mffgpr")])
10198 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
10200 ;; Generate all one-bits and clear left or right.
10201 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10202 (define_split
10203 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10204 (match_operand:DI 1 "mask64_operand" ""))]
10205 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10206 [(set (match_dup 0) (const_int -1))
10207 (set (match_dup 0)
10208 (and:DI (rotate:DI (match_dup 0)
10209 (const_int 0))
10210 (match_dup 1)))]
10211 "")
10213 ;; Split a load of a large constant into the appropriate five-instruction
10214 ;; sequence. Handle anything in a constant number of insns.
10215 ;; When non-easy constants can go in the TOC, this should use
10216 ;; easy_fp_constant predicate.
10217 (define_split
10218 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10219 (match_operand:DI 1 "const_int_operand" ""))]
10220 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10221 [(set (match_dup 0) (match_dup 2))
10222 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10223 "
10224 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10226 if (tem == operands[0])
10227 DONE;
10228 else
10229 FAIL;
10230 }")
10232 (define_split
10233 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10234 (match_operand:DI 1 "const_double_operand" ""))]
10235 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10236 [(set (match_dup 0) (match_dup 2))
10237 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10238 "
10239 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10241 if (tem == operands[0])
10242 DONE;
10243 else
10244 FAIL;
10245 }")
10246 \f
10247 ;; TImode/PTImode is similar, except that we usually want to compute the
10248 ;; address into a register and use lsi/stsi (the exception is during reload).
10250 (define_insn "*mov<mode>_string"
10251 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
10252 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
10253 "! TARGET_POWERPC64
10254 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
10255 && (gpc_reg_operand (operands[0], <MODE>mode)
10256 || gpc_reg_operand (operands[1], <MODE>mode))"
10257 "*
10258 {
10259 switch (which_alternative)
10260 {
10261 default:
10262 gcc_unreachable ();
10263 case 0:
10264 if (TARGET_STRING)
10265 return \"stswi %1,%P0,16\";
10266 case 1:
10267 return \"#\";
10268 case 2:
10269 /* If the address is not used in the output, we can use lsi. Otherwise,
10270 fall through to generating four loads. */
10271 if (TARGET_STRING
10272 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10273 return \"lswi %0,%P1,16\";
10274 /* ... fall through ... */
10275 case 3:
10276 case 4:
10277 case 5:
10278 return \"#\";
10279 }
10280 }"
10281 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
10282 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
10283 (const_string "always")
10284 (const_string "conditional")))])
10286 (define_insn "*mov<mode>_ppc64"
10287 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
10288 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
10289 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
10290 && (gpc_reg_operand (operands[0], <MODE>mode)
10291 || gpc_reg_operand (operands[1], <MODE>mode)))"
10292 {
10293 return rs6000_output_move_128bit (operands);
10294 }
10295 [(set_attr "type" "store,store,load,load,*,*")
10296 (set_attr "length" "8")])
10298 (define_split
10299 [(set (match_operand:TI2 0 "int_reg_operand" "")
10300 (match_operand:TI2 1 "const_double_operand" ""))]
10301 "TARGET_POWERPC64
10302 && (VECTOR_MEM_NONE_P (<MODE>mode)
10303 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
10304 [(set (match_dup 2) (match_dup 4))
10305 (set (match_dup 3) (match_dup 5))]
10306 "
10307 {
10308 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10309 <MODE>mode);
10310 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10311 <MODE>mode);
10312 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10313 {
10314 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10315 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10316 }
10317 else if (GET_CODE (operands[1]) == CONST_INT)
10318 {
10319 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10320 operands[5] = operands[1];
10321 }
10322 else
10323 FAIL;
10324 }")
10326 (define_split
10327 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
10328 (match_operand:TI2 1 "input_operand" ""))]
10329 "reload_completed
10330 && gpr_or_gpr_p (operands[0], operands[1])
10331 && !direct_move_p (operands[0], operands[1])
10332 && !quad_load_store_p (operands[0], operands[1])"
10333 [(pc)]
10334 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10335 \f
10336 (define_expand "load_multiple"
10337 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10338 (match_operand:SI 1 "" ""))
10339 (use (match_operand:SI 2 "" ""))])]
10340 "TARGET_STRING && !TARGET_POWERPC64"
10341 "
10342 {
10343 int regno;
10344 int count;
10345 rtx op1;
10346 int i;
10348 /* Support only loading a constant number of fixed-point registers from
10349 memory and only bother with this if more than two; the machine
10350 doesn't support more than eight. */
10351 if (GET_CODE (operands[2]) != CONST_INT
10352 || INTVAL (operands[2]) <= 2
10353 || INTVAL (operands[2]) > 8
10354 || GET_CODE (operands[1]) != MEM
10355 || GET_CODE (operands[0]) != REG
10356 || REGNO (operands[0]) >= 32)
10357 FAIL;
10359 count = INTVAL (operands[2]);
10360 regno = REGNO (operands[0]);
10362 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10363 op1 = replace_equiv_address (operands[1],
10364 force_reg (SImode, XEXP (operands[1], 0)));
10366 for (i = 0; i < count; i++)
10367 XVECEXP (operands[3], 0, i)
10368 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10369 adjust_address_nv (op1, SImode, i * 4));
10370 }")
10372 (define_insn "*ldmsi8"
10373 [(match_parallel 0 "load_multiple_operation"
10374 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10375 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10376 (set (match_operand:SI 3 "gpc_reg_operand" "")
10377 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10378 (set (match_operand:SI 4 "gpc_reg_operand" "")
10379 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10380 (set (match_operand:SI 5 "gpc_reg_operand" "")
10381 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10382 (set (match_operand:SI 6 "gpc_reg_operand" "")
10383 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10384 (set (match_operand:SI 7 "gpc_reg_operand" "")
10385 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10386 (set (match_operand:SI 8 "gpc_reg_operand" "")
10387 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10388 (set (match_operand:SI 9 "gpc_reg_operand" "")
10389 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10390 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10391 "*
10392 { return rs6000_output_load_multiple (operands); }"
10393 [(set_attr "type" "load_ux")
10394 (set_attr "length" "32")])
10396 (define_insn "*ldmsi7"
10397 [(match_parallel 0 "load_multiple_operation"
10398 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10399 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10400 (set (match_operand:SI 3 "gpc_reg_operand" "")
10401 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10402 (set (match_operand:SI 4 "gpc_reg_operand" "")
10403 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10404 (set (match_operand:SI 5 "gpc_reg_operand" "")
10405 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10406 (set (match_operand:SI 6 "gpc_reg_operand" "")
10407 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10408 (set (match_operand:SI 7 "gpc_reg_operand" "")
10409 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10410 (set (match_operand:SI 8 "gpc_reg_operand" "")
10411 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10412 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10413 "*
10414 { return rs6000_output_load_multiple (operands); }"
10415 [(set_attr "type" "load_ux")
10416 (set_attr "length" "32")])
10418 (define_insn "*ldmsi6"
10419 [(match_parallel 0 "load_multiple_operation"
10420 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10421 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10422 (set (match_operand:SI 3 "gpc_reg_operand" "")
10423 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10424 (set (match_operand:SI 4 "gpc_reg_operand" "")
10425 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10426 (set (match_operand:SI 5 "gpc_reg_operand" "")
10427 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10428 (set (match_operand:SI 6 "gpc_reg_operand" "")
10429 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10430 (set (match_operand:SI 7 "gpc_reg_operand" "")
10431 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10432 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10433 "*
10434 { return rs6000_output_load_multiple (operands); }"
10435 [(set_attr "type" "load_ux")
10436 (set_attr "length" "32")])
10438 (define_insn "*ldmsi5"
10439 [(match_parallel 0 "load_multiple_operation"
10440 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10441 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10442 (set (match_operand:SI 3 "gpc_reg_operand" "")
10443 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10444 (set (match_operand:SI 4 "gpc_reg_operand" "")
10445 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10446 (set (match_operand:SI 5 "gpc_reg_operand" "")
10447 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10448 (set (match_operand:SI 6 "gpc_reg_operand" "")
10449 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10450 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10451 "*
10452 { return rs6000_output_load_multiple (operands); }"
10453 [(set_attr "type" "load_ux")
10454 (set_attr "length" "32")])
10456 (define_insn "*ldmsi4"
10457 [(match_parallel 0 "load_multiple_operation"
10458 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10459 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10460 (set (match_operand:SI 3 "gpc_reg_operand" "")
10461 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10462 (set (match_operand:SI 4 "gpc_reg_operand" "")
10463 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10464 (set (match_operand:SI 5 "gpc_reg_operand" "")
10465 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10466 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10467 "*
10468 { return rs6000_output_load_multiple (operands); }"
10469 [(set_attr "type" "load_ux")
10470 (set_attr "length" "32")])
10472 (define_insn "*ldmsi3"
10473 [(match_parallel 0 "load_multiple_operation"
10474 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10475 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10476 (set (match_operand:SI 3 "gpc_reg_operand" "")
10477 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10478 (set (match_operand:SI 4 "gpc_reg_operand" "")
10479 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10480 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10481 "*
10482 { return rs6000_output_load_multiple (operands); }"
10483 [(set_attr "type" "load_ux")
10484 (set_attr "length" "32")])
10486 (define_expand "store_multiple"
10487 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10488 (match_operand:SI 1 "" ""))
10489 (clobber (scratch:SI))
10490 (use (match_operand:SI 2 "" ""))])]
10491 "TARGET_STRING && !TARGET_POWERPC64"
10492 "
10493 {
10494 int regno;
10495 int count;
10496 rtx to;
10497 rtx op0;
10498 int i;
10500 /* Support only storing a constant number of fixed-point registers to
10501 memory and only bother with this if more than two; the machine
10502 doesn't support more than eight. */
10503 if (GET_CODE (operands[2]) != CONST_INT
10504 || INTVAL (operands[2]) <= 2
10505 || INTVAL (operands[2]) > 8
10506 || GET_CODE (operands[0]) != MEM
10507 || GET_CODE (operands[1]) != REG
10508 || REGNO (operands[1]) >= 32)
10509 FAIL;
10511 count = INTVAL (operands[2]);
10512 regno = REGNO (operands[1]);
10514 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10515 to = force_reg (SImode, XEXP (operands[0], 0));
10516 op0 = replace_equiv_address (operands[0], to);
10518 XVECEXP (operands[3], 0, 0)
10519 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10520 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10521 gen_rtx_SCRATCH (SImode));
10523 for (i = 1; i < count; i++)
10524 XVECEXP (operands[3], 0, i + 1)
10525 = gen_rtx_SET (VOIDmode,
10526 adjust_address_nv (op0, SImode, i * 4),
10527 gen_rtx_REG (SImode, regno + i));
10528 }")
10530 (define_insn "*stmsi8"
10531 [(match_parallel 0 "store_multiple_operation"
10532 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10533 (match_operand:SI 2 "gpc_reg_operand" "r"))
10534 (clobber (match_scratch:SI 3 "=X"))
10535 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10536 (match_operand:SI 4 "gpc_reg_operand" "r"))
10537 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10538 (match_operand:SI 5 "gpc_reg_operand" "r"))
10539 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10540 (match_operand:SI 6 "gpc_reg_operand" "r"))
10541 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10542 (match_operand:SI 7 "gpc_reg_operand" "r"))
10543 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10544 (match_operand:SI 8 "gpc_reg_operand" "r"))
10545 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10546 (match_operand:SI 9 "gpc_reg_operand" "r"))
10547 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10548 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10549 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
10550 "stswi %2,%1,%O0"
10551 [(set_attr "type" "store_ux")
10552 (set_attr "cell_micro" "always")])
10554 (define_insn "*stmsi7"
10555 [(match_parallel 0 "store_multiple_operation"
10556 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10557 (match_operand:SI 2 "gpc_reg_operand" "r"))
10558 (clobber (match_scratch:SI 3 "=X"))
10559 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10560 (match_operand:SI 4 "gpc_reg_operand" "r"))
10561 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10562 (match_operand:SI 5 "gpc_reg_operand" "r"))
10563 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10564 (match_operand:SI 6 "gpc_reg_operand" "r"))
10565 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10566 (match_operand:SI 7 "gpc_reg_operand" "r"))
10567 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10568 (match_operand:SI 8 "gpc_reg_operand" "r"))
10569 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10570 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10571 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10572 "stswi %2,%1,%O0"
10573 [(set_attr "type" "store_ux")
10574 (set_attr "cell_micro" "always")])
10576 (define_insn "*stmsi6"
10577 [(match_parallel 0 "store_multiple_operation"
10578 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10579 (match_operand:SI 2 "gpc_reg_operand" "r"))
10580 (clobber (match_scratch:SI 3 "=X"))
10581 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10582 (match_operand:SI 4 "gpc_reg_operand" "r"))
10583 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10584 (match_operand:SI 5 "gpc_reg_operand" "r"))
10585 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10586 (match_operand:SI 6 "gpc_reg_operand" "r"))
10587 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10588 (match_operand:SI 7 "gpc_reg_operand" "r"))
10589 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10590 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10591 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10592 "stswi %2,%1,%O0"
10593 [(set_attr "type" "store_ux")
10594 (set_attr "cell_micro" "always")])
10596 (define_insn "*stmsi5"
10597 [(match_parallel 0 "store_multiple_operation"
10598 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10599 (match_operand:SI 2 "gpc_reg_operand" "r"))
10600 (clobber (match_scratch:SI 3 "=X"))
10601 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10602 (match_operand:SI 4 "gpc_reg_operand" "r"))
10603 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10604 (match_operand:SI 5 "gpc_reg_operand" "r"))
10605 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10606 (match_operand:SI 6 "gpc_reg_operand" "r"))
10607 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10608 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10609 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10610 "stswi %2,%1,%O0"
10611 [(set_attr "type" "store_ux")
10612 (set_attr "cell_micro" "always")])
10614 (define_insn "*stmsi4"
10615 [(match_parallel 0 "store_multiple_operation"
10616 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10617 (match_operand:SI 2 "gpc_reg_operand" "r"))
10618 (clobber (match_scratch:SI 3 "=X"))
10619 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10620 (match_operand:SI 4 "gpc_reg_operand" "r"))
10621 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10622 (match_operand:SI 5 "gpc_reg_operand" "r"))
10623 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10624 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10625 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10626 "stswi %2,%1,%O0"
10627 [(set_attr "type" "store_ux")
10628 (set_attr "cell_micro" "always")])
10630 (define_insn "*stmsi3"
10631 [(match_parallel 0 "store_multiple_operation"
10632 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10633 (match_operand:SI 2 "gpc_reg_operand" "r"))
10634 (clobber (match_scratch:SI 3 "=X"))
10635 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10636 (match_operand:SI 4 "gpc_reg_operand" "r"))
10637 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10638 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10639 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10640 "stswi %2,%1,%O0"
10641 [(set_attr "type" "store_ux")
10642 (set_attr "cell_micro" "always")])
10643 \f
10644 (define_expand "setmemsi"
10645 [(parallel [(set (match_operand:BLK 0 "" "")
10646 (match_operand 2 "const_int_operand" ""))
10647 (use (match_operand:SI 1 "" ""))
10648 (use (match_operand:SI 3 "" ""))])]
10649 ""
10650 "
10651 {
10652 /* If value to set is not zero, use the library routine. */
10653 if (operands[2] != const0_rtx)
10654 FAIL;
10656 if (expand_block_clear (operands))
10657 DONE;
10658 else
10659 FAIL;
10660 }")
10662 ;; String/block move insn.
10663 ;; Argument 0 is the destination
10664 ;; Argument 1 is the source
10665 ;; Argument 2 is the length
10666 ;; Argument 3 is the alignment
10668 (define_expand "movmemsi"
10669 [(parallel [(set (match_operand:BLK 0 "" "")
10670 (match_operand:BLK 1 "" ""))
10671 (use (match_operand:SI 2 "" ""))
10672 (use (match_operand:SI 3 "" ""))])]
10673 ""
10674 "
10675 {
10676 if (expand_block_move (operands))
10677 DONE;
10678 else
10679 FAIL;
10680 }")
10682 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10683 ;; register allocator doesn't have a clue about allocating 8 word registers.
10684 ;; rD/rS = r5 is preferred, efficient form.
10685 (define_expand "movmemsi_8reg"
10686 [(parallel [(set (match_operand 0 "" "")
10687 (match_operand 1 "" ""))
10688 (use (match_operand 2 "" ""))
10689 (use (match_operand 3 "" ""))
10690 (clobber (reg:SI 5))
10691 (clobber (reg:SI 6))
10692 (clobber (reg:SI 7))
10693 (clobber (reg:SI 8))
10694 (clobber (reg:SI 9))
10695 (clobber (reg:SI 10))
10696 (clobber (reg:SI 11))
10697 (clobber (reg:SI 12))
10698 (clobber (match_scratch:SI 4 ""))])]
10699 "TARGET_STRING"
10700 "")
10702 (define_insn ""
10703 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10704 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10705 (use (match_operand:SI 2 "immediate_operand" "i"))
10706 (use (match_operand:SI 3 "immediate_operand" "i"))
10707 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10708 (clobber (reg:SI 6))
10709 (clobber (reg:SI 7))
10710 (clobber (reg:SI 8))
10711 (clobber (reg:SI 9))
10712 (clobber (reg:SI 10))
10713 (clobber (reg:SI 11))
10714 (clobber (reg:SI 12))
10715 (clobber (match_scratch:SI 5 "=X"))]
10716 "TARGET_STRING
10717 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10718 || INTVAL (operands[2]) == 0)
10719 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10720 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10721 && REGNO (operands[4]) == 5"
10722 "lswi %4,%1,%2\;stswi %4,%0,%2"
10723 [(set_attr "type" "store_ux")
10724 (set_attr "cell_micro" "always")
10725 (set_attr "length" "8")])
10727 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10728 ;; register allocator doesn't have a clue about allocating 6 word registers.
10729 ;; rD/rS = r5 is preferred, efficient form.
10730 (define_expand "movmemsi_6reg"
10731 [(parallel [(set (match_operand 0 "" "")
10732 (match_operand 1 "" ""))
10733 (use (match_operand 2 "" ""))
10734 (use (match_operand 3 "" ""))
10735 (clobber (reg:SI 5))
10736 (clobber (reg:SI 6))
10737 (clobber (reg:SI 7))
10738 (clobber (reg:SI 8))
10739 (clobber (reg:SI 9))
10740 (clobber (reg:SI 10))
10741 (clobber (match_scratch:SI 4 ""))])]
10742 "TARGET_STRING"
10743 "")
10745 (define_insn ""
10746 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10747 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10748 (use (match_operand:SI 2 "immediate_operand" "i"))
10749 (use (match_operand:SI 3 "immediate_operand" "i"))
10750 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10751 (clobber (reg:SI 6))
10752 (clobber (reg:SI 7))
10753 (clobber (reg:SI 8))
10754 (clobber (reg:SI 9))
10755 (clobber (reg:SI 10))
10756 (clobber (match_scratch:SI 5 "=X"))]
10757 "TARGET_STRING
10758 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10759 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10760 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10761 && REGNO (operands[4]) == 5"
10762 "lswi %4,%1,%2\;stswi %4,%0,%2"
10763 [(set_attr "type" "store_ux")
10764 (set_attr "cell_micro" "always")
10765 (set_attr "length" "8")])
10767 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10768 ;; problems with TImode.
10769 ;; rD/rS = r5 is preferred, efficient form.
10770 (define_expand "movmemsi_4reg"
10771 [(parallel [(set (match_operand 0 "" "")
10772 (match_operand 1 "" ""))
10773 (use (match_operand 2 "" ""))
10774 (use (match_operand 3 "" ""))
10775 (clobber (reg:SI 5))
10776 (clobber (reg:SI 6))
10777 (clobber (reg:SI 7))
10778 (clobber (reg:SI 8))
10779 (clobber (match_scratch:SI 4 ""))])]
10780 "TARGET_STRING"
10781 "")
10783 (define_insn ""
10784 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10785 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10786 (use (match_operand:SI 2 "immediate_operand" "i"))
10787 (use (match_operand:SI 3 "immediate_operand" "i"))
10788 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10789 (clobber (reg:SI 6))
10790 (clobber (reg:SI 7))
10791 (clobber (reg:SI 8))
10792 (clobber (match_scratch:SI 5 "=X"))]
10793 "TARGET_STRING
10794 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10795 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10796 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10797 && REGNO (operands[4]) == 5"
10798 "lswi %4,%1,%2\;stswi %4,%0,%2"
10799 [(set_attr "type" "store_ux")
10800 (set_attr "cell_micro" "always")
10801 (set_attr "length" "8")])
10803 ;; Move up to 8 bytes at a time.
10804 (define_expand "movmemsi_2reg"
10805 [(parallel [(set (match_operand 0 "" "")
10806 (match_operand 1 "" ""))
10807 (use (match_operand 2 "" ""))
10808 (use (match_operand 3 "" ""))
10809 (clobber (match_scratch:DI 4 ""))
10810 (clobber (match_scratch:SI 5 ""))])]
10811 "TARGET_STRING && ! TARGET_POWERPC64"
10812 "")
10814 (define_insn ""
10815 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10816 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10817 (use (match_operand:SI 2 "immediate_operand" "i"))
10818 (use (match_operand:SI 3 "immediate_operand" "i"))
10819 (clobber (match_scratch:DI 4 "=&r"))
10820 (clobber (match_scratch:SI 5 "=X"))]
10821 "TARGET_STRING && ! TARGET_POWERPC64
10822 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10823 "lswi %4,%1,%2\;stswi %4,%0,%2"
10824 [(set_attr "type" "store_ux")
10825 (set_attr "cell_micro" "always")
10826 (set_attr "length" "8")])
10828 ;; Move up to 4 bytes at a time.
10829 (define_expand "movmemsi_1reg"
10830 [(parallel [(set (match_operand 0 "" "")
10831 (match_operand 1 "" ""))
10832 (use (match_operand 2 "" ""))
10833 (use (match_operand 3 "" ""))
10834 (clobber (match_scratch:SI 4 ""))
10835 (clobber (match_scratch:SI 5 ""))])]
10836 "TARGET_STRING"
10837 "")
10839 (define_insn ""
10840 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10841 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10842 (use (match_operand:SI 2 "immediate_operand" "i"))
10843 (use (match_operand:SI 3 "immediate_operand" "i"))
10844 (clobber (match_scratch:SI 4 "=&r"))
10845 (clobber (match_scratch:SI 5 "=X"))]
10846 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10847 "lswi %4,%1,%2\;stswi %4,%0,%2"
10848 [(set_attr "type" "store_ux")
10849 (set_attr "cell_micro" "always")
10850 (set_attr "length" "8")])
10851 \f
10852 ;; Define insns that do load or store with update. Some of these we can
10853 ;; get by using pre-decrement or pre-increment, but the hardware can also
10854 ;; do cases where the increment is not the size of the object.
10855 ;;
10856 ;; In all these cases, we use operands 0 and 1 for the register being
10857 ;; incremented because those are the operands that local-alloc will
10858 ;; tie and these are the pair most likely to be tieable (and the ones
10859 ;; that will benefit the most).
10861 (define_insn "*movdi_update1"
10862 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10863 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10864 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10865 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10866 (plus:DI (match_dup 1) (match_dup 2)))]
10867 "TARGET_POWERPC64 && TARGET_UPDATE
10868 && (!avoiding_indexed_address_p (DImode)
10869 || !gpc_reg_operand (operands[2], DImode))"
10870 "@
10871 ldux %3,%0,%2
10872 ldu %3,%2(%0)"
10873 [(set_attr "type" "load_ux,load_u")])
10875 (define_insn "movdi_<mode>_update"
10876 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10877 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10878 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10879 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10880 (plus:P (match_dup 1) (match_dup 2)))]
10881 "TARGET_POWERPC64 && TARGET_UPDATE
10882 && (!avoiding_indexed_address_p (Pmode)
10883 || !gpc_reg_operand (operands[2], Pmode)
10884 || (REG_P (operands[0])
10885 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10886 "@
10887 stdux %3,%0,%2
10888 stdu %3,%2(%0)"
10889 [(set_attr "type" "store_ux,store_u")])
10891 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10892 ;; needed for stack allocation, even if the user passes -mno-update.
10893 (define_insn "movdi_<mode>_update_stack"
10894 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10895 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10896 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10897 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10898 (plus:P (match_dup 1) (match_dup 2)))]
10899 "TARGET_POWERPC64"
10900 "@
10901 stdux %3,%0,%2
10902 stdu %3,%2(%0)"
10903 [(set_attr "type" "store_ux,store_u")])
10905 (define_insn "*movsi_update1"
10906 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10907 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10908 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10909 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10910 (plus:SI (match_dup 1) (match_dup 2)))]
10911 "TARGET_UPDATE
10912 && (!avoiding_indexed_address_p (SImode)
10913 || !gpc_reg_operand (operands[2], SImode))"
10914 "@
10915 lwzux %3,%0,%2
10916 lwzu %3,%2(%0)"
10917 [(set_attr "type" "load_ux,load_u")])
10919 (define_insn "*movsi_update2"
10920 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10921 (sign_extend:DI
10922 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10923 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10924 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10925 (plus:DI (match_dup 1) (match_dup 2)))]
10926 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10927 && !avoiding_indexed_address_p (DImode)"
10928 "lwaux %3,%0,%2"
10929 [(set_attr "type" "load_ext_ux")])
10931 (define_insn "movsi_update"
10932 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10933 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10934 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10935 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10936 (plus:SI (match_dup 1) (match_dup 2)))]
10937 "TARGET_UPDATE
10938 && (!avoiding_indexed_address_p (SImode)
10939 || !gpc_reg_operand (operands[2], SImode)
10940 || (REG_P (operands[0])
10941 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10942 "@
10943 stwux %3,%0,%2
10944 stwu %3,%2(%0)"
10945 [(set_attr "type" "store_ux,store_u")])
10947 ;; This is an unconditional pattern; needed for stack allocation, even
10948 ;; if the user passes -mno-update.
10949 (define_insn "movsi_update_stack"
10950 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10951 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10952 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10953 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10954 (plus:SI (match_dup 1) (match_dup 2)))]
10955 ""
10956 "@
10957 stwux %3,%0,%2
10958 stwu %3,%2(%0)"
10959 [(set_attr "type" "store_ux,store_u")])
10961 (define_insn "*movhi_update1"
10962 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10963 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10964 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10965 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10966 (plus:SI (match_dup 1) (match_dup 2)))]
10967 "TARGET_UPDATE
10968 && (!avoiding_indexed_address_p (SImode)
10969 || !gpc_reg_operand (operands[2], SImode))"
10970 "@
10971 lhzux %3,%0,%2
10972 lhzu %3,%2(%0)"
10973 [(set_attr "type" "load_ux,load_u")])
10975 (define_insn "*movhi_update2"
10976 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10977 (zero_extend:SI
10978 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10979 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10980 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10981 (plus:SI (match_dup 1) (match_dup 2)))]
10982 "TARGET_UPDATE
10983 && (!avoiding_indexed_address_p (SImode)
10984 || !gpc_reg_operand (operands[2], SImode))"
10985 "@
10986 lhzux %3,%0,%2
10987 lhzu %3,%2(%0)"
10988 [(set_attr "type" "load_ux,load_u")])
10990 (define_insn "*movhi_update3"
10991 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10992 (sign_extend:SI
10993 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10994 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10995 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10996 (plus:SI (match_dup 1) (match_dup 2)))]
10997 "TARGET_UPDATE && rs6000_gen_cell_microcode
10998 && (!avoiding_indexed_address_p (SImode)
10999 || !gpc_reg_operand (operands[2], SImode))"
11000 "@
11001 lhaux %3,%0,%2
11002 lhau %3,%2(%0)"
11003 [(set_attr "type" "load_ext_ux,load_ext_u")])
11005 (define_insn "*movhi_update4"
11006 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11007 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11008 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11009 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11010 (plus:SI (match_dup 1) (match_dup 2)))]
11011 "TARGET_UPDATE
11012 && (!avoiding_indexed_address_p (SImode)
11013 || !gpc_reg_operand (operands[2], SImode))"
11014 "@
11015 sthux %3,%0,%2
11016 sthu %3,%2(%0)"
11017 [(set_attr "type" "store_ux,store_u")])
11019 (define_insn "*movqi_update1"
11020 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11021 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11022 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11023 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11024 (plus:SI (match_dup 1) (match_dup 2)))]
11025 "TARGET_UPDATE
11026 && (!avoiding_indexed_address_p (SImode)
11027 || !gpc_reg_operand (operands[2], SImode))"
11028 "@
11029 lbzux %3,%0,%2
11030 lbzu %3,%2(%0)"
11031 [(set_attr "type" "load_ux,load_u")])
11033 (define_insn "*movqi_update2"
11034 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11035 (zero_extend:SI
11036 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11037 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11038 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11039 (plus:SI (match_dup 1) (match_dup 2)))]
11040 "TARGET_UPDATE
11041 && (!avoiding_indexed_address_p (SImode)
11042 || !gpc_reg_operand (operands[2], SImode))"
11043 "@
11044 lbzux %3,%0,%2
11045 lbzu %3,%2(%0)"
11046 [(set_attr "type" "load_ux,load_u")])
11048 (define_insn "*movqi_update3"
11049 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11050 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11051 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11052 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11053 (plus:SI (match_dup 1) (match_dup 2)))]
11054 "TARGET_UPDATE
11055 && (!avoiding_indexed_address_p (SImode)
11056 || !gpc_reg_operand (operands[2], SImode))"
11057 "@
11058 stbux %3,%0,%2
11059 stbu %3,%2(%0)"
11060 [(set_attr "type" "store_ux,store_u")])
11062 (define_insn "*movsf_update1"
11063 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11064 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11065 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11066 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11067 (plus:SI (match_dup 1) (match_dup 2)))]
11068 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11069 && (!avoiding_indexed_address_p (SImode)
11070 || !gpc_reg_operand (operands[2], SImode))"
11071 "@
11072 lfsux %3,%0,%2
11073 lfsu %3,%2(%0)"
11074 [(set_attr "type" "fpload_ux,fpload_u")])
11076 (define_insn "*movsf_update2"
11077 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11078 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11079 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11080 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11081 (plus:SI (match_dup 1) (match_dup 2)))]
11082 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11083 && (!avoiding_indexed_address_p (SImode)
11084 || !gpc_reg_operand (operands[2], SImode))"
11085 "@
11086 stfsux %3,%0,%2
11087 stfsu %3,%2(%0)"
11088 [(set_attr "type" "fpstore_ux,fpstore_u")])
11090 (define_insn "*movsf_update3"
11091 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11092 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11093 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11094 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11095 (plus:SI (match_dup 1) (match_dup 2)))]
11096 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11097 && (!avoiding_indexed_address_p (SImode)
11098 || !gpc_reg_operand (operands[2], SImode))"
11099 "@
11100 lwzux %3,%0,%2
11101 lwzu %3,%2(%0)"
11102 [(set_attr "type" "load_ux,load_u")])
11104 (define_insn "*movsf_update4"
11105 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11106 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11107 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11108 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11109 (plus:SI (match_dup 1) (match_dup 2)))]
11110 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11111 && (!avoiding_indexed_address_p (SImode)
11112 || !gpc_reg_operand (operands[2], SImode))"
11113 "@
11114 stwux %3,%0,%2
11115 stwu %3,%2(%0)"
11116 [(set_attr "type" "store_ux,store_u")])
11118 (define_insn "*movdf_update1"
11119 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11120 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11121 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11122 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11123 (plus:SI (match_dup 1) (match_dup 2)))]
11124 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11125 && (!avoiding_indexed_address_p (SImode)
11126 || !gpc_reg_operand (operands[2], SImode))"
11127 "@
11128 lfdux %3,%0,%2
11129 lfdu %3,%2(%0)"
11130 [(set_attr "type" "fpload_ux,fpload_u")])
11132 (define_insn "*movdf_update2"
11133 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11134 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11135 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11136 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11137 (plus:SI (match_dup 1) (match_dup 2)))]
11138 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11139 && (!avoiding_indexed_address_p (SImode)
11140 || !gpc_reg_operand (operands[2], SImode))"
11141 "@
11142 stfdux %3,%0,%2
11143 stfdu %3,%2(%0)"
11144 [(set_attr "type" "fpstore_ux,fpstore_u")])
11147 ;; After inserting conditional returns we can sometimes have
11148 ;; unnecessary register moves. Unfortunately we cannot have a
11149 ;; modeless peephole here, because some single SImode sets have early
11150 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11151 ;; sequences, using get_attr_length here will smash the operands
11152 ;; array. Neither is there an early_cobbler_p predicate.
11153 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11154 (define_peephole2
11155 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11156 (match_operand:DF 1 "any_operand" ""))
11157 (set (match_operand:DF 2 "gpc_reg_operand" "")
11158 (match_dup 0))]
11159 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11160 && peep2_reg_dead_p (2, operands[0])"
11161 [(set (match_dup 2) (match_dup 1))])
11163 (define_peephole2
11164 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11165 (match_operand:SF 1 "any_operand" ""))
11166 (set (match_operand:SF 2 "gpc_reg_operand" "")
11167 (match_dup 0))]
11168 "peep2_reg_dead_p (2, operands[0])"
11169 [(set (match_dup 2) (match_dup 1))])
11171 \f
11172 ;; TLS support.
11174 ;; Mode attributes for different ABIs.
11175 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11176 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11177 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11178 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11180 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11181 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11182 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11183 (match_operand 4 "" "g")))
11184 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11185 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11186 UNSPEC_TLSGD)
11187 (clobber (reg:SI LR_REGNO))]
11188 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11189 {
11190 if (TARGET_CMODEL != CMODEL_SMALL)
11191 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
11192 "bl %z3\;nop";
11193 else
11194 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
11195 }
11196 "&& TARGET_TLS_MARKERS"
11197 [(set (match_dup 0)
11198 (unspec:TLSmode [(match_dup 1)
11199 (match_dup 2)]
11200 UNSPEC_TLSGD))
11201 (parallel [(set (match_dup 0)
11202 (call (mem:TLSmode (match_dup 3))
11203 (match_dup 4)))
11204 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11205 (clobber (reg:SI LR_REGNO))])]
11206 ""
11207 [(set_attr "type" "two")
11208 (set (attr "length")
11209 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11210 (const_int 16)
11211 (const_int 12)))])
11213 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11214 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11215 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11216 (match_operand 4 "" "g")))
11217 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11218 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11219 UNSPEC_TLSGD)
11220 (clobber (reg:SI LR_REGNO))]
11221 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11222 {
11223 if (flag_pic)
11224 {
11225 if (TARGET_SECURE_PLT && flag_pic == 2)
11226 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11227 else
11228 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11229 }
11230 else
11231 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11232 }
11233 "&& TARGET_TLS_MARKERS"
11234 [(set (match_dup 0)
11235 (unspec:TLSmode [(match_dup 1)
11236 (match_dup 2)]
11237 UNSPEC_TLSGD))
11238 (parallel [(set (match_dup 0)
11239 (call (mem:TLSmode (match_dup 3))
11240 (match_dup 4)))
11241 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11242 (clobber (reg:SI LR_REGNO))])]
11243 ""
11244 [(set_attr "type" "two")
11245 (set_attr "length" "8")])
11247 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11248 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11249 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11250 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11251 UNSPEC_TLSGD))]
11252 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11253 "addi %0,%1,%2@got@tlsgd"
11254 "&& TARGET_CMODEL != CMODEL_SMALL"
11255 [(set (match_dup 3)
11256 (high:TLSmode
11257 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
11258 (set (match_dup 0)
11259 (lo_sum:TLSmode (match_dup 3)
11260 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
11261 "
11262 {
11263 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11264 }"
11265 [(set (attr "length")
11266 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11267 (const_int 8)
11268 (const_int 4)))])
11270 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11271 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11272 (high:TLSmode
11273 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11274 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11275 UNSPEC_TLSGD)))]
11276 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11277 "addis %0,%1,%2@got@tlsgd@ha"
11278 [(set_attr "length" "4")])
11280 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11281 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11282 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11283 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11284 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11285 UNSPEC_TLSGD)))]
11286 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11287 "addi %0,%1,%2@got@tlsgd@l"
11288 [(set_attr "length" "4")])
11290 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11291 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11292 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11293 (match_operand 2 "" "g")))
11294 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11295 UNSPEC_TLSGD)
11296 (clobber (reg:SI LR_REGNO))]
11297 "HAVE_AS_TLS && TARGET_TLS_MARKERS
11298 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11299 "bl %z1(%3@tlsgd)\;nop"
11300 [(set_attr "type" "branch")
11301 (set_attr "length" "8")])
11303 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11304 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11305 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11306 (match_operand 2 "" "g")))
11307 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11308 UNSPEC_TLSGD)
11309 (clobber (reg:SI LR_REGNO))]
11310 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11311 {
11312 if (flag_pic)
11313 {
11314 if (TARGET_SECURE_PLT && flag_pic == 2)
11315 return "bl %z1+32768(%3@tlsgd)@plt";
11316 return "bl %z1(%3@tlsgd)@plt";
11317 }
11318 return "bl %z1(%3@tlsgd)";
11319 }
11320 [(set_attr "type" "branch")
11321 (set_attr "length" "4")])
11323 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11324 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11325 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11326 (match_operand 3 "" "g")))
11327 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11328 UNSPEC_TLSLD)
11329 (clobber (reg:SI LR_REGNO))]
11330 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11331 {
11332 if (TARGET_CMODEL != CMODEL_SMALL)
11333 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
11334 "bl %z2\;nop";
11335 else
11336 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
11337 }
11338 "&& TARGET_TLS_MARKERS"
11339 [(set (match_dup 0)
11340 (unspec:TLSmode [(match_dup 1)]
11341 UNSPEC_TLSLD))
11342 (parallel [(set (match_dup 0)
11343 (call (mem:TLSmode (match_dup 2))
11344 (match_dup 3)))
11345 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11346 (clobber (reg:SI LR_REGNO))])]
11347 ""
11348 [(set_attr "type" "two")
11349 (set (attr "length")
11350 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11351 (const_int 16)
11352 (const_int 12)))])
11354 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11355 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11356 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11357 (match_operand 3 "" "g")))
11358 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11359 UNSPEC_TLSLD)
11360 (clobber (reg:SI LR_REGNO))]
11361 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11362 {
11363 if (flag_pic)
11364 {
11365 if (TARGET_SECURE_PLT && flag_pic == 2)
11366 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11367 else
11368 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11369 }
11370 else
11371 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11372 }
11373 "&& TARGET_TLS_MARKERS"
11374 [(set (match_dup 0)
11375 (unspec:TLSmode [(match_dup 1)]
11376 UNSPEC_TLSLD))
11377 (parallel [(set (match_dup 0)
11378 (call (mem:TLSmode (match_dup 2))
11379 (match_dup 3)))
11380 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11381 (clobber (reg:SI LR_REGNO))])]
11382 ""
11383 [(set_attr "length" "8")])
11385 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11386 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11387 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11388 UNSPEC_TLSLD))]
11389 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11390 "addi %0,%1,%&@got@tlsld"
11391 "&& TARGET_CMODEL != CMODEL_SMALL"
11392 [(set (match_dup 2)
11393 (high:TLSmode
11394 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
11395 (set (match_dup 0)
11396 (lo_sum:TLSmode (match_dup 2)
11397 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
11398 "
11399 {
11400 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11401 }"
11402 [(set (attr "length")
11403 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11404 (const_int 8)
11405 (const_int 4)))])
11407 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11408 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11409 (high:TLSmode
11410 (unspec:TLSmode [(const_int 0)
11411 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11412 UNSPEC_TLSLD)))]
11413 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11414 "addis %0,%1,%&@got@tlsld@ha"
11415 [(set_attr "length" "4")])
11417 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11418 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11419 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11420 (unspec:TLSmode [(const_int 0)
11421 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
11422 UNSPEC_TLSLD)))]
11423 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11424 "addi %0,%1,%&@got@tlsld@l"
11425 [(set_attr "length" "4")])
11427 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11428 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11429 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11430 (match_operand 2 "" "g")))
11431 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11432 (clobber (reg:SI LR_REGNO))]
11433 "HAVE_AS_TLS && TARGET_TLS_MARKERS
11434 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11435 "bl %z1(%&@tlsld)\;nop"
11436 [(set_attr "type" "branch")
11437 (set_attr "length" "8")])
11439 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11440 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11441 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11442 (match_operand 2 "" "g")))
11443 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11444 (clobber (reg:SI LR_REGNO))]
11445 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11446 {
11447 if (flag_pic)
11448 {
11449 if (TARGET_SECURE_PLT && flag_pic == 2)
11450 return "bl %z1+32768(%&@tlsld)@plt";
11451 return "bl %z1(%&@tlsld)@plt";
11452 }
11453 return "bl %z1(%&@tlsld)";
11454 }
11455 [(set_attr "type" "branch")
11456 (set_attr "length" "4")])
11458 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11459 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11460 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11461 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11462 UNSPEC_TLSDTPREL))]
11463 "HAVE_AS_TLS"
11464 "addi %0,%1,%2@dtprel")
11466 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11467 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11468 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11469 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11470 UNSPEC_TLSDTPRELHA))]
11471 "HAVE_AS_TLS"
11472 "addis %0,%1,%2@dtprel@ha")
11474 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11475 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11476 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11477 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11478 UNSPEC_TLSDTPRELLO))]
11479 "HAVE_AS_TLS"
11480 "addi %0,%1,%2@dtprel@l")
11482 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11483 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11484 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11485 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11486 UNSPEC_TLSGOTDTPREL))]
11487 "HAVE_AS_TLS"
11488 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11489 "&& TARGET_CMODEL != CMODEL_SMALL"
11490 [(set (match_dup 3)
11491 (high:TLSmode
11492 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
11493 (set (match_dup 0)
11494 (lo_sum:TLSmode (match_dup 3)
11495 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11496 "
11497 {
11498 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11499 }"
11500 [(set (attr "length")
11501 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11502 (const_int 8)
11503 (const_int 4)))])
11505 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11506 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11507 (high:TLSmode
11508 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11509 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11510 UNSPEC_TLSGOTDTPREL)))]
11511 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11512 "addis %0,%1,%2@got@dtprel@ha"
11513 [(set_attr "length" "4")])
11515 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11516 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11517 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11518 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11519 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11520 UNSPEC_TLSGOTDTPREL)))]
11521 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11522 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11523 [(set_attr "length" "4")])
11525 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11526 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11527 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11528 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11529 UNSPEC_TLSTPREL))]
11530 "HAVE_AS_TLS"
11531 "addi %0,%1,%2@tprel")
11533 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11534 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11535 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11536 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11537 UNSPEC_TLSTPRELHA))]
11538 "HAVE_AS_TLS"
11539 "addis %0,%1,%2@tprel@ha")
11541 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11542 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11543 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11544 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11545 UNSPEC_TLSTPRELLO))]
11546 "HAVE_AS_TLS"
11547 "addi %0,%1,%2@tprel@l")
11549 ;; "b" output constraint here and on tls_tls input to support linker tls
11550 ;; optimization. The linker may edit the instructions emitted by a
11551 ;; tls_got_tprel/tls_tls pair to addis,addi.
11552 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11553 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11554 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11555 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11556 UNSPEC_TLSGOTTPREL))]
11557 "HAVE_AS_TLS"
11558 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11559 "&& TARGET_CMODEL != CMODEL_SMALL"
11560 [(set (match_dup 3)
11561 (high:TLSmode
11562 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
11563 (set (match_dup 0)
11564 (lo_sum:TLSmode (match_dup 3)
11565 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11566 "
11567 {
11568 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11569 }"
11570 [(set (attr "length")
11571 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11572 (const_int 8)
11573 (const_int 4)))])
11575 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11576 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11577 (high:TLSmode
11578 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11579 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11580 UNSPEC_TLSGOTTPREL)))]
11581 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11582 "addis %0,%1,%2@got@tprel@ha"
11583 [(set_attr "length" "4")])
11585 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11586 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11587 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11588 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11589 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11590 UNSPEC_TLSGOTTPREL)))]
11591 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11592 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11593 [(set_attr "length" "4")])
11595 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11596 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11597 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11598 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11599 UNSPEC_TLSTLS))]
11600 "TARGET_ELF && HAVE_AS_TLS"
11601 "add %0,%1,%2@tls")
11603 (define_expand "tls_get_tpointer"
11604 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11605 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
11606 "TARGET_XCOFF && HAVE_AS_TLS"
11607 "
11608 {
11609 emit_insn (gen_tls_get_tpointer_internal ());
11610 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
11611 DONE;
11612 }")
11614 (define_insn "tls_get_tpointer_internal"
11615 [(set (reg:SI 3)
11616 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
11617 (clobber (reg:SI LR_REGNO))]
11618 "TARGET_XCOFF && HAVE_AS_TLS"
11619 "bla __get_tpointer")
11621 (define_expand "tls_get_addr<mode>"
11622 [(set (match_operand:P 0 "gpc_reg_operand" "")
11623 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
11624 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
11625 "TARGET_XCOFF && HAVE_AS_TLS"
11626 "
11627 {
11628 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
11629 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
11630 emit_insn (gen_tls_get_addr_internal<mode> ());
11631 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
11632 DONE;
11633 }")
11635 (define_insn "tls_get_addr_internal<mode>"
11636 [(set (reg:P 3)
11637 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
11638 (clobber (reg:P 0))
11639 (clobber (reg:P 4))
11640 (clobber (reg:P 5))
11641 (clobber (reg:P 11))
11642 (clobber (reg:CC CR0_REGNO))
11643 (clobber (reg:P LR_REGNO))]
11644 "TARGET_XCOFF && HAVE_AS_TLS"
11645 "bla __tls_get_addr")
11646 \f
11647 ;; Next come insns related to the calling sequence.
11648 ;;
11649 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11650 ;; We move the back-chain and decrement the stack pointer.
11652 (define_expand "allocate_stack"
11653 [(set (match_operand 0 "gpc_reg_operand" "")
11654 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11655 (set (reg 1)
11656 (minus (reg 1) (match_dup 1)))]
11657 ""
11658 "
11659 { rtx chain = gen_reg_rtx (Pmode);
11660 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11661 rtx neg_op0;
11662 rtx insn, par, set, mem;
11664 emit_move_insn (chain, stack_bot);
11666 /* Check stack bounds if necessary. */
11667 if (crtl->limit_stack)
11668 {
11669 rtx available;
11670 available = expand_binop (Pmode, sub_optab,
11671 stack_pointer_rtx, stack_limit_rtx,
11672 NULL_RTX, 1, OPTAB_WIDEN);
11673 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11674 }
11676 if (GET_CODE (operands[1]) != CONST_INT
11677 || INTVAL (operands[1]) < -32767
11678 || INTVAL (operands[1]) > 32768)
11679 {
11680 neg_op0 = gen_reg_rtx (Pmode);
11681 if (TARGET_32BIT)
11682 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11683 else
11684 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11685 }
11686 else
11687 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11689 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11690 : gen_movdi_di_update_stack))
11691 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11692 chain));
11693 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11694 it now and set the alias set/attributes. The above gen_*_update
11695 calls will generate a PARALLEL with the MEM set being the first
11696 operation. */
11697 par = PATTERN (insn);
11698 gcc_assert (GET_CODE (par) == PARALLEL);
11699 set = XVECEXP (par, 0, 0);
11700 gcc_assert (GET_CODE (set) == SET);
11701 mem = SET_DEST (set);
11702 gcc_assert (MEM_P (mem));
11703 MEM_NOTRAP_P (mem) = 1;
11704 set_mem_alias_set (mem, get_frame_alias_set ());
11706 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11707 DONE;
11708 }")
11710 ;; These patterns say how to save and restore the stack pointer. We need not
11711 ;; save the stack pointer at function level since we are careful to
11712 ;; preserve the backchain. At block level, we have to restore the backchain
11713 ;; when we restore the stack pointer.
11714 ;;
11715 ;; For nonlocal gotos, we must save both the stack pointer and its
11716 ;; backchain and restore both. Note that in the nonlocal case, the
11717 ;; save area is a memory location.
11719 (define_expand "save_stack_function"
11720 [(match_operand 0 "any_operand" "")
11721 (match_operand 1 "any_operand" "")]
11722 ""
11723 "DONE;")
11725 (define_expand "restore_stack_function"
11726 [(match_operand 0 "any_operand" "")
11727 (match_operand 1 "any_operand" "")]
11728 ""
11729 "DONE;")
11731 ;; Adjust stack pointer (op0) to a new value (op1).
11732 ;; First copy old stack backchain to new location, and ensure that the
11733 ;; scheduler won't reorder the sp assignment before the backchain write.
11734 (define_expand "restore_stack_block"
11735 [(set (match_dup 2) (match_dup 3))
11736 (set (match_dup 4) (match_dup 2))
11737 (match_dup 5)
11738 (set (match_operand 0 "register_operand" "")
11739 (match_operand 1 "register_operand" ""))]
11740 ""
11741 "
11742 {
11743 rtvec p;
11745 operands[1] = force_reg (Pmode, operands[1]);
11746 operands[2] = gen_reg_rtx (Pmode);
11747 operands[3] = gen_frame_mem (Pmode, operands[0]);
11748 operands[4] = gen_frame_mem (Pmode, operands[1]);
11749 p = rtvec_alloc (1);
11750 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11751 gen_frame_mem (BLKmode, operands[0]),
11752 const0_rtx);
11753 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11754 }")
11756 (define_expand "save_stack_nonlocal"
11757 [(set (match_dup 3) (match_dup 4))
11758 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11759 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11760 ""
11761 "
11762 {
11763 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11765 /* Copy the backchain to the first word, sp to the second. */
11766 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11767 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11768 operands[3] = gen_reg_rtx (Pmode);
11769 operands[4] = gen_frame_mem (Pmode, operands[1]);
11770 }")
11772 (define_expand "restore_stack_nonlocal"
11773 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11774 (set (match_dup 3) (match_dup 4))
11775 (set (match_dup 5) (match_dup 2))
11776 (match_dup 6)
11777 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11778 ""
11779 "
11780 {
11781 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11782 rtvec p;
11784 /* Restore the backchain from the first word, sp from the second. */
11785 operands[2] = gen_reg_rtx (Pmode);
11786 operands[3] = gen_reg_rtx (Pmode);
11787 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11788 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11789 operands[5] = gen_frame_mem (Pmode, operands[3]);
11790 p = rtvec_alloc (1);
11791 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11792 gen_frame_mem (BLKmode, operands[0]),
11793 const0_rtx);
11794 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11795 }")
11796 \f
11797 ;; TOC register handling.
11799 ;; Code to initialize the TOC register...
11801 (define_insn "load_toc_aix_si"
11802 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11803 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11804 (use (reg:SI 2))])]
11805 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
11806 "*
11807 {
11808 char buf[30];
11809 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11810 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11811 operands[2] = gen_rtx_REG (Pmode, 2);
11812 return \"lwz %0,%1(%2)\";
11813 }"
11814 [(set_attr "type" "load")])
11816 (define_insn "load_toc_aix_di"
11817 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11818 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11819 (use (reg:DI 2))])]
11820 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
11821 "*
11822 {
11823 char buf[30];
11824 #ifdef TARGET_RELOCATABLE
11825 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11826 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11827 #else
11828 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11829 #endif
11830 if (TARGET_ELF)
11831 strcat (buf, \"@toc\");
11832 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11833 operands[2] = gen_rtx_REG (Pmode, 2);
11834 return \"ld %0,%1(%2)\";
11835 }"
11836 [(set_attr "type" "load")])
11838 (define_insn "load_toc_v4_pic_si"
11839 [(set (reg:SI LR_REGNO)
11840 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11841 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11842 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11843 [(set_attr "type" "branch")
11844 (set_attr "length" "4")])
11846 (define_expand "load_toc_v4_PIC_1"
11847 [(parallel [(set (reg:SI LR_REGNO)
11848 (match_operand:SI 0 "immediate_operand" "s"))
11849 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
11850 "TARGET_ELF && DEFAULT_ABI == ABI_V4
11851 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11852 "")
11854 (define_insn "load_toc_v4_PIC_1_normal"
11855 [(set (reg:SI LR_REGNO)
11856 (match_operand:SI 0 "immediate_operand" "s"))
11857 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11858 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11859 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11860 "bcl 20,31,%0\\n%0:"
11861 [(set_attr "type" "branch")
11862 (set_attr "length" "4")])
11864 (define_insn "load_toc_v4_PIC_1_476"
11865 [(set (reg:SI LR_REGNO)
11866 (match_operand:SI 0 "immediate_operand" "s"))
11867 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11868 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11869 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11870 "*
11871 {
11872 char name[32];
11873 static char templ[32];
11875 get_ppc476_thunk_name (name);
11876 sprintf (templ, \"bl %s\\n%%0:\", name);
11877 return templ;
11878 }"
11879 [(set_attr "type" "branch")
11880 (set_attr "length" "4")])
11882 (define_expand "load_toc_v4_PIC_1b"
11883 [(parallel [(set (reg:SI LR_REGNO)
11884 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11885 (label_ref (match_operand 1 "" ""))]
11886 UNSPEC_TOCPTR))
11887 (match_dup 1)])]
11888 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11889 "")
11891 (define_insn "load_toc_v4_PIC_1b_normal"
11892 [(set (reg:SI LR_REGNO)
11893 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11894 (label_ref (match_operand 1 "" ""))]
11895 UNSPEC_TOCPTR))
11896 (match_dup 1)]
11897 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11898 "bcl 20,31,$+8\;.long %0-$"
11899 [(set_attr "type" "branch")
11900 (set_attr "length" "8")])
11902 (define_insn "load_toc_v4_PIC_1b_476"
11903 [(set (reg:SI LR_REGNO)
11904 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11905 (label_ref (match_operand 1 "" ""))]
11906 UNSPEC_TOCPTR))
11907 (match_dup 1)]
11908 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11909 "*
11910 {
11911 char name[32];
11912 static char templ[32];
11914 get_ppc476_thunk_name (name);
11915 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
11916 return templ;
11917 }"
11918 [(set_attr "type" "branch")
11919 (set_attr "length" "16")])
11921 (define_insn "load_toc_v4_PIC_2"
11922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11923 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11924 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11925 (match_operand:SI 3 "immediate_operand" "s")))))]
11926 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11927 "lwz %0,%2-%3(%1)"
11928 [(set_attr "type" "load")])
11930 (define_insn "load_toc_v4_PIC_3b"
11931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11932 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11933 (high:SI
11934 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11935 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11936 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11937 "addis %0,%1,%2-%3@ha")
11939 (define_insn "load_toc_v4_PIC_3c"
11940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11941 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11942 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11943 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11944 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11945 "addi %0,%1,%2-%3@l")
11947 ;; If the TOC is shared over a translation unit, as happens with all
11948 ;; the kinds of PIC that we support, we need to restore the TOC
11949 ;; pointer only when jumping over units of translation.
11950 ;; On Darwin, we need to reload the picbase.
11952 (define_expand "builtin_setjmp_receiver"
11953 [(use (label_ref (match_operand 0 "" "")))]
11954 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11955 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11956 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11957 "
11958 {
11959 #if TARGET_MACHO
11960 if (DEFAULT_ABI == ABI_DARWIN)
11961 {
11962 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11963 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11964 rtx tmplabrtx;
11965 char tmplab[20];
11967 crtl->uses_pic_offset_table = 1;
11968 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11969 CODE_LABEL_NUMBER (operands[0]));
11970 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11972 emit_insn (gen_load_macho_picbase (tmplabrtx));
11973 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11974 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11975 }
11976 else
11977 #endif
11978 rs6000_emit_load_toc_table (FALSE);
11979 DONE;
11980 }")
11982 ;; Largetoc support
11983 (define_insn "*largetoc_high"
11984 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11985 (high:DI
11986 (unspec [(match_operand:DI 1 "" "")
11987 (match_operand:DI 2 "gpc_reg_operand" "b")]
11988 UNSPEC_TOCREL)))]
11989 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11990 "addis %0,%2,%1@toc@ha")
11992 (define_insn "*largetoc_high_aix<mode>"
11993 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11994 (high:P
11995 (unspec [(match_operand:P 1 "" "")
11996 (match_operand:P 2 "gpc_reg_operand" "b")]
11997 UNSPEC_TOCREL)))]
11998 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11999 "addis %0,%1@u(%2)")
12001 (define_insn "*largetoc_high_plus"
12002 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
12003 (high:DI
12004 (plus:DI
12005 (unspec [(match_operand:DI 1 "" "")
12006 (match_operand:DI 2 "gpc_reg_operand" "b")]
12007 UNSPEC_TOCREL)
12008 (match_operand:DI 3 "add_cint_operand" "n"))))]
12009 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12010 "addis %0,%2,%1+%3@toc@ha")
12012 (define_insn "*largetoc_high_plus_aix<mode>"
12013 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12014 (high:P
12015 (plus:P
12016 (unspec [(match_operand:P 1 "" "")
12017 (match_operand:P 2 "gpc_reg_operand" "b")]
12018 UNSPEC_TOCREL)
12019 (match_operand:P 3 "add_cint_operand" "n"))))]
12020 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
12021 "addis %0,%1+%3@u(%2)")
12023 (define_insn "*largetoc_low"
12024 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12025 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
12026 (match_operand:DI 2 "" "")))]
12027 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12028 "@
12029 addi %0,%1,%2@l
12030 addic %0,%1,%2@l")
12032 (define_insn "*largetoc_low_aix<mode>"
12033 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12034 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
12035 (match_operand:P 2 "" "")))]
12036 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
12037 "la %0,%2@l(%1)")
12039 (define_insn_and_split "*tocref<mode>"
12040 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12041 (match_operand:P 1 "small_toc_ref" "R"))]
12042 "TARGET_TOC"
12043 "la %0,%a1"
12044 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
12045 [(set (match_dup 0) (high:P (match_dup 1)))
12046 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
12048 ;; Elf specific ways of loading addresses for non-PIC code.
12049 ;; The output of this could be r0, but we make a very strong
12050 ;; preference for a base register because it will usually
12051 ;; be needed there.
12052 (define_insn "elf_high"
12053 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12054 (high:SI (match_operand 1 "" "")))]
12055 "TARGET_ELF && ! TARGET_64BIT"
12056 "lis %0,%1@ha")
12058 (define_insn "elf_low"
12059 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12060 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12061 (match_operand 2 "" "")))]
12062 "TARGET_ELF && ! TARGET_64BIT"
12063 "@
12064 la %0,%2@l(%1)
12065 addic %0,%1,%K2")
12066 \f
12067 ;; Call and call_value insns
12068 (define_expand "call"
12069 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12070 (match_operand 1 "" ""))
12071 (use (match_operand 2 "" ""))
12072 (clobber (reg:SI LR_REGNO))])]
12073 ""
12074 "
12075 {
12076 #if TARGET_MACHO
12077 if (MACHOPIC_INDIRECT)
12078 operands[0] = machopic_indirect_call_target (operands[0]);
12079 #endif
12081 gcc_assert (GET_CODE (operands[0]) == MEM);
12082 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12084 operands[0] = XEXP (operands[0], 0);
12086 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12087 {
12088 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
12089 DONE;
12090 }
12092 if (GET_CODE (operands[0]) != SYMBOL_REF
12093 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12094 {
12095 if (INTVAL (operands[2]) & CALL_LONG)
12096 operands[0] = rs6000_longcall_ref (operands[0]);
12098 switch (DEFAULT_ABI)
12099 {
12100 case ABI_V4:
12101 case ABI_DARWIN:
12102 operands[0] = force_reg (Pmode, operands[0]);
12103 break;
12105 default:
12106 gcc_unreachable ();
12107 }
12108 }
12109 }")
12111 (define_expand "call_value"
12112 [(parallel [(set (match_operand 0 "" "")
12113 (call (mem:SI (match_operand 1 "address_operand" ""))
12114 (match_operand 2 "" "")))
12115 (use (match_operand 3 "" ""))
12116 (clobber (reg:SI LR_REGNO))])]
12117 ""
12118 "
12119 {
12120 #if TARGET_MACHO
12121 if (MACHOPIC_INDIRECT)
12122 operands[1] = machopic_indirect_call_target (operands[1]);
12123 #endif
12125 gcc_assert (GET_CODE (operands[1]) == MEM);
12126 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12128 operands[1] = XEXP (operands[1], 0);
12130 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12131 {
12132 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
12133 DONE;
12134 }
12136 if (GET_CODE (operands[1]) != SYMBOL_REF
12137 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12138 {
12139 if (INTVAL (operands[3]) & CALL_LONG)
12140 operands[1] = rs6000_longcall_ref (operands[1]);
12142 switch (DEFAULT_ABI)
12143 {
12144 case ABI_V4:
12145 case ABI_DARWIN:
12146 operands[1] = force_reg (Pmode, operands[1]);
12147 break;
12149 default:
12150 gcc_unreachable ();
12151 }
12152 }
12153 }")
12155 ;; Call to function in current module. No TOC pointer reload needed.
12156 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12157 ;; either the function was not prototyped, or it was prototyped as a
12158 ;; variable argument function. It is > 0 if FP registers were passed
12159 ;; and < 0 if they were not.
12161 (define_insn "*call_local32"
12162 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12163 (match_operand 1 "" "g,g"))
12164 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12165 (clobber (reg:SI LR_REGNO))]
12166 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12167 "*
12168 {
12169 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12170 output_asm_insn (\"crxor 6,6,6\", operands);
12172 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12173 output_asm_insn (\"creqv 6,6,6\", operands);
12175 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12176 }"
12177 [(set_attr "type" "branch")
12178 (set_attr "length" "4,8")])
12180 (define_insn "*call_local64"
12181 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12182 (match_operand 1 "" "g,g"))
12183 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12184 (clobber (reg:SI LR_REGNO))]
12185 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12186 "*
12187 {
12188 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12189 output_asm_insn (\"crxor 6,6,6\", operands);
12191 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12192 output_asm_insn (\"creqv 6,6,6\", operands);
12194 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12195 }"
12196 [(set_attr "type" "branch")
12197 (set_attr "length" "4,8")])
12199 (define_insn "*call_value_local32"
12200 [(set (match_operand 0 "" "")
12201 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12202 (match_operand 2 "" "g,g")))
12203 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12204 (clobber (reg:SI LR_REGNO))]
12205 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12206 "*
12207 {
12208 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12209 output_asm_insn (\"crxor 6,6,6\", operands);
12211 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12212 output_asm_insn (\"creqv 6,6,6\", operands);
12214 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12215 }"
12216 [(set_attr "type" "branch")
12217 (set_attr "length" "4,8")])
12220 (define_insn "*call_value_local64"
12221 [(set (match_operand 0 "" "")
12222 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12223 (match_operand 2 "" "g,g")))
12224 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12225 (clobber (reg:SI LR_REGNO))]
12226 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12227 "*
12228 {
12229 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12230 output_asm_insn (\"crxor 6,6,6\", operands);
12232 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12233 output_asm_insn (\"creqv 6,6,6\", operands);
12235 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12236 }"
12237 [(set_attr "type" "branch")
12238 (set_attr "length" "4,8")])
12241 ;; A function pointer under System V is just a normal pointer
12242 ;; operands[0] is the function pointer
12243 ;; operands[1] is the stack size to clean up
12244 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12245 ;; which indicates how to set cr1
12247 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12248 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12249 (match_operand 1 "" "g,g,g,g"))
12250 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12251 (clobber (reg:SI LR_REGNO))]
12252 "DEFAULT_ABI == ABI_V4
12253 || DEFAULT_ABI == ABI_DARWIN"
12254 {
12255 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12256 output_asm_insn ("crxor 6,6,6", operands);
12258 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12259 output_asm_insn ("creqv 6,6,6", operands);
12261 return "b%T0l";
12262 }
12263 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12264 (set_attr "length" "4,4,8,8")])
12266 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12267 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12268 (match_operand 1 "" "g,g"))
12269 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12270 (clobber (reg:SI LR_REGNO))]
12271 "(DEFAULT_ABI == ABI_DARWIN
12272 || (DEFAULT_ABI == ABI_V4
12273 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12274 {
12275 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12276 output_asm_insn ("crxor 6,6,6", operands);
12278 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12279 output_asm_insn ("creqv 6,6,6", operands);
12281 #if TARGET_MACHO
12282 return output_call(insn, operands, 0, 2);
12283 #else
12284 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12285 {
12286 gcc_assert (!TARGET_SECURE_PLT);
12287 return "bl %z0@plt";
12288 }
12289 else
12290 return "bl %z0";
12291 #endif
12292 }
12293 "DEFAULT_ABI == ABI_V4
12294 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12295 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12296 [(parallel [(call (mem:SI (match_dup 0))
12297 (match_dup 1))
12298 (use (match_dup 2))
12299 (use (match_dup 3))
12300 (clobber (reg:SI LR_REGNO))])]
12301 {
12302 operands[3] = pic_offset_table_rtx;
12303 }
12304 [(set_attr "type" "branch,branch")
12305 (set_attr "length" "4,8")])
12307 (define_insn "*call_nonlocal_sysv_secure<mode>"
12308 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12309 (match_operand 1 "" "g,g"))
12310 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12311 (use (match_operand:SI 3 "register_operand" "r,r"))
12312 (clobber (reg:SI LR_REGNO))]
12313 "(DEFAULT_ABI == ABI_V4
12314 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12315 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12316 {
12317 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12318 output_asm_insn ("crxor 6,6,6", operands);
12320 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12321 output_asm_insn ("creqv 6,6,6", operands);
12323 if (flag_pic == 2)
12324 /* The magic 32768 offset here and in the other sysv call insns
12325 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12326 See sysv4.h:toc_section. */
12327 return "bl %z0+32768@plt";
12328 else
12329 return "bl %z0@plt";
12330 }
12331 [(set_attr "type" "branch,branch")
12332 (set_attr "length" "4,8")])
12334 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12335 [(set (match_operand 0 "" "")
12336 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12337 (match_operand 2 "" "g,g,g,g")))
12338 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12339 (clobber (reg:SI LR_REGNO))]
12340 "DEFAULT_ABI == ABI_V4
12341 || DEFAULT_ABI == ABI_DARWIN"
12342 {
12343 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12344 output_asm_insn ("crxor 6,6,6", operands);
12346 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12347 output_asm_insn ("creqv 6,6,6", operands);
12349 return "b%T1l";
12350 }
12351 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12352 (set_attr "length" "4,4,8,8")])
12354 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12355 [(set (match_operand 0 "" "")
12356 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12357 (match_operand 2 "" "g,g")))
12358 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12359 (clobber (reg:SI LR_REGNO))]
12360 "(DEFAULT_ABI == ABI_DARWIN
12361 || (DEFAULT_ABI == ABI_V4
12362 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12363 {
12364 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12365 output_asm_insn ("crxor 6,6,6", operands);
12367 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12368 output_asm_insn ("creqv 6,6,6", operands);
12370 #if TARGET_MACHO
12371 return output_call(insn, operands, 1, 3);
12372 #else
12373 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12374 {
12375 gcc_assert (!TARGET_SECURE_PLT);
12376 return "bl %z1@plt";
12377 }
12378 else
12379 return "bl %z1";
12380 #endif
12381 }
12382 "DEFAULT_ABI == ABI_V4
12383 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12384 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12385 [(parallel [(set (match_dup 0)
12386 (call (mem:SI (match_dup 1))
12387 (match_dup 2)))
12388 (use (match_dup 3))
12389 (use (match_dup 4))
12390 (clobber (reg:SI LR_REGNO))])]
12391 {
12392 operands[4] = pic_offset_table_rtx;
12393 }
12394 [(set_attr "type" "branch,branch")
12395 (set_attr "length" "4,8")])
12397 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12398 [(set (match_operand 0 "" "")
12399 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12400 (match_operand 2 "" "g,g")))
12401 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12402 (use (match_operand:SI 4 "register_operand" "r,r"))
12403 (clobber (reg:SI LR_REGNO))]
12404 "(DEFAULT_ABI == ABI_V4
12405 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12406 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12407 {
12408 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12409 output_asm_insn ("crxor 6,6,6", operands);
12411 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12412 output_asm_insn ("creqv 6,6,6", operands);
12414 if (flag_pic == 2)
12415 return "bl %z1+32768@plt";
12416 else
12417 return "bl %z1@plt";
12418 }
12419 [(set_attr "type" "branch,branch")
12420 (set_attr "length" "4,8")])
12423 ;; Call to AIX abi function in the same module.
12425 (define_insn "*call_local_aix<mode>"
12426 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
12427 (match_operand 1 "" "g"))
12428 (clobber (reg:P LR_REGNO))]
12429 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12430 "bl %z0"
12431 [(set_attr "type" "branch")
12432 (set_attr "length" "4")])
12434 (define_insn "*call_value_local_aix<mode>"
12435 [(set (match_operand 0 "" "")
12436 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
12437 (match_operand 2 "" "g")))
12438 (clobber (reg:P LR_REGNO))]
12439 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12440 "bl %z1"
12441 [(set_attr "type" "branch")
12442 (set_attr "length" "4")])
12444 ;; Call to AIX abi function which may be in another module.
12445 ;; Restore the TOC pointer (r2) after the call.
12447 (define_insn "*call_nonlocal_aix<mode>"
12448 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
12449 (match_operand 1 "" "g"))
12450 (clobber (reg:P LR_REGNO))]
12451 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12452 "bl %z0\;nop"
12453 [(set_attr "type" "branch")
12454 (set_attr "length" "8")])
12456 (define_insn "*call_value_nonlocal_aix<mode>"
12457 [(set (match_operand 0 "" "")
12458 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
12459 (match_operand 2 "" "g")))
12460 (clobber (reg:P LR_REGNO))]
12461 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12462 "bl %z1\;nop"
12463 [(set_attr "type" "branch")
12464 (set_attr "length" "8")])
12466 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
12467 ;; Operand0 is the addresss of the function to call
12468 ;; Operand2 is the location in the function descriptor to load r2 from
12469 ;; Operand3 is the stack location to hold the current TOC pointer
12471 (define_insn "*call_indirect_aix<mode>"
12472 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12473 (match_operand 1 "" "g,g"))
12474 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12475 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12476 (clobber (reg:P LR_REGNO))]
12477 "DEFAULT_ABI == ABI_AIX"
12478 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12479 [(set_attr "type" "jmpreg")
12480 (set_attr "length" "12")])
12482 (define_insn "*call_value_indirect_aix<mode>"
12483 [(set (match_operand 0 "" "")
12484 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12485 (match_operand 2 "" "g,g")))
12486 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12487 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
12488 (clobber (reg:P LR_REGNO))]
12489 "DEFAULT_ABI == ABI_AIX"
12490 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12491 [(set_attr "type" "jmpreg")
12492 (set_attr "length" "12")])
12494 ;; Call to indirect functions with the ELFv2 ABI.
12495 ;; Operand0 is the addresss of the function to call
12496 ;; Operand2 is the stack location to hold the current TOC pointer
12498 (define_insn "*call_indirect_elfv2<mode>"
12499 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12500 (match_operand 1 "" "g,g"))
12501 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12502 (clobber (reg:P LR_REGNO))]
12503 "DEFAULT_ABI == ABI_ELFv2"
12504 "b%T0l\;<ptrload> 2,%2"
12505 [(set_attr "type" "jmpreg")
12506 (set_attr "length" "8")])
12508 (define_insn "*call_value_indirect_elfv2<mode>"
12509 [(set (match_operand 0 "" "")
12510 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12511 (match_operand 2 "" "g,g")))
12512 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12513 (clobber (reg:P LR_REGNO))]
12514 "DEFAULT_ABI == ABI_ELFv2"
12515 "b%T1l\;<ptrload> 2,%3"
12516 [(set_attr "type" "jmpreg")
12517 (set_attr "length" "8")])
12520 ;; Call subroutine returning any type.
12521 (define_expand "untyped_call"
12522 [(parallel [(call (match_operand 0 "" "")
12523 (const_int 0))
12524 (match_operand 1 "" "")
12525 (match_operand 2 "" "")])]
12526 ""
12527 "
12528 {
12529 int i;
12531 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12533 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12534 {
12535 rtx set = XVECEXP (operands[2], 0, i);
12536 emit_move_insn (SET_DEST (set), SET_SRC (set));
12537 }
12539 /* The optimizer does not know that the call sets the function value
12540 registers we stored in the result block. We avoid problems by
12541 claiming that all hard registers are used and clobbered at this
12542 point. */
12543 emit_insn (gen_blockage ());
12545 DONE;
12546 }")
12548 ;; sibling call patterns
12549 (define_expand "sibcall"
12550 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12551 (match_operand 1 "" ""))
12552 (use (match_operand 2 "" ""))
12553 (use (reg:SI LR_REGNO))
12554 (simple_return)])]
12555 ""
12556 "
12557 {
12558 #if TARGET_MACHO
12559 if (MACHOPIC_INDIRECT)
12560 operands[0] = machopic_indirect_call_target (operands[0]);
12561 #endif
12563 gcc_assert (GET_CODE (operands[0]) == MEM);
12564 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12566 operands[0] = XEXP (operands[0], 0);
12568 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12569 {
12570 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
12571 DONE;
12572 }
12573 }")
12575 (define_expand "sibcall_value"
12576 [(parallel [(set (match_operand 0 "register_operand" "")
12577 (call (mem:SI (match_operand 1 "address_operand" ""))
12578 (match_operand 2 "" "")))
12579 (use (match_operand 3 "" ""))
12580 (use (reg:SI LR_REGNO))
12581 (simple_return)])]
12582 ""
12583 "
12584 {
12585 #if TARGET_MACHO
12586 if (MACHOPIC_INDIRECT)
12587 operands[1] = machopic_indirect_call_target (operands[1]);
12588 #endif
12590 gcc_assert (GET_CODE (operands[1]) == MEM);
12591 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12593 operands[1] = XEXP (operands[1], 0);
12595 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12596 {
12597 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
12598 DONE;
12599 }
12600 }")
12602 ;; this and similar patterns must be marked as using LR, otherwise
12603 ;; dataflow will try to delete the store into it. This is true
12604 ;; even when the actual reg to jump to is in CTR, when LR was
12605 ;; saved and restored around the PIC-setting BCL.
12606 (define_insn "*sibcall_local32"
12607 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12608 (match_operand 1 "" "g,g"))
12609 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12610 (use (reg:SI LR_REGNO))
12611 (simple_return)]
12612 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12613 "*
12614 {
12615 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12616 output_asm_insn (\"crxor 6,6,6\", operands);
12618 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12619 output_asm_insn (\"creqv 6,6,6\", operands);
12621 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12622 }"
12623 [(set_attr "type" "branch")
12624 (set_attr "length" "4,8")])
12626 (define_insn "*sibcall_local64"
12627 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12628 (match_operand 1 "" "g,g"))
12629 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12630 (use (reg:SI LR_REGNO))
12631 (simple_return)]
12632 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12633 "*
12634 {
12635 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12636 output_asm_insn (\"crxor 6,6,6\", operands);
12638 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12639 output_asm_insn (\"creqv 6,6,6\", operands);
12641 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12642 }"
12643 [(set_attr "type" "branch")
12644 (set_attr "length" "4,8")])
12646 (define_insn "*sibcall_value_local32"
12647 [(set (match_operand 0 "" "")
12648 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12649 (match_operand 2 "" "g,g")))
12650 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12651 (use (reg:SI LR_REGNO))
12652 (simple_return)]
12653 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12654 "*
12655 {
12656 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12657 output_asm_insn (\"crxor 6,6,6\", operands);
12659 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12660 output_asm_insn (\"creqv 6,6,6\", operands);
12662 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12663 }"
12664 [(set_attr "type" "branch")
12665 (set_attr "length" "4,8")])
12667 (define_insn "*sibcall_value_local64"
12668 [(set (match_operand 0 "" "")
12669 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12670 (match_operand 2 "" "g,g")))
12671 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12672 (use (reg:SI LR_REGNO))
12673 (simple_return)]
12674 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12675 "*
12676 {
12677 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12678 output_asm_insn (\"crxor 6,6,6\", operands);
12680 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12681 output_asm_insn (\"creqv 6,6,6\", operands);
12683 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12684 }"
12685 [(set_attr "type" "branch")
12686 (set_attr "length" "4,8")])
12688 (define_insn "*sibcall_nonlocal_sysv<mode>"
12689 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12690 (match_operand 1 "" ""))
12691 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12692 (use (reg:SI LR_REGNO))
12693 (simple_return)]
12694 "(DEFAULT_ABI == ABI_DARWIN
12695 || DEFAULT_ABI == ABI_V4)
12696 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12697 "*
12698 {
12699 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12700 output_asm_insn (\"crxor 6,6,6\", operands);
12702 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12703 output_asm_insn (\"creqv 6,6,6\", operands);
12705 if (which_alternative >= 2)
12706 return \"b%T0\";
12707 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12708 {
12709 gcc_assert (!TARGET_SECURE_PLT);
12710 return \"b %z0@plt\";
12711 }
12712 else
12713 return \"b %z0\";
12714 }"
12715 [(set_attr "type" "branch")
12716 (set_attr "length" "4,8,4,8")])
12718 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12719 [(set (match_operand 0 "" "")
12720 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12721 (match_operand 2 "" "")))
12722 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12723 (use (reg:SI LR_REGNO))
12724 (simple_return)]
12725 "(DEFAULT_ABI == ABI_DARWIN
12726 || DEFAULT_ABI == ABI_V4)
12727 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12728 "*
12729 {
12730 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12731 output_asm_insn (\"crxor 6,6,6\", operands);
12733 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12734 output_asm_insn (\"creqv 6,6,6\", operands);
12736 if (which_alternative >= 2)
12737 return \"b%T1\";
12738 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12739 {
12740 gcc_assert (!TARGET_SECURE_PLT);
12741 return \"b %z1@plt\";
12742 }
12743 else
12744 return \"b %z1\";
12745 }"
12746 [(set_attr "type" "branch")
12747 (set_attr "length" "4,8,4,8")])
12749 ;; AIX ABI sibling call patterns.
12751 (define_insn "*sibcall_aix<mode>"
12752 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12753 (match_operand 1 "" "g,g"))
12754 (simple_return)]
12755 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12756 "@
12757 b %z0
12758 b%T0"
12759 [(set_attr "type" "branch")
12760 (set_attr "length" "4")])
12762 (define_insn "*sibcall_value_aix<mode>"
12763 [(set (match_operand 0 "" "")
12764 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12765 (match_operand 2 "" "g,g")))
12766 (simple_return)]
12767 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12768 "@
12769 b %z1
12770 b%T1"
12771 [(set_attr "type" "branch")
12772 (set_attr "length" "4")])
12774 (define_expand "sibcall_epilogue"
12775 [(use (const_int 0))]
12776 ""
12777 {
12778 if (!TARGET_SCHED_PROLOG)
12779 emit_insn (gen_blockage ());
12780 rs6000_emit_epilogue (TRUE);
12781 DONE;
12782 })
12784 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12785 ;; all of memory. This blocks insns from being moved across this point.
12787 (define_insn "blockage"
12788 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12789 ""
12790 "")
12792 (define_expand "probe_stack"
12793 [(set (match_operand 0 "memory_operand" "=m")
12794 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12795 ""
12796 {
12797 if (TARGET_64BIT)
12798 emit_insn (gen_probe_stack_di (operands[0]));
12799 else
12800 emit_insn (gen_probe_stack_si (operands[0]));
12801 DONE;
12802 })
12804 (define_insn "probe_stack_<mode>"
12805 [(set (match_operand:P 0 "memory_operand" "=m")
12806 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
12807 ""
12808 {
12809 operands[1] = gen_rtx_REG (Pmode, 0);
12810 return "st<wd>%U0%X0 %1,%0";
12811 }
12812 [(set (attr "type")
12813 (if_then_else
12814 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
12815 (const_string "store_ux")
12816 (if_then_else
12817 (match_test "update_address_mem (operands[0], VOIDmode)")
12818 (const_string "store_u")
12819 (const_string "store"))))
12820 (set_attr "length" "4")])
12822 (define_insn "probe_stack_range<P:mode>"
12823 [(set (match_operand:P 0 "register_operand" "=r")
12824 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
12825 (match_operand:P 2 "register_operand" "r")]
12826 UNSPECV_PROBE_STACK_RANGE))]
12827 ""
12828 "* return output_probe_stack_range (operands[0], operands[2]);"
12829 [(set_attr "type" "three")])
12830 \f
12831 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12832 ;; signed & unsigned, and one type of branch.
12833 ;;
12834 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12835 ;; insns, and branches.
12837 (define_expand "cbranch<mode>4"
12838 [(use (match_operator 0 "rs6000_cbranch_operator"
12839 [(match_operand:GPR 1 "gpc_reg_operand" "")
12840 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12841 (use (match_operand 3 ""))]
12842 ""
12843 "
12844 {
12845 /* Take care of the possibility that operands[2] might be negative but
12846 this might be a logical operation. That insn doesn't exist. */
12847 if (GET_CODE (operands[2]) == CONST_INT
12848 && INTVAL (operands[2]) < 0)
12849 {
12850 operands[2] = force_reg (<MODE>mode, operands[2]);
12851 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12852 GET_MODE (operands[0]),
12853 operands[1], operands[2]);
12854 }
12856 rs6000_emit_cbranch (<MODE>mode, operands);
12857 DONE;
12858 }")
12860 (define_expand "cbranch<mode>4"
12861 [(use (match_operator 0 "rs6000_cbranch_operator"
12862 [(match_operand:FP 1 "gpc_reg_operand" "")
12863 (match_operand:FP 2 "gpc_reg_operand" "")]))
12864 (use (match_operand 3 ""))]
12865 ""
12866 "
12867 {
12868 rs6000_emit_cbranch (<MODE>mode, operands);
12869 DONE;
12870 }")
12872 (define_expand "cstore<mode>4"
12873 [(use (match_operator 1 "rs6000_cbranch_operator"
12874 [(match_operand:GPR 2 "gpc_reg_operand" "")
12875 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12876 (clobber (match_operand:SI 0 "register_operand"))]
12877 ""
12878 "
12879 {
12880 /* Take care of the possibility that operands[3] might be negative but
12881 this might be a logical operation. That insn doesn't exist. */
12882 if (GET_CODE (operands[3]) == CONST_INT
12883 && INTVAL (operands[3]) < 0)
12884 {
12885 operands[3] = force_reg (<MODE>mode, operands[3]);
12886 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12887 GET_MODE (operands[1]),
12888 operands[2], operands[3]);
12889 }
12891 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12892 For SEQ, likewise, except that comparisons with zero should be done
12893 with an scc insns. However, due to the order that combine see the
12894 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12895 the cases we don't want to handle or are best handled by portable
12896 code. */
12897 if (GET_CODE (operands[1]) == NE)
12898 FAIL;
12899 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12900 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12901 && operands[3] == const0_rtx)
12902 FAIL;
12903 rs6000_emit_sCOND (<MODE>mode, operands);
12904 DONE;
12905 }")
12907 (define_expand "cstore<mode>4"
12908 [(use (match_operator 1 "rs6000_cbranch_operator"
12909 [(match_operand:FP 2 "gpc_reg_operand" "")
12910 (match_operand:FP 3 "gpc_reg_operand" "")]))
12911 (clobber (match_operand:SI 0 "register_operand"))]
12912 ""
12913 "
12914 {
12915 rs6000_emit_sCOND (<MODE>mode, operands);
12916 DONE;
12917 }")
12920 (define_expand "stack_protect_set"
12921 [(match_operand 0 "memory_operand" "")
12922 (match_operand 1 "memory_operand" "")]
12923 ""
12924 {
12925 #ifdef TARGET_THREAD_SSP_OFFSET
12926 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12927 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12928 operands[1] = gen_rtx_MEM (Pmode, addr);
12929 #endif
12930 if (TARGET_64BIT)
12931 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12932 else
12933 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12934 DONE;
12935 })
12937 (define_insn "stack_protect_setsi"
12938 [(set (match_operand:SI 0 "memory_operand" "=m")
12939 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12940 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12941 "TARGET_32BIT"
12942 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
12943 [(set_attr "type" "three")
12944 (set_attr "length" "12")])
12946 (define_insn "stack_protect_setdi"
12947 [(set (match_operand:DI 0 "memory_operand" "=Y")
12948 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
12949 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12950 "TARGET_64BIT"
12951 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
12952 [(set_attr "type" "three")
12953 (set_attr "length" "12")])
12955 (define_expand "stack_protect_test"
12956 [(match_operand 0 "memory_operand" "")
12957 (match_operand 1 "memory_operand" "")
12958 (match_operand 2 "" "")]
12959 ""
12960 {
12961 rtx test, op0, op1;
12962 #ifdef TARGET_THREAD_SSP_OFFSET
12963 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12964 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12965 operands[1] = gen_rtx_MEM (Pmode, addr);
12966 #endif
12967 op0 = operands[0];
12968 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12969 test = gen_rtx_EQ (VOIDmode, op0, op1);
12970 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12971 DONE;
12972 })
12974 (define_insn "stack_protect_testsi"
12975 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12976 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12977 (match_operand:SI 2 "memory_operand" "m,m")]
12978 UNSPEC_SP_TEST))
12979 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12980 (clobber (match_scratch:SI 3 "=&r,&r"))]
12981 "TARGET_32BIT"
12982 "@
12983 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12984 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
12985 [(set_attr "length" "16,20")])
12987 (define_insn "stack_protect_testdi"
12988 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12989 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
12990 (match_operand:DI 2 "memory_operand" "Y,Y")]
12991 UNSPEC_SP_TEST))
12992 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12993 (clobber (match_scratch:DI 3 "=&r,&r"))]
12994 "TARGET_64BIT"
12995 "@
12996 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12997 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
12998 [(set_attr "length" "16,20")])
13000 \f
13001 ;; Here are the actual compare insns.
13002 (define_insn "*cmp<mode>_internal1"
13003 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13004 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13005 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13006 ""
13007 "cmp<wd>%I2 %0,%1,%2"
13008 [(set_attr "type" "cmp")])
13010 ;; If we are comparing a register for equality with a large constant,
13011 ;; we can do this with an XOR followed by a compare. But this is profitable
13012 ;; only if the large constant is only used for the comparison (and in this
13013 ;; case we already have a register to reuse as scratch).
13014 ;;
13015 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13016 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13018 (define_peephole2
13019 [(set (match_operand:SI 0 "register_operand")
13020 (match_operand:SI 1 "logical_const_operand" ""))
13021 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13022 [(match_dup 0)
13023 (match_operand:SI 2 "logical_const_operand" "")]))
13024 (set (match_operand:CC 4 "cc_reg_operand" "")
13025 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13026 (match_dup 0)))
13027 (set (pc)
13028 (if_then_else (match_operator 6 "equality_operator"
13029 [(match_dup 4) (const_int 0)])
13030 (match_operand 7 "" "")
13031 (match_operand 8 "" "")))]
13032 "peep2_reg_dead_p (3, operands[0])
13033 && peep2_reg_dead_p (4, operands[4])"
13034 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13035 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13036 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13038 {
13039 /* Get the constant we are comparing against, and see what it looks like
13040 when sign-extended from 16 to 32 bits. Then see what constant we could
13041 XOR with SEXTC to get the sign-extended value. */
13042 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13043 SImode,
13044 operands[1], operands[2]);
13045 HOST_WIDE_INT c = INTVAL (cnst);
13046 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13047 HOST_WIDE_INT xorv = c ^ sextc;
13049 operands[9] = GEN_INT (xorv);
13050 operands[10] = GEN_INT (sextc);
13051 })
13053 (define_insn "*cmpsi_internal2"
13054 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13055 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13056 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13057 ""
13058 "cmplw%I2 %0,%1,%b2"
13059 [(set_attr "type" "cmp")])
13061 (define_insn "*cmpdi_internal2"
13062 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13063 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13064 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13065 ""
13066 "cmpld%I2 %0,%1,%b2"
13067 [(set_attr "type" "cmp")])
13069 ;; The following two insns don't exist as single insns, but if we provide
13070 ;; them, we can swap an add and compare, which will enable us to overlap more
13071 ;; of the required delay between a compare and branch. We generate code for
13072 ;; them by splitting.
13074 (define_insn ""
13075 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13076 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13077 (match_operand:SI 2 "short_cint_operand" "i")))
13078 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13079 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13080 ""
13081 "#"
13082 [(set_attr "length" "8")])
13084 (define_insn ""
13085 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13086 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13087 (match_operand:SI 2 "u_short_cint_operand" "i")))
13088 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13089 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13090 ""
13091 "#"
13092 [(set_attr "length" "8")])
13094 (define_split
13095 [(set (match_operand:CC 3 "cc_reg_operand" "")
13096 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13097 (match_operand:SI 2 "short_cint_operand" "")))
13098 (set (match_operand:SI 0 "gpc_reg_operand" "")
13099 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13100 ""
13101 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13102 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13104 (define_split
13105 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13106 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13107 (match_operand:SI 2 "u_short_cint_operand" "")))
13108 (set (match_operand:SI 0 "gpc_reg_operand" "")
13109 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13110 ""
13111 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13112 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13114 ;; Only need to compare second words if first words equal
13115 (define_insn "*cmptf_internal1"
13116 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13117 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13118 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13119 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13120 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13121 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13122 [(set_attr "type" "fpcompare")
13123 (set_attr "length" "12")])
13125 (define_insn_and_split "*cmptf_internal2"
13126 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13127 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13128 (match_operand:TF 2 "gpc_reg_operand" "d")))
13129 (clobber (match_scratch:DF 3 "=d"))
13130 (clobber (match_scratch:DF 4 "=d"))
13131 (clobber (match_scratch:DF 5 "=d"))
13132 (clobber (match_scratch:DF 6 "=d"))
13133 (clobber (match_scratch:DF 7 "=d"))
13134 (clobber (match_scratch:DF 8 "=d"))
13135 (clobber (match_scratch:DF 9 "=d"))
13136 (clobber (match_scratch:DF 10 "=d"))
13137 (clobber (match_scratch:GPR 11 "=b"))]
13138 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13139 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13140 "#"
13141 "&& reload_completed"
13142 [(set (match_dup 3) (match_dup 14))
13143 (set (match_dup 4) (match_dup 15))
13144 (set (match_dup 9) (abs:DF (match_dup 5)))
13145 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13146 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13147 (label_ref (match_dup 12))
13148 (pc)))
13149 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13150 (set (pc) (label_ref (match_dup 13)))
13151 (match_dup 12)
13152 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13153 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13154 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13155 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13156 (match_dup 13)]
13157 {
13158 REAL_VALUE_TYPE rv;
13159 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
13160 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
13162 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13163 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13164 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13165 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13166 operands[12] = gen_label_rtx ();
13167 operands[13] = gen_label_rtx ();
13168 real_inf (&rv);
13169 operands[14] = force_const_mem (DFmode,
13170 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13171 operands[15] = force_const_mem (DFmode,
13172 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13173 DFmode));
13174 if (TARGET_TOC)
13175 {
13176 rtx tocref;
13177 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13178 operands[14] = gen_const_mem (DFmode, tocref);
13179 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13180 operands[15] = gen_const_mem (DFmode, tocref);
13181 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13182 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13183 }
13184 })
13185 \f
13186 ;; Now we have the scc insns. We can do some combinations because of the
13187 ;; way the machine works.
13188 ;;
13189 ;; Note that this is probably faster if we can put an insn between the
13190 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13191 ;; cases the insns below which don't use an intermediate CR field will
13192 ;; be used instead.
13193 (define_insn ""
13194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13195 (match_operator:SI 1 "scc_comparison_operator"
13196 [(match_operand 2 "cc_reg_operand" "y")
13197 (const_int 0)]))]
13198 ""
13199 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
13200 [(set (attr "type")
13201 (cond [(match_test "TARGET_MFCRF")
13202 (const_string "mfcrf")
13203 ]
13204 (const_string "mfcr")))
13205 (set_attr "length" "8")])
13207 ;; Same as above, but get the GT bit.
13208 (define_insn "move_from_CR_gt_bit"
13209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13210 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13211 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13212 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
13213 [(set_attr "type" "mfcr")
13214 (set_attr "length" "8")])
13216 ;; Same as above, but get the OV/ORDERED bit.
13217 (define_insn "move_from_CR_ov_bit"
13218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13219 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
13220 UNSPEC_MV_CR_OV))]
13221 "TARGET_ISEL"
13222 "mfcr %0\;rlwinm %0,%0,%t1,1"
13223 [(set_attr "type" "mfcr")
13224 (set_attr "length" "8")])
13226 (define_insn ""
13227 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13228 (match_operator:DI 1 "scc_comparison_operator"
13229 [(match_operand 2 "cc_reg_operand" "y")
13230 (const_int 0)]))]
13231 "TARGET_POWERPC64"
13232 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
13233 [(set (attr "type")
13234 (cond [(match_test "TARGET_MFCRF")
13235 (const_string "mfcrf")
13236 ]
13237 (const_string "mfcr")))
13238 (set_attr "length" "8")])
13240 (define_insn ""
13241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13242 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13243 [(match_operand 2 "cc_reg_operand" "y,y")
13244 (const_int 0)])
13245 (const_int 0)))
13246 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13247 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13248 "TARGET_32BIT"
13249 "@
13250 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
13251 #"
13252 [(set_attr "type" "delayed_compare")
13253 (set_attr "length" "8,16")])
13255 (define_split
13256 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13257 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13258 [(match_operand 2 "cc_reg_operand" "")
13259 (const_int 0)])
13260 (const_int 0)))
13261 (set (match_operand:SI 3 "gpc_reg_operand" "")
13262 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13263 "TARGET_32BIT && reload_completed"
13264 [(set (match_dup 3)
13265 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13266 (set (match_dup 0)
13267 (compare:CC (match_dup 3)
13268 (const_int 0)))]
13269 "")
13271 (define_insn ""
13272 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13273 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13274 [(match_operand 2 "cc_reg_operand" "y")
13275 (const_int 0)])
13276 (match_operand:SI 3 "const_int_operand" "n")))]
13277 ""
13278 "*
13279 {
13280 int is_bit = ccr_bit (operands[1], 1);
13281 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13282 int count;
13284 if (is_bit >= put_bit)
13285 count = is_bit - put_bit;
13286 else
13287 count = 32 - (put_bit - is_bit);
13289 operands[4] = GEN_INT (count);
13290 operands[5] = GEN_INT (put_bit);
13292 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
13293 }"
13294 [(set (attr "type")
13295 (cond [(match_test "TARGET_MFCRF")
13296 (const_string "mfcrf")
13297 ]
13298 (const_string "mfcr")))
13299 (set_attr "length" "8")])
13301 (define_insn ""
13302 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13303 (compare:CC
13304 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13305 [(match_operand 2 "cc_reg_operand" "y,y")
13306 (const_int 0)])
13307 (match_operand:SI 3 "const_int_operand" "n,n"))
13308 (const_int 0)))
13309 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13310 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13311 (match_dup 3)))]
13312 ""
13313 "*
13314 {
13315 int is_bit = ccr_bit (operands[1], 1);
13316 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13317 int count;
13319 /* Force split for non-cc0 compare. */
13320 if (which_alternative == 1)
13321 return \"#\";
13323 if (is_bit >= put_bit)
13324 count = is_bit - put_bit;
13325 else
13326 count = 32 - (put_bit - is_bit);
13328 operands[5] = GEN_INT (count);
13329 operands[6] = GEN_INT (put_bit);
13331 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
13332 }"
13333 [(set_attr "type" "delayed_compare")
13334 (set_attr "length" "8,16")])
13336 (define_split
13337 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13338 (compare:CC
13339 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13340 [(match_operand 2 "cc_reg_operand" "")
13341 (const_int 0)])
13342 (match_operand:SI 3 "const_int_operand" ""))
13343 (const_int 0)))
13344 (set (match_operand:SI 4 "gpc_reg_operand" "")
13345 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13346 (match_dup 3)))]
13347 "reload_completed"
13348 [(set (match_dup 4)
13349 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13350 (match_dup 3)))
13351 (set (match_dup 0)
13352 (compare:CC (match_dup 4)
13353 (const_int 0)))]
13354 "")
13356 ;; There is a 3 cycle delay between consecutive mfcr instructions
13357 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13359 (define_peephole
13360 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13361 (match_operator:SI 1 "scc_comparison_operator"
13362 [(match_operand 2 "cc_reg_operand" "y")
13363 (const_int 0)]))
13364 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13365 (match_operator:SI 4 "scc_comparison_operator"
13366 [(match_operand 5 "cc_reg_operand" "y")
13367 (const_int 0)]))]
13368 "REGNO (operands[2]) != REGNO (operands[5])"
13369 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13370 [(set_attr "type" "mfcr")
13371 (set_attr "length" "12")])
13373 (define_peephole
13374 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13375 (match_operator:DI 1 "scc_comparison_operator"
13376 [(match_operand 2 "cc_reg_operand" "y")
13377 (const_int 0)]))
13378 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13379 (match_operator:DI 4 "scc_comparison_operator"
13380 [(match_operand 5 "cc_reg_operand" "y")
13381 (const_int 0)]))]
13382 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13383 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13384 [(set_attr "type" "mfcr")
13385 (set_attr "length" "12")])
13387 ;; There are some scc insns that can be done directly, without a compare.
13388 ;; These are faster because they don't involve the communications between
13389 ;; the FXU and branch units. In fact, we will be replacing all of the
13390 ;; integer scc insns here or in the portable methods in emit_store_flag.
13391 ;;
13392 ;; Also support (neg (scc ..)) since that construct is used to replace
13393 ;; branches, (plus (scc ..) ..) since that construct is common and
13394 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13395 ;; cases where it is no more expensive than (neg (scc ..)).
13397 ;; Have reload force a constant into a register for the simple insns that
13398 ;; otherwise won't accept constants. We do this because it is faster than
13399 ;; the cmp/mfcr sequence we would otherwise generate.
13401 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13402 (DI "rKJI")])
13404 (define_insn_and_split "*eq<mode>"
13405 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13406 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13407 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13408 ""
13409 "#"
13410 ""
13411 [(set (match_dup 0)
13412 (clz:GPR (match_dup 3)))
13413 (set (match_dup 0)
13414 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13415 {
13416 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13417 {
13418 /* Use output operand as intermediate. */
13419 operands[3] = operands[0];
13421 if (logical_operand (operands[2], <MODE>mode))
13422 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13423 gen_rtx_XOR (<MODE>mode,
13424 operands[1], operands[2])));
13425 else
13426 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13427 gen_rtx_PLUS (<MODE>mode, operands[1],
13428 negate_rtx (<MODE>mode,
13429 operands[2]))));
13430 }
13431 else
13432 operands[3] = operands[1];
13434 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13435 })
13437 (define_insn_and_split "*eq<mode>_compare"
13438 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13439 (compare:CC
13440 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13441 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13442 (const_int 0)))
13443 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13444 (eq:P (match_dup 1) (match_dup 2)))]
13445 "optimize_size"
13446 "#"
13447 "optimize_size"
13448 [(set (match_dup 0)
13449 (clz:P (match_dup 4)))
13450 (parallel [(set (match_dup 3)
13451 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13452 (const_int 0)))
13453 (set (match_dup 0)
13454 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13455 {
13456 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13457 {
13458 /* Use output operand as intermediate. */
13459 operands[4] = operands[0];
13461 if (logical_operand (operands[2], <MODE>mode))
13462 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13463 gen_rtx_XOR (<MODE>mode,
13464 operands[1], operands[2])));
13465 else
13466 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13467 gen_rtx_PLUS (<MODE>mode, operands[1],
13468 negate_rtx (<MODE>mode,
13469 operands[2]))));
13470 }
13471 else
13472 operands[4] = operands[1];
13474 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13475 })
13477 ;; We have insns of the form shown by the first define_insn below. If
13478 ;; there is something inside the comparison operation, we must split it.
13479 (define_split
13480 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13481 (plus:SI (match_operator 1 "comparison_operator"
13482 [(match_operand:SI 2 "" "")
13483 (match_operand:SI 3
13484 "reg_or_cint_operand" "")])
13485 (match_operand:SI 4 "gpc_reg_operand" "")))
13486 (clobber (match_operand:SI 5 "register_operand" ""))]
13487 "! gpc_reg_operand (operands[2], SImode)"
13488 [(set (match_dup 5) (match_dup 2))
13489 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
13490 (match_dup 4)))])
13492 (define_insn "*plus_eqsi"
13493 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13494 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13495 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13496 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13497 "TARGET_32BIT"
13498 "@
13499 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
13500 subfic %0,%1,0\;addze %0,%3
13501 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
13502 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
13503 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
13504 [(set_attr "type" "three,two,three,three,three")
13505 (set_attr "length" "12,8,12,12,12")])
13507 (define_insn "*compare_plus_eqsi"
13508 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13509 (compare:CC
13510 (plus:SI
13511 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13512 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13513 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13514 (const_int 0)))
13515 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13516 "TARGET_32BIT && optimize_size"
13517 "@
13518 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13519 subfic %4,%1,0\;addze. %4,%3
13520 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
13521 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
13522 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13523 #
13524 #
13525 #
13526 #
13527 #"
13528 [(set_attr "type" "compare")
13529 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13531 (define_split
13532 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13533 (compare:CC
13534 (plus:SI
13535 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13536 (match_operand:SI 2 "scc_eq_operand" ""))
13537 (match_operand:SI 3 "gpc_reg_operand" ""))
13538 (const_int 0)))
13539 (clobber (match_scratch:SI 4 ""))]
13540 "TARGET_32BIT && optimize_size && reload_completed"
13541 [(set (match_dup 4)
13542 (plus:SI (eq:SI (match_dup 1)
13543 (match_dup 2))
13544 (match_dup 3)))
13545 (set (match_dup 0)
13546 (compare:CC (match_dup 4)
13547 (const_int 0)))]
13548 "")
13550 (define_insn "*plus_eqsi_compare"
13551 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13552 (compare:CC
13553 (plus:SI
13554 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13555 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13556 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13557 (const_int 0)))
13558 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13559 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13560 "TARGET_32BIT && optimize_size"
13561 "@
13562 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13563 subfic %0,%1,0\;addze. %0,%3
13564 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
13565 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
13566 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13567 #
13568 #
13569 #
13570 #
13571 #"
13572 [(set_attr "type" "compare")
13573 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13575 (define_split
13576 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13577 (compare:CC
13578 (plus:SI
13579 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13580 (match_operand:SI 2 "scc_eq_operand" ""))
13581 (match_operand:SI 3 "gpc_reg_operand" ""))
13582 (const_int 0)))
13583 (set (match_operand:SI 0 "gpc_reg_operand" "")
13584 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13585 "TARGET_32BIT && optimize_size && reload_completed"
13586 [(set (match_dup 0)
13587 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13588 (set (match_dup 4)
13589 (compare:CC (match_dup 0)
13590 (const_int 0)))]
13591 "")
13593 (define_insn "*neg_eq0<mode>"
13594 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13595 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13596 (const_int 0))))]
13597 ""
13598 "addic %0,%1,-1\;subfe %0,%0,%0"
13599 [(set_attr "type" "two")
13600 (set_attr "length" "8")])
13602 (define_insn_and_split "*neg_eq<mode>"
13603 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13604 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13605 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13606 ""
13607 "#"
13608 ""
13609 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13610 {
13611 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13612 {
13613 /* Use output operand as intermediate. */
13614 operands[3] = operands[0];
13616 if (logical_operand (operands[2], <MODE>mode))
13617 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13618 gen_rtx_XOR (<MODE>mode,
13619 operands[1], operands[2])));
13620 else
13621 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13622 gen_rtx_PLUS (<MODE>mode, operands[1],
13623 negate_rtx (<MODE>mode,
13624 operands[2]))));
13625 }
13626 else
13627 operands[3] = operands[1];
13628 })
13630 (define_insn "*ne0_<mode>"
13631 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13632 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13633 (const_int 0)))
13634 (clobber (match_scratch:P 2 "=&r"))]
13635 "!(TARGET_32BIT && TARGET_ISEL)"
13636 "addic %2,%1,-1\;subfe %0,%2,%1"
13637 [(set_attr "type" "two")
13638 (set_attr "length" "8")])
13640 (define_insn "*plus_ne0_<mode>"
13641 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13642 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13643 (const_int 0))
13644 (match_operand:P 2 "gpc_reg_operand" "r")))
13645 (clobber (match_scratch:P 3 "=&r"))]
13646 ""
13647 "addic %3,%1,-1\;addze %0,%2"
13648 [(set_attr "type" "two")
13649 (set_attr "length" "8")])
13651 (define_insn "*compare_plus_ne0_<mode>"
13652 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13653 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13654 (const_int 0))
13655 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13656 (const_int 0)))
13657 (clobber (match_scratch:P 3 "=&r,&r"))
13658 (clobber (match_scratch:P 4 "=X,&r"))]
13659 ""
13660 "@
13661 addic %3,%1,-1\;addze. %3,%2
13662 #"
13663 [(set_attr "type" "compare")
13664 (set_attr "length" "8,12")])
13666 (define_split
13667 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13668 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13669 (const_int 0))
13670 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13671 (clobber (match_scratch:P 3 ""))
13672 (clobber (match_scratch:P 4 ""))]
13673 "reload_completed"
13674 [(parallel [(set (match_dup 3)
13675 (plus:P (ne:P (match_dup 1)
13676 (const_int 0))
13677 (match_dup 2)))
13678 (clobber (match_dup 4))])
13679 (set (match_dup 0)
13680 (compare:CC (match_dup 3)
13681 (const_int 0)))]
13682 "")
13684 ; For combine.
13685 (define_insn "*compare_plus_ne0_<mode>_1"
13686 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13687 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13688 (const_int 0))
13689 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13690 (clobber (match_scratch:P 3 "=&r,&r"))
13691 (clobber (match_scratch:P 4 "=X,&r"))]
13692 ""
13693 "@
13694 addic %3,%1,-1\;addze. %3,%2
13695 #"
13696 [(set_attr "type" "compare")
13697 (set_attr "length" "8,12")])
13699 (define_split
13700 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13701 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13702 (const_int 0))
13703 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13704 (clobber (match_scratch:P 3 ""))
13705 (clobber (match_scratch:P 4 ""))]
13706 "reload_completed"
13707 [(parallel [(set (match_dup 3)
13708 (plus:P (ne:P (match_dup 1)
13709 (const_int 0))
13710 (match_dup 2)))
13711 (clobber (match_dup 4))])
13712 (set (match_dup 0)
13713 (compare:CC (match_dup 3)
13714 (const_int 0)))]
13715 "")
13717 (define_insn "*plus_ne0_<mode>_compare"
13718 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13719 (compare:CC
13720 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13721 (const_int 0))
13722 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13723 (const_int 0)))
13724 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13725 (plus:P (ne:P (match_dup 1)
13726 (const_int 0))
13727 (match_dup 2)))
13728 (clobber (match_scratch:P 3 "=&r,&r"))]
13729 ""
13730 "@
13731 addic %3,%1,-1\;addze. %0,%2
13732 #"
13733 [(set_attr "type" "compare")
13734 (set_attr "length" "8,12")])
13736 (define_split
13737 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13738 (compare:CC
13739 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13740 (const_int 0))
13741 (match_operand:P 2 "gpc_reg_operand" ""))
13742 (const_int 0)))
13743 (set (match_operand:P 0 "gpc_reg_operand" "")
13744 (plus:P (ne:P (match_dup 1)
13745 (const_int 0))
13746 (match_dup 2)))
13747 (clobber (match_scratch:P 3 ""))]
13748 "reload_completed"
13749 [(parallel [(set (match_dup 0)
13750 (plus:P (ne:P (match_dup 1)
13751 (const_int 0))
13752 (match_dup 2)))
13753 (clobber (match_dup 3))])
13754 (set (match_dup 4)
13755 (compare:CC (match_dup 0)
13756 (const_int 0)))]
13757 "")
13759 (define_insn "*leu<mode>"
13760 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13761 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13762 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13763 ""
13764 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
13765 [(set_attr "type" "three")
13766 (set_attr "length" "12")])
13768 (define_insn "*leu<mode>_compare"
13769 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13770 (compare:CC
13771 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13772 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13773 (const_int 0)))
13774 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13775 (leu:P (match_dup 1) (match_dup 2)))]
13776 ""
13777 "@
13778 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
13779 #"
13780 [(set_attr "type" "compare")
13781 (set_attr "length" "12,16")])
13783 (define_split
13784 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13785 (compare:CC
13786 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13787 (match_operand:P 2 "reg_or_short_operand" ""))
13788 (const_int 0)))
13789 (set (match_operand:P 0 "gpc_reg_operand" "")
13790 (leu:P (match_dup 1) (match_dup 2)))]
13791 "reload_completed"
13792 [(set (match_dup 0)
13793 (leu:P (match_dup 1) (match_dup 2)))
13794 (set (match_dup 3)
13795 (compare:CC (match_dup 0)
13796 (const_int 0)))]
13797 "")
13799 (define_insn "*plus_leu<mode>"
13800 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13801 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13802 (match_operand:P 2 "reg_or_short_operand" "rI"))
13803 (match_operand:P 3 "gpc_reg_operand" "r")))]
13804 ""
13805 "subf%I2c %0,%1,%2\;addze %0,%3"
13806 [(set_attr "type" "two")
13807 (set_attr "length" "8")])
13809 (define_insn ""
13810 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13811 (compare:CC
13812 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13813 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13814 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13815 (const_int 0)))
13816 (clobber (match_scratch:SI 4 "=&r,&r"))]
13817 "TARGET_32BIT"
13818 "@
13819 subf%I2c %4,%1,%2\;addze. %4,%3
13820 #"
13821 [(set_attr "type" "compare")
13822 (set_attr "length" "8,12")])
13824 (define_split
13825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13826 (compare:CC
13827 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13828 (match_operand:SI 2 "reg_or_short_operand" ""))
13829 (match_operand:SI 3 "gpc_reg_operand" ""))
13830 (const_int 0)))
13831 (clobber (match_scratch:SI 4 ""))]
13832 "TARGET_32BIT && reload_completed"
13833 [(set (match_dup 4)
13834 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13835 (match_dup 3)))
13836 (set (match_dup 0)
13837 (compare:CC (match_dup 4)
13838 (const_int 0)))]
13839 "")
13841 (define_insn ""
13842 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13843 (compare:CC
13844 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13845 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13846 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13847 (const_int 0)))
13848 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13849 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13850 "TARGET_32BIT"
13851 "@
13852 subf%I2c %0,%1,%2\;addze. %0,%3
13853 #"
13854 [(set_attr "type" "compare")
13855 (set_attr "length" "8,12")])
13857 (define_split
13858 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13859 (compare:CC
13860 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13861 (match_operand:SI 2 "reg_or_short_operand" ""))
13862 (match_operand:SI 3 "gpc_reg_operand" ""))
13863 (const_int 0)))
13864 (set (match_operand:SI 0 "gpc_reg_operand" "")
13865 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13866 "TARGET_32BIT && reload_completed"
13867 [(set (match_dup 0)
13868 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13869 (set (match_dup 4)
13870 (compare:CC (match_dup 0)
13871 (const_int 0)))]
13872 "")
13874 (define_insn "*neg_leu<mode>"
13875 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13876 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13877 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13878 ""
13879 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
13880 [(set_attr "type" "three")
13881 (set_attr "length" "12")])
13883 (define_insn "*and_neg_leu<mode>"
13884 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13885 (and:P (neg:P
13886 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13887 (match_operand:P 2 "reg_or_short_operand" "rI")))
13888 (match_operand:P 3 "gpc_reg_operand" "r")))]
13889 ""
13890 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
13891 [(set_attr "type" "three")
13892 (set_attr "length" "12")])
13894 (define_insn ""
13895 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13896 (compare:CC
13897 (and:SI (neg:SI
13898 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13899 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13900 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13901 (const_int 0)))
13902 (clobber (match_scratch:SI 4 "=&r,&r"))]
13903 "TARGET_32BIT"
13904 "@
13905 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
13906 #"
13907 [(set_attr "type" "compare")
13908 (set_attr "length" "12,16")])
13910 (define_split
13911 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13912 (compare:CC
13913 (and:SI (neg:SI
13914 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13915 (match_operand:SI 2 "reg_or_short_operand" "")))
13916 (match_operand:SI 3 "gpc_reg_operand" ""))
13917 (const_int 0)))
13918 (clobber (match_scratch:SI 4 ""))]
13919 "TARGET_32BIT && reload_completed"
13920 [(set (match_dup 4)
13921 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13922 (match_dup 3)))
13923 (set (match_dup 0)
13924 (compare:CC (match_dup 4)
13925 (const_int 0)))]
13926 "")
13928 (define_insn ""
13929 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13930 (compare:CC
13931 (and:SI (neg:SI
13932 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13933 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13934 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13935 (const_int 0)))
13936 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13937 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13938 "TARGET_32BIT"
13939 "@
13940 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
13941 #"
13942 [(set_attr "type" "compare")
13943 (set_attr "length" "12,16")])
13945 (define_split
13946 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13947 (compare:CC
13948 (and:SI (neg:SI
13949 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13950 (match_operand:SI 2 "reg_or_short_operand" "")))
13951 (match_operand:SI 3 "gpc_reg_operand" ""))
13952 (const_int 0)))
13953 (set (match_operand:SI 0 "gpc_reg_operand" "")
13954 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13955 "TARGET_32BIT && reload_completed"
13956 [(set (match_dup 0)
13957 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13958 (match_dup 3)))
13959 (set (match_dup 4)
13960 (compare:CC (match_dup 0)
13961 (const_int 0)))]
13962 "")
13964 (define_insn_and_split "*ltu<mode>"
13965 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13966 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13967 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13968 ""
13969 "#"
13970 ""
13971 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13972 (set (match_dup 0) (neg:P (match_dup 0)))]
13973 "")
13975 (define_insn_and_split "*ltu<mode>_compare"
13976 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13977 (compare:CC
13978 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13979 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13980 (const_int 0)))
13981 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13982 (ltu:P (match_dup 1) (match_dup 2)))]
13983 ""
13984 "#"
13985 ""
13986 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13987 (parallel [(set (match_dup 3)
13988 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13989 (set (match_dup 0) (neg:P (match_dup 0)))])]
13990 "")
13992 (define_insn_and_split "*plus_ltu<mode>"
13993 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13994 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13995 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13996 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13997 ""
13998 "#"
13999 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14000 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14001 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14002 "")
14004 (define_insn_and_split "*plus_ltu<mode>_compare"
14005 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14006 (compare:CC
14007 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14008 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14009 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14010 (const_int 0)))
14011 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14012 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14013 ""
14014 "#"
14015 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14016 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14017 (parallel [(set (match_dup 4)
14018 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14019 (const_int 0)))
14020 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14021 "")
14023 (define_insn "*neg_ltu<mode>"
14024 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14025 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14026 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14027 ""
14028 "@
14029 subfc %0,%2,%1\;subfe %0,%0,%0
14030 addic %0,%1,%n2\;subfe %0,%0,%0"
14031 [(set_attr "type" "two")
14032 (set_attr "length" "8")])
14034 (define_insn "*geu<mode>"
14035 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14036 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14037 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14038 ""
14039 "@
14040 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
14041 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
14042 [(set_attr "type" "three")
14043 (set_attr "length" "12")])
14045 (define_insn "*geu<mode>_compare"
14046 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14047 (compare:CC
14048 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14049 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14050 (const_int 0)))
14051 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14052 (geu:P (match_dup 1) (match_dup 2)))]
14053 ""
14054 "@
14055 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
14056 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
14057 #
14058 #"
14059 [(set_attr "type" "compare")
14060 (set_attr "length" "12,12,16,16")])
14062 (define_split
14063 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14064 (compare:CC
14065 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14066 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14067 (const_int 0)))
14068 (set (match_operand:P 0 "gpc_reg_operand" "")
14069 (geu:P (match_dup 1) (match_dup 2)))]
14070 "reload_completed"
14071 [(set (match_dup 0)
14072 (geu:P (match_dup 1) (match_dup 2)))
14073 (set (match_dup 3)
14074 (compare:CC (match_dup 0)
14075 (const_int 0)))]
14076 "")
14078 (define_insn "*plus_geu<mode>"
14079 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14080 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14081 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14082 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14083 ""
14084 "@
14085 subfc %0,%2,%1\;addze %0,%3
14086 addic %0,%1,%n2\;addze %0,%3"
14087 [(set_attr "type" "two")
14088 (set_attr "length" "8")])
14090 (define_insn ""
14091 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14092 (compare:CC
14093 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14094 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14095 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14096 (const_int 0)))
14097 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14098 "TARGET_32BIT"
14099 "@
14100 subfc %4,%2,%1\;addze. %4,%3
14101 addic %4,%1,%n2\;addze. %4,%3
14102 #
14103 #"
14104 [(set_attr "type" "compare")
14105 (set_attr "length" "8,8,12,12")])
14107 (define_split
14108 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14109 (compare:CC
14110 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14111 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14112 (match_operand:SI 3 "gpc_reg_operand" ""))
14113 (const_int 0)))
14114 (clobber (match_scratch:SI 4 ""))]
14115 "TARGET_32BIT && reload_completed"
14116 [(set (match_dup 4)
14117 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14118 (match_dup 3)))
14119 (set (match_dup 0)
14120 (compare:CC (match_dup 4)
14121 (const_int 0)))]
14122 "")
14124 (define_insn ""
14125 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14126 (compare:CC
14127 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14128 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14129 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14130 (const_int 0)))
14131 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14132 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14133 "TARGET_32BIT"
14134 "@
14135 subfc %0,%2,%1\;addze. %0,%3
14136 addic %0,%1,%n2\;addze. %0,%3
14137 #
14138 #"
14139 [(set_attr "type" "compare")
14140 (set_attr "length" "8,8,12,12")])
14142 (define_split
14143 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14144 (compare:CC
14145 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14146 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14147 (match_operand:SI 3 "gpc_reg_operand" ""))
14148 (const_int 0)))
14149 (set (match_operand:SI 0 "gpc_reg_operand" "")
14150 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14151 "TARGET_32BIT && reload_completed"
14152 [(set (match_dup 0)
14153 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14154 (set (match_dup 4)
14155 (compare:CC (match_dup 0)
14156 (const_int 0)))]
14157 "")
14159 (define_insn "*neg_geu<mode>"
14160 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14161 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14162 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14163 ""
14164 "@
14165 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
14166 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
14167 [(set_attr "type" "three")
14168 (set_attr "length" "12")])
14170 (define_insn "*and_neg_geu<mode>"
14171 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14172 (and:P (neg:P
14173 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14174 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14175 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14176 ""
14177 "@
14178 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
14179 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
14180 [(set_attr "type" "three")
14181 (set_attr "length" "12")])
14183 (define_insn ""
14184 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14185 (compare:CC
14186 (and:SI (neg:SI
14187 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14188 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14189 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14190 (const_int 0)))
14191 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14192 "TARGET_32BIT"
14193 "@
14194 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
14195 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
14196 #
14197 #"
14198 [(set_attr "type" "compare")
14199 (set_attr "length" "12,12,16,16")])
14201 (define_split
14202 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14203 (compare:CC
14204 (and:SI (neg:SI
14205 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14206 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14207 (match_operand:SI 3 "gpc_reg_operand" ""))
14208 (const_int 0)))
14209 (clobber (match_scratch:SI 4 ""))]
14210 "TARGET_32BIT && reload_completed"
14211 [(set (match_dup 4)
14212 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14213 (match_dup 3)))
14214 (set (match_dup 0)
14215 (compare:CC (match_dup 4)
14216 (const_int 0)))]
14217 "")
14219 (define_insn ""
14220 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14221 (compare:CC
14222 (and:SI (neg:SI
14223 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14224 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14225 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14226 (const_int 0)))
14227 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14228 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14229 "TARGET_32BIT"
14230 "@
14231 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
14232 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
14233 #
14234 #"
14235 [(set_attr "type" "compare")
14236 (set_attr "length" "12,12,16,16")])
14238 (define_split
14239 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14240 (compare:CC
14241 (and:SI (neg:SI
14242 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14243 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14244 (match_operand:SI 3 "gpc_reg_operand" ""))
14245 (const_int 0)))
14246 (set (match_operand:SI 0 "gpc_reg_operand" "")
14247 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14248 "TARGET_32BIT && reload_completed"
14249 [(set (match_dup 0)
14250 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14251 (set (match_dup 4)
14252 (compare:CC (match_dup 0)
14253 (const_int 0)))]
14254 "")
14256 (define_insn "*plus_gt0<mode>"
14257 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14258 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14259 (const_int 0))
14260 (match_operand:P 2 "gpc_reg_operand" "r")))]
14261 ""
14262 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
14263 [(set_attr "type" "three")
14264 (set_attr "length" "12")])
14266 (define_insn ""
14267 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14268 (compare:CC
14269 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14270 (const_int 0))
14271 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14272 (const_int 0)))
14273 (clobber (match_scratch:SI 3 "=&r,&r"))]
14274 "TARGET_32BIT"
14275 "@
14276 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14277 #"
14278 [(set_attr "type" "compare")
14279 (set_attr "length" "12,16")])
14281 (define_split
14282 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14283 (compare:CC
14284 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14285 (const_int 0))
14286 (match_operand:SI 2 "gpc_reg_operand" ""))
14287 (const_int 0)))
14288 (clobber (match_scratch:SI 3 ""))]
14289 "TARGET_32BIT && reload_completed"
14290 [(set (match_dup 3)
14291 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14292 (match_dup 2)))
14293 (set (match_dup 0)
14294 (compare:CC (match_dup 3)
14295 (const_int 0)))]
14296 "")
14298 (define_insn ""
14299 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14300 (compare:CC
14301 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14302 (const_int 0))
14303 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14304 (const_int 0)))
14305 (clobber (match_scratch:DI 3 "=&r,&r"))]
14306 "TARGET_64BIT"
14307 "@
14308 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14309 #"
14310 [(set_attr "type" "compare")
14311 (set_attr "length" "12,16")])
14313 (define_split
14314 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14315 (compare:CC
14316 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14317 (const_int 0))
14318 (match_operand:DI 2 "gpc_reg_operand" ""))
14319 (const_int 0)))
14320 (clobber (match_scratch:DI 3 ""))]
14321 "TARGET_64BIT && reload_completed"
14322 [(set (match_dup 3)
14323 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14324 (match_dup 2)))
14325 (set (match_dup 0)
14326 (compare:CC (match_dup 3)
14327 (const_int 0)))]
14328 "")
14330 (define_insn ""
14331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14332 (compare:CC
14333 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14334 (const_int 0))
14335 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14336 (const_int 0)))
14337 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14338 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14339 "TARGET_32BIT"
14340 "@
14341 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14342 #"
14343 [(set_attr "type" "compare")
14344 (set_attr "length" "12,16")])
14346 (define_split
14347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14348 (compare:CC
14349 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14350 (const_int 0))
14351 (match_operand:SI 2 "gpc_reg_operand" ""))
14352 (const_int 0)))
14353 (set (match_operand:SI 0 "gpc_reg_operand" "")
14354 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14355 "TARGET_32BIT && reload_completed"
14356 [(set (match_dup 0)
14357 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14358 (set (match_dup 3)
14359 (compare:CC (match_dup 0)
14360 (const_int 0)))]
14361 "")
14363 (define_insn ""
14364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14365 (compare:CC
14366 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14367 (const_int 0))
14368 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14369 (const_int 0)))
14370 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14371 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14372 "TARGET_64BIT"
14373 "@
14374 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14375 #"
14376 [(set_attr "type" "compare")
14377 (set_attr "length" "12,16")])
14379 (define_split
14380 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14381 (compare:CC
14382 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14383 (const_int 0))
14384 (match_operand:DI 2 "gpc_reg_operand" ""))
14385 (const_int 0)))
14386 (set (match_operand:DI 0 "gpc_reg_operand" "")
14387 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14388 "TARGET_64BIT && reload_completed"
14389 [(set (match_dup 0)
14390 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14391 (set (match_dup 3)
14392 (compare:CC (match_dup 0)
14393 (const_int 0)))]
14394 "")
14396 (define_insn_and_split "*gtu<mode>"
14397 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14398 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14399 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14400 ""
14401 "#"
14402 ""
14403 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14404 (set (match_dup 0) (neg:P (match_dup 0)))]
14405 "")
14407 (define_insn_and_split "*gtu<mode>_compare"
14408 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14409 (compare:CC
14410 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14411 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14412 (const_int 0)))
14413 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14414 (gtu:P (match_dup 1) (match_dup 2)))]
14415 ""
14416 "#"
14417 ""
14418 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14419 (parallel [(set (match_dup 3)
14420 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14421 (set (match_dup 0) (neg:P (match_dup 0)))])]
14422 "")
14424 (define_insn_and_split "*plus_gtu<mode>"
14425 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14426 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14427 (match_operand:P 2 "reg_or_short_operand" "rI"))
14428 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14429 ""
14430 "#"
14431 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14432 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14433 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14434 "")
14436 (define_insn_and_split "*plus_gtu<mode>_compare"
14437 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14438 (compare:CC
14439 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14440 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14441 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14442 (const_int 0)))
14443 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14444 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14445 ""
14446 "#"
14447 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14448 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14449 (parallel [(set (match_dup 4)
14450 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14451 (const_int 0)))
14452 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14453 "")
14455 (define_insn "*neg_gtu<mode>"
14456 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14457 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14458 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14459 ""
14460 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
14461 [(set_attr "type" "two")
14462 (set_attr "length" "8")])
14464 \f
14465 ;; Define both directions of branch and return. If we need a reload
14466 ;; register, we'd rather use CR0 since it is much easier to copy a
14467 ;; register CC value to there.
14469 (define_insn ""
14470 [(set (pc)
14471 (if_then_else (match_operator 1 "branch_comparison_operator"
14472 [(match_operand 2
14473 "cc_reg_operand" "y")
14474 (const_int 0)])
14475 (label_ref (match_operand 0 "" ""))
14476 (pc)))]
14477 ""
14478 "*
14479 {
14480 return output_cbranch (operands[1], \"%l0\", 0, insn);
14481 }"
14482 [(set_attr "type" "branch")])
14484 (define_insn ""
14485 [(set (pc)
14486 (if_then_else (match_operator 0 "branch_comparison_operator"
14487 [(match_operand 1
14488 "cc_reg_operand" "y")
14489 (const_int 0)])
14490 (any_return)
14491 (pc)))]
14492 "<return_pred>"
14493 "*
14494 {
14495 return output_cbranch (operands[0], NULL, 0, insn);
14496 }"
14497 [(set_attr "type" "jmpreg")
14498 (set_attr "length" "4")])
14500 (define_insn ""
14501 [(set (pc)
14502 (if_then_else (match_operator 1 "branch_comparison_operator"
14503 [(match_operand 2
14504 "cc_reg_operand" "y")
14505 (const_int 0)])
14506 (pc)
14507 (label_ref (match_operand 0 "" ""))))]
14508 ""
14509 "*
14510 {
14511 return output_cbranch (operands[1], \"%l0\", 1, insn);
14512 }"
14513 [(set_attr "type" "branch")])
14515 (define_insn ""
14516 [(set (pc)
14517 (if_then_else (match_operator 0 "branch_comparison_operator"
14518 [(match_operand 1
14519 "cc_reg_operand" "y")
14520 (const_int 0)])
14521 (pc)
14522 (any_return)))]
14523 "<return_pred>"
14524 "*
14525 {
14526 return output_cbranch (operands[0], NULL, 1, insn);
14527 }"
14528 [(set_attr "type" "jmpreg")
14529 (set_attr "length" "4")])
14531 ;; Logic on condition register values.
14533 ; This pattern matches things like
14534 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14535 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14536 ; (const_int 1)))
14537 ; which are generated by the branch logic.
14538 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14540 (define_insn "*cceq_ior_compare"
14541 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14542 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14543 [(match_operator:SI 2
14544 "branch_positive_comparison_operator"
14545 [(match_operand 3
14546 "cc_reg_operand" "y,y")
14547 (const_int 0)])
14548 (match_operator:SI 4
14549 "branch_positive_comparison_operator"
14550 [(match_operand 5
14551 "cc_reg_operand" "0,y")
14552 (const_int 0)])])
14553 (const_int 1)))]
14554 ""
14555 "cr%q1 %E0,%j2,%j4"
14556 [(set_attr "type" "cr_logical,delayed_cr")])
14558 ; Why is the constant -1 here, but 1 in the previous pattern?
14559 ; Because ~1 has all but the low bit set.
14560 (define_insn ""
14561 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14562 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14563 [(not:SI (match_operator:SI 2
14564 "branch_positive_comparison_operator"
14565 [(match_operand 3
14566 "cc_reg_operand" "y,y")
14567 (const_int 0)]))
14568 (match_operator:SI 4
14569 "branch_positive_comparison_operator"
14570 [(match_operand 5
14571 "cc_reg_operand" "0,y")
14572 (const_int 0)])])
14573 (const_int -1)))]
14574 ""
14575 "cr%q1 %E0,%j2,%j4"
14576 [(set_attr "type" "cr_logical,delayed_cr")])
14578 (define_insn "*cceq_rev_compare"
14579 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14580 (compare:CCEQ (match_operator:SI 1
14581 "branch_positive_comparison_operator"
14582 [(match_operand 2
14583 "cc_reg_operand" "0,y")
14584 (const_int 0)])
14585 (const_int 0)))]
14586 ""
14587 "crnot %E0,%j1"
14588 [(set_attr "type" "cr_logical,delayed_cr")])
14590 ;; If we are comparing the result of two comparisons, this can be done
14591 ;; using creqv or crxor.
14593 (define_insn_and_split ""
14594 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14595 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14596 [(match_operand 2 "cc_reg_operand" "y")
14597 (const_int 0)])
14598 (match_operator 3 "branch_comparison_operator"
14599 [(match_operand 4 "cc_reg_operand" "y")
14600 (const_int 0)])))]
14601 ""
14602 "#"
14603 ""
14604 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14605 (match_dup 5)))]
14606 "
14607 {
14608 int positive_1, positive_2;
14610 positive_1 = branch_positive_comparison_operator (operands[1],
14611 GET_MODE (operands[1]));
14612 positive_2 = branch_positive_comparison_operator (operands[3],
14613 GET_MODE (operands[3]));
14615 if (! positive_1)
14616 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14617 GET_CODE (operands[1])),
14618 SImode,
14619 operands[2], const0_rtx);
14620 else if (GET_MODE (operands[1]) != SImode)
14621 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14622 operands[2], const0_rtx);
14624 if (! positive_2)
14625 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14626 GET_CODE (operands[3])),
14627 SImode,
14628 operands[4], const0_rtx);
14629 else if (GET_MODE (operands[3]) != SImode)
14630 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14631 operands[4], const0_rtx);
14633 if (positive_1 == positive_2)
14634 {
14635 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14636 operands[5] = constm1_rtx;
14637 }
14638 else
14639 {
14640 operands[5] = const1_rtx;
14641 }
14642 }")
14644 ;; Unconditional branch and return.
14646 (define_insn "jump"
14647 [(set (pc)
14648 (label_ref (match_operand 0 "" "")))]
14649 ""
14650 "b %l0"
14651 [(set_attr "type" "branch")])
14653 (define_insn "<return_str>return"
14654 [(any_return)]
14655 "<return_pred>"
14656 "blr"
14657 [(set_attr "type" "jmpreg")])
14659 (define_expand "indirect_jump"
14660 [(set (pc) (match_operand 0 "register_operand" ""))])
14662 (define_insn "*indirect_jump<mode>"
14663 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14664 ""
14665 "@
14666 bctr
14667 blr"
14668 [(set_attr "type" "jmpreg")])
14670 ;; Table jump for switch statements:
14671 (define_expand "tablejump"
14672 [(use (match_operand 0 "" ""))
14673 (use (label_ref (match_operand 1 "" "")))]
14674 ""
14675 "
14676 {
14677 if (TARGET_32BIT)
14678 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14679 else
14680 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14681 DONE;
14682 }")
14684 (define_expand "tablejumpsi"
14685 [(set (match_dup 3)
14686 (plus:SI (match_operand:SI 0 "" "")
14687 (match_dup 2)))
14688 (parallel [(set (pc) (match_dup 3))
14689 (use (label_ref (match_operand 1 "" "")))])]
14690 "TARGET_32BIT"
14691 "
14692 { operands[0] = force_reg (SImode, operands[0]);
14693 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14694 operands[3] = gen_reg_rtx (SImode);
14695 }")
14697 (define_expand "tablejumpdi"
14698 [(set (match_dup 4)
14699 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14700 (set (match_dup 3)
14701 (plus:DI (match_dup 4)
14702 (match_dup 2)))
14703 (parallel [(set (pc) (match_dup 3))
14704 (use (label_ref (match_operand 1 "" "")))])]
14705 "TARGET_64BIT"
14706 "
14707 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14708 operands[3] = gen_reg_rtx (DImode);
14709 operands[4] = gen_reg_rtx (DImode);
14710 }")
14712 (define_insn "*tablejump<mode>_internal1"
14713 [(set (pc)
14714 (match_operand:P 0 "register_operand" "c,*l"))
14715 (use (label_ref (match_operand 1 "" "")))]
14716 ""
14717 "@
14718 bctr
14719 blr"
14720 [(set_attr "type" "jmpreg")])
14722 (define_insn "nop"
14723 [(const_int 0)]
14724 ""
14725 "nop")
14727 (define_insn "group_ending_nop"
14728 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14729 ""
14730 "*
14731 {
14732 if (rs6000_cpu_attr == CPU_POWER6)
14733 return \"ori 1,1,0\";
14734 return \"ori 2,2,0\";
14735 }")
14736 \f
14737 ;; Define the subtract-one-and-jump insns, starting with the template
14738 ;; so loop.c knows what to generate.
14740 (define_expand "doloop_end"
14741 [(use (match_operand 0 "" "")) ; loop pseudo
14742 (use (match_operand 1 "" ""))] ; label
14743 ""
14744 "
14745 {
14746 if (TARGET_64BIT)
14747 {
14748 if (GET_MODE (operands[0]) != DImode)
14749 FAIL;
14750 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
14751 }
14752 else
14753 {
14754 if (GET_MODE (operands[0]) != SImode)
14755 FAIL;
14756 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
14757 }
14758 DONE;
14759 }")
14761 (define_expand "ctr<mode>"
14762 [(parallel [(set (pc)
14763 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14764 (const_int 1))
14765 (label_ref (match_operand 1 "" ""))
14766 (pc)))
14767 (set (match_dup 0)
14768 (plus:P (match_dup 0)
14769 (const_int -1)))
14770 (clobber (match_scratch:CC 2 ""))
14771 (clobber (match_scratch:P 3 ""))])]
14772 ""
14773 "")
14775 ;; We need to be able to do this for any operand, including MEM, or we
14776 ;; will cause reload to blow up since we don't allow output reloads on
14777 ;; JUMP_INSNs.
14778 ;; For the length attribute to be calculated correctly, the
14779 ;; label MUST be operand 0.
14781 (define_insn "*ctr<mode>_internal1"
14782 [(set (pc)
14783 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14784 (const_int 1))
14785 (label_ref (match_operand 0 "" ""))
14786 (pc)))
14787 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14788 (plus:P (match_dup 1)
14789 (const_int -1)))
14790 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14791 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14792 ""
14793 "*
14794 {
14795 if (which_alternative != 0)
14796 return \"#\";
14797 else if (get_attr_length (insn) == 4)
14798 return \"bdnz %l0\";
14799 else
14800 return \"bdz $+8\;b %l0\";
14801 }"
14802 [(set_attr "type" "branch")
14803 (set_attr "length" "*,12,16,16")])
14805 (define_insn "*ctr<mode>_internal2"
14806 [(set (pc)
14807 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14808 (const_int 1))
14809 (pc)
14810 (label_ref (match_operand 0 "" ""))))
14811 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14812 (plus:P (match_dup 1)
14813 (const_int -1)))
14814 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14815 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14816 ""
14817 "*
14818 {
14819 if (which_alternative != 0)
14820 return \"#\";
14821 else if (get_attr_length (insn) == 4)
14822 return \"bdz %l0\";
14823 else
14824 return \"bdnz $+8\;b %l0\";
14825 }"
14826 [(set_attr "type" "branch")
14827 (set_attr "length" "*,12,16,16")])
14829 ;; Similar but use EQ
14831 (define_insn "*ctr<mode>_internal5"
14832 [(set (pc)
14833 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14834 (const_int 1))
14835 (label_ref (match_operand 0 "" ""))
14836 (pc)))
14837 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14838 (plus:P (match_dup 1)
14839 (const_int -1)))
14840 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14841 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14842 ""
14843 "*
14844 {
14845 if (which_alternative != 0)
14846 return \"#\";
14847 else if (get_attr_length (insn) == 4)
14848 return \"bdz %l0\";
14849 else
14850 return \"bdnz $+8\;b %l0\";
14851 }"
14852 [(set_attr "type" "branch")
14853 (set_attr "length" "*,12,16,16")])
14855 (define_insn "*ctr<mode>_internal6"
14856 [(set (pc)
14857 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14858 (const_int 1))
14859 (pc)
14860 (label_ref (match_operand 0 "" ""))))
14861 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14862 (plus:P (match_dup 1)
14863 (const_int -1)))
14864 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14865 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14866 ""
14867 "*
14868 {
14869 if (which_alternative != 0)
14870 return \"#\";
14871 else if (get_attr_length (insn) == 4)
14872 return \"bdnz %l0\";
14873 else
14874 return \"bdz $+8\;b %l0\";
14875 }"
14876 [(set_attr "type" "branch")
14877 (set_attr "length" "*,12,16,16")])
14879 ;; Now the splitters if we could not allocate the CTR register
14881 (define_split
14882 [(set (pc)
14883 (if_then_else (match_operator 2 "comparison_operator"
14884 [(match_operand:P 1 "gpc_reg_operand" "")
14885 (const_int 1)])
14886 (match_operand 5 "" "")
14887 (match_operand 6 "" "")))
14888 (set (match_operand:P 0 "gpc_reg_operand" "")
14889 (plus:P (match_dup 1) (const_int -1)))
14890 (clobber (match_scratch:CC 3 ""))
14891 (clobber (match_scratch:P 4 ""))]
14892 "reload_completed"
14893 [(parallel [(set (match_dup 3)
14894 (compare:CC (plus:P (match_dup 1)
14895 (const_int -1))
14896 (const_int 0)))
14897 (set (match_dup 0)
14898 (plus:P (match_dup 1)
14899 (const_int -1)))])
14900 (set (pc) (if_then_else (match_dup 7)
14901 (match_dup 5)
14902 (match_dup 6)))]
14903 "
14904 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14905 operands[3], const0_rtx); }")
14907 (define_split
14908 [(set (pc)
14909 (if_then_else (match_operator 2 "comparison_operator"
14910 [(match_operand:P 1 "gpc_reg_operand" "")
14911 (const_int 1)])
14912 (match_operand 5 "" "")
14913 (match_operand 6 "" "")))
14914 (set (match_operand:P 0 "nonimmediate_operand" "")
14915 (plus:P (match_dup 1) (const_int -1)))
14916 (clobber (match_scratch:CC 3 ""))
14917 (clobber (match_scratch:P 4 ""))]
14918 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14919 [(parallel [(set (match_dup 3)
14920 (compare:CC (plus:P (match_dup 1)
14921 (const_int -1))
14922 (const_int 0)))
14923 (set (match_dup 4)
14924 (plus:P (match_dup 1)
14925 (const_int -1)))])
14926 (set (match_dup 0)
14927 (match_dup 4))
14928 (set (pc) (if_then_else (match_dup 7)
14929 (match_dup 5)
14930 (match_dup 6)))]
14931 "
14932 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14933 operands[3], const0_rtx); }")
14934 \f
14935 (define_insn "trap"
14936 [(trap_if (const_int 1) (const_int 0))]
14937 ""
14938 "trap"
14939 [(set_attr "type" "trap")])
14941 (define_expand "ctrap<mode>4"
14942 [(trap_if (match_operator 0 "ordered_comparison_operator"
14943 [(match_operand:GPR 1 "register_operand")
14944 (match_operand:GPR 2 "reg_or_short_operand")])
14945 (match_operand 3 "zero_constant" ""))]
14946 ""
14947 "")
14949 (define_insn ""
14950 [(trap_if (match_operator 0 "ordered_comparison_operator"
14951 [(match_operand:GPR 1 "register_operand" "r")
14952 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14953 (const_int 0))]
14954 ""
14955 "t<wd>%V0%I2 %1,%2"
14956 [(set_attr "type" "trap")])
14957 \f
14958 ;; Insns related to generating the function prologue and epilogue.
14960 (define_expand "prologue"
14961 [(use (const_int 0))]
14962 ""
14963 {
14964 rs6000_emit_prologue ();
14965 if (!TARGET_SCHED_PROLOG)
14966 emit_insn (gen_blockage ());
14967 DONE;
14968 })
14970 (define_insn "*movesi_from_cr_one"
14971 [(match_parallel 0 "mfcr_operation"
14972 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14973 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14974 (match_operand 3 "immediate_operand" "n")]
14975 UNSPEC_MOVESI_FROM_CR))])]
14976 "TARGET_MFCRF"
14977 "*
14978 {
14979 int mask = 0;
14980 int i;
14981 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14982 {
14983 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14984 operands[4] = GEN_INT (mask);
14985 output_asm_insn (\"mfcr %1,%4\", operands);
14986 }
14987 return \"\";
14988 }"
14989 [(set_attr "type" "mfcrf")])
14991 (define_insn "movesi_from_cr"
14992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14993 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14994 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14995 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14996 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14997 UNSPEC_MOVESI_FROM_CR))]
14998 ""
14999 "mfcr %0"
15000 [(set_attr "type" "mfcr")])
15002 (define_insn "*crsave"
15003 [(match_parallel 0 "crsave_operation"
15004 [(set (match_operand:SI 1 "memory_operand" "=m")
15005 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15006 ""
15007 "stw %2,%1"
15008 [(set_attr "type" "store")])
15010 (define_insn "*stmw"
15011 [(match_parallel 0 "stmw_operation"
15012 [(set (match_operand:SI 1 "memory_operand" "=m")
15013 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15014 "TARGET_MULTIPLE"
15015 "stmw %2,%1"
15016 [(set_attr "type" "store_ux")])
15018 ; The following comment applies to:
15019 ; save_gpregs_*
15020 ; save_fpregs_*
15021 ; restore_gpregs*
15022 ; return_and_restore_gpregs*
15023 ; return_and_restore_fpregs*
15024 ; return_and_restore_fpregs_aix*
15025 ;
15026 ; The out-of-line save / restore functions expects one input argument.
15027 ; Since those are not standard call_insn's, we must avoid using
15028 ; MATCH_OPERAND for that argument. That way the register rename
15029 ; optimization will not try to rename this register.
15030 ; Each pattern is repeated for each possible register number used in
15031 ; various ABIs (r11, r1, and for some functions r12)
15033 (define_insn "*save_gpregs_<mode>_r11"
15034 [(match_parallel 0 "any_parallel_operand"
15035 [(clobber (reg:P 65))
15036 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15037 (use (reg:P 11))
15038 (set (match_operand:P 2 "memory_operand" "=m")
15039 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15040 ""
15041 "bl %1"
15042 [(set_attr "type" "branch")
15043 (set_attr "length" "4")])
15045 (define_insn "*save_gpregs_<mode>_r12"
15046 [(match_parallel 0 "any_parallel_operand"
15047 [(clobber (reg:P 65))
15048 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15049 (use (reg:P 12))
15050 (set (match_operand:P 2 "memory_operand" "=m")
15051 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15052 ""
15053 "bl %1"
15054 [(set_attr "type" "branch")
15055 (set_attr "length" "4")])
15057 (define_insn "*save_gpregs_<mode>_r1"
15058 [(match_parallel 0 "any_parallel_operand"
15059 [(clobber (reg:P 65))
15060 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15061 (use (reg:P 1))
15062 (set (match_operand:P 2 "memory_operand" "=m")
15063 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15064 ""
15065 "bl %1"
15066 [(set_attr "type" "branch")
15067 (set_attr "length" "4")])
15069 (define_insn "*save_fpregs_<mode>_r11"
15070 [(match_parallel 0 "any_parallel_operand"
15071 [(clobber (reg:P 65))
15072 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15073 (use (reg:P 11))
15074 (set (match_operand:DF 2 "memory_operand" "=m")
15075 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15076 ""
15077 "bl %1"
15078 [(set_attr "type" "branch")
15079 (set_attr "length" "4")])
15081 (define_insn "*save_fpregs_<mode>_r12"
15082 [(match_parallel 0 "any_parallel_operand"
15083 [(clobber (reg:P 65))
15084 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15085 (use (reg:P 12))
15086 (set (match_operand:DF 2 "memory_operand" "=m")
15087 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15088 ""
15089 "bl %1"
15090 [(set_attr "type" "branch")
15091 (set_attr "length" "4")])
15093 (define_insn "*save_fpregs_<mode>_r1"
15094 [(match_parallel 0 "any_parallel_operand"
15095 [(clobber (reg:P 65))
15096 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15097 (use (reg:P 1))
15098 (set (match_operand:DF 2 "memory_operand" "=m")
15099 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15100 ""
15101 "bl %1"
15102 [(set_attr "type" "branch")
15103 (set_attr "length" "4")])
15105 ; This is to explain that changes to the stack pointer should
15106 ; not be moved over loads from or stores to stack memory.
15107 (define_insn "stack_tie"
15108 [(match_parallel 0 "tie_operand"
15109 [(set (mem:BLK (reg 1)) (const_int 0))])]
15110 ""
15111 ""
15112 [(set_attr "length" "0")])
15114 (define_expand "epilogue"
15115 [(use (const_int 0))]
15116 ""
15117 {
15118 if (!TARGET_SCHED_PROLOG)
15119 emit_insn (gen_blockage ());
15120 rs6000_emit_epilogue (FALSE);
15121 DONE;
15122 })
15124 ; On some processors, doing the mtcrf one CC register at a time is
15125 ; faster (like on the 604e). On others, doing them all at once is
15126 ; faster; for instance, on the 601 and 750.
15128 (define_expand "movsi_to_cr_one"
15129 [(set (match_operand:CC 0 "cc_reg_operand" "")
15130 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15131 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15132 ""
15133 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15135 (define_insn "*movsi_to_cr"
15136 [(match_parallel 0 "mtcrf_operation"
15137 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15138 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15139 (match_operand 3 "immediate_operand" "n")]
15140 UNSPEC_MOVESI_TO_CR))])]
15141 ""
15142 "*
15143 {
15144 int mask = 0;
15145 int i;
15146 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15147 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15148 operands[4] = GEN_INT (mask);
15149 return \"mtcrf %4,%2\";
15150 }"
15151 [(set_attr "type" "mtcr")])
15153 (define_insn "*mtcrfsi"
15154 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15155 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15156 (match_operand 2 "immediate_operand" "n")]
15157 UNSPEC_MOVESI_TO_CR))]
15158 "GET_CODE (operands[0]) == REG
15159 && CR_REGNO_P (REGNO (operands[0]))
15160 && GET_CODE (operands[2]) == CONST_INT
15161 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15162 "mtcrf %R0,%1"
15163 [(set_attr "type" "mtcr")])
15165 ; The load-multiple instructions have similar properties.
15166 ; Note that "load_multiple" is a name known to the machine-independent
15167 ; code that actually corresponds to the PowerPC load-string.
15169 (define_insn "*lmw"
15170 [(match_parallel 0 "lmw_operation"
15171 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15172 (match_operand:SI 2 "memory_operand" "m"))])]
15173 "TARGET_MULTIPLE"
15174 "lmw %1,%2"
15175 [(set_attr "type" "load_ux")
15176 (set_attr "cell_micro" "always")])
15178 (define_insn "*return_internal_<mode>"
15179 [(simple_return)
15180 (use (match_operand:P 0 "register_operand" "lc"))]
15181 ""
15182 "b%T0"
15183 [(set_attr "type" "jmpreg")])
15185 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15186 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15188 ; The following comment applies to:
15189 ; save_gpregs_*
15190 ; save_fpregs_*
15191 ; restore_gpregs*
15192 ; return_and_restore_gpregs*
15193 ; return_and_restore_fpregs*
15194 ; return_and_restore_fpregs_aix*
15195 ;
15196 ; The out-of-line save / restore functions expects one input argument.
15197 ; Since those are not standard call_insn's, we must avoid using
15198 ; MATCH_OPERAND for that argument. That way the register rename
15199 ; optimization will not try to rename this register.
15200 ; Each pattern is repeated for each possible register number used in
15201 ; various ABIs (r11, r1, and for some functions r12)
15203 (define_insn "*restore_gpregs_<mode>_r11"
15204 [(match_parallel 0 "any_parallel_operand"
15205 [(clobber (match_operand:P 1 "register_operand" "=l"))
15206 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15207 (use (reg:P 11))
15208 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15209 (match_operand:P 4 "memory_operand" "m"))])]
15210 ""
15211 "bl %2"
15212 [(set_attr "type" "branch")
15213 (set_attr "length" "4")])
15215 (define_insn "*restore_gpregs_<mode>_r12"
15216 [(match_parallel 0 "any_parallel_operand"
15217 [(clobber (match_operand:P 1 "register_operand" "=l"))
15218 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15219 (use (reg:P 12))
15220 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15221 (match_operand:P 4 "memory_operand" "m"))])]
15222 ""
15223 "bl %2"
15224 [(set_attr "type" "branch")
15225 (set_attr "length" "4")])
15227 (define_insn "*restore_gpregs_<mode>_r1"
15228 [(match_parallel 0 "any_parallel_operand"
15229 [(clobber (match_operand:P 1 "register_operand" "=l"))
15230 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15231 (use (reg:P 1))
15232 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15233 (match_operand:P 4 "memory_operand" "m"))])]
15234 ""
15235 "bl %2"
15236 [(set_attr "type" "branch")
15237 (set_attr "length" "4")])
15239 (define_insn "*return_and_restore_gpregs_<mode>_r11"
15240 [(match_parallel 0 "any_parallel_operand"
15241 [(return)
15242 (clobber (match_operand:P 1 "register_operand" "=l"))
15243 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15244 (use (reg:P 11))
15245 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15246 (match_operand:P 4 "memory_operand" "m"))])]
15247 ""
15248 "b %2"
15249 [(set_attr "type" "branch")
15250 (set_attr "length" "4")])
15252 (define_insn "*return_and_restore_gpregs_<mode>_r12"
15253 [(match_parallel 0 "any_parallel_operand"
15254 [(return)
15255 (clobber (match_operand:P 1 "register_operand" "=l"))
15256 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15257 (use (reg:P 12))
15258 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15259 (match_operand:P 4 "memory_operand" "m"))])]
15260 ""
15261 "b %2"
15262 [(set_attr "type" "branch")
15263 (set_attr "length" "4")])
15265 (define_insn "*return_and_restore_gpregs_<mode>_r1"
15266 [(match_parallel 0 "any_parallel_operand"
15267 [(return)
15268 (clobber (match_operand:P 1 "register_operand" "=l"))
15269 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15270 (use (reg:P 1))
15271 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15272 (match_operand:P 4 "memory_operand" "m"))])]
15273 ""
15274 "b %2"
15275 [(set_attr "type" "branch")
15276 (set_attr "length" "4")])
15278 (define_insn "*return_and_restore_fpregs_<mode>_r11"
15279 [(match_parallel 0 "any_parallel_operand"
15280 [(return)
15281 (clobber (match_operand:P 1 "register_operand" "=l"))
15282 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15283 (use (reg:P 11))
15284 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15285 (match_operand:DF 4 "memory_operand" "m"))])]
15286 ""
15287 "b %2"
15288 [(set_attr "type" "branch")
15289 (set_attr "length" "4")])
15291 (define_insn "*return_and_restore_fpregs_<mode>_r12"
15292 [(match_parallel 0 "any_parallel_operand"
15293 [(return)
15294 (clobber (match_operand:P 1 "register_operand" "=l"))
15295 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15296 (use (reg:P 12))
15297 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15298 (match_operand:DF 4 "memory_operand" "m"))])]
15299 ""
15300 "b %2"
15301 [(set_attr "type" "branch")
15302 (set_attr "length" "4")])
15304 (define_insn "*return_and_restore_fpregs_<mode>_r1"
15305 [(match_parallel 0 "any_parallel_operand"
15306 [(return)
15307 (clobber (match_operand:P 1 "register_operand" "=l"))
15308 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15309 (use (reg:P 1))
15310 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15311 (match_operand:DF 4 "memory_operand" "m"))])]
15312 ""
15313 "b %2"
15314 [(set_attr "type" "branch")
15315 (set_attr "length" "4")])
15317 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
15318 [(match_parallel 0 "any_parallel_operand"
15319 [(return)
15320 (use (match_operand:P 1 "register_operand" "l"))
15321 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15322 (use (reg:P 11))
15323 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15324 (match_operand:DF 4 "memory_operand" "m"))])]
15325 ""
15326 "b %2"
15327 [(set_attr "type" "branch")
15328 (set_attr "length" "4")])
15330 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
15331 [(match_parallel 0 "any_parallel_operand"
15332 [(return)
15333 (use (match_operand:P 1 "register_operand" "l"))
15334 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15335 (use (reg:P 1))
15336 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15337 (match_operand:DF 4 "memory_operand" "m"))])]
15338 ""
15339 "b %2"
15340 [(set_attr "type" "branch")
15341 (set_attr "length" "4")])
15343 ; This is used in compiling the unwind routines.
15344 (define_expand "eh_return"
15345 [(use (match_operand 0 "general_operand" ""))]
15346 ""
15347 "
15348 {
15349 if (TARGET_32BIT)
15350 emit_insn (gen_eh_set_lr_si (operands[0]));
15351 else
15352 emit_insn (gen_eh_set_lr_di (operands[0]));
15353 DONE;
15354 }")
15356 ; We can't expand this before we know where the link register is stored.
15357 (define_insn "eh_set_lr_<mode>"
15358 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15359 UNSPECV_EH_RR)
15360 (clobber (match_scratch:P 1 "=&b"))]
15361 ""
15362 "#")
15364 (define_split
15365 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15366 (clobber (match_scratch 1 ""))]
15367 "reload_completed"
15368 [(const_int 0)]
15369 "
15370 {
15371 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15372 DONE;
15373 }")
15375 (define_insn "prefetch"
15376 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15377 (match_operand:SI 1 "const_int_operand" "n")
15378 (match_operand:SI 2 "const_int_operand" "n"))]
15379 ""
15380 "*
15381 {
15382 if (GET_CODE (operands[0]) == REG)
15383 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15384 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15385 }"
15386 [(set_attr "type" "load")])
15387 \f
15388 (define_insn "bpermd_<mode>"
15389 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15390 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15391 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15392 "TARGET_POPCNTD"
15393 "bpermd %0,%1,%2"
15394 [(set_attr "type" "popcnt")])
15396 \f
15397 ;; Builtin fma support. Handle
15398 ;; Note that the conditions for expansion are in the FMA_F iterator.
15400 (define_expand "fma<mode>4"
15401 [(set (match_operand:FMA_F 0 "register_operand" "")
15402 (fma:FMA_F
15403 (match_operand:FMA_F 1 "register_operand" "")
15404 (match_operand:FMA_F 2 "register_operand" "")
15405 (match_operand:FMA_F 3 "register_operand" "")))]
15406 ""
15407 "")
15409 (define_insn "*fma<mode>4_fpr"
15410 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15411 (fma:SFDF
15412 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
15413 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15414 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
15415 "TARGET_<MODE>_FPR"
15416 "@
15417 fmadd<Ftrad> %0,%1,%2,%3
15418 xsmadda<Fvsx> %x0,%x1,%x2
15419 xsmaddm<Fvsx> %x0,%x1,%x3"
15420 [(set_attr "type" "fp")
15421 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15423 ; Altivec only has fma and nfms.
15424 (define_expand "fms<mode>4"
15425 [(set (match_operand:FMA_F 0 "register_operand" "")
15426 (fma:FMA_F
15427 (match_operand:FMA_F 1 "register_operand" "")
15428 (match_operand:FMA_F 2 "register_operand" "")
15429 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
15430 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15431 "")
15433 (define_insn "*fms<mode>4_fpr"
15434 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15435 (fma:SFDF
15436 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15437 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15438 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
15439 "TARGET_<MODE>_FPR"
15440 "@
15441 fmsub<Ftrad> %0,%1,%2,%3
15442 xsmsuba<Fvsx> %x0,%x1,%x2
15443 xsmsubm<Fvsx> %x0,%x1,%x3"
15444 [(set_attr "type" "fp")
15445 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15447 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
15448 (define_expand "fnma<mode>4"
15449 [(set (match_operand:FMA_F 0 "register_operand" "")
15450 (neg:FMA_F
15451 (fma:FMA_F
15452 (match_operand:FMA_F 1 "register_operand" "")
15453 (match_operand:FMA_F 2 "register_operand" "")
15454 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15455 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
15456 "")
15458 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
15459 (define_expand "fnms<mode>4"
15460 [(set (match_operand:FMA_F 0 "register_operand" "")
15461 (neg:FMA_F
15462 (fma:FMA_F
15463 (match_operand:FMA_F 1 "register_operand" "")
15464 (match_operand:FMA_F 2 "register_operand" "")
15465 (match_operand:FMA_F 3 "register_operand" ""))))]
15466 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15467 "")
15469 ; Not an official optab name, but used from builtins.
15470 (define_expand "nfma<mode>4"
15471 [(set (match_operand:FMA_F 0 "register_operand" "")
15472 (neg:FMA_F
15473 (fma:FMA_F
15474 (match_operand:FMA_F 1 "register_operand" "")
15475 (match_operand:FMA_F 2 "register_operand" "")
15476 (match_operand:FMA_F 3 "register_operand" ""))))]
15477 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15478 "")
15480 (define_insn "*nfma<mode>4_fpr"
15481 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15482 (neg:SFDF
15483 (fma:SFDF
15484 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15485 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15486 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
15487 "TARGET_<MODE>_FPR"
15488 "@
15489 fnmadd<Ftrad> %0,%1,%2,%3
15490 xsnmadda<Fvsx> %x0,%x1,%x2
15491 xsnmaddm<Fvsx> %x0,%x1,%x3"
15492 [(set_attr "type" "fp")
15493 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15495 ; Not an official optab name, but used from builtins.
15496 (define_expand "nfms<mode>4"
15497 [(set (match_operand:FMA_F 0 "register_operand" "")
15498 (neg:FMA_F
15499 (fma:FMA_F
15500 (match_operand:FMA_F 1 "register_operand" "")
15501 (match_operand:FMA_F 2 "register_operand" "")
15502 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15503 ""
15504 "")
15506 (define_insn "*nfmssf4_fpr"
15507 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15508 (neg:SFDF
15509 (fma:SFDF
15510 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15511 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15512 (neg:SFDF
15513 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
15514 "TARGET_<MODE>_FPR"
15515 "@
15516 fnmsub<Ftrad> %0,%1,%2,%3
15517 xsnmsuba<Fvsx> %x0,%x1,%x2
15518 xsnmsubm<Fvsx> %x0,%x1,%x3"
15519 [(set_attr "type" "fp")
15520 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15522 \f
15523 (define_expand "rs6000_get_timebase"
15524 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
15525 ""
15526 {
15527 if (TARGET_POWERPC64)
15528 emit_insn (gen_rs6000_mftb_di (operands[0]));
15529 else
15530 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
15531 DONE;
15532 })
15534 (define_insn "rs6000_get_timebase_ppc32"
15535 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
15536 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
15537 (clobber (match_scratch:SI 1 "=r"))
15538 (clobber (match_scratch:CC 2 "=y"))]
15539 "!TARGET_POWERPC64"
15540 {
15541 if (WORDS_BIG_ENDIAN)
15542 if (TARGET_MFCRF)
15543 {
15544 return "mfspr %0,269\;"
15545 "mfspr %L0,268\;"
15546 "mfspr %1,269\;"
15547 "cmpw %2,%0,%1\;"
15548 "bne- %2,$-16";
15549 }
15550 else
15551 {
15552 return "mftbu %0\;"
15553 "mftb %L0\;"
15554 "mftbu %1\;"
15555 "cmpw %2,%0,%1\;"
15556 "bne- %2,$-16";
15557 }
15558 else
15559 if (TARGET_MFCRF)
15560 {
15561 return "mfspr %L0,269\;"
15562 "mfspr %0,268\;"
15563 "mfspr %1,269\;"
15564 "cmpw %2,%L0,%1\;"
15565 "bne- %2,$-16";
15566 }
15567 else
15568 {
15569 return "mftbu %L0\;"
15570 "mftb %0\;"
15571 "mftbu %1\;"
15572 "cmpw %2,%L0,%1\;"
15573 "bne- %2,$-16";
15574 }
15575 }
15576 [(set_attr "length" "20")])
15578 (define_insn "rs6000_mftb_<mode>"
15579 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15580 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
15581 ""
15582 {
15583 if (TARGET_MFCRF)
15584 return "mfspr %0,268";
15585 else
15586 return "mftb %0";
15587 })
15589 \f
15590 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
15591 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
15592 ;; register that is being loaded. The fused ops must be physically adjacent.
15594 ;; We use define_peephole for the actual addis/load, and the register used to
15595 ;; hold the addis value must be the same as the register being loaded. We use
15596 ;; define_peephole2 to change the register used for addis to be the register
15597 ;; being loaded, since we can look at whether it is dead after the load insn.
15599 (define_peephole
15600 [(set (match_operand:P 0 "base_reg_operand" "")
15601 (match_operand:P 1 "fusion_gpr_addis" ""))
15602 (set (match_operand:INT1 2 "base_reg_operand" "")
15603 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15604 "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
15605 {
15606 return emit_fusion_gpr_load (operands);
15607 }
15608 [(set_attr "type" "load")
15609 (set_attr "length" "8")])
15611 (define_peephole2
15612 [(set (match_operand:P 0 "base_reg_operand" "")
15613 (match_operand:P 1 "fusion_gpr_addis" ""))
15614 (set (match_operand:INT1 2 "base_reg_operand" "")
15615 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15616 "TARGET_P8_FUSION
15617 && (REGNO (operands[0]) != REGNO (operands[2])
15618 || GET_CODE (operands[3]) == SIGN_EXTEND)
15619 && fusion_gpr_load_p (operands, true)"
15620 [(const_int 0)]
15621 {
15622 expand_fusion_gpr_load (operands);
15623 DONE;
15624 })
15626 \f
15628 (include "sync.md")
15629 (include "vector.md")
15630 (include "vsx.md")
15631 (include "altivec.md")
15632 (include "spe.md")
15633 (include "dfp.md")
15634 (include "paired.md")
15635 (include "crypto.md")
15636 (include "htm.md")