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Reverting merge from trunk
[official-gcc.git] / gcc / config / rl78 / rl78.h
blob3a656de626c1b6cafdf219aa4b7911dea7dbb746
1 /* GCC backend definitions for the Renesas RL78 processor.
2 Copyright (C) 2011-2013 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20 \f
21
22 #define RL78_MUL_NONE (rl78_mul_type == MUL_NONE)
23 #define RL78_MUL_RL78 (rl78_mul_type == MUL_RL78)
24 #define RL78_MUL_G13 (rl78_mul_type == MUL_G13)
25
26 #define TARGET_CPU_CPP_BUILTINS() \
27 do \
28 { \
29 builtin_define ("__RL78__"); \
30 builtin_assert ("cpu=RL78"); \
31 if (RL78_MUL_RL78) \
32 builtin_define ("__RL78_MUL_RL78__"); \
33 if (RL78_MUL_G13) \
34 builtin_define ("__RL78_MUL_G13__"); \
35 if (TARGET_G10) \
36 builtin_define ("__RL78_G10__"); \
37 } \
38 while (0)
39
40 #undef STARTFILE_SPEC
41 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
42
43 #undef ENDFILE_SPEC
44 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
45
46 #undef ASM_SPEC
47 #define ASM_SPEC "\
48 %{mrelax:-relax} \
49 %{mg10} \
50 "
51
52 #undef LINK_SPEC
53 #define LINK_SPEC "\
54 %{mrelax:-relax} \
55 %{!r:--gc-sections} \
56 "
57
58 #undef LIB_SPEC
59 #define LIB_SPEC " \
60 --start-group \
61 -lc \
62 -lsim \
63 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
64 --end-group \
65 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \
66 "
67 \f
68
69 #define BITS_BIG_ENDIAN 0
70 #define BYTES_BIG_ENDIAN 0
71 #define WORDS_BIG_ENDIAN 0
72
73 #ifdef IN_LIBGCC2
74 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
75 #define UNITS_PER_WORD 4
76 /* We have a problem with libgcc2. It only defines two versions of
77 each function, one for "int" and one for "long long". Ie it assumes
78 that "sizeof (int) == sizeof (long)". For the RL78 this is not true
79 and we need a third set of functions. We explicitly define
80 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
81 to get the SI and DI versions from the libgcc2.c sources, and we
82 provide our own set of HI functions, which is why this
83 definition is surrounded by #ifndef..#endif. */
84 #ifndef LIBGCC2_UNITS_PER_WORD
85 #define LIBGCC2_UNITS_PER_WORD 4
86 #endif
87 #else
88 /* Actual width of a word, in units (bytes). */
89 #define UNITS_PER_WORD 1
90 #endif
91
92 #define SHORT_TYPE_SIZE 16
93 #define INT_TYPE_SIZE 16
94 #define LONG_TYPE_SIZE 32
95 #define LONG_LONG_TYPE_SIZE 64
96
97 #define FLOAT_TYPE_SIZE 32
98 #define DOUBLE_TYPE_SIZE 32 /*64*/
99 #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/
100
101 #define LIBGCC2_HAS_DF_MODE 1
102 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
103
104 #define DEFAULT_SIGNED_CHAR 0
105
106 #define STRICT_ALIGNMENT 1
107 #define FUNCTION_BOUNDARY 8
108 #define BIGGEST_ALIGNMENT 16
109 #define STACK_BOUNDARY 16
110 #define PARM_BOUNDARY 16
111
112 #define STACK_GROWS_DOWNWARD 1
113 #define FRAME_GROWS_DOWNWARD 1
114 #define FIRST_PARM_OFFSET(FNDECL) 0
115
116 #define MAX_REGS_PER_ADDRESS 1
117
118 #define Pmode HImode
119 #define POINTER_SIZE 16
120 #undef SIZE_TYPE
121 #define SIZE_TYPE "unsigned int"
122 #undef PTRDIFF_TYPE
123 #define PTRDIFF_TYPE "int"
124 #undef WCHAR_TYPE
125 #define WCHAR_TYPE "long int"
126 #undef WCHAR_TYPE_SIZE
127 #define WCHAR_TYPE_SIZE BITS_PER_WORD
128 #define POINTERS_EXTEND_UNSIGNED 1
129 #define FUNCTION_MODE HImode
130 #define CASE_VECTOR_MODE Pmode
131 #define WORD_REGISTER_OPERATIONS 0
132 #define HAS_LONG_COND_BRANCH 0
133 #define HAS_LONG_UNCOND_BRANCH 0
134
135 #define MOVE_MAX 2
136 #define STARTING_FRAME_OFFSET 0
137
138 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
139
140 #define ADDR_SPACE_FAR 1
141
142 #define HAVE_PRE_DECCREMENT 0
143 #define HAVE_POST_INCREMENT 0
144
145 #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16)
146 #define SLOW_BYTE_ACCESS 0
147
148 #define STORE_FLAG_VALUE 1
149 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
150 #define SHORT_IMMEDIATES_SIGN_EXTEND 0
151 \f
152
153 /* The RL78 has four register banks. Normal operation uses RB0 as
154 real registers, RB1 and RB2 as "virtual" registers (because we know
155 they'll be there, and not used as variables), and RB3 is reserved
156 for interrupt handlers. The virtual registers are accessed as
157 SADDRs:
158
159 FFEE0-FFEE7 RB0
160 FFEE8-FFEEF RB1
161 FFEF0-FFEF7 RB2
162 FFEF8-FFEFF RB3
163 */
164 #define REGISTER_NAMES \
165 { \
166 "x", "a", "c", "b", "e", "d", "l", "h", \
167 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
168 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
169 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
170 "sp", "ap", "psw", "es", "cs" \
171 }
172
173 #define ADDITIONAL_REGISTER_NAMES \
174 { \
175 { "ax", 0 }, \
176 { "bc", 2 }, \
177 { "de", 4 }, \
178 { "hl", 6 }, \
179 { "rp0", 0 }, \
180 { "rp1", 2 }, \
181 { "rp2", 4 }, \
182 { "rp3", 6 }, \
183 { "r0", 0 }, \
184 { "r1", 1 }, \
185 { "r2", 2 }, \
186 { "r3", 3 }, \
187 { "r4", 4 }, \
188 { "r5", 5 }, \
189 { "r6", 6 }, \
190 { "r7", 7 }, \
191 }
192
193 enum reg_class
194 {
195 NO_REGS, /* No registers in set. */
196 XREG,
197 AREG,
198 AXREG,
199 CREG,
200 BREG,
201 BCREG,
202 EREG,
203 DREG,
204 DEREG,
205 LREG,
206 HREG,
207 HLREG,
208 IDX_REGS,
209 QI_REGS,
210 SPREG,
211 R8W_REGS,
212 R10W_REGS,
213 INT_REGS,
214 V_REGS, /* Virtual registers. */
215 GR_REGS, /* Integer registers. */
216 PSWREG,
217 ALL_REGS, /* All registers. */
218 LIM_REG_CLASSES /* Max value + 1. */
219 };
220
221 #define REG_CLASS_NAMES \
222 { \
223 "NO_REGS", \
224 "XREG", \
225 "AREG", \
226 "AXREG", \
227 "CREG", \
228 "BREG", \
229 "BCREG", \
230 "EREG", \
231 "DREG", \
232 "DEREG", \
233 "LREG", \
234 "HREG", \
235 "HLREG", \
236 "IDX_REGS", \
237 "QI_REGS", \
238 "SPREG", \
239 "R8W_REGS", \
240 "R10W_REGS", \
241 "INT_REGS", \
242 "V_REGS", \
243 "GR_REGS", \
244 "PSWREG", \
245 "ALL_REGS" \
246 }
247
248 #define REG_CLASS_CONTENTS \
249 { \
250 { 0x00000000, 0x00000000 }, /* No registers, */ \
251 { 0x00000001, 0x00000000 }, \
252 { 0x00000002, 0x00000000 }, \
253 { 0x00000003, 0x00000000 }, \
254 { 0x00000004, 0x00000000 }, \
255 { 0x00000008, 0x00000000 }, \
256 { 0x0000000c, 0x00000000 }, \
257 { 0x00000010, 0x00000000 }, \
258 { 0x00000020, 0x00000000 }, \
259 { 0x00000030, 0x00000000 }, \
260 { 0x00000040, 0x00000000 }, \
261 { 0x00000080, 0x00000000 }, \
262 { 0x000000c0, 0x00000000 }, \
263 { 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \
264 { 0x000000ff, 0x00000000 }, /* all real registers. */ \
265 { 0x00000000, 0x00000001 }, /* SP */ \
266 { 0x00000300, 0x00000000 }, /* R8 - HImode */ \
267 { 0x00000c00, 0x00000000 }, /* R10 - HImode */ \
268 { 0xff000000, 0x00000000 }, /* INT - HImode */ \
269 { 0xff7fff00, 0x00000000 }, /* Virtual registers. */ \
270 { 0xff7fffff, 0x00000002 }, /* General registers. */ \
271 { 0x04000000, 0x00000004 }, /* PSW. */ \
272 { 0xff7fffff, 0x0000001f } /* All registers. */ \
273 }
274
275 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
276 #define N_REG_CLASSES (int) LIM_REG_CLASSES
277 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
278 + UNITS_PER_WORD - 1) \
279 / UNITS_PER_WORD)
280
281 #define GENERAL_REGS GR_REGS
282 #define BASE_REG_CLASS V_REGS
283 #define INDEX_REG_CLASS V_REGS
284
285 #define FIRST_PSEUDO_REGISTER 37
286
287 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
288 ? GR_REGS : NO_REGS)
289
290 #define FRAME_POINTER_REGNUM 22
291 #define STACK_POINTER_REGNUM 32
292 #define ARG_POINTER_REGNUM 33
293 #define CC_REGNUM 34
294 #define FUNC_RETURN_REGNUM 8
295 #define STATIC_CHAIN_REGNUM 14
296
297 /* Trampolines are implemented with a separate data stack. The memory
298 on stack only holds the function pointer for the chosen stub.
299 */
300
301 #define TRAMPOLINE_SIZE 4
302 #define TRAMPOLINE_ALIGNMENT 16
303
304 #define ELIMINABLE_REGS \
305 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
306 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
307 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
308
309 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
310 (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
311
312
313 #define FUNCTION_ARG_REGNO_P(N) 0
314 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8)
315 #define DEFAULT_PCC_STRUCT_RETURN 0
316
317 #define FIXED_REGISTERS \
318 { \
319 1,1,1,1, 1,1,1,1, \
320 0,0,0,0, 0,0,0,0, \
321 0,0,0,0, 0,0,1,1, \
322 1,1,1,1, 1,1,1,1, \
323 0, 1, 0, 1, 1 \
324 }
325
326 #define CALL_USED_REGISTERS \
327 { \
328 1,1,1,1, 1,1,1,1, \
329 1,1,1,1, 1,1,1,1, \
330 0,0,0,0, 0,0,1,1, \
331 1,1,1,1, 1,1,1,1, \
332 0, 1, 1, 1, 1 \
333 }
334
335 #define LIBCALL_VALUE(MODE) \
336 gen_rtx_REG ((MODE), \
337 FUNC_RETURN_REGNUM)
338
339 /* Order of allocation of registers. */
340
341 #define REG_ALLOC_ORDER \
342 { 8, 9, 10, 11, 12, 13, 14, 15, \
343 16, 17, 18, 19, 20, 21, 22, 23, \
344 0, 1, 6, 7, 2, 3, 4, 5, \
345 24, 25, 26, 27, 28, 29, 30, 31, \
346 32, 33, 34 \
347 }
348
349 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
350 (IN_RANGE ((REGNO), (MIN), (MAX)) \
351 || (reg_renumber != NULL \
352 && reg_renumber[(REGNO)] >= (MIN) \
353 && reg_renumber[(REGNO)] <= (MAX)))
354
355 #ifdef REG_OK_STRICT
356 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 31)
357 #else
358 #define REGNO_OK_FOR_BASE_P(regno) 1
359 #endif
360
361 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
362
363 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
364 rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
365
366 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
367 rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
368
369 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
370 ((COUNT) == 0 \
371 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
372 : NULL_RTX)
373
374 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
375
376 #define ACCUMULATE_OUTGOING_ARGS 1
377
378 typedef unsigned int CUMULATIVE_ARGS;
379
380 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
381 (CUM) = 0
382
383 \f
384 /* FIXME */
385 #define NO_PROFILE_COUNTERS 1
386 #define PROFILE_BEFORE_PROLOGUE 1
387
388 #define FUNCTION_PROFILER(FILE, LABELNO) \
389 fprintf (FILE, "\tbsr\t__mcount\n");
390 \f
391
392 #define HARD_REGNO_NREGS(REGNO, MODE) \
393 rl78_hard_regno_nregs (REGNO, MODE)
394
395 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
396 rl78_hard_regno_mode_ok (REGNO, MODE)
397
398 #define MODES_TIEABLE_P(MODE1, MODE2) \
399 ( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
400 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
401 == ( GET_MODE_CLASS (MODE2) == MODE_FLOAT \
402 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
403 \f
404
405 #define TEXT_SECTION_ASM_OP ".text"
406 #define DATA_SECTION_ASM_OP ".data"
407 #define BSS_SECTION_ASM_OP ".bss"
408 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
409 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
410
411 #define ASM_COMMENT_START " ;"
412 #define ASM_APP_ON ""
413 #define ASM_APP_OFF ""
414 #define LOCAL_LABEL_PREFIX ".L"
415 #undef USER_LABEL_PREFIX
416 #define USER_LABEL_PREFIX "_"
417
418 #define GLOBAL_ASM_OP "\t.global\t"
419
420 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
421 fprintf (FILE, "\t.long .L%d\n", VALUE)
422
423 /* This is how to output an element of a case-vector that is relative.
424 Note: The local label referenced by the "3b" below is emitted by
425 the tablejump insn. */
426
427 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
428 fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
429
430
431 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
432 do \
433 { \
434 if ((LOG) == 0) \
435 break; \
436 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
437 } \
438 while (0)
439
440 /* For PIC put jump tables into the text section so that the offsets that
441 they contain are always computed between two same-section symbols. */
442 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
443 \f
444 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
445 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
446
447 /* Like REG_P except that this macro is true for SET expressions. */
448 #define SET_P(rtl) (GET_CODE (rtl) == SET)
449 \f
450 #undef PREFERRED_DEBUGGING_TYPE
451 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
452
453 #undef DWARF2_ADDR_SIZE
454 #define DWARF2_ADDR_SIZE 4
455
456 #define DWARF2_ASM_LINE_DEBUG_INFO 1
457
458 #define EXIT_IGNORE_STACK 0
459 #define INCOMING_FRAME_SP_OFFSET 4
460 \f
461
462 #define BRANCH_COST(SPEED,PREDICT) 1
463 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
464
465 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
466 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
467
468 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
469
470 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */
471 #define DWARF2_UNWIND_INFO 0
472
473 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()
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