gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27
  28 /* Computing the Length of an Insn.  */
  29 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  30   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  31
  32 /* Check instruction LS-37-FP-implied form.
  33    Note: actually its immediate range is imm9u
  34          since it is used for lwi37/swi37 instructions.  */
  35 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  36   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  37    && REGNO (ra) == FP_REGNUM               \
  38    && satisfies_constraint_Iu09 (imm))
  39
  40 /* Check instruction LS-37-SP-implied form.
  41    Note: actually its immediate range is imm9u
  42          since it is used for lwi37/swi37 instructions.  */
  43 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  44   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  45    && REGNO (ra) == SP_REGNUM               \
  46    && satisfies_constraint_Iu09 (imm))
  47
  48
  49 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  50 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  51
  52 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  53    Note: no need to check ra because Ra5 means it covers all registers.  */
  54 #define NDS32_LS_450_P(rt, ra, imm)                     \
  55   ((imm == const0_rtx)                                  \
  56    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  57        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  58
  59 /* Check instruction RRI-333-form.  */
  60 #define NDS32_RRI_333_P(rt, ra, imm)           \
  61   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  62    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  63    && satisfies_constraint_Iu03 (imm))
  64
  65 /* Check instruction RI-45-form.  */
  66 #define NDS32_RI_45_P(rt, ra, imm)                     \
  67   (REGNO (rt) == REGNO (ra)                            \
  68    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  69        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  70    && satisfies_constraint_Iu05 (imm))
  71
  72
  73 /* Check instruction RR-33-form.  */
  74 #define NDS32_RR_33_P(rt, ra)                   \
  75   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  76    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  77
  78 /* Check instruction RRR-333-form.  */
  79 #define NDS32_RRR_333_P(rt, ra, rb)             \
  80   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  81    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  82    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  83
  84 /* Check instruction RR-45-form.
  85    Note: no need to check rb because Rb5 means it covers all registers.  */
  86 #define NDS32_RR_45_P(rt, ra, rb)               \
  87   (REGNO (rt) == REGNO (ra)                     \
  88    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  89        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  90
  91 /* Classifies address type to distinguish 16-bit/32-bit format.  */
  92 enum nds32_16bit_address_type
  93 {
  94   /* [reg]: 45 format address.  */
  95   ADDRESS_REG,
  96   /* [lo_reg + imm3u]: 333 format address.  */
  97   ADDRESS_LO_REG_IMM3U,
  98   /* post_inc [lo_reg + imm3u]: 333 format address.  */
  99   ADDRESS_POST_INC_LO_REG_IMM3U,
 100   /* [$fp + imm7u]: fp imply address.  */
 101   ADDRESS_FP_IMM7U,
 102   /* [$sp + imm7u]: sp imply address.  */
 103   ADDRESS_SP_IMM7U,
 104   /* Other address format.  */
 105   ADDRESS_NOT_16BIT_FORMAT
 106 };
 107
 108
 109 /* ------------------------------------------------------------------------ */
 110
 111 /* Define maximum numbers of registers for passing arguments.  */
 112 #define NDS32_MAX_REGS_FOR_ARGS 6
 113
 114 /* Define the register number for first argument.  */
 115 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 116
 117 /* Define the register number for return value.  */
 118 #define NDS32_GPR_RET_FIRST_REGNUM 0
 119
 120
 121 /* Define double word alignment bits.  */
 122 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 123
 124 /* Define alignment checking macros for convenience.  */
 125 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 126 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 127 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 128
 129 /* Round X up to the nearest double word.  */
 130 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 131
 132
 133 /* This macro is used to calculate the numbers of registers for
 134    containing 'size' bytes of the argument.
 135    The size of a register is a word in nds32 target.
 136    So we use UNITS_PER_WORD to do the calculation.  */
 137 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 138   ((mode == BLKmode)                                                     \
 139    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 140    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 141
 142 /* This macro is used to return the register number for passing argument.
 143    We need to obey the following rules:
 144      1. If it is required MORE THAN one register,
 145         make sure the register number is a even value.
 146      2. If it is required ONLY one register,
 147         the register number can be odd or even value.  */
 148 #define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type) \
 149   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                \
 150    ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)    \
 151    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 152
 153 /* This macro is to check if there are still available registers
 154    for passing argument.  */
 155 #define NDS32_ARG_PASS_IN_REG_P(reg_offset, mode, type)      \
 156   (((reg_offset) < NDS32_MAX_REGS_FOR_ARGS)                  \
 157    && ((reg_offset) + NDS32_NEED_N_REGS_FOR_ARG (mode, type) \
 158        <= NDS32_MAX_REGS_FOR_ARGS))
 159
 160 /* This macro is to check if the register is required to be saved on stack.
 161    If call_used_regs[regno] == 0, regno is the callee-saved register.
 162    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 163    As long as the register satisfies both criteria above,
 164    it is required to be saved.  */
 165 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 166   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 167
 168 /* ------------------------------------------------------------------------ */
 169
 170 /* A C structure for machine-specific, per-function data.
 171    This is added to the cfun structure.  */
 172 struct GTY(()) machine_function
 173 {
 174   /* Number of bytes allocated on the stack for variadic args
 175      if we want to push them into stack as pretend arguments by ourself.  */
 176   int va_args_size;
 177   /* Number of bytes reserved on the stack for
 178      local and temporary variables.  */
 179   int local_size;
 180   /* Number of bytes allocated on the stack for outgoing arguments.  */
 181   int out_args_size;
 182
 183   /* Number of bytes on the stack for saving $fp.  */
 184   int fp_size;
 185   /* Number of bytes on the stack for saving $gp.  */
 186   int gp_size;
 187   /* Number of bytes on the stack for saving $lp.  */
 188   int lp_size;
 189
 190   /* Number of bytes on the stack for saving callee-saved registers.  */
 191   int callee_saved_regs_size;
 192   /* The padding bytes in callee-saved area may be required.  */
 193   int callee_saved_area_padding_bytes;
 194
 195   /* The first required register that should be saved on stack
 196      for va_args (one named argument + nameless arguments).  */
 197   int va_args_first_regno;
 198   /* The last required register that should be saved on stack
 199      for va_args (one named argument + nameless arguments).  */
 200   int va_args_last_regno;
 201
 202   /* The first required callee-saved register.  */
 203   int callee_saved_regs_first_regno;
 204   /* The last required callee-saved register.  */
 205   int callee_saved_regs_last_regno;
 206
 207   /* Indicate that whether this function needs
 208      prologue/epilogue code generation.  */
 209   int naked_p;
 210   /* Indicate that whether this function
 211      uses fp_as_gp optimization.  */
 212   int fp_as_gp_p;
 213 };
 214
 215 /* A C structure that contains the arguments information.  */
 216 typedef struct
 217 {
 218   unsigned int reg_offset;
 219 } nds32_cumulative_args;
 220
 221 /* ------------------------------------------------------------------------ */
 222
 223 /* The following we define C-ISR related stuff.
 224    In nds32 architecture, we have 73 vectors for interrupt/exception.
 225    For each vector (except for vector 0, which is used for reset behavior),
 226    we allow users to set its register saving scheme and interrupt level.  */
 227
 228 /* There are 73 vectors in nds32 architecture.
 229    0 for reset handler,
 230    1-8 for exception handler,
 231    and 9-72 for interrupt handler.
 232    We use an array, which is defined in nds32.c, to record
 233    essential information for each vector.  */
 234 #define NDS32_N_ISR_VECTORS 73
 235
 236 /* Define possible isr category.  */
 237 enum nds32_isr_category
 238 {
 239   NDS32_ISR_NONE,
 240   NDS32_ISR_INTERRUPT,
 241   NDS32_ISR_EXCEPTION,
 242   NDS32_ISR_RESET
 243 };
 244
 245 /* Define isr register saving scheme.  */
 246 enum nds32_isr_save_reg
 247 {
 248   NDS32_SAVE_ALL,
 249   NDS32_PARTIAL_SAVE
 250 };
 251
 252 /* Define isr nested type.  */
 253 enum nds32_isr_nested_type
 254 {
 255   NDS32_NESTED,
 256   NDS32_NOT_NESTED,
 257   NDS32_NESTED_READY
 258 };
 259
 260 /* Define structure to record isr information.
 261    The isr vector array 'isr_vectors[]' with this structure
 262    is defined in nds32.c.  */
 263 struct nds32_isr_info
 264 {
 265   /* The field to identify isr category.
 266      It should be set to NDS32_ISR_NONE by default.
 267      If user specifies a function as isr by using attribute,
 268      this field will be set accordingly.  */
 269   enum nds32_isr_category category;
 270
 271   /* A string for the applied function name.
 272      It should be set to empty string by default.  */
 273   char func_name[100];
 274
 275   /* The register saving scheme.
 276      It should be set to NDS32_PARTIAL_SAVE by default
 277      unless user specifies attribute to change it.  */
 278   enum nds32_isr_save_reg save_reg;
 279
 280   /* The nested type.
 281      It should be set to NDS32_NOT_NESTED by default
 282      unless user specifies attribute to change it.  */
 283   enum nds32_isr_nested_type nested_type;
 284
 285   /* Total vectors.
 286      The total vectors = interrupt + exception numbers + reset.
 287      It should be set to 0 by default.
 288      This field is ONLY used in NDS32_ISR_RESET category.  */
 289   unsigned int total_n_vectors;
 290
 291   /* A string for nmi handler name.
 292      It should be set to empty string by default.
 293      This field is ONLY used in NDS32_ISR_RESET category.  */
 294   char nmi_name[100];
 295
 296   /* A string for warm handler name.
 297      It should be set to empty string by default.
 298      This field is ONLY used in NDS32_ISR_RESET category.  */
 299   char warm_name[100];
 300 };
 301
 302 /* ------------------------------------------------------------------------ */
 303
 304 /* Define code for all nds32 builtins.  */
 305 enum nds32_builtins
 306 {
 307   NDS32_BUILTIN_ISYNC,
 308   NDS32_BUILTIN_ISB,
 309   NDS32_BUILTIN_MFSR,
 310   NDS32_BUILTIN_MFUSR,
 311   NDS32_BUILTIN_MTSR,
 312   NDS32_BUILTIN_MTUSR,
 313   NDS32_BUILTIN_SETGIE_EN,
 314   NDS32_BUILTIN_SETGIE_DIS
 315 };
 316
 317 /* ------------------------------------------------------------------------ */
 318
 319 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 320 #define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
 321 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 322
 323 /* ------------------------------------------------------------------------ */
 324 \f
 325 /* Controlling the Compilation Driver.  */
 326
 327 #define OPTION_DEFAULT_SPECS \
 328   {"arch", "%{!march=*:-march=%(VALUE)}" }
 329
 330 #define CC1_SPEC \
 331   ""
 332
 333 #define ASM_SPEC \
 334   " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 335
 336 /* If user issues -mrelax, -mforce-fp-as-gp, or -mex9,
 337    we need to pass '--relax' to linker.
 338    Besides, for -mex9, we need to further pass '--mex9'.  */
 339 #define LINK_SPEC \
 340   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 341   " %{mrelax|mforce-fp-as-gp|mex9:--relax}" \
 342   " %{mex9:--mex9}"
 343
 344 #define LIB_SPEC \
 345   " -lc -lgloss"
 346
 347 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 348    by applying different crt stuff.  In the convention, crt0.o is the
 349    startup file without constructor/destructor;
 350    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 351    startup files with constructor/destructor.
 352    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 353    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 354    currently provided by GCC for nds32 target.
 355
 356    For nds32 target so far:
 357    If -mno-ctor-dtor, we are going to link
 358    "crt0.o [user objects]".
 359    If general cases, we are going to link
 360    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 361 #define STARTFILE_SPEC \
 362   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 363   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 364 #define ENDFILE_SPEC \
 365   " %{!mno-ctor-dtor:crtend1.o%s}"
 366
 367 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we configure gcc
 368    with --target=nds32be-* setting.
 369    Check gcc/config.gcc for more information.
 370    In addition, currently we only have elf toolchain,
 371    where mgp-direct is always the default.  */
 372 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 373 #define MULTILIB_DEFAULTS { "mbig-endian", "mgp-direct" }
 374 #else
 375 #define MULTILIB_DEFAULTS { "mlittle-endian", "mgp-direct" }
 376 #endif
 377
 378 \f
 379 /* Run-time Target Specification.  */
 380
 381 #define TARGET_CPU_CPP_BUILTINS()                     \
 382   do                                                  \
 383     {                                                 \
 384       builtin_define ("__nds32__");                   \
 385                                                       \
 386       if (TARGET_ISA_V2)                              \
 387         builtin_define ("__NDS32_ISA_V2__");          \
 388       if (TARGET_ISA_V3)                              \
 389         builtin_define ("__NDS32_ISA_V3__");          \
 390       if (TARGET_ISA_V3M)                             \
 391         builtin_define ("__NDS32_ISA_V3M__");         \
 392                                                       \
 393       if (TARGET_BIG_ENDIAN)                          \
 394         builtin_define ("__big_endian__");            \
 395       if (TARGET_REDUCED_REGS)                        \
 396         builtin_define ("__NDS32_REDUCED_REGS__");    \
 397       if (TARGET_CMOV)                                \
 398         builtin_define ("__NDS32_CMOV__");            \
 399       if (TARGET_PERF_EXT)                            \
 400         builtin_define ("__NDS32_PERF_EXT__");        \
 401       if (TARGET_16_BIT)                              \
 402         builtin_define ("__NDS32_16_BIT__");          \
 403       if (TARGET_GP_DIRECT)                           \
 404         builtin_define ("__NDS32_GP_DIRECT__");       \
 405                                                       \
 406       builtin_assert ("cpu=nds32");                   \
 407       builtin_assert ("machine=nds32");               \
 408     } while (0)
 409
 410 \f
 411 /* Defining Data Structures for Per-function Information.  */
 412
 413 /* This macro is called once per function,
 414    before generation of any RTL has begun.  */
 415 #define INIT_EXPANDERS  nds32_init_expanders ()
 416
 417 \f
 418 /* Storage Layout.  */
 419
 420 #define BITS_BIG_ENDIAN 0
 421
 422 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 423
 424 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 425
 426 #define UNITS_PER_WORD 4
 427
 428 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 429   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 430     {                                                                       \
 431       (m) = SImode;                                                         \
 432     }
 433
 434 #define PARM_BOUNDARY 32
 435
 436 #define STACK_BOUNDARY 64
 437
 438 #define FUNCTION_BOUNDARY 32
 439
 440 #define BIGGEST_ALIGNMENT 64
 441
 442 #define EMPTY_FIELD_BOUNDARY 32
 443
 444 #define STRUCTURE_SIZE_BOUNDARY 8
 445
 446 #define STRICT_ALIGNMENT 1
 447
 448 #define PCC_BITFIELD_TYPE_MATTERS 1
 449
 450 \f
 451 /* Layout of Source Language Data Types.  */
 452
 453 #define INT_TYPE_SIZE           32
 454 #define SHORT_TYPE_SIZE         16
 455 #define LONG_TYPE_SIZE          32
 456 #define LONG_LONG_TYPE_SIZE     64
 457
 458 #define FLOAT_TYPE_SIZE         32
 459 #define DOUBLE_TYPE_SIZE        64
 460 #define LONG_DOUBLE_TYPE_SIZE   64
 461
 462 #define DEFAULT_SIGNED_CHAR 1
 463
 464 #define SIZE_TYPE "long unsigned int"
 465 #define PTRDIFF_TYPE "long int"
 466 #define WCHAR_TYPE "short unsigned int"
 467 #define WCHAR_TYPE_SIZE 16
 468
 469 \f
 470 /* Register Usage.  */
 471
 472 /* Number of actual hardware registers.
 473    The hardware registers are assigned numbers for the compiler
 474    from 0 to just below FIRST_PSEUDO_REGISTER.
 475    All registers that the compiler knows about must be given numbers,
 476    even those that are not normally considered general registers.  */
 477 #define FIRST_PSEUDO_REGISTER 34
 478
 479 /* An initializer that says which registers are used for fixed
 480    purposes all throughout the compiled code and are therefore
 481    not available for general allocation.
 482
 483    $r28 : $fp
 484    $r29 : $gp
 485    $r30 : $lp
 486    $r31 : $sp
 487
 488    caller-save registers: $r0 ~ $r5, $r16 ~ $r23
 489    callee-save registers: $r6 ~ $r10, $r11 ~ $r14
 490
 491    reserved for assembler : $r15
 492    reserved for other use : $r24, $r25, $r26, $r27 */
 493 #define FIXED_REGISTERS                 \
 494 { /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
 495       0,  0,  0,  0,  0,  0,  0,  0,    \
 496   /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
 497       0,  0,  0,  0,  0,  0,  0,  1,    \
 498   /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
 499       0,  0,  0,  0,  0,  0,  0,  0,    \
 500   /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
 501       1,  1,  1,  1,  0,  1,  0,  1,    \
 502   /* ARG_POINTER:32 */                  \
 503       1,                                \
 504   /* FRAME_POINTER:33 */                \
 505       1                                 \
 506 }
 507
 508 /* Identifies the registers that are not available for
 509    general allocation of values that must live across
 510    function calls -- so they are caller-save registers.
 511
 512    0 : callee-save registers
 513    1 : caller-save registers */
 514 #define CALL_USED_REGISTERS             \
 515 { /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
 516       1,  1,  1,  1,  1,  1,  0,  0,    \
 517   /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
 518       0,  0,  0,  0,  0,  0,  0,  1,    \
 519   /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
 520       1,  1,  1,  1,  1,  1,  1,  1,    \
 521   /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
 522       1,  1,  1,  1,  0,  1,  0,  1,    \
 523   /* ARG_POINTER:32 */                  \
 524       1,                                \
 525   /* FRAME_POINTER:33 */                \
 526       1                                 \
 527 }
 528
 529 /* In nds32 target, we have three levels of registers:
 530      LOW_COST_REGS    : $r0 ~ $r7
 531      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 532      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 533 #define REG_ALLOC_ORDER           \
 534 {                                 \
 535    0,  1,  2,  3,  4,  5,  6,  7, \
 536    8,  9, 10, 11, 16, 17, 18, 19, \
 537   12, 13, 14, 15, 20, 21, 22, 23, \
 538   24, 25, 26, 27, 28, 29, 30, 31, \
 539   32,                             \
 540   33                              \
 541 }
 542
 543 /* Tell IRA to use the order we define rather than messing it up with its
 544    own cost calculations.  */
 545 #define HONOR_REG_ALLOC_ORDER
 546
 547 /* The number of consecutive hard regs needed starting at
 548    reg "regno" for holding a value of mode "mode".  */
 549 #define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
 550
 551 /* Value is 1 if hard register "regno" can hold a value
 552    of machine-mode "mode".  */
 553 #define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
 554
 555 /* A C expression that is nonzero if a value of mode1
 556    is accessible in mode2 without copying.
 557    Define this macro to return nonzero in as many cases as possible
 558    since doing so will allow GCC to perform better register allocation.
 559    We can use general registers to tie QI/HI/SI modes together.  */
 560 #define MODES_TIEABLE_P(mode1, mode2)          \
 561   (GET_MODE_CLASS (mode1) == MODE_INT          \
 562    && GET_MODE_CLASS (mode2) == MODE_INT       \
 563    && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD  \
 564    && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
 565
 566 \f
 567 /* Register Classes.  */
 568
 569 /* In nds32 target, we have three levels of registers:
 570      Low cost regsiters    : $r0 ~ $r7
 571      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 572      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 573
 574    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 575    so that it provides more chance to use low cost registers.  */
 576 enum reg_class
 577 {
 578   NO_REGS,
 579   R15_TA_REG,
 580   STACK_REG,
 581   LOW_REGS,
 582   MIDDLE_REGS,
 583   HIGH_REGS,
 584   GENERAL_REGS,
 585   FRAME_REGS,
 586   ALL_REGS,
 587   LIM_REG_CLASSES
 588 };
 589
 590 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 591
 592 #define REG_CLASS_NAMES \
 593 {                       \
 594   "NO_REGS",            \
 595   "R15_TA_REG",         \
 596   "STACK_REG",          \
 597   "LOW_REGS",           \
 598   "MIDDLE_REGS",        \
 599   "HIGH_REGS",          \
 600   "GENERAL_REGS",       \
 601   "FRAME_REGS",         \
 602   "ALL_REGS"            \
 603 }
 604
 605 #define REG_CLASS_CONTENTS \
 606 {                                                            \
 607   {0x00000000, 0x00000000}, /* NO_REGS     :              */ \
 608   {0x00008000, 0x00000000}, /* R15_TA_REG  : 15           */ \
 609   {0x80000000, 0x00000000}, /* STACK_REG   : 31           */ \
 610   {0x000000ff, 0x00000000}, /* LOW_REGS    : 0-7          */ \
 611   {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19  */ \
 612   {0xfff07000, 0x00000000}, /* HIGH_REGS   : 12-14, 20-31 */ \
 613   {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31         */ \
 614   {0x00000000, 0x00000003}, /* FRAME_REGS  : 32, 33       */ \
 615   {0xffffffff, 0x00000003}  /* ALL_REGS    : 0-31, 32, 33 */ \
 616 }
 617
 618 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 619
 620 #define BASE_REG_CLASS GENERAL_REGS
 621 #define INDEX_REG_CLASS GENERAL_REGS
 622
 623 /* Return nonzero if it is suitable for use as a
 624    base register in operand addresses.
 625    So far, we return nonzero only if "num" is a hard reg
 626    of the suitable class or a pseudo register which is
 627    allocated to a suitable hard reg.  */
 628 #define REGNO_OK_FOR_BASE_P(num) \
 629   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 630
 631 /* Return nonzero if it is suitable for use as a
 632    index register in operand addresses.
 633    So far, we return nonzero only if "num" is a hard reg
 634    of the suitable class or a pseudo register which is
 635    allocated to a suitable hard reg.
 636    The difference between an index register and a base register is that
 637    the index register may be scaled.  */
 638 #define REGNO_OK_FOR_INDEX_P(num) \
 639   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 640
 641 \f
 642 /* Obsolete Macros for Defining Constraints.  */
 643
 644 \f
 645 /* Stack Layout and Calling Conventions.  */
 646
 647 #define STACK_GROWS_DOWNWARD
 648
 649 #define FRAME_GROWS_DOWNWARD 1
 650
 651 #define STARTING_FRAME_OFFSET 0
 652
 653 #define STACK_POINTER_OFFSET 0
 654
 655 #define FIRST_PARM_OFFSET(fundecl) 0
 656
 657 #define RETURN_ADDR_RTX(count, frameaddr) \
 658   nds32_return_addr_rtx (count, frameaddr)
 659
 660 /* A C expression whose value is RTL representing the location
 661    of the incoming return address at the beginning of any function
 662    before the prologue.
 663    If this RTL is REG, you should also define
 664    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 665 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 666 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 667
 668 #define STACK_POINTER_REGNUM SP_REGNUM
 669
 670 #define FRAME_POINTER_REGNUM 33
 671
 672 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 673
 674 #define ARG_POINTER_REGNUM 32
 675
 676 #define STATIC_CHAIN_REGNUM 16
 677
 678 #define ELIMINABLE_REGS                                \
 679 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 680   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 681   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 682   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 683
 684 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 685   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 686
 687 #define ACCUMULATE_OUTGOING_ARGS 1
 688
 689 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 690
 691 #define CUMULATIVE_ARGS nds32_cumulative_args
 692
 693 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 694   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 695
 696 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
 697    We better cast REGNO into signed integer so that we can avoid
 698    'comparison of unsigned expression >= 0 is always true' warning.  */
 699 #define FUNCTION_ARG_REGNO_P(regno)                                        \
 700   (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
 701    && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_REGS_FOR_ARGS))
 702
 703 #define DEFAULT_PCC_STRUCT_RETURN 0
 704
 705 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 706    from a function, the stack pointer does not matter.
 707    The value is tested only in functions that have frame pointers.
 708    In nds32 target, the function epilogue recovers the
 709    stack pointer from the frame.  */
 710 #define EXIT_IGNORE_STACK 1
 711
 712 #define FUNCTION_PROFILER(file, labelno) \
 713   fprintf (file, "/* profiler %d */", (labelno))
 714
 715 \f
 716 /* Implementing the Varargs Macros.  */
 717
 718 \f
 719 /* Trampolines for Nested Functions.  */
 720
 721 /* Giving A-function and B-function,
 722    if B-function wants to call A-function's nested function,
 723    we need to fill trampoline code into A-function's stack
 724    so that B-function can execute the code in stack to indirectly
 725    jump to (like 'trampoline' action) desired nested function.
 726
 727    The trampoline code for nds32 target must contains following parts:
 728
 729      1. instructions (4 * 4 = 16 bytes):
 730           get $pc first
 731           load chain_value to static chain register via $pc
 732           load nested function address to $r15 via $pc
 733           jump to desired nested function via $r15
 734      2. data (4 * 2 = 8 bytes):
 735           chain_value
 736           nested function address
 737
 738    Please check nds32.c implementation for more information.  */
 739 #define TRAMPOLINE_SIZE 24
 740
 741 /* Because all instructions/data in trampoline template are 4-byte size,
 742    we set trampoline alignment 8*4=32 bits.  */
 743 #define TRAMPOLINE_ALIGNMENT 32
 744
 745 \f
 746 /* Implicit Calls to Library Routines.  */
 747
 748 \f
 749 /* Addressing Modes.  */
 750
 751 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
 752 #define HAVE_POST_INCREMENT 1
 753 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
 754 #define HAVE_POST_DECREMENT 1
 755
 756 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
 757 #define HAVE_POST_MODIFY_DISP 1
 758 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
 759 #define HAVE_POST_MODIFY_REG  1
 760
 761 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
 762
 763 #define MAX_REGS_PER_ADDRESS 2
 764
 765 \f
 766 /* Anchored Addresses.  */
 767
 768 \f
 769 /* Condition Code Status.  */
 770
 771 \f
 772 /* Describing Relative Costs of Operations.  */
 773
 774 /* A C expression for the cost of a branch instruction.
 775    A value of 1 is the default;
 776    other values are interpreted relative to that.  */
 777 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
 778
 779 #define SLOW_BYTE_ACCESS 1
 780
 781 #define NO_FUNCTION_CSE
 782
 783 \f
 784 /* Adjusting the Instruction Scheduler.  */
 785
 786 \f
 787 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
 788
 789 #define TEXT_SECTION_ASM_OP     "\t.text"
 790 #define DATA_SECTION_ASM_OP     "\t.data"
 791
 792 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
 793    So we use '.section .bss' alternatively.  */
 794 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
 795
 796 /* Define this macro to be an expression with a nonzero value if jump tables
 797    (for tablejump insns) should be output in the text section,
 798    along with the assembler instructions.
 799    Otherwise, the readonly data section is used.  */
 800 #define JUMP_TABLES_IN_TEXT_SECTION 1
 801
 802 \f
 803 /* Position Independent Code.  */
 804
 805 \f
 806 /* Defining the Output Assembler Language.  */
 807
 808 #define ASM_COMMENT_START "!"
 809
 810 #define ASM_APP_ON "! #APP"
 811
 812 #define ASM_APP_OFF "! #NO_APP\n"
 813
 814 #define ASM_OUTPUT_LABELREF(stream, name) \
 815   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
 816
 817 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
 818   assemble_name (stream, XSTR (sym, 0))
 819
 820 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
 821   assemble_name (stream, buf)
 822
 823 #define LOCAL_LABEL_PREFIX "."
 824
 825 #define REGISTER_NAMES                                            \
 826 {                                                                 \
 827   "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
 828   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
 829   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
 830   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
 831   "$AP",                                                          \
 832   "$SFP"                                                          \
 833 }
 834
 835 /* Output normal jump table entry.  */
 836 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 837   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
 838
 839 /* Output pc relative jump table entry.  */
 840 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
 841   do                                                                    \
 842     {                                                                   \
 843       switch (GET_MODE (body))                                          \
 844         {                                                               \
 845         case QImode:                                                    \
 846           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
 847           break;                                                        \
 848         case HImode:                                                    \
 849           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
 850           break;                                                        \
 851         case SImode:                                                    \
 852           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
 853           break;                                                        \
 854         default:                                                        \
 855           gcc_unreachable();                                            \
 856         }                                                               \
 857     } while (0)
 858
 859 /* We have to undef it first because elfos.h formerly define it
 860    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
 861 #undef  ASM_OUTPUT_CASE_LABEL
 862 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
 863   do                                                               \
 864     {                                                              \
 865       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
 866       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
 867     } while (0)
 868
 869 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
 870   do                                                   \
 871     {                                                  \
 872       /* Because our jump table is in text section,    \
 873          we need to make sure 2-byte alignment after   \
 874          the jump table for instructions fetch.  */    \
 875       if (GET_MODE (PATTERN (table)) == QImode)        \
 876         ASM_OUTPUT_ALIGN (stream, 1);                  \
 877       asm_fprintf (stream, "\t! Jump Table End\n");    \
 878     }  while (0)
 879
 880 /* This macro is not documented yet.
 881    But we do need it to make jump table vector aligned.  */
 882 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
 883
 884 #define DWARF2_UNWIND_INFO 1
 885
 886 #define JUMP_ALIGN(x) \
 887   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
 888
 889 #define LOOP_ALIGN(x) \
 890   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
 891
 892 #define LABEL_ALIGN(x) \
 893   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
 894
 895 #define ASM_OUTPUT_ALIGN(stream, power) \
 896   fprintf (stream, "\t.align\t%d\n", power)
 897
 898 \f
 899 /* Controlling Debugging Information Format.  */
 900
 901 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 902
 903 #define DWARF2_DEBUGGING_INFO 1
 904
 905 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 906
 907 \f
 908 /* Cross Compilation and Floating Point.  */
 909
 910 \f
 911 /* Mode Switching Instructions.  */
 912
 913 \f
 914 /* Defining target-specific uses of __attribute__.  */
 915
 916 \f
 917 /* Emulating TLS.  */
 918
 919 \f
 920 /* Defining coprocessor specifics for MIPS targets.  */
 921
 922 \f
 923 /* Parameters for Precompiled Header Validity Checking.  */
 924
 925 \f
 926 /* C++ ABI parameters.  */
 927
 928 \f
 929 /* Adding support for named address spaces.  */
 930
 931 \f
 932 /* Miscellaneous Parameters.  */
 933
 934 /* This is the machine mode that elements of a jump-table should have.  */
 935 #define CASE_VECTOR_MODE Pmode
 936
 937 /* Return the preferred mode for and addr_diff_vec when the mininum
 938    and maximum offset are known.  */
 939 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
 940    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
 941    : (max_offset >= 100) ? HImode                               \
 942    : QImode)
 943
 944 /* Generate pc relative jump table when -fpic or -Os.  */
 945 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
 946
 947 /* Define this macro if operations between registers with integral mode
 948    smaller than a word are always performed on the entire register.  */
 949 #define WORD_REGISTER_OPERATIONS
 950
 951 /* A C expression indicating when insns that read memory in mem_mode,
 952    an integral mode narrower than a word, set the bits outside of mem_mode
 953    to be either the sign-extension or the zero-extension of the data read.  */
 954 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 955
 956 /* The maximum number of bytes that a single instruction can move quickly
 957    between memory and registers or between two memory locations.  */
 958 #define MOVE_MAX 4
 959
 960 /* A C expression that is nonzero if on this machine the number of bits
 961    actually used for the count of a shift operation is equal to the number
 962    of bits needed to represent the size of the object being shifted.  */
 963 #define SHIFT_COUNT_TRUNCATED 1
 964
 965 /* A C expression which is nonzero if on this machine it is safe to "convert"
 966    an integer of 'inprec' bits to one of 'outprec' bits by merely operating
 967    on it as if it had only 'outprec' bits.  */
 968 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
 969
 970 /* A C expression describing the value returned by a comparison operator with
 971    an integral mode and stored by a store-flag instruction ('cstoremode4')
 972    when the condition is true.  */
 973 #define STORE_FLAG_VALUE 1
 974
 975 /* An alias for the machine mode for pointers.  */
 976 #define Pmode SImode
 977
 978 /* An alias for the machine mode used for memory references to functions
 979    being called, in call RTL expressions.  */
 980 #define FUNCTION_MODE SImode
 981
 982 /* ------------------------------------------------------------------------ */