1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
8 by the Free Software Foundation; either version 3, or (at your
9 option) any later version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
32 #include "insn-attr.h"
37 #include "diagnostic-core.h"
42 #include "target-def.h"
43 #include "tm-constrs.h"
46 /* Array of valid operand punctuation characters. */
47 static char m32r_punct_chars
[256];
49 /* Machine-specific symbol_ref flags. */
50 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
51 #define SYMBOL_REF_MODEL(X) \
52 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
54 /* For string literals, etc. */
55 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
57 /* Forward declaration. */
58 static void m32r_option_override (void);
59 static void init_reg_tables (void);
60 static void block_move_call (rtx
, rtx
, rtx
);
61 static int m32r_is_insn (rtx
);
62 static bool m32r_legitimate_address_p (enum machine_mode
, rtx
, bool);
63 static rtx
m32r_legitimize_address (rtx
, rtx
, enum machine_mode
);
64 static bool m32r_mode_dependent_address_p (const_rtx
, addr_space_t
);
65 static tree
m32r_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
66 static void m32r_print_operand (FILE *, rtx
, int);
67 static void m32r_print_operand_address (FILE *, rtx
);
68 static bool m32r_print_operand_punct_valid_p (unsigned char code
);
69 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT
);
70 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT
);
72 static void m32r_file_start (void);
74 static int m32r_adjust_priority (rtx
, int);
75 static int m32r_issue_rate (void);
77 static void m32r_encode_section_info (tree
, rtx
, int);
78 static bool m32r_in_small_data_p (const_tree
);
79 static bool m32r_return_in_memory (const_tree
, const_tree
);
80 static rtx
m32r_function_value (const_tree
, const_tree
, bool);
81 static rtx
m32r_libcall_value (enum machine_mode
, const_rtx
);
82 static bool m32r_function_value_regno_p (const unsigned int);
83 static void m32r_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
,
85 static void init_idents (void);
86 static bool m32r_rtx_costs (rtx
, int, int, int, int *, bool speed
);
87 static int m32r_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
88 static bool m32r_pass_by_reference (cumulative_args_t
, enum machine_mode
,
90 static int m32r_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
92 static rtx
m32r_function_arg (cumulative_args_t
, enum machine_mode
,
94 static void m32r_function_arg_advance (cumulative_args_t
, enum machine_mode
,
96 static bool m32r_can_eliminate (const int, const int);
97 static void m32r_conditional_register_usage (void);
98 static void m32r_trampoline_init (rtx
, tree
, rtx
);
99 static bool m32r_legitimate_constant_p (enum machine_mode
, rtx
);
101 /* M32R specific attributes. */
103 static const struct attribute_spec m32r_attribute_table
[] =
105 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
106 affects_type_identity } */
107 { "interrupt", 0, 0, true, false, false, NULL
, false },
108 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
,
110 { NULL
, 0, 0, false, false, false, NULL
, false }
113 /* Initialize the GCC target structure. */
114 #undef TARGET_ATTRIBUTE_TABLE
115 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
117 #undef TARGET_LEGITIMATE_ADDRESS_P
118 #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
119 #undef TARGET_LEGITIMIZE_ADDRESS
120 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
121 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
122 #define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
124 #undef TARGET_ASM_ALIGNED_HI_OP
125 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
126 #undef TARGET_ASM_ALIGNED_SI_OP
127 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
129 #undef TARGET_PRINT_OPERAND
130 #define TARGET_PRINT_OPERAND m32r_print_operand
131 #undef TARGET_PRINT_OPERAND_ADDRESS
132 #define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
133 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
134 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
136 #undef TARGET_ASM_FUNCTION_PROLOGUE
137 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
138 #undef TARGET_ASM_FUNCTION_EPILOGUE
139 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
141 #undef TARGET_ASM_FILE_START
142 #define TARGET_ASM_FILE_START m32r_file_start
144 #undef TARGET_SCHED_ADJUST_PRIORITY
145 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
146 #undef TARGET_SCHED_ISSUE_RATE
147 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
149 #undef TARGET_OPTION_OVERRIDE
150 #define TARGET_OPTION_OVERRIDE m32r_option_override
152 #undef TARGET_ENCODE_SECTION_INFO
153 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
154 #undef TARGET_IN_SMALL_DATA_P
155 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
158 #undef TARGET_MEMORY_MOVE_COST
159 #define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
160 #undef TARGET_RTX_COSTS
161 #define TARGET_RTX_COSTS m32r_rtx_costs
162 #undef TARGET_ADDRESS_COST
163 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
165 #undef TARGET_PROMOTE_PROTOTYPES
166 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
167 #undef TARGET_RETURN_IN_MEMORY
168 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
170 #undef TARGET_FUNCTION_VALUE
171 #define TARGET_FUNCTION_VALUE m32r_function_value
172 #undef TARGET_LIBCALL_VALUE
173 #define TARGET_LIBCALL_VALUE m32r_libcall_value
174 #undef TARGET_FUNCTION_VALUE_REGNO_P
175 #define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
177 #undef TARGET_SETUP_INCOMING_VARARGS
178 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
179 #undef TARGET_MUST_PASS_IN_STACK
180 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
181 #undef TARGET_PASS_BY_REFERENCE
182 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
183 #undef TARGET_ARG_PARTIAL_BYTES
184 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
185 #undef TARGET_FUNCTION_ARG
186 #define TARGET_FUNCTION_ARG m32r_function_arg
187 #undef TARGET_FUNCTION_ARG_ADVANCE
188 #define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
190 #undef TARGET_CAN_ELIMINATE
191 #define TARGET_CAN_ELIMINATE m32r_can_eliminate
193 #undef TARGET_CONDITIONAL_REGISTER_USAGE
194 #define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
196 #undef TARGET_TRAMPOLINE_INIT
197 #define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
199 #undef TARGET_LEGITIMATE_CONSTANT_P
200 #define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* Called by m32r_option_override to initialize various things. */
211 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
212 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
213 m32r_punct_chars
['#'] = 1;
214 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
216 /* Provide default value if not specified. */
217 if (!global_options_set
.x_g_switch_value
)
218 g_switch_value
= SDATA_DEFAULT_SIZE
;
222 m32r_option_override (void)
224 /* These need to be done at start up.
225 It's convenient to do them here. */
227 SUBTARGET_OVERRIDE_OPTIONS
;
230 /* Vectors to keep interesting information about registers where it can easily
231 be got. We use to use the actual mode value as the bit number, but there
232 is (or may be) more than 32 modes now. Instead we use two tables: one
233 indexed by hard register number, and one indexed by mode. */
235 /* The purpose of m32r_mode_class is to shrink the range of modes so that
236 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
237 mapped into one m32r_mode_class mode. */
242 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
243 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
246 /* Modes for condition codes. */
247 #define C_MODES (1 << (int) C_MODE)
249 /* Modes for single-word and smaller quantities. */
250 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
252 /* Modes for double-word and smaller quantities. */
253 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
255 /* Modes for quad-word and smaller quantities. */
256 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
258 /* Modes for accumulators. */
259 #define A_MODES (1 << (int) A_MODE)
261 /* Value is 1 if register/mode pair is acceptable on arc. */
263 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
265 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
266 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
267 S_MODES
, C_MODES
, A_MODES
, A_MODES
270 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
272 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
275 init_reg_tables (void)
279 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
281 switch (GET_MODE_CLASS (i
))
284 case MODE_PARTIAL_INT
:
285 case MODE_COMPLEX_INT
:
286 if (GET_MODE_SIZE (i
) <= 4)
287 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
288 else if (GET_MODE_SIZE (i
) == 8)
289 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
290 else if (GET_MODE_SIZE (i
) == 16)
291 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
292 else if (GET_MODE_SIZE (i
) == 32)
293 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
295 m32r_mode_class
[i
] = 0;
298 case MODE_COMPLEX_FLOAT
:
299 if (GET_MODE_SIZE (i
) <= 4)
300 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
301 else if (GET_MODE_SIZE (i
) == 8)
302 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
303 else if (GET_MODE_SIZE (i
) == 16)
304 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
305 else if (GET_MODE_SIZE (i
) == 32)
306 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
308 m32r_mode_class
[i
] = 0;
311 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
314 m32r_mode_class
[i
] = 0;
319 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
322 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
323 else if (i
== ARG_POINTER_REGNUM
)
324 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
326 m32r_regno_reg_class
[i
] = NO_REGS
;
330 /* M32R specific attribute support.
332 interrupt - for interrupt functions
334 model - select code model used to access object
336 small: addresses use 24 bits, use bl to make calls
337 medium: addresses use 32 bits, use bl to make calls
338 large: addresses use 32 bits, use seth/add3/jl to make calls
340 Grep for MODEL in m32r.h for more info. */
342 static tree small_ident1
;
343 static tree small_ident2
;
344 static tree medium_ident1
;
345 static tree medium_ident2
;
346 static tree large_ident1
;
347 static tree large_ident2
;
352 if (small_ident1
== 0)
354 small_ident1
= get_identifier ("small");
355 small_ident2
= get_identifier ("__small__");
356 medium_ident1
= get_identifier ("medium");
357 medium_ident2
= get_identifier ("__medium__");
358 large_ident1
= get_identifier ("large");
359 large_ident2
= get_identifier ("__large__");
363 /* Handle an "model" attribute; arguments as in
364 struct attribute_spec.handler. */
366 m32r_handle_model_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
,
367 tree args
, int flags ATTRIBUTE_UNUSED
,
373 arg
= TREE_VALUE (args
);
375 if (arg
!= small_ident1
376 && arg
!= small_ident2
377 && arg
!= medium_ident1
378 && arg
!= medium_ident2
379 && arg
!= large_ident1
380 && arg
!= large_ident2
)
382 warning (OPT_Wattributes
, "invalid argument of %qs attribute",
383 IDENTIFIER_POINTER (name
));
384 *no_add_attrs
= true;
390 /* Encode section information of DECL, which is either a VAR_DECL,
391 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
393 For the M32R we want to record:
395 - whether the object lives in .sdata/.sbss.
396 - what code model should be used to access the object
400 m32r_encode_section_info (tree decl
, rtx rtl
, int first
)
404 enum m32r_model model
;
406 default_encode_section_info (decl
, rtl
, first
);
411 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
418 id
= TREE_VALUE (TREE_VALUE (model_attr
));
420 if (id
== small_ident1
|| id
== small_ident2
)
421 model
= M32R_MODEL_SMALL
;
422 else if (id
== medium_ident1
|| id
== medium_ident2
)
423 model
= M32R_MODEL_MEDIUM
;
424 else if (id
== large_ident1
|| id
== large_ident2
)
425 model
= M32R_MODEL_LARGE
;
427 gcc_unreachable (); /* shouldn't happen */
431 if (TARGET_MODEL_SMALL
)
432 model
= M32R_MODEL_SMALL
;
433 else if (TARGET_MODEL_MEDIUM
)
434 model
= M32R_MODEL_MEDIUM
;
435 else if (TARGET_MODEL_LARGE
)
436 model
= M32R_MODEL_LARGE
;
438 gcc_unreachable (); /* shouldn't happen */
440 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
443 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
446 /* Only mark the object as being small data area addressable if
447 it hasn't been explicitly marked with a code model.
449 The user can explicitly put an object in the small data area with the
450 section attribute. If the object is in sdata/sbss and marked with a
451 code model do both [put the object in .sdata and mark it as being
452 addressed with a specific code model - don't mark it as being addressed
453 with an SDA reloc though]. This is ok and might be useful at times. If
454 the object doesn't fit the linker will give an error. */
457 m32r_in_small_data_p (const_tree decl
)
461 if (TREE_CODE (decl
) != VAR_DECL
)
464 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
467 section
= DECL_SECTION_NAME (decl
);
470 const char *const name
= TREE_STRING_POINTER (section
);
471 if (strcmp (name
, ".sdata") == 0 || strcmp (name
, ".sbss") == 0)
476 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
478 int size
= int_size_in_bytes (TREE_TYPE (decl
));
480 if (size
> 0 && size
<= g_switch_value
)
488 /* Do anything needed before RTL is emitted for each function. */
491 m32r_init_expanders (void)
493 /* ??? At one point there was code here. The function is left in
494 to make it easy to experiment. */
498 call_operand (rtx op
, enum machine_mode mode
)
503 return call_address_operand (op
, mode
);
506 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
509 small_data_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
511 if (! TARGET_SDATA_USE
)
514 if (GET_CODE (op
) == SYMBOL_REF
)
515 return SYMBOL_REF_SMALL_P (op
);
517 if (GET_CODE (op
) == CONST
518 && GET_CODE (XEXP (op
, 0)) == PLUS
519 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
520 && satisfies_constraint_J (XEXP (XEXP (op
, 0), 1)))
521 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
526 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
529 addr24_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
536 if (GET_CODE (op
) == LABEL_REF
)
537 return TARGET_ADDR24
;
539 if (GET_CODE (op
) == SYMBOL_REF
)
541 else if (GET_CODE (op
) == CONST
542 && GET_CODE (XEXP (op
, 0)) == PLUS
543 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
544 && satisfies_constraint_M (XEXP (XEXP (op
, 0), 1)))
545 sym
= XEXP (XEXP (op
, 0), 0);
549 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
553 && (CONSTANT_POOL_ADDRESS_P (sym
)
554 || LIT_NAME_P (XSTR (sym
, 0))))
560 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
563 addr32_operand (rtx op
, enum machine_mode mode
)
567 if (GET_CODE (op
) == LABEL_REF
)
568 return TARGET_ADDR32
;
570 if (GET_CODE (op
) == SYMBOL_REF
)
572 else if (GET_CODE (op
) == CONST
573 && GET_CODE (XEXP (op
, 0)) == PLUS
574 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
575 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
577 sym
= XEXP (XEXP (op
, 0), 0);
581 return (! addr24_operand (sym
, mode
)
582 && ! small_data_operand (sym
, mode
));
585 /* Return 1 if OP is a function that can be called with the `bl' insn. */
588 call26_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
593 if (GET_CODE (op
) == SYMBOL_REF
)
594 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
596 return TARGET_CALL26
;
599 /* Return 1 if OP is a DImode const we want to handle inline.
600 This must match the code in the movdi pattern.
601 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
604 easy_di_const (rtx op
)
606 rtx high_rtx
, low_rtx
;
607 HOST_WIDE_INT high
, low
;
609 split_double (op
, &high_rtx
, &low_rtx
);
610 high
= INTVAL (high_rtx
);
611 low
= INTVAL (low_rtx
);
612 /* Pick constants loadable with 2 16-bit `ldi' insns. */
613 if (high
>= -128 && high
<= 127
614 && low
>= -128 && low
<= 127)
619 /* Return 1 if OP is a DFmode const we want to handle inline.
620 This must match the code in the movdf pattern.
621 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
624 easy_df_const (rtx op
)
629 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
630 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
631 if (l
[0] == 0 && l
[1] == 0)
633 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
638 /* Return 1 if OP is (mem (reg ...)).
639 This is used in insn length calcs. */
642 memreg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
644 return MEM_P (op
) && REG_P (XEXP (op
, 0));
647 /* Return nonzero if TYPE must be passed by indirect reference. */
650 m32r_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
651 enum machine_mode mode
, const_tree type
,
652 bool named ATTRIBUTE_UNUSED
)
657 size
= int_size_in_bytes (type
);
659 size
= GET_MODE_SIZE (mode
);
661 return (size
< 0 || size
> 8);
666 /* X and Y are two things to compare using CODE. Emit the compare insn and
667 return the rtx for compare [arg0 of the if_then_else].
668 If need_compare is true then the comparison insn must be generated, rather
669 than being subsumed into the following branch instruction. */
672 gen_compare (enum rtx_code code
, rtx x
, rtx y
, int need_compare
)
674 enum rtx_code compare_code
;
675 enum rtx_code branch_code
;
676 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
681 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
682 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
683 case LT
: compare_code
= LT
; branch_code
= NE
; break;
684 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
685 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
686 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
687 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
688 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
689 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
690 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
698 switch (compare_code
)
701 if (satisfies_constraint_P (y
) /* Reg equal to small const. */
704 rtx tmp
= gen_reg_rtx (SImode
);
706 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
710 else if (CONSTANT_P (y
)) /* Reg equal to const. */
712 rtx tmp
= force_reg (GET_MODE (x
), y
);
716 if (register_operand (y
, SImode
) /* Reg equal to reg. */
717 || y
== const0_rtx
) /* Reg equal to zero. */
719 emit_insn (gen_cmp_eqsi_insn (x
, y
));
721 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
726 if (register_operand (y
, SImode
)
727 || satisfies_constraint_P (y
))
729 rtx tmp
= gen_reg_rtx (SImode
); /* Reg compared to reg. */
734 emit_insn (gen_cmp_ltsi_insn (x
, y
));
741 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
742 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
747 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
749 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
750 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
754 emit_insn (gen_cmp_ltsi_insn (x
, y
));
761 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
766 if (register_operand (y
, SImode
)
767 || satisfies_constraint_P (y
))
769 rtx tmp
= gen_reg_rtx (SImode
); /* Reg (unsigned) compared to reg. */
774 emit_insn (gen_cmp_ltusi_insn (x
, y
));
781 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
782 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
787 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
789 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
790 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
794 emit_insn (gen_cmp_ltusi_insn (x
, y
));
801 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
811 /* Reg/reg equal comparison. */
812 if (compare_code
== EQ
813 && register_operand (y
, SImode
))
814 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
816 /* Reg/zero signed comparison. */
817 if ((compare_code
== EQ
|| compare_code
== LT
)
819 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
821 /* Reg/smallconst equal comparison. */
822 if (compare_code
== EQ
823 && satisfies_constraint_P (y
))
825 rtx tmp
= gen_reg_rtx (SImode
);
827 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
828 return gen_rtx_fmt_ee (code
, CCmode
, tmp
, const0_rtx
);
831 /* Reg/const equal comparison. */
832 if (compare_code
== EQ
835 rtx tmp
= force_reg (GET_MODE (x
), y
);
837 return gen_rtx_fmt_ee (code
, CCmode
, x
, tmp
);
844 y
= force_reg (GET_MODE (x
), y
);
847 int ok_const
= reg_or_int16_operand (y
, GET_MODE (y
));
850 y
= force_reg (GET_MODE (x
), y
);
854 switch (compare_code
)
857 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
860 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
863 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
870 return gen_rtx_fmt_ee (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
874 gen_cond_store (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
876 enum machine_mode mode
= GET_MODE (op0
);
878 gcc_assert (mode
== SImode
);
882 if (!register_operand (op1
, mode
))
883 op1
= force_reg (mode
, op1
);
885 if (TARGET_M32RX
|| TARGET_M32R2
)
887 if (!reg_or_zero_operand (op2
, mode
))
888 op2
= force_reg (mode
, op2
);
890 emit_insn (gen_seq_insn_m32rx (op0
, op1
, op2
));
893 if (CONST_INT_P (op2
) && INTVAL (op2
) == 0)
895 emit_insn (gen_seq_zero_insn (op0
, op1
));
899 if (!reg_or_eq_int16_operand (op2
, mode
))
900 op2
= force_reg (mode
, op2
);
902 emit_insn (gen_seq_insn (op0
, op1
, op2
));
906 if (!CONST_INT_P (op2
)
907 || (INTVAL (op2
) != 0 && satisfies_constraint_K (op2
)))
911 if (reload_completed
|| reload_in_progress
)
914 reg
= gen_reg_rtx (SImode
);
915 emit_insn (gen_xorsi3 (reg
, op1
, op2
));
918 if (!register_operand (op1
, mode
))
919 op1
= force_reg (mode
, op1
);
921 emit_insn (gen_sne_zero_insn (op0
, op1
));
936 if (!register_operand (op1
, mode
))
937 op1
= force_reg (mode
, op1
);
939 if (!reg_or_int16_operand (op2
, mode
))
940 op2
= force_reg (mode
, op2
);
942 emit_insn (gen_slt_insn (op0
, op1
, op2
));
955 if (!register_operand (op1
, mode
))
956 op1
= force_reg (mode
, op1
);
958 if (!reg_or_int16_operand (op2
, mode
))
959 op2
= force_reg (mode
, op2
);
961 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
966 if (!register_operand (op1
, mode
))
967 op1
= force_reg (mode
, op1
);
969 if (!reg_or_int16_operand (op2
, mode
))
970 op2
= force_reg (mode
, op2
);
973 emit_insn (gen_sge_insn (op0
, op1
, op2
));
975 emit_insn (gen_sgeu_insn (op0
, op1
, op2
));
980 if (!register_operand (op1
, mode
))
981 op1
= force_reg (mode
, op1
);
983 if (CONST_INT_P (op2
))
985 HOST_WIDE_INT value
= INTVAL (op2
);
986 if (value
>= 2147483647)
988 emit_move_insn (op0
, const1_rtx
);
992 op2
= GEN_INT (value
+ 1);
993 if (value
< -32768 || value
>= 32767)
994 op2
= force_reg (mode
, op2
);
997 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
999 emit_insn (gen_slt_insn (op0
, op1
, op2
));
1003 if (!register_operand (op2
, mode
))
1004 op2
= force_reg (mode
, op2
);
1007 emit_insn (gen_sleu_insn (op0
, op1
, op2
));
1009 emit_insn (gen_sle_insn (op0
, op1
, op2
));
1018 /* Split a 2 word move (DI or DF) into component parts. */
1021 gen_split_move_double (rtx operands
[])
1023 enum machine_mode mode
= GET_MODE (operands
[0]);
1024 rtx dest
= operands
[0];
1025 rtx src
= operands
[1];
1028 /* We might have (SUBREG (MEM)) here, so just get rid of the
1029 subregs to make this code simpler. It is safe to call
1030 alter_subreg any time after reload. */
1031 if (GET_CODE (dest
) == SUBREG
)
1032 alter_subreg (&dest
, true);
1033 if (GET_CODE (src
) == SUBREG
)
1034 alter_subreg (&src
, true);
1039 int dregno
= REGNO (dest
);
1044 int sregno
= REGNO (src
);
1046 int reverse
= (dregno
== sregno
+ 1);
1048 /* We normally copy the low-numbered register first. However, if
1049 the first register operand 0 is the same as the second register of
1050 operand 1, we must copy in the opposite order. */
1051 emit_insn (gen_rtx_SET (VOIDmode
,
1052 operand_subword (dest
, reverse
, TRUE
, mode
),
1053 operand_subword (src
, reverse
, TRUE
, mode
)));
1055 emit_insn (gen_rtx_SET (VOIDmode
,
1056 operand_subword (dest
, !reverse
, TRUE
, mode
),
1057 operand_subword (src
, !reverse
, TRUE
, mode
)));
1060 /* Reg = constant. */
1061 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
1064 split_double (src
, &words
[0], &words
[1]);
1065 emit_insn (gen_rtx_SET (VOIDmode
,
1066 operand_subword (dest
, 0, TRUE
, mode
),
1069 emit_insn (gen_rtx_SET (VOIDmode
,
1070 operand_subword (dest
, 1, TRUE
, mode
),
1075 else if (MEM_P (src
))
1077 /* If the high-address word is used in the address, we must load it
1078 last. Otherwise, load it first. */
1080 = (refers_to_regno_p (dregno
, dregno
+ 1, XEXP (src
, 0), 0) != 0);
1082 /* We used to optimize loads from single registers as
1086 if r3 were not used subsequently. However, the REG_NOTES aren't
1087 propagated correctly by the reload phase, and it can cause bad
1088 code to be generated. We could still try:
1090 ld r1,r3+; ld r2,r3; addi r3,-4
1092 which saves 2 bytes and doesn't force longword alignment. */
1093 emit_insn (gen_rtx_SET (VOIDmode
,
1094 operand_subword (dest
, reverse
, TRUE
, mode
),
1095 adjust_address (src
, SImode
,
1096 reverse
* UNITS_PER_WORD
)));
1098 emit_insn (gen_rtx_SET (VOIDmode
,
1099 operand_subword (dest
, !reverse
, TRUE
, mode
),
1100 adjust_address (src
, SImode
,
1101 !reverse
* UNITS_PER_WORD
)));
1108 /* We used to optimize loads from single registers as
1112 if r3 were not used subsequently. However, the REG_NOTES aren't
1113 propagated correctly by the reload phase, and it can cause bad
1114 code to be generated. We could still try:
1116 st r1,r3; st r2,+r3; addi r3,-4
1118 which saves 2 bytes and doesn't force longword alignment. */
1119 else if (MEM_P (dest
) && REG_P (src
))
1121 emit_insn (gen_rtx_SET (VOIDmode
,
1122 adjust_address (dest
, SImode
, 0),
1123 operand_subword (src
, 0, TRUE
, mode
)));
1125 emit_insn (gen_rtx_SET (VOIDmode
,
1126 adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1127 operand_subword (src
, 1, TRUE
, mode
)));
1140 m32r_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
1141 tree type
, bool named ATTRIBUTE_UNUSED
)
1143 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1147 (((mode
== BLKmode
&& type
)
1148 ? (unsigned int) int_size_in_bytes (type
)
1149 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1152 if (*cum
>= M32R_MAX_PARM_REGS
)
1154 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1155 words
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1159 return words
* UNITS_PER_WORD
;
1162 /* The ROUND_ADVANCE* macros are local to this file. */
1163 /* Round SIZE up to a word boundary. */
1164 #define ROUND_ADVANCE(SIZE) \
1165 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1167 /* Round arg MODE/TYPE up to the next word boundary. */
1168 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1169 ((MODE) == BLKmode \
1170 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1171 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1173 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1174 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1176 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1177 a reg. This includes arguments that have to be passed by reference as the
1178 pointer to them is passed in a reg if one is available (and that is what
1180 This macro is only used in this file. */
1181 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1182 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1184 /* Determine where to put an argument to a function.
1185 Value is zero to push the argument on the stack,
1186 or a hard register in which to store the argument.
1188 MODE is the argument's machine mode.
1189 TYPE is the data type of the argument (as a tree).
1190 This is null for libcalls where that information may
1192 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1193 the preceding args and about the function being called.
1194 NAMED is nonzero if this argument is a named parameter
1195 (otherwise it is an extra parameter matching an ellipsis). */
1196 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1197 and the rest are pushed. */
1200 m32r_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
1201 const_tree type ATTRIBUTE_UNUSED
,
1202 bool named ATTRIBUTE_UNUSED
)
1204 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1206 return (PASS_IN_REG_P (*cum
, mode
, type
)
1207 ? gen_rtx_REG (mode
, ROUND_ADVANCE_CUM (*cum
, mode
, type
))
1211 /* Update the data in CUM to advance over an argument
1212 of mode MODE and data type TYPE.
1213 (TYPE is null for libcalls where that information may not be available.) */
1216 m32r_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1217 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1219 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1221 *cum
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1222 + ROUND_ADVANCE_ARG (mode
, type
));
1225 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1228 m32r_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1230 cumulative_args_t dummy
= pack_cumulative_args (NULL
);
1232 return m32r_pass_by_reference (dummy
, TYPE_MODE (type
), type
, false);
1235 /* Worker function for TARGET_FUNCTION_VALUE. */
1238 m32r_function_value (const_tree valtype
,
1239 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1240 bool outgoing ATTRIBUTE_UNUSED
)
1242 return gen_rtx_REG (TYPE_MODE (valtype
), 0);
1245 /* Worker function for TARGET_LIBCALL_VALUE. */
1248 m32r_libcall_value (enum machine_mode mode
,
1249 const_rtx fun ATTRIBUTE_UNUSED
)
1251 return gen_rtx_REG (mode
, 0);
1254 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1256 ??? What about r1 in DI/DF values. */
1259 m32r_function_value_regno_p (const unsigned int regno
)
1261 return (regno
== 0);
1264 /* Do any needed setup for a variadic function. For the M32R, we must
1265 create a register parameter block, and then copy any anonymous arguments
1266 in registers to memory.
1268 CUM has not been updated for the last named argument which has type TYPE
1269 and mode MODE, and we rely on this fact. */
1272 m32r_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
1273 tree type
, int *pretend_size
, int no_rtl
)
1280 /* All BLKmode values are passed by reference. */
1281 gcc_assert (mode
!= BLKmode
);
1283 first_anon_arg
= (ROUND_ADVANCE_CUM (*get_cumulative_args (cum
), mode
, type
)
1284 + ROUND_ADVANCE_ARG (mode
, type
));
1286 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1288 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1289 int first_reg_offset
= first_anon_arg
;
1290 /* Size in words to "pretend" allocate. */
1291 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1294 regblock
= gen_frame_mem (BLKmode
,
1295 plus_constant (Pmode
, arg_pointer_rtx
,
1296 FIRST_PARM_OFFSET (0)));
1297 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1298 move_block_from_reg (first_reg_offset
, regblock
, size
);
1300 *pretend_size
= (size
* UNITS_PER_WORD
);
1305 /* Return true if INSN is real instruction bearing insn. */
1308 m32r_is_insn (rtx insn
)
1310 return (NONDEBUG_INSN_P (insn
)
1311 && GET_CODE (PATTERN (insn
)) != USE
1312 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
1315 /* Increase the priority of long instructions so that the
1316 short instructions are scheduled ahead of the long ones. */
1319 m32r_adjust_priority (rtx insn
, int priority
)
1321 if (m32r_is_insn (insn
)
1322 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1329 /* Indicate how many instructions can be issued at the same time.
1330 This is sort of a lie. The m32r can issue only 1 long insn at
1331 once, but it can issue 2 short insns. The default therefore is
1332 set at 2, but this can be overridden by the command line option
1336 m32r_issue_rate (void)
1338 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1341 /* Cost functions. */
1342 /* Memory is 3 times as expensive as registers.
1343 ??? Is that the right way to look at it? */
1346 m32r_memory_move_cost (enum machine_mode mode
,
1347 reg_class_t rclass ATTRIBUTE_UNUSED
,
1348 bool in ATTRIBUTE_UNUSED
)
1350 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
1357 m32r_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
,
1358 int opno ATTRIBUTE_UNUSED
, int *total
,
1359 bool speed ATTRIBUTE_UNUSED
)
1363 /* Small integers are as cheap as registers. 4 byte values can be
1364 fetched as immediate constants - let's give that the cost of an
1367 if (INT16_P (INTVAL (x
)))
1377 *total
= COSTS_N_INSNS (1);
1384 split_double (x
, &high
, &low
);
1385 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1386 + !INT16_P (INTVAL (low
)));
1391 *total
= COSTS_N_INSNS (3);
1398 *total
= COSTS_N_INSNS (10);
1406 /* Type of function DECL.
1408 The result is cached. To reset the cache at the end of a function,
1409 call with DECL = NULL_TREE. */
1411 enum m32r_function_type
1412 m32r_compute_function_type (tree decl
)
1415 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1416 /* Last function we were called for. */
1417 static tree last_fn
= NULL_TREE
;
1419 /* Resetting the cached value? */
1420 if (decl
== NULL_TREE
)
1422 fn_type
= M32R_FUNCTION_UNKNOWN
;
1423 last_fn
= NULL_TREE
;
1427 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1430 /* Compute function type. */
1431 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1432 ? M32R_FUNCTION_INTERRUPT
1433 : M32R_FUNCTION_NORMAL
);
1438 \f/* Function prologue/epilogue handlers. */
1440 /* M32R stack frames look like:
1442 Before call After call
1443 +-----------------------+ +-----------------------+
1445 high | local variables, | | local variables, |
1446 mem | reg save area, etc. | | reg save area, etc. |
1448 +-----------------------+ +-----------------------+
1450 | arguments on stack. | | arguments on stack. |
1452 SP+0->+-----------------------+ +-----------------------+
1453 | reg parm save area, |
1454 | only created for |
1455 | variable argument |
1457 +-----------------------+
1458 | previous frame ptr |
1459 +-----------------------+
1461 | register save area |
1463 +-----------------------+
1465 +-----------------------+
1469 +-----------------------+
1471 | alloca allocations |
1473 +-----------------------+
1475 low | arguments on stack |
1477 SP+0->+-----------------------+
1480 1) The "reg parm save area" does not exist for non variable argument fns.
1481 2) The "reg parm save area" can be eliminated completely if we saved regs
1482 containing anonymous args separately but that complicates things too
1483 much (so it's not done).
1484 3) The return address is saved after the register save area so as to have as
1485 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1487 /* Structure to be filled in by m32r_compute_frame_size with register
1488 save masks, and offsets for the current function. */
1489 struct m32r_frame_info
1491 unsigned int total_size
; /* # bytes that the entire frame takes up. */
1492 unsigned int extra_size
; /* # bytes of extra stuff. */
1493 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
1494 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
1495 unsigned int reg_size
; /* # bytes needed to store regs. */
1496 unsigned int var_size
; /* # bytes that variables take up. */
1497 unsigned int gmask
; /* Mask of saved gp registers. */
1498 unsigned int save_fp
; /* Nonzero if fp must be saved. */
1499 unsigned int save_lr
; /* Nonzero if lr (return addr) must be saved. */
1500 int initialized
; /* Nonzero if frame size already calculated. */
1503 /* Current frame information calculated by m32r_compute_frame_size. */
1504 static struct m32r_frame_info current_frame_info
;
1506 /* Zero structure to initialize current_frame_info. */
1507 static struct m32r_frame_info zero_frame_info
;
1509 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1510 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1512 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1513 The return address and frame pointer are treated separately.
1514 Don't consider them here. */
1515 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1516 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1517 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
1519 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1520 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1522 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1523 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1525 /* Return the bytes needed to compute the frame pointer from the current
1528 SIZE is the size needed for local variables. */
1531 m32r_compute_frame_size (int size
) /* # of var. bytes allocated. */
1534 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1535 unsigned int reg_size
;
1537 enum m32r_function_type fn_type
;
1539 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1542 var_size
= M32R_STACK_ALIGN (size
);
1543 args_size
= M32R_STACK_ALIGN (crtl
->outgoing_args_size
);
1544 pretend_size
= crtl
->args
.pretend_args_size
;
1545 extra_size
= FIRST_PARM_OFFSET (0);
1546 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1550 /* See if this is an interrupt handler. Call used registers must be saved
1552 fn_type
= m32r_compute_function_type (current_function_decl
);
1553 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1555 /* Calculate space needed for registers. */
1556 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1558 if (MUST_SAVE_REGISTER (regno
, interrupt_p
)
1559 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1561 reg_size
+= UNITS_PER_WORD
;
1562 gmask
|= 1 << regno
;
1566 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1567 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
|| pic_reg_used
;
1569 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1571 total_size
+= reg_size
;
1573 /* ??? Not sure this is necessary, and I don't think the epilogue
1574 handler will do the right thing if this changes total_size. */
1575 total_size
= M32R_STACK_ALIGN (total_size
);
1577 /* frame_size = total_size - (pretend_size + reg_size); */
1579 /* Save computed information. */
1580 current_frame_info
.total_size
= total_size
;
1581 current_frame_info
.extra_size
= extra_size
;
1582 current_frame_info
.pretend_size
= pretend_size
;
1583 current_frame_info
.var_size
= var_size
;
1584 current_frame_info
.args_size
= args_size
;
1585 current_frame_info
.reg_size
= reg_size
;
1586 current_frame_info
.gmask
= gmask
;
1587 current_frame_info
.initialized
= reload_completed
;
1589 /* Ok, we're done. */
1593 /* Worker function for TARGET_CAN_ELIMINATE. */
1596 m32r_can_eliminate (const int from
, const int to
)
1598 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
1599 ? ! frame_pointer_needed
1604 /* The table we use to reference PIC data. */
1605 static rtx global_offset_table
;
1608 m32r_reload_lr (rtx sp
, int size
)
1610 rtx lr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
1613 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, sp
)));
1614 else if (size
< 32768)
1615 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
,
1616 gen_rtx_PLUS (Pmode
, sp
,
1620 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1622 emit_insn (gen_movsi (tmp
, GEN_INT (size
)));
1623 emit_insn (gen_addsi3 (tmp
, tmp
, sp
));
1624 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, tmp
)));
1631 m32r_load_pic_register (void)
1633 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1634 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
1635 GEN_INT (TARGET_MODEL_SMALL
)));
1637 /* Need to emit this whether or not we obey regdecls,
1638 since setjmp/longjmp can cause life info to screw up. */
1639 emit_use (pic_offset_table_rtx
);
1642 /* Expand the m32r prologue as a series of insns. */
1645 m32r_expand_prologue (void)
1650 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1653 if (! current_frame_info
.initialized
)
1654 m32r_compute_frame_size (get_frame_size ());
1656 gmask
= current_frame_info
.gmask
;
1658 /* These cases shouldn't happen. Catch them now. */
1659 gcc_assert (current_frame_info
.total_size
|| !gmask
);
1661 /* Allocate space for register arguments if this is a variadic function. */
1662 if (current_frame_info
.pretend_size
!= 0)
1664 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1665 the wrong result on a 64-bit host. */
1666 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1667 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1669 GEN_INT (-pretend_size
)));
1672 /* Save any registers we need to and set up fp. */
1673 if (current_frame_info
.save_fp
)
1674 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1676 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1678 /* Save any needed call-saved regs (and call-used if this is an
1679 interrupt handler). */
1680 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1682 if ((gmask
& (1 << regno
)) != 0)
1683 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1684 gen_rtx_REG (Pmode
, regno
)));
1687 if (current_frame_info
.save_lr
)
1688 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1689 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1691 /* Allocate the stack frame. */
1692 frame_size
= (current_frame_info
.total_size
1693 - (current_frame_info
.pretend_size
1694 + current_frame_info
.reg_size
));
1696 if (frame_size
== 0)
1697 ; /* Nothing to do. */
1698 else if (frame_size
<= 32768)
1699 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1700 GEN_INT (-frame_size
)));
1703 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1705 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1706 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1709 if (frame_pointer_needed
)
1710 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1713 /* Push lr for mcount (form_pc, x). */
1714 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1715 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1719 m32r_load_pic_register ();
1720 m32r_reload_lr (stack_pointer_rtx
,
1721 (crtl
->profile
? 0 : frame_size
));
1724 if (crtl
->profile
&& !pic_reg_used
)
1725 emit_insn (gen_blockage ());
1729 /* Set up the stack and frame pointer (if desired) for the function.
1730 Note, if this is changed, you need to mirror the changes in
1731 m32r_compute_frame_size which calculates the prolog size. */
1734 m32r_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
1736 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1738 /* If this is an interrupt handler, mark it as such. */
1739 if (M32R_INTERRUPT_P (fn_type
))
1740 fprintf (file
, "\t%s interrupt handler\n", ASM_COMMENT_START
);
1742 if (! current_frame_info
.initialized
)
1743 m32r_compute_frame_size (size
);
1745 /* This is only for the human reader. */
1747 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1749 current_frame_info
.var_size
,
1750 current_frame_info
.reg_size
/ 4,
1751 current_frame_info
.args_size
,
1752 current_frame_info
.extra_size
);
1755 /* Output RTL to pop register REGNO from the stack. */
1762 x
= emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode
, regno
),
1763 stack_pointer_rtx
));
1764 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
1767 /* Expand the m32r epilogue as a series of insns. */
1770 m32r_expand_epilogue (void)
1773 int noepilogue
= FALSE
;
1776 gcc_assert (current_frame_info
.initialized
);
1777 total_size
= current_frame_info
.total_size
;
1779 if (total_size
== 0)
1781 rtx insn
= get_last_insn ();
1783 /* If the last insn was a BARRIER, we don't have to write any code
1784 because a jump (aka return) was put there. */
1785 if (insn
&& NOTE_P (insn
))
1786 insn
= prev_nonnote_insn (insn
);
1787 if (insn
&& BARRIER_P (insn
))
1793 unsigned int var_size
= current_frame_info
.var_size
;
1794 unsigned int args_size
= current_frame_info
.args_size
;
1795 unsigned int gmask
= current_frame_info
.gmask
;
1796 int can_trust_sp_p
= !cfun
->calls_alloca
;
1798 if (flag_exceptions
)
1799 emit_insn (gen_blockage ());
1801 /* The first thing to do is point the sp at the bottom of the register
1805 unsigned int reg_offset
= var_size
+ args_size
;
1807 if (reg_offset
== 0)
1808 ; /* Nothing to do. */
1809 else if (reg_offset
< 32768)
1810 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1811 GEN_INT (reg_offset
)));
1814 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1816 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1817 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1821 else if (frame_pointer_needed
)
1823 unsigned int reg_offset
= var_size
+ args_size
;
1825 if (reg_offset
== 0)
1826 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1827 else if (reg_offset
< 32768)
1828 emit_insn (gen_addsi3 (stack_pointer_rtx
, frame_pointer_rtx
,
1829 GEN_INT (reg_offset
)));
1832 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1834 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1835 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1836 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1843 if (current_frame_info
.save_lr
)
1844 pop (RETURN_ADDR_REGNUM
);
1846 /* Restore any saved registers, in reverse order of course. */
1847 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1848 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1850 if ((gmask
& (1L << regno
)) != 0)
1854 if (current_frame_info
.save_fp
)
1855 pop (FRAME_POINTER_REGNUM
);
1857 /* Remove varargs area if present. */
1858 if (current_frame_info
.pretend_size
!= 0)
1859 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1860 GEN_INT (current_frame_info
.pretend_size
)));
1862 emit_insn (gen_blockage ());
1866 /* Do any necessary cleanup after a function to restore stack, frame,
1870 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED
,
1871 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1873 /* Reset state info for each function. */
1874 current_frame_info
= zero_frame_info
;
1875 m32r_compute_function_type (NULL_TREE
);
1878 /* Return nonzero if this function is known to have a null or 1 instruction
1882 direct_return (void)
1884 if (!reload_completed
)
1887 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl
)))
1890 if (! current_frame_info
.initialized
)
1891 m32r_compute_frame_size (get_frame_size ());
1893 return current_frame_info
.total_size
== 0;
1900 m32r_legitimate_pic_operand_p (rtx x
)
1902 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1905 if (GET_CODE (x
) == CONST
1906 && GET_CODE (XEXP (x
, 0)) == PLUS
1907 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1908 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
1909 && (CONST_INT_P (XEXP (XEXP (x
, 0), 1))))
1916 m32r_legitimize_pic_address (rtx orig
, rtx reg
)
1919 printf("m32r_legitimize_pic_address()\n");
1922 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1924 rtx pic_ref
, address
;
1929 gcc_assert (!reload_in_progress
&& !reload_completed
);
1930 reg
= gen_reg_rtx (Pmode
);
1936 address
= gen_reg_rtx (Pmode
);
1940 crtl
->uses_pic_offset_table
= 1;
1942 if (GET_CODE (orig
) == LABEL_REF
1943 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
1945 emit_insn (gen_gotoff_load_addr (reg
, orig
));
1946 emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1950 emit_insn (gen_pic_load_addr (address
, orig
));
1952 emit_insn (gen_addsi3 (address
, address
, pic_offset_table_rtx
));
1953 pic_ref
= gen_const_mem (Pmode
, address
);
1954 emit_move_insn (reg
, pic_ref
);
1957 else if (GET_CODE (orig
) == CONST
)
1961 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1962 && XEXP (XEXP (orig
, 0), 1) == pic_offset_table_rtx
)
1967 gcc_assert (!reload_in_progress
&& !reload_completed
);
1968 reg
= gen_reg_rtx (Pmode
);
1971 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1973 base
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
1975 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), NULL_RTX
);
1977 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), reg
);
1982 if (CONST_INT_P (offset
))
1984 if (INT16_P (INTVAL (offset
)))
1985 return plus_constant (Pmode
, base
, INTVAL (offset
));
1988 gcc_assert (! reload_in_progress
&& ! reload_completed
);
1989 offset
= force_reg (Pmode
, offset
);
1993 return gen_rtx_PLUS (Pmode
, base
, offset
);
2000 m32r_legitimize_address (rtx x
, rtx orig_x ATTRIBUTE_UNUSED
,
2001 enum machine_mode mode ATTRIBUTE_UNUSED
)
2004 return m32r_legitimize_pic_address (x
, NULL_RTX
);
2009 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2012 m32r_mode_dependent_address_p (const_rtx addr
, addr_space_t as ATTRIBUTE_UNUSED
)
2014 if (GET_CODE (addr
) == LO_SUM
)
2020 /* Nested function support. */
2022 /* Emit RTL insns to initialize the variable parts of a trampoline.
2023 FNADDR is an RTX for the address of the function's pure code.
2024 CXT is an RTX for the static chain value for the function. */
2027 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED
,
2028 rtx fnaddr ATTRIBUTE_UNUSED
,
2029 rtx cxt ATTRIBUTE_UNUSED
)
2034 m32r_file_start (void)
2036 default_file_start ();
2038 if (flag_verbose_asm
)
2039 fprintf (asm_out_file
,
2040 "%s M32R/D special options: -G %d\n",
2041 ASM_COMMENT_START
, g_switch_value
);
2043 if (TARGET_LITTLE_ENDIAN
)
2044 fprintf (asm_out_file
, "\t.little\n");
2047 /* Print operand X (an rtx) in assembler syntax to file FILE.
2048 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2049 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2052 m32r_print_operand (FILE * file
, rtx x
, int code
)
2058 /* The 's' and 'p' codes are used by output_block_move() to
2059 indicate post-increment 's'tores and 'p're-increment loads. */
2062 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2064 output_operand_lossage ("invalid operand to %%s code");
2069 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2071 output_operand_lossage ("invalid operand to %%p code");
2075 /* Write second word of DImode or DFmode reference,
2076 register or memory. */
2078 fputs (reg_names
[REGNO (x
)+1], file
);
2081 fprintf (file
, "@(");
2082 /* Handle possible auto-increment. Since it is pre-increment and
2083 we have already done it, we can just use an offset of four. */
2084 /* ??? This is taken from rs6000.c I think. I don't think it is
2085 currently necessary, but keep it around. */
2086 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2087 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2088 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 4));
2090 output_address (plus_constant (Pmode
, XEXP (x
, 0), 4));
2094 output_operand_lossage ("invalid operand to %%R code");
2097 case 'H' : /* High word. */
2098 case 'L' : /* Low word. */
2101 /* L = least significant word, H = most significant word. */
2102 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2103 fputs (reg_names
[REGNO (x
)], file
);
2105 fputs (reg_names
[REGNO (x
)+1], file
);
2107 else if (CONST_INT_P (x
)
2108 || GET_CODE (x
) == CONST_DOUBLE
)
2112 split_double (x
, &first
, &second
);
2113 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2114 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2117 output_operand_lossage ("invalid operand to %%H/%%L code");
2124 if (GET_CODE (x
) != CONST_DOUBLE
2125 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2126 fatal_insn ("bad insn for 'A'", x
);
2128 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
2129 fprintf (file
, "%s", str
);
2133 case 'B' : /* Bottom half. */
2134 case 'T' : /* Top half. */
2135 /* Output the argument to a `seth' insn (sets the Top half-word).
2136 For constants output arguments to a seth/or3 pair to set Top and
2137 Bottom halves. For symbols output arguments to a seth/add3 pair to
2138 set Top and Bottom halves. The difference exists because for
2139 constants seth/or3 is more readable but for symbols we need to use
2140 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
2141 switch (GET_CODE (x
))
2148 split_double (x
, &first
, &second
);
2149 x
= WORDS_BIG_ENDIAN
? second
: first
;
2150 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2152 ? INTVAL (x
) & 0xffff
2153 : (INTVAL (x
) >> 16) & 0xffff));
2159 && small_data_operand (x
, VOIDmode
))
2161 fputs ("sda(", file
);
2162 output_addr_const (file
, x
);
2168 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2169 output_addr_const (file
, x
);
2173 output_operand_lossage ("invalid operand to %%T/%%B code");
2180 /* Output a load/store with update indicator if appropriate. */
2183 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2184 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2188 output_operand_lossage ("invalid operand to %%U code");
2192 /* Print a constant value negated. */
2193 if (CONST_INT_P (x
))
2194 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2196 output_operand_lossage ("invalid operand to %%N code");
2200 /* Print a const_int in hex. Used in comments. */
2201 if (CONST_INT_P (x
))
2202 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
2206 fputs (IMMEDIATE_PREFIX
, file
);
2210 /* Do nothing special. */
2215 output_operand_lossage ("invalid operand output code");
2218 switch (GET_CODE (x
))
2221 fputs (reg_names
[REGNO (x
)], file
);
2226 if (GET_CODE (addr
) == PRE_INC
)
2228 if (!REG_P (XEXP (addr
, 0)))
2229 fatal_insn ("pre-increment address is not a register", x
);
2231 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2233 else if (GET_CODE (addr
) == PRE_DEC
)
2235 if (!REG_P (XEXP (addr
, 0)))
2236 fatal_insn ("pre-decrement address is not a register", x
);
2238 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2240 else if (GET_CODE (addr
) == POST_INC
)
2242 if (!REG_P (XEXP (addr
, 0)))
2243 fatal_insn ("post-increment address is not a register", x
);
2245 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2250 output_address (XEXP (x
, 0));
2256 /* We handle SFmode constants here as output_addr_const doesn't. */
2257 if (GET_MODE (x
) == SFmode
)
2262 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2263 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
2264 fprintf (file
, "0x%08lx", l
);
2268 /* Fall through. Let output_addr_const deal with it. */
2271 output_addr_const (file
, x
);
2276 /* Print a memory address as an operand to reference that memory location. */
2279 m32r_print_operand_address (FILE * file
, rtx addr
)
2285 switch (GET_CODE (addr
))
2288 fputs (reg_names
[REGNO (addr
)], file
);
2292 if (CONST_INT_P (XEXP (addr
, 0)))
2293 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2294 else if (CONST_INT_P (XEXP (addr
, 1)))
2295 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2297 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2300 /* Print the offset first (if present) to conform to the manual. */
2304 fprintf (file
, "%d,", offset
);
2305 fputs (reg_names
[REGNO (base
)], file
);
2307 /* The chip doesn't support this, but left in for generality. */
2308 else if (REG_P (index
))
2309 fprintf (file
, "%s,%s",
2310 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2311 /* Not sure this can happen, but leave in for now. */
2312 else if (GET_CODE (index
) == SYMBOL_REF
)
2314 output_addr_const (file
, index
);
2316 fputs (reg_names
[REGNO (base
)], file
);
2319 fatal_insn ("bad address", addr
);
2321 else if (GET_CODE (base
) == LO_SUM
)
2323 gcc_assert (!index
&& REG_P (XEXP (base
, 0)));
2324 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2325 fputs ("sda(", file
);
2327 fputs ("low(", file
);
2328 output_addr_const (file
, plus_constant (Pmode
, XEXP (base
, 1),
2331 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2334 fatal_insn ("bad address", addr
);
2338 if (!REG_P (XEXP (addr
, 0)))
2339 fatal_insn ("lo_sum not of register", addr
);
2340 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2341 fputs ("sda(", file
);
2343 fputs ("low(", file
);
2344 output_addr_const (file
, XEXP (addr
, 1));
2346 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2349 case PRE_INC
: /* Assume SImode. */
2350 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2353 case PRE_DEC
: /* Assume SImode. */
2354 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2357 case POST_INC
: /* Assume SImode. */
2358 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2362 output_addr_const (file
, addr
);
2368 m32r_print_operand_punct_valid_p (unsigned char code
)
2370 return m32r_punct_chars
[code
];
2373 /* Return true if the operands are the constants 0 and 1. */
2376 zero_and_one (rtx operand1
, rtx operand2
)
2379 CONST_INT_P (operand1
)
2380 && CONST_INT_P (operand2
)
2381 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2382 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2385 /* Generate the correct assembler code to handle the conditional loading of a
2386 value into a register. It is known that the operands satisfy the
2387 conditional_move_operand() function above. The destination is operand[0].
2388 The condition is operand [1]. The 'true' value is operand [2] and the
2389 'false' value is operand [3]. */
2392 emit_cond_move (rtx
* operands
, rtx insn ATTRIBUTE_UNUSED
)
2394 static char buffer
[100];
2395 const char * dest
= reg_names
[REGNO (operands
[0])];
2399 /* Destination must be a register. */
2400 gcc_assert (REG_P (operands
[0]));
2401 gcc_assert (conditional_move_operand (operands
[2], SImode
));
2402 gcc_assert (conditional_move_operand (operands
[3], SImode
));
2404 /* Check to see if the test is reversed. */
2405 if (GET_CODE (operands
[1]) == NE
)
2407 rtx tmp
= operands
[2];
2408 operands
[2] = operands
[3];
2412 sprintf (buffer
, "mvfc %s, cbr", dest
);
2414 /* If the true value was '0' then we need to invert the results of the move. */
2415 if (INTVAL (operands
[2]) == 0)
2416 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2422 /* Returns true if the registers contained in the two
2423 rtl expressions are different. */
2426 m32r_not_same_reg (rtx a
, rtx b
)
2431 while (GET_CODE (a
) == SUBREG
)
2437 while (GET_CODE (b
) == SUBREG
)
2443 return reg_a
!= reg_b
;
2448 m32r_function_symbol (const char *name
)
2450 int extra_flags
= 0;
2451 enum m32r_model model
;
2452 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
2454 if (TARGET_MODEL_SMALL
)
2455 model
= M32R_MODEL_SMALL
;
2456 else if (TARGET_MODEL_MEDIUM
)
2457 model
= M32R_MODEL_MEDIUM
;
2458 else if (TARGET_MODEL_LARGE
)
2459 model
= M32R_MODEL_LARGE
;
2461 gcc_unreachable (); /* Shouldn't happen. */
2462 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
2465 SYMBOL_REF_FLAGS (sym
) |= extra_flags
;
2470 /* Use a library function to move some bytes. */
2473 block_move_call (rtx dest_reg
, rtx src_reg
, rtx bytes_rtx
)
2475 /* We want to pass the size as Pmode, which will normally be SImode
2476 but will be DImode if we are using 64-bit longs and pointers. */
2477 if (GET_MODE (bytes_rtx
) != VOIDmode
2478 && GET_MODE (bytes_rtx
) != Pmode
)
2479 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2481 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL
,
2482 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2483 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2484 TYPE_UNSIGNED (sizetype
)),
2485 TYPE_MODE (sizetype
));
2488 /* Expand string/block move operations.
2490 operands[0] is the pointer to the destination.
2491 operands[1] is the pointer to the source.
2492 operands[2] is the number of bytes to move.
2493 operands[3] is the alignment.
2495 Returns 1 upon success, 0 otherwise. */
2498 m32r_expand_block_move (rtx operands
[])
2500 rtx orig_dst
= operands
[0];
2501 rtx orig_src
= operands
[1];
2502 rtx bytes_rtx
= operands
[2];
2503 rtx align_rtx
= operands
[3];
2504 int constp
= CONST_INT_P (bytes_rtx
);
2505 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2506 int align
= INTVAL (align_rtx
);
2511 if (constp
&& bytes
<= 0)
2514 /* Move the address into scratch registers. */
2515 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2516 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2518 if (align
> UNITS_PER_WORD
)
2519 align
= UNITS_PER_WORD
;
2521 /* If we prefer size over speed, always use a function call.
2522 If we do not know the size, use a function call.
2523 If the blocks are not word aligned, use a function call. */
2524 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2526 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2530 leftover
= bytes
% MAX_MOVE_BYTES
;
2533 /* If necessary, generate a loop to handle the bulk of the copy. */
2536 rtx label
= NULL_RTX
;
2537 rtx final_src
= NULL_RTX
;
2538 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2539 rtx rounded_total
= GEN_INT (bytes
);
2540 rtx new_dst_reg
= gen_reg_rtx (SImode
);
2541 rtx new_src_reg
= gen_reg_rtx (SImode
);
2543 /* If we are going to have to perform this loop more than
2544 once, then generate a label and compute the address the
2545 source register will contain upon completion of the final
2547 if (bytes
> MAX_MOVE_BYTES
)
2549 final_src
= gen_reg_rtx (Pmode
);
2552 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2555 emit_insn (gen_movsi (final_src
, rounded_total
));
2556 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2559 label
= gen_label_rtx ();
2563 /* It is known that output_block_move() will update src_reg to point
2564 to the word after the end of the source block, and dst_reg to point
2565 to the last word of the destination block, provided that the block
2566 is MAX_MOVE_BYTES long. */
2567 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, at_a_time
,
2568 new_dst_reg
, new_src_reg
));
2569 emit_move_insn (dst_reg
, new_dst_reg
);
2570 emit_move_insn (src_reg
, new_src_reg
);
2571 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2573 if (bytes
> MAX_MOVE_BYTES
)
2575 rtx test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
2576 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
2581 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
),
2582 gen_reg_rtx (SImode
),
2583 gen_reg_rtx (SImode
)));
2588 /* Emit load/stores for a small constant word aligned block_move.
2590 operands[0] is the memory address of the destination.
2591 operands[1] is the memory address of the source.
2592 operands[2] is the number of bytes to move.
2593 operands[3] is a temp register.
2594 operands[4] is a temp register. */
2597 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
2599 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2603 gcc_assert (bytes
>= 1 && bytes
<= MAX_MOVE_BYTES
);
2605 /* We do not have a post-increment store available, so the first set of
2606 stores are done without any increment, then the remaining ones can use
2607 the pre-increment addressing mode.
2609 Note: expand_block_move() also relies upon this behavior when building
2610 loops to copy large blocks. */
2619 output_asm_insn ("ld\t%5, %p1", operands
);
2620 output_asm_insn ("ld\t%6, %p1", operands
);
2621 output_asm_insn ("st\t%5, @%0", operands
);
2622 output_asm_insn ("st\t%6, %s0", operands
);
2626 output_asm_insn ("ld\t%5, %p1", operands
);
2627 output_asm_insn ("ld\t%6, %p1", operands
);
2628 output_asm_insn ("st\t%5, %s0", operands
);
2629 output_asm_insn ("st\t%6, %s0", operands
);
2634 else if (bytes
>= 4)
2639 output_asm_insn ("ld\t%5, %p1", operands
);
2642 output_asm_insn ("ld\t%6, %p1", operands
);
2645 output_asm_insn ("st\t%5, @%0", operands
);
2647 output_asm_insn ("st\t%5, %s0", operands
);
2653 /* Get the entire next word, even though we do not want all of it.
2654 The saves us from doing several smaller loads, and we assume that
2655 we cannot cause a page fault when at least part of the word is in
2656 valid memory [since we don't get called if things aren't properly
2658 int dst_offset
= first_time
? 0 : 4;
2659 /* The amount of increment we have to make to the
2660 destination pointer. */
2661 int dst_inc_amount
= dst_offset
+ bytes
- 4;
2662 /* The same for the source pointer. */
2663 int src_inc_amount
= bytes
;
2667 /* If got_extra is true then we have already loaded
2668 the next word as part of loading and storing the previous word. */
2670 output_asm_insn ("ld\t%6, @%1", operands
);
2676 output_asm_insn ("sra3\t%5, %6, #16", operands
);
2677 my_operands
[0] = operands
[5];
2678 my_operands
[1] = GEN_INT (dst_offset
);
2679 my_operands
[2] = operands
[0];
2680 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2682 /* If there is a byte left to store then increment the
2683 destination address and shift the contents of the source
2684 register down by 8 bits. We could not do the address
2685 increment in the store half word instruction, because it does
2686 not have an auto increment mode. */
2687 if (bytes
> 0) /* assert (bytes == 1) */
2698 my_operands
[0] = operands
[6];
2699 my_operands
[1] = GEN_INT (last_shift
);
2700 output_asm_insn ("srai\t%0, #%1", my_operands
);
2701 my_operands
[0] = operands
[6];
2702 my_operands
[1] = GEN_INT (dst_offset
);
2703 my_operands
[2] = operands
[0];
2704 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2707 /* Update the destination pointer if needed. We have to do
2708 this so that the patterns matches what we output in this
2711 && !find_reg_note (insn
, REG_UNUSED
, operands
[0]))
2713 my_operands
[0] = operands
[0];
2714 my_operands
[1] = GEN_INT (dst_inc_amount
);
2715 output_asm_insn ("addi\t%0, #%1", my_operands
);
2718 /* Update the source pointer if needed. We have to do this
2719 so that the patterns matches what we output in this
2722 && !find_reg_note (insn
, REG_UNUSED
, operands
[1]))
2724 my_operands
[0] = operands
[1];
2725 my_operands
[1] = GEN_INT (src_inc_amount
);
2726 output_asm_insn ("addi\t%0, #%1", my_operands
);
2736 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2739 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
2740 unsigned int new_reg
)
2742 /* Interrupt routines can't clobber any register that isn't already used. */
2743 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2744 && !df_regs_ever_live_p (new_reg
))
2751 m32r_return_addr (int count
)
2756 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
2760 m32r_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2762 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
2763 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2764 0x017e8e17 : 0x178e7e01, SImode
));
2765 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
2766 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2767 0x0c00ae86 : 0x86ae000c, SImode
));
2768 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
2769 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2770 0xe627871e : 0x1e8727e6, SImode
));
2771 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
2772 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2773 0xc616c626 : 0x26c61fc6, SImode
));
2774 emit_move_insn (adjust_address (m_tramp
, SImode
, 16),
2776 emit_move_insn (adjust_address (m_tramp
, SImode
, 20),
2777 XEXP (DECL_RTL (fndecl
), 0));
2779 if (m32r_cache_flush_trap
>= 0)
2780 emit_insn (gen_flush_icache
2781 (validize_mem (adjust_address (m_tramp
, SImode
, 0)),
2782 gen_int_mode (m32r_cache_flush_trap
, SImode
)));
2783 else if (m32r_cache_flush_func
&& m32r_cache_flush_func
[0])
2784 emit_library_call (m32r_function_symbol (m32r_cache_flush_func
),
2785 LCT_NORMAL
, VOIDmode
, 3, XEXP (m_tramp
, 0), Pmode
,
2786 gen_int_mode (TRAMPOLINE_SIZE
, SImode
), SImode
,
2787 GEN_INT (3), SImode
);
2790 /* True if X is a reg that can be used as a base reg. */
2793 m32r_rtx_ok_for_base_p (const_rtx x
, bool strict
)
2800 if (GPR_P (REGNO (x
)))
2805 if (GPR_P (REGNO (x
))
2806 || REGNO (x
) == ARG_POINTER_REGNUM
2807 || ! HARD_REGISTER_P (x
))
2815 m32r_rtx_ok_for_offset_p (const_rtx x
)
2817 return (CONST_INT_P (x
) && INT16_P (INTVAL (x
)));
2821 m32r_legitimate_offset_addres_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2822 const_rtx x
, bool strict
)
2824 if (GET_CODE (x
) == PLUS
2825 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2826 && m32r_rtx_ok_for_offset_p (XEXP (x
, 1)))
2832 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2833 since more than one instruction will be required. */
2836 m32r_legitimate_lo_sum_addres_p (enum machine_mode mode
, const_rtx x
,
2839 if (GET_CODE (x
) == LO_SUM
2840 && (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2841 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2842 && CONSTANT_P (XEXP (x
, 1)))
2848 /* Is this a load and increment operation. */
2851 m32r_load_postinc_p (enum machine_mode mode
, const_rtx x
, bool strict
)
2853 if ((mode
== SImode
|| mode
== SFmode
)
2854 && GET_CODE (x
) == POST_INC
2855 && REG_P (XEXP (x
, 0))
2856 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2862 /* Is this an increment/decrement and store operation. */
2865 m32r_store_preinc_predec_p (enum machine_mode mode
, const_rtx x
, bool strict
)
2867 if ((mode
== SImode
|| mode
== SFmode
)
2868 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
2869 && REG_P (XEXP (x
, 0)) \
2870 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2876 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2879 m32r_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
2881 if (m32r_rtx_ok_for_base_p (x
, strict
)
2882 || m32r_legitimate_offset_addres_p (mode
, x
, strict
)
2883 || m32r_legitimate_lo_sum_addres_p (mode
, x
, strict
)
2884 || m32r_load_postinc_p (mode
, x
, strict
)
2885 || m32r_store_preinc_predec_p (mode
, x
, strict
))
2892 m32r_conditional_register_usage (void)
2896 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2897 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2901 /* Implement TARGET_LEGITIMATE_CONSTANT_P
2903 We don't allow (plus symbol large-constant) as the relocations can't
2904 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
2905 We allow all CONST_DOUBLE's as the md file patterns will force the
2906 constant to memory if they can't handle them. */
2909 m32r_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2911 return !(GET_CODE (x
) == CONST
2912 && GET_CODE (XEXP (x
, 0)) == PLUS
2913 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2914 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
2915 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
2916 && UINTVAL (XEXP (XEXP (x
, 0), 1)) > 32767);