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Reverting merge from trunk
[official-gcc.git] / gcc / config / ia64 / ia64.h
blobae9027c82d5ff547c27e128c09da25671b4c6b5f
1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* ??? Look at ABI group documents for list of preprocessor macros and
23 other features required for ABI compliance. */
24
25 /* ??? Functions containing a non-local goto target save many registers. Why?
26 See for instance execute/920428-2.c. */
27
28 \f
29 /* Run-time target specifications */
30
31 /* Target CPU builtins. */
32 #define TARGET_CPU_CPP_BUILTINS() \
33 do { \
34 builtin_assert("cpu=ia64"); \
35 builtin_assert("machine=ia64"); \
36 builtin_define("__ia64"); \
37 builtin_define("__ia64__"); \
38 builtin_define("__itanium__"); \
39 if (TARGET_BIG_ENDIAN) \
40 builtin_define("__BIG_ENDIAN__"); \
41 } while (0)
42
43 #ifndef SUBTARGET_EXTRA_SPECS
44 #define SUBTARGET_EXTRA_SPECS
45 #endif
46
47 #define EXTRA_SPECS \
48 { "asm_extra", ASM_EXTRA_SPEC }, \
49 SUBTARGET_EXTRA_SPECS
50
51 #define CC1_SPEC "%(cc1_cpu) "
52
53 #define ASM_EXTRA_SPEC ""
54
55 /* Variables which are this size or smaller are put in the sdata/sbss
56 sections. */
57 extern unsigned int ia64_section_threshold;
58
59 /* If the assembler supports thread-local storage, assume that the
60 system does as well. If a particular target system has an
61 assembler that supports TLS -- but the rest of the system does not
62 support TLS -- that system should explicit define TARGET_HAVE_TLS
63 to false in its own configuration file. */
64 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
65 #define TARGET_HAVE_TLS true
66 #endif
67
68 #define TARGET_TLS14 (ia64_tls_size == 14)
69 #define TARGET_TLS22 (ia64_tls_size == 22)
70 #define TARGET_TLS64 (ia64_tls_size == 64)
71
72 #define TARGET_HPUX 0
73 #define TARGET_HPUX_LD 0
74
75 #define TARGET_ABI_OPEN_VMS 0
76
77 #ifndef TARGET_ILP32
78 #define TARGET_ILP32 0
79 #endif
80
81 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
82 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
83 #endif
84
85 /* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and
86 TARGET_INLINE_SQRT. */
87
88 enum ia64_inline_type
89 {
90 INL_NO = 0,
91 INL_MIN_LAT = 1,
92 INL_MAX_THR = 2
93 };
94
95 /* Default target_flags if no switches are specified */
96
97 #ifndef TARGET_DEFAULT
98 #define TARGET_DEFAULT (MASK_DWARF2_ASM)
99 #endif
100
101 #ifndef TARGET_CPU_DEFAULT
102 #define TARGET_CPU_DEFAULT 0
103 #endif
104 \f
105 /* Driver configuration */
106
107 /* A C string constant that tells the GCC driver program options to pass to
108 `cc1'. It can also specify how to translate options you give to GCC into
109 options for GCC to pass to the `cc1'. */
110
111 #undef CC1_SPEC
112 #define CC1_SPEC "%{G*}"
113
114 /* A C string constant that tells the GCC driver program options to pass to
115 `cc1plus'. It can also specify how to translate options you give to GCC
116 into options for GCC to pass to the `cc1plus'. */
117
118 /* #define CC1PLUS_SPEC "" */
119 \f
120 /* Storage Layout */
121
122 /* Define this macro to have the value 1 if the most significant bit in a byte
123 has the lowest number; otherwise define it to have the value zero. */
124
125 #define BITS_BIG_ENDIAN 0
126
127 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
128
129 /* Define this macro to have the value 1 if, in a multiword object, the most
130 significant word has the lowest number. */
131
132 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
133
134 #define UNITS_PER_WORD 8
135
136 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
137
138 /* A C expression whose value is zero if pointers that need to be extended
139 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
140 they are zero-extended and negative one if there is a ptr_extend operation.
141
142 You need not define this macro if the `POINTER_SIZE' is equal to the width
143 of `Pmode'. */
144 /* Need this for 32-bit pointers, see hpux.h for setting it. */
145 /* #define POINTERS_EXTEND_UNSIGNED */
146
147 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
148 which has the specified mode and signedness is to be stored in a register.
149 This macro is only called when TYPE is a scalar type. */
150 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
151 do \
152 { \
153 if (GET_MODE_CLASS (MODE) == MODE_INT \
154 && GET_MODE_SIZE (MODE) < 4) \
155 (MODE) = SImode; \
156 } \
157 while (0)
158
159 #define PARM_BOUNDARY 64
160
161 /* Define this macro if you wish to preserve a certain alignment for the stack
162 pointer. The definition is a C expression for the desired alignment
163 (measured in bits). */
164
165 #define STACK_BOUNDARY 128
166
167 /* Align frames on double word boundaries */
168 #ifndef IA64_STACK_ALIGN
169 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
170 #endif
171
172 #define FUNCTION_BOUNDARY 128
173
174 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
175 128-bit integers all require 128-bit alignment. */
176 #define BIGGEST_ALIGNMENT 128
177
178 /* If defined, a C expression to compute the alignment for a static variable.
179 TYPE is the data type, and ALIGN is the alignment that the object
180 would ordinarily have. The value of this macro is used instead of that
181 alignment to align the object. */
182
183 #define DATA_ALIGNMENT(TYPE, ALIGN) \
184 (TREE_CODE (TYPE) == ARRAY_TYPE \
185 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
186 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
187
188 /* If defined, a C expression to compute the alignment given to a constant that
189 is being placed in memory. CONSTANT is the constant and ALIGN is the
190 alignment that the object would ordinarily have. The value of this macro is
191 used instead of that alignment to align the object. */
192
193 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
194 (TREE_CODE (EXP) == STRING_CST \
195 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
196
197 #define STRICT_ALIGNMENT 1
198
199 /* Define this if you wish to imitate the way many other C compilers handle
200 alignment of bitfields and the structures that contain them.
201 The behavior is that the type written for a bit-field (`int', `short', or
202 other integer type) imposes an alignment for the entire structure, as if the
203 structure really did contain an ordinary field of that type. In addition,
204 the bit-field is placed within the structure so that it would fit within such
205 a field, not crossing a boundary for it. */
206 #define PCC_BITFIELD_TYPE_MATTERS 1
207
208 /* An integer expression for the size in bits of the largest integer machine
209 mode that should actually be used. */
210
211 /* Allow pairs of registers to be used, which is the intent of the default. */
212 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
213
214 /* By default, the C++ compiler will use function addresses in the
215 vtable entries. Setting this nonzero tells the compiler to use
216 function descriptors instead. The value of this macro says how
217 many words wide the descriptor is (normally 2). It is assumed
218 that the address of a function descriptor may be treated as a
219 pointer to a function.
220
221 For reasons known only to HP, the vtable entries (as opposed to
222 normal function descriptors) are 16 bytes wide in 32-bit mode as
223 well, even though the 3rd and 4th words are unused. */
224 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
225
226 /* Due to silliness in the HPUX linker, vtable entries must be
227 8-byte aligned even in 32-bit mode. Rather than create multiple
228 ABIs, force this restriction on everyone else too. */
229 #define TARGET_VTABLE_ENTRY_ALIGN 64
230
231 /* Due to the above, we need extra padding for the data entries below 0
232 to retain the alignment of the descriptors. */
233 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
234 \f
235 /* Layout of Source Language Data Types */
236
237 #define INT_TYPE_SIZE 32
238
239 #define SHORT_TYPE_SIZE 16
240
241 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
242
243 #define LONG_LONG_TYPE_SIZE 64
244
245 #define FLOAT_TYPE_SIZE 32
246
247 #define DOUBLE_TYPE_SIZE 64
248
249 /* long double is XFmode normally, and TFmode for HPUX. It should be
250 TFmode for VMS as well but we only support up to DFmode now. */
251 #define LONG_DOUBLE_TYPE_SIZE \
252 (TARGET_HPUX ? 128 \
253 : TARGET_ABI_OPEN_VMS ? 64 \
254 : 80)
255
256 /* We always want the XFmode operations from libgcc2.c, except on VMS
257 where this yields references to unimplemented "insns". */
258 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE (TARGET_ABI_OPEN_VMS ? 64 : 80)
259
260
261 /* On HP-UX, we use the l suffix for TFmode in libgcc2.c. */
262 #define LIBGCC2_TF_CEXT l
263
264 #define DEFAULT_SIGNED_CHAR 1
265
266 /* A C expression for a string describing the name of the data type to use for
267 size values. The typedef name `size_t' is defined using the contents of the
268 string. */
269 /* ??? Needs to be defined for P64 code. */
270 /* #define SIZE_TYPE */
271
272 /* A C expression for a string describing the name of the data type to use for
273 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
274 defined using the contents of the string. See `SIZE_TYPE' above for more
275 information. */
276 /* ??? Needs to be defined for P64 code. */
277 /* #define PTRDIFF_TYPE */
278
279 /* A C expression for a string describing the name of the data type to use for
280 wide characters. The typedef name `wchar_t' is defined using the contents
281 of the string. See `SIZE_TYPE' above for more information. */
282 /* #define WCHAR_TYPE */
283
284 /* A C expression for the size in bits of the data type for wide characters.
285 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
286 /* #define WCHAR_TYPE_SIZE */
287
288 \f
289 /* Register Basics */
290
291 /* Number of hardware registers known to the compiler.
292 We have 128 general registers, 128 floating point registers,
293 64 predicate registers, 8 branch registers, one frame pointer,
294 and several "application" registers. */
295
296 #define FIRST_PSEUDO_REGISTER 334
297
298 /* Ranges for the various kinds of registers. */
299 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
300 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
301 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
302 #define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159)
303 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
304 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
305 #define GENERAL_REGNO_P(REGNO) \
306 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
307
308 #define GR_REG(REGNO) ((REGNO) + 0)
309 #define FR_REG(REGNO) ((REGNO) + 128)
310 #define PR_REG(REGNO) ((REGNO) + 256)
311 #define BR_REG(REGNO) ((REGNO) + 320)
312 #define OUT_REG(REGNO) ((REGNO) + 120)
313 #define IN_REG(REGNO) ((REGNO) + 112)
314 #define LOC_REG(REGNO) ((REGNO) + 32)
315
316 #define AR_CCV_REGNUM 329
317 #define AR_UNAT_REGNUM 330
318 #define AR_PFS_REGNUM 331
319 #define AR_LC_REGNUM 332
320 #define AR_EC_REGNUM 333
321
322 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
323 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
324 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
325
326 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
327 || (REGNO) == AR_UNAT_REGNUM)
328 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
329 && (REGNO) < FIRST_PSEUDO_REGISTER)
330 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
331 && (REGNO) < FIRST_PSEUDO_REGISTER)
332
333
334 /* ??? Don't really need two sets of macros. I like this one better because
335 it is less typing. */
336 #define R_GR(REGNO) GR_REG (REGNO)
337 #define R_FR(REGNO) FR_REG (REGNO)
338 #define R_PR(REGNO) PR_REG (REGNO)
339 #define R_BR(REGNO) BR_REG (REGNO)
340
341 /* An initializer that says which registers are used for fixed purposes all
342 throughout the compiled code and are therefore not available for general
343 allocation.
344
345 r0: constant 0
346 r1: global pointer (gp)
347 r12: stack pointer (sp)
348 r13: thread pointer (tp)
349 f0: constant 0.0
350 f1: constant 1.0
351 p0: constant true
352 fp: eliminable frame pointer */
353
354 /* The last 16 stacked regs are reserved for the 8 input and 8 output
355 registers. */
356
357 #define FIXED_REGISTERS \
358 { /* General registers. */ \
359 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
360 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
361 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
363 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
364 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
365 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
366 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
367 /* Floating-point registers. */ \
368 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
369 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
370 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
371 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
372 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
373 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
374 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
375 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
376 /* Predicate registers. */ \
377 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
378 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
379 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
380 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
381 /* Branch registers. */ \
382 0, 0, 0, 0, 0, 0, 0, 0, \
383 /*FP CCV UNAT PFS LC EC */ \
384 1, 1, 1, 1, 1, 1 \
385 }
386
387 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
388 (in general) by function calls as well as for fixed registers. This
389 macro therefore identifies the registers that are not available for
390 general allocation of values that must live across function calls. */
391
392 #define CALL_USED_REGISTERS \
393 { /* General registers. */ \
394 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
395 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
396 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
397 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
398 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
399 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
400 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
401 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
402 /* Floating-point registers. */ \
403 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
404 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
405 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
407 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
408 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
409 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
410 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
411 /* Predicate registers. */ \
412 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
413 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
414 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
415 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
416 /* Branch registers. */ \
417 1, 0, 0, 0, 0, 0, 1, 1, \
418 /*FP CCV UNAT PFS LC EC */ \
419 1, 1, 1, 1, 1, 1 \
420 }
421
422 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
423 problem which makes CALL_USED_REGISTERS *always* include
424 all the FIXED_REGISTERS. Until this problem has been
425 resolved this macro can be used to overcome this situation.
426 In particular, block_propagate() requires this list
427 be accurate, or we can remove registers which should be live.
428 This macro is used in regs_invalidated_by_call. */
429
430 #define CALL_REALLY_USED_REGISTERS \
431 { /* General registers. */ \
432 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, \
433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
434 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
436 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
437 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
438 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
439 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
440 /* Floating-point registers. */ \
441 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
442 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
443 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
444 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
445 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
446 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
447 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
448 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
449 /* Predicate registers. */ \
450 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
454 /* Branch registers. */ \
455 1, 0, 0, 0, 0, 0, 1, 1, \
456 /*FP CCV UNAT PFS LC EC */ \
457 0, 1, 0, 1, 0, 0 \
458 }
459
460
461 /* Define this macro if the target machine has register windows. This C
462 expression returns the register number as seen by the called function
463 corresponding to the register number OUT as seen by the calling function.
464 Return OUT if register number OUT is not an outbound register. */
465
466 #define INCOMING_REGNO(OUT) \
467 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
468
469 /* Define this macro if the target machine has register windows. This C
470 expression returns the register number as seen by the calling function
471 corresponding to the register number IN as seen by the called function.
472 Return IN if register number IN is not an inbound register. */
473
474 #define OUTGOING_REGNO(IN) \
475 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
476
477 /* Define this macro if the target machine has register windows. This
478 C expression returns true if the register is call-saved but is in the
479 register window. */
480
481 #define LOCAL_REGNO(REGNO) \
482 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
483
484 /* We define CCImode in ia64-modes.def so we need a selector. */
485
486 #define SELECT_CC_MODE(OP,X,Y) CCmode
487 \f
488 /* Order of allocation of registers */
489
490 /* If defined, an initializer for a vector of integers, containing the numbers
491 of hard registers in the order in which GCC should prefer to use them
492 (from most preferred to least).
493
494 If this macro is not defined, registers are used lowest numbered first (all
495 else being equal).
496
497 One use of this macro is on machines where the highest numbered registers
498 must always be saved and the save-multiple-registers instruction supports
499 only sequences of consecutive registers. On such machines, define
500 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
501 allocatable register first. */
502
503 /* ??? Should the GR return value registers come before or after the rest
504 of the caller-save GRs? */
505
506 #define REG_ALLOC_ORDER \
507 { \
508 /* Caller-saved general registers. */ \
509 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
510 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
511 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
512 R_GR (30), R_GR (31), \
513 /* Output registers. */ \
514 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
515 R_GR (126), R_GR (127), \
516 /* Caller-saved general registers, also used for return values. */ \
517 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
518 /* addl caller-saved general registers. */ \
519 R_GR (2), R_GR (3), \
520 /* Caller-saved FP registers. */ \
521 R_FR (6), R_FR (7), \
522 /* Caller-saved FP registers, used for parameters and return values. */ \
523 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
524 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
525 /* Rotating caller-saved FP registers. */ \
526 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
527 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
528 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
529 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
530 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
531 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
532 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
533 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
534 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
535 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
536 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
537 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
538 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
539 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
540 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
541 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
542 R_FR (126), R_FR (127), \
543 /* Caller-saved predicate registers. */ \
544 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
545 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
546 /* Rotating caller-saved predicate registers. */ \
547 R_PR (16), R_PR (17), \
548 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
549 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
550 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
551 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
552 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
553 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
554 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
555 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
556 /* Caller-saved branch registers. */ \
557 R_BR (6), R_BR (7), \
558 \
559 /* Stacked callee-saved general registers. */ \
560 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
561 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
562 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
563 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
564 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
565 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
566 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
567 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
568 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
569 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
570 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
571 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
572 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
573 R_GR (108), \
574 /* Input registers. */ \
575 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
576 R_GR (118), R_GR (119), \
577 /* Callee-saved general registers. */ \
578 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
579 /* Callee-saved FP registers. */ \
580 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
581 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
582 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
583 R_FR (30), R_FR (31), \
584 /* Callee-saved predicate registers. */ \
585 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
586 /* Callee-saved branch registers. */ \
587 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
588 \
589 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
590 R_GR (109), R_GR (110), R_GR (111), \
591 \
592 /* Special general registers. */ \
593 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
594 /* Special FP registers. */ \
595 R_FR (0), R_FR (1), \
596 /* Special predicate registers. */ \
597 R_PR (0), \
598 /* Special branch registers. */ \
599 R_BR (0), \
600 /* Other fixed registers. */ \
601 FRAME_POINTER_REGNUM, \
602 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
603 AR_EC_REGNUM \
604 }
605 \f
606 /* How Values Fit in Registers */
607
608 /* A C expression for the number of consecutive hard registers, starting at
609 register number REGNO, required to hold a value of mode MODE. */
610
611 /* ??? We say that BImode PR values require two registers. This allows us to
612 easily store the normal and inverted values. We use CCImode to indicate
613 a single predicate register. */
614
615 #define HARD_REGNO_NREGS(REGNO, MODE) \
616 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
617 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
618 : (PR_REGNO_P (REGNO) || GR_REGNO_P (REGNO)) && (MODE) == CCImode ? 1\
619 : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
620 : FR_REGNO_P (REGNO) && (MODE) == RFmode ? 1 \
621 : FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
622 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
623
624 /* A C expression that is nonzero if it is permissible to store a value of mode
625 MODE in hard register number REGNO (or in several registers starting with
626 that one). */
627
628 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
629 (FR_REGNO_P (REGNO) ? \
630 GET_MODE_CLASS (MODE) != MODE_CC && \
631 (MODE) != BImode && \
632 (MODE) != TFmode \
633 : PR_REGNO_P (REGNO) ? \
634 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
635 : GR_REGNO_P (REGNO) ? \
636 (MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \
637 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
638 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
639 : 0)
640
641 /* A C expression that is nonzero if it is desirable to choose register
642 allocation so as to avoid move instructions between a value of mode MODE1
643 and a value of mode MODE2.
644
645 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
646 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
647 zero. */
648 /* Don't tie integer and FP modes, as that causes us to get integer registers
649 allocated for FP instructions. XFmode only supported in FP registers so
650 we can't tie it with any other modes. */
651 #define MODES_TIEABLE_P(MODE1, MODE2) \
652 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
653 && ((((MODE1) == XFmode) || ((MODE1) == XCmode) || ((MODE1) == RFmode)) \
654 == (((MODE2) == XFmode) || ((MODE2) == XCmode) || ((MODE2) == RFmode))) \
655 && (((MODE1) == BImode) == ((MODE2) == BImode)))
656
657 /* Specify the modes required to caller save a given hard regno.
658 We need to ensure floating pt regs are not saved as DImode. */
659
660 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
661 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \
662 : choose_hard_reg_mode ((REGNO), (NREGS), false))
663 \f
664 /* Handling Leaf Functions */
665
666 /* A C initializer for a vector, indexed by hard register number, which
667 contains 1 for a register that is allowable in a candidate for leaf function
668 treatment. */
669 /* ??? This might be useful. */
670 /* #define LEAF_REGISTERS */
671
672 /* A C expression whose value is the register number to which REGNO should be
673 renumbered, when a function is treated as a leaf function. */
674 /* ??? This might be useful. */
675 /* #define LEAF_REG_REMAP(REGNO) */
676
677 \f
678 /* Register Classes */
679
680 /* An enumeral type that must be defined with all the register class names as
681 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
682 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
683 which is not a register class but rather tells how many classes there
684 are. */
685 /* ??? When compiling without optimization, it is possible for the only use of
686 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
687 Regclass handles this case specially and does not assign any costs to the
688 pseudo. The pseudo then ends up using the last class before ALL_REGS.
689 Thus we must not let either PR_REGS or BR_REGS be the last class. The
690 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
691 enum reg_class
692 {
693 NO_REGS,
694 PR_REGS,
695 BR_REGS,
696 AR_M_REGS,
697 AR_I_REGS,
698 ADDL_REGS,
699 GR_REGS,
700 FP_REGS,
701 FR_REGS,
702 GR_AND_BR_REGS,
703 GR_AND_FR_REGS,
704 ALL_REGS,
705 LIM_REG_CLASSES
706 };
707
708 #define GENERAL_REGS GR_REGS
709
710 /* The number of distinct register classes. */
711 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
712
713 /* An initializer containing the names of the register classes as C string
714 constants. These names are used in writing some of the debugging dumps. */
715 #define REG_CLASS_NAMES \
716 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
717 "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \
718 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
719
720 /* An initializer containing the contents of the register classes, as integers
721 which are bit masks. The Nth integer specifies the contents of class N.
722 The way the integer MASK is interpreted is that register R is in the class
723 if `MASK & (1 << R)' is 1. */
724 #define REG_CLASS_CONTENTS \
725 { \
726 /* NO_REGS. */ \
727 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
728 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
729 0x00000000, 0x00000000, 0x0000 }, \
730 /* PR_REGS. */ \
731 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
732 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
733 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
734 /* BR_REGS. */ \
735 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
736 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
737 0x00000000, 0x00000000, 0x00FF }, \
738 /* AR_M_REGS. */ \
739 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
740 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
741 0x00000000, 0x00000000, 0x0600 }, \
742 /* AR_I_REGS. */ \
743 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
744 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
745 0x00000000, 0x00000000, 0x3800 }, \
746 /* ADDL_REGS. */ \
747 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
748 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
749 0x00000000, 0x00000000, 0x0000 }, \
750 /* GR_REGS. */ \
751 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
752 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
753 0x00000000, 0x00000000, 0x0100 }, \
754 /* FP_REGS. */ \
755 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
756 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \
757 0x00000000, 0x00000000, 0x0000 }, \
758 /* FR_REGS. */ \
759 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
760 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
761 0x00000000, 0x00000000, 0x0000 }, \
762 /* GR_AND_BR_REGS. */ \
763 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
764 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
765 0x00000000, 0x00000000, 0x01FF }, \
766 /* GR_AND_FR_REGS. */ \
767 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
768 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
769 0x00000000, 0x00000000, 0x0100 }, \
770 /* ALL_REGS. */ \
771 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
772 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
773 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
774 }
775
776 /* A C expression whose value is a register class containing hard register
777 REGNO. In general there is more than one such class; choose a class which
778 is "minimal", meaning that no smaller class also contains the register. */
779 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
780 may call here with private (invalid) register numbers, such as
781 REG_VOLATILE. */
782 #define REGNO_REG_CLASS(REGNO) \
783 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
784 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
785 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \
786 && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \
787 : PR_REGNO_P (REGNO) ? PR_REGS \
788 : BR_REGNO_P (REGNO) ? BR_REGS \
789 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
790 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
791 : NO_REGS)
792
793 /* A macro whose definition is the name of the class to which a valid base
794 register must belong. A base register is one used in an address which is
795 the register value plus a displacement. */
796 #define BASE_REG_CLASS GENERAL_REGS
797
798 /* A macro whose definition is the name of the class to which a valid index
799 register must belong. An index register is one used in an address where its
800 value is either multiplied by a scale factor or added to another register
801 (as well as added to a displacement). This is needed for POST_MODIFY. */
802 #define INDEX_REG_CLASS GENERAL_REGS
803
804 /* A C expression which is nonzero if register number NUM is suitable for use
805 as a base register in operand addresses. It may be either a suitable hard
806 register or a pseudo register that has been allocated such a hard reg. */
807 #define REGNO_OK_FOR_BASE_P(REGNO) \
808 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
809
810 /* A C expression which is nonzero if register number NUM is suitable for use
811 as an index register in operand addresses. It may be either a suitable hard
812 register or a pseudo register that has been allocated such a hard reg.
813 This is needed for POST_MODIFY. */
814 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
815
816 /* You should define this macro to indicate to the reload phase that it may
817 need to allocate at least one register for a reload in addition to the
818 register to contain the data. Specifically, if copying X to a register
819 CLASS in MODE requires an intermediate register, you should define this
820 to return the largest register class all of whose registers can be used
821 as intermediate registers or scratch registers. */
822
823 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
824 ia64_secondary_reload_class (CLASS, MODE, X)
825
826 /* Certain machines have the property that some registers cannot be copied to
827 some other registers without using memory. Define this macro on those
828 machines to be a C expression that is nonzero if objects of mode M in
829 registers of CLASS1 can only be copied to registers of class CLASS2 by
830 storing a register of CLASS1 into memory and loading that memory location
831 into a register of CLASS2. */
832
833 #if 0
834 /* ??? May need this, but since we've disallowed XFmode in GR_REGS,
835 I'm not quite sure how it could be invoked. The normal problems
836 with unions should be solved with the addressof fiddling done by
837 movxf and friends. */
838 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
839 (((MODE) == XFmode || (MODE) == XCmode) \
840 && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
841 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
842 #endif
843
844 /* A C expression for the maximum number of consecutive registers of
845 class CLASS needed to hold a value of mode MODE.
846 This is closely related to the macro `HARD_REGNO_NREGS'. */
847
848 #define CLASS_MAX_NREGS(CLASS, MODE) \
849 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
850 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
851 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \
852 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
853 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
854
855 /* In BR regs, we can't change the DImode at all.
856 In FP regs, we can't change FP values to integer values and vice versa,
857 but we can change e.g. DImode to SImode, and V2SFmode into DImode. */
858
859 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
860 (reg_classes_intersect_p (CLASS, BR_REGS) \
861 ? (FROM) != (TO) \
862 : (SCALAR_FLOAT_MODE_P (FROM) != SCALAR_FLOAT_MODE_P (TO) \
863 ? reg_classes_intersect_p (CLASS, FR_REGS) \
864 : 0))
865 \f
866 /* Basic Stack Layout */
867
868 /* Define this macro if pushing a word onto the stack moves the stack pointer
869 to a smaller address. */
870 #define STACK_GROWS_DOWNWARD 1
871
872 /* Define this macro to nonzero if the addresses of local variable slots
873 are at negative offsets from the frame pointer. */
874 #define FRAME_GROWS_DOWNWARD 0
875
876 /* Offset from the frame pointer to the first local variable slot to
877 be allocated. */
878 #define STARTING_FRAME_OFFSET 0
879
880 /* Offset from the stack pointer register to the first location at which
881 outgoing arguments are placed. If not specified, the default value of zero
882 is used. This is the proper value for most machines. */
883 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
884 #define STACK_POINTER_OFFSET 16
885
886 /* Offset from the argument pointer register to the first argument's address.
887 On some machines it may depend on the data type of the function. */
888 #define FIRST_PARM_OFFSET(FUNDECL) 0
889
890 /* A C expression whose value is RTL representing the value of the return
891 address for the frame COUNT steps up from the current frame, after the
892 prologue. */
893
894 /* ??? Frames other than zero would likely require interpreting the frame
895 unwind info, so we don't try to support them. We would also need to define
896 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
897
898 #define RETURN_ADDR_RTX(COUNT, FRAME) \
899 ia64_return_addr_rtx (COUNT, FRAME)
900
901 /* A C expression whose value is RTL representing the location of the incoming
902 return address at the beginning of any function, before the prologue. This
903 RTL is either a `REG', indicating that the return value is saved in `REG',
904 or a `MEM' representing a location in the stack. This enables DWARF2
905 unwind info for C++ EH. */
906 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
907
908 /* A C expression whose value is an integer giving the offset, in bytes, from
909 the value of the stack pointer register to the top of the stack frame at the
910 beginning of any function, before the prologue. The top of the frame is
911 defined to be the value of the stack pointer in the previous frame, just
912 before the call instruction. */
913 /* The CFA is past the red zone, not at the entry-point stack
914 pointer. */
915 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
916
917 /* We shorten debug info by using CFA-16 as DW_AT_frame_base. */
918 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET)
919
920 \f
921 /* Register That Address the Stack Frame. */
922
923 /* The register number of the stack pointer register, which must also be a
924 fixed register according to `FIXED_REGISTERS'. On most machines, the
925 hardware determines which register this is. */
926
927 #define STACK_POINTER_REGNUM 12
928
929 /* The register number of the frame pointer register, which is used to access
930 automatic variables in the stack frame. On some machines, the hardware
931 determines which register this is. On other machines, you can choose any
932 register you wish for this purpose. */
933
934 #define FRAME_POINTER_REGNUM 328
935
936 /* Base register for access to local variables of the function. */
937 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
938
939 /* The register number of the arg pointer register, which is used to access the
940 function's argument list. */
941 /* r0 won't otherwise be used, so put the always eliminated argument pointer
942 in it. */
943 #define ARG_POINTER_REGNUM R_GR(0)
944
945 /* Due to the way varargs and argument spilling happens, the argument
946 pointer is not 16-byte aligned like the stack pointer. */
947 #define INIT_EXPANDERS \
948 do { \
949 ia64_init_expanders (); \
950 if (crtl->emit.regno_pointer_align) \
951 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
952 } while (0)
953
954 /* Register numbers used for passing a function's static chain pointer. */
955 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
956 #define STATIC_CHAIN_REGNUM 15
957 \f
958 /* Eliminating the Frame Pointer and the Arg Pointer */
959
960 /* If defined, this macro specifies a table of register pairs used to eliminate
961 unneeded registers that point into the stack frame. */
962
963 #define ELIMINABLE_REGS \
964 { \
965 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
966 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
967 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
968 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
969 }
970
971 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
972 specifies the initial difference between the specified pair of
973 registers. This macro must be defined if `ELIMINABLE_REGS' is
974 defined. */
975 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
976 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
977 \f
978 /* Passing Function Arguments on the Stack */
979
980 /* If defined, the maximum amount of space required for outgoing arguments will
981 be computed and placed into the variable
982 `crtl->outgoing_args_size'. */
983
984 #define ACCUMULATE_OUTGOING_ARGS 1
985
986 \f
987 /* Function Arguments in Registers */
988
989 #define MAX_ARGUMENT_SLOTS 8
990 #define MAX_INT_RETURN_SLOTS 4
991 #define GR_ARG_FIRST IN_REG (0)
992 #define GR_RET_FIRST GR_REG (8)
993 #define GR_RET_LAST GR_REG (11)
994 #define FR_ARG_FIRST FR_REG (8)
995 #define FR_RET_FIRST FR_REG (8)
996 #define FR_RET_LAST FR_REG (15)
997 #define AR_ARG_FIRST OUT_REG (0)
998
999 /* A C type for declaring a variable that is used as the first argument of
1000 `FUNCTION_ARG' and other related values. For some target machines, the type
1001 `int' suffices and can hold the number of bytes of argument so far. */
1002
1003 enum ivms_arg_type {I64, FF, FD, FG, FS, FT};
1004 /* VMS floating point formats VAX F, VAX D, VAX G, IEEE S, IEEE T. */
1005
1006 typedef struct ia64_args
1007 {
1008 int words; /* # words of arguments so far */
1009 int int_regs; /* # GR registers used so far */
1010 int fp_regs; /* # FR registers used so far */
1011 int prototype; /* whether function prototyped */
1012 enum ivms_arg_type atypes[8]; /* which VMS float type or if not float */
1013 } CUMULATIVE_ARGS;
1014
1015 /* A C statement (sans semicolon) for initializing the variable CUM for the
1016 state at the beginning of the argument list. */
1017
1018 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1019 do { \
1020 (CUM).words = 0; \
1021 (CUM).int_regs = 0; \
1022 (CUM).fp_regs = 0; \
1023 (CUM).prototype = ((FNTYPE) && prototype_p (FNTYPE)) || (LIBNAME); \
1024 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
1025 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
1026 (CUM).atypes[6] = (CUM).atypes[7] = I64; \
1027 } while (0)
1028
1029 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1030 arguments for the function being compiled. If this macro is undefined,
1031 `INIT_CUMULATIVE_ARGS' is used instead. */
1032
1033 /* We set prototype to true so that we never try to return a PARALLEL from
1034 function_arg. */
1035 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1036 do { \
1037 (CUM).words = 0; \
1038 (CUM).int_regs = 0; \
1039 (CUM).fp_regs = 0; \
1040 (CUM).prototype = 1; \
1041 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
1042 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
1043 (CUM).atypes[6] = (CUM).atypes[7] = I64; \
1044 } while (0)
1045
1046 /* A C expression that is nonzero if REGNO is the number of a hard register in
1047 which function arguments are sometimes passed. This does *not* include
1048 implicit arguments such as the static chain and the structure-value address.
1049 On many machines, no registers can be used for this purpose since all
1050 function arguments are pushed on the stack. */
1051 #define FUNCTION_ARG_REGNO_P(REGNO) \
1052 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1053 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1054
1055 \f
1056 /* How Large Values are Returned */
1057
1058 #define DEFAULT_PCC_STRUCT_RETURN 0
1059
1060 \f
1061 /* Caller-Saves Register Allocation */
1062
1063 /* A C expression to determine whether it is worthwhile to consider placing a
1064 pseudo-register in a call-clobbered hard register and saving and restoring
1065 it around each function call. The expression should be 1 when this is worth
1066 doing, and 0 otherwise.
1067
1068 If you don't define this macro, a default is used which is good on most
1069 machines: `4 * CALLS < REFS'. */
1070 /* ??? Investigate. */
1071 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1072
1073 \f
1074 /* Function Entry and Exit */
1075
1076 /* Define this macro as a C expression that is nonzero if the return
1077 instruction or the function epilogue ignores the value of the stack pointer;
1078 in other words, if it is safe to delete an instruction to adjust the stack
1079 pointer before a return from the function. */
1080
1081 #define EXIT_IGNORE_STACK 1
1082
1083 /* Define this macro as a C expression that is nonzero for registers
1084 used by the epilogue or the `return' pattern. */
1085
1086 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1087
1088 /* Nonzero for registers used by the exception handling mechanism. */
1089
1090 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
1091
1092 /* Output part N of a function descriptor for DECL. For ia64, both
1093 words are emitted with a single relocation, so ignore N > 0. */
1094 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1095 do { \
1096 if ((PART) == 0) \
1097 { \
1098 if (TARGET_ILP32) \
1099 fputs ("\tdata8.ua @iplt(", FILE); \
1100 else \
1101 fputs ("\tdata16.ua @iplt(", FILE); \
1102 mark_decl_referenced (DECL); \
1103 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1104 fputs (")\n", FILE); \
1105 if (TARGET_ILP32) \
1106 fputs ("\tdata8.ua 0\n", FILE); \
1107 } \
1108 } while (0)
1109 \f
1110 /* Generating Code for Profiling. */
1111
1112 /* A C statement or compound statement to output to FILE some assembler code to
1113 call the profiling subroutine `mcount'. */
1114
1115 #undef FUNCTION_PROFILER
1116 #define FUNCTION_PROFILER(FILE, LABELNO) \
1117 ia64_output_function_profiler(FILE, LABELNO)
1118
1119 /* Neither hpux nor linux use profile counters. */
1120 #define NO_PROFILE_COUNTERS 1
1121 \f
1122 /* Trampolines for Nested Functions. */
1123
1124 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1125 the function containing a non-local goto target. */
1126
1127 #define STACK_SAVEAREA_MODE(LEVEL) \
1128 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1129
1130 /* A C expression for the size in bytes of the trampoline, as an integer. */
1131
1132 #define TRAMPOLINE_SIZE 32
1133
1134 /* Alignment required for trampolines, in bits. */
1135
1136 #define TRAMPOLINE_ALIGNMENT 64
1137 \f
1138 /* Addressing Modes */
1139
1140 /* Define this macro if the machine supports post-increment addressing. */
1141
1142 #define HAVE_POST_INCREMENT 1
1143 #define HAVE_POST_DECREMENT 1
1144 #define HAVE_POST_MODIFY_DISP 1
1145 #define HAVE_POST_MODIFY_REG 1
1146
1147 /* A C expression that is 1 if the RTX X is a constant which is a valid
1148 address. */
1149
1150 #define CONSTANT_ADDRESS_P(X) 0
1151
1152 /* The max number of registers that can appear in a valid memory address. */
1153
1154 #define MAX_REGS_PER_ADDRESS 2
1155
1156 \f
1157 /* Condition Code Status */
1158
1159 /* One some machines not all possible comparisons are defined, but you can
1160 convert an invalid comparison into a valid one. */
1161 /* ??? Investigate. See the alpha definition. */
1162 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1163
1164 \f
1165 /* Describing Relative Costs of Operations */
1166
1167 /* A C expression for the cost of a branch instruction. A value of 1 is the
1168 default; other values are interpreted relative to that. Used by the
1169 if-conversion code as max instruction count. */
1170 /* ??? This requires investigation. The primary effect might be how
1171 many additional insn groups we run into, vs how good the dynamic
1172 branch predictor is. */
1173
1174 #define BRANCH_COST(speed_p, predictable_p) 6
1175
1176 /* Define this macro as a C expression which is nonzero if accessing less than
1177 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1178 word of memory. */
1179
1180 #define SLOW_BYTE_ACCESS 1
1181
1182 /* Define this macro if it is as good or better to call a constant function
1183 address than to call an address kept in a register.
1184
1185 Indirect function calls are more expensive that direct function calls, so
1186 don't cse function addresses. */
1187
1188 #define NO_FUNCTION_CSE
1189
1190 \f
1191 /* Dividing the output into sections. */
1192
1193 /* A C expression whose value is a string containing the assembler operation
1194 that should precede instructions and read-only data. */
1195
1196 #define TEXT_SECTION_ASM_OP "\t.text"
1197
1198 /* A C expression whose value is a string containing the assembler operation to
1199 identify the following data as writable initialized data. */
1200
1201 #define DATA_SECTION_ASM_OP "\t.data"
1202
1203 /* If defined, a C expression whose value is a string containing the assembler
1204 operation to identify the following data as uninitialized global data. */
1205
1206 #define BSS_SECTION_ASM_OP "\t.bss"
1207
1208 #define IA64_DEFAULT_GVALUE 8
1209 \f
1210 /* Position Independent Code. */
1211
1212 /* The register number of the register used to address a table of static data
1213 addresses in memory. */
1214
1215 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1216 gen_rtx_REG (DImode, 1). */
1217
1218 /* ??? Should we set flag_pic? Probably need to define
1219 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1220
1221 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1222
1223 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1224 clobbered by calls. */
1225
1226 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
1227
1228 \f
1229 /* The Overall Framework of an Assembler File. */
1230
1231 /* A C string constant describing how to begin a comment in the target
1232 assembler language. The compiler assumes that the comment will end at the
1233 end of the line. */
1234
1235 #define ASM_COMMENT_START "//"
1236
1237 /* A C string constant for text to be output before each `asm' statement or
1238 group of consecutive ones. */
1239
1240 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
1241
1242 /* A C string constant for text to be output after each `asm' statement or
1243 group of consecutive ones. */
1244
1245 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
1246 \f
1247 /* Output and Generation of Labels. */
1248
1249 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1250 assembler definition of a label named NAME. */
1251
1252 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1253 why ia64_asm_output_label exists. */
1254
1255 extern int ia64_asm_output_label;
1256 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1257 do { \
1258 ia64_asm_output_label = 1; \
1259 assemble_name (STREAM, NAME); \
1260 fputs (":\n", STREAM); \
1261 ia64_asm_output_label = 0; \
1262 } while (0)
1263
1264 /* Globalizing directive for a label. */
1265 #define GLOBAL_ASM_OP "\t.global "
1266
1267 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1268 necessary for declaring the name of an external symbol named NAME which is
1269 referenced in this compilation but not defined. */
1270
1271 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1272 ia64_asm_output_external (FILE, DECL, NAME)
1273
1274 /* A C statement to store into the string STRING a label whose name is made
1275 from the string PREFIX and the number NUM. */
1276
1277 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1278 do { \
1279 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1280 } while (0)
1281
1282 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1283
1284 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1285
1286 /* A C statement to output to the stdio stream STREAM assembler code which
1287 defines (equates) the symbol NAME to have the value VALUE. */
1288
1289 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1290 do { \
1291 assemble_name (STREAM, NAME); \
1292 fputs (" = ", STREAM); \
1293 if (ISDIGIT (*VALUE)) \
1294 ia64_asm_output_label = 1; \
1295 assemble_name (STREAM, VALUE); \
1296 fputc ('\n', STREAM); \
1297 ia64_asm_output_label = 0; \
1298 } while (0)
1299
1300 \f
1301 /* Macros Controlling Initialization Routines. */
1302
1303 /* This is handled by sysv4.h. */
1304
1305 \f
1306 /* Output of Assembler Instructions. */
1307
1308 /* A C initializer containing the assembler's names for the machine registers,
1309 each one as a C string constant. */
1310
1311 #define REGISTER_NAMES \
1312 { \
1313 /* General registers. */ \
1314 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1315 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1316 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1317 "r30", "r31", \
1318 /* Local registers. */ \
1319 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1320 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1321 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1322 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1323 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1324 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1325 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1326 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1327 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1328 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1329 /* Input registers. */ \
1330 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1331 /* Output registers. */ \
1332 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1333 /* Floating-point registers. */ \
1334 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1335 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1336 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1337 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1338 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1339 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1340 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1341 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1342 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1343 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1344 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1345 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1346 "f120","f121","f122","f123","f124","f125","f126","f127", \
1347 /* Predicate registers. */ \
1348 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1349 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1350 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1351 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1352 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1353 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1354 "p60", "p61", "p62", "p63", \
1355 /* Branch registers. */ \
1356 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
1357 /* Frame pointer. Application registers. */ \
1358 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
1359 }
1360
1361 /* If defined, a C initializer for an array of structures containing a name and
1362 a register number. This macro defines additional names for hard registers,
1363 thus allowing the `asm' option in declarations to refer to registers using
1364 alternate names. */
1365
1366 #define ADDITIONAL_REGISTER_NAMES \
1367 { \
1368 { "gp", R_GR (1) }, \
1369 { "sp", R_GR (12) }, \
1370 { "in0", IN_REG (0) }, \
1371 { "in1", IN_REG (1) }, \
1372 { "in2", IN_REG (2) }, \
1373 { "in3", IN_REG (3) }, \
1374 { "in4", IN_REG (4) }, \
1375 { "in5", IN_REG (5) }, \
1376 { "in6", IN_REG (6) }, \
1377 { "in7", IN_REG (7) }, \
1378 { "out0", OUT_REG (0) }, \
1379 { "out1", OUT_REG (1) }, \
1380 { "out2", OUT_REG (2) }, \
1381 { "out3", OUT_REG (3) }, \
1382 { "out4", OUT_REG (4) }, \
1383 { "out5", OUT_REG (5) }, \
1384 { "out6", OUT_REG (6) }, \
1385 { "out7", OUT_REG (7) }, \
1386 { "loc0", LOC_REG (0) }, \
1387 { "loc1", LOC_REG (1) }, \
1388 { "loc2", LOC_REG (2) }, \
1389 { "loc3", LOC_REG (3) }, \
1390 { "loc4", LOC_REG (4) }, \
1391 { "loc5", LOC_REG (5) }, \
1392 { "loc6", LOC_REG (6) }, \
1393 { "loc7", LOC_REG (7) }, \
1394 { "loc8", LOC_REG (8) }, \
1395 { "loc9", LOC_REG (9) }, \
1396 { "loc10", LOC_REG (10) }, \
1397 { "loc11", LOC_REG (11) }, \
1398 { "loc12", LOC_REG (12) }, \
1399 { "loc13", LOC_REG (13) }, \
1400 { "loc14", LOC_REG (14) }, \
1401 { "loc15", LOC_REG (15) }, \
1402 { "loc16", LOC_REG (16) }, \
1403 { "loc17", LOC_REG (17) }, \
1404 { "loc18", LOC_REG (18) }, \
1405 { "loc19", LOC_REG (19) }, \
1406 { "loc20", LOC_REG (20) }, \
1407 { "loc21", LOC_REG (21) }, \
1408 { "loc22", LOC_REG (22) }, \
1409 { "loc23", LOC_REG (23) }, \
1410 { "loc24", LOC_REG (24) }, \
1411 { "loc25", LOC_REG (25) }, \
1412 { "loc26", LOC_REG (26) }, \
1413 { "loc27", LOC_REG (27) }, \
1414 { "loc28", LOC_REG (28) }, \
1415 { "loc29", LOC_REG (29) }, \
1416 { "loc30", LOC_REG (30) }, \
1417 { "loc31", LOC_REG (31) }, \
1418 { "loc32", LOC_REG (32) }, \
1419 { "loc33", LOC_REG (33) }, \
1420 { "loc34", LOC_REG (34) }, \
1421 { "loc35", LOC_REG (35) }, \
1422 { "loc36", LOC_REG (36) }, \
1423 { "loc37", LOC_REG (37) }, \
1424 { "loc38", LOC_REG (38) }, \
1425 { "loc39", LOC_REG (39) }, \
1426 { "loc40", LOC_REG (40) }, \
1427 { "loc41", LOC_REG (41) }, \
1428 { "loc42", LOC_REG (42) }, \
1429 { "loc43", LOC_REG (43) }, \
1430 { "loc44", LOC_REG (44) }, \
1431 { "loc45", LOC_REG (45) }, \
1432 { "loc46", LOC_REG (46) }, \
1433 { "loc47", LOC_REG (47) }, \
1434 { "loc48", LOC_REG (48) }, \
1435 { "loc49", LOC_REG (49) }, \
1436 { "loc50", LOC_REG (50) }, \
1437 { "loc51", LOC_REG (51) }, \
1438 { "loc52", LOC_REG (52) }, \
1439 { "loc53", LOC_REG (53) }, \
1440 { "loc54", LOC_REG (54) }, \
1441 { "loc55", LOC_REG (55) }, \
1442 { "loc56", LOC_REG (56) }, \
1443 { "loc57", LOC_REG (57) }, \
1444 { "loc58", LOC_REG (58) }, \
1445 { "loc59", LOC_REG (59) }, \
1446 { "loc60", LOC_REG (60) }, \
1447 { "loc61", LOC_REG (61) }, \
1448 { "loc62", LOC_REG (62) }, \
1449 { "loc63", LOC_REG (63) }, \
1450 { "loc64", LOC_REG (64) }, \
1451 { "loc65", LOC_REG (65) }, \
1452 { "loc66", LOC_REG (66) }, \
1453 { "loc67", LOC_REG (67) }, \
1454 { "loc68", LOC_REG (68) }, \
1455 { "loc69", LOC_REG (69) }, \
1456 { "loc70", LOC_REG (70) }, \
1457 { "loc71", LOC_REG (71) }, \
1458 { "loc72", LOC_REG (72) }, \
1459 { "loc73", LOC_REG (73) }, \
1460 { "loc74", LOC_REG (74) }, \
1461 { "loc75", LOC_REG (75) }, \
1462 { "loc76", LOC_REG (76) }, \
1463 { "loc77", LOC_REG (77) }, \
1464 { "loc78", LOC_REG (78) }, \
1465 { "loc79", LOC_REG (79) }, \
1466 }
1467
1468 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
1469 `%I' options of `asm_fprintf' (see `final.c'). */
1470
1471 #define REGISTER_PREFIX ""
1472 #define LOCAL_LABEL_PREFIX "."
1473 #define USER_LABEL_PREFIX ""
1474 #define IMMEDIATE_PREFIX ""
1475
1476 \f
1477 /* Output of dispatch tables. */
1478
1479 /* This macro should be provided on machines where the addresses in a dispatch
1480 table are relative to the table's own address. */
1481
1482 /* ??? Depends on the pointer size. */
1483
1484 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1485 do { \
1486 if (CASE_VECTOR_MODE == SImode) \
1487 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
1488 else \
1489 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
1490 } while (0)
1491
1492 /* Jump tables only need 4 or 8 byte alignment. */
1493
1494 #define ADDR_VEC_ALIGN(ADDR_VEC) (CASE_VECTOR_MODE == SImode ? 2 : 3)
1495
1496 \f
1497 /* Assembler Commands for Exception Regions. */
1498
1499 /* Select a format to encode pointers in exception handling data. CODE
1500 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1501 true if the symbol may be affected by dynamic relocations. */
1502 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1503 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
1504 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \
1505 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
1506
1507 /* Handle special EH pointer encodings. Absolute, pc-relative, and
1508 indirect are handled automatically. */
1509 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1510 do { \
1511 const char *reltag = NULL; \
1512 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
1513 reltag = "@segrel("; \
1514 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
1515 reltag = "@gprel("; \
1516 if (reltag) \
1517 { \
1518 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1519 fputs (reltag, FILE); \
1520 assemble_name (FILE, XSTR (ADDR, 0)); \
1521 fputc (')', FILE); \
1522 goto DONE; \
1523 } \
1524 } while (0)
1525
1526 \f
1527 /* Assembler Commands for Alignment. */
1528
1529 /* ??? Investigate. */
1530
1531 /* The alignment (log base 2) to put in front of LABEL, which follows
1532 a BARRIER. */
1533
1534 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
1535
1536 /* The desired alignment for the location counter at the beginning
1537 of a loop. */
1538
1539 /* #define LOOP_ALIGN(LABEL) */
1540
1541 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
1542 section because it fails put zeros in the bytes that are skipped. */
1543
1544 #define ASM_NO_SKIP_IN_TEXT 1
1545
1546 /* A C statement to output to the stdio stream STREAM an assembler command to
1547 advance the location counter to a multiple of 2 to the POWER bytes. */
1548
1549 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1550 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
1551
1552 \f
1553 /* Macros Affecting all Debug Formats. */
1554
1555 /* This is handled in sysv4.h. */
1556
1557 \f
1558 /* Specific Options for DBX Output. */
1559
1560 /* This is handled by dbxelf.h. */
1561
1562 \f
1563 /* Open ended Hooks for DBX Output. */
1564
1565 /* Likewise. */
1566
1567 \f
1568 /* File names in DBX format. */
1569
1570 /* Likewise. */
1571
1572 \f
1573 /* Macros for SDB and Dwarf Output. */
1574
1575 /* Define this macro if GCC should produce dwarf version 2 format debugging
1576 output in response to the `-g' option. */
1577
1578 #define DWARF2_DEBUGGING_INFO 1
1579
1580 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
1581
1582 /* Use tags for debug info labels, so that they don't break instruction
1583 bundles. This also avoids getting spurious DV warnings from the
1584 assembler. This is similar to (*targetm.asm_out.internal_label), except that we
1585 add brackets around the label. */
1586
1587 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
1588 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
1589
1590 /* Use section-relative relocations for debugging offsets. Unlike other
1591 targets that fake this by putting the section VMA at 0, IA-64 has
1592 proper relocations for them. */
1593 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, SECTION) \
1594 do { \
1595 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1596 fputs ("@secrel(", FILE); \
1597 assemble_name (FILE, LABEL); \
1598 fputc (')', FILE); \
1599 } while (0)
1600
1601 /* Emit a PC-relative relocation. */
1602 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1603 do { \
1604 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1605 fputs ("@pcrel(", FILE); \
1606 assemble_name (FILE, LABEL); \
1607 fputc (')', FILE); \
1608 } while (0)
1609 \f
1610 /* Register Renaming Parameters. */
1611
1612 /* A C expression that is nonzero if hard register number REGNO2 can be
1613 considered for use as a rename register for REGNO1 */
1614
1615 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
1616 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
1617
1618 \f
1619 /* Miscellaneous Parameters. */
1620
1621 /* Flag to mark data that is in the small address area (addressable
1622 via "addl", that is, within a 2MByte offset of 0. */
1623 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
1624 #define SYMBOL_REF_SMALL_ADDR_P(X) \
1625 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
1626
1627 /* An alias for a machine mode name. This is the machine mode that elements of
1628 a jump-table should have. */
1629
1630 #define CASE_VECTOR_MODE ptr_mode
1631
1632 /* Define as C expression which evaluates to nonzero if the tablejump
1633 instruction expects the table to contain offsets from the address of the
1634 table. */
1635
1636 #define CASE_VECTOR_PC_RELATIVE 1
1637
1638 /* Define this macro if operations between registers with integral mode smaller
1639 than a word are always performed on the entire register. */
1640
1641 #define WORD_REGISTER_OPERATIONS
1642
1643 /* Define this macro to be a C expression indicating when insns that read
1644 memory in MODE, an integral mode narrower than a word, set the bits outside
1645 of MODE to be either the sign-extension or the zero-extension of the data
1646 read. */
1647
1648 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1649
1650 /* The maximum number of bytes that a single instruction can move quickly from
1651 memory to memory. */
1652 #define MOVE_MAX 8
1653
1654 /* A C expression which is nonzero if on this machine it is safe to "convert"
1655 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
1656 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
1657
1658 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1659
1660 /* A C expression describing the value returned by a comparison operator with
1661 an integral mode and stored by a store-flag instruction (`sCOND') when the
1662 condition is true. */
1663
1664 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */
1665
1666 /* An alias for the machine mode for pointers. */
1667
1668 /* ??? This would change if we had ILP32 support. */
1669
1670 #define Pmode DImode
1671
1672 /* An alias for the machine mode used for memory references to functions being
1673 called, in `call' RTL expressions. */
1674
1675 #define FUNCTION_MODE Pmode
1676
1677 /* A C expression for the maximum number of instructions to execute via
1678 conditional execution instructions instead of a branch. A value of
1679 BRANCH_COST+1 is the default if the machine does not use
1680 cc0, and 1 if it does use cc0. */
1681 /* ??? Investigate. */
1682 #define MAX_CONDITIONAL_EXECUTE 12
1683
1684 extern int ia64_final_schedule;
1685
1686 #define TARGET_UNWIND_TABLES_DEFAULT true
1687
1688 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
1689
1690 /* This function contains machine specific function data. */
1691 struct GTY(()) machine_function
1692 {
1693 /* The new stack pointer when unwinding from EH. */
1694 rtx ia64_eh_epilogue_sp;
1695
1696 /* The new bsp value when unwinding from EH. */
1697 rtx ia64_eh_epilogue_bsp;
1698
1699 /* The GP value save register. */
1700 rtx ia64_gp_save;
1701
1702 /* The number of varargs registers to save. */
1703 int n_varargs;
1704
1705 /* The number of the next unwind state to copy. */
1706 int state_num;
1707 };
1708
1709 #define DONT_USE_BUILTIN_SETJMP
1710
1711 /* Output any profiling code before the prologue. */
1712
1713 #undef PROFILE_BEFORE_PROLOGUE
1714 #define PROFILE_BEFORE_PROLOGUE 1
1715
1716 /* Initialize library function table. */
1717 #undef TARGET_INIT_LIBFUNCS
1718 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
1719 \f
1720
1721 /* Switch on code for querying unit reservations. */
1722 #define CPU_UNITS_QUERY 1
1723
1724 /* End of ia64.h */
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