gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2013 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #ifdef __GNUC__
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x2c:
 130         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 131         break;
 132       case 0x39:
 133         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 134         break;
 135       case 0x3a:
 136         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 137         break;
 138       case 0x3b:
 139         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 140         break;
 141       case 0x3c:
 142         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 143         break;
 144       case 0x3d:
 145         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 146         break;
 147       case 0x3e:
 148         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 149         break;
 150       case 0x41:
 151         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 152         break;
 153       case 0x42:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 155         break;
 156       case 0x43:
 157         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 158         break;
 159       case 0x44:
 160         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 161         break;
 162       case 0x45:
 163         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x49:
 166         if (xeon_mp)
 167           break;
 168         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 169         break;
 170       case 0x4e:
 171         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 172         break;
 173       case 0x60:
 174         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 175         break;
 176       case 0x66:
 177         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 178         break;
 179       case 0x67:
 180         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 181         break;
 182       case 0x68:
 183         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 184         break;
 185       case 0x78:
 186         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 187         break;
 188       case 0x79:
 189         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 190         break;
 191       case 0x7a:
 192         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 193         break;
 194       case 0x7b:
 195         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 196         break;
 197       case 0x7c:
 198         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 199         break;
 200       case 0x7d:
 201         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 202         break;
 203       case 0x7f:
 204         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 205         break;
 206       case 0x82:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 208         break;
 209       case 0x83:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 211         break;
 212       case 0x84:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 214         break;
 215       case 0x85:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 217         break;
 218       case 0x86:
 219         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 220         break;
 221       case 0x87:
 222         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 223
 224       default:
 225         break;
 226       }
 227 }
 228
 229 /* Detect cache parameters using CPUID function 2.  */
 230
 231 static void
 232 detect_caches_cpuid2 (bool xeon_mp,
 233                       struct cache_desc *level1, struct cache_desc *level2)
 234 {
 235   unsigned regs[4];
 236   int nreps, i;
 237
 238   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 239
 240   nreps = regs[0] & 0x0f;
 241   regs[0] &= ~0x0f;
 242
 243   while (--nreps >= 0)
 244     {
 245       for (i = 0; i < 4; i++)
 246         if (regs[i] && !((regs[i] >> 31) & 1))
 247           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 248
 249       if (nreps)
 250         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 251     }
 252 }
 253
 254 /* Detect cache parameters using CPUID function 4. This
 255    method doesn't require hardcoded tables.  */
 256
 257 enum cache_type
 258 {
 259   CACHE_END = 0,
 260   CACHE_DATA = 1,
 261   CACHE_INST = 2,
 262   CACHE_UNIFIED = 3
 263 };
 264
 265 static void
 266 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 267                       struct cache_desc *level3)
 268 {
 269   struct cache_desc *cache;
 270
 271   unsigned eax, ebx, ecx, edx;
 272   int count;
 273
 274   for (count = 0;; count++)
 275     {
 276       __cpuid_count(4, count, eax, ebx, ecx, edx);
 277       switch (eax & 0x1f)
 278         {
 279         case CACHE_END:
 280           return;
 281         case CACHE_DATA:
 282         case CACHE_UNIFIED:
 283           {
 284             switch ((eax >> 5) & 0x07)
 285               {
 286               case 1:
 287                 cache = level1;
 288                 break;
 289               case 2:
 290                 cache = level2;
 291                 break;
 292               case 3:
 293                 cache = level3;
 294                 break;
 295               default:
 296                 cache = NULL;
 297               }
 298
 299             if (cache)
 300               {
 301                 unsigned sets = ecx + 1;
 302                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 303
 304                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 305                 cache->line = (ebx & 0x0fff) + 1;
 306
 307                 cache->sizekb = (cache->assoc * part
 308                                  * cache->line * sets) / 1024;
 309               }
 310           }
 311         default:
 312           break;
 313         }
 314     }
 315 }
 316
 317 /* Returns the description of caches for an Intel processor.  */
 318
 319 static const char *
 320 detect_caches_intel (bool xeon_mp, unsigned max_level,
 321                      unsigned max_ext_level, unsigned *l2sizekb)
 322 {
 323   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 324
 325   if (max_level >= 4)
 326     detect_caches_cpuid4 (&level1, &level2, &level3);
 327   else if (max_level >= 2)
 328     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 329   else
 330     return "";
 331
 332   if (level1.sizekb == 0)
 333     return "";
 334
 335   /* Let the L3 replace the L2. This assumes inclusive caches
 336      and single threaded program for now. */
 337   if (level3.sizekb)
 338     level2 = level3;
 339
 340   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 341      method if other methods fail to provide L2 cache parameters.  */
 342   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 343     detect_l2_cache (&level2);
 344
 345   *l2sizekb = level2.sizekb;
 346
 347   return describe_cache (level1, level2);
 348 }
 349
 350 /* This will be called by the spec parser in gcc.c when it sees
 351    a %:local_cpu_detect(args) construct.  Currently it will be called
 352    with either "arch" or "tune" as argument depending on if -march=native
 353    or -mtune=native is to be substituted.
 354
 355    It returns a string containing new command line parameters to be
 356    put at the place of the above two options, depending on what CPU
 357    this is executed.  E.g. "-march=k8" on an AMD64 machine
 358    for -march=native.
 359
 360    ARGC and ARGV are set depending on the actual arguments given
 361    in the spec.  */
 362
 363 const char *host_detect_local_cpu (int argc, const char **argv)
 364 {
 365   enum processor_type processor = PROCESSOR_I386;
 366   const char *cpu = "i386";
 367
 368   const char *cache = "";
 369   const char *options = "";
 370
 371   unsigned int eax, ebx, ecx, edx;
 372
 373   unsigned int max_level, ext_level;
 374
 375   unsigned int vendor;
 376   unsigned int model, family;
 377
 378   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 379   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 380
 381   /* Extended features */
 382   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 383   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 384   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 385   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 386   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 387   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 388   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 389   unsigned int has_hle = 0, has_rtm = 0;
 390   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 391   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 392   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 393   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 394   unsigned int has_avx512f = 0;
 395
 396   bool arch;
 397
 398   unsigned int l2sizekb = 0;
 399
 400   if (argc < 1)
 401     return NULL;
 402
 403   arch = !strcmp (argv[0], "arch");
 404
 405   if (!arch && strcmp (argv[0], "tune"))
 406     return NULL;
 407
 408   max_level = __get_cpuid_max (0, &vendor);
 409   if (max_level < 1)
 410     goto done;
 411
 412   __cpuid (1, eax, ebx, ecx, edx);
 413
 414   model = (eax >> 4) & 0x0f;
 415   family = (eax >> 8) & 0x0f;
 416   if (vendor == signature_INTEL_ebx)
 417     {
 418       unsigned int extended_model, extended_family;
 419
 420       extended_model = (eax >> 12) & 0xf0;
 421       extended_family = (eax >> 20) & 0xff;
 422       if (family == 0x0f)
 423         {
 424           family += extended_family;
 425           model += extended_model;
 426         }
 427       else if (family == 0x06)
 428         model += extended_model;
 429     }
 430
 431   has_sse3 = ecx & bit_SSE3;
 432   has_ssse3 = ecx & bit_SSSE3;
 433   has_sse4_1 = ecx & bit_SSE4_1;
 434   has_sse4_2 = ecx & bit_SSE4_2;
 435   has_avx = ecx & bit_AVX;
 436   has_osxsave = ecx & bit_OSXSAVE;
 437   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 438   has_movbe = ecx & bit_MOVBE;
 439   has_popcnt = ecx & bit_POPCNT;
 440   has_aes = ecx & bit_AES;
 441   has_pclmul = ecx & bit_PCLMUL;
 442   has_fma = ecx & bit_FMA;
 443   has_f16c = ecx & bit_F16C;
 444   has_rdrnd = ecx & bit_RDRND;
 445   has_xsave = ecx & bit_XSAVE;
 446
 447   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 448   has_cmov = edx & bit_CMOV;
 449   has_mmx = edx & bit_MMX;
 450   has_fxsr = edx & bit_FXSAVE;
 451   has_sse = edx & bit_SSE;
 452   has_sse2 = edx & bit_SSE2;
 453
 454   if (max_level >= 7)
 455     {
 456       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 457
 458       has_bmi = ebx & bit_BMI;
 459       has_hle = ebx & bit_HLE;
 460       has_rtm = ebx & bit_RTM;
 461       has_avx2 = ebx & bit_AVX2;
 462       has_bmi2 = ebx & bit_BMI2;
 463       has_fsgsbase = ebx & bit_FSGSBASE;
 464       has_rdseed = ebx & bit_RDSEED;
 465       has_adx = ebx & bit_ADX;
 466       has_avx512f = ebx & bit_AVX512F;
 467       has_avx512er = ebx & bit_AVX512ER;
 468       has_avx512pf = ebx & bit_AVX512PF;
 469       has_avx512cd = ebx & bit_AVX512CD;
 470     }
 471
 472   if (max_level >= 13)
 473     {
 474       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 475
 476       has_xsaveopt = eax & bit_XSAVEOPT;
 477     }
 478
 479   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 480 #define XCR_XFEATURE_ENABLED_MASK       0x0
 481 #define XSTATE_FP                       0x1
 482 #define XSTATE_SSE                      0x2
 483 #define XSTATE_YMM                      0x4
 484   if (has_osxsave)
 485     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 486          : "=a" (eax), "=d" (edx)
 487          : "c" (XCR_XFEATURE_ENABLED_MASK));
 488
 489   /* Check if SSE and YMM states are supported.  */
 490   if (!has_osxsave
 491       || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
 492     {
 493       has_avx = 0;
 494       has_avx2 = 0;
 495       has_fma = 0;
 496       has_fma4 = 0;
 497       has_xop = 0;
 498       has_xsave = 0;
 499       has_xsaveopt = 0;
 500     }
 501
 502   /* Check cpuid level of extended features.  */
 503   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 504
 505   if (ext_level > 0x80000000)
 506     {
 507       __cpuid (0x80000001, eax, ebx, ecx, edx);
 508
 509       has_lahf_lm = ecx & bit_LAHF_LM;
 510       has_sse4a = ecx & bit_SSE4a;
 511       has_abm = ecx & bit_ABM;
 512       has_lwp = ecx & bit_LWP;
 513       has_fma4 = ecx & bit_FMA4;
 514       has_xop = ecx & bit_XOP;
 515       has_tbm = ecx & bit_TBM;
 516       has_lzcnt = ecx & bit_LZCNT;
 517       has_prfchw = ecx & bit_PRFCHW;
 518
 519       has_longmode = edx & bit_LM;
 520       has_3dnowp = edx & bit_3DNOWP;
 521       has_3dnow = edx & bit_3DNOW;
 522     }
 523
 524   if (!arch)
 525     {
 526       if (vendor == signature_AMD_ebx
 527           || vendor == signature_CENTAUR_ebx
 528           || vendor == signature_CYRIX_ebx
 529           || vendor == signature_NSC_ebx)
 530         cache = detect_caches_amd (ext_level);
 531       else if (vendor == signature_INTEL_ebx)
 532         {
 533           bool xeon_mp = (family == 15 && model == 6);
 534           cache = detect_caches_intel (xeon_mp, max_level,
 535                                        ext_level, &l2sizekb);
 536         }
 537     }
 538
 539   if (vendor == signature_AMD_ebx)
 540     {
 541       unsigned int name;
 542
 543       /* Detect geode processor by its processor signature.  */
 544       if (ext_level > 0x80000001)
 545         __cpuid (0x80000002, name, ebx, ecx, edx);
 546       else
 547         name = 0;
 548
 549       if (name == signature_NSC_ebx)
 550         processor = PROCESSOR_GEODE;
 551       else if (has_movbe)
 552         processor = PROCESSOR_BTVER2;
 553       else if (has_avx2)
 554         processor = PROCESSOR_BDVER4;
 555       else if (has_xsaveopt)
 556         processor = PROCESSOR_BDVER3;
 557       else if (has_bmi)
 558         processor = PROCESSOR_BDVER2;
 559       else if (has_xop)
 560         processor = PROCESSOR_BDVER1;
 561       else if (has_sse4a && has_ssse3)
 562         processor = PROCESSOR_BTVER1;
 563       else if (has_sse4a)
 564         processor = PROCESSOR_AMDFAM10;
 565       else if (has_sse2 || has_longmode)
 566         processor = PROCESSOR_K8;
 567       else if (has_3dnowp && family == 6)
 568         processor = PROCESSOR_ATHLON;
 569       else if (has_mmx)
 570         processor = PROCESSOR_K6;
 571       else
 572         processor = PROCESSOR_PENTIUM;
 573     }
 574   else if (vendor == signature_CENTAUR_ebx)
 575     {
 576       if (arch)
 577         {
 578           switch (family)
 579             {
 580             case 6:
 581               if (model > 9)
 582                 /* Use the default detection procedure.  */
 583                 processor = PROCESSOR_GENERIC;
 584               else if (model == 9)
 585                 cpu = "c3-2";
 586               else if (model >= 6)
 587                 cpu = "c3";
 588               else
 589                 processor = PROCESSOR_GENERIC;
 590               break;
 591             case 5:
 592               if (has_3dnow)
 593                 cpu = "winchip2";
 594               else if (has_mmx)
 595                 cpu = "winchip2-c6";
 596               else
 597                 processor = PROCESSOR_GENERIC;
 598               break;
 599             default:
 600               /* We have no idea.  */
 601               processor = PROCESSOR_GENERIC;
 602             }
 603         }
 604     }
 605   else
 606     {
 607       switch (family)
 608         {
 609         case 4:
 610           processor = PROCESSOR_I486;
 611           break;
 612         case 5:
 613           processor = PROCESSOR_PENTIUM;
 614           break;
 615         case 6:
 616           processor = PROCESSOR_PENTIUMPRO;
 617           break;
 618         case 15:
 619           processor = PROCESSOR_PENTIUM4;
 620           break;
 621         default:
 622           /* We have no idea.  */
 623           processor = PROCESSOR_GENERIC;
 624         }
 625     }
 626
 627   switch (processor)
 628     {
 629     case PROCESSOR_I386:
 630       /* Default.  */
 631       break;
 632     case PROCESSOR_I486:
 633       cpu = "i486";
 634       break;
 635     case PROCESSOR_PENTIUM:
 636       if (arch && has_mmx)
 637         cpu = "pentium-mmx";
 638       else
 639         cpu = "pentium";
 640       break;
 641     case PROCESSOR_PENTIUMPRO:
 642       switch (model)
 643         {
 644         case 0x1c:
 645         case 0x26:
 646           /* Atom.  */
 647           cpu = "atom";
 648           break;
 649         case 0x0f:
 650           /* Merom.  */
 651         case 0x17:
 652         case 0x1d:
 653           /* Penryn.  */
 654           cpu = "core2";
 655           break;
 656         case 0x1a:
 657         case 0x1e:
 658         case 0x1f:
 659         case 0x2e:
 660           /* Nehalem.  */
 661         case 0x25:
 662         case 0x2c:
 663         case 0x2f:
 664           /* Westmere.  */
 665           cpu = "corei7";
 666           break;
 667         case 0x2a:
 668         case 0x2d:
 669           /* Sandy Bridge.  */
 670           cpu = "corei7-avx";
 671           break;
 672         case 0x3a:
 673         case 0x3e:
 674           /* Ivy Bridge.  */
 675           cpu = "core-avx-i";
 676           break;
 677         case 0x3c:
 678         case 0x45:
 679         case 0x46:
 680           /* Haswell.  */
 681           cpu = "core-avx2";
 682           break;
 683         default:
 684           if (arch)
 685             {
 686               /* This is unknown family 0x6 CPU.  */
 687               if (has_avx2)
 688                 /* Assume Haswell.  */
 689                 cpu = "core-avx2";
 690               else if (has_avx)
 691                 /* Assume Sandy Bridge.  */
 692                 cpu = "corei7-avx";
 693               else if (has_sse4_2)
 694                 {
 695                   if (has_movbe)
 696                     /* Assume SLM.  */
 697                     cpu = "slm";
 698                   else
 699                     /* Assume Core i7.  */
 700                     cpu = "corei7";
 701                 }
 702               else if (has_ssse3)
 703                 {
 704                   if (has_movbe)
 705                     /* Assume Atom.  */
 706                     cpu = "atom";
 707                   else
 708                     /* Assume Core 2.  */
 709                     cpu = "core2";
 710                 }
 711               else if (has_sse3)
 712                 /* It is Core Duo.  */
 713                 cpu = "pentium-m";
 714               else if (has_sse2)
 715                 /* It is Pentium M.  */
 716                 cpu = "pentium-m";
 717               else if (has_sse)
 718                 /* It is Pentium III.  */
 719                 cpu = "pentium3";
 720               else if (has_mmx)
 721                 /* It is Pentium II.  */
 722                 cpu = "pentium2";
 723               else
 724                 /* Default to Pentium Pro.  */
 725                 cpu = "pentiumpro";
 726             }
 727           else
 728             /* For -mtune, we default to -mtune=generic.  */
 729             cpu = "generic";
 730           break;
 731         }
 732       break;
 733     case PROCESSOR_PENTIUM4:
 734       if (has_sse3)
 735         {
 736           if (has_longmode)
 737             cpu = "nocona";
 738           else
 739             cpu = "prescott";
 740         }
 741       else
 742         cpu = "pentium4";
 743       break;
 744     case PROCESSOR_GEODE:
 745       cpu = "geode";
 746       break;
 747     case PROCESSOR_K6:
 748       if (arch && has_3dnow)
 749         cpu = "k6-3";
 750       else
 751         cpu = "k6";
 752       break;
 753     case PROCESSOR_ATHLON:
 754       if (arch && has_sse)
 755         cpu = "athlon-4";
 756       else
 757         cpu = "athlon";
 758       break;
 759     case PROCESSOR_K8:
 760       if (arch && has_sse3)
 761         cpu = "k8-sse3";
 762       else
 763         cpu = "k8";
 764       break;
 765     case PROCESSOR_AMDFAM10:
 766       cpu = "amdfam10";
 767       break;
 768     case PROCESSOR_BDVER1:
 769       cpu = "bdver1";
 770       break;
 771     case PROCESSOR_BDVER2:
 772       cpu = "bdver2";
 773       break;
 774     case PROCESSOR_BDVER3:
 775       cpu = "bdver3";
 776       break;
 777     case PROCESSOR_BDVER4:
 778       cpu = "bdver4";
 779       break;
 780     case PROCESSOR_BTVER1:
 781       cpu = "btver1";
 782       break;
 783     case PROCESSOR_BTVER2:
 784       cpu = "btver2";
 785       break;
 786
 787     default:
 788       /* Use something reasonable.  */
 789       if (arch)
 790         {
 791           if (has_ssse3)
 792             cpu = "core2";
 793           else if (has_sse3)
 794             {
 795               if (has_longmode)
 796                 cpu = "nocona";
 797               else
 798                 cpu = "prescott";
 799             }
 800           else if (has_sse2)
 801             cpu = "pentium4";
 802           else if (has_cmov)
 803             cpu = "pentiumpro";
 804           else if (has_mmx)
 805             cpu = "pentium-mmx";
 806           else if (has_cmpxchg8b)
 807             cpu = "pentium";
 808         }
 809       else
 810         cpu = "generic";
 811     }
 812
 813   if (arch)
 814     {
 815       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
 816       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
 817       const char *sse = has_sse ? " -msse" : " -mno-sse";
 818       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
 819       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
 820       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
 821       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
 822       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 823       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 824       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 825       const char *aes = has_aes ? " -maes" : " -mno-aes";
 826       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 827       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 828       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 829       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 830       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 831       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 832       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 833       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 834       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 835       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 836       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 837       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 838       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 839       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 840       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
 841       const char *hle = has_hle ? " -mhle" : " -mno-hle";
 842       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
 843       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
 844       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
 845       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
 846       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
 847       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
 848       const char *adx = has_adx ? " -madx" : " -mno-adx";
 849       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
 850       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
 851       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
 852       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
 853       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
 854       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
 855       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
 856
 857       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
 858                         sse4a, cx16, sahf, movbe, aes, pclmul,
 859                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
 860                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
 861                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
 862                         fxsr, xsave, xsaveopt, avx512f, avx512er,
 863                         avx512cd, avx512pf, NULL);
 864     }
 865
 866 done:
 867   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
 868 }
 869 #else
 870
 871 /* If we aren't compiling with GCC then the driver will just ignore
 872    -march and -mtune "native" target and will leave to the newly
 873    built compiler to generate code for its default target.  */
 874
 875 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
 876                                    const char **argv ATTRIBUTE_UNUSED)
 877 {
 878   return NULL;
 879 }
 880 #endif /* __GNUC__ */