1 ;; Machine description for GNU compiler,
2 ;; for Atmel AVR micro controllers.
3 ;; Copyright (C) 1998-2013 Free Software Foundation, Inc.
4 ;; Contributed by Georg Lay (avr@gjlay.de)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
24 ;; The purpose of this file is to provide a light-weight DImode
25 ;; implementation for AVR. The trouble with DImode is that tree -> RTL
26 ;; lowering leads to really unpleasant code for operations that don't
27 ;; work byte-wise like NEG, PLUS, MINUS, etc. Defining optabs entries for
28 ;; them won't help because the optab machinery assumes these operations
29 ;; are cheap and does not check if a libgcc implementation is available.
31 ;; The DImode insns are all straight forward -- except movdi. The approach
32 ;; of this implementation is to provide DImode insns without the burden of
35 ;; The caveat is that if there are insns for some mode, there must also be a
36 ;; respective move insn that describes reloads. Therefore, this
37 ;; implementation uses an accumulator-based model with two hard-coded,
38 ;; accumulator-like registers
43 ;; so that no DImode insn contains pseudos or needs reloading.
49 ;; Supported modes that are 8 bytes wide
50 (define_mode_iterator ALL8 [DI DQ UDQ DA UDA TA UTA])
52 (define_mode_iterator ALL8U [UDQ UDA UTA])
53 (define_mode_iterator ALL8S [ DQ DA TA])
55 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
63 (define_expand "add<mode>3"
64 [(parallel [(match_operand:ALL8 0 "general_operand" "")
65 (match_operand:ALL8 1 "general_operand" "")
66 (match_operand:ALL8 2 "general_operand" "")])]
69 rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
71 emit_move_insn (acc_a, operands[1]);
73 if (DImode == <MODE>mode
74 && s8_operand (operands[2], VOIDmode))
76 emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
77 emit_insn (gen_adddi3_const8_insn ());
79 else if (const_operand (operands[2], GET_MODE (operands[2])))
81 emit_insn (gen_add<mode>3_const_insn (operands[2]));
85 emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
86 emit_insn (gen_add<mode>3_insn ());
89 emit_move_insn (operands[0], acc_a);
94 ;; "adddq3_insn" "addudq3_insn"
95 ;; "addda3_insn" "adduda3_insn"
96 ;; "addta3_insn" "adduta3_insn"
97 (define_insn "add<mode>3_insn"
98 [(set (reg:ALL8 ACC_A)
99 (plus:ALL8 (reg:ALL8 ACC_A)
103 [(set_attr "adjust_len" "call")
104 (set_attr "cc" "clobber")])
106 (define_insn "adddi3_const8_insn"
108 (plus:DI (reg:DI ACC_A)
109 (sign_extend:DI (reg:QI REG_X))))]
112 [(set_attr "adjust_len" "call")
113 (set_attr "cc" "clobber")])
115 ;; "adddi3_const_insn"
116 ;; "adddq3_const_insn" "addudq3_const_insn"
117 ;; "addda3_const_insn" "adduda3_const_insn"
118 ;; "addta3_const_insn" "adduta3_const_insn"
119 (define_insn "add<mode>3_const_insn"
120 [(set (reg:ALL8 ACC_A)
121 (plus:ALL8 (reg:ALL8 ACC_A)
122 (match_operand:ALL8 0 "const_operand" "n Ynn")))]
124 && !s8_operand (operands[0], VOIDmode)"
126 return avr_out_plus (insn, operands);
128 [(set_attr "adjust_len" "plus")
129 (set_attr "cc" "clobber")])
132 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
134 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
137 ;; "subdq3" "subudq3"
138 ;; "subda3" "subuda3"
139 ;; "subta3" "subuta3"
140 (define_expand "sub<mode>3"
141 [(parallel [(match_operand:ALL8 0 "general_operand" "")
142 (match_operand:ALL8 1 "general_operand" "")
143 (match_operand:ALL8 2 "general_operand" "")])]
146 rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
148 emit_move_insn (acc_a, operands[1]);
150 if (const_operand (operands[2], GET_MODE (operands[2])))
152 emit_insn (gen_sub<mode>3_const_insn (operands[2]));
156 emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
157 emit_insn (gen_sub<mode>3_insn ());
160 emit_move_insn (operands[0], acc_a);
165 ;; "subdq3_insn" "subudq3_insn"
166 ;; "subda3_insn" "subuda3_insn"
167 ;; "subta3_insn" "subuta3_insn"
168 (define_insn "sub<mode>3_insn"
169 [(set (reg:ALL8 ACC_A)
170 (minus:ALL8 (reg:ALL8 ACC_A)
174 [(set_attr "adjust_len" "call")
175 (set_attr "cc" "set_czn")])
177 ;; "subdi3_const_insn"
178 ;; "subdq3_const_insn" "subudq3_const_insn"
179 ;; "subda3_const_insn" "subuda3_const_insn"
180 ;; "subta3_const_insn" "subuta3_const_insn"
181 (define_insn "sub<mode>3_const_insn"
182 [(set (reg:ALL8 ACC_A)
183 (minus:ALL8 (reg:ALL8 ACC_A)
184 (match_operand:ALL8 0 "const_operand" "n Ynn")))]
187 return avr_out_plus (insn, operands);
189 [(set_attr "adjust_len" "plus")
190 (set_attr "cc" "clobber")])
192 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
193 ;; Signed Saturating Addition and Subtraction
194 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
196 (define_expand "<code_stdname><mode>3"
197 [(set (match_operand:ALL8S 0 "general_operand" "")
198 (ss_addsub:ALL8S (match_operand:ALL8S 1 "general_operand" "")
199 (match_operand:ALL8S 2 "general_operand" "")))]
202 rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
204 emit_move_insn (acc_a, operands[1]);
206 if (const_operand (operands[2], GET_MODE (operands[2])))
208 emit_insn (gen_<code_stdname><mode>3_const_insn (operands[2]));
212 emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
213 emit_insn (gen_<code_stdname><mode>3_insn ());
216 emit_move_insn (operands[0], acc_a);
220 (define_insn "<code_stdname><mode>3_insn"
221 [(set (reg:ALL8S ACC_A)
222 (ss_addsub:ALL8S (reg:ALL8S ACC_A)
225 "%~call __<code_stdname><mode>3"
226 [(set_attr "adjust_len" "call")
227 (set_attr "cc" "clobber")])
229 (define_insn "<code_stdname><mode>3_const_insn"
230 [(set (reg:ALL8S ACC_A)
231 (ss_addsub:ALL8S (reg:ALL8S ACC_A)
232 (match_operand:ALL8S 0 "const_operand" "n Ynn")))]
235 return avr_out_plus (insn, operands);
237 [(set_attr "adjust_len" "plus")
238 (set_attr "cc" "clobber")])
240 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
241 ;; Unsigned Saturating Addition and Subtraction
242 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
244 (define_expand "<code_stdname><mode>3"
245 [(set (match_operand:ALL8U 0 "general_operand" "")
246 (us_addsub:ALL8U (match_operand:ALL8U 1 "general_operand" "")
247 (match_operand:ALL8U 2 "general_operand" "")))]
250 rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
252 emit_move_insn (acc_a, operands[1]);
254 if (const_operand (operands[2], GET_MODE (operands[2])))
256 emit_insn (gen_<code_stdname><mode>3_const_insn (operands[2]));
260 emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
261 emit_insn (gen_<code_stdname><mode>3_insn ());
264 emit_move_insn (operands[0], acc_a);
268 (define_insn "<code_stdname><mode>3_insn"
269 [(set (reg:ALL8U ACC_A)
270 (us_addsub:ALL8U (reg:ALL8U ACC_A)
273 "%~call __<code_stdname><mode>3"
274 [(set_attr "adjust_len" "call")
275 (set_attr "cc" "clobber")])
277 (define_insn "<code_stdname><mode>3_const_insn"
278 [(set (reg:ALL8U ACC_A)
279 (us_addsub:ALL8U (reg:ALL8U ACC_A)
280 (match_operand:ALL8U 0 "const_operand" "n Ynn")))]
283 return avr_out_plus (insn, operands);
285 [(set_attr "adjust_len" "plus")
286 (set_attr "cc" "clobber")])
288 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
290 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
292 (define_expand "negdi2"
293 [(parallel [(match_operand:DI 0 "general_operand" "")
294 (match_operand:DI 1 "general_operand" "")])]
297 rtx acc_a = gen_rtx_REG (DImode, ACC_A);
299 emit_move_insn (acc_a, operands[1]);
300 emit_insn (gen_negdi2_insn ());
301 emit_move_insn (operands[0], acc_a);
305 (define_insn "negdi2_insn"
307 (neg:DI (reg:DI ACC_A)))]
310 [(set_attr "adjust_len" "call")
311 (set_attr "cc" "clobber")])
314 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
316 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
318 (define_expand "conditional_jump"
321 (match_operator 0 "ordered_comparison_operator" [(cc0)
323 (label_ref (match_operand 1 "" ""))
328 ;; "cbranchdq4" "cbranchudq4"
329 ;; "cbranchda4" "cbranchuda4"
330 ;; "cbranchta4" "cbranchuta4"
331 (define_expand "cbranch<mode>4"
332 [(parallel [(match_operand:ALL8 1 "register_operand" "")
333 (match_operand:ALL8 2 "nonmemory_operand" "")
334 (match_operator 0 "ordered_comparison_operator" [(cc0)
336 (label_ref (match_operand 3 "" ""))])]
339 rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
341 emit_move_insn (acc_a, operands[1]);
343 if (s8_operand (operands[2], VOIDmode))
345 emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
346 emit_insn (gen_compare_const8_di2 ());
348 else if (const_operand (operands[2], GET_MODE (operands[2])))
350 emit_insn (gen_compare_const_<mode>2 (operands[2]));
354 emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
355 emit_insn (gen_compare_<mode>2 ());
358 emit_jump_insn (gen_conditional_jump (operands[0], operands[3]));
363 ;; "compare_dq2" "compare_udq2"
364 ;; "compare_da2" "compare_uda2"
365 ;; "compare_ta2" "compare_uta2"
366 (define_insn "compare_<mode>2"
368 (compare (reg:ALL8 ACC_A)
372 [(set_attr "adjust_len" "call")
373 (set_attr "cc" "compare")])
375 (define_insn "compare_const8_di2"
377 (compare (reg:DI ACC_A)
378 (sign_extend:DI (reg:QI REG_X))))]
381 [(set_attr "adjust_len" "call")
382 (set_attr "cc" "compare")])
384 ;; "compare_const_di2"
385 ;; "compare_const_dq2" "compare_const_udq2"
386 ;; "compare_const_da2" "compare_const_uda2"
387 ;; "compare_const_ta2" "compare_const_uta2"
388 (define_insn "compare_const_<mode>2"
390 (compare (reg:ALL8 ACC_A)
391 (match_operand:ALL8 0 "const_operand" "n Ynn")))
392 (clobber (match_scratch:QI 1 "=&d"))]
394 && !s8_operand (operands[0], VOIDmode)"
396 return avr_out_compare64 (insn, operands, NULL);
398 [(set_attr "adjust_len" "compare64")
399 (set_attr "cc" "compare")])
402 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
404 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
406 (define_code_iterator di_shifts
407 [ashift ashiftrt lshiftrt rotate])
409 ;; Shift functions from libgcc are called without defining these insns,
410 ;; but with them we can describe their reduced register footprint.
412 ;; "ashldi3" "ashrdi3" "lshrdi3" "rotldi3"
413 ;; "ashldq3" "ashrdq3" "lshrdq3" "rotldq3"
414 ;; "ashlda3" "ashrda3" "lshrda3" "rotlda3"
415 ;; "ashlta3" "ashrta3" "lshrta3" "rotlta3"
416 ;; "ashludq3" "ashrudq3" "lshrudq3" "rotludq3"
417 ;; "ashluda3" "ashruda3" "lshruda3" "rotluda3"
418 ;; "ashluta3" "ashruta3" "lshruta3" "rotluta3"
419 (define_expand "<code_stdname><mode>3"
420 [(parallel [(match_operand:ALL8 0 "general_operand" "")
421 (di_shifts:ALL8 (match_operand:ALL8 1 "general_operand" "")
422 (match_operand:QI 2 "general_operand" ""))])]
425 rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
427 emit_move_insn (acc_a, operands[1]);
428 emit_move_insn (gen_rtx_REG (QImode, 16), operands[2]);
429 emit_insn (gen_<code_stdname><mode>3_insn ());
430 emit_move_insn (operands[0], acc_a);
434 ;; "ashldi3_insn" "ashrdi3_insn" "lshrdi3_insn" "rotldi3_insn"
435 ;; "ashldq3_insn" "ashrdq3_insn" "lshrdq3_insn" "rotldq3_insn"
436 ;; "ashlda3_insn" "ashrda3_insn" "lshrda3_insn" "rotlda3_insn"
437 ;; "ashlta3_insn" "ashrta3_insn" "lshrta3_insn" "rotlta3_insn"
438 ;; "ashludq3_insn" "ashrudq3_insn" "lshrudq3_insn" "rotludq3_insn"
439 ;; "ashluda3_insn" "ashruda3_insn" "lshruda3_insn" "rotluda3_insn"
440 ;; "ashluta3_insn" "ashruta3_insn" "lshruta3_insn" "rotluta3_insn"
441 (define_insn "<code_stdname><mode>3_insn"
442 [(set (reg:ALL8 ACC_A)
443 (di_shifts:ALL8 (reg:ALL8 ACC_A)
446 "%~call __<code_stdname>di3"
447 [(set_attr "adjust_len" "call")
448 (set_attr "cc" "clobber")])
452 (define_expand "<extend_u>mulsidi3"
453 [(parallel [(match_operand:DI 0 "register_operand" "")
454 (match_operand:SI 1 "general_operand" "")
455 (match_operand:SI 2 "general_operand" "")
456 ;; Just to mention the iterator
457 (clobber (any_extend:SI (match_dup 1)))])]
460 emit_move_insn (gen_rtx_REG (SImode, 22), operands[1]);
461 emit_move_insn (gen_rtx_REG (SImode, 18), operands[2]);
462 emit_insn (gen_<extend_u>mulsidi3_insn());
463 // Use emit_move_insn and not open-coded expand because of missing movdi
464 emit_move_insn (operands[0], gen_rtx_REG (DImode, ACC_A));
470 (define_insn "<extend_u>mulsidi3_insn"
472 (mult:DI (any_extend:DI (reg:SI 18))
473 (any_extend:DI (reg:SI 22))))
474 (clobber (reg:HI REG_X))
475 (clobber (reg:HI REG_Z))]
477 "%~call __<extend_u>mulsidi3"
478 [(set_attr "adjust_len" "call")
479 (set_attr "cc" "clobber")])