gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VD_RE (CREATE, create, 0)
  43   BUILTIN_VDC (COMBINE, combine, 0)
  44   BUILTIN_VB (BINOP, pmul, 0)
  45   BUILTIN_VDQF (UNOP, sqrt, 2)
  46   BUILTIN_VD_BHSI (BINOP, addp, 0)
  47   VAR1 (UNOP, addp, 0, di)
  48   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
  49
  50   BUILTIN_VALL (GETLANE, get_lane, 0)
  51   VAR1 (GETLANE, get_lane, 0, di)
  52
  53   BUILTIN_VD_RE (REINTERP, reinterpretdi, 0)
  54   BUILTIN_VDC (REINTERP, reinterpretv8qi, 0)
  55   BUILTIN_VDC (REINTERP, reinterpretv4hi, 0)
  56   BUILTIN_VDC (REINTERP, reinterpretv2si, 0)
  57   BUILTIN_VDC (REINTERP, reinterpretv2sf, 0)
  58   BUILTIN_VQ (REINTERP, reinterpretv16qi, 0)
  59   BUILTIN_VQ (REINTERP, reinterpretv8hi, 0)
  60   BUILTIN_VQ (REINTERP, reinterpretv4si, 0)
  61   BUILTIN_VQ (REINTERP, reinterpretv4sf, 0)
  62   BUILTIN_VQ (REINTERP, reinterpretv2di, 0)
  63   BUILTIN_VQ (REINTERP, reinterpretv2df, 0)
  64
  65   BUILTIN_VDQ_I (BINOP, dup_lane, 0)
  66   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  67   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  68   BUILTIN_VSDQ_I (BINOP, uqshl, 0)
  69   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  70   BUILTIN_VSDQ_I (BINOP, uqrshl, 0)
  71   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  72   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  73   BUILTIN_VSDQ_I (BINOP, uqadd, 0)
  74   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  75   BUILTIN_VSDQ_I (BINOP, uqsub, 0)
  76   /* Implemented by aarch64_<sur>qadd<mode>.  */
  77   BUILTIN_VSDQ_I (BINOP, suqadd, 0)
  78   BUILTIN_VSDQ_I (BINOP, usqadd, 0)
  79
  80   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  81   BUILTIN_VDC (GETLANE, get_dregoi, 0)
  82   BUILTIN_VDC (GETLANE, get_dregci, 0)
  83   BUILTIN_VDC (GETLANE, get_dregxi, 0)
  84   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  85   BUILTIN_VQ (GETLANE, get_qregoi, 0)
  86   BUILTIN_VQ (GETLANE, get_qregci, 0)
  87   BUILTIN_VQ (GETLANE, get_qregxi, 0)
  88   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
  89   BUILTIN_VQ (SETLANE, set_qregoi, 0)
  90   BUILTIN_VQ (SETLANE, set_qregci, 0)
  91   BUILTIN_VQ (SETLANE, set_qregxi, 0)
  92   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
  93   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
  94   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
  95   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
  96   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
  97   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
  98   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
  99   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
 100   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
 101   BUILTIN_VDC (STORESTRUCT, st2, 0)
 102   BUILTIN_VDC (STORESTRUCT, st3, 0)
 103   BUILTIN_VDC (STORESTRUCT, st4, 0)
 104   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
 105   BUILTIN_VQ (STORESTRUCT, st2, 0)
 106   BUILTIN_VQ (STORESTRUCT, st3, 0)
 107   BUILTIN_VQ (STORESTRUCT, st4, 0)
 108
 109   BUILTIN_VQW (BINOP, saddl2, 0)
 110   BUILTIN_VQW (BINOP, uaddl2, 0)
 111   BUILTIN_VQW (BINOP, ssubl2, 0)
 112   BUILTIN_VQW (BINOP, usubl2, 0)
 113   BUILTIN_VQW (BINOP, saddw2, 0)
 114   BUILTIN_VQW (BINOP, uaddw2, 0)
 115   BUILTIN_VQW (BINOP, ssubw2, 0)
 116   BUILTIN_VQW (BINOP, usubw2, 0)
 117   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 118   BUILTIN_VDW (BINOP, saddl, 0)
 119   BUILTIN_VDW (BINOP, uaddl, 0)
 120   BUILTIN_VDW (BINOP, ssubl, 0)
 121   BUILTIN_VDW (BINOP, usubl, 0)
 122   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 123   BUILTIN_VDW (BINOP, saddw, 0)
 124   BUILTIN_VDW (BINOP, uaddw, 0)
 125   BUILTIN_VDW (BINOP, ssubw, 0)
 126   BUILTIN_VDW (BINOP, usubw, 0)
 127   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 128   BUILTIN_VQ_S (BINOP, shadd, 0)
 129   BUILTIN_VQ_S (BINOP, uhadd, 0)
 130   BUILTIN_VQ_S (BINOP, srhadd, 0)
 131   BUILTIN_VQ_S (BINOP, urhadd, 0)
 132   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 133   BUILTIN_VQN (BINOP, addhn, 0)
 134   BUILTIN_VQN (BINOP, raddhn, 0)
 135   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 136   BUILTIN_VQN (TERNOP, addhn2, 0)
 137   BUILTIN_VQN (TERNOP, raddhn2, 0)
 138
 139   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 140   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 141   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 142   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 143   /* Implemented by aarch64_s<optab><mode>.  */
 144   BUILTIN_VSDQ_I_BHSI (UNOP, sqabs, 0)
 145   BUILTIN_VSDQ_I_BHSI (UNOP, sqneg, 0)
 146
 147   BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
 148   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
 149   BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
 150   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
 151   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 152   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 153   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
 154   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
 155   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
 156   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
 157   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 158   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 159   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 160   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 161   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 162   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 163   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 164   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 165
 166   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 167   BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
 168   BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0)
 169   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 170   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 171   BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
 172   BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0)
 173   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 174   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 175   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 176   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 177   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 178   BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0)
 179   BUILTIN_VDQHS (TERNOP, sqdmulh_laneq, 0)
 180   BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0)
 181   BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq, 0)
 182   BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0)
 183   BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0)
 184
 185   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 186   /* Implemented by aarch64_<sur>shl<mode>.  */
 187   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 188   BUILTIN_VSDQ_I_DI (BINOP, ushl, 0)
 189   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 190   BUILTIN_VSDQ_I_DI (BINOP, urshl, 0)
 191
 192   BUILTIN_VSDQ_I_DI (SHIFTIMM, ashr, 3)
 193   BUILTIN_VSDQ_I_DI (SHIFTIMM, lshr, 3)
 194   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 195   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 196   BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n, 0)
 197   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 198   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 199   BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n, 0)
 200   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 201   BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n, 0)
 202   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 203   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
 204   BUILTIN_VDW (SHIFTIMM, ushll_n, 0)
 205   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 206   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 207   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 208   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 209   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 210   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 211   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 212   BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n, 0)
 213   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 214   BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n, 0)
 215   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 216   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 217   BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n, 0)
 218   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 219   BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n, 0)
 220   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 221   BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n, 0)
 222   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 223   BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n, 0)
 224
 225   /* Implemented by aarch64_cm<cmp><mode>.  */
 226   BUILTIN_VALLDI (BINOP, cmeq, 0)
 227   BUILTIN_VALLDI (BINOP, cmge, 0)
 228   BUILTIN_VALLDI (BINOP, cmgt, 0)
 229   BUILTIN_VALLDI (BINOP, cmle, 0)
 230   BUILTIN_VALLDI (BINOP, cmlt, 0)
 231   /* Implemented by aarch64_cm<cmp><mode>.  */
 232   BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
 233   BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
 234   BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
 235
 236   /* Implemented by reduc_<sur>plus_<mode>.  */
 237   BUILTIN_VALL (UNOP, reduc_splus_, 10)
 238   BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
 239
 240   /* Implemented by reduc_<maxmin_uns>_<mode>.  */
 241   BUILTIN_VDQIF (UNOP, reduc_smax_, 10)
 242   BUILTIN_VDQIF (UNOP, reduc_smin_, 10)
 243   BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10)
 244   BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10)
 245   BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10)
 246   BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10)
 247
 248   /* Implemented by <maxmin><mode>3.
 249      smax variants map to fmaxnm,
 250      smax_nan variants map to fmax.  */
 251   BUILTIN_VDQIF (BINOP, smax, 3)
 252   BUILTIN_VDQIF (BINOP, smin, 3)
 253   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 254   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 255   BUILTIN_VDQF (BINOP, smax_nan, 3)
 256   BUILTIN_VDQF (BINOP, smin_nan, 3)
 257
 258   /* Implemented by <frint_pattern><mode>2.  */
 259   BUILTIN_VDQF (UNOP, btrunc, 2)
 260   BUILTIN_VDQF (UNOP, ceil, 2)
 261   BUILTIN_VDQF (UNOP, floor, 2)
 262   BUILTIN_VDQF (UNOP, nearbyint, 2)
 263   BUILTIN_VDQF (UNOP, rint, 2)
 264   BUILTIN_VDQF (UNOP, round, 2)
 265   BUILTIN_VDQF (UNOP, frintn, 2)
 266
 267   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
 268   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
 269   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
 270   VAR1 (UNOP, lbtruncv2df, 2, v2di)
 271
 272   VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
 273   VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
 274   VAR1 (UNOP, lbtruncuv2df, 2, v2di)
 275
 276   VAR1 (UNOP, lroundv2sf, 2, v2si)
 277   VAR1 (UNOP, lroundv4sf, 2, v4si)
 278   VAR1 (UNOP, lroundv2df, 2, v2di)
 279   /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
 280   VAR1 (UNOP, lroundsf, 2, si)
 281   VAR1 (UNOP, lrounddf, 2, di)
 282
 283   VAR1 (UNOP, lrounduv2sf, 2, v2si)
 284   VAR1 (UNOP, lrounduv4sf, 2, v4si)
 285   VAR1 (UNOP, lrounduv2df, 2, v2di)
 286   VAR1 (UNOP, lroundusf, 2, si)
 287   VAR1 (UNOP, lroundudf, 2, di)
 288
 289   VAR1 (UNOP, lceilv2sf, 2, v2si)
 290   VAR1 (UNOP, lceilv4sf, 2, v4si)
 291   VAR1 (UNOP, lceilv2df, 2, v2di)
 292
 293   VAR1 (UNOP, lceiluv2sf, 2, v2si)
 294   VAR1 (UNOP, lceiluv4sf, 2, v4si)
 295   VAR1 (UNOP, lceiluv2df, 2, v2di)
 296   VAR1 (UNOP, lceilusf, 2, si)
 297   VAR1 (UNOP, lceiludf, 2, di)
 298
 299   VAR1 (UNOP, lfloorv2sf, 2, v2si)
 300   VAR1 (UNOP, lfloorv4sf, 2, v4si)
 301   VAR1 (UNOP, lfloorv2df, 2, v2di)
 302
 303   VAR1 (UNOP, lflooruv2sf, 2, v2si)
 304   VAR1 (UNOP, lflooruv4sf, 2, v4si)
 305   VAR1 (UNOP, lflooruv2df, 2, v2di)
 306   VAR1 (UNOP, lfloorusf, 2, si)
 307   VAR1 (UNOP, lfloorudf, 2, di)
 308
 309   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
 310   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
 311   VAR1 (UNOP, lfrintnv2df, 2, v2di)
 312   VAR1 (UNOP, lfrintnsf, 2, si)
 313   VAR1 (UNOP, lfrintndf, 2, di)
 314
 315   VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
 316   VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
 317   VAR1 (UNOP, lfrintnuv2df, 2, v2di)
 318   VAR1 (UNOP, lfrintnusf, 2, si)
 319   VAR1 (UNOP, lfrintnudf, 2, di)
 320
 321   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
 322   VAR1 (UNOP, floatv2si, 2, v2sf)
 323   VAR1 (UNOP, floatv4si, 2, v4sf)
 324   VAR1 (UNOP, floatv2di, 2, v2df)
 325
 326   VAR1 (UNOP, floatunsv2si, 2, v2sf)
 327   VAR1 (UNOP, floatunsv4si, 2, v4sf)
 328   VAR1 (UNOP, floatunsv2di, 2, v2df)
 329
 330   /* Implemented by
 331      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 332   BUILTIN_VALL (BINOP, zip1, 0)
 333   BUILTIN_VALL (BINOP, zip2, 0)
 334   BUILTIN_VALL (BINOP, uzp1, 0)
 335   BUILTIN_VALL (BINOP, uzp2, 0)
 336   BUILTIN_VALL (BINOP, trn1, 0)
 337   BUILTIN_VALL (BINOP, trn2, 0)
 338
 339   /* Implemented by
 340      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 341   BUILTIN_GPF (UNOP, frecpe, 0)
 342   BUILTIN_GPF (BINOP, frecps, 0)
 343   BUILTIN_GPF (UNOP, frecpx, 0)
 344
 345   BUILTIN_VDQF (UNOP, frecpe, 0)
 346   BUILTIN_VDQF (BINOP, frecps, 0)
 347
 348   BUILTIN_VALLDI (UNOP, abs, 2)
 349
 350   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
 351   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
 352
 353   VAR1 (UNOP, float_extend_lo_, 0, v2df)
 354   VAR1 (UNOP, float_truncate_lo_, 0, v2sf)
 355
 356   /* Implemented by aarch64_ld1<VALL:mode>.  */
 357   BUILTIN_VALL (LOAD1, ld1, 0)
 358
 359   /* Implemented by aarch64_st1<VALL:mode>.  */
 360   BUILTIN_VALL (STORE1, st1, 0)
 361
 362   /* Implemented by fma<mode>4.  */
 363   BUILTIN_VDQF (TERNOP, fma, 4)
 364