| blob | 2bd19445ae0b0c4e3eba7358c3a1515c318f7e99 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
59 /* Not really meaningful values, but at least something. */
60 #ifndef SIMULTANEOUS_PREFETCHES
61 #define SIMULTANEOUS_PREFETCHES 3
62 #endif
63 #ifndef PREFETCH_BLOCK
64 #define PREFETCH_BLOCK 32
65 #endif
66 #ifndef HAVE_prefetch
67 #define HAVE_prefetch 0
68 #define CODE_FOR_prefetch 0
69 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
70 #endif
72 /* Give up the prefetch optimizations once we exceed a given threshhold.
73 It is unlikely that we would be able to optimize something in a loop
74 with so many detected prefetches. */
75 #define MAX_PREFETCHES 100
76 /* The number of prefetch blocks that are beneficial to fetch at once before
77 a loop with a known (and low) iteration count. */
78 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
79 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
80 since it is likely that the data are already in the cache. */
81 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
82 /* The minimal number of prefetch blocks that a loop must consume to make
83 the emitting of prefetch instruction in the body of loop worthwhile. */
84 #define PREFETCH_BLOCKS_IN_LOOP_MIN 6
86 /* Parameterize some prefetch heuristics so they can be turned on and off
87 easily for performance testing on new architecures. These can be
88 defined in target-dependent files. */
90 /* Prefetch is worthwhile only when loads/stores are dense. */
91 #ifndef PREFETCH_ONLY_DENSE_MEM
92 #define PREFETCH_ONLY_DENSE_MEM 1
93 #endif
95 /* Define what we mean by "dense" loads and stores; This value divided by 256
96 is the minimum percentage of memory references that worth prefetching. */
97 #ifndef PREFETCH_DENSE_MEM
98 #define PREFETCH_DENSE_MEM 220
99 #endif
101 /* Do not prefetch for a loop whose iteration count is known to be low. */
102 #ifndef PREFETCH_NO_LOW_LOOPCNT
103 #define PREFETCH_NO_LOW_LOOPCNT 1
104 #endif
106 /* Define what we mean by a "low" iteration count. */
107 #ifndef PREFETCH_LOW_LOOPCNT
108 #define PREFETCH_LOW_LOOPCNT 32
109 #endif
111 /* Do not prefetch for a loop that contains a function call; such a loop is
112 probably not an internal loop. */
113 #ifndef PREFETCH_NO_CALL
114 #define PREFETCH_NO_CALL 1
115 #endif
117 /* Do not prefetch accesses with an extreme stride. */
118 #ifndef PREFETCH_NO_EXTREME_STRIDE
119 #define PREFETCH_NO_EXTREME_STRIDE 1
120 #endif
122 /* Define what we mean by an "extreme" stride. */
123 #ifndef PREFETCH_EXTREME_STRIDE
124 #define PREFETCH_EXTREME_STRIDE 4096
125 #endif
127 /* Do not handle reversed order prefetches (negative stride). */
128 #ifndef PREFETCH_NO_REVERSE_ORDER
129 #define PREFETCH_NO_REVERSE_ORDER 1
130 #endif
132 /* Prefetch even if the GIV is not always executed. */
133 #ifndef PREFETCH_NOT_ALWAYS
134 #define PREFETCH_NOT_ALWAYS 0
135 #endif
137 /* If the loop requires more prefetches than the target can process in
138 parallel then don't prefetch anything in that loop. */
139 #ifndef PREFETCH_LIMIT_TO_SIMULTANEOUS
140 #define PREFETCH_LIMIT_TO_SIMULTANEOUS 1
141 #endif
143 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
144 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
146 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
147 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
148 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
150 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
151 ((REGNO) < FIRST_PSEUDO_REGISTER \
152 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
155 /* Vector mapping INSN_UIDs to luids.
156 The luids are like uids but increase monotonically always.
157 We use them to see whether a jump comes from outside a given loop. */
161 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
162 number the insn is contained in. */
166 /* 1 + largest uid of any insn. */
170 /* 1 + luid of last insn. */
174 /* Number of loops detected in current function. Used as index to the
175 next few tables. */
179 /* Bound on pseudo register number before loop optimization.
180 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
183 /* The value to pass to the next call of reg_scan_update. */
186 #define obstack_chunk_alloc xmalloc
187 #define obstack_chunk_free free
188 \f
189 /* During the analysis of a loop, a chain of `struct movable's
190 is made to record all the movable insns found.
191 Then the entire chain can be scanned to decide which to move. */
193 struct movable
194 {
199 of any registers used within the LIBCALL. */
201 that must be moved with this one. */
204 may be adjusted when matching movables
205 that load the same value are found. */
207 including other movables that force this
208 or match this one. */
212 /* If PARTIAL is 1, GLOBAL means something different:
213 that the reg is live outside the range from where it is set
214 to the following label. */
218 In particular, moving it does not make it
219 invariant. */
221 load SRC, rather than copying INSN. */
223 first insn of a consecutive sets group. */
226 that we should avoid changing when clearing
227 the rest of the reg. */
231 };
236 /* Forward declarations. */
250 #if 0
252 #endif
282 rtx *));
364 {
365 rtx r1;
366 rtx r2;
370 {
371 rtx match;
372 rtx replacement;
373 rtx insn;
376 /* Nonzero iff INSN is between START and END, inclusive. */
377 #define INSN_IN_RANGE_P(INSN, START, END) \
378 (INSN_UID (INSN) < max_uid_for_loop \
379 && INSN_LUID (INSN) >= INSN_LUID (START) \
380 && INSN_LUID (INSN) <= INSN_LUID (END))
382 /* Indirect_jump_in_function is computed once per function. */
390 rtx));
391 \f
392 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
393 copy the value of the strength reduced giv to its original register. */
396 /* Cost of using a register, to normalize the benefits of a giv. */
399 void
401 {
407 }
408 \f
409 /* Compute the mapping from uids to luids.
410 LUIDs are numbers assigned to insns, like uids,
411 except that luids increase monotonically through the code.
412 Start at insn START and stop just before END. Assign LUIDs
413 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
414 static int
418 {
420 rtx insn;
423 {
426 /* Don't assign luids to line-number NOTEs, so that the distance in
427 luids between two insns is not affected by -g. */
431 else
432 /* Give a line number note the same luid as preceding insn. */
434 }
436 }
437 \f
438 /* Entry point of this file. Perform loop optimization
439 on the current function. F is the first insn of the function
440 and DUMPFILE is a stream for output of a trace of actions taken
441 (or 0 if none should be output). */
443 void
445 /* f is the first instruction of a chain of insns for one function */
446 rtx f;
449 {
450 rtx insn;
465 /* Count the number of loops. */
469 {
472 max_loop_num++;
473 }
475 /* Don't waste time if no loops. */
481 /* Get size to use for tables indexed by uids.
482 Leave some space for labels allocated by find_and_verify_loops. */
489 /* Allocate storage for array of loops. */
493 /* Find and process each loop.
494 First, find them, and record them in order of their beginnings. */
497 /* Allocate and initialize auxiliary loop information. */
502 /* Now find all register lifetimes. This must be done after
503 find_and_verify_loops, because it might reorder the insns in the
504 function. */
507 /* This must occur after reg_scan so that registers created by gcse
508 will have entries in the register tables.
510 We could have added a call to reg_scan after gcse_main in toplev.c,
511 but moving this call to init_alias_analysis is more efficient. */
514 /* See if we went too far. Note that get_max_uid already returns
515 one more that the maximum uid of all insn. */
518 /* Now reset it to the actual size we need. See above. */
521 /* find_and_verify_loops has already called compute_luids, but it
522 might have rearranged code afterwards, so we need to recompute
523 the luids now. */
526 /* Don't leave gaps in uid_luid for insns that have been
527 deleted. It is possible that the first or last insn
528 using some register has been deleted by cross-jumping.
529 Make sure that uid_luid for that former insn's uid
530 points to the general area where that insn used to be. */
532 {
536 }
541 /* Determine if the function has indirect jump. On some systems
542 this prevents low overhead loop instructions from being used. */
545 /* Now scan the loops, last ones first, since this means inner ones are done
546 before outer ones. */
548 {
553 }
555 /* If there were lexical blocks inside the loop, they have been
556 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
557 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
558 the BLOCKs as well. */
564 /* Clean up. */
569 }
570 \f
571 /* Returns the next insn, in execution order, after INSN. START and
572 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
573 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
574 insn-stream; it is used with loops that are entered near the
575 bottom. */
577 static rtx
580 rtx insn;
581 {
585 {
587 /* Go to the top of the loop, and continue there. */
589 else
590 /* We're done. */
592 }
595 /* We're done. */
599 }
601 /* Optimize one loop described by LOOP. */
603 /* ??? Could also move memory writes out of loops if the destination address
604 is invariant, the source is invariant, the memory write is not volatile,
605 and if we can prove that no read inside the loop can read this address
606 before the write occurs. If there is a read of this address after the
607 write, then we can also mark the memory read as invariant. */
609 static void
613 {
619 rtx p;
620 /* 1 if we are scanning insns that could be executed zero times. */
622 /* 1 if we are scanning insns that might never be executed
623 due to a subroutine call which might exit before they are reached. */
625 /* Jump insn that enters the loop, or 0 if control drops in. */
627 /* Number of insns in the loop. */
631 /* The SET from an insn, if it is the only SET in the insn. */
633 /* Chain describing insns movable in current loop. */
635 /* Ratio of extra register life span we can justify
636 for saving an instruction. More if loop doesn't call subroutines
637 since in that case saving an insn makes more difference
638 and more registers are available. */
640 /* Nonzero if we are scanning instructions in a sub-loop. */
648 /* Determine whether this loop starts with a jump down to a test at
649 the end. This will occur for a small number of loops with a test
650 that is too complex to duplicate in front of the loop.
652 We search for the first insn or label in the loop, skipping NOTEs.
653 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
654 (because we might have a loop executed only once that contains a
655 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
656 (in case we have a degenerate loop).
658 Note that if we mistakenly think that a loop is entered at the top
659 when, in fact, it is entered at the exit test, the only effect will be
660 slightly poorer optimization. Making the opposite error can generate
661 incorrect code. Since very few loops now start with a jump to the
662 exit test, the code here to detect that case is very conservative. */
665 p != loop_end
671 ;
675 /* If loop end is the end of the current function, then emit a
676 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
677 note insn. This is the position we use when sinking insns out of
678 the loop. */
681 else
684 /* Set up variables describing this loop. */
688 /* If loop has a jump before the first label,
689 the true entry is the target of that jump.
690 Start scan from there.
691 But record in LOOP->TOP the place where the end-test jumps
692 back to so we can scan that after the end of the loop. */
694 {
697 /* Loop entry must be unconditional jump (and not a RETURN) */
700 /* Check to see whether the jump actually
701 jumps out of the loop (meaning it's no loop).
702 This case can happen for things like
703 do {..} while (0). If this label was generated previously
704 by loop, we can't tell anything about it and have to reject
705 the loop. */
707 {
710 }
711 }
713 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
714 as required by loop_reg_used_before_p. So skip such loops. (This
715 test may never be true, but it's best to play it safe.)
717 Also, skip loops where we do not start scanning at a label. This
718 test also rejects loops starting with a JUMP_INSN that failed the
719 test above. */
723 {
728 }
730 /* Allocate extra space for REGs that might be created by load_mems.
731 We allocate a little extra slop as well, in the hopes that we
732 won't have to reallocate the regs array. */
737 {
743 }
745 /* Scan through the loop finding insns that are safe to move.
746 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
747 this reg will be considered invariant for subsequent insns.
748 We consider whether subsequent insns use the reg
749 in deciding whether it is worth actually moving.
751 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
752 and therefore it is possible that the insns we are scanning
753 would never be executed. At such times, we must make sure
754 that it is safe to execute the insn once instead of zero times.
755 When MAYBE_NEVER is 0, all insns will be executed at least once
756 so that is not a problem. */
761 {
765 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
767 #endif
769 {
776 /* Figure out what to use as a source of this insn. If a REG_EQUIV
777 note is given or if a REG_EQUAL note with a constant operand is
778 specified, use it as the source and mark that we should move
779 this insn by calling emit_move_insn rather that duplicating the
780 insn.
782 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
783 is present. */
787 else
788 {
793 {
795 /* A libcall block can use regs that don't appear in
796 the equivalent expression. To move the libcall,
797 we must move those regs too. */
799 }
800 }
802 /* For parallels, add any possible uses to the depencies, as we can't move
803 the insn without resolving them first. */
805 {
807 {
811 }
812 }
814 /* Don't try to optimize a register that was made
815 by loop-optimization for an inner loop.
816 We don't know its life-span, so we can't compute the benefit. */
818 ;
820 than the one where it is set (meaning that
821 something after this point in the loop might
822 depend on its value before the set). */
824 /* And the set is not guaranteed to be executed once
825 the loop starts, or the value before the set is
826 needed before the set occurs...
828 ??? Note we have quadratic behaviour here, mitigated
829 by the fact that the previous test will often fail for
830 large loops. Rather than re-scanning the entire loop
831 each time for register usage, we should build tables
832 of the register usage and use them here instead. */
833 && (maybe_never
835 /* It is unsafe to move the set.
837 This code used to consider it OK to move a set of a variable
838 which was not created by the user and not used in an exit test.
839 That behavior is incorrect and was removed. */
840 ;
845 || (tem1
846 = consec_sets_invariant_p
849 p)))
850 /* If the insn can cause a trap (such as divide by zero),
851 can't move it unless it's guaranteed to be executed
852 once loop is entered. Even a function call might
853 prevent the trap insn from being reached
854 (since it might exit!) */
857 {
861 /* A potential lossage is where we have a case where two insns
862 can be combined as long as they are both in the loop, but
863 we move one of them outside the loop. For large loops,
864 this can lose. The most common case of this is the address
865 of a function being called.
867 Therefore, if this register is marked as being used exactly
868 once if we are in a loop with calls (a "large loop"), see if
869 we can replace the usage of this register with the source
870 of this SET. If we can, delete this insn.
872 Don't do this if P has a REG_RETVAL note or if we have
873 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
885 && (! SMALL_REGISTER_CLASSES
888 /* This test is not redundant; SET_SRC (set) might be
889 a call-clobbered register and the life of REGNO
890 might span a call. */
896 {
897 /* Replace any usage in a REG_EQUAL note. Must copy the
898 new source, so that we don't get rtx sharing between the
899 SET_SOURCE and REG_NOTES of insn p. */
908 }
926 /* Set M->cond if either loop_invariant_p
927 or consec_sets_invariant_p returned 2
928 (only conditionally invariant). */
938 /* Add M to the end of the chain MOVABLES. */
942 {
943 /* It is possible for the first instruction to have a
944 REG_EQUAL note but a non-invariant SET_SRC, so we must
945 remember the status of the first instruction in case
946 the last instruction doesn't have a REG_EQUAL note. */
949 /* Skip this insn, not checking REG_LIBCALL notes. */
951 /* Skip the consecutive insns, if there are any. */
953 /* Back up to the last insn of the consecutive group. */
956 /* We must now reset m->move_insn, m->is_equiv, and possibly
957 m->set_src to correspond to the effects of all the
958 insns. */
962 else
963 {
967 else
970 }
972 }
973 }
974 /* If this register is always set within a STRICT_LOW_PART
975 or set to zero, then its high bytes are constant.
976 So clear them outside the loop and within the loop
977 just load the low bytes.
978 We must check that the machine has an instruction to do so.
979 Also, if the value loaded into the register
980 depends on the same register, this cannot be done. */
990 {
993 {
1007 /* If the insn may not be executed on some cycles,
1008 we can't clear the whole reg; clear just high part.
1009 Not even if the reg is used only within this loop.
1010 Consider this:
1011 while (1)
1012 while (s != t) {
1013 if (foo ()) x = *s;
1014 use (x);
1015 }
1016 Clearing x before the inner loop could clobber a value
1017 being saved from the last time around the outer loop.
1018 However, if the reg is not used outside this loop
1019 and all uses of the register are in the same
1020 basic block as the store, there is no problem.
1022 If this insn was made by loop, we don't know its
1023 INSN_LUID and hence must make a conservative
1024 assumption. */
1027 || (labels_in_range_p
1031 else
1040 /* Add M to the end of the chain MOVABLES. */
1042 }
1043 }
1044 }
1045 /* Past a call insn, we get to insns which might not be executed
1046 because the call might exit. This matters for insns that trap.
1047 Constant and pure call insns always return, so they don't count. */
1050 /* Past a label or a jump, we get to insns for which we
1051 can't count on whether or how many times they will be
1052 executed during each iteration. Therefore, we can
1053 only move out sets of trivial variables
1054 (those not used after the loop). */
1055 /* Similar code appears twice in strength_reduce. */
1057 /* If we enter the loop in the middle, and scan around to the
1058 beginning, don't set maybe_never for that. This must be an
1059 unconditional jump, otherwise the code at the top of the
1060 loop might never be executed. Unconditional jumps are
1061 followed by a barrier then the loop_end. */
1067 {
1068 /* At the virtual top of a converted loop, insns are again known to
1069 be executed: logically, the loop begins here even though the exit
1070 code has been duplicated. */
1074 loop_depth++;
1076 loop_depth--;
1077 }
1078 }
1080 /* If one movable subsumes another, ignore that other. */
1084 /* For each movable insn, see if the reg that it loads
1085 leads when it dies right into another conditionally movable insn.
1086 If so, record that the second insn "forces" the first one,
1087 since the second can be moved only if the first is. */
1091 /* See if there are multiple movable insns that load the same value.
1092 If there are, make all but the first point at the first one
1093 through the `match' field, and add the priorities of them
1094 all together as the priority of the first. */
1098 /* Now consider each movable insn to decide whether it is worth moving.
1099 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1101 Generally this increases code size, so do not move moveables when
1102 optimizing for code size. */
1105 {
1108 /* Recalculate regs->array if move_movables has created new
1109 registers. */
1111 {
1117 ;
1122 }
1123 }
1125 /* Now candidates that still are negative are those not moved.
1126 Change regs->array[I].set_in_loop to indicate that those are not actually
1127 invariant. */
1132 /* Now that we've moved some things out of the loop, we might be able to
1133 hoist even more memory references. */
1136 /* Recalculate regs->array if load_mems has created new registers. */
1144 ;
1151 {
1153 /* Ensure our label doesn't go away. */
1164 }
1167 /* The movable information is required for strength reduction. */
1173 }
1174 \f
1175 /* Add elements to *OUTPUT to record all the pseudo-regs
1176 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1178 void
1182 {
1190 {
1208 }
1212 {
1216 {
1225 }
1226 }
1227 }
1228 \f
1229 /* Check what regs are referred to in the libcall block ending with INSN,
1230 aside from those mentioned in the equivalent value.
1231 If there are none, return 0.
1232 If there are one or more, return an EXPR_LIST containing all of them. */
1234 rtx
1237 {
1242 /* First, find all the regs used in the libcall block
1243 that are not mentioned as inputs to the result. */
1246 {
1251 }
1254 }
1255 \f
1256 /* Return 1 if all uses of REG
1257 are between INSN and the end of the basic block. */
1259 static int
1262 {
1264 rtx p;
1269 /* Search this basic block for the already recorded last use of the reg. */
1271 {
1273 {
1279 /* Ordinary insn: if this is the last use, we win. */
1285 /* Jump insn: if this is the last use, we win. */
1288 /* Otherwise, it's the end of the basic block, so we lose. */
1293 /* It's the end of the basic block, so we lose. */
1298 }
1299 }
1301 /* The "last use" that was recorded can't be found after the first
1302 use. This can happen when the last use was deleted while
1303 processing an inner loop, this inner loop was then completely
1304 unrolled, and the outer loop is always exited after the inner loop,
1305 so that everything after the first use becomes a single basic block. */
1307 }
1308 \f
1309 /* Compute the benefit of eliminating the insns in the block whose
1310 last insn is LAST. This may be a group of insns used to compute a
1311 value directly or can contain a library call. */
1313 static int
1315 rtx last;
1316 {
1317 rtx insn;
1322 {
1325 routine. */
1329 benefit++;
1330 }
1333 }
1334 \f
1335 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1337 static rtx
1339 rtx insn;
1341 {
1343 {
1344 rtx temp;
1346 /* If first insn of libcall sequence, skip to end. */
1347 /* Do this at start of loop, since INSN is guaranteed to
1348 be an insn here. */
1353 do
1356 }
1359 }
1361 /* Ignore any movable whose insn falls within a libcall
1362 which is part of another movable.
1363 We make use of the fact that the movable for the libcall value
1364 was made later and so appears later on the chain. */
1366 static void
1369 {
1373 {
1374 /* Is this a movable for the value of a libcall? */
1377 {
1378 rtx insn;
1379 /* Check for earlier movables inside that range,
1380 and mark them invalid. We cannot use LUIDs here because
1381 insns created by loop.c for prior loops don't have LUIDs.
1382 Rather than reject all such insns from movables, we just
1383 explicitly check each insn in the libcall (since invariant
1384 libcalls aren't that common). */
1389 }
1390 }
1391 }
1393 /* For each movable insn, see if the reg that it loads
1394 leads when it dies right into another conditionally movable insn.
1395 If so, record that the second insn "forces" the first one,
1396 since the second can be moved only if the first is. */
1398 static void
1401 {
1405 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1407 {
1410 /* ??? Could this be a bug? What if CSE caused the
1411 register of M1 to be used after this insn?
1412 Since CSE does not update regno_last_uid,
1413 this insn M->insn might not be where it dies.
1414 But very likely this doesn't matter; what matters is
1415 that M's reg is computed from M1's reg. */
1420 /* If m->consec, m->set_src isn't valid. */
1424 /* Increase the priority of the moving the first insn
1425 since it permits the second to be moved as well. */
1427 {
1431 }
1432 }
1433 }
1434 \f
1435 /* Find invariant expressions that are equal and can be combined into
1436 one register. */
1438 static void
1442 {
1447 /* Regs that are set more than once are not allowed to match
1448 or be matched. I'm no longer sure why not. */
1449 /* Perhaps testing m->consec_sets would be more appropriate here? */
1454 {
1461 /* We want later insns to match the first one. Don't make the first
1462 one match any later ones. So start this loop at m->next. */
1464 /* ??? HACK! move_movables does not verify that the replacement
1465 is valid, which can have disasterous effects with hard regs
1466 and match_dup. Turn combination off for now. */
1469 /* A reg used outside the loop mustn't be eliminated. */
1471 /* A reg used for zero-extending mustn't be eliminated. */
1474 ||
1475 (
1476 /* Can combine regs with different modes loaded from the
1477 same constant only if the modes are the same or
1478 if both are integer modes with M wider or the same
1479 width as M1. The check for integer is redundant, but
1480 safe, since the only case of differing destination
1481 modes with equal sources is when both sources are
1482 VOIDmode, i.e., CONST_INT. */
1488 /* See if the source of M1 says it matches M. */
1495 {
1501 }
1502 }
1504 /* Now combine the regs used for zero-extension.
1505 This can be done for those not marked `global'
1506 provided their lives don't overlap. */
1510 {
1513 /* Combine all the registers for extension from mode MODE.
1514 Don't combine any that are used outside this loop. */
1518 {
1525 {
1526 /* First one: don't check for overlap, just record it. */
1529 }
1531 /* Make sure they extend to the same mode.
1532 (Almost always true.) */
1536 /* We already have one: check for overlap with those
1537 already combined together. */
1544 /* No overlap: we can combine this with the others. */
1550 overlap:
1551 ;
1552 }
1553 }
1555 /* Clean up. */
1557 }
1559 /* Returns the number of movable instructions in LOOP that were not
1560 moved outside the loop. */
1562 static int
1565 {
1574 }
1576 \f
1577 /* Return 1 if regs X and Y will become the same if moved. */
1579 static int
1583 {
1600 }
1602 /* Return 1 if X and Y are identical-looking rtx's.
1603 This is the Lisp function EQUAL for rtx arguments.
1605 If two registers are matching movables or a movable register and an
1606 equivalent constant, consider them equal. */
1608 static int
1613 {
1627 /* If we have a register and a constant, they may sometimes be
1628 equal. */
1631 {
1636 }
1639 {
1644 }
1646 /* Otherwise, rtx's of different codes cannot be equal. */
1650 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1651 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1656 /* These three types of rtx's can be compared nonrecursively. */
1665 /* Compare the elements. If any pair of corresponding elements
1666 fail to match, return 0 for the whole things. */
1670 {
1672 {
1684 /* Two vectors must have the same length. */
1688 /* And the corresponding elements must match. */
1707 /* These are just backpointers, so they don't matter. */
1713 /* It is believed that rtx's at this level will never
1714 contain anything but integers and other rtx's,
1715 except for within LABEL_REFs and SYMBOL_REFs. */
1718 }
1719 }
1721 }
1722 \f
1723 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1724 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1725 references is incremented once for each added note. */
1727 static void
1729 rtx x;
1730 rtx insns;
1731 {
1735 rtx insn;
1738 {
1739 /* This code used to ignore labels that referred to dispatch tables to
1740 avoid flow generating (slighly) worse code.
1742 We no longer ignore such label references (see LABEL_REF handling in
1743 mark_jump_label for additional information). */
1746 {
1751 }
1752 }
1756 {
1762 }
1763 }
1764 \f
1765 /* Scan MOVABLES, and move the insns that deserve to be moved.
1766 If two matching movables are combined, replace one reg with the
1767 other throughout. */
1769 static void
1775 {
1780 rtx p;
1783 /* Map of pseudo-register replacements to handle combining
1784 when we move several insns that load the same value
1785 into different pseudo-registers. */
1790 {
1791 /* Describe this movable insn. */
1794 {
1815 }
1817 /* Ignore the insn if it's already done (it matched something else).
1818 Otherwise, see if it is now safe to move. */
1830 {
1832 rtx p;
1835 /* We have an insn that is safe to move.
1836 Compute its desirability. */
1847 /* An insn MUST be moved if we already moved something else
1848 which is safe only if this one is moved too: that is,
1849 if already_moved[REGNO] is nonzero. */
1851 /* An insn is desirable to move if the new lifetime of the
1852 register is no more than THRESHOLD times the old lifetime.
1853 If it's not desirable, it means the loop is so big
1854 that moving won't speed things up much,
1855 and it is liable to make register usage worse. */
1857 /* It is also desirable to move if it can be moved at no
1858 extra cost because something else was already moved. */
1861 || flag_move_all_movables
1866 {
1871 /* Now move the insns that set the reg. */
1874 {
1877 /* Find the end of this chain of matching regs.
1878 Thus, we load each reg in the chain from that one reg.
1879 And that reg is loaded with 0 directly,
1880 since it has ->match == 0. */
1886 /* Mark the moved, invariant reg as being allowed to
1887 share a hard reg with the other matching invariant. */
1891 regs_may_share
1894 regs_may_share));
1902 }
1903 /* If we are to re-generate the item being moved with a
1904 new move insn, first delete what we have and then emit
1905 the move insn before the loop. */
1907 {
1911 {
1912 /* If this is the first insn of a library call sequence,
1913 skip to the end. */
1918 /* If this is the last insn of a libcall sequence, then
1919 delete every insn in the sequence except the last.
1920 The last insn is handled in the normal manner. */
1923 {
1927 }
1932 /* simplify_giv_expr expects that it can walk the insns
1933 at m->insn forwards and see this old sequence we are
1934 tossing here. delete_insn does preserve the next
1935 pointers, but when we skip over a NOTE we must fix
1936 it up. Otherwise that code walks into the non-deleted
1937 insn stream. */
1940 }
1959 /* The more regs we move, the less we like moving them. */
1961 }
1962 else
1963 {
1965 {
1968 /* If first insn of libcall sequence, skip to end. */
1969 /* Do this at start of loop, since p is guaranteed to
1970 be an insn here. */
1975 /* If last insn of libcall sequence, move all
1976 insns except the last before the loop. The last
1977 insn is handled in the normal manner. */
1980 {
1988 {
1989 rtx body;
1990 rtx n;
1991 rtx next;
1998 /* Find the next insn after TEMP,
1999 not counting USE or NOTE insns. */
2007 /* If that is the call, this may be the insn
2008 that loads the function address.
2010 Extract the function address from the insn
2011 that loads it into a register.
2012 If this insn was cse'd, we get incorrect code.
2014 So emit a new move insn that copies the
2015 function address into the register that the
2016 call insn will use. flow.c will delete any
2017 redundant stores that we have created. */
2022 NULL_RTX)))
2023 {
2029 }
2030 /* We have the call insn.
2031 If it uses the register we suspect it might,
2032 load it with the correct address directly. */
2037 gen_move_insn
2041 {
2043 /* Because the USAGE information potentially
2044 contains objects other than hard registers
2045 we need to copy it. */
2049 }
2050 else
2059 }
2062 }
2064 {
2065 /* P sets REG to zero; but we should clear only
2066 the bits that are not covered by the mode
2067 m->savemode. */
2069 rtx sequence;
2070 rtx tem;
2073 tem = expand_simple_binop
2086 }
2088 {
2090 /* Because the USAGE information potentially
2091 contains objects other than hard registers
2092 we need to copy it. */
2096 }
2098 {
2099 rtx seq;
2100 /* The SET_SRC might not be invariant, so we must
2101 use the REG_EQUAL note. */
2114 }
2115 else
2119 {
2123 /* If there is a REG_EQUAL note present whose value
2124 is not loop invariant, then delete it, since it
2125 may cause problems with later optimization passes.
2126 It is possible for cse to create such notes
2127 like this as a result of record_jump_cond. */
2132 }
2141 /* If library call, now fix the REG_NOTES that contain
2142 insn pointers, namely REG_LIBCALL on FIRST
2143 and REG_RETVAL on I1. */
2145 {
2149 }
2155 /* simplify_giv_expr expects that it can walk the insns
2156 at m->insn forwards and see this old sequence we are
2157 tossing here. delete_insn does preserve the next
2158 pointers, but when we skip over a NOTE we must fix
2159 it up. Otherwise that code walks into the non-deleted
2160 insn stream. */
2163 }
2165 /* The more regs we move, the less we like moving them. */
2167 }
2169 /* Any other movable that loads the same register
2170 MUST be moved. */
2173 /* This reg has been moved out of one loop. */
2176 /* The reg set here is now invariant. */
2178 {
2182 }
2186 /* Change the length-of-life info for the register
2187 to say it lives at least the full length of this loop.
2188 This will help guide optimizations in outer loops. */
2191 /* This is the old insn before all the moved insns.
2192 We can't use the moved insn because it is out of range
2193 in uid_luid. Only the old insns have luids. */
2198 /* Combine with this moved insn any other matching movables. */
2203 {
2204 rtx temp;
2206 /* Schedule the reg loaded by M1
2207 for replacement so that shares the reg of M.
2208 If the modes differ (only possible in restricted
2209 circumstances, make a SUBREG.
2211 Note this assumes that the target dependent files
2212 treat REG and SUBREG equally, including within
2213 GO_IF_LEGITIMATE_ADDRESS and in all the
2214 predicates since we never verify that replacing the
2215 original register with a SUBREG results in a
2216 recognizable insn. */
2219 else
2224 /* Get rid of the matching insn
2225 and prevent further processing of it. */
2228 /* if library call, delete all insns. */
2230 NULL_RTX)))
2232 else
2235 /* Any other movable that loads the same register
2236 MUST be moved. */
2239 /* The reg merged here is now invariant,
2240 if the reg it matches is invariant. */
2242 {
2246 i++)
2248 }
2249 }
2250 }
2253 }
2259 }
2264 /* Go through all the instructions in the loop, making
2265 all the register substitutions scheduled in REG_MAP. */
2269 {
2273 }
2275 /* Clean up. */
2278 }
2281 static void
2285 {
2288 else
2291 }
2294 static void
2297 {
2302 {
2305 }
2306 }
2307 \f
2308 #if 0
2309 /* Scan X and replace the address of any MEM in it with ADDR.
2310 REG is the address that MEM should have before the replacement. */
2312 static void
2315 {
2324 {
2336 /* Short cut for very common case. */
2341 /* Short cut for very common case. */
2346 /* If this MEM uses a reg other than the one we expected,
2347 something is wrong. */
2355 }
2359 {
2363 {
2367 }
2368 }
2369 }
2370 #endif
2371 \f
2372 /* Return the number of memory refs to addresses that vary
2373 in the rtx X. */
2375 static int
2378 rtx x;
2379 {
2390 {
2407 }
2412 {
2416 {
2420 }
2421 }
2423 }
2424 \f
2425 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2426 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2427 `unknown_address_altered', `unknown_constant_address_altered', and
2428 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2429 list `store_mems' in LOOP. */
2431 static void
2434 {
2436 rtx insn;
2440 /* The label after END. Jumping here is just like falling off the
2441 end of the loop. We use next_nonnote_insn instead of next_label
2442 as a hedge against the (pathological) case where some actual insn
2443 might end up between the two. */
2465 {
2467 {
2470 }
2471 }
2475 {
2477 {
2480 {
2482 /* Count number of loops contained in this one. */
2484 }
2491 {
2494 }
2502 {
2506 {
2510 {
2513 }
2514 else
2515 {
2518 }
2520 do
2521 {
2523 {
2525 {
2526 /* Something tricky. */
2529 }
2532 {
2533 /* A jump outside the current loop. */
2536 }
2537 }
2541 }
2543 }
2544 else
2545 {
2546 /* A return, or something tricky. */
2548 }
2549 }
2550 /* FALLTHRU */
2571 }
2572 }
2574 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2576 anywhere. */
2578 /* We don't want loads for MEMs moved to a location before the
2579 one at which their stack memory becomes allocated. (Note
2580 that this is not a problem for malloc, etc., since those
2581 require actual function calls. */
2582 && ! current_function_calls_alloca
2583 /* There are ways to leave the loop other than falling off the
2584 end. */
2590 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2591 that loop_invariant_p and load_mems can use true_dependence
2592 to determine what is really clobbered. */
2594 {
2597 loop_info->store_mems
2599 }
2601 {
2605 loop_info->store_mems
2607 }
2608 }
2609 \f
2610 /* Scan the function looking for loops. Record the start and end of each loop.
2611 Also mark as invalid loops any loops that contain a setjmp or are branched
2612 to from outside the loop. */
2614 static void
2616 rtx f;
2618 {
2619 rtx insn;
2620 rtx label;
2630 /* If there are jumps to undefined labels,
2631 treat them as jumps out of any/all loops.
2632 This also avoids writing past end of tables when there are no loops. */
2635 /* Find boundaries of loops, mark which loops are contained within
2636 loops, and invalidate loops that have setjmp. */
2641 {
2644 {
2648 num_loops++;
2672 }
2676 {
2677 /* In this case, we must invalidate our current loop and any
2678 enclosing loop. */
2680 {
2686 }
2687 }
2689 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2690 enclosing loop, but this doesn't matter. */
2692 }
2694 /* Any loop containing a label used in an initializer must be invalidated,
2695 because it can be jumped into from anywhere. */
2698 {
2702 }
2704 /* Any loop containing a label used for an exception handler must be
2705 invalidated, because it can be jumped into from anywhere. */
2708 {
2712 }
2714 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2715 loop that it is not contained within, that loop is marked invalid.
2716 If any INSN or CALL_INSN uses a label's address, then the loop containing
2717 that label is marked invalid, because it could be jumped into from
2718 anywhere.
2720 Also look for blocks of code ending in an unconditional branch that
2721 exits the loop. If such a block is surrounded by a conditional
2722 branch around the block, move the block elsewhere (see below) and
2723 invert the jump to point to the code block. This may eliminate a
2724 label in our loop and will simplify processing by both us and a
2725 possible second cse pass. */
2729 {
2733 {
2736 {
2740 }
2741 }
2748 /* See if this is an unconditional branch outside the loop. */
2756 {
2757 rtx p;
2763 /* Go backwards until we reach the start of the loop, a label,
2764 or a JUMP_INSN. */
2771 ;
2773 /* Check for the case where we have a jump to an inner nested
2774 loop, and do not perform the optimization in that case. */
2777 {
2780 {
2785 }
2786 }
2788 /* Make sure that the target of P is within the current loop. */
2794 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2795 we have a block of code to try to move.
2797 We look backward and then forward from the target of INSN
2798 to find a BARRIER at the same loop depth as the target.
2799 If we find such a BARRIER, we make a new label for the start
2800 of the block, invert the jump in P and point it to that label,
2801 and move the block of code to the spot we found. */
2806 /* Just ignore jumps to labels that were never emitted.
2807 These always indicate compilation errors. */
2811 /* If it's not safe to move the sequence, then we
2812 mustn't try. */
2815 {
2816 rtx target
2820 rtx tmp;
2822 /* Search for possible garbage past the conditional jumps
2823 and look for the last barrier. */
2831 /* Don't move things inside a tablejump. */
2844 /* Don't move things inside a tablejump. */
2855 {
2859 /* Ensure our label doesn't go away. */
2862 /* Verify that uid_loop is large enough and that
2863 we can invert P. */
2865 {
2868 /* If no suitable BARRIER was found, create a suitable
2869 one before TARGET. Since TARGET is a fall through
2870 path, we'll need to insert an jump around our block
2871 and add a BARRIER before TARGET.
2873 This creates an extra unconditional jump outside
2874 the loop. However, the benefits of removing rarely
2875 executed instructions from inside the loop usually
2876 outweighs the cost of the extra unconditional jump
2877 outside the loop. */
2879 {
2880 rtx temp;
2887 }
2889 /* Include the BARRIER after INSN and copy the
2890 block after LOC. */
2895 /* All those insns are now in TARGET_LOOP. */
2901 /* The label jumped to by INSN is no longer a loop
2902 exit. Unless INSN does not have a label (e.g.,
2903 it is a RETURN insn), search loop->exit_labels
2904 to find its label_ref, and remove it. Also turn
2905 off LABEL_OUTSIDE_LOOP_P bit. */
2907 {
2909 r;
2912 {
2916 else
2919 }
2925 /* If we didn't find it, then something is
2926 wrong. */
2929 }
2931 /* P is now a jump outside the loop, so it must be put
2932 in loop->exit_labels, and marked as such.
2933 The easiest way to do this is to just call
2934 mark_loop_jump again for P. */
2937 /* If INSN now jumps to the insn after it,
2938 delete INSN. */
2943 }
2945 /* Continue the loop after where the conditional
2946 branch used to jump, since the only branch insn
2947 in the block (if it still remains) is an inter-loop
2948 branch and hence needs no processing. */
2954 /* This loop will be continued with NEXT_INSN (insn). */
2956 }
2957 }
2958 }
2959 }
2960 }
2962 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2963 loops it is contained in, mark the target loop invalid.
2965 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2967 static void
2969 rtx x;
2971 {
2977 {
2989 /* There could be a label reference in here. */
3001 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3013 /* Link together all labels that branch outside the loop. This
3014 is used by final_[bg]iv_value and the loop unrolling code. Also
3015 mark this LABEL_REF so we know that this branch should predict
3016 false. */
3018 /* A check to make sure the label is not in an inner nested loop,
3019 since this does not count as a loop exit. */
3021 {
3026 }
3027 else
3031 {
3040 }
3042 /* If this is inside a loop, but not in the current loop or one enclosed
3043 by it, it invalidates at least one loop. */
3048 /* We must invalidate every nested loop containing the target of this
3049 label, except those that also contain the jump insn. */
3052 {
3053 /* Stop when we reach a loop that also contains the jump insn. */
3058 /* If we get here, we know we need to invalidate a loop. */
3065 }
3069 /* If this is not setting pc, ignore. */
3091 /* Strictly speaking this is not a jump into the loop, only a possible
3092 jump out of the loop. However, we have no way to link the destination
3093 of this jump onto the list of exit labels. To be safe we mark this
3094 loop and any containing loops as invalid. */
3096 {
3098 {
3104 }
3105 }
3107 }
3108 }
3109 \f
3110 /* Return nonzero if there is a label in the range from
3111 insn INSN to and including the insn whose luid is END
3112 INSN must have an assigned luid (i.e., it must not have
3113 been previously created by loop.c). */
3115 static int
3117 rtx insn;
3119 {
3121 {
3125 }
3128 }
3130 /* Record that a memory reference X is being set. */
3132 static void
3134 rtx x;
3135 rtx y ATTRIBUTE_UNUSED;
3137 {
3143 /* Count number of memory writes.
3144 This affects heuristics in strength_reduce. */
3147 /* BLKmode MEM means all memory is clobbered. */
3149 {
3152 else
3156 }
3160 }
3162 /* X is a value modified by an INSN that references a biv inside a loop
3163 exit test (ie, X is somehow related to the value of the biv). If X
3164 is a pseudo that is used more than once, then the biv is (effectively)
3165 used more than once. DATA is a pointer to a loop_regs structure. */
3167 static void
3169 rtx x;
3170 rtx y ATTRIBUTE_UNUSED;
3172 {
3187 /* If we do not have usage information, or if we know the register
3188 is used more than once, note that fact for check_dbra_loop. */
3193 }
3194 \f
3195 /* Return nonzero if the rtx X is invariant over the current loop.
3197 The value is 2 if we refer to something only conditionally invariant.
3199 A memory ref is invariant if it is not volatile and does not conflict
3200 with anything stored in `loop_info->store_mems'. */
3202 int
3205 rtx x;
3206 {
3213 rtx mem_list_entry;
3219 {
3227 /* A LABEL_REF is normally invariant, however, if we are unrolling
3228 loops, and this label is inside the loop, then it isn't invariant.
3229 This is because each unrolled copy of the loop body will have
3230 a copy of this label. If this was invariant, then an insn loading
3231 the address of this label into a register might get moved outside
3232 the loop, and then each loop body would end up using the same label.
3234 We don't know the loop bounds here though, so just fail for all
3235 labels. */
3238 else
3247 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3248 since the reg might be set by initialization within the loop. */
3265 /* Volatile memory references must be rejected. Do this before
3266 checking for read-only items, so that volatile read-only items
3267 will be rejected also. */
3271 /* See if there is any dependence between a store and this load. */
3274 {
3280 }
3282 /* It's not invalidated by a store in memory
3283 but we must still verify the address is invariant. */
3287 /* Don't mess with insns declared volatile. */
3294 }
3298 {
3300 {
3306 }
3308 {
3311 {
3317 }
3319 }
3320 }
3323 }
3324 \f
3325 /* Return nonzero if all the insns in the loop that set REG
3326 are INSN and the immediately following insns,
3327 and if each of those insns sets REG in an invariant way
3328 (not counting uses of REG in them).
3330 The value is 2 if some of these insns are only conditionally invariant.
3332 We assume that INSN itself is the first set of REG
3333 and that its source is invariant. */
3335 static int
3340 {
3344 rtx temp;
3345 /* Number of sets we have to insist on finding after INSN. */
3351 /* If N_SETS hit the limit, we can't rely on its value. */
3358 {
3360 rtx set;
3365 /* If library call, skip to end of it. */
3374 {
3379 {
3380 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3381 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3382 notes are OK. */
3388 }
3389 }
3391 count--;
3393 {
3396 }
3397 }
3400 /* If loop_invariant_p ever returned 2, we return 2. */
3402 }
3404 #if 0
3405 /* I don't think this condition is sufficient to allow INSN
3406 to be moved, so we no longer test it. */
3408 /* Return 1 if all insns in the basic block of INSN and following INSN
3409 that set REG are invariant according to TABLE. */
3411 static int
3415 {
3420 {
3429 {
3432 }
3433 }
3434 }
3436 \f
3437 /* Look at all uses (not sets) of registers in X. For each, if it is
3438 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3439 a different insn, set USAGE[REGNO] to const0_rtx. */
3441 static void
3444 rtx insn;
3445 rtx x;
3446 {
3458 {
3459 /* Don't count SET_DEST if it is a REG; otherwise count things
3460 in SET_DEST because if a register is partially modified, it won't
3461 show up as a potential movable so we don't care how USAGE is set
3462 for it. */
3466 }
3467 else
3469 {
3475 }
3476 }
3477 \f
3478 /* Count and record any set in X which is contained in INSN. Update
3479 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3480 in X. */
3482 static void
3487 {
3489 /* Don't move a reg that has an explicit clobber.
3490 It's not worth the pain to try to do it correctly. */
3494 {
3502 {
3506 {
3507 /* If this is the first setting of this reg
3508 in current basic block, and it was set before,
3509 it must be set in two basic blocks, so it cannot
3510 be moved out of the loop. */
3514 /* If this is not first setting in current basic block,
3515 see if reg was used in between previous one and this.
3516 If so, neither one can be moved. */
3523 }
3524 }
3525 }
3526 }
3527 \f
3528 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3529 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3530 contained in insn INSN is used by any insn that precedes INSN in
3531 cyclic order starting from the loop entry point.
3533 We don't want to use INSN_LUID here because if we restrict INSN to those
3534 that have a valid INSN_LUID, it means we cannot move an invariant out
3535 from an inner loop past two loops. */
3537 static int
3541 {
3543 rtx p;
3545 /* Scan forward checking for register usage. If we hit INSN, we
3546 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3548 {
3554 }
3557 }
3558 \f
3560 /* Information we collect about arrays that we might want to prefetch. */
3561 struct prefetch_info
3562 {
3566 index. */
3567 HOST_WIDE_INT index;
3569 iteration. */
3571 prefetch area in one iteration. */
3573 This is set only for loops with known
3574 iteration counts and is 0xffffffff
3575 otherwise. */
3578 /* 1 for those chosen for prefetching. */
3580 /* 1 for those chosen for prefetching. */
3581 };
3583 /* Data used by check_store function. */
3584 struct check_store_data
3585 {
3586 rtx mem_address;
3588 };
3594 /* Set mem_write when mem_address is found. Used as callback to
3595 note_stores. */
3596 static void
3600 {
3605 }
3606 \f
3607 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3608 important to get some addresses combined. Later more sophisticated
3609 transformations can be added when necesary.
3611 ??? Same trick with swapping operand is done at several other places.
3612 It can be nice to develop some common way to handle this. */
3614 static int
3617 {
3631 {
3636 }
3637 /* Compare the elements. If any pair of corresponding elements fails to
3638 match, return 0 for the whole thing. */
3642 {
3644 {
3656 /* Two vectors must have the same length. */
3660 /* And the corresponding elements must match. */
3678 /* These are just backpointers, so they don't matter. */
3684 /* It is believed that rtx's at this level will never
3685 contain anything but integers and other rtx's,
3686 except for within LABEL_REFs and SYMBOL_REFs. */
3689 }
3690 }
3692 }
3693 \f
3694 /* Remove constant addition value from the expression X (when present)
3695 and return it. */
3697 static HOST_WIDE_INT
3700 {
3704 /* Avoid clobbering a shared CONST expression. */
3706 {
3710 {
3713 }
3715 }
3718 {
3721 }
3723 /* For plus expression recurse on ourself. */
3725 {
3729 /* In case our parameter was constant, remove extra zero from the
3730 expression. */
3735 }
3738 }
3740 /* Attempt to identify accesses to arrays that are most likely to cause cache
3741 misses, and emit prefetch instructions a few prefetch blocks forward.
3743 To detect the arrays we use the GIV information that was collected by the
3744 strength reduction pass.
3746 The prefetch instructions are generated after the GIV information is done
3747 and before the strength reduction process. The new GIVs are injected into
3748 the strength reduction tables, so the prefetch addresses are optimized as
3749 well.
3751 GIVs are split into base address, stride, and constant addition values.
3752 GIVs with the same address, stride and close addition values are combined
3753 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3754 for write instructions can be used for the block we write to, on machines
3755 that support write prefetches.
3757 Several heuristics are used to determine when to prefetch. They are
3758 controlled by defined symbols that can be overridden for each target. */
3760 static void
3763 {
3777 /* Consider only loops w/o calls. When a call is done, the loop is probably
3778 slow enough to read the memory. */
3780 {
3785 }
3790 {
3795 }
3797 /* Search all induction variables and pick those interesting for the prefetch
3798 machinery. */
3800 {
3806 /* Expect all BIVs to be executed in each iteration. This makes our
3807 analysis more conservative. */
3809 {
3810 /* Discard non-constant additions that we can't handle well yet, and
3811 BIVs that are executed multiple times; such BIVs ought to be
3812 handled in the nested loop. We accept not_every_iteration BIVs,
3813 since these only result in larger strides and make our
3814 heuristics more conservative.
3815 ??? What does the last sentence mean? */
3817 {
3819 {
3825 }
3827 }
3830 {
3832 {
3838 }
3840 }
3844 }
3850 {
3851 rtx address;
3852 rtx temp;
3855 HOST_WIDE_INT stride;
3859 /* There are several reasons why an induction variable is not
3860 interesting to us. */
3862 /* We are interested only in constant stride memory references
3863 in order to be able to compute density easily. */
3865 /* Don't handle reversed order prefetches, since they are usually
3866 ineffective. Later we may be able to reverse such BIVs. */
3867 || (PREFETCH_NO_REVERSE_ORDER
3869 /* Prefetching of accesses with such an extreme stride is probably
3870 not worthwhile, either. */
3871 || (PREFETCH_NO_EXTREME_STRIDE
3873 /* Ignore GIVs with varying add values; we can't predict the
3874 value for the next iteration. */
3876 /* Ignore GIVs in the nested loops; they ought to have been
3877 handled already. */
3879 {
3884 }
3886 /* Determine the pointer to the basic array we are examining. It is
3887 the sum of the BIV's initial value and the GIV's add_val. */
3900 /* When the GIV is not always executed, we might be better off by
3901 not dirtying the cache pages. */
3905 /* Attempt to find another prefetch to the same array and see if we
3906 can merge this one. */
3910 {
3911 /* In case both access same array (same location
3912 just with small difference in constant indexes), merge
3913 the prefetches. Just do the later and the earlier will
3914 get prefetched from previous iteration.
3915 4096 is artificial threshold. It should not be too small,
3916 but also not bigger than small portion of memory usually
3917 traversed by single loop. */
3919 {
3928 }
3931 {
3936 }
3937 }
3939 /* Merging failed. */
3941 {
3949 num_prefetches++;
3951 {
3956 }
3957 }
3958 }
3959 }
3962 {
3963 /* Attempt to calculate the number of bytes fetched by the loop.
3964 Avoid overflow. */
3969 else
3972 /* Prefetch is worthwhile only when the loads/stores are dense. */
3977 {
3982 }
3983 else
3987 {
3991 num_real_write_prefetches
3993 }
3994 }
3997 {
3999 {
4014 }
4018 }
4029 {
4031 {
4036 {
4038 rtx insn;
4043 /* We can save some effort by offsetting the address on
4044 architectures with offsettable memory references. */
4047 else
4048 {
4054 }
4056 /* Make sure the address operand is valid for prefetch. */
4063 before_insn);
4065 /* Check all insns emitted and record the new GIV
4066 information. */
4069 {
4074 }
4075 }
4076 }
4079 {
4082 /* Emit INSNs before the loop to fetch the first cache lines. */
4086 {
4098 loop_start);
4099 }
4100 }
4101 }
4104 }
4105 \f
4106 /* A "basic induction variable" or biv is a pseudo reg that is set
4107 (within this loop) only by incrementing or decrementing it. */
4108 /* A "general induction variable" or giv is a pseudo reg whose
4109 value is a linear function of a biv. */
4111 /* Bivs are recognized by `basic_induction_var';
4112 Givs by `general_induction_var'. */
4114 /* Communication with routines called via `note_stores'. */
4118 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4122 /* ??? Unfinished optimizations, and possible future optimizations,
4123 for the strength reduction code. */
4125 /* ??? The interaction of biv elimination, and recognition of 'constant'
4126 bivs, may cause problems. */
4128 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4129 performance problems.
4131 Perhaps don't eliminate things that can be combined with an addressing
4132 mode. Find all givs that have the same biv, mult_val, and add_val;
4133 then for each giv, check to see if its only use dies in a following
4134 memory address. If so, generate a new memory address and check to see
4135 if it is valid. If it is valid, then store the modified memory address,
4136 otherwise, mark the giv as not done so that it will get its own iv. */
4138 /* ??? Could try to optimize branches when it is known that a biv is always
4139 positive. */
4141 /* ??? When replace a biv in a compare insn, we should replace with closest
4142 giv so that an optimized branch can still be recognized by the combiner,
4143 e.g. the VAX acb insn. */
4145 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4146 was rerun in loop_optimize whenever a register was added or moved.
4147 Also, some of the optimizations could be a little less conservative. */
4148 \f
4149 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4150 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4151 callback.
4153 NOT_EVERY_ITERATION if current insn is not executed at least once for every
4154 loop iteration except for the last one.
4156 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4157 loop iteration.
4158 */
4159 void
4162 loop_insn_callback fncall;
4163 {
4164 /* This is 1 if current insn is not executed at least once for every loop
4165 iteration. */
4170 rtx p;
4172 /* If loop_scan_start points to the loop exit test, we have to be wary of
4173 subversive use of gotos inside expression statements. */
4177 /* Scan through loop to find all possible bivs. */
4182 {
4185 /* Past CODE_LABEL, we get to insns that may be executed multiple
4186 times. The only way we can be sure that they can't is if every
4187 jump insn between here and the end of the loop either
4188 returns, exits the loop, is a jump to a location that is still
4189 behind the label, or is a jump to the loop start. */
4192 {
4198 {
4203 {
4206 else
4210 }
4218 {
4221 }
4222 }
4223 }
4225 /* Past a jump, we get to insns for which we can't count
4226 on whether they will be executed during each iteration. */
4227 /* This code appears twice in strength_reduce. There is also similar
4228 code in scan_loop. */
4230 /* If we enter the loop in the middle, and scan around to the
4231 beginning, don't set not_every_iteration for that.
4232 This can be any kind of jump, since we want to know if insns
4233 will be executed if the loop is executed. */
4238 {
4241 /* If this is a jump outside the loop, then it also doesn't
4242 matter. Check to see if the target of this branch is on the
4243 loop->exits_labels list. */
4251 }
4254 {
4255 /* At the virtual top of a converted loop, insns are again known to
4256 be executed each iteration: logically, the loop begins here
4257 even though the exit code has been duplicated.
4259 Insns are also again known to be executed each iteration at
4260 the LOOP_CONT note. */
4266 loop_depth++;
4268 loop_depth--;
4269 }
4271 /* Note if we pass a loop latch. If we do, then we can not clear
4272 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4273 a loop since a jump before the last CODE_LABEL may have started
4274 a new loop iteration.
4276 Note that LOOP_TOP is only set for rotated loops and we need
4277 this check for all loops, so compare against the CODE_LABEL
4278 which immediately follows LOOP_START. */
4283 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4284 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4285 or not an insn is known to be executed each iteration of the
4286 loop, whether or not any iterations are known to occur.
4288 Therefore, if we have just passed a label and have no more labels
4289 between here and the test insn of the loop, and we have not passed
4290 a jump to the top of the loop, then we know these insns will be
4291 executed each iteration. */
4294 && !past_loop_latch
4299 }
4300 }
4301 \f
4302 static void
4305 {
4308 /* Temporary list pointers for traversing ivs->list. */
4315 /* Scan ivs->list to remove all regs that proved not to be bivs.
4316 Make a sanity check against regs->n_times_set. */
4318 {
4320 /* Above happens if register modified by subreg, etc. */
4321 /* Make sure it is not recognized as a basic induction var: */
4323 /* If never incremented, it is invariant that we decided not to
4324 move. So leave it alone. */
4326 {
4337 }
4338 else
4339 {
4344 }
4345 }
4346 }
4349 /* Determine how BIVS are initialised by looking through pre-header
4350 extended basic block. */
4351 static void
4354 {
4356 /* Temporary list pointers for traversing ivs->list. */
4359 rtx p;
4361 /* Find initial value for each biv by searching backwards from loop_start,
4362 halting at first label. Also record any test condition. */
4366 {
4367 rtx test;
4377 /* Record any test of a biv that branches around the loop if no store
4378 between it and the start of loop. We only care about tests with
4379 constants and registers and only certain of those. */
4389 {
4390 /* If an NE test, we have an initial value! */
4392 {
4396 }
4397 else
4399 }
4400 }
4401 }
4404 /* Look at the each biv and see if we can say anything better about its
4405 initial value from any initializing insns set up above. (This is done
4406 in two passes to avoid missing SETs in a PARALLEL.) */
4407 static void
4410 {
4412 /* Temporary list pointers for traversing ivs->list. */
4417 {
4418 rtx src;
4419 rtx note;
4424 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4425 is a constant, use the value of that. */
4431 else
4444 {
4448 {
4451 }
4452 }
4453 /* If we can't make it a giv,
4454 let biv keep initial value of "itself". */
4457 }
4458 }
4461 /* Search the loop for general induction variables. */
4463 static void
4466 {
4468 }
4471 /* For each giv for which we still don't know whether or not it is
4472 replaceable, check to see if it is replaceable because its final value
4473 can be calculated. */
4475 static void
4478 {
4483 {
4489 }
4490 }
4493 /* Return non-zero if it is possible to eliminate the biv BL provided
4494 all givs are reduced. This is possible if either the reg is not
4495 used outside the loop, or we can compute what its final value will
4496 be. */
4498 static int
4504 {
4505 /* For architectures with a decrement_and_branch_until_zero insn,
4506 don't do this if we put a REG_NONNEG note on the endtest for this
4507 biv. */
4509 #ifdef HAVE_decrement_and_branch_until_zero
4511 {
4516 }
4517 #endif
4519 /* Check that biv is used outside loop or if it has a final value.
4520 Compare against bl->init_insn rather than loop->start. We aren't
4521 concerned with any uses of the biv between init_insn and
4522 loop->start since these won't be affected by the value of the biv
4523 elsewhere in the function, so long as init_insn doesn't use the
4524 biv itself. */
4535 {
4543 }
4545 }
4548 /* Reduce each giv of BL that we have decided to reduce. */
4550 static void
4554 {
4558 {
4561 {
4564 /* If the code for derived givs immediately below has already
4565 allocated a new_reg, we must keep it. */
4569 #ifdef AUTO_INC_DEC
4570 /* If the target has auto-increment addressing modes, and
4571 this is an address giv, then try to put the increment
4572 immediately after its use, so that flow can create an
4573 auto-increment addressing mode. */
4576 /* We don't handle reversed biv's because bl->biv->insn
4577 does not have a valid INSN_LUID. */
4581 {
4582 /* If other giv's have been combined with this one, then
4583 this will work only if all uses of the other giv's occur
4584 before this giv's insn. This is difficult to check.
4586 We simplify this by looking for the common case where
4587 there is one DEST_REG giv, and this giv's insn is the
4588 last use of the dest_reg of that DEST_REG giv. If the
4589 increment occurs after the address giv, then we can
4590 perform the optimization. (Otherwise, the increment
4591 would have to go before other_giv, and we would not be
4592 able to combine it with the address giv to get an
4593 auto-inc address.) */
4595 {
4600 {
4603 else
4605 }
4612 }
4613 /* Check for case where increment is before the address
4614 giv. Do this test in "loop order". */
4623 else
4626 #ifdef HAVE_cc0
4627 {
4628 rtx prev;
4630 /* We can't put an insn immediately after one setting
4631 cc0, or immediately before one using cc0. */
4638 }
4639 #endif
4643 }
4644 #endif
4646 /* For each place where the biv is incremented, add an insn
4647 to increment the new, reduced reg for the giv. */
4649 {
4650 rtx insert_before;
4656 else
4664 /* A multiply is acceptable here
4665 since this is presumed to be seldom executed. */
4669 }
4671 /* Add code at loop start to initialize giv's reduced reg. */
4676 }
4677 }
4678 }
4681 /* Check for givs whose first use is their definition and whose
4682 last use is the definition of another giv. If so, it is likely
4683 dead and should not be used to derive another giv nor to
4684 eliminate a biv. */
4686 static void
4690 {
4694 {
4701 {
4707 }
4708 }
4709 }
4712 static void
4717 {
4721 {
4728 /* Update expression if this was combined, in case other giv was
4729 replaced. */
4734 /* See if this register is known to be a pointer to something. If
4735 so, see if we can find the alignment. First see if there is a
4736 destination register that is a pointer. If so, this shares the
4737 alignment too. Next see if we can deduce anything from the
4738 computational information. If not, and this is a DEST_ADDR
4739 giv, at least we know that it's a pointer, though we don't know
4740 the alignment. */
4748 {
4757 }
4761 {
4769 }
4774 /* Store reduced reg as the address in the memref where we found
4775 this giv. */
4778 {
4780 }
4781 else
4782 {
4783 /* Not replaceable; emit an insn to set the original giv reg from
4784 the reduced giv, same as above. */
4787 }
4789 /* When a loop is reversed, givs which depend on the reversed
4790 biv, and which are live outside the loop, must be set to their
4791 correct final value. This insn is only needed if the giv is
4792 not replaceable. The correct final value is the same as the
4793 value that the giv starts the reversed loop with. */
4803 {
4808 }
4809 }
4810 }
4813 static int
4818 rtx test_reg;
4819 {
4828 /* Reduce benefit if not replaceable, since we will insert a
4829 move-insn to replace the insn that calculates this giv. Don't do
4830 this unless the giv is a user variable, since it will often be
4831 marked non-replaceable because of the duplication of the exit
4832 code outside the loop. In such a case, the copies we insert are
4833 dead and will be deleted. So they don't have a cost. Similar
4834 situations exist. */
4835 /* ??? The new final_[bg]iv_value code does a much better job of
4836 finding replaceable giv's, and hence this code may no longer be
4837 necessary. */
4842 /* Decrease the benefit to count the add-insns that we will insert
4843 to increment the reduced reg for the giv. ??? This can
4844 overestimate the run-time cost of the additional insns, e.g. if
4845 there are multiple basic blocks that increment the biv, but only
4846 one of these blocks is executed during each iteration. There is
4847 no good way to detect cases like this with the current structure
4848 of the loop optimizer. This code is more accurate for
4849 determining code size than run-time benefits. */
4852 /* Decide whether to strength-reduce this giv or to leave the code
4853 unchanged (recompute it from the biv each time it is used). This
4854 decision can be made independently for each giv. */
4856 #ifdef AUTO_INC_DEC
4857 /* Attempt to guess whether autoincrement will handle some of the
4858 new add insns; if so, increase BENEFIT (undo the subtraction of
4859 add_cost that was done above). */
4861 /* Increasing the benefit is risky, since this is only a guess.
4862 Avoid increasing register pressure in cases where there would
4863 be no other benefit from reducing this giv. */
4866 {
4881 }
4882 #endif
4885 }
4888 /* Free IV structures for LOOP. */
4890 static void
4893 {
4900 {
4906 {
4909 }
4911 {
4914 }
4918 }
4919 }
4922 /* Perform strength reduction and induction variable elimination.
4924 Pseudo registers created during this function will be beyond the
4925 last valid index in several tables including
4926 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4927 problem here, because the added registers cannot be givs outside of
4928 their loop, and hence will never be reconsidered. But scan_loop
4929 must check regnos to make sure they are in bounds. */
4931 static void
4935 {
4939 rtx p;
4940 /* Temporary list pointer for traversing ivs->list. */
4942 /* Ratio of extra register life span we can justify
4943 for saving an instruction. More if loop doesn't call subroutines
4944 since in that case saving an insn makes more difference
4945 and more registers are available. */
4946 /* ??? could set this to last value of threshold in move_movables */
4948 /* Map of pseudo-register replacements. */
4960 /* Find all BIVs in loop. */
4963 /* Exit if there are no bivs. */
4965 {
4966 /* Can still unroll the loop anyways, but indicate that there is no
4967 strength reduction info available. */
4973 }
4975 /* Determine how BIVS are initialised by looking through pre-header
4976 extended basic block. */
4979 /* Look at the each biv and see if we can say anything better about its
4980 initial value from any initializing insns set up above. */
4983 /* Search the loop for general induction variables. */
4986 /* Try to calculate and save the number of loop iterations. This is
4987 set to zero if the actual number can not be calculated. This must
4988 be called after all giv's have been identified, since otherwise it may
4989 fail if the iteration variable is a giv. */
4992 #ifdef HAVE_prefetch
4995 #endif
4997 /* Now for each giv for which we still don't know whether or not it is
4998 replaceable, check to see if it is replaceable because its final value
4999 can be calculated. This must be done after loop_iterations is called,
5000 so that final_giv_value will work correctly. */
5003 /* Try to prove that the loop counter variable (if any) is always
5004 nonnegative; if so, record that fact with a REG_NONNEG note
5005 so that "decrement and branch until zero" insn can be used. */
5008 /* Create reg_map to hold substitutions for replaceable giv regs.
5009 Some givs might have been made from biv increments, so look at
5010 ivs->reg_iv_type for a suitable size. */
5014 /* Examine each iv class for feasibility of strength reduction/induction
5015 variable elimination. */
5018 {
5022 /* Test whether it will be possible to eliminate this biv
5023 provided all givs are reduced. */
5026 /* This will be true at the end, if all givs which depend on this
5027 biv have been strength reduced.
5028 We can't (currently) eliminate the biv unless this is so. */
5031 /* Check each extension dependent giv in this class to see if its
5032 root biv is safe from wrapping in the interior mode. */
5035 /* Combine all giv's for this iv_class. */
5039 {
5047 /* If an insn is not to be strength reduced, then set its ignore
5048 flag, and clear bl->all_reduced. */
5050 /* A giv that depends on a reversed biv must be reduced if it is
5051 used after the loop exit, otherwise, it would have the wrong
5052 value after the loop exit. To make it simple, just reduce all
5053 of such giv's whether or not we know they are used after the loop
5054 exit. */
5059 {
5067 }
5068 else
5069 {
5070 /* Check that we can increment the reduced giv without a
5071 multiply insn. If not, reject it. */
5076 {
5084 }
5085 }
5086 }
5088 /* Check for givs whose first use is their definition and whose
5089 last use is the definition of another giv. If so, it is likely
5090 dead and should not be used to derive another giv nor to
5091 eliminate a biv. */
5094 /* Reduce each giv that we decided to reduce. */
5097 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5098 as not reduced.
5100 For each giv register that can be reduced now: if replaceable,
5101 substitute reduced reg wherever the old giv occurs;
5102 else add new move insn "giv_reg = reduced_reg". */
5105 /* All the givs based on the biv bl have been reduced if they
5106 merit it. */
5108 /* For each giv not marked as maybe dead that has been combined with a
5109 second giv, clear any "maybe dead" mark on that second giv.
5110 v->new_reg will either be or refer to the register of the giv it
5111 combined with.
5113 Doing this clearing avoids problems in biv elimination where
5114 a giv's new_reg is a complex value that can't be put in the
5115 insn but the giv combined with (with a reg as new_reg) is
5116 marked maybe_dead. Since the register will be used in either
5117 case, we'd prefer it be used from the simpler giv. */
5123 /* Try to eliminate the biv, if it is a candidate.
5124 This won't work if ! bl->all_reduced,
5125 since the givs we planned to use might not have been reduced.
5127 We have to be careful that we didn't initially think we could
5128 eliminate this biv because of a giv that we now think may be
5129 dead and shouldn't be used as a biv replacement.
5131 Also, there is the possibility that we may have a giv that looks
5132 like it can be used to eliminate a biv, but the resulting insn
5133 isn't valid. This can happen, for example, on the 88k, where a
5134 JUMP_INSN can compare a register only with zero. Attempts to
5135 replace it with a compare with a constant will fail.
5137 Note that in cases where this call fails, we may have replaced some
5138 of the occurrences of the biv with a giv, but no harm was done in
5139 doing so in the rare cases where it can occur. */
5143 {
5144 /* ?? If we created a new test to bypass the loop entirely,
5145 or otherwise drop straight in, based on this test, then
5146 we might want to rewrite it also. This way some later
5147 pass has more hope of removing the initialization of this
5148 biv entirely. */
5150 /* If final_value != 0, then the biv may be used after loop end
5151 and we must emit an insn to set it just in case.
5153 Reversed bivs already have an insn after the loop setting their
5154 value, so we don't need another one. We can't calculate the
5155 proper final value for such a biv here anyways. */
5163 }
5164 /* See above note wrt final_value. But since we couldn't eliminate
5165 the biv, we must set the value after the loop instead of before. */
5169 }
5171 /* Go through all the instructions in the loop, making all the
5172 register substitutions scheduled in REG_MAP. */
5177 {
5181 }
5184 {
5185 /* When we completely unroll a loop we will likely not need the increment
5186 of the loop BIV and we will not need the conditional branch at the
5187 end of the loop. */
5190 #ifdef HAVE_cc0
5191 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5192 need the comparison before the conditional branch at the end of the
5193 loop. */
5195 #endif
5197 /* We'll need one copy for each loop iteration. */
5200 /* A little slop to account for the ability to remove initialization
5201 code, better CSE, and other secondary benefits of completely
5202 unrolling some loops. */
5205 /* Clamp the value. */
5208 }
5210 /* Unroll loops from within strength reduction so that we can use the
5211 induction variable information that strength_reduce has already
5212 collected. Always unroll loops that would be as small or smaller
5213 unrolled than when rolled. */
5219 #ifdef HAVE_doloop_end
5224 /* In case number of iterations is known, drop branch prediction note
5225 in the branch. Do that only in second loop pass, as loop unrolling
5226 may change the number of iterations performed. */
5229 {
5232 PRED_LOOP_ITERATIONS,
5234 }
5242 }
5243 \f
5244 /*Record all basic induction variables calculated in the insn. */
5245 static rtx
5248 rtx p;
5251 {
5253 rtx set;
5254 rtx dest_reg;
5255 rtx inc_val;
5256 rtx mult_val;
5262 {
5267 {
5272 {
5273 /* It is a possible basic induction variable.
5274 Create and initialize an induction structure for it. */
5282 }
5285 }
5286 }
5288 }
5289 \f
5290 /* Record all givs calculated in the insn.
5291 A register is a giv if: it is only set once, it is a function of a
5292 biv and a constant (or invariant), and it is not a biv. */
5293 static rtx
5296 rtx p;
5299 {
5302 rtx set;
5303 /* Look for a general induction variable in a register. */
5308 {
5309 rtx src_reg;
5310 rtx dest_reg;
5311 rtx add_val;
5312 rtx mult_val;
5313 rtx ext_val;
5316 rtx last_consec_insn;
5325 /* Equivalent expression is a giv. */
5330 /* Don't try to handle any regs made by loop optimization.
5331 We have nothing on them in regno_first_uid, etc. */
5333 /* Don't recognize a BASIC_INDUCT_VAR here. */
5335 /* This must be the only place where the register is set. */
5337 /* or all sets must be consecutive and make a giv. */
5342 {
5346 /* If this is a library call, increase benefit. */
5350 /* Skip the consecutive insns, if there are any. */
5358 }
5359 }
5361 #ifndef DONT_REDUCE_ADDR
5362 /* Look for givs which are memory addresses. */
5363 /* This resulted in worse code on a VAX 8600. I wonder if it
5364 still does. */
5367 maybe_multiple);
5368 #endif
5370 /* Update the status of whether giv can derive other givs. This can
5371 change when we pass a label or an insn that updates a biv. */
5376 }
5377 \f
5378 /* Return 1 if X is a valid source for an initial value (or as value being
5379 compared against in an initial test).
5381 X must be either a register or constant and must not be clobbered between
5382 the current insn and the start of the loop.
5384 INSN is the insn containing X. */
5386 static int
5388 rtx x;
5389 rtx insn;
5391 rtx loop_start;
5392 {
5396 /* Only consider pseudos we know about initialized in insns whose luids
5397 we know. */
5402 /* Don't use call-clobbered registers across a call which clobbers it. On
5403 some machines, don't use any hard registers at all. */
5405 && (SMALL_REGISTER_CLASSES
5409 /* Don't use registers that have been clobbered before the start of the
5410 loop. */
5415 }
5416 \f
5417 /* Scan X for memory refs and check each memory address
5418 as a possible giv. INSN is the insn whose pattern X comes from.
5419 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5420 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5421 more thanonce in each loop iteration. */
5423 static void
5426 rtx x;
5427 rtx insn;
5429 {
5439 {
5455 {
5456 rtx src_reg;
5457 rtx add_val;
5458 rtx mult_val;
5459 rtx ext_val;
5462 /* This code used to disable creating GIVs with mult_val == 1 and
5463 add_val == 0. However, this leads to lost optimizations when
5464 it comes time to combine a set of related DEST_ADDR GIVs, since
5465 this one would not be seen. */
5470 {
5471 /* Found one; record it. */
5480 }
5481 }
5486 }
5488 /* Recursively scan the subexpressions for other mem refs. */
5494 maybe_multiple);
5498 maybe_multiple);
5499 }
5500 \f
5501 /* Fill in the data about one biv update.
5502 V is the `struct induction' in which we record the biv. (It is
5503 allocated by the caller, with alloca.)
5504 INSN is the insn that sets it.
5505 DEST_REG is the biv's reg.
5507 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5508 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5509 being set to INC_VAL.
5511 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5512 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5513 can be executed more than once per iteration. If MAYBE_MULTIPLE
5514 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5515 executed exactly once per iteration. */
5517 static void
5522 rtx insn;
5523 rtx dest_reg;
5524 rtx inc_val;
5525 rtx mult_val;
5529 {
5545 /* Add this to the reg's iv_class, creating a class
5546 if this is the first incrementation of the reg. */
5550 {
5551 /* Create and initialize new iv_class. */
5561 /* Set initial value to the reg itself. */
5564 /* We haven't seen the initializing insn yet */
5574 /* Add this class to ivs->list. */
5578 /* Put it in the array of biv register classes. */
5580 }
5582 /* Update IV_CLASS entry for this biv. */
5591 }
5592 \f
5593 /* Fill in the data about one giv.
5594 V is the `struct induction' in which we record the giv. (It is
5595 allocated by the caller, with alloca.)
5596 INSN is the insn that sets it.
5597 BENEFIT estimates the savings from deleting this insn.
5598 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5599 into a register or is used as a memory address.
5601 SRC_REG is the biv reg which the giv is computed from.
5602 DEST_REG is the giv's reg (if the giv is stored in a reg).
5603 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5604 LOCATION points to the place where this giv's value appears in INSN. */
5606 static void
5611 rtx insn;
5612 rtx src_reg;
5613 rtx dest_reg;
5619 {
5624 rtx temp;
5626 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5627 undo the MULT canonicalization that we performed earlier. */
5657 /* The v->always_computable field is used in update_giv_derive, to
5658 determine whether a giv can be used to derive another giv. For a
5659 DEST_REG giv, INSN computes a new value for the giv, so its value
5660 isn't computable if INSN insn't executed every iteration.
5661 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5662 it does not compute a new value. Hence the value is always computable
5663 regardless of whether INSN is executed each iteration. */
5667 else
5673 {
5676 }
5678 {
5683 /* If the lifetime is zero, it means that this register is
5684 really a dead store. So mark this as a giv that can be
5685 ignored. This will not prevent the biv from being eliminated. */
5691 }
5693 /* Add the giv to the class of givs computed from one biv. */
5697 {
5700 /* Don't count DEST_ADDR. This is supposed to count the number of
5701 insns that calculate givs. */
5705 }
5706 else
5707 /* Fatal error, biv missing for this giv? */
5712 else
5713 {
5714 /* The giv can be replaced outright by the reduced register only if all
5715 of the following conditions are true:
5716 - the insn that sets the giv is always executed on any iteration
5717 on which the giv is used at all
5718 (there are two ways to deduce this:
5719 either the insn is executed on every iteration,
5720 or all uses follow that insn in the same basic block),
5721 - the giv is not used outside the loop
5722 - no assignments to the biv occur during the giv's lifetime. */
5725 /* Previous line always fails if INSN was moved by loop opt. */
5728 && (! not_every_iteration
5730 {
5731 /* Now check that there are no assignments to the biv within the
5732 giv's lifetime. This requires two separate checks. */
5734 /* Check each biv update, and fail if any are between the first
5735 and last use of the giv.
5737 If this loop contains an inner loop that was unrolled, then
5738 the insn modifying the biv may have been emitted by the loop
5739 unrolling code, and hence does not have a valid luid. Just
5740 mark the biv as not replaceable in this case. It is not very
5741 useful as a biv, because it is used in two different loops.
5742 It is very unlikely that we would be able to optimize the giv
5743 using this biv anyways. */
5747 {
5753 {
5757 }
5758 }
5760 /* If there are any backwards branches that go from after the
5761 biv update to before it, then this giv is not replaceable. */
5765 {
5769 }
5770 }
5771 else
5772 {
5773 /* May still be replaceable, we don't have enough info here to
5774 decide. */
5777 }
5778 }
5780 /* Record whether the add_val contains a const_int, for later use by
5781 combine_givs. */
5782 {
5787 ;
5791 {
5793 {
5798 else
5800 }
5803 }
5804 }
5808 }
5810 /* All this does is determine whether a giv can be made replaceable because
5811 its final value can be calculated. This code can not be part of record_giv
5812 above, because final_giv_value requires that the number of loop iterations
5813 be known, and that can not be accurately calculated until after all givs
5814 have been identified. */
5816 static void
5820 {
5827 /* DEST_ADDR givs will never reach here, because they are always marked
5828 replaceable above in record_giv. */
5830 /* The giv can be replaced outright by the reduced register only if all
5831 of the following conditions are true:
5832 - the insn that sets the giv is always executed on any iteration
5833 on which the giv is used at all
5834 (there are two ways to deduce this:
5835 either the insn is executed on every iteration,
5836 or all uses follow that insn in the same basic block),
5837 - its final value can be calculated (this condition is different
5838 than the one above in record_giv)
5839 - it's not used before the it's set
5840 - no assignments to the biv occur during the giv's lifetime. */
5842 #if 0
5843 /* This is only called now when replaceable is known to be false. */
5844 /* Clear replaceable, so that it won't confuse final_giv_value. */
5846 #endif
5850 {
5853 rtx last_giv_use;
5857 /* When trying to determine whether or not a biv increment occurs
5858 during the lifetime of the giv, we can ignore uses of the variable
5859 outside the loop because final_value is true. Hence we can not
5860 use regno_last_uid and regno_first_uid as above in record_giv. */
5862 /* Search the loop to determine whether any assignments to the
5863 biv occur during the giv's lifetime. Start with the insn
5864 that sets the giv, and search around the loop until we come
5865 back to that insn again.
5867 Also fail if there is a jump within the giv's lifetime that jumps
5868 to somewhere outside the lifetime but still within the loop. This
5869 catches spaghetti code where the execution order is not linear, and
5870 hence the above test fails. Here we assume that the giv lifetime
5871 does not extend from one iteration of the loop to the next, so as
5872 to make the test easier. Since the lifetime isn't known yet,
5873 this requires two loops. See also record_giv above. */
5878 {
5881 {
5884 }
5890 {
5891 /* It is possible for the BIV increment to use the GIV if we
5892 have a cycle. Thus we must be sure to check each insn for
5893 both BIV and GIV uses, and we must check for BIV uses
5894 first. */
5901 {
5903 {
5907 }
5909 }
5910 }
5911 }
5913 /* Now that the lifetime of the giv is known, check for branches
5914 from within the lifetime to outside the lifetime if it is still
5915 replaceable. */
5918 {
5921 {
5934 {
5943 }
5944 }
5945 }
5947 /* If it is replaceable, then save the final value. */
5950 }
5955 }
5956 \f
5957 /* Update the status of whether a giv can derive other givs.
5959 We need to do something special if there is or may be an update to the biv
5960 between the time the giv is defined and the time it is used to derive
5961 another giv.
5963 In addition, a giv that is only conditionally set is not allowed to
5964 derive another giv once a label has been passed.
5966 The cases we look at are when a label or an update to a biv is passed. */
5968 static void
5971 rtx p;
5972 {
5976 rtx tem;
5979 /* Search all IV classes, then all bivs, and finally all givs.
5981 There are three cases we are concerned with. First we have the situation
5982 of a giv that is only updated conditionally. In that case, it may not
5983 derive any givs after a label is passed.
5985 The second case is when a biv update occurs, or may occur, after the
5986 definition of a giv. For certain biv updates (see below) that are
5987 known to occur between the giv definition and use, we can adjust the
5988 giv definition. For others, or when the biv update is conditional,
5989 we must prevent the giv from deriving any other givs. There are two
5990 sub-cases within this case.
5992 If this is a label, we are concerned with any biv update that is done
5993 conditionally, since it may be done after the giv is defined followed by
5994 a branch here (actually, we need to pass both a jump and a label, but
5995 this extra tracking doesn't seem worth it).
5997 If this is a jump, we are concerned about any biv update that may be
5998 executed multiple times. We are actually only concerned about
5999 backward jumps, but it is probably not worth performing the test
6000 on the jump again here.
6002 If this is a biv update, we must adjust the giv status to show that a
6003 subsequent biv update was performed. If this adjustment cannot be done,
6004 the giv cannot derive further givs. */
6010 {
6012 {
6013 /* If cant_derive is already true, there is no point in
6014 checking all of these conditions again. */
6018 /* If this giv is conditionally set and we have passed a label,
6019 it cannot derive anything. */
6023 /* Skip givs that have mult_val == 0, since
6024 they are really invariants. Also skip those that are
6025 replaceable, since we know their lifetime doesn't contain
6026 any biv update. */
6030 /* The only way we can allow this giv to derive another
6031 is if this is a biv increment and we can form the product
6032 of biv->add_val and giv->mult_val. In this case, we will
6033 be able to compute a compensation. */
6035 {
6036 rtx ext_val_dummy;
6047 tem = simplify_giv_expr
6054 else
6056 }
6060 }
6061 }
6062 }
6063 \f
6064 /* Check whether an insn is an increment legitimate for a basic induction var.
6065 X is the source of insn P, or a part of it.
6066 MODE is the mode in which X should be interpreted.
6068 DEST_REG is the putative biv, also the destination of the insn.
6069 We accept patterns of these forms:
6070 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6071 REG = INVARIANT + REG
6073 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6074 store the additive term into *INC_VAL, and store the place where
6075 we found the additive term into *LOCATION.
6077 If X is an assignment of an invariant into DEST_REG, we set
6078 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6080 We also want to detect a BIV when it corresponds to a variable
6081 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6082 of the variable may be a PLUS that adds a SUBREG of that variable to
6083 an invariant and then sign- or zero-extends the result of the PLUS
6084 into the variable.
6086 Most GIVs in such cases will be in the promoted mode, since that is the
6087 probably the natural computation mode (and almost certainly the mode
6088 used for addresses) on the machine. So we view the pseudo-reg containing
6089 the variable as the BIV, as if it were simply incremented.
6091 Note that treating the entire pseudo as a BIV will result in making
6092 simple increments to any GIVs based on it. However, if the variable
6093 overflows in its declared mode but not its promoted mode, the result will
6094 be incorrect. This is acceptable if the variable is signed, since
6095 overflows in such cases are undefined, but not if it is unsigned, since
6096 those overflows are defined. So we only check for SIGN_EXTEND and
6097 not ZERO_EXTEND.
6099 If we cannot find a biv, we return 0. */
6101 static int
6104 rtx x;
6106 rtx dest_reg;
6107 rtx p;
6111 {
6119 {
6125 {
6127 }
6132 {
6134 }
6135 else
6148 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6149 handle addition of promoted variables.
6150 ??? The comment at the start of this function is wrong: promoted
6151 variable increments don't look like it says they do. */
6157 /* If this register is assigned in a previous insn, look at its
6158 source, but don't go outside the loop or past a label. */
6160 /* If this sets a register to itself, we would repeat any previous
6161 biv increment if we applied this strategy blindly. */
6167 {
6168 rtx dest;
6169 do
6170 {
6172 }
6201 }
6202 /* Fall through. */
6204 /* Can accept constant setting of biv only when inside inner most loop.
6205 Otherwise, a biv of an inner loop may be incorrectly recognized
6206 as a biv of the outer loop,
6207 causing code to be moved INTO the inner loop. */
6214 /* convert_modes aborts if we try to convert to or from CCmode, so just
6215 exclude that case. It is very unlikely that a condition code value
6216 would be a useful iterator anyways. */
6220 {
6221 /* Possible bug here? Perhaps we don't know the mode of X. */
6225 }
6226 else
6234 /* Similar, since this can be a sign extension. */
6239 ;
6253 location);
6258 }
6259 }
6260 \f
6261 /* A general induction variable (giv) is any quantity that is a linear
6262 function of a basic induction variable,
6263 i.e. giv = biv * mult_val + add_val.
6264 The coefficients can be any loop invariant quantity.
6265 A giv need not be computed directly from the biv;
6266 it can be computed by way of other givs. */
6268 /* Determine whether X computes a giv.
6269 If it does, return a nonzero value
6270 which is the benefit from eliminating the computation of X;
6271 set *SRC_REG to the register of the biv that it is computed from;
6272 set *ADD_VAL and *MULT_VAL to the coefficients,
6273 such that the value of X is biv * mult + add; */
6275 static int
6279 rtx x;
6287 {
6291 /* If this is an invariant, forget it, it isn't a giv. */
6302 {
6305 /* Since this is now an invariant and wasn't before, it must be a giv
6306 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6307 with. */
6314 /* This is equivalent to a BIV. */
6321 /* Either (plus (biv) (invar)) or
6322 (plus (mult (biv) (invar_1)) (invar_2)). */
6324 {
6327 }
6328 else
6329 {
6332 }
6337 /* ADD_VAL is zero. */
6345 }
6347 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6348 unless they are CONST_INT). */
6356 else
6359 /* Always return true if this is a giv so it will be detected as such,
6360 even if the benefit is zero or negative. This allows elimination
6361 of bivs that might otherwise not be eliminated. */
6363 }
6364 \f
6365 /* Given an expression, X, try to form it as a linear function of a biv.
6366 We will canonicalize it to be of the form
6367 (plus (mult (BIV) (invar_1))
6368 (invar_2))
6369 with possible degeneracies.
6371 The invariant expressions must each be of a form that can be used as a
6372 machine operand. We surround then with a USE rtx (a hack, but localized
6373 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6374 routine; it is the caller's responsibility to strip them.
6376 If no such canonicalization is possible (i.e., two biv's are used or an
6377 expression that is neither invariant nor a biv or giv), this routine
6378 returns 0.
6380 For a non-zero return, the result will have a code of CONST_INT, USE,
6381 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6383 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6388 static rtx
6391 rtx x;
6394 {
6399 rtx tem;
6401 /* If this is not an integer mode, or if we cannot do arithmetic in this
6402 mode, this can't be a giv. */
6409 {
6416 /* Put constant last, CONST_INT last if both constant. */
6424 /* Handle addition of zero, then addition of an invariant. */
6429 {
6432 /* Adding two invariants must result in an invariant, so enclose
6433 addition operation inside a USE and return it. */
6443 else
6452 /* biv + invar or mult + invar. Return sum. */
6456 /* (a + invar_1) + invar_2. Associate. */
6457 return
6463 arg1)),
6468 }
6470 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6471 MULT to reduce cases. */
6477 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6478 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6479 Recurse to associate the second PLUS. */
6484 return
6492 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6508 /* Handle "a - b" as "a + b * (-1)". */
6514 constm1_rtx)),
6523 /* Put constant last, CONST_INT last if both constant. */
6528 /* If second argument is not now constant, not giv. */
6532 /* Handle multiply by 0 or 1. */
6540 {
6542 /* biv * invar. Done. */
6546 /* Product of two constants. */
6550 /* invar * invar is a giv, but attempt to simplify it somehow. */
6556 {
6557 /* (invar_0 * invar_1) * invar_2. Associate. */
6564 arg1)),
6566 }
6567 /* Porpagate the MULT expressions to the intermost nodes. */
6569 {
6570 /* (invar_0 + invar_1) * invar_2. Distribute. */
6576 arg1),
6580 arg1)),
6582 }
6586 /* (a * invar_1) * invar_2. Associate. */
6592 arg1)),
6596 /* (a + invar_1) * invar_2. Distribute. */
6601 arg1),
6604 arg1)),
6609 }
6612 /* Shift by constant is multiply by power of two. */
6616 return
6625 /* "-a" is "a * (-1)" */
6631 /* "~a" is "-a - 1". Silly, but easy. */
6635 const1_rtx),
6639 /* Already in proper form for invariant. */
6645 /* Conditionally recognize extensions of simple IVs. After we've
6646 computed loop traversal counts and verified the range of the
6647 source IV, we'll reevaluate this as a GIV. */
6649 {
6652 {
6655 }
6656 }
6660 /* If this is a new register, we can't deal with it. */
6664 /* Check for biv or giv. */
6666 {
6670 {
6673 /* Form expression from giv and add benefit. Ensure this giv
6674 can derive another and subtract any needed adjustment if so. */
6676 /* Increasing the benefit here is risky. The only case in which it
6677 is arguably correct is if this is the only use of V. In other
6678 cases, this will artificially inflate the benefit of the current
6679 giv, and lead to suboptimal code. Thus, it is disabled, since
6680 potentially not reducing an only marginally beneficial giv is
6681 less harmful than reducing many givs that are not really
6682 beneficial. */
6683 {
6687 }
6700 {
6703 }
6704 else
6705 {
6708 }
6710 }
6713 do_default:
6714 /* If it isn't an induction variable, and it is invariant, we
6715 may be able to simplify things further by looking through
6716 the bits we just moved outside the loop. */
6718 {
6724 {
6725 /* Ok, we found a match. Substitute and simplify. */
6727 /* If we match another movable, we must use that, as
6728 this one is going away. */
6733 /* If consec is non-zero, this is a member of a group of
6734 instructions that were moved together. We handle this
6735 case only to the point of seeking to the last insn and
6736 looking for a REG_EQUAL. Fail if we don't find one. */
6738 {
6741 do
6742 {
6744 }
6750 }
6751 else
6752 {
6756 }
6759 {
6760 /* What we are most interested in is pointer
6761 arithmetic on invariants -- only take
6762 patterns we may be able to do something with. */
6768 {
6770 benefit);
6773 }
6778 {
6783 }
6784 }
6786 }
6787 }
6789 }
6791 /* Fall through to general case. */
6793 /* If invariant, return as USE (unless CONST_INT).
6794 Otherwise, not giv. */
6799 {
6808 }
6809 else
6811 }
6812 }
6814 /* This routine folds invariants such that there is only ever one
6815 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6817 static rtx
6820 {
6826 {
6829 }
6832 {
6835 }
6836 else
6837 {
6840 }
6841 }
6843 static rtx
6847 {
6849 {
6853 else
6856 }
6859 else
6862 }
6863 \f
6864 /* Help detect a giv that is calculated by several consecutive insns;
6865 for example,
6866 giv = biv * M
6867 giv = giv + A
6868 The caller has already identified the first insn P as having a giv as dest;
6869 we check that all other insns that set the same register follow
6870 immediately after P, that they alter nothing else,
6871 and that the result of the last is still a giv.
6873 The value is 0 if the reg set in P is not really a giv.
6874 Otherwise, the value is the amount gained by eliminating
6875 all the consecutive insns that compute the value.
6877 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6878 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6880 The coefficients of the ultimate giv value are stored in
6881 *MULT_VAL and *ADD_VAL. */
6883 static int
6888 rtx p;
6889 rtx src_reg;
6890 rtx dest_reg;
6895 {
6901 rtx temp;
6902 rtx set;
6904 /* Indicate that this is a giv so that we can update the value produced in
6905 each insn of the multi-insn sequence.
6907 This induction structure will be used only by the call to
6908 general_induction_var below, so we can allocate it on our stack.
6909 If this is a giv, our caller will replace the induct var entry with
6910 a new induction structure. */
6931 {
6935 /* If libcall, skip to end of call sequence. */
6946 /* Giv created by equivalent expression. */
6952 {
6956 count--;
6960 }
6962 {
6963 /* Allow insns that set something other than this giv to a
6964 constant. Such insns are needed on machines which cannot
6965 include long constants and should not disqualify a giv. */
6974 }
6975 }
6980 }
6981 \f
6982 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6983 represented by G1. If no such expression can be found, or it is clear that
6984 it cannot possibly be a valid address, 0 is returned.
6986 To perform the computation, we note that
6987 G1 = x * v + a and
6988 G2 = y * v + b
6989 where `v' is the biv.
6991 So G2 = (y/b) * G1 + (b - a*y/x).
6993 Note that MULT = y/x.
6995 Update: A and B are now allowed to be additive expressions such that
6996 B contains all variables in A. That is, computing B-A will not require
6997 subtracting variables. */
6999 static rtx
7002 {
7003 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7008 /* If MULT is not 1, we cannot handle A with non-constants, since we
7009 would then be required to subtract multiples of the registers in A.
7010 This is theoretically possible, and may even apply to some Fortran
7011 constructs, but it is a lot of work and we do not attempt it here. */
7016 /* In general these structures are sorted top to bottom (down the PLUS
7017 chain), but not left to right across the PLUS. If B is a higher
7018 order giv than A, we can strip one level and recurse. If A is higher
7019 order, we'll eventually bail out, but won't know that until the end.
7020 If they are the same, we'll strip one level around this loop. */
7023 {
7035 /* We matched: remove one reg completely. */
7038 /* An alternate match. */
7041 /* An alternate match. */
7043 else
7044 {
7045 /* Indicates an extra register in B. Strip one level from B and
7046 recurse, hoping B was the higher order expression. */
7051 }
7052 }
7054 /* Here we are at the last level of A, go through the cases hoping to
7055 get rid of everything but a constant. */
7058 {
7071 }
7073 {
7075 }
7077 {
7082 }
7084 {
7089 else
7091 }
7096 }
7098 rtx
7101 {
7104 /* The value that G1 will be multiplied by must be a constant integer. Also,
7105 the only chance we have of getting a valid address is if b*c/a (see above
7106 for notation) is also an integer. */
7109 {
7114 }
7117 else
7118 {
7119 /* ??? Find out if the one is a multiple of the other? */
7121 }
7125 {
7126 /* Failed. If we've got a multiplication factor between G1 and G2,
7127 scale G1's addend and try again. */
7129 {
7133 {
7134 HOST_WIDE_INT m;
7138 }
7139 else
7140 {
7142 mult);
7143 }
7146 }
7147 }
7151 /* Form simplified final result. */
7156 else
7161 else
7162 {
7165 {
7169 }
7172 }
7173 }
7174 \f
7175 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7176 represented by G1. This indicates that G2 should be combined with G1 and
7177 that G2 can use (either directly or via an address expression) a register
7178 used to represent G1. */
7180 static rtx
7183 {
7186 /* With the introduction of ext dependent givs, we must care for modes.
7187 G2 must not use a wider mode than G1. */
7197 /* If these givs are identical, they can be combined. We use the results
7198 of express_from because the addends are not in a canonical form, so
7199 rtx_equal_p is a weaker test. */
7200 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7201 combination to be the other way round. */
7204 {
7206 }
7208 /* If G2 can be expressed as a function of G1 and that function is valid
7209 as an address and no more expensive than using a register for G2,
7210 the expression of G2 in terms of G1 can be used. */
7214 /* ??? Looses, especially with -fforce-addr, where *g2->location
7215 will always be a register, and so anything more complicated
7216 gets discarded. */
7217 #if 0
7218 #ifdef ADDRESS_COST
7220 #else
7222 #endif
7223 #endif
7224 )
7225 {
7227 }
7230 }
7231 \f
7232 /* Check each extension dependent giv in this class to see if its
7233 root biv is safe from wrapping in the interior mode, which would
7234 make the giv illegal. */
7236 static void
7240 {
7243 HOST_WIDE_INT start_val;
7249 /* Make sure the iteration data is available. We must have
7250 constants in order to be certain of no overflow. */
7251 /* ??? An unknown iteration count with an increment of +-1
7252 combined with friendly exit tests of against an invariant
7253 value is also ameanable to optimization. Not implemented. */
7259 /* Make sure the host can represent the arithmetic. */
7261 {
7263 HOST_WIDE_INT s_end_val;
7275 /* Check for host arithmatic overflow. */
7277 {
7279 HOST_WIDE_INT s_max;
7286 /* Check zero extension of biv ok. */
7288 /* Check for host arithmatic overflow. */
7289 && (neg_incr
7292 /* Check for target arithmetic overflow. */
7293 && (neg_incr
7296 {
7298 }
7300 /* Check sign extension of biv ok. */
7301 /* ??? While it is true that overflow with signed and pointer
7302 arithmetic is undefined, I fear too many programmers don't
7303 keep this fact in mind -- myself included on occasion.
7304 So leave alone with the signed overflow optimizations. */
7306 /* Check for host arithmatic overflow. */
7307 && (neg_incr
7310 /* Check for target arithmetic overflow. */
7311 && (neg_incr
7314 {
7316 }
7317 }
7318 }
7320 /* Invalidate givs that fail the tests. */
7323 {
7328 {
7337 /* We don't know whether this value is being used as either
7338 signed or unsigned, so to safely truncate we must satisfy
7339 both. The initial check here verifies the BIV itself;
7340 once that is successful we may check its range wrt the
7341 derived GIV. */
7343 {
7347 /* We know from the above that both endpoints are nonnegative,
7348 and that there is no wrapping. Verify that both endpoints
7349 are within the (signed) range of the outer mode. */
7352 }
7357 }
7360 {
7362 {
7366 }
7367 }
7368 else
7369 {
7371 {
7376 else
7377 {
7382 else
7384 }
7389 }
7392 }
7393 }
7394 }
7396 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7398 rtx
7401 rtx value;
7402 {
7408 /* Recall that check_ext_dependent_givs verified that the known bounds
7409 of a biv did not overflow or wrap with respect to the extension for
7410 the giv. Therefore, constants need no additional adjustment. */
7414 /* Otherwise, we must adjust the value to compensate for the
7415 differing modes of the biv and the giv. */
7417 }
7418 \f
7419 struct combine_givs_stats
7420 {
7423 };
7425 static int
7429 {
7436 /* Stabilize the sort. */
7440 }
7442 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7443 any other. If so, point SAME to the giv combined with and set NEW_REG to
7444 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7445 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7447 static void
7451 {
7452 /* Additional benefit to add for being combined multiple times. */
7460 /* Count givs, because bl->giv_count is incorrect here. */
7464 giv_count++;
7466 giv_array
7477 {
7479 rtx single_use;
7484 /* If a DEST_REG GIV is used only once, do not allow it to combine
7485 with anything, for in doing so we will gain nothing that cannot
7486 be had by simply letting the GIV with which we would have combined
7487 to be reduced on its own. The losage shows up in particular with
7488 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7489 be seen elsewhere as well. */
7496 /* Add an additional weight for zero addends. */
7501 {
7502 rtx this_combine;
7507 {
7510 }
7511 }
7513 }
7515 /* Iterate, combining until we can't. */
7516 restart:
7520 {
7523 {
7529 }
7531 }
7534 {
7540 /* If it has already been combined, skip. */
7545 {
7548 /* If it has already been combined, skip. */
7550 {
7555 /* For destination, we now may replace by mem expression instead
7556 of register. This changes the costs considerably, so add the
7557 compensation. */
7567 /* ??? The new final_[bg]iv_value code does a much better job
7568 of finding replaceable giv's, and hence this code may no
7569 longer be necessary. */
7573 /* To help optimize the next set of combinations, remove
7574 this giv from the benefits of other potential mates. */
7576 {
7580 }
7587 }
7588 }
7590 /* To help optimize the next set of combinations, remove
7591 this giv from the benefits of other potential mates. */
7593 {
7595 {
7599 }
7603 /* We've finished with this giv, and everything it touched.
7604 Restart the combination so that proper weights for the
7605 rest of the givs are properly taken into account. */
7606 /* ??? Ideally we would compact the arrays at this point, so
7607 as to not cover old ground. But sanely compacting
7608 can_combine is tricky. */
7610 }
7611 }
7613 /* Clean up. */
7616 }
7617 \f
7618 /* Generate sequence for REG = B * M + A. */
7620 static rtx
7626 {
7627 rtx seq;
7628 rtx result;
7631 /* Use unsigned arithmetic. */
7639 }
7642 /* Update registers created in insn sequence SEQ. */
7644 static void
7647 rtx seq;
7648 {
7649 /* Update register info for alias analysis. */
7652 {
7655 {
7659 }
7660 }
7661 else
7662 {
7666 }
7667 }
7670 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7672 void
7679 basic_block before_bb;
7680 rtx before_insn;
7681 {
7682 rtx seq;
7685 {
7688 }
7690 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7693 /* Increase the lifetime of any invariants moved further in code. */
7700 /* It is possible that the expansion created lots of new registers.
7701 Iterate over the sequence we just created and record them all. */
7703 }
7706 /* Emit insns in loop pre-header to set REG = B * M + A. */
7708 void
7715 {
7716 rtx seq;
7718 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7721 /* Increase the lifetime of any invariants moved further in code.
7722 ???? Is this really necessary? */
7729 /* It is possible that the expansion created lots of new registers.
7730 Iterate over the sequence we just created and record them all. */
7732 }
7735 /* Emit insns after loop to set REG = B * M + A. */
7737 void
7744 {
7745 rtx seq;
7747 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7752 /* It is possible that the expansion created lots of new registers.
7753 Iterate over the sequence we just created and record them all. */
7755 }
7759 /* Similar to gen_add_mult, but compute cost rather than generating
7760 sequence. */
7762 static int
7768 {
7778 {
7783 }
7786 }
7787 \f
7788 /* Test whether A * B can be computed without
7789 an actual multiply insn. Value is 1 if so. */
7791 static int
7793 rtx a;
7794 rtx b;
7795 {
7797 rtx tmp;
7800 /* If only one is constant, make it B. */
7804 /* If first constant, both constant, so don't need multiply. */
7808 /* If second not constant, neither is constant, so would need multiply. */
7812 /* One operand is constant, so might not need multiply insn. Generate the
7813 code for the multiply and see if a call or multiply, or long sequence
7814 of insns is generated. */
7822 {
7827 else
7829 {
7838 {
7841 }
7842 }
7843 }
7853 }
7854 \f
7855 /* Check to see if loop can be terminated by a "decrement and branch until
7856 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7857 Also try reversing an increment loop to a decrement loop
7858 to see if the optimization can be performed.
7859 Value is nonzero if optimization was performed. */
7861 /* This is useful even if the architecture doesn't have such an insn,
7862 because it might change a loops which increments from 0 to n to a loop
7863 which decrements from n to 0. A loop that decrements to zero is usually
7864 faster than one that increments from zero. */
7866 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7867 such as approx_final_value, biv_total_increment, loop_iterations, and
7868 final_[bg]iv_value. */
7870 static int
7874 {
7879 rtx reg;
7880 rtx jump_label;
7881 rtx final_value;
7882 rtx start_value;
7883 rtx new_add_val;
7884 rtx comparison;
7885 rtx before_comparison;
7886 rtx p;
7887 rtx jump;
7888 rtx first_compare;
7893 /* If last insn is a conditional branch, and the insn before tests a
7894 register value, try to optimize it. Otherwise, we can't do anything. */
7903 /* Try to compute whether the compare/branch at the loop end is one or
7904 two instructions. */
7910 else
7913 {
7914 /* If more than one condition is present to control the loop, then
7915 do not proceed, as this function does not know how to rewrite
7916 loop tests with more than one condition.
7918 Look backwards from the first insn in the last comparison
7919 sequence and see if we've got another comparison sequence. */
7921 rtx jump1;
7925 }
7927 /* Check all of the bivs to see if the compare uses one of them.
7928 Skip biv's set more than once because we can't guarantee that
7929 it will be zero on the last iteration. Also skip if the biv is
7930 used between its update and the test insn. */
7933 {
7938 first_compare))
7940 }
7945 /* Look for the case where the basic induction variable is always
7946 nonnegative, and equals zero on the last iteration.
7947 In this case, add a reg_note REG_NONNEG, which allows the
7948 m68k DBRA instruction to be used. */
7956 {
7957 /* Initial value must be greater than 0,
7958 init_val % -dec_value == 0 to ensure that it equals zero on
7959 the last iteration */
7965 {
7966 /* register always nonnegative, add REG_NOTE to branch */
7974 }
7976 /* If the decrement is 1 and the value was tested as >= 0 before
7977 the loop, then we can safely optimize. */
7979 {
7992 {
8000 }
8001 }
8002 }
8005 {
8006 /* Try to change inc to dec, so can apply above optimization. */
8007 /* Can do this if:
8008 all registers modified are induction variables or invariant,
8009 all memory references have non-overlapping addresses
8010 (obviously true if only one write)
8011 allow 2 insns for the compare/jump at the end of the loop. */
8012 /* Also, we must avoid any instructions which use both the reversed
8013 biv and another biv. Such instructions will fail if the loop is
8014 reversed. We meet this condition by requiring that either
8015 no_use_except_counting is true, or else that there is only
8016 one biv. */
8018 /* 1 if the iteration var is used only to count iterations. */
8020 /* 1 if the loop has no memory store, or it has a single memory store
8021 which is reversible. */
8027 {
8031 /* If there are no givs for this biv, and the only exit is the
8032 fall through at the end of the loop, then
8033 see if perhaps there are no uses except to count. */
8037 {
8042 /* An insn that sets the biv is okay. */
8043 ;
8047 {
8048 /* If either of these insns uses the biv and sets a pseudo
8049 that has more than one usage, then the biv has uses
8050 other than counting since it's used to derive a value
8051 that is used more than one time. */
8053 regs);
8055 {
8058 }
8059 }
8061 {
8064 }
8065 }
8067 /* A biv has uses besides counting if it is used to set
8068 another biv. */
8072 {
8075 }
8076 }
8079 /* No need to worry about MEMs. */
8080 ;
8082 {
8087 /* If the loop has a single store, and the destination address is
8088 invariant, then we can't reverse the loop, because this address
8089 might then have the wrong value at loop exit.
8090 This would work if the source was invariant also, however, in that
8091 case, the insn should have been moved out of the loop. */
8094 {
8097 /* If we could prove that each of the memory locations
8098 written to was different, then we could reverse the
8099 store -- but we don't presently have any way of
8100 knowing that. */
8103 /* If the store depends on a register that is set after the
8104 store, it depends on the initial value, and is thus not
8105 reversible. */
8107 {
8114 }
8115 }
8116 }
8117 else
8120 /* This code only acts for innermost loops. Also it simplifies
8121 the memory address check by only reversing loops with
8122 zero or one memory access.
8123 Two memory accesses could involve parts of the same array,
8124 and that can't be reversed.
8125 If the biv is used only for counting, than we don't need to worry
8126 about all these things. */
8131 && reversible_mem_store
8136 {
8137 rtx tem;
8139 /* Loop can be reversed. */
8143 /* Now check other conditions:
8145 The increment must be a constant, as must the initial value,
8146 and the comparison code must be LT.
8148 This test can probably be improved since +/- 1 in the constant
8149 can be obtained by changing LT to LE and vice versa; this is
8150 confusing. */
8153 /* for constants, LE gets turned into LT */
8157 {
8168 comparison_const_width
8170 else
8171 comparison_const_width
8175 comparison_sign_mask
8178 /* If the comparison value is not a loop invariant, then we
8179 can not reverse this loop.
8181 ??? If the insns which initialize the comparison value as
8182 a whole compute an invariant result, then we could move
8183 them out of the loop and proceed with loop reversal. */
8191 /* Normalize the initial value if it is an integer and
8192 has no other use except as a counter. This will allow
8193 a few more loops to be reversed. */
8197 {
8199 /* The code below requires comparison_val to be a multiple
8200 of add_val in order to do the loop reversal, so
8201 round up comparison_val to a multiple of add_val.
8202 Since comparison_value is constant, we know that the
8203 current comparison code is LT. */
8205 comparison_val
8207 /* We postpone overflow checks for COMPARISON_VAL here;
8208 even if there is an overflow, we might still be able to
8209 reverse the loop, if converting the loop exit test to
8210 NE is possible. */
8212 }
8214 /* First check if we can do a vanilla loop reversal. */
8216 /* If we have a decrement_and_branch_on_count,
8217 prefer the NE test, since this will allow that
8218 instruction to be generated. Note that we must
8219 use a vanilla loop reversal if the biv is used to
8220 calculate a giv or has a non-counting use. */
8221 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8222 && defined (HAVE_decrement_and_branch_on_count)
8226 #endif
8228 /* Now do postponed overflow checks on COMPARISON_VAL. */
8231 {
8232 /* Register will always be nonnegative, with value
8233 0 on last iteration */
8237 }
8241 {
8244 }
8245 else
8251 /* If the initial value is not zero, or if the comparison
8252 value is not an exact multiple of the increment, then we
8253 can not reverse this loop. */
8256 {
8259 }
8260 else
8261 {
8264 }
8268 /* Reset these in case we normalized the initial value
8269 and comparison value above. */
8272 {
8274 final_value
8276 }
8279 /* Save some info needed to produce the new insns. */
8284 /* Set start_value; if this is not a CONST_INT, we need
8285 to generate a SUB.
8286 Initialize biv to start_value before loop start.
8287 The old initializing insn will be deleted as a
8288 dead store by flow.c. */
8291 {
8294 }
8296 {
8304 start_value
8310 }
8312 {
8315 initial_value);
8319 start_value
8322 }
8323 else
8324 /* We could handle the other cases too, but it'll be
8325 better to have a testcase first. */
8328 /* We may not have a single insn which can increment a reg, so
8329 create a sequence to hold all the insns from expand_inc. */
8338 /* Update biv info to reflect its new status. */
8343 /* Update loop info. */
8352 /* Inc LABEL_NUSES so that delete_insn will
8353 not delete the label. */
8356 /* Emit an insn after the end of the loop to set the biv's
8357 proper exit value if it is used anywhere outside the loop. */
8363 /* Delete compare/branch at end of loop. */
8368 /* Add new compare/branch insn at end of loop. */
8380 ;
8386 {
8388 {
8389 /* Increment of LABEL_NUSES done above. */
8390 /* Register is now always nonnegative,
8391 so add REG_NONNEG note to the branch. */
8394 }
8396 }
8398 /* No insn may reference both the reversed and another biv or it
8399 will fail (see comment near the top of the loop reversal
8400 code).
8401 Earlier on, we have verified that the biv has no use except
8402 counting, or it is the only biv in this function.
8403 However, the code that computes no_use_except_counting does
8404 not verify reg notes. It's possible to have an insn that
8405 references another biv, and has a REG_EQUAL note with an
8406 expression based on the reversed biv. To avoid this case,
8407 remove all REG_EQUAL notes based on the reversed biv
8408 here. */
8411 {
8414 /* If this is a set of a GIV based on the reversed biv, any
8415 REG_EQUAL notes should still be correct. */
8422 {
8427 else
8429 }
8430 }
8432 /* Mark that this biv has been reversed. Each giv which depends
8433 on this biv, and which is also live past the end of the loop
8434 will have to be fixed up. */
8439 {
8443 else
8445 }
8448 }
8449 }
8450 }
8453 }
8454 \f
8455 /* Verify whether the biv BL appears to be eliminable,
8456 based on the insns in the loop that refer to it.
8458 If ELIMINATE_P is non-zero, actually do the elimination.
8460 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8461 determine whether invariant insns should be placed inside or at the
8462 start of the loop. */
8464 static int
8470 {
8473 rtx p;
8475 /* Scan all insns in the loop, stopping if we find one that uses the
8476 biv in a way that we cannot eliminate. */
8479 {
8484 /* If this is a libcall that sets a giv, skip ahead to its end. */
8486 {
8490 {
8495 {
8502 }
8503 }
8504 }
8509 {
8515 }
8516 }
8519 {
8524 }
8527 }
8528 \f
8529 /* INSN and REFERENCE are instructions in the same insn chain.
8530 Return non-zero if INSN is first. */
8532 int
8535 {
8539 {
8540 /* Start with test for not first so that INSN == REFERENCE yields not
8541 first. */
8547 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8548 previous insn, hence the <= comparison below does not work if
8549 P is a note. */
8560 }
8561 }
8563 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8564 the offset that we have to take into account due to auto-increment /
8565 div derivation is zero. */
8566 static int
8569 rtx insn;
8570 {
8571 /* If the giv V had the auto-inc address optimization applied
8572 to it, and INSN occurs between the giv insn and the biv
8573 insn, then we'd have to adjust the value used here.
8574 This is rare, so we don't bother to make this possible. */
8583 }
8585 /* If BL appears in X (part of the pattern of INSN), see if we can
8586 eliminate its use. If so, return 1. If not, return 0.
8588 If BIV does not appear in X, return 1.
8590 If ELIMINATE_P is non-zero, actually do the elimination.
8591 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8592 Depending on how many items have been moved out of the loop, it
8593 will either be before INSN (when WHERE_INSN is non-zero) or at the
8594 start of the loop (when WHERE_INSN is zero). */
8596 static int
8602 basic_block where_bb;
8603 rtx where_insn;
8604 {
8610 #ifdef HAVE_cc0
8612 #endif
8618 {
8620 /* If we haven't already been able to do something with this BIV,
8621 we can't eliminate it. */
8627 /* If this sets the BIV, it is not a problem. */
8631 /* If this is an insn that defines a giv, it is also ok because
8632 it will go away when the giv is reduced. */
8637 #ifdef HAVE_cc0
8639 {
8640 /* Can replace with any giv that was reduced and
8641 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8642 Require a constant for MULT_VAL, so we know it's nonzero.
8643 ??? We disable this optimization to avoid potential
8644 overflows. */
8652 {
8659 /* If the giv has the opposite direction of change,
8660 then reverse the comparison. */
8664 else
8667 /* We can probably test that giv's reduced reg. */
8670 }
8672 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8673 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8674 Require a constant for MULT_VAL, so we know it's nonzero.
8675 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8676 overflow problem. */
8688 {
8695 /* If the giv has the opposite direction of change,
8696 then reverse the comparison. */
8700 else
8704 /* Replace biv with the giv's reduced register. */
8709 /* Insn doesn't support that constant or invariant. Copy it
8710 into a register (it will be a loop invariant.) */
8717 /* Substitute the new register for its invariant value in
8718 the compare expression. */
8722 }
8723 }
8724 #endif
8731 /* See if either argument is the biv. */
8736 else
8740 {
8741 /* First try to replace with any giv that has constant positive
8742 mult_val and constant add_val. We might be able to support
8743 negative mult_val, but it seems complex to do it in general. */
8755 {
8762 /* Replace biv with the giv's reduced reg. */
8765 /* If all constants are actually constant integers and
8766 the derived constant can be directly placed in the COMPARE,
8767 do so. */
8771 {
8776 }
8777 else
8778 {
8779 /* Otherwise, load it into a register. */
8785 }
8788 }
8790 /* Look for giv with positive constant mult_val and nonconst add_val.
8791 Insert insns to calculate new compare value.
8792 ??? Turn this off due to possible overflow. */
8800 {
8801 rtx tem;
8811 /* Replace biv with giv's reduced register. */
8815 /* Compute value to compare against. */
8819 /* Use it in this insn. */
8823 }
8824 }
8826 {
8828 {
8829 /* Look for giv with constant positive mult_val and nonconst
8830 add_val. Insert insns to compute new compare value.
8831 ??? Turn this off due to possible overflow. */
8838 {
8839 rtx tem;
8849 /* Replace biv with giv's reduced register. */
8853 /* Compute value to compare against. */
8860 }
8861 }
8863 /* This code has problems. Basically, you can't know when
8864 seeing if we will eliminate BL, whether a particular giv
8865 of ARG will be reduced. If it isn't going to be reduced,
8866 we can't eliminate BL. We can try forcing it to be reduced,
8867 but that can generate poor code.
8869 The problem is that the benefit of reducing TV, below should
8870 be increased if BL can actually be eliminated, but this means
8871 we might have to do a topological sort of the order in which
8872 we try to process biv. It doesn't seem worthwhile to do
8873 this sort of thing now. */
8875 #if 0
8876 /* Otherwise the reg compared with had better be a biv. */
8881 /* Look for a pair of givs, one for each biv,
8882 with identical coefficients. */
8884 {
8896 {
8903 /* Replace biv with its giv's reduced reg. */
8905 /* Replace other operand with the other giv's
8906 reduced reg. */
8909 }
8910 }
8911 #endif
8912 }
8914 /* If we get here, the biv can't be eliminated. */
8918 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8919 biv is used in it, since it will be replaced. */
8927 }
8929 /* See if any subexpression fails elimination. */
8932 {
8934 {
8947 }
8948 }
8951 }
8952 \f
8953 /* Return nonzero if the last use of REG
8954 is in an insn following INSN in the same basic block. */
8956 static int
8958 rtx reg;
8959 rtx insn;
8960 {
8961 rtx n;
8965 {
8968 }
8970 }
8971 \f
8972 /* Called via `note_stores' to record the initial value of a biv. Here we
8973 just record the location of the set and process it later. */
8975 static void
8977 rtx dest;
8978 rtx set;
8980 {
8991 /* If this is the first set found, record it. */
8993 {
8996 }
8997 }
8998 \f
8999 /* If any of the registers in X are "old" and currently have a last use earlier
9000 than INSN, update them to have a last use of INSN. Their actual last use
9001 will be the previous insn but it will not have a valid uid_luid so we can't
9002 use it. X must be a source expression only. */
9004 static void
9006 rtx x;
9007 rtx insn;
9008 {
9009 /* Check for the case where INSN does not have a valid luid. In this case,
9010 there is no need to modify the regno_last_uid, as this can only happen
9011 when code is inserted after the loop_end to set a pseudo's final value,
9012 and hence this insn will never be the last use of x.
9013 ???? This comment is not correct. See for example loop_givs_reduce.
9014 This may insert an insn before another new insn. */
9018 {
9020 }
9021 else
9022 {
9026 {
9032 }
9033 }
9034 }
9035 \f
9036 /* Given an insn INSN and condition COND, return the condition in a
9037 canonical form to simplify testing by callers. Specifically:
9039 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9040 (2) Both operands will be machine operands; (cc0) will have been replaced.
9041 (3) If an operand is a constant, it will be the second operand.
9042 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9043 for GE, GEU, and LEU.
9045 If the condition cannot be understood, or is an inequality floating-point
9046 comparison which needs to be reversed, 0 will be returned.
9048 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9050 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9051 insn used in locating the condition was found. If a replacement test
9052 of the condition is desired, it should be placed in front of that
9053 insn and we will be sure that the inputs are still valid.
9055 If WANT_REG is non-zero, we wish the condition to be relative to that
9056 register, if possible. Therefore, do not canonicalize the condition
9057 further. */
9059 rtx
9061 rtx insn;
9062 rtx cond;
9065 rtx want_reg;
9066 {
9069 rtx set;
9070 rtx tem;
9088 /* If we are comparing a register with zero, see if the register is set
9089 in the previous insn to a COMPARE or a comparison operation. Perform
9090 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9091 in cse.c */
9096 {
9097 /* Set non-zero when we find something of interest. */
9100 #ifdef HAVE_cc0
9101 /* If comparison with cc0, import actual comparison from compare
9102 insn. */
9104 {
9115 }
9116 #endif
9118 /* If this is a COMPARE, pick up the two things being compared. */
9120 {
9124 }
9128 /* Go back to the previous insn. Stop if it is not an INSN. We also
9129 stop if it isn't a single set or if it has a REG_INC note because
9130 we don't want to bother dealing with it. */
9144 /* If this is setting OP0, get what it sets it to if it looks
9145 relevant. */
9147 {
9150 /* ??? We may not combine comparisons done in a CCmode with
9151 comparisons not done in a CCmode. This is to aid targets
9152 like Alpha that have an IEEE compliant EQ instruction, and
9153 a non-IEEE compliant BEQ instruction. The use of CCmode is
9154 actually artificial, simply to prevent the combination, but
9155 should not affect other platforms.
9157 However, we must allow VOIDmode comparisons to match either
9158 CCmode or non-CCmode comparison, because some ports have
9159 modeless comparisons inside branch patterns.
9161 ??? This mode check should perhaps look more like the mode check
9162 in simplify_comparison in combine. */
9170 && (STORE_FLAG_VALUE
9173 #ifdef FLOAT_STORE_FLAG_VALUE
9176 && (REAL_VALUE_NEGATIVE
9178 #endif
9179 ))
9190 && (STORE_FLAG_VALUE
9193 #ifdef FLOAT_STORE_FLAG_VALUE
9196 && (REAL_VALUE_NEGATIVE
9198 #endif
9199 ))
9205 {
9208 }
9209 else
9211 }
9214 /* If this sets OP0, but not directly, we have to give up. */
9218 {
9222 {
9227 }
9232 }
9233 }
9235 /* If constant is first, put it last. */
9239 /* If OP0 is the result of a comparison, we weren't able to find what
9240 was really being compared, so fail. */
9244 /* Canonicalize any ordered comparison with integers involving equality
9245 if we can do computations in the relevant mode and we do not
9246 overflow. */
9251 {
9254 unsigned HOST_WIDE_INT max_val
9258 {
9264 /* When cross-compiling, const_val might be sign-extended from
9265 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9285 }
9286 }
9288 #ifdef HAVE_cc0
9289 /* Never return CC0; return zero instead. */
9292 #endif
9295 }
9297 /* Given a jump insn JUMP, return the condition that will cause it to branch
9298 to its JUMP_LABEL. If the condition cannot be understood, or is an
9299 inequality floating-point comparison which needs to be reversed, 0 will
9300 be returned.
9302 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9303 insn used in locating the condition was found. If a replacement test
9304 of the condition is desired, it should be placed in front of that
9305 insn and we will be sure that the inputs are still valid. */
9307 rtx
9309 rtx jump;
9311 {
9312 rtx cond;
9314 rtx set;
9316 /* If this is not a standard conditional jump, we can't parse it. */
9324 /* If this branches to JUMP_LABEL when the condition is false, reverse
9325 the condition. */
9326 reverse
9331 }
9333 /* Similar to above routine, except that we also put an invariant last
9334 unless both operands are invariants. */
9336 rtx
9339 rtx x;
9340 {
9350 }
9352 /* Scan the function and determine whether it has indirect (computed) jumps.
9354 This is taken mostly from flow.c; similar code exists elsewhere
9355 in the compiler. It may be useful to put this into rtlanal.c. */
9356 static int
9358 rtx start;
9359 {
9360 rtx insn;
9367 }
9369 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9370 documentation for LOOP_MEMS for the definition of `appropriate'.
9371 This function is called from prescan_loop via for_each_rtx. */
9373 static int
9377 {
9386 {
9391 /* We're not interested in MEMs that are only clobbered. */
9395 /* We're not interested in the MEM associated with a
9396 CONST_DOUBLE, so there's no need to traverse into this. */
9400 /* We're not interested in any MEMs that only appear in notes. */
9404 /* This is not a MEM. */
9406 }
9408 /* See if we've already seen this MEM. */
9411 {
9413 /* The modes of the two memory accesses are different. If
9414 this happens, something tricky is going on, and we just
9415 don't optimize accesses to this MEM. */
9419 }
9421 /* Resize the array, if necessary. */
9423 {
9426 else
9432 }
9434 /* Actually insert the MEM. */
9436 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9437 because we can't put it in a register. We still store it in the
9438 table, though, so that if we see the same address later, but in a
9439 non-BLK mode, we'll not think we can optimize it at that point. */
9445 }
9448 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9450 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9451 register that is modified by an insn between FROM and TO. If the
9452 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9453 more, stop incrementing it, to avoid overflow.
9455 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9456 register I is used, if it is only used once. Otherwise, it is set
9457 to 0 (for no uses) or const0_rtx for more than one use. This
9458 parameter may be zero, in which case this processing is not done.
9460 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9461 optimize register I. */
9463 static void
9467 {
9470 /* last_set[n] is nonzero iff reg n has been set in the current
9471 basic block. In that case, it is the insn that last set reg n. */
9473 rtx insn;
9479 /* Grow the regs array if not allocated or too small. */
9481 {
9487 /* Zero the new elements. */
9490 }
9492 /* Clear previously scanned fields but do not clear n_times_set. */
9494 {
9498 }
9502 /* Scan the loop, recording register usage. */
9505 {
9507 {
9508 /* Record registers that have exactly one use. */
9511 /* Include uses in REG_EQUAL notes. */
9519 {
9523 last_set);
9524 }
9525 }
9529 }
9531 /* Invalidate all hard registers clobbered by calls. With one exception:
9532 a call-clobbered PIC register is still function-invariant for our
9533 purposes, since we can hoist any PIC calculations out of the loop.
9534 Thus the call to rtx_varies_p. */
9539 {
9542 }
9544 #ifdef AVOID_CCMODE_COPIES
9545 /* Don't try to move insns which set CC registers if we should not
9546 create CCmode register copies. */
9550 #endif
9552 /* Set regs->array[I].n_times_set for the new registers. */
9557 }
9559 /* Returns the number of real INSNs in the LOOP. */
9561 static int
9564 {
9566 rtx insn;
9574 }
9576 /* Move MEMs into registers for the duration of the loop. */
9578 static void
9581 {
9588 rtx end_label;
9589 /* Nonzero if the next instruction may never be executed. */
9596 /* We cannot use next_label here because it skips over normal insns. */
9601 /* Check to see if it's possible that some instructions in the loop are
9602 never executed. Also check if there is a goto out of the loop other
9603 than right after the end of the loop. */
9607 {
9611 /* If we enter the loop in the middle, and scan
9612 around to the beginning, don't set maybe_never
9613 for that. This must be an unconditional jump,
9614 otherwise the code at the top of the loop might
9615 never be executed. Unconditional jumps are
9616 followed a by barrier then loop end. */
9621 {
9622 /* If this is a jump outside of the loop but not right
9623 after the end of the loop, we would have to emit new fixup
9624 sequences for each such label. */
9626 JUMP_INSN is executed, we must be conservative. */
9635 /* Something complicated. */
9637 else
9638 /* If there are any more instructions in the loop, they
9639 might not be reached. */
9641 }
9644 }
9646 /* Find start of the extended basic block that enters the loop. */
9650 ;
9655 /* Build table of mems that get set to constant values before the
9656 loop. */
9660 /* Actually move the MEMs. */
9662 {
9663 regset_head load_copies;
9664 regset_head store_copies;
9666 rtx reg;
9668 rtx mem_list_entry;
9672 /* There's no telling whether or not MEM is modified. */
9675 /* Go through the MEMs written to in the loop to see if this
9676 one is aliased by one of them. */
9679 {
9684 {
9685 /* MEM is indeed aliased by this store. */
9688 }
9690 }
9696 /* If this MEM is written to, we must be sure that there
9697 are no reads from another MEM that aliases this one. */
9699 {
9703 {
9707 VOIDmode,
9709 rtx_varies_p))
9710 {
9711 /* It's not safe to hoist loop_info->mems[i] out of
9712 the loop because writes to it might not be
9713 seen by reads from loop_info->mems[j]. */
9716 }
9717 }
9718 }
9721 /* We can't access the MEM outside the loop; it might
9722 cause a trap that wouldn't have happened otherwise. */
9726 /* We thought we were going to lift this MEM out of the
9727 loop, but later discovered that we could not. */
9733 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9734 order to keep scan_loop from moving stores to this MEM
9735 out of the loop just because this REG is neither a
9736 user-variable nor used in the loop test. */
9741 /* Now, replace all references to the MEM with the
9742 corresponding pseudos. */
9747 {
9749 {
9750 rtx set;
9754 /* See if this copies the mem into a register that isn't
9755 modified afterwards. We'll try to do copy propagation
9756 a little further on. */
9758 /* @@@ This test is _way_ too conservative. */
9759 && ! maybe_never
9767 /* See if this copies the mem from a register that isn't
9768 modified afterwards. We'll try to remove the
9769 redundant copy later on by doing a little register
9770 renaming and copy propagation. This will help
9771 to untangle things for the BIV detection code. */
9773 && ! maybe_never
9781 /* Replace the memory reference with the shadow register. */
9784 }
9789 }
9792 /* We couldn't replace all occurrences of the MEM. */
9794 else
9795 {
9796 /* Load the memory immediately before LOOP->START, which is
9797 the NOTE_LOOP_BEG. */
9799 rtx set;
9805 {
9809 {
9813 /* Extending hard register lifetimes causes crash
9814 on SRC targets. Doing so on non-SRC is
9815 probably also not good idea, since we most
9816 probably have pseudoregister equivalence as
9817 well. */
9820 }
9821 /* Use the constant equivalence if that is cheap enough. */
9827 {
9830 }
9832 /* If best_equiv is nonzero, we know that MEM is set to a
9833 constant or register before the loop. We will use this
9834 knowledge to initialize the shadow register with that
9835 constant or reg rather than by loading from MEM. */
9838 }
9843 {
9846 {
9849 }
9850 }
9856 {
9858 {
9861 }
9863 /* Store the memory immediately after END, which is
9864 the NOTE_LOOP_END. */
9867 }
9870 {
9875 }
9877 /* Attempt a bit of copy propagation. This helps untangle the
9878 data flow, and enables {basic,general}_induction_var to find
9879 more bivs/givs. */
9880 EXECUTE_IF_SET_IN_REG_SET
9882 {
9884 });
9887 EXECUTE_IF_SET_IN_REG_SET
9889 {
9891 });
9893 }
9894 }
9897 {
9898 /* Now, we need to replace all references to the previous exit
9899 label with the new one. */
9900 rtx_pair rr;
9905 {
9908 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9909 field. This is not handled by for_each_rtx because it doesn't
9910 handle unprinted ('0') fields. We need to update JUMP_LABEL
9911 because the immediately following unroll pass will use it.
9912 replace_label would not work anyways, because that only handles
9913 LABEL_REFs. */
9916 }
9917 }
9920 }
9922 /* For communication between note_reg_stored and its caller. */
9923 struct note_reg_stored_arg
9924 {
9926 rtx reg;
9927 };
9929 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9930 is equal to ARG. */
9931 static void
9935 {
9939 }
9941 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9942 There must be exactly one insn that sets this pseudo; it will be
9943 deleted if all replacements succeed and we can prove that the register
9944 is not used after the loop. */
9946 static void
9949 rtx replacement;
9951 {
9952 /* This is the reg that we are copying from. */
9955 rtx insn;
9956 /* These help keep track of whether we replaced all uses of the reg. */
9963 {
9964 rtx set;
9966 /* Only substitute within one extended basic block from the initializing
9967 insn. */
9974 /* Is this the initializing insn? */
9979 {
9986 }
9988 /* Only substitute after seeing the initializing insn. */
9990 {
9997 /* Stop replacing when REPLACEMENT is modified. */
10002 {
10005 /* It is possible that we've turned previously valid REG_EQUAL to
10006 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10007 REPLACEMENT is modified, we get different meaning. */
10011 }
10012 }
10013 }
10017 {
10021 {
10022 rtx first;
10023 rtx retval_note;
10025 /* Assume we're just deleting INIT_INSN. */
10027 /* Look for REG_RETVAL note. If we're deleting the end of
10028 the libcall sequence, the whole sequence can go. */
10030 /* If we found a REG_RETVAL note, find the first instruction
10031 in the sequence. */
10035 /* Delete the instructions. */
10037 }
10040 }
10041 }
10043 /* Replace all the instructions from FIRST up to and including LAST
10044 with NOTE_INSN_DELETED notes. */
10046 static void
10048 rtx first;
10049 rtx last;
10050 {
10052 {
10058 /* If this was the LAST instructions we're supposed to delete,
10059 we're done. */
10064 }
10065 }
10067 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10068 loop LOOP if the order of the sets of these registers can be
10069 swapped. There must be exactly one insn within the loop that sets
10070 this pseudo followed immediately by a move insn that sets
10071 REPLACEMENT with REGNO. */
10072 static void
10075 rtx replacement;
10077 {
10078 rtx insn;
10087 {
10088 /* Search for the insn that copies REGNO to NEW_REGNO? */
10096 }
10099 {
10100 rtx prev_insn;
10101 rtx prev_set;
10103 /* Some DEF-USE info would come in handy here to make this
10104 function more general. For now, just check the previous insn
10105 which is the most likely candidate for setting REGNO. */
10113 {
10114 /* We have:
10115 (set (reg regno) (expr))
10116 (set (reg new_regno) (reg regno))
10118 so try converting this to:
10119 (set (reg new_regno) (expr))
10120 (set (reg regno) (reg new_regno))
10122 The former construct is often generated when a global
10123 variable used for an induction variable is shadowed by a
10124 register (NEW_REGNO). The latter construct improves the
10125 chances of GIV replacement and BIV elimination. */
10135 {
10142 /* Update first use of REGNO. */
10146 /* Now perform copy propagation to hopefully
10147 remove all uses of REGNO within the loop. */
10149 }
10150 }
10151 }
10152 }
10154 /* Replace MEM with its associated pseudo register. This function is
10155 called from load_mems via for_each_rtx. DATA is actually a pointer
10156 to a structure describing the instruction currently being scanned
10157 and the MEM we are currently replacing. */
10159 static int
10163 {
10171 {
10176 /* We're not interested in the MEM associated with a
10177 CONST_DOUBLE, so there's no need to traverse into one. */
10181 /* This is not a MEM. */
10183 }
10186 /* This is not the MEM we are currently replacing. */
10189 /* Actually replace the MEM. */
10193 }
10195 static void
10197 rtx insn;
10198 rtx mem;
10199 rtx reg;
10200 {
10201 loop_replace_args args;
10208 }
10210 /* Replace one register with another. Called through for_each_rtx; PX points
10211 to the rtx being scanned. DATA is actually a pointer to
10212 a structure of arguments. */
10214 static int
10218 {
10229 }
10231 static void
10233 rtx insn;
10234 rtx reg;
10235 rtx replacement;
10236 {
10237 loop_replace_args args;
10244 }
10246 /* Replace occurrences of the old exit label for the loop with the new
10247 one. DATA is an rtx_pair containing the old and new labels,
10248 respectively. */
10250 static int
10254 {
10273 }
10274 \f
10275 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10276 (ignored in the interim). */
10278 static rtx
10281 basic_block where_bb ATTRIBUTE_UNUSED;
10282 rtx where_insn;
10283 rtx pattern;
10284 {
10286 }
10289 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10290 in basic block WHERE_BB (ignored in the interim) within the loop
10291 otherwise hoist PATTERN into the loop pre-header. */
10293 rtx
10296 basic_block where_bb ATTRIBUTE_UNUSED;
10297 rtx where_insn;
10298 rtx pattern;
10299 {
10303 }
10306 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10307 WHERE_BB (ignored in the interim) within the loop. */
10309 static rtx
10312 basic_block where_bb ATTRIBUTE_UNUSED;
10313 rtx where_insn;
10314 rtx pattern;
10315 {
10317 }
10320 /* Hoist insn for PATTERN into the loop pre-header. */
10322 rtx
10325 rtx pattern;
10326 {
10328 }
10331 /* Hoist call insn for PATTERN into the loop pre-header. */
10333 static rtx
10336 rtx pattern;
10337 {
10339 }
10342 /* Sink insn for PATTERN after the loop end. */
10344 rtx
10347 rtx pattern;
10348 {
10350 }
10353 /* If the loop has multiple exits, emit insn for PATTERN before the
10354 loop to ensure that it will always be executed no matter how the
10355 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10356 since this is slightly more efficient. */
10358 static rtx
10361 rtx pattern;
10362 {
10365 else
10367 }
10368 \f
10369 static void
10374 {
10382 iv_num++;
10387 {
10390 }
10391 }
10394 static void
10399 {
10401 rtx incr;
10412 {
10415 }
10417 {
10420 }
10424 {
10428 }
10431 {
10435 }
10437 /* List the increments. */
10439 {
10443 }
10445 /* List the givs. */
10447 {
10452 else
10455 }
10456 }
10459 static void
10464 {
10475 {
10479 }
10482 }
10485 static void
10490 {
10497 else
10513 {
10515 {
10527 }
10528 }
10539 {
10543 }
10546 }
10549 void
10552 {
10554 }
10557 void
10560 {
10562 }
10565 void
10568 {
10570 }
10573 void
10576 {
10578 }
10581 #define LOOP_BLOCK_NUM_1(INSN) \
10582 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10584 /* The notes do not have an assigned block, so look at the next insn. */
10585 #define LOOP_BLOCK_NUM(INSN) \
10586 ((INSN) ? (GET_CODE (INSN) == NOTE \
10587 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10588 : LOOP_BLOCK_NUM_1 (INSN)) \
10589 : -1)
10591 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10593 static void
10598 {
10599 rtx label;
10604 /* Print diagnostics to compare our concept of a loop with
10605 what the loop notes say. */
10620 {
10640 {
10643 {
10646 }
10647 }
10650 /* This can happen when a marked loop appears as two nested loops,
10651 say from while (a || b) {}. The inner loop won't match
10652 the loop markers but the outer one will. */
10655 }
10656 }
10658 /* Call this function from the debugger to dump LOOP. */
10660 void
10663 {
10665 }
10667 /* Call this function from the debugger to dump LOOPS. */
10669 void
10672 {
10674 }