gcc/config/aarch64/aarch64.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_H
  23 #define GCC_AARCH64_H
  24
  25 /* Target CPU builtins.  */
  26 #define TARGET_CPU_CPP_BUILTINS()       \
  27   aarch64_cpu_cpp_builtins (pfile)
  28
  29 \f
  30
  31 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
  32
  33 /* Target machine storage layout.  */
  34
  35 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  36   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  37       && GET_MODE_SIZE (MODE) < 4)              \
  38     {                                           \
  39       if (MODE == QImode || MODE == HImode)     \
  40         {                                       \
  41           MODE = SImode;                        \
  42         }                                       \
  43     }
  44
  45 /* Bits are always numbered from the LSBit.  */
  46 #define BITS_BIG_ENDIAN 0
  47
  48 /* Big/little-endian flavour.  */
  49 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
  50 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
  51
  52 /* AdvSIMD is supported in the default configuration, unless disabled by
  53    -mgeneral-regs-only or by the +nosimd extension.  */
  54 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
  55 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
  56
  57 #define UNITS_PER_WORD          8
  58
  59 #define UNITS_PER_VREG          16
  60
  61 #define PARM_BOUNDARY           64
  62
  63 #define STACK_BOUNDARY          128
  64
  65 #define FUNCTION_BOUNDARY       32
  66
  67 #define EMPTY_FIELD_BOUNDARY    32
  68
  69 #define BIGGEST_ALIGNMENT       128
  70
  71 #define SHORT_TYPE_SIZE         16
  72
  73 #define INT_TYPE_SIZE           32
  74
  75 #define LONG_TYPE_SIZE          (TARGET_ILP32 ? 32 : 64)
  76
  77 #define POINTER_SIZE            (TARGET_ILP32 ? 32 : 64)
  78
  79 #define LONG_LONG_TYPE_SIZE     64
  80
  81 #define FLOAT_TYPE_SIZE         32
  82
  83 #define DOUBLE_TYPE_SIZE        64
  84
  85 #define LONG_DOUBLE_TYPE_SIZE   128
  86
  87 /* The architecture reserves all bits of the address for hardware use,
  88    so the vbit must go into the delta field of pointers to member
  89    functions.  This is the same config as that in the AArch32
  90    port.  */
  91 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
  92
  93 /* Align definitions of arrays, unions and structures so that
  94    initializations and copies can be made more efficient.  This is not
  95    ABI-changing, so it only affects places where we can see the
  96    definition.  Increasing the alignment tends to introduce padding,
  97    so don't do this when optimizing for size/conserving stack space.  */
  98 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN)                      \
  99   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 100     && (TREE_CODE (EXP) == ARRAY_TYPE                                   \
 101         || TREE_CODE (EXP) == UNION_TYPE                                \
 102         || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 103
 104 /* Align global data.  */
 105 #define DATA_ALIGNMENT(EXP, ALIGN)                      \
 106   AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
 107
 108 /* Similarly, make sure that objects on the stack are sensibly aligned.  */
 109 #define LOCAL_ALIGNMENT(EXP, ALIGN)                             \
 110   AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
 111
 112 #define STRUCTURE_SIZE_BOUNDARY         8
 113
 114 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY).  */
 115 #define MALLOC_ABI_ALIGNMENT  128
 116
 117 /* Defined by the ABI */
 118 #define WCHAR_TYPE "unsigned int"
 119 #define WCHAR_TYPE_SIZE                 32
 120
 121 /* Using long long breaks -ansi and -std=c90, so these will need to be
 122    made conditional for an LLP64 ABI.  */
 123
 124 #define SIZE_TYPE       "long unsigned int"
 125
 126 #define PTRDIFF_TYPE    "long int"
 127
 128 #define PCC_BITFIELD_TYPE_MATTERS       1
 129
 130 /* Major revision number of the ARM Architecture implemented by the target.  */
 131 extern unsigned aarch64_architecture_version;
 132
 133 /* Instruction tuning/selection flags.  */
 134
 135 /* Bit values used to identify processor capabilities.  */
 136 #define AARCH64_FL_SIMD       (1 << 0)  /* Has SIMD instructions.  */
 137 #define AARCH64_FL_FP         (1 << 1)  /* Has FP.  */
 138 #define AARCH64_FL_CRYPTO     (1 << 2)  /* Has crypto.  */
 139 #define AARCH64_FL_CRC        (1 << 3)  /* Has CRC.  */
 140 /* ARMv8.1-A architecture extensions.  */
 141 #define AARCH64_FL_LSE        (1 << 4)  /* Has Large System Extensions.  */
 142 #define AARCH64_FL_RDMA       (1 << 5)  /* Has Round Double Multiply Add.  */
 143 #define AARCH64_FL_V8_1       (1 << 6)  /* Has ARMv8.1-A extensions.  */
 144 /* ARMv8.2-A architecture extensions.  */
 145 #define AARCH64_FL_V8_2       (1 << 8)  /* Has ARMv8.2-A features.  */
 146 #define AARCH64_FL_F16        (1 << 9)  /* Has ARMv8.2-A FP16 extensions.  */
 147 /* ARMv8.3-A architecture extensions.  */
 148 #define AARCH64_FL_V8_3       (1 << 10)  /* Has ARMv8.3-A features.  */
 149 #define AARCH64_FL_RCPC       (1 << 11)  /* Has support for RCpc model.  */
 150 #define AARCH64_FL_DOTPROD    (1 << 12)  /* Has ARMv8.2-A Dot Product ins.  */
 151 /* New flags to split crypto into aes and sha2.  */
 152 #define AARCH64_FL_AES        (1 << 13)  /* Has Crypto AES.  */
 153 #define AARCH64_FL_SHA2       (1 << 14)  /* Has Crypto SHA2.  */
 154 /* ARMv8.4-A architecture extensions.  */
 155 #define AARCH64_FL_V8_4       (1 << 15)  /* Has ARMv8.4-A features.  */
 156 #define AARCH64_FL_SM4        (1 << 16)  /* Has ARMv8.4-A SM3 and SM4.  */
 157 #define AARCH64_FL_SHA3       (1 << 17)  /* Has ARMv8.4-a SHA3 and SHA512.  */
 158 #define AARCH64_FL_F16FML     (1 << 18)  /* Has ARMv8.4-a FP16 extensions.  */
 159
 160 /* Has FP and SIMD.  */
 161 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 162
 163 /* Has FP without SIMD.  */
 164 #define AARCH64_FL_FPQ16      (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
 165
 166 /* Architecture flags that effect instruction selection.  */
 167 #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
 168 #define AARCH64_FL_FOR_ARCH8_1                         \
 169   (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \
 170    | AARCH64_FL_RDMA | AARCH64_FL_V8_1)
 171 #define AARCH64_FL_FOR_ARCH8_2                  \
 172   (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
 173 #define AARCH64_FL_FOR_ARCH8_3                  \
 174   (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
 175 #define AARCH64_FL_FOR_ARCH8_4                  \
 176   (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \
 177    | AARCH64_FL_DOTPROD)
 178
 179 /* Macros to test ISA flags.  */
 180
 181 #define AARCH64_ISA_CRC            (aarch64_isa_flags & AARCH64_FL_CRC)
 182 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
 183 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
 184 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
 185 #define AARCH64_ISA_LSE            (aarch64_isa_flags & AARCH64_FL_LSE)
 186 #define AARCH64_ISA_RDMA           (aarch64_isa_flags & AARCH64_FL_RDMA)
 187 #define AARCH64_ISA_V8_2           (aarch64_isa_flags & AARCH64_FL_V8_2)
 188 #define AARCH64_ISA_F16            (aarch64_isa_flags & AARCH64_FL_F16)
 189 #define AARCH64_ISA_V8_3           (aarch64_isa_flags & AARCH64_FL_V8_3)
 190 #define AARCH64_ISA_DOTPROD        (aarch64_isa_flags & AARCH64_FL_DOTPROD)
 191 #define AARCH64_ISA_AES            (aarch64_isa_flags & AARCH64_FL_AES)
 192 #define AARCH64_ISA_SHA2           (aarch64_isa_flags & AARCH64_FL_SHA2)
 193 #define AARCH64_ISA_V8_4           (aarch64_isa_flags & AARCH64_FL_V8_4)
 194 #define AARCH64_ISA_SM4            (aarch64_isa_flags & AARCH64_FL_SM4)
 195 #define AARCH64_ISA_SHA3           (aarch64_isa_flags & AARCH64_FL_SHA3)
 196 #define AARCH64_ISA_F16FML         (aarch64_isa_flags & AARCH64_FL_F16FML)
 197
 198 /* Crypto is an optional extension to AdvSIMD.  */
 199 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
 200
 201 /* SHA2 is an optional extension to AdvSIMD.  */
 202 #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO)
 203
 204 /* SHA3 is an optional extension to AdvSIMD.  */
 205 #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3)
 206
 207 /* AES is an optional extension to AdvSIMD.  */
 208 #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO)
 209
 210 /* SM is an optional extension to AdvSIMD.  */
 211 #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4)
 212
 213 /* FP16FML is an optional extension to AdvSIMD.  */
 214 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST)
 215
 216 /* CRC instructions that can be enabled through +crc arch extension.  */
 217 #define TARGET_CRC32 (AARCH64_ISA_CRC)
 218
 219 /* Atomic instructions that can be enabled through the +lse extension.  */
 220 #define TARGET_LSE (AARCH64_ISA_LSE)
 221
 222 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
 223 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
 224 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
 225
 226 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod.  */
 227 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD)
 228
 229 /* ARMv8.3-A features.  */
 230 #define TARGET_ARMV8_3  (AARCH64_ISA_V8_3)
 231
 232 /* Make sure this is always defined so we don't have to check for ifdefs
 233    but rather use normal ifs.  */
 234 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
 235 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
 236 #else
 237 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
 238 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
 239 #endif
 240
 241 /* Apply the workaround for Cortex-A53 erratum 835769.  */
 242 #define TARGET_FIX_ERR_A53_835769       \
 243   ((aarch64_fix_a53_err835769 == 2)     \
 244   ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
 245
 246 /* Make sure this is always defined so we don't have to check for ifdefs
 247    but rather use normal ifs.  */
 248 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
 249 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
 250 #else
 251 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
 252 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
 253 #endif
 254
 255 /* Apply the workaround for Cortex-A53 erratum 843419.  */
 256 #define TARGET_FIX_ERR_A53_843419       \
 257   ((aarch64_fix_a53_err843419 == 2)     \
 258   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
 259
 260 /* ARMv8.1-A Adv.SIMD support.  */
 261 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
 262
 263 /* Standard register usage.  */
 264
 265 /* 31 64-bit general purpose registers R0-R30:
 266    R30          LR (link register)
 267    R29          FP (frame pointer)
 268    R19-R28      Callee-saved registers
 269    R18          The platform register; use as temporary register.
 270    R17          IP1 The second intra-procedure-call temporary register
 271                 (can be used by call veneers and PLT code); otherwise use
 272                 as a temporary register
 273    R16          IP0 The first intra-procedure-call temporary register (can
 274                 be used by call veneers and PLT code); otherwise use as a
 275                 temporary register
 276    R9-R15       Temporary registers
 277    R8           Structure value parameter / temporary register
 278    R0-R7        Parameter/result registers
 279
 280    SP           stack pointer, encoded as X/R31 where permitted.
 281    ZR           zero register, encoded as X/R31 elsewhere
 282
 283    32 x 128-bit floating-point/vector registers
 284    V16-V31      Caller-saved (temporary) registers
 285    V8-V15       Callee-saved registers
 286    V0-V7        Parameter/result registers
 287
 288    The vector register V0 holds scalar B0, H0, S0 and D0 in its least
 289    significant bits.  Unlike AArch32 S1 is not packed into D0,
 290    etc.  */
 291
 292 /* Note that we don't mark X30 as a call-clobbered register.  The idea is
 293    that it's really the call instructions themselves which clobber X30.
 294    We don't care what the called function does with it afterwards.
 295
 296    This approach makes it easier to implement sibcalls.  Unlike normal
 297    calls, sibcalls don't clobber X30, so the register reaches the
 298    called function intact.  EPILOGUE_USES says that X30 is useful
 299    to the called function.  */
 300
 301 #define FIXED_REGISTERS                                 \
 302   {                                                     \
 303     0, 0, 0, 0,   0, 0, 0, 0,   /* R0 - R7 */           \
 304     0, 0, 0, 0,   0, 0, 0, 0,   /* R8 - R15 */          \
 305     0, 0, 0, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 306     0, 0, 0, 0,   0, 1, 0, 1,   /* R24 - R30, SP */     \
 307     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
 308     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 309     0, 0, 0, 0,   0, 0, 0, 0,   /* V16 - V23 */         \
 310     0, 0, 0, 0,   0, 0, 0, 0,   /* V24 - V31 */         \
 311     1, 1, 1,                    /* SFP, AP, CC */       \
 312   }
 313
 314 #define CALL_USED_REGISTERS                             \
 315   {                                                     \
 316     1, 1, 1, 1,   1, 1, 1, 1,   /* R0 - R7 */           \
 317     1, 1, 1, 1,   1, 1, 1, 1,   /* R8 - R15 */          \
 318     1, 1, 1, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 319     0, 0, 0, 0,   0, 1, 1, 1,   /* R24 - R30, SP */     \
 320     1, 1, 1, 1,   1, 1, 1, 1,   /* V0 - V7 */           \
 321     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 322     1, 1, 1, 1,   1, 1, 1, 1,   /* V16 - V23 */         \
 323     1, 1, 1, 1,   1, 1, 1, 1,   /* V24 - V31 */         \
 324     1, 1, 1,                    /* SFP, AP, CC */       \
 325   }
 326
 327 #define REGISTER_NAMES                                          \
 328   {                                                             \
 329     "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",      \
 330     "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",     \
 331     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",     \
 332     "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",      \
 333     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",      \
 334     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",     \
 335     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",     \
 336     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",     \
 337     "sfp", "ap",  "cc",                                         \
 338   }
 339
 340 /* Generate the register aliases for core register N */
 341 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
 342                      {"w" # N, R0_REGNUM + (N)}
 343
 344 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
 345                      {"d" # N, V0_REGNUM + (N)}, \
 346                      {"s" # N, V0_REGNUM + (N)}, \
 347                      {"h" # N, V0_REGNUM + (N)}, \
 348                      {"b" # N, V0_REGNUM + (N)}
 349
 350 /* Provide aliases for all of the ISA defined register name forms.
 351    These aliases are convenient for use in the clobber lists of inline
 352    asm statements.  */
 353
 354 #define ADDITIONAL_REGISTER_NAMES \
 355   { R_ALIASES(0),  R_ALIASES(1),  R_ALIASES(2),  R_ALIASES(3),  \
 356     R_ALIASES(4),  R_ALIASES(5),  R_ALIASES(6),  R_ALIASES(7),  \
 357     R_ALIASES(8),  R_ALIASES(9),  R_ALIASES(10), R_ALIASES(11), \
 358     R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
 359     R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
 360     R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
 361     R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
 362     R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
 363     V_ALIASES(0),  V_ALIASES(1),  V_ALIASES(2),  V_ALIASES(3),  \
 364     V_ALIASES(4),  V_ALIASES(5),  V_ALIASES(6),  V_ALIASES(7),  \
 365     V_ALIASES(8),  V_ALIASES(9),  V_ALIASES(10), V_ALIASES(11), \
 366     V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
 367     V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
 368     V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
 369     V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
 370     V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31)  \
 371   }
 372
 373 /* Say that the epilogue uses the return address register.  Note that
 374    in the case of sibcalls, the values "used by the epilogue" are
 375    considered live at the start of the called function.  */
 376
 377 #define EPILOGUE_USES(REGNO) \
 378   (epilogue_completed && (REGNO) == LR_REGNUM)
 379
 380 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 381    the stack pointer does not matter.  This is only true if the function
 382    uses alloca.  */
 383 #define EXIT_IGNORE_STACK       (cfun->calls_alloca)
 384
 385 #define STATIC_CHAIN_REGNUM             R18_REGNUM
 386 #define HARD_FRAME_POINTER_REGNUM       R29_REGNUM
 387 #define FRAME_POINTER_REGNUM            SFP_REGNUM
 388 #define STACK_POINTER_REGNUM            SP_REGNUM
 389 #define ARG_POINTER_REGNUM              AP_REGNUM
 390 #define FIRST_PSEUDO_REGISTER           67
 391
 392 /* The number of (integer) argument register available.  */
 393 #define NUM_ARG_REGS                    8
 394 #define NUM_FP_ARG_REGS                 8
 395
 396 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
 397    four members.  */
 398 #define HA_MAX_NUM_FLDS         4
 399
 400 /* External dwarf register number scheme.  These number are used to
 401    identify registers in dwarf debug information, the values are
 402    defined by the AArch64 ABI.  The numbering scheme is independent of
 403    GCC's internal register numbering scheme.  */
 404
 405 #define AARCH64_DWARF_R0        0
 406
 407 /* The number of R registers, note 31! not 32.  */
 408 #define AARCH64_DWARF_NUMBER_R 31
 409
 410 #define AARCH64_DWARF_SP       31
 411 #define AARCH64_DWARF_V0       64
 412
 413 /* The number of V registers.  */
 414 #define AARCH64_DWARF_NUMBER_V 32
 415
 416 /* For signal frames we need to use an alternative return column.  This
 417    value must not correspond to a hard register and must be out of the
 418    range of DWARF_FRAME_REGNUM().  */
 419 #define DWARF_ALT_FRAME_RETURN_COLUMN   \
 420   (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
 421
 422 /* We add 1 extra frame register for use as the
 423    DWARF_ALT_FRAME_RETURN_COLUMN.  */
 424 #define DWARF_FRAME_REGISTERS           (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
 425
 426
 427 #define DBX_REGISTER_NUMBER(REGNO)      aarch64_dbx_register_number (REGNO)
 428 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
 429    can use DWARF_ALT_FRAME_RETURN_COLUMN defined below.  This is just the same
 430    as the default definition in dwarf2out.c.  */
 431 #undef DWARF_FRAME_REGNUM
 432 #define DWARF_FRAME_REGNUM(REGNO)       DBX_REGISTER_NUMBER (REGNO)
 433
 434 #define DWARF_FRAME_RETURN_COLUMN       DWARF_FRAME_REGNUM (LR_REGNUM)
 435
 436 #define DWARF2_UNWIND_INFO 1
 437
 438 /* Use R0 through R3 to pass exception handling information.  */
 439 #define EH_RETURN_DATA_REGNO(N) \
 440   ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
 441
 442 /* Select a format to encode pointers in exception handling data.  */
 443 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
 444   aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
 445
 446 /* Output the assembly strings we want to add to a function definition.  */
 447 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)      \
 448   aarch64_declare_function_name (STR, NAME, DECL)
 449
 450 /* For EH returns X4 contains the stack adjustment.  */
 451 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, R4_REGNUM)
 452 #define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
 453
 454 /* Don't use __builtin_setjmp until we've defined it.  */
 455 #undef DONT_USE_BUILTIN_SETJMP
 456 #define DONT_USE_BUILTIN_SETJMP 1
 457
 458 /* Register in which the structure value is to be returned.  */
 459 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
 460
 461 /* Non-zero if REGNO is part of the Core register set.
 462
 463    The rather unusual way of expressing this check is to avoid
 464    warnings when building the compiler when R0_REGNUM is 0 and REGNO
 465    is unsigned.  */
 466 #define GP_REGNUM_P(REGNO)                                              \
 467   (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
 468
 469 #define FP_REGNUM_P(REGNO)                      \
 470   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
 471
 472 #define FP_LO_REGNUM_P(REGNO)            \
 473   (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
 474
 475 \f
 476 /* Register and constant classes.  */
 477
 478 enum reg_class
 479 {
 480   NO_REGS,
 481   CALLER_SAVE_REGS,
 482   GENERAL_REGS,
 483   STACK_REG,
 484   POINTER_REGS,
 485   FP_LO_REGS,
 486   FP_REGS,
 487   POINTER_AND_FP_REGS,
 488   ALL_REGS,
 489   LIM_REG_CLASSES               /* Last */
 490 };
 491
 492 #define N_REG_CLASSES   ((int) LIM_REG_CLASSES)
 493
 494 #define REG_CLASS_NAMES                         \
 495 {                                               \
 496   "NO_REGS",                                    \
 497   "CALLER_SAVE_REGS",                           \
 498   "GENERAL_REGS",                               \
 499   "STACK_REG",                                  \
 500   "POINTER_REGS",                               \
 501   "FP_LO_REGS",                                 \
 502   "FP_REGS",                                    \
 503   "POINTER_AND_FP_REGS",                        \
 504   "ALL_REGS"                                    \
 505 }
 506
 507 #define REG_CLASS_CONTENTS                                              \
 508 {                                                                       \
 509   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 510   { 0x0007ffff, 0x00000000, 0x00000000 },       /* CALLER_SAVE_REGS */  \
 511   { 0x7fffffff, 0x00000000, 0x00000003 },       /* GENERAL_REGS */      \
 512   { 0x80000000, 0x00000000, 0x00000000 },       /* STACK_REG */         \
 513   { 0xffffffff, 0x00000000, 0x00000003 },       /* POINTER_REGS */      \
 514   { 0x00000000, 0x0000ffff, 0x00000000 },       /* FP_LO_REGS  */       \
 515   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS  */          \
 516   { 0xffffffff, 0xffffffff, 0x00000003 },       /* POINTER_AND_FP_REGS */\
 517   { 0xffffffff, 0xffffffff, 0x00000007 }        /* ALL_REGS */          \
 518 }
 519
 520 #define REGNO_REG_CLASS(REGNO)  aarch64_regno_regclass (REGNO)
 521
 522 #define INDEX_REG_CLASS GENERAL_REGS
 523 #define BASE_REG_CLASS  POINTER_REGS
 524
 525 /* Register pairs used to eliminate unneeded registers that point into
 526    the stack frame.  */
 527 #define ELIMINABLE_REGS                                                 \
 528 {                                                                       \
 529   { ARG_POINTER_REGNUM,         STACK_POINTER_REGNUM            },      \
 530   { ARG_POINTER_REGNUM,         HARD_FRAME_POINTER_REGNUM       },      \
 531   { FRAME_POINTER_REGNUM,       STACK_POINTER_REGNUM            },      \
 532   { FRAME_POINTER_REGNUM,       HARD_FRAME_POINTER_REGNUM       },      \
 533 }
 534
 535 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 536   (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
 537
 538 /* CPU/ARCH option handling.  */
 539 #include "config/aarch64/aarch64-opts.h"
 540
 541 enum target_cpus
 542 {
 543 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
 544   TARGET_CPU_##INTERNAL_IDENT,
 545 #include "aarch64-cores.def"
 546   TARGET_CPU_generic
 547 };
 548
 549 /* If there is no CPU defined at configure, use generic as default.  */
 550 #ifndef TARGET_CPU_DEFAULT
 551 #define TARGET_CPU_DEFAULT \
 552   (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
 553 #endif
 554
 555 /* If inserting NOP before a mult-accumulate insn remember to adjust the
 556    length so that conditional branching code is updated appropriately.  */
 557 #define ADJUST_INSN_LENGTH(insn, length)        \
 558   do                                            \
 559     {                                           \
 560        if (aarch64_madd_needs_nop (insn))       \
 561          length += 4;                           \
 562     } while (0)
 563
 564 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)      \
 565     aarch64_final_prescan_insn (INSN);                  \
 566
 567 /* The processor for which instructions should be scheduled.  */
 568 extern enum aarch64_processor aarch64_tune;
 569
 570 /* RTL generation support.  */
 571 #define INIT_EXPANDERS aarch64_init_expanders ()
 572 \f
 573
 574 /* Stack layout; function entry, exit and calling.  */
 575 #define STACK_GROWS_DOWNWARD    1
 576
 577 #define FRAME_GROWS_DOWNWARD    1
 578
 579 #define ACCUMULATE_OUTGOING_ARGS        1
 580
 581 #define FIRST_PARM_OFFSET(FNDECL) 0
 582
 583 /* Fix for VFP */
 584 #define LIBCALL_VALUE(MODE)  \
 585   gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
 586
 587 #define DEFAULT_PCC_STRUCT_RETURN 0
 588
 589 #ifdef HAVE_POLY_INT_H
 590 struct GTY (()) aarch64_frame
 591 {
 592   HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
 593
 594   /* The number of extra stack bytes taken up by register varargs.
 595      This area is allocated by the callee at the very top of the
 596      frame.  This value is rounded up to a multiple of
 597      STACK_BOUNDARY.  */
 598   HOST_WIDE_INT saved_varargs_size;
 599
 600   /* The size of the saved callee-save int/FP registers.  */
 601
 602   HOST_WIDE_INT saved_regs_size;
 603
 604   /* Offset from the base of the frame (incomming SP) to the
 605      top of the locals area.  This value is always a multiple of
 606      STACK_BOUNDARY.  */
 607   poly_int64 locals_offset;
 608
 609   /* Offset from the base of the frame (incomming SP) to the
 610      hard_frame_pointer.  This value is always a multiple of
 611      STACK_BOUNDARY.  */
 612   poly_int64 hard_fp_offset;
 613
 614   /* The size of the frame.  This value is the offset from base of the
 615      frame (incomming SP) to the stack_pointer.  This value is always
 616      a multiple of STACK_BOUNDARY.  */
 617   poly_int64 frame_size;
 618
 619   /* The size of the initial stack adjustment before saving callee-saves.  */
 620   poly_int64 initial_adjust;
 621
 622   /* The writeback value when pushing callee-save registers.
 623      It is zero when no push is used.  */
 624   HOST_WIDE_INT callee_adjust;
 625
 626   /* The offset from SP to the callee-save registers after initial_adjust.
 627      It may be non-zero if no push is used (ie. callee_adjust == 0).  */
 628   poly_int64 callee_offset;
 629
 630   /* The size of the stack adjustment after saving callee-saves.  */
 631   poly_int64 final_adjust;
 632
 633   /* Store FP,LR and setup a frame pointer.  */
 634   bool emit_frame_chain;
 635
 636   unsigned wb_candidate1;
 637   unsigned wb_candidate2;
 638
 639   bool laid_out;
 640 };
 641
 642 typedef struct GTY (()) machine_function
 643 {
 644   struct aarch64_frame frame;
 645   /* One entry for each hard register.  */
 646   bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
 647 } machine_function;
 648 #endif
 649
 650 /* Which ABI to use.  */
 651 enum aarch64_abi_type
 652 {
 653   AARCH64_ABI_LP64 = 0,
 654   AARCH64_ABI_ILP32 = 1
 655 };
 656
 657 #ifndef AARCH64_ABI_DEFAULT
 658 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
 659 #endif
 660
 661 #define TARGET_ILP32    (aarch64_abi & AARCH64_ABI_ILP32)
 662
 663 enum arm_pcs
 664 {
 665   ARM_PCS_AAPCS64,              /* Base standard AAPCS for 64 bit.  */
 666   ARM_PCS_UNKNOWN
 667 };
 668
 669
 670
 671
 672 /* We can't use machine_mode inside a generator file because it
 673    hasn't been created yet; we shouldn't be using any code that
 674    needs the real definition though, so this ought to be safe.  */
 675 #ifdef GENERATOR_FILE
 676 #define MACHMODE int
 677 #else
 678 #include "insn-modes.h"
 679 #define MACHMODE machine_mode
 680 #endif
 681
 682 #ifndef USED_FOR_TARGET
 683 /* AAPCS related state tracking.  */
 684 typedef struct
 685 {
 686   enum arm_pcs pcs_variant;
 687   int aapcs_arg_processed;      /* No need to lay out this argument again.  */
 688   int aapcs_ncrn;               /* Next Core register number.  */
 689   int aapcs_nextncrn;           /* Next next core register number.  */
 690   int aapcs_nvrn;               /* Next Vector register number.  */
 691   int aapcs_nextnvrn;           /* Next Next Vector register number.  */
 692   rtx aapcs_reg;                /* Register assigned to this argument.  This
 693                                    is NULL_RTX if this parameter goes on
 694                                    the stack.  */
 695   MACHMODE aapcs_vfp_rmode;
 696   int aapcs_stack_words;        /* If the argument is passed on the stack, this
 697                                    is the number of words needed, after rounding
 698                                    up.  Only meaningful when
 699                                    aapcs_reg == NULL_RTX.  */
 700   int aapcs_stack_size;         /* The total size (in words, per 8 byte) of the
 701                                    stack arg area so far.  */
 702 } CUMULATIVE_ARGS;
 703 #endif
 704
 705 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
 706   (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
 707
 708 #define PAD_VARARGS_DOWN        0
 709
 710 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 711   aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
 712
 713 #define FUNCTION_ARG_REGNO_P(REGNO) \
 714   aarch64_function_arg_regno_p(REGNO)
 715 \f
 716
 717 /* ISA Features.  */
 718
 719 /* Addressing modes, etc.  */
 720 #define HAVE_POST_INCREMENT     1
 721 #define HAVE_PRE_INCREMENT      1
 722 #define HAVE_POST_DECREMENT     1
 723 #define HAVE_PRE_DECREMENT      1
 724 #define HAVE_POST_MODIFY_DISP   1
 725 #define HAVE_PRE_MODIFY_DISP    1
 726
 727 #define MAX_REGS_PER_ADDRESS    2
 728
 729 #define CONSTANT_ADDRESS_P(X)           aarch64_constant_address_p(X)
 730
 731 #define REGNO_OK_FOR_BASE_P(REGNO)      \
 732   aarch64_regno_ok_for_base_p (REGNO, true)
 733
 734 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 735   aarch64_regno_ok_for_index_p (REGNO, true)
 736
 737 #define LEGITIMATE_PIC_OPERAND_P(X) \
 738   aarch64_legitimate_pic_operand_p (X)
 739
 740 #define CASE_VECTOR_MODE Pmode
 741
 742 #define DEFAULT_SIGNED_CHAR 0
 743
 744 /* An integer expression for the size in bits of the largest integer machine
 745    mode that should actually be used.  We allow pairs of registers.  */
 746 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
 747
 748 /* Maximum bytes moved by a single instruction (load/store pair).  */
 749 #define MOVE_MAX (UNITS_PER_WORD * 2)
 750
 751 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
 752 #define AARCH64_CALL_RATIO 8
 753
 754 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
 755    move_by_pieces will continually copy the largest safe chunks.  So a
 756    7-byte copy is a 4-byte + 2-byte + byte copy.  This proves inefficient
 757    for both size and speed of copy, so we will instead use the "movmem"
 758    standard name to implement the copy.  This logic does not apply when
 759    targeting -mstrict-align, so keep a sensible default in that case.  */
 760 #define MOVE_RATIO(speed) \
 761   (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
 762
 763 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 764    of the length of a memset call, but use the default otherwise.  */
 765 #define CLEAR_RATIO(speed) \
 766   ((speed) ? 15 : AARCH64_CALL_RATIO)
 767
 768 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
 769    optimizing for size adjust the ratio to account for the overhead of loading
 770    the constant.  */
 771 #define SET_RATIO(speed) \
 772   ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
 773
 774 /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
 775    rarely a good idea in straight-line code since it adds an extra address
 776    dependency between each instruction.  Better to use incrementing offsets.  */
 777 #define USE_LOAD_POST_INCREMENT(MODE)   0
 778 #define USE_LOAD_POST_DECREMENT(MODE)   0
 779 #define USE_LOAD_PRE_INCREMENT(MODE)    0
 780 #define USE_LOAD_PRE_DECREMENT(MODE)    0
 781 #define USE_STORE_POST_INCREMENT(MODE)  0
 782 #define USE_STORE_POST_DECREMENT(MODE)  0
 783 #define USE_STORE_PRE_INCREMENT(MODE)   0
 784 #define USE_STORE_PRE_DECREMENT(MODE)   0
 785
 786 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
 787    The assigned word_mode is DImode but operations narrower than SImode
 788    behave as 32-bit operations if using the W-form of the registers rather
 789    than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
 790    expects.  */
 791 #define WORD_REGISTER_OPERATIONS 0
 792
 793 /* Define if loading from memory in MODE, an integral mode narrower than
 794    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
 795    macro should be the code that says which one of the two operations is
 796    implicitly done, or UNKNOWN if none.  */
 797 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 798
 799 /* Define this macro to be non-zero if instructions will fail to work
 800    if given data not on the nominal alignment.  */
 801 #define STRICT_ALIGNMENT                TARGET_STRICT_ALIGN
 802
 803 /* Define this macro to be non-zero if accessing less than a word of
 804    memory is no faster than accessing a word of memory, i.e., if such
 805    accesses require more than one instruction or if there is no
 806    difference in cost.
 807    Although there's no difference in instruction count or cycles,
 808    in AArch64 we don't want to expand to a sub-word to a 64-bit access
 809    if we don't have to, for power-saving reasons.  */
 810 #define SLOW_BYTE_ACCESS                0
 811
 812 #define NO_FUNCTION_CSE 1
 813
 814 /* Specify the machine mode that the hardware addresses have.
 815    After generation of rtl, the compiler makes no further distinction
 816    between pointers and any other objects of this machine mode.  */
 817 #define Pmode           DImode
 818
 819 /* A C expression whose value is zero if pointers that need to be extended
 820    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
 821    greater then zero if they are zero-extended and less then zero if the
 822    ptr_extend instruction should be used.  */
 823 #define POINTERS_EXTEND_UNSIGNED 1
 824
 825 /* Mode of a function address in a call instruction (for indexing purposes).  */
 826 #define FUNCTION_MODE   Pmode
 827
 828 #define SELECT_CC_MODE(OP, X, Y)        aarch64_select_cc_mode (OP, X, Y)
 829
 830 #define REVERSIBLE_CC_MODE(MODE) 1
 831
 832 #define REVERSE_CONDITION(CODE, MODE)           \
 833   (((MODE) == CCFPmode || (MODE) == CCFPEmode)  \
 834    ? reverse_condition_maybe_unordered (CODE)   \
 835    : reverse_condition (CODE))
 836
 837 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 838   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 839 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 840   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 841
 842 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 843
 844 #define RETURN_ADDR_RTX aarch64_return_addr
 845
 846 /* 3 insns + padding + 2 pointer-sized entries.  */
 847 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
 848
 849 /* Trampolines contain dwords, so must be dword aligned.  */
 850 #define TRAMPOLINE_ALIGNMENT 64
 851
 852 /* Put trampolines in the text section so that mapping symbols work
 853    correctly.  */
 854 #define TRAMPOLINE_SECTION text_section
 855
 856 /* To start with.  */
 857 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
 858   (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
 859 \f
 860
 861 /* Assembly output.  */
 862
 863 /* For now we'll make all jump tables pc-relative.  */
 864 #define CASE_VECTOR_PC_RELATIVE 1
 865
 866 #define CASE_VECTOR_SHORTEN_MODE(min, max, body)        \
 867   ((min < -0x1fff0 || max > 0x1fff0) ? SImode           \
 868    : (min < -0x1f0 || max > 0x1f0) ? HImode             \
 869    : QImode)
 870
 871 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL.  */
 872 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
 873
 874 #define MCOUNT_NAME "_mcount"
 875
 876 #define NO_PROFILE_COUNTERS 1
 877
 878 /* Emit rtl for profiling.  Output assembler code to FILE
 879    to call "_mcount" for profiling a function entry.  */
 880 #define PROFILE_HOOK(LABEL)                                             \
 881   {                                                                     \
 882     rtx fun, lr;                                                        \
 883     lr = get_hard_reg_initial_val (Pmode, LR_REGNUM);                   \
 884     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 885     emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode);           \
 886   }
 887
 888 /* All the work done in PROFILE_HOOK, but still required.  */
 889 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 890
 891 /* For some reason, the Linux headers think they know how to define
 892    these macros.  They don't!!!  */
 893 #undef ASM_APP_ON
 894 #undef ASM_APP_OFF
 895 #define ASM_APP_ON      "\t" ASM_COMMENT_START " Start of user assembly\n"
 896 #define ASM_APP_OFF     "\t" ASM_COMMENT_START " End of user assembly\n"
 897
 898 #define CONSTANT_POOL_BEFORE_FUNCTION 0
 899
 900 /* This definition should be relocated to aarch64-elf-raw.h.  This macro
 901    should be undefined in aarch64-linux.h and a clear_cache pattern
 902    implmented to emit either the call to __aarch64_sync_cache_range()
 903    directly or preferably the appropriate sycall or cache clear
 904    instructions inline.  */
 905 #define CLEAR_INSN_CACHE(beg, end)                              \
 906   extern void  __aarch64_sync_cache_range (void *, void *);     \
 907   __aarch64_sync_cache_range (beg, end)
 908
 909 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
 910
 911 /* Choose appropriate mode for caller saves, so we do the minimum
 912    required size of load/store.  */
 913 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 914   aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
 915
 916 #undef SWITCHABLE_TARGET
 917 #define SWITCHABLE_TARGET 1
 918
 919 /* Check TLS Descriptors mechanism is selected.  */
 920 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
 921
 922 extern enum aarch64_code_model aarch64_cmodel;
 923
 924 /* When using the tiny addressing model conditional and unconditional branches
 925    can span the whole of the available address space (1MB).  */
 926 #define HAS_LONG_COND_BRANCH                            \
 927   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 928    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 929
 930 #define HAS_LONG_UNCOND_BRANCH                          \
 931   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 932    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 933
 934 #define TARGET_SUPPORTS_WIDE_INT 1
 935
 936 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register.  */
 937 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
 938   ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
 939    || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
 940    || (MODE) == DFmode)
 941
 942 /* Modes valid for AdvSIMD Q registers.  */
 943 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
 944   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
 945    || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
 946    || (MODE) == V2DFmode)
 947
 948 #define ENDIAN_LANE_N(NUNITS, N) \
 949   (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N)
 950
 951 /* Support for a configure-time default CPU, etc.  We currently support
 952    --with-arch and --with-cpu.  Both are ignored if either is specified
 953    explicitly on the command line at run time.  */
 954 #define OPTION_DEFAULT_SPECS                            \
 955   {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" },  \
 956   {"cpu",  "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },
 957
 958 #define MCPU_TO_MARCH_SPEC \
 959    " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
 960
 961 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
 962 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
 963   { "rewrite_mcpu", aarch64_rewrite_mcpu },
 964
 965 #if defined(__aarch64__)
 966 extern const char *host_detect_local_cpu (int argc, const char **argv);
 967 # define EXTRA_SPEC_FUNCTIONS                                           \
 968   { "local_cpu_detect", host_detect_local_cpu },                        \
 969   MCPU_TO_MARCH_SPEC_FUNCTIONS
 970
 971 # define MCPU_MTUNE_NATIVE_SPECS                                        \
 972    " %{march=native:%<march=native %:local_cpu_detect(arch)}"           \
 973    " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}"              \
 974    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
 975 #else
 976 # define MCPU_MTUNE_NATIVE_SPECS ""
 977 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
 978 #endif
 979
 980 #define ASM_CPU_SPEC \
 981    MCPU_TO_MARCH_SPEC
 982
 983 #define EXTRA_SPECS                                             \
 984   { "asm_cpu_spec",             ASM_CPU_SPEC }
 985
 986 #define ASM_OUTPUT_POOL_EPILOGUE  aarch64_asm_output_pool_epilogue
 987
 988 /* This type is the user-visible __fp16, and a pointer to that type.  We
 989    need it in many places in the backend.  Defined in aarch64-builtins.c.  */
 990 extern tree aarch64_fp16_type_node;
 991 extern tree aarch64_fp16_ptr_type_node;
 992
 993 /* The generic unwind code in libgcc does not initialize the frame pointer.
 994    So in order to unwind a function using a frame pointer, the very first
 995    function that is unwound must save the frame pointer.  That way the frame
 996    pointer is restored and its value is now valid - otherwise _Unwind_GetGR
 997    crashes.  Libgcc can now be safely built with -fomit-frame-pointer.  */
 998 #define LIBGCC2_UNWIND_ATTRIBUTE \
 999   __attribute__((optimize ("no-omit-frame-pointer")))
1000
1001 #endif /* GCC_AARCH64_H */