1 ; Options for the RISC-V port of the compiler
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22 config/riscv/riscv-opts.h
25 Target RejectNegative Mask(BIG_ENDIAN)
26 Assume target CPU is configured as big endian.
29 Target RejectNegative InverseMask(BIG_ENDIAN)
30 Assume target CPU is configured as little endian.
33 Target RejectNegative Joined UInteger Var(riscv_branch_cost)
34 -mbranch-cost=N Set the cost of branches to roughly N instructions.
37 Target Var(TARGET_PLT) Init(1)
38 When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
41 Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) Negative(mabi=)
42 Specify integer and floating-point calling convention.
44 mpreferred-stack-boundary=
45 Target RejectNegative Joined UInteger Var(riscv_preferred_stack_boundary_arg)
46 Attempt to keep stack aligned to this power of 2.
49 Name(abi_type) Type(enum riscv_abi_type)
50 Supported ABIs (for use with the -mabi= option):
53 Enum(abi_type) String(ilp32) Value(ABI_ILP32)
56 Enum(abi_type) String(ilp32e) Value(ABI_ILP32E)
59 Enum(abi_type) String(ilp32f) Value(ABI_ILP32F)
62 Enum(abi_type) String(ilp32d) Value(ABI_ILP32D)
65 Enum(abi_type) String(lp64) Value(ABI_LP64)
68 Enum(abi_type) String(lp64e) Value(ABI_LP64E)
71 Enum(abi_type) String(lp64f) Value(ABI_LP64F)
74 Enum(abi_type) String(lp64d) Value(ABI_LP64D)
78 Use hardware floating-point divide and square root instructions.
82 Use hardware instructions for integer division.
85 Target RejectNegative Joined Negative(march=)
86 -march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be
90 Target RejectNegative Joined Var(riscv_tune_string) Save
91 -mtune=PROCESSOR Optimize the output for PROCESSOR.
94 Target RejectNegative Joined Var(riscv_cpu_string) Save
95 -mcpu=PROCESSOR Use architecture of and optimize the output for PROCESSOR.
98 Target Joined UInteger Var(g_switch_value) Init(8)
99 -msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets).
102 Target Mask(SAVE_RESTORE)
103 Use smaller but slower prologue and epilogue code.
106 Target Bool Var(riscv_mshorten_memrefs) Init(1)
107 Convert BASE + LARGE_OFFSET addresses to NEW_BASE + SMALL_OFFSET to allow more
108 memory accesses to be generated as compressed instructions. Currently targets
109 32-bit integer load/stores.
112 Target RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL) Save
113 Specify the code model.
116 Target Mask(STRICT_ALIGN) Save
117 Do not generate unaligned memory accesses.
120 Name(code_model) Type(enum riscv_code_model)
121 Known code models (for use with the -mcmodel= option):
124 Enum(code_model) String(medlow) Value(CM_MEDLOW)
127 Enum(code_model) String(medany) Value(CM_MEDANY)
130 Enum(code_model) String(large) Value(CM_LARGE)
133 Target Mask(EXPLICIT_RELOCS)
134 Use %reloc() operators, rather than assembly macros, to load addresses.
137 Target Bool Var(riscv_mrelax) Init(1)
138 Take advantage of linker relaxations to reduce the number of instructions
139 required to materialize symbol addresses.
142 Target Bool Var(riscv_mcsr_check) Init(0)
143 Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
144 The ISA-dependent CSR are only valid when the specific ISA is set. The
145 read-only CSR can not be written by the CSR instructions.
147 momit-leaf-frame-pointer
148 Target Mask(OMIT_LEAF_FRAME_POINTER) Save
149 Omit the frame pointer in leaf functions.
170 Target Var(riscv_emit_attribute_p) Init(-1)
171 Emit RISC-V ELF attribute.
174 Target RejectNegative Joined Var(riscv_align_data_type) Enum(riscv_align_data) Init(riscv_align_data_type_xlen)
175 Use the given data alignment.
178 Name(riscv_align_data) Type(enum riscv_align_data)
179 Known data alignment choices (for use with the -malign-data= option):
182 Enum(riscv_align_data) String(xlen) Value(riscv_align_data_type_xlen)
185 Enum(riscv_align_data) String(natural) Value(riscv_align_data_type_natural)
187 mstack-protector-guard=
188 Target RejectNegative Joined Enum(stack_protector_guard) Var(riscv_stack_protector_guard) Init(SSP_GLOBAL)
189 Use given stack-protector guard.
192 Name(stack_protector_guard) Type(enum stack_protector_guard)
193 Valid arguments to -mstack-protector-guard=:
196 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
199 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
201 mstack-protector-guard-reg=
202 Target RejectNegative Joined Var(riscv_stack_protector_guard_reg_str)
203 Use the given base register for addressing the stack-protector guard.
206 int riscv_stack_protector_guard_reg = 0
208 mstack-protector-guard-offset=
209 Target RejectNegative Joined Integer Var(riscv_stack_protector_guard_offset_str)
210 Use the given offset for addressing the stack-protector guard.
213 long riscv_stack_protector_guard_offset = 0
218 Mask(ZICSR) Var(riscv_zi_subext)
220 Mask(ZIFENCEI) Var(riscv_zi_subext)
222 Mask(ZIHINTNTL) Var(riscv_zi_subext)
224 Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
226 Mask(ZICOND) Var(riscv_zi_subext)
231 Mask(ZAWRS) Var(riscv_za_subext)
236 Mask(ZBA) Var(riscv_zb_subext)
238 Mask(ZBB) Var(riscv_zb_subext)
240 Mask(ZBC) Var(riscv_zb_subext)
242 Mask(ZBS) Var(riscv_zb_subext)
245 int riscv_zinx_subext
247 Mask(ZFINX) Var(riscv_zinx_subext)
249 Mask(ZDINX) Var(riscv_zinx_subext)
251 Mask(ZHINX) Var(riscv_zinx_subext)
253 Mask(ZHINXMIN) Var(riscv_zinx_subext)
258 Mask(ZBKB) Var(riscv_zk_subext)
260 Mask(ZBKC) Var(riscv_zk_subext)
262 Mask(ZBKX) Var(riscv_zk_subext)
264 Mask(ZKNE) Var(riscv_zk_subext)
266 Mask(ZKND) Var(riscv_zk_subext)
268 Mask(ZKNH) Var(riscv_zk_subext)
270 Mask(ZKR) Var(riscv_zk_subext)
272 Mask(ZKSED) Var(riscv_zk_subext)
274 Mask(ZKSH) Var(riscv_zk_subext)
276 Mask(ZKT) Var(riscv_zk_subext)
279 int riscv_vector_elen_flags
281 Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags)
283 Mask(VECTOR_ELEN_64) Var(riscv_vector_elen_flags)
285 Mask(VECTOR_ELEN_FP_32) Var(riscv_vector_elen_flags)
287 Mask(VECTOR_ELEN_FP_64) Var(riscv_vector_elen_flags)
289 Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags)
291 Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags)
296 Mask(ZVL32B) Var(riscv_zvl_flags)
298 Mask(ZVL64B) Var(riscv_zvl_flags)
300 Mask(ZVL128B) Var(riscv_zvl_flags)
302 Mask(ZVL256B) Var(riscv_zvl_flags)
304 Mask(ZVL512B) Var(riscv_zvl_flags)
306 Mask(ZVL1024B) Var(riscv_zvl_flags)
308 Mask(ZVL2048B) Var(riscv_zvl_flags)
310 Mask(ZVL4096B) Var(riscv_zvl_flags)
312 Mask(ZVL8192B) Var(riscv_zvl_flags)
314 Mask(ZVL16384B) Var(riscv_zvl_flags)
316 Mask(ZVL32768B) Var(riscv_zvl_flags)
318 Mask(ZVL65536B) Var(riscv_zvl_flags)
323 Mask(ZVBB) Var(riscv_zvb_subext)
325 Mask(ZVBC) Var(riscv_zvb_subext)
327 Mask(ZVKB) Var(riscv_zvb_subext)
332 Mask(ZVKG) Var(riscv_zvk_subext)
334 Mask(ZVKNED) Var(riscv_zvk_subext)
336 Mask(ZVKNHA) Var(riscv_zvk_subext)
338 Mask(ZVKNHB) Var(riscv_zvk_subext)
340 Mask(ZVKSED) Var(riscv_zvk_subext)
342 Mask(ZVKSH) Var(riscv_zvk_subext)
344 Mask(ZVKN) Var(riscv_zvk_subext)
346 Mask(ZVKNC) Var(riscv_zvk_subext)
348 Mask(ZVKNG) Var(riscv_zvk_subext)
350 Mask(ZVKS) Var(riscv_zvk_subext)
352 Mask(ZVKSC) Var(riscv_zvk_subext)
354 Mask(ZVKSG) Var(riscv_zvk_subext)
356 Mask(ZVKT) Var(riscv_zvk_subext)
359 int riscv_zicmo_subext
361 Mask(ZICBOZ) Var(riscv_zicmo_subext)
363 Mask(ZICBOM) Var(riscv_zicmo_subext)
365 Mask(ZICBOP) Var(riscv_zicmo_subext)
370 Mask(ZFHMIN) Var(riscv_zf_subext)
372 Mask(ZFH) Var(riscv_zf_subext)
374 Mask(ZVFBFMIN) Var(riscv_zf_subext)
376 Mask(ZVFHMIN) Var(riscv_zf_subext)
378 Mask(ZVFH) Var(riscv_zf_subext)
383 Mask(ZFA) Var(riscv_zfa_subext)
388 Mask(ZMMUL) Var(riscv_zm_subext)
393 Mask(ZCA) Var(riscv_zc_subext)
395 Mask(ZCB) Var(riscv_zc_subext)
397 Mask(ZCE) Var(riscv_zc_subext)
399 Mask(ZCF) Var(riscv_zc_subext)
401 Mask(ZCD) Var(riscv_zc_subext)
403 Mask(ZCMP) Var(riscv_zc_subext)
405 Mask(ZCMT) Var(riscv_zc_subext)
410 Mask(SVINVAL) Var(riscv_sv_subext)
412 Mask(SVNAPOT) Var(riscv_sv_subext)
415 int riscv_ztso_subext
417 Mask(ZTSO) Var(riscv_ztso_subext)
422 Mask(XCVMAC) Var(riscv_xcv_subext)
424 Mask(XCVALU) Var(riscv_xcv_subext)
426 Mask(XCVELW) Var(riscv_xcv_subext)
429 int riscv_xthead_subext
431 Mask(XTHEADBA) Var(riscv_xthead_subext)
433 Mask(XTHEADBB) Var(riscv_xthead_subext)
435 Mask(XTHEADBS) Var(riscv_xthead_subext)
437 Mask(XTHEADCMO) Var(riscv_xthead_subext)
439 Mask(XTHEADCONDMOV) Var(riscv_xthead_subext)
441 Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext)
443 Mask(XTHEADFMV) Var(riscv_xthead_subext)
445 Mask(XTHEADINT) Var(riscv_xthead_subext)
447 Mask(XTHEADMAC) Var(riscv_xthead_subext)
449 Mask(XTHEADMEMIDX) Var(riscv_xthead_subext)
451 Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
453 Mask(XTHEADSYNC) Var(riscv_xthead_subext)
456 int riscv_xventana_subext
458 Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
461 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
462 Supported ISA specs (for use with the -misa-spec= option):
465 Enum(isa_spec_class) String(2.2) Value(ISA_SPEC_CLASS_2P2)
468 Enum(isa_spec_class) String(20190608) Value(ISA_SPEC_CLASS_20190608)
471 Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213)
474 Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC)
475 Set the version of RISC-V ISA spec.
478 Target Var(TARGET_MOVCC)
479 Enable conditional moves unconditionally.
482 Target Var(TARGET_INLINE_SUBWORD_ATOMIC) Init(1)
483 Always inline subword atomic operations.
486 Target Bool Var(riscv_inline_strcmp) Init(0)
487 Inline strcmp calls if possible.
490 Target Bool Var(riscv_inline_strncmp) Init(0)
491 Inline strncmp calls if possible.
494 Target Bool Var(riscv_inline_strlen) Init(0)
495 Inline strlen calls if possible.
497 -param=riscv-strcmp-inline-limit=
498 Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64)
499 Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64).
502 Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)
503 Valid arguments to -param=riscv-autovec-preference=:
506 Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)
509 Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)
512 Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)
514 -param=riscv-autovec-preference=
515 Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(RVV_SCALABLE)
516 -param=riscv-autovec-preference=<string> Set the preference of auto-vectorization in the RISC-V port.
519 Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum)
520 The RVV possible LMUL (-param=riscv-autovec-lmul=):
523 Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1)
526 Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2)
529 Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4)
532 Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8)
535 Enum(riscv_autovec_lmul) String(dynamic) Value(RVV_DYNAMIC)
537 -param=riscv-autovec-lmul=
538 Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) Init(RVV_M1)
539 -param=riscv-autovec-lmul=<string> Set the RVV LMUL of auto-vectorization in the RISC-V port.
542 Target Var(TARGET_ADJUST_LMUL_COST) Init(0)
544 -param=riscv-vector-abi
545 Target Undocumented Bool Var(riscv_vector_abi) Init(0)
546 Enable the use of vector registers for function arguments and return value.
547 This is an experimental switch and may be subject to change in the future.
550 Name(stringop_strategy) Type(enum stringop_strategy_enum)
551 Valid arguments to -mstringop-strategy=:
554 Enum(stringop_strategy) String(auto) Value(STRATEGY_AUTO)
557 Enum(stringop_strategy) String(libcall) Value(STRATEGY_LIBCALL)
560 Enum(stringop_strategy) String(scalar) Value(STRATEGY_SCALAR)
563 Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
566 Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
567 Specify stringop expansion strategy.