1 /* List of supported core and tune info for RISC
-V.
2 Copyright (C
) 2020-2024 Free Software Foundation
, Inc.
4 This file is part of GCC.
6 GCC is free software
; you can redistribute it and
/or modify it
7 under the terms of the GNU General Public License as published by
8 the Free Software Foundation
; either version
3, or (at your option
)
11 GCC is distributed in the hope that it will be useful
, but
12 WITHOUT ANY WARRANTY
; without even the implied warranty of
13 MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC
; see the file COPYING3. If not see
18 <http
://www.gnu.org
/licenses
/>.
*/
20 /* This is a list of tune that implement RISC
-V.
22 Before using #include to read this file
, define a macro
:
24 RISCV_TUNE(TUNE_NAME
, PIPELINE_MODEL
, TUNE_INFO
)
26 The TUNE_NAME is the name of the micro
-arch
, represented as a string.
27 The PIPELINE_MODEL is the pipeline model of the micro
-arch
, represented as a
28 string
, defined in riscv.md.
29 The TUNE_INFO is the detail cost model for this core
, represented as an
30 identifier
, reference to riscv.cc.
*/
33 #define
RISCV_TUNE(TUNE_NAME
, PIPELINE_MODEL
, TUNE_INFO
)
36 RISCV_TUNE("rocket", generic
, rocket_tune_info
)
37 RISCV_TUNE("sifive-3-series", generic
, rocket_tune_info
)
38 RISCV_TUNE("sifive-5-series", generic
, rocket_tune_info
)
39 RISCV_TUNE("sifive-7-series", sifive_7
, sifive_7_tune_info
)
40 RISCV_TUNE("thead-c906", generic
, thead_c906_tune_info
)
41 RISCV_TUNE("generic-ooo", generic_ooo
, generic_ooo_tune_info
)
42 RISCV_TUNE("size", generic
, optimize_size_tune_info
)
46 /* This is a list of cores that implement RISC
-V.
48 Before using #include to read this file
, define a macro
:
50 RISCV_CORE(CORE_NAME
, ARCH
, MICRO_ARCH
)
52 The CORE_NAME is the name of the core
, represented as a string.
53 The ARCH is the default arch of the core
, represented as a string
,
54 can be NULL if no default arch.
55 The MICRO_ARCH is the name of the core for which scheduling decisions
56 will be made
, represented as an identifier.
*/
59 #define
RISCV_CORE(CORE_NAME
, ARCH
, MICRO_ARCH
)
62 RISCV_CORE("sifive-e20", "rv32imc", "rocket")
63 RISCV_CORE("sifive-e21", "rv32imac", "rocket")
64 RISCV_CORE("sifive-e24", "rv32imafc", "rocket")
65 RISCV_CORE("sifive-e31", "rv32imac", "sifive-3-series")
66 RISCV_CORE("sifive-e34", "rv32imafc", "sifive-3-series")
67 RISCV_CORE("sifive-e76", "rv32imafc", "sifive-7-series")
69 RISCV_CORE("sifive-s21", "rv64imac", "rocket")
70 RISCV_CORE("sifive-s51", "rv64imac", "sifive-5-series")
71 RISCV_CORE("sifive-s54", "rv64imafdc", "sifive-5-series")
72 RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series")
74 RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
75 RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
76 RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series")
78 RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
79 "xtheadcondmov_xtheadfmemidx_xtheadmac_"
80 "xtheadmemidx_xtheadmempair_xtheadsync",