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* pretty-print.c (pp_base_maybe_space): New function.
[official-gcc.git] / gcc / longlong.h
blob0f5d05ffe2d357df2d546b96670bd4839e2043f3
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2004
3 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 2, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
19
20 /* You have to define the following before including this file:
21
22 UWtype -- An unsigned type, default type for operations (typically a "word")
23 UHWtype -- An unsigned type, at least half the size of UWtype.
24 UDWtype -- An unsigned type, at least twice as large a UWtype
25 W_TYPE_SIZE -- size in bits of UWtype
26
27 UQItype -- Unsigned 8 bit type.
28 SItype, USItype -- Signed and unsigned 32 bit types.
29 DItype, UDItype -- Signed and unsigned 64 bit types.
30
31 On a 32 bit machine UWtype should typically be USItype;
32 on a 64 bit machine, UWtype should typically be UDItype.
33 */
34
35 #define __BITS4 (W_TYPE_SIZE / 4)
36 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
37 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
38 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
39
40 #ifndef W_TYPE_SIZE
41 #define W_TYPE_SIZE 32
42 #define UWtype USItype
43 #define UHWtype USItype
44 #define UDWtype UDItype
45 #endif
46
47 /* Define auxiliary asm macros.
48
49 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
50 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
52
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
55
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
63
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
66 is rounded towards 0.
67
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first nonzero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
72
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
75
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
81
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
87 and is lost.
88
89 If any of these macros are left undefined for a particular CPU,
90 C macros are used. */
91
92 /* The CPUs come in alphabetical order below.
93
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below!
96 (E.g. WE32100, IBM360.) */
97
98 #if defined (__GNUC__) && !defined (NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 #if defined (__alpha) && W_TYPE_SIZE == 64
111 #define umul_ppmm(ph, pl, m0, m1) \
112 do { \
113 UDItype __m0 = (m0), __m1 = (m1); \
114 (ph) = __builtin_alpha_umulh (__m0, __m1); \
115 (pl) = __m0 * __m1; \
116 } while (0)
117 #define UMUL_TIME 46
118 #ifndef LONGLONG_STANDALONE
119 #define udiv_qrnnd(q, r, n1, n0, d) \
120 do { UDItype __r; \
121 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
122 (r) = __r; \
123 } while (0)
124 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
125 #define UDIV_TIME 220
126 #endif /* LONGLONG_STANDALONE */
127 #ifdef __alpha_cix__
128 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
129 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
130 #define COUNT_LEADING_ZEROS_0 64
131 #else
132 extern const UQItype __clz_tab[] ATTRIBUTE_HIDDEN;
133 #define count_leading_zeros(COUNT,X) \
134 do { \
135 UDItype __xr = (X), __t, __a; \
136 __t = __builtin_alpha_cmpbge (0, __xr); \
137 __a = __clz_tab[__t ^ 0xff] - 1; \
138 __t = __builtin_alpha_extbl (__xr, __a); \
139 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
140 } while (0)
141 #define count_trailing_zeros(COUNT,X) \
142 do { \
143 UDItype __xr = (X), __t, __a; \
144 __t = __builtin_alpha_cmpbge (0, __xr); \
145 __t = ~__t & -~__t; \
146 __a = ((__t & 0xCC) != 0) * 2; \
147 __a += ((__t & 0xF0) != 0) * 4; \
148 __a += ((__t & 0xAA) != 0); \
149 __t = __builtin_alpha_extbl (__xr, __a); \
150 __a <<= 3; \
151 __t &= -__t; \
152 __a += ((__t & 0xCC) != 0) * 2; \
153 __a += ((__t & 0xF0) != 0) * 4; \
154 __a += ((__t & 0xAA) != 0); \
155 (COUNT) = __a; \
156 } while (0)
157 #endif /* __alpha_cix__ */
158 #endif /* __alpha */
159
160 #if defined (__arc__) && W_TYPE_SIZE == 32
161 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
162 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
163 : "=r" ((USItype) (sh)), \
164 "=&r" ((USItype) (sl)) \
165 : "%r" ((USItype) (ah)), \
166 "rIJ" ((USItype) (bh)), \
167 "%r" ((USItype) (al)), \
168 "rIJ" ((USItype) (bl)))
169 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
170 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
171 : "=r" ((USItype) (sh)), \
172 "=&r" ((USItype) (sl)) \
173 : "r" ((USItype) (ah)), \
174 "rIJ" ((USItype) (bh)), \
175 "r" ((USItype) (al)), \
176 "rIJ" ((USItype) (bl)))
177 /* Call libgcc routine. */
178 #define umul_ppmm(w1, w0, u, v) \
179 do { \
180 DWunion __w; \
181 __w.ll = __umulsidi3 (u, v); \
182 w1 = __w.s.high; \
183 w0 = __w.s.low; \
184 } while (0)
185 #define __umulsidi3 __umulsidi3
186 UDItype __umulsidi3 (USItype, USItype);
187 #endif
188
189 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
190 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
191 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
192 : "=r" ((USItype) (sh)), \
193 "=&r" ((USItype) (sl)) \
194 : "%r" ((USItype) (ah)), \
195 "rI" ((USItype) (bh)), \
196 "%r" ((USItype) (al)), \
197 "rI" ((USItype) (bl)))
198 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
199 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
200 : "=r" ((USItype) (sh)), \
201 "=&r" ((USItype) (sl)) \
202 : "r" ((USItype) (ah)), \
203 "rI" ((USItype) (bh)), \
204 "r" ((USItype) (al)), \
205 "rI" ((USItype) (bl)))
206 #define umul_ppmm(xh, xl, a, b) \
207 {register USItype __t0, __t1, __t2; \
208 __asm__ ("%@ Inlined umul_ppmm\n" \
209 " mov %2, %5, lsr #16\n" \
210 " mov %0, %6, lsr #16\n" \
211 " bic %3, %5, %2, lsl #16\n" \
212 " bic %4, %6, %0, lsl #16\n" \
213 " mul %1, %3, %4\n" \
214 " mul %4, %2, %4\n" \
215 " mul %3, %0, %3\n" \
216 " mul %0, %2, %0\n" \
217 " adds %3, %4, %3\n" \
218 " addcs %0, %0, #65536\n" \
219 " adds %1, %1, %3, lsl #16\n" \
220 " adc %0, %0, %3, lsr #16" \
221 : "=&r" ((USItype) (xh)), \
222 "=r" ((USItype) (xl)), \
223 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
224 : "r" ((USItype) (a)), \
225 "r" ((USItype) (b)));}
226 #define UMUL_TIME 20
227 #define UDIV_TIME 100
228 #endif /* __arm__ */
229
230 #if defined (__hppa) && W_TYPE_SIZE == 32
231 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
232 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
233 : "=r" ((USItype) (sh)), \
234 "=&r" ((USItype) (sl)) \
235 : "%rM" ((USItype) (ah)), \
236 "rM" ((USItype) (bh)), \
237 "%rM" ((USItype) (al)), \
238 "rM" ((USItype) (bl)))
239 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
240 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
241 : "=r" ((USItype) (sh)), \
242 "=&r" ((USItype) (sl)) \
243 : "rM" ((USItype) (ah)), \
244 "rM" ((USItype) (bh)), \
245 "rM" ((USItype) (al)), \
246 "rM" ((USItype) (bl)))
247 #if defined (_PA_RISC1_1)
248 #define umul_ppmm(w1, w0, u, v) \
249 do { \
250 union \
251 { \
252 UDItype __f; \
253 struct {USItype __w1, __w0;} __w1w0; \
254 } __t; \
255 __asm__ ("xmpyu %1,%2,%0" \
256 : "=x" (__t.__f) \
257 : "x" ((USItype) (u)), \
258 "x" ((USItype) (v))); \
259 (w1) = __t.__w1w0.__w1; \
260 (w0) = __t.__w1w0.__w0; \
261 } while (0)
262 #define UMUL_TIME 8
263 #else
264 #define UMUL_TIME 30
265 #endif
266 #define UDIV_TIME 40
267 #define count_leading_zeros(count, x) \
268 do { \
269 USItype __tmp; \
270 __asm__ ( \
271 "ldi 1,%0\n" \
272 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
273 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
274 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
275 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
276 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
277 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
278 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
279 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
280 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
281 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
282 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
283 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
284 " extru %1,30,1,%1 ; Extract bit 1.\n" \
285 " sub %0,%1,%0 ; Subtract it.\n" \
286 : "=r" (count), "=r" (__tmp) : "1" (x)); \
287 } while (0)
288 #endif
289
290 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
291 #define smul_ppmm(xh, xl, m0, m1) \
292 do { \
293 union {DItype __ll; \
294 struct {USItype __h, __l;} __i; \
295 } __x; \
296 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
297 : "=&r" (__x.__ll) \
298 : "r" (m0), "r" (m1)); \
299 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
300 } while (0)
301 #define sdiv_qrnnd(q, r, n1, n0, d) \
302 do { \
303 union {DItype __ll; \
304 struct {USItype __h, __l;} __i; \
305 } __x; \
306 __x.__i.__h = n1; __x.__i.__l = n0; \
307 __asm__ ("dr %0,%2" \
308 : "=r" (__x.__ll) \
309 : "0" (__x.__ll), "r" (d)); \
310 (q) = __x.__i.__l; (r) = __x.__i.__h; \
311 } while (0)
312 #endif
313
314 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
315 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
316 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
317 : "=r" ((USItype) (sh)), \
318 "=&r" ((USItype) (sl)) \
319 : "%0" ((USItype) (ah)), \
320 "g" ((USItype) (bh)), \
321 "%1" ((USItype) (al)), \
322 "g" ((USItype) (bl)))
323 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
324 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
325 : "=r" ((USItype) (sh)), \
326 "=&r" ((USItype) (sl)) \
327 : "0" ((USItype) (ah)), \
328 "g" ((USItype) (bh)), \
329 "1" ((USItype) (al)), \
330 "g" ((USItype) (bl)))
331 #define umul_ppmm(w1, w0, u, v) \
332 __asm__ ("mull %3" \
333 : "=a" ((USItype) (w0)), \
334 "=d" ((USItype) (w1)) \
335 : "%0" ((USItype) (u)), \
336 "rm" ((USItype) (v)))
337 #define udiv_qrnnd(q, r, n1, n0, dv) \
338 __asm__ ("divl %4" \
339 : "=a" ((USItype) (q)), \
340 "=d" ((USItype) (r)) \
341 : "0" ((USItype) (n0)), \
342 "1" ((USItype) (n1)), \
343 "rm" ((USItype) (dv)))
344 #define count_leading_zeros(count, x) \
345 do { \
346 USItype __cbtmp; \
347 __asm__ ("bsrl %1,%0" \
348 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
349 (count) = __cbtmp ^ 31; \
350 } while (0)
351 #define count_trailing_zeros(count, x) \
352 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
353 #define UMUL_TIME 40
354 #define UDIV_TIME 40
355 #endif /* 80x86 */
356
357 #if defined (__i960__) && W_TYPE_SIZE == 32
358 #define umul_ppmm(w1, w0, u, v) \
359 ({union {UDItype __ll; \
360 struct {USItype __l, __h;} __i; \
361 } __xx; \
362 __asm__ ("emul %2,%1,%0" \
363 : "=d" (__xx.__ll) \
364 : "%dI" ((USItype) (u)), \
365 "dI" ((USItype) (v))); \
366 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
367 #define __umulsidi3(u, v) \
368 ({UDItype __w; \
369 __asm__ ("emul %2,%1,%0" \
370 : "=d" (__w) \
371 : "%dI" ((USItype) (u)), \
372 "dI" ((USItype) (v))); \
373 __w; })
374 #endif /* __i960__ */
375
376 #if defined (__M32R__) && W_TYPE_SIZE == 32
377 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
378 /* The cmp clears the condition bit. */ \
379 __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0" \
380 : "=r" ((USItype) (sh)), \
381 "=&r" ((USItype) (sl)) \
382 : "%0" ((USItype) (ah)), \
383 "r" ((USItype) (bh)), \
384 "%1" ((USItype) (al)), \
385 "r" ((USItype) (bl)) \
386 : "cbit")
387 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
388 /* The cmp clears the condition bit. */ \
389 __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0" \
390 : "=r" ((USItype) (sh)), \
391 "=&r" ((USItype) (sl)) \
392 : "0" ((USItype) (ah)), \
393 "r" ((USItype) (bh)), \
394 "1" ((USItype) (al)), \
395 "r" ((USItype) (bl)) \
396 : "cbit")
397 #endif /* __M32R__ */
398
399 #if defined (__mc68000__) && W_TYPE_SIZE == 32
400 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
401 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
402 : "=d" ((USItype) (sh)), \
403 "=&d" ((USItype) (sl)) \
404 : "%0" ((USItype) (ah)), \
405 "d" ((USItype) (bh)), \
406 "%1" ((USItype) (al)), \
407 "g" ((USItype) (bl)))
408 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
409 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
410 : "=d" ((USItype) (sh)), \
411 "=&d" ((USItype) (sl)) \
412 : "0" ((USItype) (ah)), \
413 "d" ((USItype) (bh)), \
414 "1" ((USItype) (al)), \
415 "g" ((USItype) (bl)))
416
417 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
418 #if (defined (__mc68020__) && !defined (__mc68060__))
419 #define umul_ppmm(w1, w0, u, v) \
420 __asm__ ("mulu%.l %3,%1:%0" \
421 : "=d" ((USItype) (w0)), \
422 "=d" ((USItype) (w1)) \
423 : "%0" ((USItype) (u)), \
424 "dmi" ((USItype) (v)))
425 #define UMUL_TIME 45
426 #define udiv_qrnnd(q, r, n1, n0, d) \
427 __asm__ ("divu%.l %4,%1:%0" \
428 : "=d" ((USItype) (q)), \
429 "=d" ((USItype) (r)) \
430 : "0" ((USItype) (n0)), \
431 "1" ((USItype) (n1)), \
432 "dmi" ((USItype) (d)))
433 #define UDIV_TIME 90
434 #define sdiv_qrnnd(q, r, n1, n0, d) \
435 __asm__ ("divs%.l %4,%1:%0" \
436 : "=d" ((USItype) (q)), \
437 "=d" ((USItype) (r)) \
438 : "0" ((USItype) (n0)), \
439 "1" ((USItype) (n1)), \
440 "dmi" ((USItype) (d)))
441
442 #elif defined (__mcoldfire__) /* not mc68020 */
443
444 #define umul_ppmm(xh, xl, a, b) \
445 __asm__ ("| Inlined umul_ppmm\n" \
446 " move%.l %2,%/d0\n" \
447 " move%.l %3,%/d1\n" \
448 " move%.l %/d0,%/d2\n" \
449 " swap %/d0\n" \
450 " move%.l %/d1,%/d3\n" \
451 " swap %/d1\n" \
452 " move%.w %/d2,%/d4\n" \
453 " mulu %/d3,%/d4\n" \
454 " mulu %/d1,%/d2\n" \
455 " mulu %/d0,%/d3\n" \
456 " mulu %/d0,%/d1\n" \
457 " move%.l %/d4,%/d0\n" \
458 " clr%.w %/d0\n" \
459 " swap %/d0\n" \
460 " add%.l %/d0,%/d2\n" \
461 " add%.l %/d3,%/d2\n" \
462 " jcc 1f\n" \
463 " add%.l %#65536,%/d1\n" \
464 "1: swap %/d2\n" \
465 " moveq %#0,%/d0\n" \
466 " move%.w %/d2,%/d0\n" \
467 " move%.w %/d4,%/d2\n" \
468 " move%.l %/d2,%1\n" \
469 " add%.l %/d1,%/d0\n" \
470 " move%.l %/d0,%0" \
471 : "=g" ((USItype) (xh)), \
472 "=g" ((USItype) (xl)) \
473 : "g" ((USItype) (a)), \
474 "g" ((USItype) (b)) \
475 : "d0", "d1", "d2", "d3", "d4")
476 #define UMUL_TIME 100
477 #define UDIV_TIME 400
478 #else /* not ColdFire */
479 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
480 #define umul_ppmm(xh, xl, a, b) \
481 __asm__ ("| Inlined umul_ppmm\n" \
482 " move%.l %2,%/d0\n" \
483 " move%.l %3,%/d1\n" \
484 " move%.l %/d0,%/d2\n" \
485 " swap %/d0\n" \
486 " move%.l %/d1,%/d3\n" \
487 " swap %/d1\n" \
488 " move%.w %/d2,%/d4\n" \
489 " mulu %/d3,%/d4\n" \
490 " mulu %/d1,%/d2\n" \
491 " mulu %/d0,%/d3\n" \
492 " mulu %/d0,%/d1\n" \
493 " move%.l %/d4,%/d0\n" \
494 " eor%.w %/d0,%/d0\n" \
495 " swap %/d0\n" \
496 " add%.l %/d0,%/d2\n" \
497 " add%.l %/d3,%/d2\n" \
498 " jcc 1f\n" \
499 " add%.l %#65536,%/d1\n" \
500 "1: swap %/d2\n" \
501 " moveq %#0,%/d0\n" \
502 " move%.w %/d2,%/d0\n" \
503 " move%.w %/d4,%/d2\n" \
504 " move%.l %/d2,%1\n" \
505 " add%.l %/d1,%/d0\n" \
506 " move%.l %/d0,%0" \
507 : "=g" ((USItype) (xh)), \
508 "=g" ((USItype) (xl)) \
509 : "g" ((USItype) (a)), \
510 "g" ((USItype) (b)) \
511 : "d0", "d1", "d2", "d3", "d4")
512 #define UMUL_TIME 100
513 #define UDIV_TIME 400
514
515 #endif /* not mc68020 */
516
517 /* The '020, '030, '040 and '060 have bitfield insns.
518 cpu32 disguises as a 68020, but lacks them. */
519 #if defined (__mc68020__) && !defined (__mcpu32__)
520 #define count_leading_zeros(count, x) \
521 __asm__ ("bfffo %1{%b2:%b2},%0" \
522 : "=d" ((USItype) (count)) \
523 : "od" ((USItype) (x)), "n" (0))
524 #endif
525 #endif /* mc68000 */
526
527 #if defined (__m88000__) && W_TYPE_SIZE == 32
528 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
529 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
530 : "=r" ((USItype) (sh)), \
531 "=&r" ((USItype) (sl)) \
532 : "%rJ" ((USItype) (ah)), \
533 "rJ" ((USItype) (bh)), \
534 "%rJ" ((USItype) (al)), \
535 "rJ" ((USItype) (bl)))
536 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
537 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
538 : "=r" ((USItype) (sh)), \
539 "=&r" ((USItype) (sl)) \
540 : "rJ" ((USItype) (ah)), \
541 "rJ" ((USItype) (bh)), \
542 "rJ" ((USItype) (al)), \
543 "rJ" ((USItype) (bl)))
544 #define count_leading_zeros(count, x) \
545 do { \
546 USItype __cbtmp; \
547 __asm__ ("ff1 %0,%1" \
548 : "=r" (__cbtmp) \
549 : "r" ((USItype) (x))); \
550 (count) = __cbtmp ^ 31; \
551 } while (0)
552 #define COUNT_LEADING_ZEROS_0 63 /* sic */
553 #if defined (__mc88110__)
554 #define umul_ppmm(wh, wl, u, v) \
555 do { \
556 union {UDItype __ll; \
557 struct {USItype __h, __l;} __i; \
558 } __xx; \
559 __asm__ ("mulu.d %0,%1,%2" \
560 : "=r" (__xx.__ll) \
561 : "r" ((USItype) (u)), \
562 "r" ((USItype) (v))); \
563 (wh) = __xx.__i.__h; \
564 (wl) = __xx.__i.__l; \
565 } while (0)
566 #define udiv_qrnnd(q, r, n1, n0, d) \
567 ({union {UDItype __ll; \
568 struct {USItype __h, __l;} __i; \
569 } __xx; \
570 USItype __q; \
571 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
572 __asm__ ("divu.d %0,%1,%2" \
573 : "=r" (__q) \
574 : "r" (__xx.__ll), \
575 "r" ((USItype) (d))); \
576 (r) = (n0) - __q * (d); (q) = __q; })
577 #define UMUL_TIME 5
578 #define UDIV_TIME 25
579 #else
580 #define UMUL_TIME 17
581 #define UDIV_TIME 150
582 #endif /* __mc88110__ */
583 #endif /* __m88000__ */
584
585 #if defined (__mips__) && W_TYPE_SIZE == 32
586 #define umul_ppmm(w1, w0, u, v) \
587 __asm__ ("multu %2,%3" \
588 : "=l" ((USItype) (w0)), \
589 "=h" ((USItype) (w1)) \
590 : "d" ((USItype) (u)), \
591 "d" ((USItype) (v)))
592 #define UMUL_TIME 10
593 #define UDIV_TIME 100
594 #endif /* __mips__ */
595
596 #if defined (__ns32000__) && W_TYPE_SIZE == 32
597 #define umul_ppmm(w1, w0, u, v) \
598 ({union {UDItype __ll; \
599 struct {USItype __l, __h;} __i; \
600 } __xx; \
601 __asm__ ("meid %2,%0" \
602 : "=g" (__xx.__ll) \
603 : "%0" ((USItype) (u)), \
604 "g" ((USItype) (v))); \
605 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
606 #define __umulsidi3(u, v) \
607 ({UDItype __w; \
608 __asm__ ("meid %2,%0" \
609 : "=g" (__w) \
610 : "%0" ((USItype) (u)), \
611 "g" ((USItype) (v))); \
612 __w; })
613 #define udiv_qrnnd(q, r, n1, n0, d) \
614 ({union {UDItype __ll; \
615 struct {USItype __l, __h;} __i; \
616 } __xx; \
617 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
618 __asm__ ("deid %2,%0" \
619 : "=g" (__xx.__ll) \
620 : "0" (__xx.__ll), \
621 "g" ((USItype) (d))); \
622 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
623 #define count_trailing_zeros(count,x) \
624 do { \
625 __asm__ ("ffsd %2,%0" \
626 : "=r" ((USItype) (count)) \
627 : "0" ((USItype) 0), \
628 "r" ((USItype) (x))); \
629 } while (0)
630 #endif /* __ns32000__ */
631
632 /* FIXME: We should test _IBMR2 here when we add assembly support for the
633 system vendor compilers.
634 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
635 enough, since that hits ARM and m68k too. */
636 #if (defined (_ARCH_PPC) /* AIX */ \
637 || defined (_ARCH_PWR) /* AIX */ \
638 || defined (_ARCH_COM) /* AIX */ \
639 || defined (__powerpc__) /* gcc */ \
640 || defined (__POWERPC__) /* BEOS */ \
641 || defined (__ppc__) /* Darwin */ \
642 || defined (PPC) /* GNU/Linux, SysV */ \
643 ) && W_TYPE_SIZE == 32
644 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
645 do { \
646 if (__builtin_constant_p (bh) && (bh) == 0) \
647 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
648 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
649 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
650 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
651 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
652 else \
653 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
654 : "=r" (sh), "=&r" (sl) \
655 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
656 } while (0)
657 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
658 do { \
659 if (__builtin_constant_p (ah) && (ah) == 0) \
660 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
661 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
662 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
663 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
664 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
665 else if (__builtin_constant_p (bh) && (bh) == 0) \
666 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
667 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
668 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
669 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
670 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
671 else \
672 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
673 : "=r" (sh), "=&r" (sl) \
674 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
675 } while (0)
676 #define count_leading_zeros(count, x) \
677 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
678 #define COUNT_LEADING_ZEROS_0 32
679 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
680 || defined (__ppc__) || defined (PPC)
681 #define umul_ppmm(ph, pl, m0, m1) \
682 do { \
683 USItype __m0 = (m0), __m1 = (m1); \
684 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
685 (pl) = __m0 * __m1; \
686 } while (0)
687 #define UMUL_TIME 15
688 #define smul_ppmm(ph, pl, m0, m1) \
689 do { \
690 SItype __m0 = (m0), __m1 = (m1); \
691 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
692 (pl) = __m0 * __m1; \
693 } while (0)
694 #define SMUL_TIME 14
695 #define UDIV_TIME 120
696 #elif defined (_ARCH_PWR)
697 #define UMUL_TIME 8
698 #define smul_ppmm(xh, xl, m0, m1) \
699 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
700 #define SMUL_TIME 4
701 #define sdiv_qrnnd(q, r, nh, nl, d) \
702 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
703 #define UDIV_TIME 100
704 #endif
705 #endif /* 32-bit POWER architecture variants. */
706
707 /* We should test _IBMR2 here when we add assembly support for the system
708 vendor compilers. */
709 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
710 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
711 do { \
712 if (__builtin_constant_p (bh) && (bh) == 0) \
713 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
714 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
715 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
716 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
717 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
718 else \
719 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
720 : "=r" (sh), "=&r" (sl) \
721 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
722 } while (0)
723 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
724 do { \
725 if (__builtin_constant_p (ah) && (ah) == 0) \
726 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
727 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
728 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
729 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
730 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
731 else if (__builtin_constant_p (bh) && (bh) == 0) \
732 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
733 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
734 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
735 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
736 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
737 else \
738 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
739 : "=r" (sh), "=&r" (sl) \
740 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
741 } while (0)
742 #define count_leading_zeros(count, x) \
743 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
744 #define COUNT_LEADING_ZEROS_0 64
745 #define umul_ppmm(ph, pl, m0, m1) \
746 do { \
747 UDItype __m0 = (m0), __m1 = (m1); \
748 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
749 (pl) = __m0 * __m1; \
750 } while (0)
751 #define UMUL_TIME 15
752 #define smul_ppmm(ph, pl, m0, m1) \
753 do { \
754 DItype __m0 = (m0), __m1 = (m1); \
755 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
756 (pl) = __m0 * __m1; \
757 } while (0)
758 #define SMUL_TIME 14 /* ??? */
759 #define UDIV_TIME 120 /* ??? */
760 #endif /* 64-bit PowerPC. */
761
762 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
763 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
764 __asm__ ("a %1,%5\n\tae %0,%3" \
765 : "=r" ((USItype) (sh)), \
766 "=&r" ((USItype) (sl)) \
767 : "%0" ((USItype) (ah)), \
768 "r" ((USItype) (bh)), \
769 "%1" ((USItype) (al)), \
770 "r" ((USItype) (bl)))
771 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
772 __asm__ ("s %1,%5\n\tse %0,%3" \
773 : "=r" ((USItype) (sh)), \
774 "=&r" ((USItype) (sl)) \
775 : "0" ((USItype) (ah)), \
776 "r" ((USItype) (bh)), \
777 "1" ((USItype) (al)), \
778 "r" ((USItype) (bl)))
779 #define umul_ppmm(ph, pl, m0, m1) \
780 do { \
781 USItype __m0 = (m0), __m1 = (m1); \
782 __asm__ ( \
783 "s r2,r2\n" \
784 " mts r10,%2\n" \
785 " m r2,%3\n" \
786 " m r2,%3\n" \
787 " m r2,%3\n" \
788 " m r2,%3\n" \
789 " m r2,%3\n" \
790 " m r2,%3\n" \
791 " m r2,%3\n" \
792 " m r2,%3\n" \
793 " m r2,%3\n" \
794 " m r2,%3\n" \
795 " m r2,%3\n" \
796 " m r2,%3\n" \
797 " m r2,%3\n" \
798 " m r2,%3\n" \
799 " m r2,%3\n" \
800 " m r2,%3\n" \
801 " cas %0,r2,r0\n" \
802 " mfs r10,%1" \
803 : "=r" ((USItype) (ph)), \
804 "=r" ((USItype) (pl)) \
805 : "%r" (__m0), \
806 "r" (__m1) \
807 : "r2"); \
808 (ph) += ((((SItype) __m0 >> 31) & __m1) \
809 + (((SItype) __m1 >> 31) & __m0)); \
810 } while (0)
811 #define UMUL_TIME 20
812 #define UDIV_TIME 200
813 #define count_leading_zeros(count, x) \
814 do { \
815 if ((x) >= 0x10000) \
816 __asm__ ("clz %0,%1" \
817 : "=r" ((USItype) (count)) \
818 : "r" ((USItype) (x) >> 16)); \
819 else \
820 { \
821 __asm__ ("clz %0,%1" \
822 : "=r" ((USItype) (count)) \
823 : "r" ((USItype) (x))); \
824 (count) += 16; \
825 } \
826 } while (0)
827 #endif
828
829 #if defined (__sh2__) && W_TYPE_SIZE == 32
830 #define umul_ppmm(w1, w0, u, v) \
831 __asm__ ( \
832 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
833 : "=r" ((USItype)(w1)), \
834 "=r" ((USItype)(w0)) \
835 : "r" ((USItype)(u)), \
836 "r" ((USItype)(v)) \
837 : "macl", "mach")
838 #define UMUL_TIME 5
839 #endif
840
841 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
842 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
843 #define count_leading_zeros(count, x) \
844 do \
845 { \
846 UDItype x_ = (USItype)(x); \
847 SItype c_; \
848 \
849 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
850 (count) = c_ - 31; \
851 } \
852 while (0)
853 #define COUNT_LEADING_ZEROS_0 32
854 #endif
855
856 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
857 && W_TYPE_SIZE == 32
858 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
859 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
860 : "=r" ((USItype) (sh)), \
861 "=&r" ((USItype) (sl)) \
862 : "%rJ" ((USItype) (ah)), \
863 "rI" ((USItype) (bh)), \
864 "%rJ" ((USItype) (al)), \
865 "rI" ((USItype) (bl)) \
866 __CLOBBER_CC)
867 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
868 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
869 : "=r" ((USItype) (sh)), \
870 "=&r" ((USItype) (sl)) \
871 : "rJ" ((USItype) (ah)), \
872 "rI" ((USItype) (bh)), \
873 "rJ" ((USItype) (al)), \
874 "rI" ((USItype) (bl)) \
875 __CLOBBER_CC)
876 #if defined (__sparc_v8__)
877 #define umul_ppmm(w1, w0, u, v) \
878 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
879 : "=r" ((USItype) (w1)), \
880 "=r" ((USItype) (w0)) \
881 : "r" ((USItype) (u)), \
882 "r" ((USItype) (v)))
883 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
884 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
885 : "=&r" ((USItype) (__q)), \
886 "=&r" ((USItype) (__r)) \
887 : "r" ((USItype) (__n1)), \
888 "r" ((USItype) (__n0)), \
889 "r" ((USItype) (__d)))
890 #else
891 #if defined (__sparclite__)
892 /* This has hardware multiply but not divide. It also has two additional
893 instructions scan (ffs from high bit) and divscc. */
894 #define umul_ppmm(w1, w0, u, v) \
895 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
896 : "=r" ((USItype) (w1)), \
897 "=r" ((USItype) (w0)) \
898 : "r" ((USItype) (u)), \
899 "r" ((USItype) (v)))
900 #define udiv_qrnnd(q, r, n1, n0, d) \
901 __asm__ ("! Inlined udiv_qrnnd\n" \
902 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
903 " tst %%g0\n" \
904 " divscc %3,%4,%%g1\n" \
905 " divscc %%g1,%4,%%g1\n" \
906 " divscc %%g1,%4,%%g1\n" \
907 " divscc %%g1,%4,%%g1\n" \
908 " divscc %%g1,%4,%%g1\n" \
909 " divscc %%g1,%4,%%g1\n" \
910 " divscc %%g1,%4,%%g1\n" \
911 " divscc %%g1,%4,%%g1\n" \
912 " divscc %%g1,%4,%%g1\n" \
913 " divscc %%g1,%4,%%g1\n" \
914 " divscc %%g1,%4,%%g1\n" \
915 " divscc %%g1,%4,%%g1\n" \
916 " divscc %%g1,%4,%%g1\n" \
917 " divscc %%g1,%4,%%g1\n" \
918 " divscc %%g1,%4,%%g1\n" \
919 " divscc %%g1,%4,%%g1\n" \
920 " divscc %%g1,%4,%%g1\n" \
921 " divscc %%g1,%4,%%g1\n" \
922 " divscc %%g1,%4,%%g1\n" \
923 " divscc %%g1,%4,%%g1\n" \
924 " divscc %%g1,%4,%%g1\n" \
925 " divscc %%g1,%4,%%g1\n" \
926 " divscc %%g1,%4,%%g1\n" \
927 " divscc %%g1,%4,%%g1\n" \
928 " divscc %%g1,%4,%%g1\n" \
929 " divscc %%g1,%4,%%g1\n" \
930 " divscc %%g1,%4,%%g1\n" \
931 " divscc %%g1,%4,%%g1\n" \
932 " divscc %%g1,%4,%%g1\n" \
933 " divscc %%g1,%4,%%g1\n" \
934 " divscc %%g1,%4,%%g1\n" \
935 " divscc %%g1,%4,%0\n" \
936 " rd %%y,%1\n" \
937 " bl,a 1f\n" \
938 " add %1,%4,%1\n" \
939 "1: ! End of inline udiv_qrnnd" \
940 : "=r" ((USItype) (q)), \
941 "=r" ((USItype) (r)) \
942 : "r" ((USItype) (n1)), \
943 "r" ((USItype) (n0)), \
944 "rI" ((USItype) (d)) \
945 : "g1" __AND_CLOBBER_CC)
946 #define UDIV_TIME 37
947 #define count_leading_zeros(count, x) \
948 do { \
949 __asm__ ("scan %1,1,%0" \
950 : "=r" ((USItype) (count)) \
951 : "r" ((USItype) (x))); \
952 } while (0)
953 /* Early sparclites return 63 for an argument of 0, but they warn that future
954 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
955 undefined. */
956 #else
957 /* SPARC without integer multiplication and divide instructions.
958 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
959 #define umul_ppmm(w1, w0, u, v) \
960 __asm__ ("! Inlined umul_ppmm\n" \
961 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
962 " sra %3,31,%%o5 ! Don't move this insn\n" \
963 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
964 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
965 " mulscc %%g1,%3,%%g1\n" \
966 " mulscc %%g1,%3,%%g1\n" \
967 " mulscc %%g1,%3,%%g1\n" \
968 " mulscc %%g1,%3,%%g1\n" \
969 " mulscc %%g1,%3,%%g1\n" \
970 " mulscc %%g1,%3,%%g1\n" \
971 " mulscc %%g1,%3,%%g1\n" \
972 " mulscc %%g1,%3,%%g1\n" \
973 " mulscc %%g1,%3,%%g1\n" \
974 " mulscc %%g1,%3,%%g1\n" \
975 " mulscc %%g1,%3,%%g1\n" \
976 " mulscc %%g1,%3,%%g1\n" \
977 " mulscc %%g1,%3,%%g1\n" \
978 " mulscc %%g1,%3,%%g1\n" \
979 " mulscc %%g1,%3,%%g1\n" \
980 " mulscc %%g1,%3,%%g1\n" \
981 " mulscc %%g1,%3,%%g1\n" \
982 " mulscc %%g1,%3,%%g1\n" \
983 " mulscc %%g1,%3,%%g1\n" \
984 " mulscc %%g1,%3,%%g1\n" \
985 " mulscc %%g1,%3,%%g1\n" \
986 " mulscc %%g1,%3,%%g1\n" \
987 " mulscc %%g1,%3,%%g1\n" \
988 " mulscc %%g1,%3,%%g1\n" \
989 " mulscc %%g1,%3,%%g1\n" \
990 " mulscc %%g1,%3,%%g1\n" \
991 " mulscc %%g1,%3,%%g1\n" \
992 " mulscc %%g1,%3,%%g1\n" \
993 " mulscc %%g1,%3,%%g1\n" \
994 " mulscc %%g1,%3,%%g1\n" \
995 " mulscc %%g1,%3,%%g1\n" \
996 " mulscc %%g1,%3,%%g1\n" \
997 " mulscc %%g1,0,%%g1\n" \
998 " add %%g1,%%o5,%0\n" \
999 " rd %%y,%1" \
1000 : "=r" ((USItype) (w1)), \
1001 "=r" ((USItype) (w0)) \
1002 : "%rI" ((USItype) (u)), \
1003 "r" ((USItype) (v)) \
1004 : "g1", "o5" __AND_CLOBBER_CC)
1005 #define UMUL_TIME 39 /* 39 instructions */
1006 /* It's quite necessary to add this much assembler for the sparc.
1007 The default udiv_qrnnd (in C) is more than 10 times slower! */
1008 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1009 __asm__ ("! Inlined udiv_qrnnd\n" \
1010 " mov 32,%%g1\n" \
1011 " subcc %1,%2,%%g0\n" \
1012 "1: bcs 5f\n" \
1013 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1014 " sub %1,%2,%1 ! this kills msb of n\n" \
1015 " addx %1,%1,%1 ! so this can't give carry\n" \
1016 " subcc %%g1,1,%%g1\n" \
1017 "2: bne 1b\n" \
1018 " subcc %1,%2,%%g0\n" \
1019 " bcs 3f\n" \
1020 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1021 " b 3f\n" \
1022 " sub %1,%2,%1 ! this kills msb of n\n" \
1023 "4: sub %1,%2,%1\n" \
1024 "5: addxcc %1,%1,%1\n" \
1025 " bcc 2b\n" \
1026 " subcc %%g1,1,%%g1\n" \
1027 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1028 " bne 4b\n" \
1029 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1030 " sub %1,%2,%1\n" \
1031 "3: xnor %0,0,%0\n" \
1032 " ! End of inline udiv_qrnnd" \
1033 : "=&r" ((USItype) (__q)), \
1034 "=&r" ((USItype) (__r)) \
1035 : "r" ((USItype) (__d)), \
1036 "1" ((USItype) (__n1)), \
1037 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1038 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1039 #endif /* __sparclite__ */
1040 #endif /* __sparc_v8__ */
1041 #endif /* sparc32 */
1042
1043 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1044 && W_TYPE_SIZE == 64
1045 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1046 __asm__ ("addcc %r4,%5,%1\n\t" \
1047 "add %r2,%3,%0\n\t" \
1048 "bcs,a,pn %%xcc, 1f\n\t" \
1049 "add %0, 1, %0\n" \
1050 "1:" \
1051 : "=r" ((UDItype)(sh)), \
1052 "=&r" ((UDItype)(sl)) \
1053 : "%rJ" ((UDItype)(ah)), \
1054 "rI" ((UDItype)(bh)), \
1055 "%rJ" ((UDItype)(al)), \
1056 "rI" ((UDItype)(bl)) \
1057 __CLOBBER_CC)
1058
1059 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1060 __asm__ ("subcc %r4,%5,%1\n\t" \
1061 "sub %r2,%3,%0\n\t" \
1062 "bcs,a,pn %%xcc, 1f\n\t" \
1063 "sub %0, 1, %0\n\t" \
1064 "1:" \
1065 : "=r" ((UDItype)(sh)), \
1066 "=&r" ((UDItype)(sl)) \
1067 : "rJ" ((UDItype)(ah)), \
1068 "rI" ((UDItype)(bh)), \
1069 "rJ" ((UDItype)(al)), \
1070 "rI" ((UDItype)(bl)) \
1071 __CLOBBER_CC)
1072
1073 #define umul_ppmm(wh, wl, u, v) \
1074 do { \
1075 UDItype tmp1, tmp2, tmp3, tmp4; \
1076 __asm__ __volatile__ ( \
1077 "srl %7,0,%3\n\t" \
1078 "mulx %3,%6,%1\n\t" \
1079 "srlx %6,32,%2\n\t" \
1080 "mulx %2,%3,%4\n\t" \
1081 "sllx %4,32,%5\n\t" \
1082 "srl %6,0,%3\n\t" \
1083 "sub %1,%5,%5\n\t" \
1084 "srlx %5,32,%5\n\t" \
1085 "addcc %4,%5,%4\n\t" \
1086 "srlx %7,32,%5\n\t" \
1087 "mulx %3,%5,%3\n\t" \
1088 "mulx %2,%5,%5\n\t" \
1089 "sethi %%hi(0x80000000),%2\n\t" \
1090 "addcc %4,%3,%4\n\t" \
1091 "srlx %4,32,%4\n\t" \
1092 "add %2,%2,%2\n\t" \
1093 "movcc %%xcc,%%g0,%2\n\t" \
1094 "addcc %5,%4,%5\n\t" \
1095 "sllx %3,32,%3\n\t" \
1096 "add %1,%3,%1\n\t" \
1097 "add %5,%2,%0" \
1098 : "=r" ((UDItype)(wh)), \
1099 "=&r" ((UDItype)(wl)), \
1100 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1101 : "r" ((UDItype)(u)), \
1102 "r" ((UDItype)(v)) \
1103 __CLOBBER_CC); \
1104 } while (0)
1105 #define UMUL_TIME 96
1106 #define UDIV_TIME 230
1107 #endif /* sparc64 */
1108
1109 #if defined (__vax__) && W_TYPE_SIZE == 32
1110 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1111 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1112 : "=g" ((USItype) (sh)), \
1113 "=&g" ((USItype) (sl)) \
1114 : "%0" ((USItype) (ah)), \
1115 "g" ((USItype) (bh)), \
1116 "%1" ((USItype) (al)), \
1117 "g" ((USItype) (bl)))
1118 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1119 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1120 : "=g" ((USItype) (sh)), \
1121 "=&g" ((USItype) (sl)) \
1122 : "0" ((USItype) (ah)), \
1123 "g" ((USItype) (bh)), \
1124 "1" ((USItype) (al)), \
1125 "g" ((USItype) (bl)))
1126 #define umul_ppmm(xh, xl, m0, m1) \
1127 do { \
1128 union { \
1129 UDItype __ll; \
1130 struct {USItype __l, __h;} __i; \
1131 } __xx; \
1132 USItype __m0 = (m0), __m1 = (m1); \
1133 __asm__ ("emul %1,%2,$0,%0" \
1134 : "=r" (__xx.__ll) \
1135 : "g" (__m0), \
1136 "g" (__m1)); \
1137 (xh) = __xx.__i.__h; \
1138 (xl) = __xx.__i.__l; \
1139 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1140 + (((SItype) __m1 >> 31) & __m0)); \
1141 } while (0)
1142 #define sdiv_qrnnd(q, r, n1, n0, d) \
1143 do { \
1144 union {DItype __ll; \
1145 struct {SItype __l, __h;} __i; \
1146 } __xx; \
1147 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1148 __asm__ ("ediv %3,%2,%0,%1" \
1149 : "=g" (q), "=g" (r) \
1150 : "g" (__xx.__ll), "g" (d)); \
1151 } while (0)
1152 #endif /* __vax__ */
1153
1154 #if defined (__z8000__) && W_TYPE_SIZE == 16
1155 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1156 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1157 : "=r" ((unsigned int)(sh)), \
1158 "=&r" ((unsigned int)(sl)) \
1159 : "%0" ((unsigned int)(ah)), \
1160 "r" ((unsigned int)(bh)), \
1161 "%1" ((unsigned int)(al)), \
1162 "rQR" ((unsigned int)(bl)))
1163 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1164 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1165 : "=r" ((unsigned int)(sh)), \
1166 "=&r" ((unsigned int)(sl)) \
1167 : "0" ((unsigned int)(ah)), \
1168 "r" ((unsigned int)(bh)), \
1169 "1" ((unsigned int)(al)), \
1170 "rQR" ((unsigned int)(bl)))
1171 #define umul_ppmm(xh, xl, m0, m1) \
1172 do { \
1173 union {long int __ll; \
1174 struct {unsigned int __h, __l;} __i; \
1175 } __xx; \
1176 unsigned int __m0 = (m0), __m1 = (m1); \
1177 __asm__ ("mult %S0,%H3" \
1178 : "=r" (__xx.__i.__h), \
1179 "=r" (__xx.__i.__l) \
1180 : "%1" (__m0), \
1181 "rQR" (__m1)); \
1182 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1183 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1184 + (((signed int) __m1 >> 15) & __m0)); \
1185 } while (0)
1186 #endif /* __z8000__ */
1187
1188 #endif /* __GNUC__ */
1189
1190 /* If this machine has no inline assembler, use C macros. */
1191
1192 #if !defined (add_ssaaaa)
1193 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1194 do { \
1195 UWtype __x; \
1196 __x = (al) + (bl); \
1197 (sh) = (ah) + (bh) + (__x < (al)); \
1198 (sl) = __x; \
1199 } while (0)
1200 #endif
1201
1202 #if !defined (sub_ddmmss)
1203 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1204 do { \
1205 UWtype __x; \
1206 __x = (al) - (bl); \
1207 (sh) = (ah) - (bh) - (__x > (al)); \
1208 (sl) = __x; \
1209 } while (0)
1210 #endif
1211
1212 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1213 smul_ppmm. */
1214 #if !defined (umul_ppmm) && defined (smul_ppmm)
1215 #define umul_ppmm(w1, w0, u, v) \
1216 do { \
1217 UWtype __w1; \
1218 UWtype __xm0 = (u), __xm1 = (v); \
1219 smul_ppmm (__w1, w0, __xm0, __xm1); \
1220 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1221 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1222 } while (0)
1223 #endif
1224
1225 /* If we still don't have umul_ppmm, define it using plain C. */
1226 #if !defined (umul_ppmm)
1227 #define umul_ppmm(w1, w0, u, v) \
1228 do { \
1229 UWtype __x0, __x1, __x2, __x3; \
1230 UHWtype __ul, __vl, __uh, __vh; \
1231 \
1232 __ul = __ll_lowpart (u); \
1233 __uh = __ll_highpart (u); \
1234 __vl = __ll_lowpart (v); \
1235 __vh = __ll_highpart (v); \
1236 \
1237 __x0 = (UWtype) __ul * __vl; \
1238 __x1 = (UWtype) __ul * __vh; \
1239 __x2 = (UWtype) __uh * __vl; \
1240 __x3 = (UWtype) __uh * __vh; \
1241 \
1242 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1243 __x1 += __x2; /* but this indeed can */ \
1244 if (__x1 < __x2) /* did we get it? */ \
1245 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1246 \
1247 (w1) = __x3 + __ll_highpart (__x1); \
1248 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1249 } while (0)
1250 #endif
1251
1252 #if !defined (__umulsidi3)
1253 #define __umulsidi3(u, v) \
1254 ({DWunion __w; \
1255 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1256 __w.ll; })
1257 #endif
1258
1259 /* Define this unconditionally, so it can be used for debugging. */
1260 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1261 do { \
1262 UWtype __d1, __d0, __q1, __q0; \
1263 UWtype __r1, __r0, __m; \
1264 __d1 = __ll_highpart (d); \
1265 __d0 = __ll_lowpart (d); \
1266 \
1267 __r1 = (n1) % __d1; \
1268 __q1 = (n1) / __d1; \
1269 __m = (UWtype) __q1 * __d0; \
1270 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1271 if (__r1 < __m) \
1272 { \
1273 __q1--, __r1 += (d); \
1274 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1275 if (__r1 < __m) \
1276 __q1--, __r1 += (d); \
1277 } \
1278 __r1 -= __m; \
1279 \
1280 __r0 = __r1 % __d1; \
1281 __q0 = __r1 / __d1; \
1282 __m = (UWtype) __q0 * __d0; \
1283 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1284 if (__r0 < __m) \
1285 { \
1286 __q0--, __r0 += (d); \
1287 if (__r0 >= (d)) \
1288 if (__r0 < __m) \
1289 __q0--, __r0 += (d); \
1290 } \
1291 __r0 -= __m; \
1292 \
1293 (q) = (UWtype) __q1 * __ll_B | __q0; \
1294 (r) = __r0; \
1295 } while (0)
1296
1297 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1298 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1299 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1300 #define udiv_qrnnd(q, r, nh, nl, d) \
1301 do { \
1302 USItype __r; \
1303 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1304 (r) = __r; \
1305 } while (0)
1306 #endif
1307
1308 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1309 #if !defined (udiv_qrnnd)
1310 #define UDIV_NEEDS_NORMALIZATION 1
1311 #define udiv_qrnnd __udiv_qrnnd_c
1312 #endif
1313
1314 #if !defined (count_leading_zeros)
1315 extern const UQItype __clz_tab[] ATTRIBUTE_HIDDEN;
1316 #define count_leading_zeros(count, x) \
1317 do { \
1318 UWtype __xr = (x); \
1319 UWtype __a; \
1320 \
1321 if (W_TYPE_SIZE <= 32) \
1322 { \
1323 __a = __xr < ((UWtype)1<<2*__BITS4) \
1324 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1325 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1326 } \
1327 else \
1328 { \
1329 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1330 if (((__xr >> __a) & 0xff) != 0) \
1331 break; \
1332 } \
1333 \
1334 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1335 } while (0)
1336 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1337 #endif
1338
1339 #if !defined (count_trailing_zeros)
1340 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1341 defined in asm, but if it is not, the C version above is good enough. */
1342 #define count_trailing_zeros(count, x) \
1343 do { \
1344 UWtype __ctz_x = (x); \
1345 UWtype __ctz_c; \
1346 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1347 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1348 } while (0)
1349 #endif
1350
1351 #ifndef UDIV_NEEDS_NORMALIZATION
1352 #define UDIV_NEEDS_NORMALIZATION 0
1353 #endif
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