| blob | af3aa0b895674a67164458cd26f12827b3243dbb |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
68 /* This file should be included last. */
71 /* Defined for convenience. */
72 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
74 /* Classifies an address.
76 ADDRESS_REG_IMM
77 A simple base register plus immediate offset.
79 ADDRESS_REG_WB
80 A base register indexed by immediate offset with writeback.
82 ADDRESS_REG_REG
83 A base register indexed by (optionally scaled) register.
85 ADDRESS_REG_UXTW
86 A base register indexed by (optionally scaled) zero-extended register.
88 ADDRESS_REG_SXTW
89 A base register indexed by (optionally scaled) sign-extended register.
91 ADDRESS_LO_SUM
92 A LO_SUM rtx with a base register and "LO12" symbol relocation.
94 ADDRESS_SYMBOLIC:
95 A constant symbolic address, in pc-relative literal pool. */
98 ADDRESS_REG_IMM,
99 ADDRESS_REG_WB,
100 ADDRESS_REG_REG,
101 ADDRESS_REG_UXTW,
102 ADDRESS_REG_SXTW,
103 ADDRESS_LO_SUM,
104 ADDRESS_SYMBOLIC
105 };
109 rtx base;
110 rtx offset;
113 };
115 struct simd_immediate_info
116 {
117 rtx value;
122 };
124 /* The current code model. */
127 #ifdef HAVE_AS_TLS
128 #undef TARGET_HAVE_TLS
129 #define TARGET_HAVE_TLS 1
130 #endif
134 const_tree,
145 /* Major revision number of the ARM Architecture implemented by the target. */
148 /* The processor for which instructions should be scheduled. */
151 /* Mask to specify which instruction scheduling options should be used. */
154 /* Global flag for PC relative loads. */
157 /* Support for command line parsing of boolean flags in the tuning
158 structures. */
159 struct aarch64_flag_desc
160 {
163 };
165 #define AARCH64_FUSION_PAIR(name, internal_name) \
166 { name, AARCH64_FUSE_##internal_name },
168 {
173 };
175 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
176 { name, AARCH64_EXTRA_TUNE_##internal_name },
178 {
183 };
185 /* Tuning parameters. */
188 {
189 {
194 },
201 };
204 {
205 {
210 },
217 };
220 {
221 {
226 },
233 };
236 {
237 {
242 },
249 };
252 {
253 {
258 },
265 };
268 {
269 {
274 },
281 };
284 {
286 /* Avoid the use of slow int<->fp moves for spilling by setting
287 their cost higher than memmov_cost. */
291 };
294 {
296 /* Avoid the use of slow int<->fp moves for spilling by setting
297 their cost higher than memmov_cost. */
301 };
304 {
306 /* Avoid the use of slow int<->fp moves for spilling by setting
307 their cost higher than memmov_cost. */
311 };
314 {
316 /* Avoid the use of slow int<->fp moves for spilling by setting
317 their cost higher than memmov_cost (actual, 4 and 9). */
321 };
324 {
329 };
332 {
334 /* Avoid the use of slow int<->fp moves for spilling by setting
335 their cost higher than memmov_cost. */
339 };
342 {
344 /* Avoid the use of int<->fp moves for spilling. */
348 };
351 {
353 /* Avoid the use of int<->fp moves for spilling. */
357 };
359 /* Generic costs for vector insn classes. */
361 {
375 };
377 /* ThunderX costs for vector insn classes. */
379 {
393 };
395 /* Generic costs for vector insn classes. */
397 {
411 };
414 {
428 };
430 /* Generic costs for vector insn classes. */
432 {
446 };
448 /* Costs for vector insn classes for Vulcan. */
450 {
464 };
466 /* Generic costs for branch instructions. */
468 {
471 };
473 /* Branch costs for Cortex-A57. */
475 {
478 };
480 /* Branch costs for Vulcan. */
482 {
485 };
487 /* Generic approximation modes. */
489 {
492 AARCH64_APPROX_NONE /* recip_sqrt */
493 };
495 /* Approximation modes for Exynos M1. */
497 {
500 AARCH64_APPROX_ALL /* recip_sqrt */
501 };
503 /* Approximation modes for X-Gene 1. */
505 {
508 AARCH64_APPROX_ALL /* recip_sqrt */
509 };
512 {
534 };
537 {
560 };
563 {
586 };
589 {
612 };
615 {
638 };
641 {
664 };
667 {
689 };
692 {
714 };
717 {
739 };
742 {
765 };
768 {
790 };
792 /* Support for fine-grained override of the tuning structures. */
793 struct aarch64_tuning_override_function
794 {
797 };
802 static const struct aarch64_tuning_override_function
803 aarch64_tuning_override_functions[] =
804 {
808 };
810 /* A processor implementing AArch64. */
811 struct processor
812 {
820 };
822 /* Architectures implementing AArch64. */
824 {
825 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
826 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
829 };
831 /* Processor cores implementing AArch64. */
833 {
834 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
835 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
836 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
837 FLAGS, &COSTS##_tunings},
842 };
845 /* Target specification. These are populated by the -march, -mtune, -mcpu
846 handling code or by target attributes. */
851 /* The current tuning set. */
854 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
856 /* An ISA extension in the co-processor and main instruction set space. */
857 struct aarch64_option_extension
858 {
862 };
865 {
869 }
870 aarch64_cc;
872 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
874 /* The condition codes of the processor, and the inverse function. */
876 {
879 };
881 /* Generate code to enable conditional branches in functions over 1 MiB. */
885 {
902 }
904 void
906 {
910 else
912 }
914 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
915 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
916 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
917 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
918 cost (in this case the best class is the lowest cost one). Using ALL_REGS
919 irrespectively of its cost results in bad allocations with many redundant
920 int<->FP moves which are expensive on various cores.
921 To avoid this we don't allow ALL_REGS as the allocno class, but force a
922 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
923 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
924 Otherwise set the allocno class depending on the mode.
925 The result of this is that it is no longer inefficient to have a higher
926 memory move cost than the register move cost.
927 */
929 static reg_class_t
931 reg_class_t best_class)
932 {
943 }
945 static unsigned int
947 {
951 }
953 static int
956 {
964 }
966 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
967 unsigned
969 {
977 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
978 equivalent DWARF register. */
980 }
982 /* Return TRUE if MODE is any of the large INT modes. */
983 static bool
985 {
987 }
989 /* Return TRUE if MODE is any of the vector modes. */
990 static bool
992 {
995 }
997 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
998 static bool
1001 {
1009 }
1011 /* Implement HARD_REGNO_NREGS. */
1013 int
1015 {
1017 {
1023 }
1025 }
1027 /* Implement HARD_REGNO_MODE_OK. */
1029 int
1031 {
1036 /* The purpose of comparing with ptr_mode is to support the
1037 global register variable associated with the stack pointer
1038 register via the syntax of asm ("wsp") in ILP32. */
1048 {
1050 return
1052 else
1054 }
1057 }
1059 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1060 machine_mode
1062 machine_mode mode)
1063 {
1064 /* Handle modes that fit within single registers. */
1066 {
1069 else
1071 }
1072 /* Fall back to generic for multi-reg and very large modes. */
1073 else
1075 }
1077 /* Return true if calls to DECL should be treated as
1078 long-calls (ie called via a register). */
1079 static bool
1081 {
1083 }
1085 /* Return true if calls to symbol-ref SYM should be treated as
1086 long-calls (ie called via a register). */
1087 bool
1089 {
1091 }
1093 /* Return true if calls to symbol-ref SYM should not go through
1094 plt stubs. */
1096 bool
1098 {
1102 && decl
1103 && (!flag_plt
1109 }
1111 /* Return true if the offsets to a zero/sign-extract operation
1112 represent an expression that matches an extend operation. The
1113 operands represent the paramters from
1115 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1116 bool
1118 rtx extract_imm)
1119 {
1136 }
1138 /* Emit an insn that's a simple single-set. Both the operands must be
1139 known to be valid. */
1142 {
1144 }
1146 /* X and Y are two things to compare using CODE. Emit the compare insn and
1147 return the rtx for register 0 in the proper mode. */
1148 rtx
1150 {
1156 }
1158 /* Build the SYMBOL_REF for __tls_get_addr. */
1162 rtx
1164 {
1168 }
1170 /* Return the TLS model to use for ADDR. */
1172 static enum tls_model
1174 {
1179 {
1183 }
1188 }
1190 /* We'll allow lo_sum's in addresses in our legitimate addresses
1191 so that combine would take care of combining addresses where
1192 necessary, but for generation purposes, we'll generate the address
1193 as :
1194 RTL Absolute
1195 tmp = hi (symbol_ref); adrp x1, foo
1196 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1197 nop
1199 PIC TLS
1200 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1201 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1202 bl __tls_get_addr
1203 nop
1205 Load TLS symbol, depending on TLS mechanism and TLS access model.
1207 Global Dynamic - Traditional TLS:
1208 adrp tmp, :tlsgd:imm
1209 add dest, tmp, #:tlsgd_lo12:imm
1210 bl __tls_get_addr
1212 Global Dynamic - TLS Descriptors:
1213 adrp dest, :tlsdesc:imm
1214 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1215 add dest, dest, #:tlsdesc_lo12:imm
1216 blr tmp
1217 mrs tp, tpidr_el0
1218 add dest, dest, tp
1220 Initial Exec:
1221 mrs tp, tpidr_el0
1222 adrp tmp, :gottprel:imm
1223 ldr dest, [tmp, #:gottprel_lo12:imm]
1224 add dest, dest, tp
1226 Local Exec:
1227 mrs tp, tpidr_el0
1228 add t0, tp, #:tprel_hi12:imm, lsl #12
1229 add t0, t0, #:tprel_lo12_nc:imm
1230 */
1232 static void
1235 {
1237 {
1239 {
1240 /* In ILP32, the mode of dest can be either SImode or DImode. */
1252 }
1259 {
1262 rtx insn;
1263 rtx mem;
1265 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1266 here before rtl expand. Tree IVOPT will generate rtl pattern to
1267 decide rtx costs, in which case pic_offset_table_rtx is not
1268 initialized. For that case no need to generate the first adrp
1269 instruction as the final cost for global variable access is
1270 one instruction. */
1272 {
1273 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1274 using the page base as GOT base, the first page may be wasted,
1275 in the worst scenario, there is only 28K space for GOT).
1277 The generate instruction sequence for accessing global variable
1278 is:
1280 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1282 Only one instruction needed. But we must initialize
1283 pic_offset_table_rtx properly. We generate initialize insn for
1284 every global access, and allow CSE to remove all redundant.
1286 The final instruction sequences will look like the following
1287 for multiply global variables access.
1289 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1291 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1292 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1293 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1294 ... */
1302 }
1305 {
1308 else
1312 }
1313 else
1314 {
1319 }
1321 /* The operand is expected to be MEM. Whenever the related insn
1322 pattern changed, above code which calculate mem should be
1323 updated. */
1329 }
1332 {
1333 /* In ILP32, the mode of dest can be either SImode or DImode,
1334 while the got entry is always of SImode size. The mode of
1335 dest depends on how dest is used: if dest is assigned to a
1336 pointer (e.g. in the memory), it has SImode; it may have
1337 DImode if dest is dereferenced to access the memeory.
1338 This is why we have to handle three different ldr_got_small
1339 patterns here (two patterns for ILP32). */
1341 rtx insn;
1342 rtx mem;
1351 {
1354 else
1358 }
1359 else
1360 {
1365 }
1372 }
1375 {
1387 }
1390 {
1393 rtx tp;
1397 /* In ILP32, the got entry is always of SImode size. Unlike
1398 small GOT, the dest is fixed at reg 0. */
1401 else
1411 }
1414 {
1415 /* In ILP32, the mode of dest can be either SImode or DImode,
1416 while the got entry is always of SImode size. The mode of
1417 dest depends on how dest is used: if dest is assigned to a
1418 pointer (e.g. in the memory), it has SImode; it may have
1419 DImode if dest is dereferenced to access the memeory.
1420 This is why we have to handle three different tlsie_small
1421 patterns here (two patterns for ILP32). */
1427 {
1430 else
1431 {
1434 }
1435 }
1436 else
1437 {
1440 }
1445 }
1451 {
1459 {
1482 }
1486 }
1493 {
1498 {
1501 else
1502 {
1505 }
1506 }
1507 else
1508 {
1511 }
1515 }
1519 }
1520 }
1522 /* Emit a move from SRC to DEST. Assume that the move expanders can
1523 handle all moves if !can_create_pseudo_p (). The distinction is
1524 important because, unlike emit_move_insn, the move expanders know
1525 how to force Pmode objects into the constant pool even when the
1526 constant pool address is not itself legitimate. */
1527 static rtx
1529 {
1533 }
1535 /* Split a 128-bit move operation into two 64-bit move operations,
1536 taking care to handle partial overlap of register to register
1537 copies. Special cases are needed when moving between GP regs and
1538 FP regs. SRC can be a register, constant or memory; DST a register
1539 or memory. If either operand is memory it must not have any side
1540 effects. */
1541 void
1543 {
1554 {
1558 /* Handle FP <-> GP regs. */
1560 {
1565 {
1568 }
1569 else
1570 {
1573 }
1575 }
1577 {
1582 {
1585 }
1586 else
1587 {
1590 }
1592 }
1593 }
1600 /* At most one pairing may overlap. */
1602 {
1605 }
1606 else
1607 {
1610 }
1611 }
1613 bool
1615 {
1618 }
1620 /* Split a complex SIMD combine. */
1622 void
1624 {
1631 {
1635 {
1659 }
1663 }
1664 }
1666 /* Split a complex SIMD move. */
1668 void
1670 {
1677 {
1683 {
1707 }
1711 }
1712 }
1714 bool
1717 {
1721 }
1724 static rtx
1726 {
1729 else
1730 {
1733 }
1734 }
1737 static rtx
1739 {
1741 {
1742 rtx high;
1743 /* Load the full offset into a register. This
1744 might be improvable in the future. */
1750 }
1752 }
1754 static int
1756 machine_mode mode)
1757 {
1766 {
1770 }
1773 {
1775 {
1780 else
1783 }
1785 }
1787 /* Remaining cases are all for DImode. */
1796 {
1797 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1798 For a 64-bit bitmask try whether changing 16 bits to all ones or
1799 zeroes creates a valid bitmask. To check any repeated bitmask,
1800 try using 16 bits from the other 32-bit half of val. */
1803 {
1814 }
1816 {
1818 {
1822 }
1824 }
1825 }
1827 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1828 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1829 otherwise skip zero bits. */
1841 {
1847 num_insns ++;
1848 }
1851 }
1854 void
1856 {
1861 /* Check on what type of symbol it is. */
1865 {
1869 /* If we have (const (plus symbol offset)), separate out the offset
1870 before we start classifying the symbol. */
1875 {
1879 {
1885 }
1890 /* If we aren't generating PC relative literals, then
1891 we need to expand the literal pool access carefully.
1892 This is something that needs to be done in a number
1893 of places, so could well live as a separate function. */
1895 {
1900 }
1917 {
1923 }
1924 /* FALLTHRU */
1937 }
1938 }
1941 {
1944 else
1945 {
1949 }
1952 }
1955 }
1957 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
1958 temporary value if necessary. FRAME_RELATED_P should be true if
1959 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
1960 to the generated instructions. If SCRATCHREG is known to hold
1961 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
1962 immediate again.
1964 Since this function may be used to adjust the stack pointer, we must
1965 ensure that it cannot cause transient stack deallocation (for example
1966 by first incrementing SP and then decrementing when adjusting by a
1967 large immediate). */
1969 static void
1973 {
1981 /* Single instruction adjustment. */
1983 {
1987 }
1989 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
1990 Only do this if mdelta is not a 16-bit move as adjusting using a move
1991 is better. */
1993 {
2002 }
2004 /* Emit a move immediate if required and an addition/subtraction. */
2011 {
2015 }
2016 }
2020 HOST_WIDE_INT delta)
2021 {
2023 }
2027 {
2030 }
2034 {
2037 }
2039 static bool
2041 tree exp ATTRIBUTE_UNUSED)
2042 {
2043 /* Currently, always true. */
2045 }
2047 /* Implement TARGET_PASS_BY_REFERENCE. */
2049 static bool
2051 machine_mode mode,
2052 const_tree type,
2054 {
2055 HOST_WIDE_INT size;
2056 machine_mode dummymode;
2059 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2063 /* Aggregates are passed by reference based on their size. */
2065 {
2067 }
2069 /* Variable sized arguments are always returned by reference. */
2073 /* Can this be a candidate to be passed in fp/simd register(s)? */
2076 NULL))
2079 /* Arguments which are variable sized or larger than 2 registers are
2080 passed by reference unless they are a homogenous floating point
2081 aggregate. */
2083 }
2085 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2086 static bool
2088 {
2089 machine_mode dummy_mode;
2092 /* Never happens in little-endian mode. */
2096 /* Only composite types smaller than or equal to 16 bytes can
2097 be potentially returned in registers. */
2103 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2104 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2105 is always passed/returned in the least significant bits of fp/simd
2106 register(s). */
2112 }
2114 /* Implement TARGET_FUNCTION_VALUE.
2115 Define how to find the value returned by a function. */
2117 static rtx
2120 {
2121 machine_mode mode;
2124 machine_mode ag_mode;
2131 {
2135 {
2138 }
2139 }
2143 {
2145 {
2148 }
2149 else
2150 {
2152 rtx par;
2156 {
2161 }
2163 }
2164 }
2165 else
2167 }
2169 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2170 Return true if REGNO is the number of a hard register in which the values
2171 of called function may come back. */
2173 static bool
2175 {
2176 /* Maximum of 16 bytes can be returned in the general registers. Examples
2177 of 16-byte return values are: 128-bit integers and 16-byte small
2178 structures (excluding homogeneous floating-point aggregates). */
2182 /* Up to four fp/simd registers can return a function value, e.g. a
2183 homogeneous floating-point aggregate having four members. */
2188 }
2190 /* Implement TARGET_RETURN_IN_MEMORY.
2192 If the type T of the result of a function is such that
2193 void func (T arg)
2194 would require that arg be passed as a value in a register (or set of
2195 registers) according to the parameter passing rules, then the result
2196 is returned in the same registers as would be used for such an
2197 argument. */
2199 static bool
2201 {
2202 HOST_WIDE_INT size;
2203 machine_mode ag_mode;
2209 /* Simple scalar types always returned in registers. */
2213 type,
2216 NULL))
2219 /* Types larger than 2 registers returned in memory. */
2222 }
2224 static bool
2227 {
2230 type,
2232 nregs,
2233 NULL);
2234 }
2236 /* Given MODE and TYPE of a function argument, return the alignment in
2237 bits. The idea is to suppress any stronger alignment requested by
2238 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2239 This is a helper function for local use only. */
2241 static unsigned int
2243 {
2263 }
2265 /* Layout a function argument according to the AAPCS64 rules. The rule
2266 numbers refer to the rule numbers in the AAPCS64. */
2268 static void
2270 const_tree type,
2272 {
2276 HOST_WIDE_INT size;
2278 /* We need to do this once per argument. */
2284 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2285 size
2287 UNITS_PER_WORD);
2291 mode,
2292 type,
2295 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2296 The following code thus handles passing by SIMD/FP registers first. */
2300 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2301 and homogenous short-vector aggregates (HVA). */
2303 {
2308 {
2311 {
2314 }
2315 else
2316 {
2317 rtx par;
2321 {
2324 tmp = gen_rtx_EXPR_LIST
2328 }
2330 }
2332 }
2333 else
2334 {
2335 /* C.3 NSRN is set to 8. */
2338 }
2339 }
2344 /* C6 - C9. though the sign and zero extension semantics are
2345 handled elsewhere. This is the case where the argument fits
2346 entirely general registers. */
2348 {
2353 /* C.8 if the argument has an alignment of 16 then the NGRN is
2354 rounded up to the next even number. */
2356 {
2359 }
2360 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2361 A reg is still generated for it, but the caller should be smart
2362 enough not to use it. */
2364 {
2366 }
2367 else
2368 {
2369 rtx par;
2374 {
2379 }
2381 }
2385 }
2387 /* C.11 */
2390 /* The argument is passed on stack; record the needed number of words for
2391 this argument and align the total size if necessary. */
2392 on_stack:
2398 }
2400 /* Implement TARGET_FUNCTION_ARG. */
2402 static rtx
2405 {
2414 }
2416 void
2418 const_tree fntype ATTRIBUTE_UNUSED,
2419 rtx libname ATTRIBUTE_UNUSED,
2420 const_tree fndecl ATTRIBUTE_UNUSED,
2422 {
2436 {
2443 }
2445 }
2447 static void
2449 machine_mode mode,
2450 const_tree type,
2452 {
2455 {
2465 }
2466 }
2468 bool
2470 {
2473 }
2475 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2476 PARM_BOUNDARY bits of alignment, but will be given anything up
2477 to STACK_BOUNDARY bits if the type requires it. This makes sure
2478 that both before and after the layout of each argument, the Next
2479 Stacked Argument Address (NSAA) will have a minimum alignment of
2480 8 bytes. */
2482 static unsigned int
2484 {
2492 }
2494 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2496 Return true if an argument passed on the stack should be padded upwards,
2497 i.e. if the least-significant byte of the stack slot has useful data.
2499 Small aggregate types are placed in the lowest memory address.
2501 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2503 bool
2505 {
2506 /* On little-endian targets, the least significant byte of every stack
2507 argument is passed at the lowest byte address of the stack slot. */
2511 /* Otherwise, integral, floating-point and pointer types are padded downward:
2512 the least significant byte of a stack argument is passed at the highest
2513 byte address of the stack slot. */
2520 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2522 }
2524 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2526 It specifies padding for the last (may also be the only)
2527 element of a block move between registers and memory. If
2528 assuming the block is in the memory, padding upward means that
2529 the last element is padded after its highest significant byte,
2530 while in downward padding, the last element is padded at the
2531 its least significant byte side.
2533 Small aggregates and small complex types are always padded
2534 upwards.
2536 We don't need to worry about homogeneous floating-point or
2537 short-vector aggregates; their move is not affected by the
2538 padding direction determined here. Regardless of endianness,
2539 each element of such an aggregate is put in the least
2540 significant bits of a fp/simd register.
2542 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2543 register has useful data, and return the opposite if the most
2544 significant byte does. */
2546 bool
2549 {
2551 /* Small composite types are always padded upward. */
2553 {
2558 }
2560 /* Otherwise, use the default padding. */
2562 }
2564 static machine_mode
2566 {
2568 }
2570 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2572 /* We use the 12-bit shifted immediate arithmetic instructions so values
2573 must be multiple of (1 << 12), i.e. 4096. */
2574 #define ARITH_FACTOR 4096
2576 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2577 #error Cannot use simple address calculation for stack probing
2578 #endif
2580 /* The pair of scratch registers used for stack probing. */
2581 #define PROBE_STACK_FIRST_REG 9
2582 #define PROBE_STACK_SECOND_REG 10
2584 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2585 inclusive. These are offsets from the current stack pointer. */
2587 static void
2589 {
2592 /* See the same assertion on PROBE_INTERVAL above. */
2595 /* See if we have a constant small number of probes to generate. If so,
2596 that's the easy case. */
2598 {
2605 }
2607 /* The run-time loop is made up of 8 insns in the generic case while the
2608 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2610 {
2615 stack_pointer_rtx,
2619 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2620 it exceeds SIZE. If only two probes are needed, this will not
2621 generate any code. Then probe at FIRST + SIZE. */
2623 {
2627 }
2631 {
2636 }
2637 else
2639 }
2641 /* Otherwise, do the same as above, but in a loop. Note that we must be
2642 extra careful with variables wrapping around because we might be at
2643 the very top (or the very bottom) of the address space and we have
2644 to be able to handle this case properly; in particular, we use an
2645 equality test for the loop condition. */
2646 else
2647 {
2650 /* Step 1: round SIZE to the previous multiple of the interval. */
2655 /* Step 2: compute initial and final value of the loop counter. */
2657 /* TEST_ADDR = SP + FIRST. */
2661 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2667 /* Step 3: the loop
2669 do
2670 {
2671 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2672 probe at TEST_ADDR
2673 }
2674 while (TEST_ADDR != LAST_ADDR)
2676 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2677 until it is equal to ROUNDED_SIZE. */
2681 else
2685 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2686 that SIZE is equal to ROUNDED_SIZE. */
2689 {
2693 {
2698 }
2699 else
2701 }
2702 }
2704 /* Make sure nothing is scheduled before we are done. */
2706 }
2708 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2709 absolute addresses. */
2713 {
2720 /* Loop. */
2723 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2728 /* Probe at TEST_ADDR. */
2731 /* Test if TEST_ADDR == LAST_ADDR. */
2735 /* Branch. */
2741 }
2743 static bool
2745 {
2746 /* In aarch64_override_options_after_change
2747 flag_omit_leaf_frame_pointer turns off the frame pointer by
2748 default. Turn it back on now if we've not got a leaf
2749 function. */
2755 }
2757 /* Mark the registers that need to be saved by the callee and calculate
2758 the size of the callee-saved registers area and frame record (both FP
2759 and LR may be omitted). */
2760 static void
2762 {
2769 #define SLOT_NOT_REQUIRED (-2)
2770 #define SLOT_REQUIRED (-1)
2775 /* First mark all the registers that really need to be saved... */
2782 /* ... that includes the eh data registers (if needed)... */
2788 /* ... and any callee saved register that dataflow says is live. */
2798 {
2801 }
2804 {
2805 /* FP and LR are placed in the linkage record. */
2811 }
2813 /* Now assign stack slots for them. */
2816 {
2823 }
2831 {
2832 /* If there is an alignment gap between integer and fp callee-saves,
2833 allocate the last fp register to it if possible. */
2835 {
2838 }
2847 }
2853 HOST_WIDE_INT varargs_and_saved_regs_size
2880 {
2881 /* Simple, small frame with no outgoing arguments:
2882 stp reg1, reg2, [sp, -frame_size]!
2883 stp reg3, reg4, [sp, 16] */
2885 }
2890 {
2891 /* Frame with small outgoing arguments:
2892 sub sp, sp, frame_size
2893 stp reg1, reg2, [sp, outgoing_args_size]
2894 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2898 }
2900 {
2901 /* Frame with large outgoing arguments but a small local area:
2902 stp reg1, reg2, [sp, -hard_fp_offset]!
2903 stp reg3, reg4, [sp, 16]
2904 sub sp, sp, outgoing_args_size */
2908 }
2911 {
2912 /* Frame with large local area and outgoing arguments (this pushes the
2913 callee-saves first, followed by the locals and outgoing area):
2914 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
2915 stp reg3, reg4, [sp, 16]
2916 sub sp, sp, frame_size - varargs_and_saved_regs_size */
2922 }
2923 else
2924 {
2925 /* Frame with large local area and outgoing arguments using frame pointer:
2926 sub sp, sp, hard_fp_offset
2927 stp x29, x30, [sp, 0]
2928 add x29, sp, 0
2929 stp reg3, reg4, [sp, 16]
2930 sub sp, sp, outgoing_args_size */
2934 }
2937 }
2939 /* Return true if the register REGNO is saved on entry to
2940 the current function. */
2942 static bool
2944 {
2946 }
2948 /* Return the next register up from REGNO up to LIMIT for the callee
2949 to save. */
2951 static unsigned
2953 {
2955 regno ++;
2957 }
2959 /* Push the register number REGNO of mode MODE to the stack with write-back
2960 adjusting the stack by ADJUSTMENT. */
2962 static void
2964 HOST_WIDE_INT adjustment)
2965 {
2976 }
2978 /* Generate and return an instruction to store the pair of registers
2979 REG and REG2 of mode MODE to location BASE with write-back adjusting
2980 the stack location BASE by ADJUSTMENT. */
2982 static rtx
2984 HOST_WIDE_INT adjustment)
2985 {
2987 {
2998 }
2999 }
3001 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3002 stack pointer by ADJUSTMENT. */
3004 static void
3006 {
3021 }
3023 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3024 adjusting it by ADJUSTMENT afterwards. */
3026 static rtx
3028 HOST_WIDE_INT adjustment)
3029 {
3031 {
3040 }
3041 }
3043 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3044 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3045 into CFI_OPS. */
3047 static void
3050 {
3057 {
3061 }
3062 else
3063 {
3068 }
3069 }
3071 /* Generate and return a store pair instruction of mode MODE to store
3072 register REG1 to MEM1 and register REG2 to MEM2. */
3074 static rtx
3076 rtx reg2)
3077 {
3079 {
3088 }
3089 }
3091 /* Generate and regurn a load pair isntruction of mode MODE to load register
3092 REG1 from MEM1 and register REG2 from MEM2. */
3094 static rtx
3096 rtx mem2)
3097 {
3099 {
3108 }
3109 }
3111 /* Emit code to save the callee-saved registers from register number START
3112 to LIMIT to the stack at the location starting at offset START_OFFSET,
3113 skipping any write-back candidates if SKIP_WB is true. */
3115 static void
3118 {
3128 {
3130 HOST_WIDE_INT offset;
3143 offset));
3152 {
3154 rtx mem2;
3158 offset));
3160 reg2));
3162 /* The first part of a frame-related parallel insn is
3163 always assumed to be relevant to the frame
3164 calculations; subsequent parts, are only
3165 frame-related if explicitly marked. */
3168 }
3169 else
3173 }
3174 }
3176 /* Emit code to restore the callee registers of mode MODE from register
3177 number START up to and including LIMIT. Restore from the stack offset
3178 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3179 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3181 static void
3185 {
3191 HOST_WIDE_INT offset;
3196 {
3217 {
3219 rtx mem2;
3227 }
3228 else
3231 }
3232 }
3236 HOST_WIDE_INT offset)
3237 {
3239 }
3243 {
3247 }
3249 bool
3251 {
3255 }
3257 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3259 static sbitmap
3261 {
3267 /* The registers we need saved to the frame. */
3270 {
3275 /* Check that we can access the stack slot of the register with one
3276 direct load with no adjustments needed. */
3279 }
3281 /* Don't mess with the hard frame pointer. */
3287 /* If aarch64_layout_frame has chosen registers to store/restore with
3288 writeback don't interfere with them to avoid having to output explicit
3289 stack adjustment instructions. */
3299 }
3301 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3303 static sbitmap
3305 {
3313 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3322 }
3324 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3325 Nothing to do for aarch64. */
3327 static void
3329 {
3330 }
3332 /* Return the next set bit in BMP from START onwards. Return the total number
3333 of bits in BMP if no set bit is found at or after START. */
3335 static unsigned int
3337 {
3348 }
3350 /* Do the work for aarch64_emit_prologue_components and
3351 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3352 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3353 for these components or the epilogue sequence. That is, it determines
3354 whether we should emit stores or loads and what kind of CFA notes to attach
3355 to the insns. Otherwise the logic for the two sequences is very
3356 similar. */
3358 static void
3360 {
3362 ? HARD_FRAME_POINTER_REGNUM
3370 {
3371 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3372 so DFmode for the vector registers is enough. */
3384 /* No more registers to handle after REGNO.
3385 Emit a single save/restore and exit. */
3387 {
3392 else
3395 }
3398 /* The next register is not of the same class or its offset is not
3399 mergeable with the current one into a pair. */
3404 {
3409 else
3414 }
3416 /* REGNO2 can be saved/restored in a pair with REGNO. */
3428 else
3433 {
3436 }
3437 else
3438 {
3441 }
3444 }
3445 }
3447 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3449 static void
3451 {
3453 }
3455 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3457 static void
3459 {
3461 }
3463 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3465 static void
3467 {
3471 }
3473 /* AArch64 stack frames generated by this compiler look like:
3475 +-------------------------------+
3476 | |
3477 | incoming stack arguments |
3478 | |
3479 +-------------------------------+
3480 | | <-- incoming stack pointer (aligned)
3481 | callee-allocated save area |
3482 | for register varargs |
3483 | |
3484 +-------------------------------+
3485 | local variables | <-- frame_pointer_rtx
3486 | |
3487 +-------------------------------+
3488 | padding0 | \
3489 +-------------------------------+ |
3490 | callee-saved registers | | frame.saved_regs_size
3491 +-------------------------------+ |
3492 | LR' | |
3493 +-------------------------------+ |
3494 | FP' | / <- hard_frame_pointer_rtx (aligned)
3495 +-------------------------------+
3496 | dynamic allocation |
3497 +-------------------------------+
3498 | padding |
3499 +-------------------------------+
3500 | outgoing stack arguments | <-- arg_pointer
3501 | |
3502 +-------------------------------+
3503 | | <-- stack_pointer_rtx (aligned)
3505 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3506 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3507 unchanged. */
3509 /* Generate the prologue instructions for entry into a function.
3510 Establish the stack frame by decreasing the stack pointer with a
3511 properly calculated size and, if necessary, create a frame record
3512 filled with the values of LR and previous frame pointer. The
3513 current FP is also set up if it is in use. */
3515 void
3517 {
3533 {
3535 {
3539 }
3542 }
3550 {
3555 stack_pointer_rtx,
3559 }
3566 }
3568 /* Return TRUE if we can use a simple_return insn.
3570 This function checks whether the callee saved stack is empty, which
3571 means no restore actions are need. The pro_and_epilogue will use
3572 this to check whether shrink-wrapping opt is feasible. */
3574 bool
3576 {
3586 }
3588 /* Generate the epilogue instructions for returning from a function.
3589 This is almost exactly the reverse of the prolog sequence, except
3590 that we need to insert barriers to avoid scheduling loads that read
3591 from a deallocated stack, and we optimize the unwind records by
3592 emitting them all together if possible. */
3593 void
3595 {
3607 /* We need to add memory barrier to prevent read from deallocated stack. */
3611 /* Emit a barrier to prevent loads from a deallocated stack. */
3613 {
3616 }
3618 /* Restore the stack pointer from the frame pointer if it may not
3619 be the same as the stack pointer. */
3621 {
3623 hard_frame_pointer_rtx,
3625 /* If writeback is used when restoring callee-saves, the CFA
3626 is restored on the instruction doing the writeback. */
3628 }
3629 else
3644 {
3645 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3651 }
3656 {
3657 /* Emit delayed restores and reset the CFA to be SP. */
3662 }
3664 /* Stack adjustment for exception handler. */
3666 {
3667 /* We need to unwind the stack by the offset computed by
3668 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3669 to be SP; letting the CFA move during this adjustment
3670 is just as correct as retaining the CFA from the body
3671 of the function. Therefore, do nothing special. */
3673 }
3678 }
3680 /* Return the place to copy the exception unwinding return address to.
3681 This will probably be a stack slot, but could (in theory be the
3682 return register). */
3683 rtx
3685 {
3686 HOST_WIDE_INT fp_offset;
3696 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
3697 result in a store to save LR introduced by builtin_eh_return () being
3698 incorrectly deleted because the alias is not detected.
3699 So in the calculation of the address to copy the exception unwinding
3700 return address to, we note 2 cases.
3701 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
3702 we return a SP-relative location since all the addresses are SP-relative
3703 in this case. This prevents the store from being optimized away.
3704 If the fp_offset is not 0, then the addresses will be FP-relative and
3705 therefore we return a FP-relative location. */
3708 {
3712 else
3715 }
3717 /* If FP is not needed, we calculate the location of LR, which would be
3718 at the top of the saved registers block. */
3722 stack_pointer_rtx,
3723 fp_offset
3726 }
3728 /* Output code to add DELTA to the first argument, and then jump
3729 to FUNCTION. Used for C++ multiple inheritance. */
3730 static void
3732 HOST_WIDE_INT delta,
3733 HOST_WIDE_INT vcall_offset,
3734 tree function)
3735 {
3736 /* The this pointer is always in x0. Note that this differs from
3737 Arm where the this pointer maybe bumped to r1 if r0 is required
3738 to return a pointer to an aggregate. On AArch64 a result value
3739 pointer will be in x8. */
3749 else
3750 {
3759 {
3763 else
3765 }
3769 else
3776 else
3777 {
3779 Pmode);
3781 }
3785 else
3791 }
3793 /* Generate a tail call to the target function. */
3795 {
3798 }
3810 /* Stop pretending to be a post-reload pass. */
3812 }
3814 static bool
3816 {
3821 {
3825 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3826 TLS offsets, not real symbol references. */
3829 }
3831 }
3834 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3835 a left shift of 0 or 12 bits. */
3836 bool
3838 {
3841 );
3842 }
3845 /* Return true if val is an immediate that can be loaded into a
3846 register by a MOVZ instruction. */
3847 static bool
3849 {
3851 {
3855 }
3856 else
3857 {
3858 /* Ignore sign extension. */
3860 }
3863 }
3865 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3868 {
3874 };
3877 /* Return true if val is a valid bitmask immediate. */
3879 bool
3881 {
3885 /* Check for a single sequence of one bits and return quickly if so.
3886 The special cases of all ones and all zeroes returns false. */
3893 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3897 /* Invert if the immediate doesn't start with a zero bit - this means we
3898 only need to search for sequences of one bits. */
3902 /* Find the first set bit and set tmp to val with the first sequence of one
3903 bits removed. Return success if there is a single sequence of ones. */
3910 /* Find the next set bit and compute the difference in bit position. */
3915 /* Check the bit position difference is a power of 2, and that the first
3916 sequence of one bits fits within 'bits' bits. */
3920 /* Check the sequence of one bits is repeated 64/bits times. */
3922 }
3924 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
3925 Assumed precondition: VAL_IN Is not zero. */
3927 unsigned HOST_WIDE_INT
3929 {
3936 }
3938 /* Create constant where bits outside of lowest bit set to highest bit set
3939 are set to 1. */
3941 unsigned HOST_WIDE_INT
3943 {
3945 }
3947 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
3949 bool
3951 {
3961 }
3963 /* Return true if val is an immediate that can be loaded into a
3964 register in a single instruction. */
3965 bool
3967 {
3971 }
3973 static bool
3975 {
3983 {
3987 else
3988 /* Avoid generating a 64-bit relocation in ILP32; leave
3989 to aarch64_expand_mov_immediate to handle it properly. */
3991 }
3994 }
3996 /* Implement TARGET_CASE_VALUES_THRESHOLD.
3997 The expansion for a table switch is quite expensive due to the number
3998 of instructions, the table lookup and hard to predict indirect jump.
3999 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4000 set, otherwise use tables for > 16 cases as a tradeoff between size and
4001 performance. When optimizing for size, use the default setting. */
4003 static unsigned int
4005 {
4006 /* Use the specified limit for the number of cases before using jump
4007 tables at higher optimization levels. */
4011 else
4013 }
4015 /* Return true if register REGNO is a valid index register.
4016 STRICT_P is true if REG_OK_STRICT is in effect. */
4018 bool
4020 {
4022 {
4030 }
4032 }
4034 /* Return true if register REGNO is a valid base register for mode MODE.
4035 STRICT_P is true if REG_OK_STRICT is in effect. */
4037 bool
4039 {
4041 {
4049 }
4051 /* The fake registers will be eliminated to either the stack or
4052 hard frame pointer, both of which are usually valid base registers.
4053 Reload deals with the cases where the eliminated form isn't valid. */
4058 }
4060 /* Return true if X is a valid base register for mode MODE.
4061 STRICT_P is true if REG_OK_STRICT is in effect. */
4063 static bool
4065 {
4070 }
4072 /* Return true if address offset is a valid index. If it is, fill in INFO
4073 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4075 static bool
4078 {
4080 rtx index;
4083 /* (reg:P) */
4086 {
4090 }
4091 /* (sign_extend:DI (reg:SI)) */
4096 {
4101 }
4102 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4109 {
4114 }
4115 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4122 {
4127 }
4128 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4135 {
4143 }
4144 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4145 (const_int 0xffffffff<<shift)) */
4152 {
4158 }
4159 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4166 {
4174 }
4175 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4176 (const_int 0xffffffff<<shift)) */
4183 {
4189 }
4190 /* (mult:P (reg:P) (const_int scale)) */
4195 {
4199 }
4200 /* (ashift:P (reg:P) (const_int shift)) */
4205 {
4209 }
4210 else
4221 {
4226 }
4229 }
4231 /* Return true if MODE is one of the modes for which we
4232 support LDP/STP operations. */
4234 static bool
4236 {
4241 }
4243 /* Return true if REGNO is a virtual pointer register, or an eliminable
4244 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4245 include stack_pointer or hard_frame_pointer. */
4246 static bool
4248 {
4253 }
4255 /* Return true if X is a valid address for machine mode MODE. If it is,
4256 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4257 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4259 static bool
4263 {
4267 /* On BE, we use load/store pair for all large int mode load/stores. */
4269 || (BYTES_BIG_ENDIAN
4273 !load_store_pair_p
4277 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4278 REG addressing. */
4284 {
4300 {
4306 }
4311 {
4318 /* TImode and TFmode values are allowed in both pairs of X
4319 registers and individual Q registers. The available
4320 address modes are:
4321 X,X: 7-bit signed scaled offset
4322 Q: 9-bit signed offset
4323 We conservatively require an offset representable in either mode.
4324 When performing the check for pairs of X registers i.e. LDP/STP
4325 pass down DImode since that is the natural size of the LDP/STP
4326 instruction memory accesses. */
4331 /* A 7bit offset check because OImode will emit a ldp/stp
4332 instruction (only big endian will get here).
4333 For ldp/stp instructions, the offset is scaled for the size of a
4334 single element of the pair. */
4338 /* Three 9/12 bit offsets checks because CImode will emit three
4339 ldr/str instructions (only big endian will get here). */
4346 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4347 instructions (only big endian will get here). */
4356 else
4359 }
4362 {
4363 /* Look for base + (scaled/extended) index register. */
4366 {
4369 }
4372 {
4375 }
4376 }
4397 {
4398 HOST_WIDE_INT offset;
4402 /* TImode and TFmode values are allowed in both pairs of X
4403 registers and individual Q registers. The available
4404 address modes are:
4405 X,X: 7-bit signed scaled offset
4406 Q: 9-bit signed offset
4407 We conservatively require an offset representable in either mode.
4408 */
4416 else
4418 }
4424 /* load literal: pc-relative constant pool entry. Only supported
4425 for SI mode or larger. */
4429 {
4437 }
4446 {
4451 {
4452 /* The symbol and offset must be aligned to the access size. */
4459 {
4463 }
4469 else
4478 }
4479 }
4484 }
4485 }
4487 bool
4489 {
4490 rtx offset;
4494 }
4496 /* Classify the base of symbolic expression X. */
4498 enum aarch64_symbol_type
4500 {
4501 rtx offset;
4505 }
4508 /* Return TRUE if X is a legitimate address for accessing memory in
4509 mode MODE. */
4510 static bool
4512 {
4516 }
4518 /* Return TRUE if X is a legitimate address for accessing memory in
4519 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4520 pair operation. */
4521 bool
4524 {
4528 }
4530 /* Split an out-of-range address displacement into a base and offset.
4531 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4532 to increase opportunities for sharing the base address of different sizes.
4533 For TI/TFmode and unaligned accesses use a 256-byte range. */
4534 static bool
4536 {
4546 }
4548 /* Return TRUE if rtx X is immediate constant 0.0 */
4549 bool
4551 {
4558 }
4560 /* Return the fixed registers used for condition codes. */
4562 static bool
4564 {
4568 }
4570 /* Emit call insn with PAT and do aarch64-specific handling. */
4572 void
4574 {
4580 }
4582 machine_mode
4584 {
4585 /* All floating point compares return CCFP if it is an equality
4586 comparison, and CCFPE otherwise. */
4588 {
4590 {
4611 }
4612 }
4614 /* Equality comparisons of short modes against zero can be performed
4615 using the TST instruction with the appropriate bitmask. */
4621 /* Similarly, comparisons of zero_extends from shorter modes can
4622 be performed using an ANDS with an immediate mask. */
4638 /* A compare with a shifted operand. Because of canonicalization,
4639 the comparison will have to be swapped when we emit the assembly
4640 code. */
4648 /* Similarly for a negated operand, but we can only do this for
4649 equalities. */
4656 /* A test for unsigned overflow. */
4663 /* For everything else, return CCmode. */
4665 }
4667 static int
4670 int
4672 {
4679 }
4681 static int
4683 {
4685 {
4689 {
4703 }
4708 {
4720 }
4725 {
4737 }
4742 {
4748 }
4753 {
4757 }
4762 {
4766 }
4771 }
4774 }
4776 bool
4778 HOST_WIDE_INT minval,
4779 HOST_WIDE_INT maxval)
4780 {
4781 HOST_WIDE_INT firstval;
4798 }
4800 bool
4802 {
4804 }
4807 /* N Z C V. */
4808 #define AARCH64_CC_V 1
4809 #define AARCH64_CC_C (1 << 1)
4810 #define AARCH64_CC_Z (1 << 2)
4811 #define AARCH64_CC_N (1 << 3)
4813 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4815 {
4832 };
4834 static void
4836 {
4838 {
4839 /* An integer or symbol address without a preceding # sign. */
4842 {
4854 {
4857 }
4858 /* Fall through. */
4862 }
4866 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4867 {
4872 {
4875 }
4878 {
4891 }
4892 }
4896 {
4899 /* Print N such that 2^N == X. */
4901 {
4904 }
4907 }
4911 /* Print the number of non-zero bits in X (a const_int). */
4913 {
4916 }
4922 /* Print the higher numbered register of a pair (TImode) of regs. */
4924 {
4927 }
4934 {
4936 /* Print a condition (eq, ne, etc) or its inverse. */
4938 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
4940 {
4944 }
4947 {
4950 }
4957 }
4965 /* Print a scalar FP/SIMD register name. */
4967 {
4968 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4970 }
4978 /* Print the first FP/SIMD register name in a list. */
4980 {
4981 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4983 }
4988 /* Print a scalar FP/SIMD register name + 1. */
4990 {
4991 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4993 }
4998 /* Print bottom 16 bits of integer constant in hex. */
5000 {
5003 }
5009 /* Print a general register name or the zero register (32-bit or
5010 64-bit). */
5013 {
5016 }
5019 {
5022 }
5025 {
5028 }
5030 /* Fall through */
5033 /* Print a normal operand, if it's a general register, then we
5034 assume DImode. */
5036 {
5039 }
5042 {
5063 {
5066 HOST_WIDE_INT_MIN,
5067 HOST_WIDE_INT_MAX));
5069 }
5071 {
5073 }
5074 else
5079 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5080 be getting CONST_DOUBLEs holding integers. */
5083 {
5086 }
5088 {
5089 #define buf_size 20
5097 #undef buf_size
5098 }
5104 }
5112 {
5139 }
5145 {
5180 }
5187 {
5193 }
5198 {
5199 HOST_WIDE_INT cond_code;
5200 /* Print nzcv. */
5203 {
5206 }
5211 }
5217 }
5218 }
5220 static void
5222 {
5227 {
5231 else
5240 else
5249 else
5258 else
5265 {
5292 }
5303 }
5306 }
5308 bool
5310 {
5317 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5318 referencing instruction, but they are constant offsets, not
5319 symbols. */
5325 {
5327 {
5333 }
5336 }
5339 }
5341 /* Implement REGNO_REG_CLASS. */
5343 enum reg_class
5345 {
5360 }
5362 static rtx
5364 {
5365 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5366 where mask is selected by alignment and size of the offset.
5367 We try to pick as large a range for the offset as possible to
5368 maximize the chance of a CSE. However, for aligned addresses
5369 we limit the range to 4k so that structures with different sized
5370 elements are likely to use the same base. We need to be careful
5371 not to split a CONST for some forms of address expression, otherwise
5372 it will generate sub-optimal code. */
5375 {
5381 {
5385 /* Force any scaling into a temp for CSE. */
5389 /* Let the pointer register be in op0. */
5393 /* If the pointer is virtual or frame related, then we know that
5394 virtual register instantiation or register elimination is going
5395 to apply a second constant. We want the two constants folded
5396 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5398 {
5402 }
5404 /* Otherwise, in order to encourage CSE (and thence loop strength
5405 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5409 }
5411 /* Does it look like we'll need a load/store-pair operation? */
5412 HOST_WIDE_INT base_offset;
5417 /* For offsets aren't a multiple of the access size, the limit is
5418 -256...255. */
5420 {
5423 /* BLKmode typically uses LDP of X-registers. */
5426 }
5427 /* Small negative offsets are supported. */
5430 /* Use 12-bit offset by access size. */
5431 else
5435 {
5439 }
5440 }
5443 }
5445 /* Return the reload icode required for a constant pool in mode. */
5446 static enum insn_code
5448 {
5450 {
5486 }
5489 }
5490 static reg_class_t
5492 reg_class_t rclass,
5493 machine_mode mode,
5495 {
5497 /* If we have to disable direct literal pool loads and stores because the
5498 function is too big, then we need a scratch register. */
5503 {
5506 }
5508 /* Without the TARGET_SIMD instructions we cannot move a Q register
5509 to a Q register directly. We need a scratch. */
5513 {
5519 }
5521 /* A TFmode or TImode memory access should be handled via an FP_REGS
5522 because AArch64 has richer addressing modes for LDR/STR instructions
5523 than LDP/STP instructions. */
5532 }
5534 static bool
5536 {
5537 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5538 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5541 {
5553 }
5554 else
5555 {
5556 /* If we decided that we didn't need a leaf frame pointer but then used
5557 LR in the function, then we'll want a frame pointer after all, so
5558 prevent this elimination to ensure a frame pointer is used. */
5560 && flag_omit_leaf_frame_pointer
5563 }
5566 }
5568 HOST_WIDE_INT
5570 {
5574 {
5581 }
5584 {
5588 }
5591 }
5593 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5594 previous frame. */
5596 rtx
5598 {
5602 }
5605 static void
5607 {
5609 {
5612 }
5613 else
5614 {
5617 }
5622 }
5624 static void
5626 {
5630 /* Don't need to copy the trailing D-words, we fill those in below. */
5642 /* XXX We should really define a "clear_cache" pattern and use
5643 gen_clear_cache(). */
5648 ptr_mode);
5649 }
5651 static unsigned char
5653 {
5655 {
5662 return
5674 }
5676 }
5678 static reg_class_t
5680 {
5685 {
5691 }
5693 /* If it's an integer immediate that MOVI can't handle, then
5694 FP_REGS is not an option, so we return NO_REGS instead. */
5699 /* Register eliminiation can result in a request for
5700 SP+constant->FP_REGS. We cannot support such operations which
5701 use SP as source and an FP_REG as destination, so reject out
5702 right now. */
5704 {
5707 /* Look through a possible SUBREG introduced by ILP32. */
5713 POINTER_REGS));
5715 }
5718 }
5720 void
5722 {
5724 }
5726 static void
5728 {
5731 else
5732 {
5740 }
5741 }
5743 static void
5745 {
5748 else
5749 {
5757 }
5758 }
5762 {
5768 {
5769 {
5772 },
5773 {
5776 },
5777 {
5780 },
5781 /* We assume that DImode is only generated when not optimizing and
5782 that we don't really need 64-bit address offsets. That would
5783 imply an object file with 8GB of code in a single function! */
5784 {
5787 }
5788 };
5796 /* Need to implement table size reduction, by chaning the code below. */
5806 }
5809 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5810 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5811 operator. */
5813 int
5815 {
5817 {
5820 {
5824 }
5825 }
5827 }
5829 /* Constant pools are per function only when PC relative
5830 literal loads are true or we are in the large memory
5831 model. */
5835 {
5838 }
5840 static bool
5842 {
5843 /* Fixme:: In an ideal world this would work similar
5844 to the logic in aarch64_select_rtx_section but this
5845 breaks bootstrap in gcc go. For now we workaround
5846 this by returning false here. */
5848 }
5850 /* Select appropriate section for constants depending
5851 on where we place literal pools. */
5855 rtx x,
5857 {
5862 }
5864 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5865 void
5867 HOST_WIDE_INT offset)
5868 {
5869 /* When using per-function literal pools, we must ensure that any code
5870 section is aligned to the minimal instruction length, lest we get
5871 errors from the assembler re "unaligned instructions". */
5874 }
5876 /* Costs. */
5878 /* Helper function for rtx cost calculation. Strip a shift expression
5879 from X. Returns the inner operand if successful, or the original
5880 expression on failure. */
5881 static rtx
5883 {
5886 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5887 we can convert both to ROR during final output. */
5902 }
5904 /* Helper function for rtx cost calculation. Strip an extend
5905 expression from X. Returns the inner operand if successful, or the
5906 original expression on failure. We deal with a number of possible
5907 canonicalization variations here. */
5908 static rtx
5910 {
5913 /* Zero and sign extraction of a widened value. */
5921 /* It can also be represented (for zero-extend) as an AND with an
5922 immediate. */
5931 /* Now handle extended register, as this may also have an optional
5932 left shift by 1..4. */
5946 }
5948 /* Return true iff CODE is a shift supported in combination
5949 with arithmetic instructions. */
5951 static bool
5953 {
5955 }
5957 /* Helper function for rtx cost calculation. Calculate the cost of
5958 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5959 Return the calculated cost of the expression, recursing manually in to
5960 operands where needed. */
5962 static int
5964 {
5980 /* Integer multiply/fma. */
5982 {
5983 /* The multiply will be canonicalized as a shift, cost it as such. */
5987 {
5991 {
5993 {
5995 /* ARITH + shift-by-register. */
5998 /* ARITH + extended register. We don't have a cost field
5999 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6001 else
6002 /* ARITH + shift-by-immediate. */
6004 }
6005 else
6006 /* LSL (immediate). */
6009 }
6010 /* Strip extends as we will have costed them in the case above. */
6017 }
6019 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6020 compound and let the below cases handle it. After all, MNEG is a
6021 special-case alias of MSUB. */
6023 {
6026 }
6028 /* Integer multiplies or FMAs have zero/sign extending variants. */
6033 {
6038 {
6040 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6042 else
6043 /* MUL/SMULL/UMULL. */
6045 }
6048 }
6050 /* This is either an integer multiply or a MADD. In both cases
6051 we want to recurse and cost the operands. */
6056 {
6058 /* MADD/MSUB. */
6060 else
6061 /* MUL. */
6063 }
6066 }
6067 else
6068 {
6070 {
6071 /* Floating-point FMA/FMUL can also support negations of the
6072 operands, unless the rounding mode is upward or downward in
6073 which case FNMUL is different than FMUL with operand negation. */
6077 {
6082 }
6085 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6087 else
6088 /* FMUL/FNMUL. */
6090 }
6095 }
6096 }
6098 static int
6100 machine_mode mode,
6101 addr_space_t as ATTRIBUTE_UNUSED,
6103 {
6111 {
6113 {
6114 /* This is a CONST or SYMBOL ref which will be split
6115 in a different way depending on the code model in use.
6116 Cost it through the generic infrastructure. */
6118 /* Divide through by the cost of one instruction to
6119 bring it to the same units as the address costs. */
6121 /* The cost is then the cost of preparing the address,
6122 followed by an immediate (possibly 0) offset. */
6124 }
6125 else
6126 {
6127 /* This is most likely a jump table from a case
6128 statement. */
6130 }
6131 }
6134 {
6146 else
6165 }
6169 {
6170 /* For the sake of calculating the cost of the shifted register
6171 component, we can treat same sized modes in the same way. */
6173 {
6186 /* We can't tell, or this is a 128-bit vector. */
6190 }
6191 }
6194 }
6196 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6197 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6198 to be taken. */
6200 int
6202 {
6203 /* When optimizing for speed, use the cost of unpredictable branches. */
6209 else
6211 }
6213 /* Return true if the RTX X in mode MODE is a zero or sign extract
6214 usable in an ADD or SUB (extended register) instruction. */
6215 static bool
6217 {
6218 /* Catch add with a sign extract.
6219 This is add_<optab><mode>_multp2. */
6222 {
6233 op1))
6234 {
6236 }
6237 }
6238 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6239 No shift. */
6245 }
6247 static bool
6249 {
6251 {
6263 }
6264 }
6266 /* Return true iff X is an rtx that will match an extr instruction
6267 i.e. as described in the *extr<mode>5_insn family of patterns.
6268 OP0 and OP1 will be set to the operands of the shifts involved
6269 on success and will be NULL_RTX otherwise. */
6271 static bool
6273 {
6288 {
6289 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6301 {
6305 }
6306 }
6309 }
6311 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6312 storing it in *COST. Result is true if the total cost of the operation
6313 has now been calculated. */
6314 static bool
6316 {
6317 rtx inner;
6318 rtx comparator;
6322 {
6326 }
6327 else
6328 {
6332 }
6335 {
6336 /* Conditional branch. */
6339 else
6340 {
6342 {
6344 {
6345 /* TBZ/TBNZ/CBZ/CBNZ. */
6347 /* TBZ/TBNZ. */
6350 else
6351 /* CBZ/CBNZ. */
6355 }
6356 }
6358 {
6359 /* TBZ/TBNZ. */
6362 }
6363 }
6364 }
6366 {
6367 /* CCMP. */
6369 {
6370 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6374 {
6381 else
6383 }
6385 }
6387 /* It's a conditional operation based on the status flags,
6388 so it must be some flavor of CSEL. */
6390 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6396 {
6397 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6400 }
6405 }
6407 /* We don't know what this is, cost all operands. */
6409 }
6411 /* Check whether X is a bitfield operation of the form shift + extend that
6412 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6413 operand to which the bitfield operation is applied. Otherwise return
6414 NULL_RTX. */
6416 static rtx
6418 {
6432 {
6450 }
6453 }
6455 /* Return true if the mask and a shift amount from an RTX of the form
6456 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6457 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6459 bool
6461 {
6466 }
6468 /* Calculate the cost of calculating X, storing it in *COST. Result
6469 is true if the total cost of the operation has now been calculated. */
6470 static bool
6473 {
6479 /* By default, assume that everything has equivalent cost to the
6480 cheapest instruction. Any additional costs are applied as a delta
6481 above this default. */
6485 {
6487 /* The cost depends entirely on the operands to SET. */
6493 {
6496 {
6510 }
6519 /* Fall through. */
6521 /* The cost is one per vector-register copied. */
6523 {
6527 }
6528 /* const0_rtx is in general free, but we will use an
6529 instruction to set a register to 0. */
6531 {
6532 /* The cost is 1 per register copied. */
6536 }
6537 else
6538 /* Cost is just the cost of the RHS of the set. */
6544 /* Bit-field insertion. Strip any redundant widening of
6545 the RHS to meet the width of the target. */
6556 {
6557 /* MOV immediate is assumed to always be cheap. */
6559 }
6560 else
6561 {
6562 /* BFM. */
6566 }
6571 /* We can't make sense of this, assume default cost. */
6574 }
6578 /* If an instruction can incorporate a constant within the
6579 instruction, the instruction's expression avoids calling
6580 rtx_cost() on the constant. If rtx_cost() is called on a
6581 constant, then it is usually because the constant must be
6582 moved into a register by one or more instructions.
6584 The exception is constant 0, which can be expressed
6585 as XZR/WZR and is therefore free. The exception to this is
6586 if we have (set (reg) (const0_rtx)) in which case we must cost
6587 the move. However, we can catch that when we cost the SET, so
6588 we don't need to consider that here. */
6591 else
6592 {
6593 /* To an approximation, building any other constant is
6594 proportionally expensive to the number of instructions
6595 required to build that constant. This is true whether we
6596 are compiling for SPEED or otherwise. */
6599 }
6604 {
6605 /* mov[df,sf]_aarch64. */
6607 /* FMOV (scalar immediate). */
6610 {
6611 /* This will be a load from memory. */
6614 else
6616 }
6617 else
6618 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6619 or MOV v0.s[0], wzr - neither of which are modeled by the
6620 cost tables. Just use the default cost. */
6621 {
6622 }
6623 }
6629 {
6630 /* For loads we want the base cost of a load, plus an
6631 approximation for the additional cost of the addressing
6632 mode. */
6646 }
6654 {
6656 {
6657 /* FNEG. */
6659 }
6661 }
6664 {
6667 {
6668 /* CSETM. */
6671 }
6673 /* Cost this as SUB wzr, X. */
6677 }
6680 {
6681 /* Support (neg(fma...)) as a single instruction only if
6682 sign of zeros is unimportant. This matches the decision
6683 making in aarch64.md. */
6685 {
6686 /* FNMADD. */
6689 }
6691 {
6692 /* FNMUL. */
6695 }
6697 /* FNEG. */
6700 }
6707 {
6710 else
6712 }
6722 {
6726 }
6729 {
6730 /* TODO: A write to the CC flags possibly costs extra, this
6731 needs encoding in the cost tables. */
6734 /* ANDS. */
6736 {
6739 }
6742 {
6743 /* ADDS (and CMN alias). */
6746 }
6749 {
6750 /* SUBS. */
6753 }
6758 {
6759 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6760 Handle it here directly rather than going to cost_logic
6761 since we know the immediate generated for the TST is valid
6762 so we can avoid creating an intermediate rtx for it only
6763 for costing purposes. */
6770 }
6773 {
6774 /* CMN. */
6781 }
6783 /* CMP.
6785 Compare can freely swap the order of operands, and
6786 canonicalization puts the more complex operation first.
6787 But the integer MINUS logic expects the shift/extend
6788 operation in op1. */
6791 {
6794 }
6796 }
6799 {
6800 /* FCMP. */
6805 {
6807 /* FCMP supports constant 0.0 for no extra cost. */
6809 }
6811 }
6814 {
6815 /* Vector compare. */
6820 {
6821 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6822 cost. */
6824 }
6826 }
6830 {
6834 cost_minus:
6837 /* Detect valid immediates. */
6843 {
6845 /* SUB(S) (immediate). */
6848 }
6850 /* Look for SUB (extended register). */
6852 {
6860 }
6864 /* Cost this as an FMA-alike operation. */
6868 {
6871 speed);
6873 }
6878 {
6880 {
6881 /* Vector SUB. */
6883 }
6885 {
6886 /* SUB(S). */
6888 }
6890 {
6891 /* FSUB. */
6893 }
6894 }
6896 }
6899 {
6900 rtx new_op0;
6905 cost_plus:
6908 {
6909 /* CSINC. */
6913 }
6918 {
6922 /* ADD (immediate). */
6925 }
6929 /* Look for ADD (extended register). */
6931 {
6939 }
6941 /* Strip any extend, leave shifts behind as we will
6942 cost them through mult_cost. */
6947 {
6949 speed);
6951 }
6956 {
6958 {
6959 /* Vector ADD. */
6961 }
6963 {
6964 /* ADD. */
6966 }
6968 {
6969 /* FADD. */
6971 }
6972 }
6974 }
6980 {
6983 else
6985 }
6990 {
6994 {
6997 else
6999 }
7001 }
7004 {
7011 }
7012 /* Fall through. */
7015 cost_logic:
7020 {
7024 }
7032 {
7033 /* This is a UBFM/SBFM. */
7038 }
7041 {
7043 {
7044 /* We have a mask + shift version of a UBFIZ
7045 i.e. the *andim_ashift<mode>_bfiz pattern. */
7049 {
7056 }
7058 {
7059 /* We possibly get the immediate for free, this is not
7060 modelled. */
7066 }
7067 }
7068 else
7069 {
7072 /* Handle ORN, EON, or BIC. */
7078 /* If we had a shift on op0 then this is a logical-shift-
7079 by-register/immediate operation. Otherwise, this is just
7080 a logical operation. */
7082 {
7084 {
7085 /* Shift by immediate. */
7088 else
7090 }
7091 else
7093 }
7095 /* In both cases we want to cost both operands. */
7100 }
7101 }
7109 {
7110 /* Vector NOT. */
7113 }
7115 /* MVN-shifted-reg. */
7117 {
7124 }
7125 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7126 Handle the second form here taking care that 'a' in the above can
7127 be a shift. */
7129 {
7138 {
7141 else
7143 }
7146 }
7147 /* MVN. */
7156 /* If a value is written in SI mode, then zero extended to DI
7157 mode, the operation will in general be free as a write to
7158 a 'w' register implicitly zeroes the upper bits of an 'x'
7159 register. However, if this is
7161 (set (reg) (zero_extend (reg)))
7163 we must cost the explicit register move. */
7167 {
7170 /* If OP_COST is non-zero, then the cost of the zero extend
7171 is effectively the cost of the inner operation. Otherwise
7172 we have a MOV instruction and we take the cost from the MOV
7173 itself. This is true independently of whether we are
7174 optimizing for space or time. */
7179 }
7181 {
7182 /* All loads can zero extend to any size for free. */
7185 }
7189 {
7194 }
7197 {
7199 {
7200 /* UMOV. */
7202 }
7203 else
7204 {
7205 /* We generate an AND instead of UXTB/UXTH. */
7207 }
7208 }
7213 {
7214 /* LDRSH. */
7216 {
7223 }
7225 }
7229 {
7234 }
7237 {
7240 else
7242 }
7250 {
7252 {
7254 {
7255 /* Vector shift (immediate). */
7257 }
7258 else
7259 {
7260 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7261 aliases. */
7263 }
7264 }
7266 /* We can incorporate zero/sign extend for free. */
7273 }
7274 else
7275 {
7277 {
7279 {
7280 /* Vector shift (register). */
7282 }
7283 else
7284 {
7285 /* LSLV. */
7287 }
7288 }
7290 }
7300 {
7301 /* ASR (immediate) and friends. */
7303 {
7306 else
7308 }
7312 }
7313 else
7314 {
7316 /* ASR (register) and friends. */
7318 {
7321 else
7323 }
7325 }
7331 {
7332 /* LDR. */
7335 }
7338 {
7339 /* ADRP, followed by ADD. */
7343 }
7346 {
7347 /* ADR. */
7350 }
7353 {
7354 /* One extra load instruction, after accessing the GOT. */
7358 }
7363 /* ADRP/ADD (immediate). */
7370 /* UBFX/SBFX. */
7372 {
7375 else
7377 }
7379 /* We can trust that the immediates used will be correct (there
7380 are no by-register forms), so we need only cost op0. */
7386 /* aarch64_rtx_mult_cost always handles recursion to its
7387 operands. */
7391 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7392 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7393 an unconditional negate. This case should only ever be reached through
7394 the set_smod_pow2_cheap check in expmed.c. */
7398 {
7399 /* We expand to 4 instructions. Reset the baseline. */
7407 }
7409 /* Fall-through. */
7412 {
7424 }
7431 {
7435 /* There is no integer SQRT, so only DIV and UDIV can get
7436 here. */
7438 else
7440 }
7466 {
7469 else
7471 }
7473 /* FMSUB, FNMADD, and FNMSUB are free. */
7480 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7481 and the by-element operand as operand 0. */
7485 /* Catch vector-by-element operations. The by-element operand can
7486 either be (vec_duplicate (vec_select (x))) or just
7487 (vec_select (x)), depending on whether we are multiplying by
7488 a vector or a scalar.
7490 Canonicalization is not very good in these cases, FMA4 will put the
7491 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7502 /* If the remaining parameters are not registers,
7503 get the cost to put them into registers. */
7517 {
7519 {
7520 /*Vector truncate. */
7522 }
7523 else
7525 }
7530 {
7532 {
7533 /*Vector conversion. */
7535 }
7536 else
7538 }
7544 /* Strip the rounding part. They will all be implemented
7545 by the fcvt* family of instructions anyway. */
7547 {
7556 }
7559 {
7562 else
7564 }
7566 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7567 fixed-point fcvt. */
7572 {
7576 }
7583 {
7584 /* ABS (vector). */
7587 }
7589 {
7592 /* FABD, which is analogous to FADD. */
7594 {
7601 }
7602 /* Simple FABS is analogous to FNEG. */
7605 }
7606 else
7607 {
7608 /* Integer ABS will either be split to
7609 two arithmetic instructions, or will be an ABS
7610 (scalar), which we don't model. */
7614 }
7620 {
7623 else
7624 {
7625 /* FMAXNM/FMINNM/FMAX/FMIN.
7626 TODO: This may not be accurate for all implementations, but
7627 we do not model this in the cost tables. */
7629 }
7630 }
7634 /* The floating point round to integer frint* instructions. */
7636 {
7641 }
7644 {
7649 }
7654 /* Decompose <su>muldi3_highpart. */
7656 mode == DImode
7657 /* (lshiftrt:TI */
7660 /* (mult:TI */
7662 /* (ANY_EXTEND:TI (reg:DI))
7663 (ANY_EXTEND:TI (reg:DI))) */
7670 /* (const_int 64) */
7673 {
7674 /* UMULH/SMULH. */
7682 }
7684 /* Fall through. */
7687 }
7695 }
7697 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7698 calculated for X. This cost is stored in *COST. Returns true
7699 if the total cost of X was calculated. */
7700 static bool
7703 {
7708 {
7713 }
7716 }
7718 static int
7721 {
7727 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7734 /* Moving between GPR and stack cost is the same as GP2GP. */
7739 /* To/From the stack register, we move via the gprs. */
7745 {
7746 /* 128-bit operations on general registers require 2 instructions. */
7754 /* When AdvSIMD instructions are disabled it is not possible to move
7755 a 128-bit value directly between Q registers. This is handled in
7756 secondary reload. A general register is used as a scratch to move
7757 the upper DI value and the lower DI value is moved directly,
7758 hence the cost is the sum of three moves. */
7763 }
7773 }
7775 static int
7777 reg_class_t rclass ATTRIBUTE_UNUSED,
7779 {
7781 }
7783 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7784 to optimize 1.0/sqrt. */
7786 static bool
7788 {
7790 && flag_unsafe_math_optimizations
7794 }
7796 /* Function to decide when to use the approximate reciprocal square root
7797 builtin. */
7799 static tree
7801 {
7807 }
7811 /* Select reciprocal square root initial estimate insn depending on machine
7812 mode. */
7814 static rsqrte_type
7816 {
7818 {
7825 }
7826 }
7830 /* Select reciprocal square root series step insn depending on machine mode. */
7832 static rsqrts_type
7834 {
7836 {
7843 }
7844 }
7846 /* Emit instruction sequence to compute either the approximate square root
7847 or its approximate reciprocal, depending on the flag RECP, and return
7848 whether the sequence was emitted or not. */
7850 bool
7852 {
7858 machine_mode mmsk = mode_for_vector
7862 && (flag_mlow_precision_sqrt
7866 && (flag_mrecip_low_precision_sqrt
7871 || flag_trapping_math
7872 || !flag_unsafe_math_optimizations
7879 /* When calculating the approximate square root, compare the argument with
7880 0.0 and create a mask. */
7884 /* Estimate the approximate reciprocal square root. */
7888 /* Iterate over the series twice for SF and thrice for DF. */
7891 /* Optionally iterate over the series once less for faster performance
7892 while sacrificing the accuracy. */
7895 iterations--;
7897 /* Iterate over the series to calculate the approximate reciprocal square
7898 root. */
7901 {
7909 }
7912 {
7913 /* Qualify the approximate reciprocal square root when the argument is
7914 0.0 by squashing the intermediary result to 0.0. */
7920 /* Calculate the approximate square root. */
7922 }
7924 /* Finalize the approximation. */
7928 }
7932 /* Select reciprocal initial estimate insn depending on machine mode. */
7934 static recpe_type
7936 {
7938 {
7945 }
7946 }
7950 /* Select reciprocal series step insn depending on machine mode. */
7952 static recps_type
7954 {
7956 {
7963 }
7964 }
7966 /* Emit the instruction sequence to compute the approximation for the division
7967 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
7969 bool
7971 {
7982 || flag_trapping_math
7983 || !flag_unsafe_math_optimizations
7988 /* Estimate the approximate reciprocal. */
7992 /* Iterate over the series twice for SF and thrice for DF. */
7995 /* Optionally iterate over the series once less for faster performance,
7996 while sacrificing the accuracy. */
7998 iterations--;
8000 /* Iterate over the series to calculate the approximate reciprocal. */
8003 {
8008 }
8011 {
8012 /* As the approximate reciprocal of DEN is already calculated, only
8013 calculate the approximate division when NUM is not 1.0. */
8016 }
8018 /* Finalize the approximation. */
8021 }
8023 /* Return the number of instructions that can be issued per cycle. */
8024 static int
8026 {
8028 }
8030 static int
8032 {
8036 }
8039 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8040 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8041 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8043 static int
8046 {
8048 }
8051 /* Vectorizer cost model target hooks. */
8053 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8054 static int
8056 tree vectype,
8058 {
8062 {
8111 }
8112 }
8114 /* Implement targetm.vectorize.add_stmt_cost. */
8115 static unsigned
8119 {
8124 {
8129 /* Statements in an inner loop relative to the loop being
8130 vectorized are weighted more heavily. The value here is
8131 arbitrary and could potentially be improved with analysis. */
8137 }
8140 }
8144 /* Parse the TO_PARSE string and put the architecture struct that it
8145 selects into RES and the architectural features into ISA_FLAGS.
8146 Return an aarch64_parse_opt_result describing the parse result.
8147 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8149 static enum aarch64_parse_opt_result
8152 {
8164 else
8171 /* Loop through the list of supported ARCHes to find a match. */
8173 {
8175 {
8179 {
8180 /* TO_PARSE string contains at least one extension. */
8181 enum aarch64_parse_opt_result ext_res
8186 }
8187 /* Extension parsing was successful. Confirm the result
8188 arch and ISA flags. */
8192 }
8193 }
8195 /* ARCH name not found in list. */
8197 }
8199 /* Parse the TO_PARSE string and put the result tuning in RES and the
8200 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8201 describing the parse result. If there is an error parsing, RES and
8202 ISA_FLAGS are left unchanged. */
8204 static enum aarch64_parse_opt_result
8207 {
8219 else
8226 /* Loop through the list of supported CPUs to find a match. */
8228 {
8230 {
8235 {
8236 /* TO_PARSE string contains at least one extension. */
8237 enum aarch64_parse_opt_result ext_res
8242 }
8243 /* Extension parsing was successfull. Confirm the result
8244 cpu and ISA flags. */
8248 }
8249 }
8251 /* CPU name not found in list. */
8253 }
8255 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8256 Return an aarch64_parse_opt_result describing the parse result.
8257 If the parsing fails the RES does not change. */
8259 static enum aarch64_parse_opt_result
8261 {
8267 /* Loop through the list of supported CPUs to find a match. */
8269 {
8271 {
8274 }
8275 }
8277 /* CPU name not found in list. */
8279 }
8281 /* Parse TOKEN, which has length LENGTH to see if it is an option
8282 described in FLAG. If it is, return the index bit for that fusion type.
8283 If not, error (printing OPTION_NAME) and return zero. */
8285 static unsigned int
8290 {
8292 {
8296 }
8300 }
8302 /* Parse OPTION which is a comma-separated list of flags to enable.
8303 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8304 default state we inherit from the CPU tuning structures. OPTION_NAME
8305 gives the top-level option we are parsing in the -moverride string,
8306 for use in error messages. */
8308 static unsigned int
8313 {
8320 {
8323 token_length,
8324 flags,
8325 option_name);
8326 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8327 in the token stream, reset the supported operations. So:
8329 adrp+add.cmp+branch.none.adrp+add
8331 would have the result of turning on only adrp+add fusion. */
8337 }
8339 /* We ended with a comma, print something. */
8341 {
8344 }
8346 /* We still have one more token to parse. */
8349 token_length,
8350 flags,
8351 option_name);
8357 }
8359 /* Support for overriding instruction fusion. */
8361 static void
8364 {
8366 aarch64_fusible_pairs,
8369 }
8371 /* Support for overriding other tuning flags. */
8373 static void
8376 {
8377 tune->extra_tuning_flags
8379 aarch64_tuning_flags,
8382 }
8384 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8385 we understand. If it is, extract the option string and handoff to
8386 the appropriate function. */
8388 void
8392 {
8398 {
8401 }
8403 /* Get the length of the option name. */
8405 /* Skip the '=' to get to the option string. */
8406 option_part++;
8409 {
8411 {
8414 }
8415 }
8419 }
8421 /* A checking mechanism for the implementation of the tls size. */
8423 static void
8425 {
8430 {
8432 /* Both the default and maximum TLS size allowed under tiny is 1M which
8433 needs two instructions to address, so we clamp the size to 24. */
8438 /* The maximum TLS size allowed under small is 4G. */
8443 /* The maximum TLS size allowed under large is 16E.
8444 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8450 }
8453 }
8455 /* Parse STRING looking for options in the format:
8456 string :: option:string
8457 option :: name=substring
8458 name :: {a-z}
8459 substring :: defined by option. */
8461 static void
8464 {
8475 {
8477 /* Make this substring look like a string. */
8481 }
8483 /* One last option to parse. */
8486 }
8489 static void
8491 {
8492 /* The logic here is that if we are disabling all frame pointer generation
8493 then we do not need to disable leaf frame pointer generation as a
8494 separate operation. But if we are *only* disabling leaf frame pointer
8495 generation then we set flag_omit_frame_pointer to true, but in
8496 aarch64_frame_pointer_required we return false only for leaf functions.
8498 PR 70044: We have to be careful about being called multiple times for the
8499 same function. Once we have decided to set flag_omit_frame_pointer just
8500 so that we can omit leaf frame pointers, we must then not interpret a
8501 second call as meaning that all frame pointer generation should be
8502 omitted. We do this by setting flag_omit_frame_pointer to a special,
8503 non-zero value. */
8512 /* If not optimizing for size, set the default
8513 alignment to what the target wants. */
8515 {
8522 }
8524 /* We default to no pc-relative literal loads. */
8528 /* If -mpc-relative-literal-loads is set on the command line, this
8529 implies that the user asked for PC relative literal loads. */
8533 /* This is PR70113. When building the Linux kernel with
8534 CONFIG_ARM64_ERRATUM_843419, support for relocations
8535 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8536 removed from the kernel to avoid loading objects with possibly
8537 offending sequences. Without -mpc-relative-literal-loads we would
8538 generate such relocations, preventing the kernel build from
8539 succeeding. */
8544 /* In the tiny memory model it makes no sense to disallow PC relative
8545 literal pool loads. */
8550 /* When enabling the lower precision Newton series for the square root, also
8551 enable it for the reciprocal square root, since the latter is an
8552 intermediary step for the former. */
8555 }
8557 /* 'Unpack' up the internal tuning structs and update the options
8558 in OPTS. The caller must have set up selected_tune and selected_arch
8559 as all the other target-specific codegen decisions are
8560 derived from them. */
8562 void
8564 {
8567 /* Make a copy of the tuning parameters attached to the core, which
8568 we may later overwrite. */
8576 /* This target defaults to strict volatile bitfields. */
8585 {
8597 }
8599 /* We don't mind passing in global_options_set here as we don't use
8600 the *options_set structs anyway. */
8602 queue_depth,
8606 /* Set the L1 cache line size. */
8614 }
8616 /* Print a hint with a suggestion for a core or architecture name that
8617 most closely resembles what the user passed in STR. ARCH is true if
8618 the user is asking for an architecture name. ARCH is false if the user
8619 is asking for a core name. */
8621 static void
8623 {
8634 }
8636 /* Print a hint with a suggestion for a core name that most closely resembles
8637 what the user passed in STR. */
8641 {
8643 }
8645 /* Print a hint with a suggestion for an architecture name that most closely
8646 resembles what the user passed in STR. */
8650 {
8652 }
8654 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8655 specified in STR and throw errors if appropriate. Put the results if
8656 they are valid in RES and ISA_FLAGS. Return whether the option is
8657 valid. */
8659 static bool
8662 {
8663 enum aarch64_parse_opt_result parse_res
8670 {
8683 }
8686 }
8688 /* Validate a command-line -march option. Parse the arch and extensions
8689 (if any) specified in STR and throw errors if appropriate. Put the
8690 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8691 option is valid. */
8693 static bool
8696 {
8697 enum aarch64_parse_opt_result parse_res
8704 {
8717 }
8720 }
8722 /* Validate a command-line -mtune option. Parse the cpu
8723 specified in STR and throw errors if appropriate. Put the
8724 result, if it is valid, in RES. Return whether the option is
8725 valid. */
8727 static bool
8729 {
8730 enum aarch64_parse_opt_result parse_res
8737 {
8747 }
8749 }
8751 /* Return the CPU corresponding to the enum CPU.
8752 If it doesn't specify a cpu, return the default. */
8756 {
8760 /* The & 0x3f is to extract the bottom 6 bits that encode the
8761 default cpu as selected by the --with-cpu GCC configure option
8762 in config.gcc.
8763 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8764 flags mechanism should be reworked to make it more sane. */
8766 }
8768 /* Return the architecture corresponding to the enum ARCH.
8769 If it doesn't specify a valid architecture, return the default. */
8773 {
8780 }
8782 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8783 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8784 tuning structs. In particular it must set selected_tune and
8785 aarch64_isa_flags that define the available ISA features and tuning
8786 decisions. It must also set selected_arch as this will be used to
8787 output the .arch asm tags for each function. */
8789 static void
8791 {
8804 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8805 If either of -march or -mtune is given, they override their
8806 respective component of -mcpu. */
8818 /* If the user did not specify a processor, choose the default
8819 one for them. This will be the CPU set during configuration using
8820 --with-cpu, otherwise it is "generic". */
8822 {
8824 {
8828 }
8829 else
8830 {
8831 /* Get default configure-time CPU. */
8834 }
8838 }
8839 /* If both -mcpu and -march are specified check that they are architecturally
8840 compatible, warn if they're not and prefer the -march ISA flags. */
8842 {
8844 {
8848 }
8853 }
8854 else
8855 {
8856 /* -mcpu but no -march. */
8863 }
8865 /* Set the arch as well as we will need it when outputing
8866 the .arch directive in assembly. */
8868 {
8871 }
8876 #ifndef HAVE_AS_MABI_OPTION
8877 /* The compiler may have been configured with 2.23.* binutils, which does
8878 not have support for ILP32. */
8881 #endif
8883 /* Make sure we properly set up the explicit options. */
8894 /* Save these options as the default ones in case we push and pop them later
8895 while processing functions with potential target attributes. */
8896 target_option_default_node = target_option_current_node
8898 }
8900 /* Implement targetm.override_options_after_change. */
8902 static void
8904 {
8906 }
8910 {
8914 }
8916 void
8918 {
8920 }
8922 /* A checking mechanism for the implementation of the various code models. */
8923 static void
8925 {
8927 {
8929 {
8934 #ifdef HAVE_AS_SMALL_PIC_RELOCS
8936 ? AARCH64_CMODEL_SMALL_PIC
8938 #else
8940 #endif
8948 }
8949 }
8950 else
8952 }
8954 /* Implement TARGET_OPTION_SAVE. */
8956 static void
8958 {
8960 }
8962 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
8963 using the information saved in PTR. */
8965 static void
8967 {
8975 }
8977 /* Implement TARGET_OPTION_PRINT. */
8979 static void
8981 {
8992 }
8996 void
8998 {
9000 }
9002 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9003 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9004 make sure optab availability predicates are recomputed when necessary. */
9006 void
9008 {
9013 else
9015 }
9017 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9018 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9019 of the function, if such exists. This function may be called multiple
9020 times on a single function so use aarch64_previous_fndecl to avoid
9021 setting up identical state. */
9023 static void
9025 {
9029 tree old_tree = (aarch64_previous_fndecl
9035 /* If current function has no attributes but the previous one did,
9036 use the default node. */
9040 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9041 the default have been handled by aarch64_save_restore_target_globals from
9042 aarch64_pragma_target_parse. */
9048 /* First set the target options. */
9052 }
9054 /* Enum describing the various ways we can handle attributes.
9055 In many cases we can reuse the generic option handling machinery. */
9057 enum aarch64_attr_opt_type
9058 {
9062 aarch64_attr_custom /* Attribute requires a custom handling function. */
9063 };
9065 /* All the information needed to handle a target attribute.
9066 NAME is the name of the attribute.
9067 ATTR_TYPE specifies the type of behavior of the attribute as described
9068 in the definition of enum aarch64_attr_opt_type.
9069 ALLOW_NEG is true if the attribute supports a "no-" form.
9070 HANDLER is the function that takes the attribute string and whether
9071 it is a pragma or attribute and handles the option. It is needed only
9072 when the ATTR_TYPE is aarch64_attr_custom.
9073 OPT_NUM is the enum specifying the option that the attribute modifies.
9074 This is needed for attributes that mirror the behavior of a command-line
9075 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9076 aarch64_attr_enum. */
9078 struct aarch64_attribute_info
9079 {
9085 };
9087 /* Handle the ARCH_STR argument to the arch= target attribute.
9088 PRAGMA_OR_ATTR is used in potential error messages. */
9090 static bool
9092 {
9094 enum aarch64_parse_opt_result parse_res
9098 {
9103 }
9106 {
9120 }
9123 }
9125 /* Handle the argument CPU_STR to the cpu= target attribute.
9126 PRAGMA_OR_ATTR is used in potential error messages. */
9128 static bool
9130 {
9132 enum aarch64_parse_opt_result parse_res
9136 {
9144 }
9147 {
9161 }
9164 }
9166 /* Handle the argument STR to the tune= target attribute.
9167 PRAGMA_OR_ATTR is used in potential error messages. */
9169 static bool
9171 {
9173 enum aarch64_parse_opt_result parse_res
9177 {
9182 }
9185 {
9192 }
9195 }
9197 /* Parse an architecture extensions target attribute string specified in STR.
9198 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9199 if successful. Update aarch64_isa_flags to reflect the ISA features
9200 modified.
9201 PRAGMA_OR_ATTR is used in potential error messages. */
9203 static bool
9205 {
9209 /* We allow "+nothing" in the beginning to clear out all architectural
9210 features if the user wants to handpick specific features. */
9212 {
9215 }
9220 {
9223 }
9226 {
9239 }
9242 }
9244 /* The target attributes that we support. On top of these we also support just
9245 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9246 handled explicitly in aarch64_process_one_target_attr. */
9249 {
9251 OPT_mgeneral_regs_only },
9253 OPT_mfix_cortex_a53_835769 },
9255 OPT_mfix_cortex_a53_843419 },
9259 OPT_momit_leaf_frame_pointer },
9262 OPT_march_ },
9265 OPT_mtune_ },
9267 };
9269 /* Parse ARG_STR which contains the definition of one target attribute.
9270 Show appropriate errors if any or return true if the attribute is valid.
9271 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9272 we're processing a target attribute or pragma. */
9274 static bool
9276 {
9282 {
9285 }
9290 /* Skip leading whitespace. */
9292 str_to_check++;
9294 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9295 It is easier to detect and handle it explicitly here rather than going
9296 through the machinery for the rest of the target attributes in this
9297 function. */
9302 {
9305 }
9308 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9309 and point ARG to "foo". */
9311 {
9313 arg++;
9314 }
9318 {
9319 /* If the names don't match up, or the user has given an argument
9320 to an attribute that doesn't accept one, or didn't give an argument
9321 to an attribute that expects one, fail to match. */
9330 {
9334 }
9336 /* If the name matches but the attribute does not allow "no-" versions
9337 then we can't match. */
9339 {
9343 }
9346 {
9347 /* Has a custom handler registered.
9348 For example, cpu=, arch=, tune=. */
9355 /* Either set or unset a boolean option. */
9357 {
9365 }
9366 /* Set or unset a bit in the target_flags. aarch64_handle_option
9367 should know what mask to apply given the option number. */
9369 {
9371 /* We only need to specify the option number.
9372 aarch64_handle_option will know which mask to apply. */
9378 }
9379 /* Use the option setting machinery to set an option to an enum. */
9381 {
9388 {
9391 global_dc);
9392 }
9393 else
9394 {
9397 }
9399 }
9402 }
9403 }
9405 /* If we reached here we either have found an attribute and validated
9406 it or didn't match any. If we matched an attribute but its arguments
9407 were malformed we will have returned false already. */
9409 }
9411 /* Count how many times the character C appears in
9412 NULL-terminated string STR. */
9414 static unsigned int
9416 {
9419 {
9421 res++;
9423 str++;
9424 }
9427 }
9429 /* Parse the tree in ARGS that contains the target attribute information
9430 and update the global target options space. PRAGMA_OR_ATTR is a string
9431 to be used in error messages, specifying whether this is processing
9432 a target attribute or a target pragma. */
9434 bool
9436 {
9438 {
9439 do
9440 {
9443 {
9446 }
9451 }
9452 /* We expect to find a string to parse. */
9460 {
9463 }
9465 /* Used to catch empty spaces between commas i.e.
9466 attribute ((target ("attr1,,attr2"))). */
9469 /* Handle multiple target attributes separated by ','. */
9474 {
9475 num_attrs++;
9477 {
9480 }
9483 }
9486 {
9490 }
9493 }
9495 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9496 process attribute ((target ("..."))). */
9498 static bool
9500 {
9503 tree old_optimize;
9507 /* If what we're processing is the current pragma string then the
9508 target option node is already stored in target_option_current_node
9509 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9510 having to re-parse the string. This is especially useful to keep
9511 arm_neon.h compile times down since that header contains a lot
9512 of intrinsics enclosed in pragmas. */
9514 {
9517 }
9523 /* If the function changed the optimization levels as well as setting
9524 target options, start with the optimizations specified. */
9529 /* Save the current target options to restore at the end. */
9532 /* If fndecl already has some target attributes applied to it, unpack
9533 them so that we add this attribute on top of them, rather than
9534 overwriting them. */
9536 {
9542 }
9543 else
9550 /* Set up any additional state. */
9552 {
9554 /* Initialize SIMD builtins if we haven't already.
9555 Set current_target_pragma to NULL for the duration so that
9556 the builtin initialization code doesn't try to tag the functions
9557 being built with the attributes specified by any current pragma, thus
9558 going into an infinite recursion. */
9560 {
9565 }
9567 }
9568 else
9574 {
9579 }
9587 }
9589 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9590 tri-bool options (yes, no, don't care) and the default value is
9591 DEF, determine whether to reject inlining. */
9593 static bool
9596 {
9597 /* If the callee doesn't care, always allow inlining. */
9601 /* If the caller doesn't care, always allow inlining. */
9605 /* Otherwise, allow inlining if either the callee and caller values
9606 agree, or if the callee is using the default value. */
9608 }
9610 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9611 to inline CALLEE into CALLER based on target-specific info.
9612 Make sure that the caller and callee have compatible architectural
9613 features. Then go through the other possible target attributes
9614 and see if they can block inlining. Try not to reject always_inline
9615 callees unless they are incompatible architecturally. */
9617 static bool
9619 {
9623 /* If callee has no option attributes, then it is ok to inline. */
9634 /* Callee's ISA flags should be a subset of the caller's. */
9639 /* Allow non-strict aligned functions inlining into strict
9640 aligned ones. */
9650 /* If the architectural features match up and the callee is always_inline
9651 then the other attributes don't matter. */
9663 /* Honour explicit requests to workaround errata. */
9676 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9677 caller and calle and they don't match up, reject inlining. */
9684 /* If the callee has specific tuning overrides, respect them. */
9689 /* If the user specified tuning override strings for the
9690 caller and callee and they don't match up, reject inlining.
9691 We just do a string compare here, we don't analyze the meaning
9692 of the string, as it would be too costly for little gain. */
9700 }
9702 /* Return true if SYMBOL_REF X binds locally. */
9704 static bool
9706 {
9710 }
9712 /* Return true if SYMBOL_REF X is thread local */
9713 static bool
9715 {
9723 }
9725 /* Classify a TLS symbol into one of the TLS kinds. */
9726 enum aarch64_symbol_type
9728 {
9732 {
9739 {
9745 }
9756 else
9765 }
9766 }
9768 /* Return the method that should be used to access SYMBOL_REF or
9769 LABEL_REF X. */
9771 enum aarch64_symbol_type
9773 {
9775 {
9777 {
9792 }
9793 }
9796 {
9801 {
9803 /* When we retrieve symbol + offset address, we have to make sure
9804 the offset does not cause overflow of the final address. But
9805 we have no way of knowing the address of symbol at compile time
9806 so we can't accurately say if the distance between the PC and
9807 symbol + offset is outside the addressible range of +/-1M in the
9808 TINY code model. So we rely on images not being greater than
9809 1M and cap the offset at 1M and anything beyond 1M will have to
9810 be loaded using an alternative mechanism. Furthermore if the
9811 symbol is a weak reference to something that isn't known to
9812 resolve to a symbol in this module, then force to memory. */
9820 /* Same reasoning as the tiny code model, but the offset cap here is
9821 4G. */
9842 /* This is alright even in PIC code as the constant
9843 pool reference is always PC relative and within
9844 the same translation unit. */
9847 else
9852 }
9853 }
9855 /* By default push everything into the constant pool. */
9857 }
9859 bool
9861 {
9863 }
9865 bool
9867 {
9875 }
9877 /* Return true if X holds either a quarter-precision or
9878 floating-point +0.0 constant. */
9879 static bool
9881 {
9888 /* We only handle moving 0.0 to a TFmode register. */
9893 }
9895 static bool
9897 {
9898 /* Do not allow vector struct mode constants. We could support
9899 0 and -1 easily, but they need support in aarch64-simd.md. */
9903 /* This could probably go away because
9904 we now decompose CONST_INTs according to expand_mov_immediate. */
9915 }
9917 rtx
9919 {
9925 /* Can return in any reg. */
9928 }
9930 /* On AAPCS systems, this is the "struct __va_list". */
9933 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
9934 Return the type to use as __builtin_va_list.
9936 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
9938 struct __va_list
9939 {
9940 void *__stack;
9941 void *__gr_top;
9942 void *__vr_top;
9943 int __gr_offs;
9944 int __vr_offs;
9945 }; */
9947 static tree
9949 {
9950 tree va_list_name;
9953 /* Create the type. */
9955 /* Give it the required name. */
9957 TYPE_DECL,
9959 va_list_type);
9964 /* Create the fields. */
9967 ptr_type_node);
9970 ptr_type_node);
9973 ptr_type_node);
9976 integer_type_node);
9979 integer_type_node);
9981 /* Tell tree-stdarg pass about our internal offset fields.
9982 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
9983 purpose to identify whether the code is updating va_list internal
9984 offset fields through irregular way. */
10006 /* Compute its layout. */
10010 }
10012 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10013 static void
10015 {
10019 tree t;
10033 {
10036 }
10045 NULL_TREE);
10047 NULL_TREE);
10049 NULL_TREE);
10051 NULL_TREE);
10053 NULL_TREE);
10055 /* Emit code to initialize STACK, which points to the next varargs stack
10056 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10057 by named arguments. STACK is 8-byte aligned. */
10064 /* Emit code to initialize GRTOP, the top of the GR save area.
10065 virtual_incoming_args_rtx should have been 16 byte aligned. */
10070 /* Emit code to initialize VRTOP, the top of the VR save area.
10071 This address is gr_save_area_bytes below GRTOP, rounded
10072 down to the next 16-byte boundary. */
10082 /* Emit code to initialize GROFF, the offset from GRTOP of the
10083 next GPR argument. */
10088 /* Likewise emit code to initialize VROFF, the offset from FTOP
10089 of the next VR argument. */
10093 }
10095 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10097 static tree
10100 {
10101 tree addr;
10107 machine_mode mode;
10134 type,
10138 {
10139 /* TYPE passed in fp/simd registers. */
10151 {
10154 }
10157 {
10159 }
10160 }
10161 else
10162 {
10163 /* TYPE passed in general registers. */
10176 {
10178 }
10179 }
10181 /* Get a local temporary for the field value. */
10184 /* Emit code to branch if off >= 0. */
10190 {
10191 /* Emit: offs = (offs + 15) & -16. */
10197 }
10198 else
10201 /* Update ap.__[g|v]r_offs */
10206 /* String up. */
10210 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10215 /* String up: make sure the assignment happens before the use. */
10219 /* Prepare the trees handling the argument that is passed on the stack;
10220 the top level node will store in ON_STACK. */
10223 {
10224 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10232 }
10233 else
10235 /* Advance ap.__stack */
10243 /* String up roundup and advance. */
10246 /* String up with arg */
10248 /* Big-endianness related address adjustment. */
10251 {
10255 }
10260 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10270 {
10271 /* type ha; // treat as "struct {ftype field[n];}"
10272 ... [computing offs]
10273 for (i = 0; i <nregs; ++i, offs += 16)
10274 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10275 return ha; */
10279 /* Declare a local variable. */
10283 /* Establish the base type. */
10285 {
10304 {
10308 }
10312 }
10314 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10322 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10324 {
10334 }
10338 }
10348 }
10350 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10352 static void
10356 {
10358 CUMULATIVE_ARGS local_cum;
10362 /* The caller has advanced CUM up to, but not beyond, the last named
10363 argument. Advance a local copy of CUM past the last "real" named
10364 argument, to find out how many registers are left over. */
10368 /* Found out how many registers we need to save.
10369 Honor tree-stdvar analysis results. */
10378 {
10381 }
10384 {
10386 {
10389 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10397 }
10399 {
10400 /* We can't use move_block_from_reg, because it will use
10401 the wrong mode, storing D regs only. */
10405 /* Set OFF to the offset from virtual_incoming_args_rtx of
10406 the first vector register. The VR save area lies below
10407 the GR one, and is aligned to 16 bytes. */
10414 {
10422 }
10423 }
10424 }
10426 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10427 any complication of having crtl->args.pretend_args_size changed. */
10432 }
10434 static void
10436 {
10439 {
10441 {
10444 }
10445 }
10446 }
10448 /* Walk down the type tree of TYPE counting consecutive base elements.
10449 If *MODEP is VOIDmode, then set it to the first valid floating point
10450 type. If a non-floating point type is found, or if a floating point
10451 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10452 otherwise return the count in the sub-tree. */
10453 static int
10455 {
10456 machine_mode mode;
10457 HOST_WIDE_INT size;
10460 {
10490 /* Use V2SImode and V4SImode as representatives of all 64-bit
10491 and 128-bit vector types. */
10494 {
10503 }
10508 /* Vector modes are considered to be opaque: two vectors are
10509 equivalent for the purposes of being homogeneous aggregates
10510 if they are the same size. */
10517 {
10521 /* Can't handle incomplete types nor sizes that are not
10522 fixed. */
10529 || !index
10540 /* There must be no padding. */
10545 }
10548 {
10551 tree field;
10553 /* Can't handle incomplete types nor sizes that are not
10554 fixed. */
10560 {
10568 }
10570 /* There must be no padding. */
10575 }
10579 {
10580 /* These aren't very interesting except in a degenerate case. */
10583 tree field;
10585 /* Can't handle incomplete types nor sizes that are not
10586 fixed. */
10592 {
10600 }
10602 /* There must be no padding. */
10607 }
10611 }
10614 }
10616 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10617 type as described in AAPCS64 \S 4.1.2.
10619 See the comment above aarch64_composite_type_p for the notes on MODE. */
10621 static bool
10623 machine_mode mode)
10624 {
10634 }
10636 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10637 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10638 array types. The C99 floating-point complex types are also considered
10639 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10640 types, which are GCC extensions and out of the scope of AAPCS64, are
10641 treated as composite types here as well.
10643 Note that MODE itself is not sufficient in determining whether a type
10644 is such a composite type or not. This is because
10645 stor-layout.c:compute_record_mode may have already changed the MODE
10646 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10647 structure with only one field may have its MODE set to the mode of the
10648 field. Also an integer mode whose size matches the size of the
10649 RECORD_TYPE type may be used to substitute the original mode
10650 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10651 solely relied on. */
10653 static bool
10655 machine_mode mode)
10656 {
10669 }
10671 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10672 shall be passed or returned in simd/fp register(s) (providing these
10673 parameter passing registers are available).
10675 Upon successful return, *COUNT returns the number of needed registers,
10676 *BASE_MODE returns the mode of the individual register and when IS_HAF
10677 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10678 floating-point aggregate or a homogeneous short-vector aggregate. */
10680 static bool
10682 const_tree type,
10686 {
10694 {
10697 }
10699 {
10703 }
10705 {
10709 {
10712 }
10713 else
10715 }
10716 else
10721 }
10723 /* Implement TARGET_STRUCT_VALUE_RTX. */
10725 static rtx
10728 {
10730 }
10732 /* Implements target hook vector_mode_supported_p. */
10733 static bool
10735 {
10747 }
10749 /* Return appropriate SIMD container
10750 for MODE within a vector of WIDTH bits. */
10751 static machine_mode
10753 {
10756 {
10759 {
10774 }
10775 else
10777 {
10788 }
10789 }
10791 }
10793 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10794 static machine_mode
10796 {
10798 }
10800 /* Return the bitmask of possible vector sizes for the vectorizer
10801 to iterate over. */
10802 static unsigned int
10804 {
10806 }
10808 /* Implement TARGET_MANGLE_TYPE. */
10812 {
10813 /* The AArch64 ABI documents say that "__va_list" has to be
10814 managled as if it is in the "std" namespace. */
10818 /* Half-precision float. */
10822 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10823 builtin types. */
10827 /* Use the default mangling. */
10829 }
10832 /* Return true if the rtx_insn contains a MEM RTX somewhere
10833 in it. */
10835 static bool
10837 {
10844 }
10846 /* Find the first rtx_insn before insn that will generate an assembly
10847 instruction. */
10851 {
10855 do
10856 {
10858 }
10862 }
10864 static bool
10866 {
10868 /* A number of these may be AArch32 only. */
10873 };
10876 {
10879 }
10882 }
10884 /* Check if there is a register dependency between a load and the insn
10885 for which we hold recog_data. */
10887 static bool
10889 {
10890 rtx load_reg;
10900 {
10906 }
10908 }
10911 /* When working around the Cortex-A53 erratum 835769,
10912 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10913 instruction and has a preceding memory instruction such that a NOP
10914 should be inserted between them. */
10916 bool
10918 {
10921 rtx body;
10934 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
10935 Restore recog state to INSN to avoid state corruption. */
10943 /* If the previous insn is a memory op and there is no dependency between
10944 it and the DImode madd, emit a NOP between them. If body is NULL then we
10945 have a complex memory operation, probably a load/store pair.
10946 Be conservative for now and emit a NOP. */
10953 }
10956 /* Implement FINAL_PRESCAN_INSN. */
10958 void
10960 {
10963 }
10966 /* Return the equivalent letter for size. */
10967 static char
10969 {
10971 {
10977 }
10978 }
10980 /* Return true iff x is a uniform vector of floating-point
10981 constants, and the constant can be represented in
10982 quarter-precision form. Note, as aarch64_float_const_representable
10983 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
10984 static bool
10986 {
10987 rtx elt;
10991 }
10993 /* Return true for valid and false for invalid. */
10994 bool
10997 {
10998 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
10999 matches = 1; \
11000 for (i = 0; i < idx; i += (STRIDE)) \
11001 if (!(TEST)) \
11002 matches = 0; \
11003 if (matches) \
11004 { \
11005 immtype = (CLASS); \
11006 elsize = (ELSIZE); \
11007 eshift = (SHIFT); \
11008 emvn = (NEG); \
11009 break; \
11010 }
11020 {
11026 {
11031 }
11034 }
11036 /* Splat vector constant out into a byte vector. */
11038 {
11039 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11040 it must be laid out in the vector register in reverse order. */
11048 {
11051 }
11053 }
11055 /* Sanity check. */
11058 do
11059 {
11108 }
11115 {
11125 /* Un-invert bytes of recognized vector, if necessary. */
11131 {
11132 /* FIXME: Broken on 32-bit H_W_I hosts. */
11141 }
11142 else
11143 {
11147 /* Construct 'abcdefgh' because the assembler cannot handle
11148 generic constants. */
11153 }
11154 }
11157 #undef CHECK
11158 }
11160 /* Check of immediate shift constants are within range. */
11161 bool
11163 {
11167 else
11169 }
11171 /* Return true if X is a uniform vector where all elements
11172 are either the floating-point constant 0.0 or the
11173 integer constant 0. */
11174 bool
11176 {
11178 }
11181 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11182 operation of width WIDTH at bit position POS. */
11184 rtx
11186 {
11190 unsigned HOST_WIDE_INT mask
11193 }
11195 bool
11197 {
11202 {
11207 }
11210 }
11212 bool
11214 {
11227 }
11229 /* Return a const_int vector of VAL. */
11230 rtx
11232 {
11241 }
11243 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11245 bool
11247 {
11248 machine_mode vmode;
11254 }
11256 /* Construct and return a PARALLEL RTX vector with elements numbering the
11257 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11258 the vector - from the perspective of the architecture. This does not
11259 line up with GCC's perspective on lane numbers, so we end up with
11260 different masks depending on our target endian-ness. The diagram
11261 below may help. We must draw the distinction when building masks
11262 which select one half of the vector. An instruction selecting
11263 architectural low-lanes for a big-endian target, must be described using
11264 a mask selecting GCC high-lanes.
11266 Big-Endian Little-Endian
11268 GCC 0 1 2 3 3 2 1 0
11269 | x | x | x | x | | x | x | x | x |
11270 Architecture 3 2 1 0 3 2 1 0
11272 Low Mask: { 2, 3 } { 0, 1 }
11273 High Mask: { 0, 1 } { 2, 3 }
11274 */
11276 rtx
11278 {
11284 rtx t1;
11289 else
11297 }
11299 /* Check OP for validity as a PARALLEL RTX vector with elements
11300 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11301 from the perspective of the architecture. See the diagram above
11302 aarch64_simd_vect_par_cnst_half for more details. */
11304 bool
11307 {
11320 {
11327 }
11329 }
11331 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11332 HIGH (exclusive). */
11333 void
11335 const_tree exp)
11336 {
11337 HOST_WIDE_INT lane;
11342 {
11345 else
11347 }
11348 }
11350 /* Return TRUE if OP is a valid vector addressing mode. */
11351 bool
11353 {
11356 }
11358 /* Emit a register copy from operand to operand, taking care not to
11359 early-clobber source registers in the process.
11361 COUNT is the number of components into which the copy needs to be
11362 decomposed. */
11363 void
11366 {
11376 else
11380 }
11382 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11383 one of VSTRUCT modes: OI, CI, or XI. */
11384 int
11386 {
11388 }
11390 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11391 alignment of a vector to 128 bits. */
11392 static HOST_WIDE_INT
11394 {
11397 }
11399 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11400 static bool
11402 {
11406 /* We guarantee alignment for vectors up to 128-bits. */
11411 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11413 }
11415 /* If VALS is a vector constant that can be loaded into a register
11416 using DUP, generate instructions to do so and return an RTX to
11417 assign to the register. Otherwise return NULL_RTX. */
11418 static rtx
11420 {
11423 rtx x;
11428 /* We can load this constant by using DUP and a constant in a
11429 single ARM register. This will be cheaper than a vector
11430 load. */
11433 }
11436 /* Generate code to load VALS, which is a PARALLEL containing only
11437 constants (for vec_init) or CONST_VECTOR, efficiently into a
11438 register. Returns an RTX to copy into the register, or NULL_RTX
11439 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11440 static rtx
11442 {
11444 rtx const_dup;
11453 {
11454 /* A CONST_VECTOR must contain only CONST_INTs and
11455 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11456 Only store valid constants in a CONST_VECTOR. */
11458 {
11461 n_const++;
11462 }
11465 }
11466 else
11471 /* Load using MOVI/MVNI. */
11474 /* Loaded using DUP. */
11477 /* Load from constant pool. We can not take advantage of single-cycle
11478 LD1 because we need a PC-relative addressing mode. */
11480 else
11481 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11482 We can not construct an initializer. */
11484 }
11486 /* Expand a vector initialisation sequence, such that TARGET is
11487 initialised to contain VALS. */
11489 void
11491 {
11494 /* The number of vector elements. */
11496 /* The number of vector elements which are not constant. */
11499 /* The first element of vals. */
11503 /* Count the number of variable elements to initialise. */
11505 {
11509 else
11513 }
11515 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11516 how best to handle this. */
11518 {
11521 {
11524 }
11525 }
11527 /* Splat a single non-constant element if we can. */
11529 {
11533 }
11535 /* Initialise a vector which is part-variable. We want to first try
11536 to build those lanes which are constant in the most efficient way we
11537 can. */
11539 {
11542 /* Load constant part of vector. We really don't care what goes into the
11543 parts we will overwrite, but we're more likely to be able to load the
11544 constant efficiently if it has fewer, larger, repeating parts
11545 (see aarch64_simd_valid_immediate). */
11547 {
11553 {
11554 /* Look in the copied vector, as more elements are const. */
11557 {
11560 }
11561 }
11563 }
11565 }
11567 /* Insert the variable lanes directly. */
11573 {
11579 }
11580 }
11582 static unsigned HOST_WIDE_INT
11584 {
11585 return
11586 (!SHIFT_COUNT_TRUNCATED
11589 }
11591 /* Select a format to encode pointers in exception handling data. */
11592 int
11594 {
11597 {
11603 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11604 for everything. */
11608 /* No assumptions here. 8-byte relocs required. */
11611 }
11613 }
11615 /* The last .arch and .tune assembly strings that we printed. */
11619 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11620 by the function fndecl. */
11622 void
11624 tree fndecl)
11625 {
11631 else
11642 /* Only update the assembler .arch string if it is distinct from the last
11643 such string we printed. */
11646 {
11649 }
11651 /* Print the cpu name we're tuning for in the comments, might be
11652 useful to readers of the generated asm. Do it only when it changes
11653 from function to function and verbose assembly is requested. */
11658 {
11662 }
11664 /* Don't forget the type directive for ELF. */
11667 }
11669 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11671 static void
11673 {
11690 }
11692 /* Emit load exclusive. */
11694 static void
11697 {
11701 {
11708 }
11711 }
11713 /* Emit store exclusive. */
11715 static void
11718 {
11722 {
11729 }
11732 }
11734 /* Mark the previous jump instruction as unlikely. */
11736 static void
11738 {
11743 }
11745 /* Expand a compare and swap pattern. */
11747 void
11749 {
11754 gen_cas_fn gen;
11756 {
11757 gen_aarch64_compare_and_swapqi,
11758 gen_aarch64_compare_and_swaphi,
11759 gen_aarch64_compare_and_swapsi,
11760 gen_aarch64_compare_and_swapdi
11761 };
11763 {
11764 gen_aarch64_compare_and_swapqi_lse,
11765 gen_aarch64_compare_and_swaphi_lse,
11766 gen_aarch64_compare_and_swapsi_lse,
11767 gen_aarch64_compare_and_swapdi_lse
11768 };
11781 /* Normally the succ memory model must be stronger than fail, but in the
11782 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11783 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11790 {
11793 /* For short modes, we're going to perform the comparison in SImode,
11794 so do the zero-extension now. */
11798 /* Fall through. */
11802 /* Force the value into a register if needed. */
11809 }
11812 {
11819 }
11822 else
11833 }
11835 /* Test whether the target supports using a atomic load-operate instruction.
11836 CODE is the operation and AFTER is TRUE if the data in memory after the
11837 operation should be returned and FALSE if the data before the operation
11838 should be returned. Returns FALSE if the operation isn't supported by the
11839 architecture. */
11841 bool
11843 {
11848 {
11858 }
11859 }
11861 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11862 sequence implementing an atomic operation. */
11864 static void
11866 {
11873 {
11875 }
11876 }
11878 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11879 for the data in memory. EXPECTED is the value expected to be in memory.
11880 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11881 is the memory ordering to use. */
11883 void
11886 rtx model)
11887 {
11889 machine_mode mode;
11894 {
11901 }
11903 /* Move the expected value into the CAS destination register. */
11906 /* Emit the CAS. */
11909 /* Compare the expected value with the value loaded by the CAS, to establish
11910 whether the swap was made. */
11912 }
11914 /* Split a compare and swap pattern. */
11916 void
11918 {
11920 machine_mode mode;
11925 rtx model_rtx;
11939 {
11942 }
11945 /* The initial load can be relaxed for a __sync operation since a final
11946 barrier will be emitted to stop code hoisting. */
11950 else
11962 {
11967 }
11968 else
11969 {
11973 }
11977 /* Emit any final barrier needed for a __sync operation. */
11980 }
11982 /* Emit a BIC instruction. */
11984 static void
11986 {
11991 {
11996 }
11999 }
12001 /* Emit an atomic swap. */
12003 static void
12006 {
12010 {
12017 }
12020 }
12022 /* Operations supported by aarch64_emit_atomic_load_op. */
12024 enum aarch64_atomic_load_op_code
12025 {
12029 AARCH64_LDOP_BIC /* A & ~B */
12030 };
12032 /* Emit an atomic load-operate. */
12034 static void
12038 {
12041 {
12042 gen_aarch64_atomic_loadaddqi,
12043 gen_aarch64_atomic_loadaddhi,
12044 gen_aarch64_atomic_loadaddsi,
12045 gen_aarch64_atomic_loadadddi
12046 };
12048 {
12049 gen_aarch64_atomic_loadeorqi,
12050 gen_aarch64_atomic_loadeorhi,
12051 gen_aarch64_atomic_loadeorsi,
12052 gen_aarch64_atomic_loadeordi
12053 };
12055 {
12056 gen_aarch64_atomic_loadsetqi,
12057 gen_aarch64_atomic_loadsethi,
12058 gen_aarch64_atomic_loadsetsi,
12059 gen_aarch64_atomic_loadsetdi
12060 };
12062 {
12063 gen_aarch64_atomic_loadclrqi,
12064 gen_aarch64_atomic_loadclrhi,
12065 gen_aarch64_atomic_loadclrsi,
12066 gen_aarch64_atomic_loadclrdi
12067 };
12068 aarch64_atomic_load_op_fn gen;
12072 {
12079 }
12082 {
12089 }
12092 }
12094 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12095 location to store the data read from memory. OUT_RESULT is the location to
12096 store the result of the operation. MEM is the memory location to read and
12097 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12098 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12099 be NULL. */
12101 void
12104 {
12108 aarch64_atomic_load_op_code ldop_code;
12109 rtx src;
12110 rtx x;
12118 /* Make sure the value is in a register, putting it into a destination
12119 register if it needs to be manipulated. */
12122 {
12125 }
12126 else
12130 /* Preprocess the data for the operation as necessary. If the operation is
12131 a SET then emit a swap instruction and finish. */
12133 {
12139 /* Negate the value and treat it as a PLUS. */
12140 {
12141 rtx neg_src;
12143 /* Resize the value if necessary. */
12152 }
12153 /* Fall-through. */
12167 {
12168 rtx not_src;
12170 /* Resize the value if necessary. */
12179 }
12184 /* The operation can't be done with atomic instructions. */
12186 }
12190 /* If necessary, calculate the data in memory after the update by redoing the
12191 operation from values in registers. */
12196 {
12200 }
12205 {
12221 }
12226 }
12228 /* Split an atomic operation. */
12230 void
12233 {
12239 rtx x;
12241 /* Split the atomic operation into a sequence. */
12249 else
12253 /* The initial load can be relaxed for a __sync operation since a final
12254 barrier will be emitted to stop code hoisting. */
12258 else
12262 {
12276 {
12279 }
12280 /* Fall through. */
12286 }
12296 /* Emit any final barrier needed for a __sync operation. */
12299 }
12301 static void
12303 {
12304 /* Half-precision float operations. The compiler handles all operations
12305 with NULL libfuncs by converting to SFmode. */
12307 /* Conversions. */
12311 /* Arithmetic. */
12318 /* Comparisons. */
12326 }
12328 /* Target hook for c_mode_for_suffix. */
12329 static machine_mode
12331 {
12336 }
12338 /* We can only represent floating point constants which will fit in
12339 "quarter-precision" values. These values are characterised by
12340 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12341 by:
12343 (-1)^s * (n/16) * 2^r
12345 Where:
12346 's' is the sign bit.
12347 'n' is an integer in the range 16 <= n <= 31.
12348 'r' is an integer in the range -3 <= r <= 4. */
12350 /* Return true iff X can be represented by a quarter-precision
12351 floating point immediate operand X. Note, we cannot represent 0.0. */
12352 bool
12354 {
12355 /* This represents our current view of how many bits
12356 make up the mantissa. */
12366 /* We don't support HFmode constants yet. */
12372 /* We cannot represent infinities, NaNs or +/-zero. We won't
12373 know if we have +zero until we analyse the mantissa, but we
12374 can reject the other invalid values. */
12379 /* Extract exponent. */
12383 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12384 highest (sign) bit, with a fixed binary point at bit point_pos.
12385 m1 holds the low part of the mantissa, m2 the high part.
12386 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12387 bits for the mantissa, this can fail (low bits will be lost). */
12391 /* If the low part of the mantissa has bits set we cannot represent
12392 the value. */
12395 /* We have rejected the lower HOST_WIDE_INT, so update our
12396 understanding of how many bits lie in the mantissa and
12397 look only at the high HOST_WIDE_INT. */
12401 /* We can only represent values with a mantissa of the form 1.xxxx. */
12406 /* Having filtered unrepresentable values, we may now remove all
12407 but the highest 5 bits. */
12410 /* We cannot represent the value 0.0, so reject it. This is handled
12411 elsewhere. */
12415 /* Then, as bit 4 is always set, we can mask it off, leaving
12416 the mantissa in the range [0, 15]. */
12420 /* GCC internally does not use IEEE754-like encoding (where normalized
12421 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12422 Our mantissa values are shifted 4 places to the left relative to
12423 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12424 by 5 places to correct for GCC's representation. */
12428 }
12432 machine_mode mode,
12434 {
12444 /* This will return true to show const_vector is legal for use as either
12445 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12446 also update INFO to show how the immediate should be generated. */
12455 {
12457 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12458 move immediate path. */
12461 else
12462 {
12471 else
12475 }
12476 }
12489 else
12493 }
12497 machine_mode mode)
12498 {
12499 machine_mode vmode;
12505 }
12507 /* Split operands into moves from op[1] + op[2] into op[0]. */
12509 void
12511 {
12522 {
12523 /* No-op move. Can't split to nothing; emit something. */
12526 }
12528 /* Preserve register attributes for variable tracking. */
12533 /* Special case of reversed high/low parts. */
12536 {
12540 }
12542 {
12543 /* Try to avoid unnecessary moves if part of the result
12544 is in the right place already. */
12549 }
12550 else
12551 {
12556 }
12557 }
12559 /* vec_perm support. */
12561 #define MAX_VECT_LEN 16
12563 struct expand_vec_perm_d
12564 {
12567 machine_mode vmode;
12571 };
12573 /* Generate a variable permutation. */
12575 static void
12577 {
12588 {
12590 {
12591 /* Expand the argument to a V16QI mode by duplicating it. */
12595 }
12596 else
12597 {
12599 }
12600 }
12601 else
12602 {
12603 rtx pair;
12606 {
12610 }
12611 else
12612 {
12616 }
12617 }
12618 }
12620 void
12622 {
12626 rtx mask;
12628 /* The TBL instruction does not use a modulo index, so we must take care
12629 of that ourselves. */
12634 /* For big-endian, we also need to reverse the index within the vector
12635 (but not which vector). */
12637 {
12638 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12643 }
12645 }
12647 /* Recognize patterns suitable for the TRN instructions. */
12648 static bool
12650 {
12659 /* Note that these are little-endian tests.
12660 We correct for big-endian later. */
12665 else
12670 {
12675 }
12677 /* Success! */
12684 {
12687 }
12691 {
12693 {
12708 }
12709 }
12710 else
12711 {
12713 {
12728 }
12729 }
12733 }
12735 /* Recognize patterns suitable for the UZP instructions. */
12736 static bool
12738 {
12747 /* Note that these are little-endian tests.
12748 We correct for big-endian later. */
12753 else
12758 {
12762 }
12764 /* Success! */
12771 {
12774 }
12778 {
12780 {
12795 }
12796 }
12797 else
12798 {
12800 {
12815 }
12816 }
12820 }
12822 /* Recognize patterns suitable for the ZIP instructions. */
12823 static bool
12825 {
12834 /* Note that these are little-endian tests.
12835 We correct for big-endian later. */
12838 /* Do Nothing. */
12839 ;
12842 else
12847 {
12854 }
12856 /* Success! */
12863 {
12866 }
12870 {
12872 {
12887 }
12888 }
12889 else
12890 {
12892 {
12907 }
12908 }
12912 }
12914 /* Recognize patterns for the EXT insn. */
12916 static bool
12918 {
12921 rtx offset;
12925 /* Check if the extracted indices are increasing by one. */
12927 {
12930 {
12931 /* We'll pass the same vector in twice, so allow indices to wrap. */
12933 }
12936 }
12939 {
12954 }
12956 /* Success! */
12960 /* The case where (location == 0) is a no-op for both big- and little-endian,
12961 and is removed by the mid-end at optimization levels -O1 and higher. */
12964 {
12965 /* After setup, we want the high elements of the first vector (stored
12966 at the LSB end of the register), and the low elements of the second
12967 vector (stored at the MSB end of the register). So swap. */
12969 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
12971 }
12976 }
12978 /* Recognize patterns for the REV insns. */
12980 static bool
12982 {
12991 {
12994 {
12999 }
13003 {
13010 }
13014 {
13027 }
13031 }
13035 {
13036 /* This is guaranteed to be true as the value of diff
13037 is 7, 3, 1 and we should have enough elements in the
13038 queue to generate this. Getting a vector mask with a
13039 value of diff other than these values implies that
13040 something is wrong by the time we get here. */
13044 }
13046 /* Success! */
13052 }
13054 static bool
13056 {
13059 rtx in0;
13062 rtx lane;
13066 {
13069 }
13071 /* The generic preparation in aarch64_expand_vec_perm_const_1
13072 swaps the operand order and the permute indices if it finds
13073 d->perm[0] to be in the second operand. Thus, we can always
13074 use d->op0 and need not do any extra arithmetic to get the
13075 correct lane number. */
13080 {
13095 }
13099 }
13101 static bool
13103 {
13111 /* Generic code will try constant permutation twice. Once with the
13112 original mode and again with the elements lowered to QImode.
13113 So wait and don't do the selector expansion ourselves. */
13118 {
13121 /* If big-endian and two vectors we end up with a weird mixed-endian
13122 mode on NEON. Reverse the index within each word but not the word
13123 itself. */
13126 }
13132 }
13134 static bool
13136 {
13137 /* The pattern matching functions above are written to look for a small
13138 number to begin the sequence (0, 1, N/2). If we begin with an index
13139 from the second operand, we can swap the operands. */
13141 {
13149 }
13152 {
13166 }
13168 }
13170 /* Expand a vec_perm_const pattern. */
13172 bool
13174 {
13188 {
13193 }
13196 {
13205 /* The elements of PERM do not suggest that only the first operand
13206 is used, but both operands are identical. Allow easier matching
13207 of the permutation by folding the permutation into the single
13208 input vector. */
13209 /* Fall Through. */
13221 }
13224 }
13226 static bool
13229 {
13239 /* Calculate whether all elements are in one vector. */
13241 {
13245 }
13247 /* If all elements are from the second vector, reindex as if from the
13248 first vector. */
13253 /* Check whether the mask can be applied to a single vector. */
13266 }
13268 rtx
13270 {
13271 /* We have to reverse each vector because we dont have
13272 a permuted load that can reverse-load according to ABI rules. */
13273 rtx mask;
13287 }
13289 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13290 However due to issues with register allocation it is preferable to avoid
13291 tieing integer scalar and FP scalar modes. Executing integer operations
13292 in general registers is better than treating them as scalar vector
13293 operations. This reduces latency and avoids redundant int<->FP moves.
13294 So tie modes if they are either the same class, or vector modes with
13295 other vector modes, vector structs or any scalar mode.
13296 */
13298 bool
13300 {
13304 /* We specifically want to allow elements of "structure" modes to
13305 be tieable to the structure. This more general condition allows
13306 other rarer situations too. */
13310 /* Also allow any scalar modes with vectors. */
13316 }
13318 /* Return a new RTX holding the result of moving POINTER forward by
13319 AMOUNT bytes. */
13321 static rtx
13323 {
13328 }
13330 /* Return a new RTX holding the result of moving POINTER forward by the
13331 size of the mode it points to. */
13333 static rtx
13335 {
13339 }
13341 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13342 MODE bytes. */
13344 static void
13346 machine_mode mode)
13347 {
13350 /* "Cast" the pointers to the correct mode. */
13353 /* Emit the memcpy. */
13356 /* Move the pointers forward. */
13359 }
13361 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13362 we succeed, otherwise return false. */
13364 bool
13366 {
13370 rtx base;
13373 /* When optimizing for size, give a better estimate of the length of a
13374 memcpy call, but use the default otherwise. */
13377 /* We can't do anything smart if the amount to copy is not constant. */
13383 /* Try to keep the number of instructions low. For cases below 16 bytes we
13384 need to make at most two moves. For cases above 16 bytes it will be one
13385 move for each 16 byte chunk, then at most two additional moves. */
13395 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13396 1-byte chunk. */
13398 {
13400 {
13403 }
13409 }
13411 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13412 4-byte chunk, partially overlapping with the previously copied chunk. */
13414 {
13418 {
13424 }
13426 }
13428 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13429 them, then (if applicable) an 8-byte chunk. */
13431 {
13433 {
13436 }
13437 else
13438 {
13441 }
13442 }
13444 /* Finish the final bytes of the copy. We can always do this in one
13445 instruction. We either copy the exact amount we need, or partially
13446 overlap with the previous chunk we copied and copy 8-bytes. */
13455 else
13456 {
13458 {
13462 }
13463 else
13464 {
13470 }
13471 }
13474 }
13476 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
13477 SImode stores. Handle the case when the constant has identical
13478 bottom and top halves. This is beneficial when the two stores can be
13479 merged into an STP and we avoid synthesising potentially expensive
13480 immediates twice. Return true if such a split is possible. */
13482 bool
13484 {
13493 unsigned int orig_cost
13495 unsigned int lo_cost
13498 /* We want to transform:
13499 MOV x1, 49370
13500 MOVK x1, 0x140, lsl 16
13501 MOVK x1, 0xc0da, lsl 32
13502 MOVK x1, 0x140, lsl 48
13503 STR x1, [x0]
13504 into:
13505 MOV w1, 49370
13506 MOVK w1, 0x140, lsl 16
13507 STP w1, w1, [x0]
13508 So we want to perform this only when we save two instructions
13509 or more. When optimizing for size, however, accept any code size
13510 savings we can. */
13525 /* Don't emit an explicit store pair as this may not be always profitable.
13526 Let the sched-fusion logic decide whether to merge them. */
13531 }
13533 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13535 static unsigned HOST_WIDE_INT
13537 {
13539 }
13541 static bool
13546 {
13547 /* STORE_BY_PIECES can be used when copying a constant string, but
13548 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13549 For now we always fail this and let the move_by_pieces code copy
13550 the string from read-only memory. */
13555 }
13557 static rtx
13560 {
13564 insn_code icode;
13575 {
13603 }
13608 {
13611 }
13620 {
13623 }
13629 }
13631 static rtx
13634 {
13638 insn_code icode;
13650 {
13678 }
13683 {
13686 }
13694 {
13699 }
13710 {
13713 }
13719 }
13721 #undef TARGET_GEN_CCMP_FIRST
13722 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13724 #undef TARGET_GEN_CCMP_NEXT
13725 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13727 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13728 instruction fusion of some sort. */
13730 static bool
13732 {
13734 }
13737 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13738 should be kept together during scheduling. */
13740 static bool
13742 {
13743 rtx set_dest;
13746 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13753 {
13754 /* We are trying to match:
13755 prev (mov) == (set (reg r0) (const_int imm16))
13756 curr (movk) == (set (zero_extract (reg r0)
13757 (const_int 16)
13758 (const_int 16))
13759 (const_int imm16_1)) */
13771 {
13773 }
13774 }
13777 {
13779 /* We're trying to match:
13780 prev (adrp) == (set (reg r1)
13781 (high (symbol_ref ("SYM"))))
13782 curr (add) == (set (reg r0)
13783 (lo_sum (reg r1)
13784 (symbol_ref ("SYM"))))
13785 Note that r0 need not necessarily be the same as r1, especially
13786 during pre-regalloc scheduling. */
13790 {
13798 }
13799 }
13802 {
13804 /* We're trying to match:
13805 prev (movk) == (set (zero_extract (reg r0)
13806 (const_int 16)
13807 (const_int 32))
13808 (const_int imm16_1))
13809 curr (movk) == (set (zero_extract (reg r0)
13810 (const_int 16)
13811 (const_int 48))
13812 (const_int imm16_2)) */
13828 }
13830 {
13831 /* We're trying to match:
13832 prev (adrp) == (set (reg r0)
13833 (high (symbol_ref ("SYM"))))
13834 curr (ldr) == (set (reg r1)
13835 (mem (lo_sum (reg r0)
13836 (symbol_ref ("SYM")))))
13837 or
13838 curr (ldr) == (set (reg r1)
13839 (zero_extend (mem
13840 (lo_sum (reg r0)
13841 (symbol_ref ("SYM")))))) */
13844 {
13857 }
13858 }
13866 {
13869 /* FIXME: this misses some which is considered simple arthematic
13870 instructions for ThunderX. Simple shifts are missed here. */
13876 }
13879 }
13881 /* Return true iff the instruction fusion described by OP is enabled. */
13883 bool
13885 {
13887 }
13889 /* If MEM is in the form of [base+offset], extract the two parts
13890 of address and set to BASE and OFFSET, otherwise return false
13891 after clearing BASE and OFFSET. */
13893 bool
13895 {
13896 rtx addr;
13903 {
13907 }
13911 {
13915 }
13921 }
13923 /* Types for scheduling fusion. */
13924 enum sched_fusion_type
13925 {
13927 SCHED_FUSION_LD_SIGN_EXTEND,
13928 SCHED_FUSION_LD_ZERO_EXTEND,
13929 SCHED_FUSION_LD,
13930 SCHED_FUSION_ST,
13931 SCHED_FUSION_NUM
13932 };
13934 /* If INSN is a load or store of address in the form of [base+offset],
13935 extract the two parts and set to BASE and OFFSET. Return scheduling
13936 fusion type this INSN is. */
13938 static enum sched_fusion_type
13940 {
13958 {
13963 }
13965 {
13970 }
13975 {
13978 }
13979 else
13986 }
13988 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
13990 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
13991 and PRI are only calculated for these instructions. For other instruction,
13992 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
13993 type instruction fusion can be added by returning different priorities.
13995 It's important that irrelevant instructions get the largest FUSION_PRI. */
13997 static void
14000 {
14010 {
14014 }
14016 /* Set FUSION_PRI according to fusion type and base register. */
14019 /* Calculate PRI. */
14022 /* INSN with smaller offset goes first. */
14026 else
14031 }
14033 /* Given OPERANDS of consecutive load/store, check if we can merge
14034 them into ldp/stp. LOAD is true if they are load instructions.
14035 MODE is the mode of memory operands. */
14037 bool
14040 {
14046 {
14054 }
14055 else
14056 {
14061 }
14063 /* The mems cannot be volatile. */
14067 /* If we have SImode and slow unaligned ldp,
14068 check the alignment to be at least 8 byte. */
14072 && !optimize_size
14076 /* Check if the addresses are in the form of [base+offset]. */
14084 /* Check if the bases are same. */
14091 /* Check if the offsets are consecutive. */
14095 /* Check if the addresses are clobbered by load. */
14097 {
14101 /* In increasing order, the last load can clobber the address. */
14104 }
14108 else
14113 else
14116 /* Check if the registers are of same class. */
14121 }
14123 /* Given OPERANDS of consecutive load/store, check if we can merge
14124 them into ldp/stp by adjusting the offset. LOAD is true if they
14125 are load instructions. MODE is the mode of memory operands.
14127 Given below consecutive stores:
14129 str w1, [xb, 0x100]
14130 str w1, [xb, 0x104]
14131 str w1, [xb, 0x108]
14132 str w1, [xb, 0x10c]
14134 Though the offsets are out of the range supported by stp, we can
14135 still pair them after adjusting the offset, like:
14137 add scratch, xb, 0x100
14138 stp w1, w1, [scratch]
14139 stp w1, w1, [scratch, 0x8]
14141 The peephole patterns detecting this opportunity should guarantee
14142 the scratch register is avaliable. */
14144 bool
14147 {
14154 {
14167 }
14168 else
14169 {
14178 }
14179 /* Skip if memory operand is by itslef valid for ldp/stp. */
14183 /* The mems cannot be volatile. */
14188 /* Check if the addresses are in the form of [base+offset]. */
14202 /* Check if the bases are same. */
14213 /* Check if the offsets are consecutive. */
14222 /* Check if the addresses are clobbered by load. */
14224 {
14230 /* In increasing order, the last load can clobber the address. */
14233 }
14235 /* If we have SImode and slow unaligned ldp,
14236 check the alignment to be at least 8 byte. */
14240 && !optimize_size
14246 else
14251 else
14256 else
14261 else
14264 /* Check if the registers are of same class. */
14269 }
14271 /* Given OPERANDS of consecutive load/store, this function pairs them
14272 into ldp/stp after adjusting the offset. It depends on the fact
14273 that addresses of load/store instructions are in increasing order.
14274 MODE is the mode of memory operands. CODE is the rtl operator
14275 which should be applied to all memory operands, it's SIGN_EXTEND,
14276 ZERO_EXTEND or UNKNOWN. */
14278 bool
14281 {
14287 {
14292 }
14293 else
14294 {
14300 }
14305 /* Adjust offset thus it can fit in ldp/stp instruction. */
14313 /* Further adjust to make sure all offsets are OK. */
14315 {
14318 }
14320 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14325 {
14328 }
14330 /* Create new memory references. */
14334 /* Check if the adjusted address is OK for ldp/stp. */
14353 {
14358 }
14360 {
14365 }
14368 {
14373 }
14374 else
14375 {
14380 }
14382 /* Emit adjusting instruction. */
14384 /* Emit ldp/stp instructions. */
14392 }
14394 /* Return 1 if pseudo register should be created and used to hold
14395 GOT address for PIC code. */
14397 bool
14399 {
14401 }
14403 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
14405 static int
14407 {
14409 {
14416 }
14419 }
14422 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
14423 return the log2 of that value. Otherwise return -1. */
14425 int
14427 {
14442 }
14444 /* If X is a vector of equal CONST_DOUBLE values and that value is
14445 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
14447 int
14449 {
14465 }
14467 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
14468 to float.
14470 __fp16 always promotes through this hook.
14471 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
14472 through the generic excess precision logic rather than here. */
14474 static tree
14476 {
14482 }
14484 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
14486 static bool
14488 optimization_type opt_type)
14489 {
14491 {
14497 }
14498 }
14500 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
14501 if MODE is HFmode, and punt to the generic implementation otherwise. */
14503 static bool
14505 {
14509 }
14511 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
14512 if MODE is HFmode, and punt to the generic implementation otherwise. */
14514 static bool
14516 {
14520 }
14522 /* Set the value of FLT_EVAL_METHOD.
14523 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
14525 0: evaluate all operations and constants, whose semantic type has at
14526 most the range and precision of type float, to the range and
14527 precision of float; evaluate all other operations and constants to
14528 the range and precision of the semantic type;
14530 N, where _FloatN is a supported interchange floating type
14531 evaluate all operations and constants, whose semantic type has at
14532 most the range and precision of _FloatN type, to the range and
14533 precision of the _FloatN type; evaluate all other operations and
14534 constants to the range and precision of the semantic type;
14536 If we have the ARMv8.2-A extensions then we support _Float16 in native
14537 precision, so we should set this to 16. Otherwise, we support the type,
14538 but want to evaluate expressions in float precision, so set this to
14539 0. */
14541 static enum flt_eval_method
14543 {
14545 {
14548 /* We can calculate either in 16-bit range and precision or
14549 32-bit range and precision. Make that decision based on whether
14550 we have native support for the ARMv8.2-A 16-bit floating-point
14551 instructions or not. */
14553 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
14559 }
14561 }
14563 #undef TARGET_ADDRESS_COST
14564 #define TARGET_ADDRESS_COST aarch64_address_cost
14566 /* This hook will determines whether unnamed bitfields affect the alignment
14567 of the containing structure. The hook returns true if the structure
14568 should inherit the alignment requirements of an unnamed bitfield's
14569 type. */
14570 #undef TARGET_ALIGN_ANON_BITFIELD
14571 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14573 #undef TARGET_ASM_ALIGNED_DI_OP
14576 #undef TARGET_ASM_ALIGNED_HI_OP
14579 #undef TARGET_ASM_ALIGNED_SI_OP
14582 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14583 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14584 hook_bool_const_tree_hwi_hwi_const_tree_true
14586 #undef TARGET_ASM_FILE_START
14587 #define TARGET_ASM_FILE_START aarch64_start_file
14589 #undef TARGET_ASM_OUTPUT_MI_THUNK
14590 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14592 #undef TARGET_ASM_SELECT_RTX_SECTION
14593 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14595 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14596 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14598 #undef TARGET_BUILD_BUILTIN_VA_LIST
14599 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14601 #undef TARGET_CALLEE_COPIES
14602 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14604 #undef TARGET_CAN_ELIMINATE
14605 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14607 #undef TARGET_CAN_INLINE_P
14608 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14610 #undef TARGET_CANNOT_FORCE_CONST_MEM
14611 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14613 #undef TARGET_CASE_VALUES_THRESHOLD
14614 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14616 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14617 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14619 /* Only the least significant bit is used for initialization guard
14620 variables. */
14621 #undef TARGET_CXX_GUARD_MASK_BIT
14622 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14624 #undef TARGET_C_MODE_FOR_SUFFIX
14625 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14627 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14628 #undef TARGET_DEFAULT_TARGET_FLAGS
14629 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14630 #endif
14632 #undef TARGET_CLASS_MAX_NREGS
14633 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14635 #undef TARGET_BUILTIN_DECL
14636 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14638 #undef TARGET_BUILTIN_RECIPROCAL
14639 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14641 #undef TARGET_C_EXCESS_PRECISION
14642 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
14644 #undef TARGET_EXPAND_BUILTIN
14645 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14647 #undef TARGET_EXPAND_BUILTIN_VA_START
14648 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14650 #undef TARGET_FOLD_BUILTIN
14651 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14653 #undef TARGET_FUNCTION_ARG
14654 #define TARGET_FUNCTION_ARG aarch64_function_arg
14656 #undef TARGET_FUNCTION_ARG_ADVANCE
14657 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14659 #undef TARGET_FUNCTION_ARG_BOUNDARY
14660 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14662 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14663 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14665 #undef TARGET_FUNCTION_VALUE
14666 #define TARGET_FUNCTION_VALUE aarch64_function_value
14668 #undef TARGET_FUNCTION_VALUE_REGNO_P
14669 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14671 #undef TARGET_FRAME_POINTER_REQUIRED
14672 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14674 #undef TARGET_GIMPLE_FOLD_BUILTIN
14675 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14677 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14678 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14680 #undef TARGET_INIT_BUILTINS
14681 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14683 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
14684 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
14685 aarch64_ira_change_pseudo_allocno_class
14687 #undef TARGET_LEGITIMATE_ADDRESS_P
14688 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14690 #undef TARGET_LEGITIMATE_CONSTANT_P
14691 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14693 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
14694 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
14695 aarch64_legitimize_address_displacement
14697 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14698 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14700 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
14701 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
14702 aarch64_libgcc_floating_mode_supported_p
14704 #undef TARGET_MANGLE_TYPE
14705 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14707 #undef TARGET_MEMORY_MOVE_COST
14708 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14710 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14711 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14713 #undef TARGET_MUST_PASS_IN_STACK
14714 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14716 /* This target hook should return true if accesses to volatile bitfields
14717 should use the narrowest mode possible. It should return false if these
14718 accesses should use the bitfield container type. */
14719 #undef TARGET_NARROW_VOLATILE_BITFIELD
14720 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14722 #undef TARGET_OPTION_OVERRIDE
14723 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14725 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14726 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14727 aarch64_override_options_after_change
14729 #undef TARGET_OPTION_SAVE
14730 #define TARGET_OPTION_SAVE aarch64_option_save
14732 #undef TARGET_OPTION_RESTORE
14733 #define TARGET_OPTION_RESTORE aarch64_option_restore
14735 #undef TARGET_OPTION_PRINT
14736 #define TARGET_OPTION_PRINT aarch64_option_print
14738 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14739 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14741 #undef TARGET_SET_CURRENT_FUNCTION
14742 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14744 #undef TARGET_PASS_BY_REFERENCE
14745 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14747 #undef TARGET_PREFERRED_RELOAD_CLASS
14748 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
14750 #undef TARGET_SCHED_REASSOCIATION_WIDTH
14751 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
14753 #undef TARGET_PROMOTED_TYPE
14754 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
14756 #undef TARGET_SECONDARY_RELOAD
14757 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
14759 #undef TARGET_SHIFT_TRUNCATION_MASK
14760 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
14762 #undef TARGET_SETUP_INCOMING_VARARGS
14763 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
14765 #undef TARGET_STRUCT_VALUE_RTX
14766 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
14768 #undef TARGET_REGISTER_MOVE_COST
14769 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
14771 #undef TARGET_RETURN_IN_MEMORY
14772 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
14774 #undef TARGET_RETURN_IN_MSB
14775 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
14777 #undef TARGET_RTX_COSTS
14778 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
14780 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14781 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
14783 #undef TARGET_SCHED_ISSUE_RATE
14784 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
14786 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14787 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14788 aarch64_sched_first_cycle_multipass_dfa_lookahead
14790 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
14791 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
14792 aarch64_first_cycle_multipass_dfa_lookahead_guard
14794 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
14795 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
14796 aarch64_get_separate_components
14798 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
14799 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
14800 aarch64_components_for_bb
14802 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
14803 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
14804 aarch64_disqualify_components
14806 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
14807 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
14808 aarch64_emit_prologue_components
14810 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
14811 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
14812 aarch64_emit_epilogue_components
14814 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
14815 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
14816 aarch64_set_handled_components
14818 #undef TARGET_TRAMPOLINE_INIT
14819 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
14821 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14822 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
14824 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14825 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
14827 #undef TARGET_ARRAY_MODE_SUPPORTED_P
14828 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
14830 #undef TARGET_VECTORIZE_ADD_STMT_COST
14831 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
14833 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
14834 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
14835 aarch64_builtin_vectorization_cost
14837 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
14838 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
14840 #undef TARGET_VECTORIZE_BUILTINS
14841 #define TARGET_VECTORIZE_BUILTINS
14843 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
14844 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
14845 aarch64_builtin_vectorized_function
14847 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
14848 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
14849 aarch64_autovectorize_vector_sizes
14851 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14852 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
14853 aarch64_atomic_assign_expand_fenv
14855 /* Section anchor support. */
14857 #undef TARGET_MIN_ANCHOR_OFFSET
14858 #define TARGET_MIN_ANCHOR_OFFSET -256
14860 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
14861 byte offset; we can do much more for larger data types, but have no way
14862 to determine the size of the access. We assume accesses are aligned. */
14863 #undef TARGET_MAX_ANCHOR_OFFSET
14864 #define TARGET_MAX_ANCHOR_OFFSET 4095
14866 #undef TARGET_VECTOR_ALIGNMENT
14867 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
14869 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
14870 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
14871 aarch64_simd_vector_alignment_reachable
14873 /* vec_perm support. */
14875 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
14876 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
14877 aarch64_vectorize_vec_perm_const_ok
14879 #undef TARGET_INIT_LIBFUNCS
14880 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
14882 #undef TARGET_FIXED_CONDITION_CODE_REGS
14883 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
14885 #undef TARGET_FLAGS_REGNUM
14886 #define TARGET_FLAGS_REGNUM CC_REGNUM
14888 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
14889 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
14891 #undef TARGET_ASAN_SHADOW_OFFSET
14892 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
14894 #undef TARGET_LEGITIMIZE_ADDRESS
14895 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
14897 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
14898 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
14899 aarch64_use_by_pieces_infrastructure_p
14901 #undef TARGET_CAN_USE_DOLOOP_P
14902 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
14904 #undef TARGET_SCHED_MACRO_FUSION_P
14905 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
14907 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
14908 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
14910 #undef TARGET_SCHED_FUSION_PRIORITY
14911 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
14913 #undef TARGET_UNSPEC_MAY_TRAP_P
14914 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
14916 #undef TARGET_USE_PSEUDO_PIC_REG
14917 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
14919 #undef TARGET_PRINT_OPERAND
14920 #define TARGET_PRINT_OPERAND aarch64_print_operand
14922 #undef TARGET_PRINT_OPERAND_ADDRESS
14923 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
14925 #undef TARGET_OPTAB_SUPPORTED_P
14926 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
14928 #undef TARGET_OMIT_STRUCT_RETURN_REG
14929 #define TARGET_OMIT_STRUCT_RETURN_REG true