gcc/
[official-gcc.git] / gcc / expmed.c
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1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2014 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "diagnostic-core.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "stor-layout.h"
30 #include "tm_p.h"
31 #include "flags.h"
32 #include "insn-config.h"
33 #include "expr.h"
34 #include "optabs.h"
35 #include "recog.h"
36 #include "langhooks.h"
37 #include "df.h"
38 #include "target.h"
39 #include "expmed.h"
41 struct target_expmed default_target_expmed;
42 #if SWITCHABLE_TARGET
43 struct target_expmed *this_target_expmed = &default_target_expmed;
44 #endif
46 static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
47 unsigned HOST_WIDE_INT,
48 unsigned HOST_WIDE_INT,
49 unsigned HOST_WIDE_INT,
50 rtx);
51 static void store_fixed_bit_field_1 (rtx, unsigned HOST_WIDE_INT,
52 unsigned HOST_WIDE_INT,
53 rtx);
54 static void store_split_bit_field (rtx, unsigned HOST_WIDE_INT,
55 unsigned HOST_WIDE_INT,
56 unsigned HOST_WIDE_INT,
57 unsigned HOST_WIDE_INT,
58 rtx);
59 static rtx extract_fixed_bit_field (enum machine_mode, rtx,
60 unsigned HOST_WIDE_INT,
61 unsigned HOST_WIDE_INT, rtx, int);
62 static rtx extract_fixed_bit_field_1 (enum machine_mode, rtx,
63 unsigned HOST_WIDE_INT,
64 unsigned HOST_WIDE_INT, rtx, int);
65 static rtx lshift_value (enum machine_mode, unsigned HOST_WIDE_INT, int);
66 static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT,
67 unsigned HOST_WIDE_INT, int);
68 static void do_cmp_and_jump (rtx, rtx, enum rtx_code, enum machine_mode, rtx_code_label *);
69 static rtx expand_smod_pow2 (enum machine_mode, rtx, HOST_WIDE_INT);
70 static rtx expand_sdiv_pow2 (enum machine_mode, rtx, HOST_WIDE_INT);
72 /* Return a constant integer mask value of mode MODE with BITSIZE ones
73 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
74 The mask is truncated if necessary to the width of mode MODE. The
75 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
77 static inline rtx
78 mask_rtx (enum machine_mode mode, int bitpos, int bitsize, bool complement)
80 return immed_wide_int_const
81 (wi::shifted_mask (bitpos, bitsize, complement,
82 GET_MODE_PRECISION (mode)), mode);
85 /* Test whether a value is zero of a power of two. */
86 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
87 (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0)
89 struct init_expmed_rtl
91 rtx reg;
92 rtx plus;
93 rtx neg;
94 rtx mult;
95 rtx sdiv;
96 rtx udiv;
97 rtx sdiv_32;
98 rtx smod_32;
99 rtx wide_mult;
100 rtx wide_lshr;
101 rtx wide_trunc;
102 rtx shift;
103 rtx shift_mult;
104 rtx shift_add;
105 rtx shift_sub0;
106 rtx shift_sub1;
107 rtx zext;
108 rtx trunc;
110 rtx pow2[MAX_BITS_PER_WORD];
111 rtx cint[MAX_BITS_PER_WORD];
114 static void
115 init_expmed_one_conv (struct init_expmed_rtl *all, enum machine_mode to_mode,
116 enum machine_mode from_mode, bool speed)
118 int to_size, from_size;
119 rtx which;
121 /* We're given no information about the true size of a partial integer,
122 only the size of the "full" integer it requires for storage. For
123 comparison purposes here, reduce the bit size by one in that case. */
124 to_size = (GET_MODE_BITSIZE (to_mode)
125 - (GET_MODE_CLASS (to_mode) == MODE_PARTIAL_INT));
126 from_size = (GET_MODE_BITSIZE (from_mode)
127 - (GET_MODE_CLASS (from_mode) == MODE_PARTIAL_INT));
129 /* Assume cost of zero-extend and sign-extend is the same. */
130 which = (to_size < from_size ? all->trunc : all->zext);
132 PUT_MODE (all->reg, from_mode);
133 set_convert_cost (to_mode, from_mode, speed, set_src_cost (which, speed));
136 static void
137 init_expmed_one_mode (struct init_expmed_rtl *all,
138 enum machine_mode mode, int speed)
140 int m, n, mode_bitsize;
141 enum machine_mode mode_from;
143 mode_bitsize = GET_MODE_UNIT_BITSIZE (mode);
145 PUT_MODE (all->reg, mode);
146 PUT_MODE (all->plus, mode);
147 PUT_MODE (all->neg, mode);
148 PUT_MODE (all->mult, mode);
149 PUT_MODE (all->sdiv, mode);
150 PUT_MODE (all->udiv, mode);
151 PUT_MODE (all->sdiv_32, mode);
152 PUT_MODE (all->smod_32, mode);
153 PUT_MODE (all->wide_trunc, mode);
154 PUT_MODE (all->shift, mode);
155 PUT_MODE (all->shift_mult, mode);
156 PUT_MODE (all->shift_add, mode);
157 PUT_MODE (all->shift_sub0, mode);
158 PUT_MODE (all->shift_sub1, mode);
159 PUT_MODE (all->zext, mode);
160 PUT_MODE (all->trunc, mode);
162 set_add_cost (speed, mode, set_src_cost (all->plus, speed));
163 set_neg_cost (speed, mode, set_src_cost (all->neg, speed));
164 set_mul_cost (speed, mode, set_src_cost (all->mult, speed));
165 set_sdiv_cost (speed, mode, set_src_cost (all->sdiv, speed));
166 set_udiv_cost (speed, mode, set_src_cost (all->udiv, speed));
168 set_sdiv_pow2_cheap (speed, mode, (set_src_cost (all->sdiv_32, speed)
169 <= 2 * add_cost (speed, mode)));
170 set_smod_pow2_cheap (speed, mode, (set_src_cost (all->smod_32, speed)
171 <= 4 * add_cost (speed, mode)));
173 set_shift_cost (speed, mode, 0, 0);
175 int cost = add_cost (speed, mode);
176 set_shiftadd_cost (speed, mode, 0, cost);
177 set_shiftsub0_cost (speed, mode, 0, cost);
178 set_shiftsub1_cost (speed, mode, 0, cost);
181 n = MIN (MAX_BITS_PER_WORD, mode_bitsize);
182 for (m = 1; m < n; m++)
184 XEXP (all->shift, 1) = all->cint[m];
185 XEXP (all->shift_mult, 1) = all->pow2[m];
187 set_shift_cost (speed, mode, m, set_src_cost (all->shift, speed));
188 set_shiftadd_cost (speed, mode, m, set_src_cost (all->shift_add, speed));
189 set_shiftsub0_cost (speed, mode, m, set_src_cost (all->shift_sub0, speed));
190 set_shiftsub1_cost (speed, mode, m, set_src_cost (all->shift_sub1, speed));
193 if (SCALAR_INT_MODE_P (mode))
195 for (mode_from = MIN_MODE_INT; mode_from <= MAX_MODE_INT;
196 mode_from = (enum machine_mode)(mode_from + 1))
197 init_expmed_one_conv (all, mode, mode_from, speed);
199 if (GET_MODE_CLASS (mode) == MODE_INT)
201 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
202 if (wider_mode != VOIDmode)
204 PUT_MODE (all->zext, wider_mode);
205 PUT_MODE (all->wide_mult, wider_mode);
206 PUT_MODE (all->wide_lshr, wider_mode);
207 XEXP (all->wide_lshr, 1) = GEN_INT (mode_bitsize);
209 set_mul_widen_cost (speed, wider_mode,
210 set_src_cost (all->wide_mult, speed));
211 set_mul_highpart_cost (speed, mode,
212 set_src_cost (all->wide_trunc, speed));
217 void
218 init_expmed (void)
220 struct init_expmed_rtl all;
221 enum machine_mode mode = QImode;
222 int m, speed;
224 memset (&all, 0, sizeof all);
225 for (m = 1; m < MAX_BITS_PER_WORD; m++)
227 all.pow2[m] = GEN_INT ((HOST_WIDE_INT) 1 << m);
228 all.cint[m] = GEN_INT (m);
231 /* Avoid using hard regs in ways which may be unsupported. */
232 all.reg = gen_rtx_raw_REG (mode, LAST_VIRTUAL_REGISTER + 1);
233 all.plus = gen_rtx_PLUS (mode, all.reg, all.reg);
234 all.neg = gen_rtx_NEG (mode, all.reg);
235 all.mult = gen_rtx_MULT (mode, all.reg, all.reg);
236 all.sdiv = gen_rtx_DIV (mode, all.reg, all.reg);
237 all.udiv = gen_rtx_UDIV (mode, all.reg, all.reg);
238 all.sdiv_32 = gen_rtx_DIV (mode, all.reg, all.pow2[5]);
239 all.smod_32 = gen_rtx_MOD (mode, all.reg, all.pow2[5]);
240 all.zext = gen_rtx_ZERO_EXTEND (mode, all.reg);
241 all.wide_mult = gen_rtx_MULT (mode, all.zext, all.zext);
242 all.wide_lshr = gen_rtx_LSHIFTRT (mode, all.wide_mult, all.reg);
243 all.wide_trunc = gen_rtx_TRUNCATE (mode, all.wide_lshr);
244 all.shift = gen_rtx_ASHIFT (mode, all.reg, all.reg);
245 all.shift_mult = gen_rtx_MULT (mode, all.reg, all.reg);
246 all.shift_add = gen_rtx_PLUS (mode, all.shift_mult, all.reg);
247 all.shift_sub0 = gen_rtx_MINUS (mode, all.shift_mult, all.reg);
248 all.shift_sub1 = gen_rtx_MINUS (mode, all.reg, all.shift_mult);
249 all.trunc = gen_rtx_TRUNCATE (mode, all.reg);
251 for (speed = 0; speed < 2; speed++)
253 crtl->maybe_hot_insn_p = speed;
254 set_zero_cost (speed, set_src_cost (const0_rtx, speed));
256 for (mode = MIN_MODE_INT; mode <= MAX_MODE_INT;
257 mode = (enum machine_mode)(mode + 1))
258 init_expmed_one_mode (&all, mode, speed);
260 if (MIN_MODE_PARTIAL_INT != VOIDmode)
261 for (mode = MIN_MODE_PARTIAL_INT; mode <= MAX_MODE_PARTIAL_INT;
262 mode = (enum machine_mode)(mode + 1))
263 init_expmed_one_mode (&all, mode, speed);
265 if (MIN_MODE_VECTOR_INT != VOIDmode)
266 for (mode = MIN_MODE_VECTOR_INT; mode <= MAX_MODE_VECTOR_INT;
267 mode = (enum machine_mode)(mode + 1))
268 init_expmed_one_mode (&all, mode, speed);
271 if (alg_hash_used_p ())
273 struct alg_hash_entry *p = alg_hash_entry_ptr (0);
274 memset (p, 0, sizeof (*p) * NUM_ALG_HASH_ENTRIES);
276 else
277 set_alg_hash_used_p (true);
278 default_rtl_profile ();
280 ggc_free (all.trunc);
281 ggc_free (all.shift_sub1);
282 ggc_free (all.shift_sub0);
283 ggc_free (all.shift_add);
284 ggc_free (all.shift_mult);
285 ggc_free (all.shift);
286 ggc_free (all.wide_trunc);
287 ggc_free (all.wide_lshr);
288 ggc_free (all.wide_mult);
289 ggc_free (all.zext);
290 ggc_free (all.smod_32);
291 ggc_free (all.sdiv_32);
292 ggc_free (all.udiv);
293 ggc_free (all.sdiv);
294 ggc_free (all.mult);
295 ggc_free (all.neg);
296 ggc_free (all.plus);
297 ggc_free (all.reg);
300 /* Return an rtx representing minus the value of X.
301 MODE is the intended mode of the result,
302 useful if X is a CONST_INT. */
305 negate_rtx (enum machine_mode mode, rtx x)
307 rtx result = simplify_unary_operation (NEG, mode, x, mode);
309 if (result == 0)
310 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
312 return result;
315 /* Adjust bitfield memory MEM so that it points to the first unit of mode
316 MODE that contains a bitfield of size BITSIZE at bit position BITNUM.
317 If MODE is BLKmode, return a reference to every byte in the bitfield.
318 Set *NEW_BITNUM to the bit position of the field within the new memory. */
320 static rtx
321 narrow_bit_field_mem (rtx mem, enum machine_mode mode,
322 unsigned HOST_WIDE_INT bitsize,
323 unsigned HOST_WIDE_INT bitnum,
324 unsigned HOST_WIDE_INT *new_bitnum)
326 if (mode == BLKmode)
328 *new_bitnum = bitnum % BITS_PER_UNIT;
329 HOST_WIDE_INT offset = bitnum / BITS_PER_UNIT;
330 HOST_WIDE_INT size = ((*new_bitnum + bitsize + BITS_PER_UNIT - 1)
331 / BITS_PER_UNIT);
332 return adjust_bitfield_address_size (mem, mode, offset, size);
334 else
336 unsigned int unit = GET_MODE_BITSIZE (mode);
337 *new_bitnum = bitnum % unit;
338 HOST_WIDE_INT offset = (bitnum - *new_bitnum) / BITS_PER_UNIT;
339 return adjust_bitfield_address (mem, mode, offset);
343 /* The caller wants to perform insertion or extraction PATTERN on a
344 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
345 BITREGION_START and BITREGION_END are as for store_bit_field
346 and FIELDMODE is the natural mode of the field.
348 Search for a mode that is compatible with the memory access
349 restrictions and (where applicable) with a register insertion or
350 extraction. Return the new memory on success, storing the adjusted
351 bit position in *NEW_BITNUM. Return null otherwise. */
353 static rtx
354 adjust_bit_field_mem_for_reg (enum extraction_pattern pattern,
355 rtx op0, HOST_WIDE_INT bitsize,
356 HOST_WIDE_INT bitnum,
357 unsigned HOST_WIDE_INT bitregion_start,
358 unsigned HOST_WIDE_INT bitregion_end,
359 enum machine_mode fieldmode,
360 unsigned HOST_WIDE_INT *new_bitnum)
362 bit_field_mode_iterator iter (bitsize, bitnum, bitregion_start,
363 bitregion_end, MEM_ALIGN (op0),
364 MEM_VOLATILE_P (op0));
365 enum machine_mode best_mode;
366 if (iter.next_mode (&best_mode))
368 /* We can use a memory in BEST_MODE. See whether this is true for
369 any wider modes. All other things being equal, we prefer to
370 use the widest mode possible because it tends to expose more
371 CSE opportunities. */
372 if (!iter.prefer_smaller_modes ())
374 /* Limit the search to the mode required by the corresponding
375 register insertion or extraction instruction, if any. */
376 enum machine_mode limit_mode = word_mode;
377 extraction_insn insn;
378 if (get_best_reg_extraction_insn (&insn, pattern,
379 GET_MODE_BITSIZE (best_mode),
380 fieldmode))
381 limit_mode = insn.field_mode;
383 enum machine_mode wider_mode;
384 while (iter.next_mode (&wider_mode)
385 && GET_MODE_SIZE (wider_mode) <= GET_MODE_SIZE (limit_mode))
386 best_mode = wider_mode;
388 return narrow_bit_field_mem (op0, best_mode, bitsize, bitnum,
389 new_bitnum);
391 return NULL_RTX;
394 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
395 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
396 offset is then BITNUM / BITS_PER_UNIT. */
398 static bool
399 lowpart_bit_field_p (unsigned HOST_WIDE_INT bitnum,
400 unsigned HOST_WIDE_INT bitsize,
401 enum machine_mode struct_mode)
403 if (BYTES_BIG_ENDIAN)
404 return (bitnum % BITS_PER_UNIT == 0
405 && (bitnum + bitsize == GET_MODE_BITSIZE (struct_mode)
406 || (bitnum + bitsize) % BITS_PER_WORD == 0));
407 else
408 return bitnum % BITS_PER_WORD == 0;
411 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
412 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
413 Return false if the access would touch memory outside the range
414 BITREGION_START to BITREGION_END for conformance to the C++ memory
415 model. */
417 static bool
418 strict_volatile_bitfield_p (rtx op0, unsigned HOST_WIDE_INT bitsize,
419 unsigned HOST_WIDE_INT bitnum,
420 enum machine_mode fieldmode,
421 unsigned HOST_WIDE_INT bitregion_start,
422 unsigned HOST_WIDE_INT bitregion_end)
424 unsigned HOST_WIDE_INT modesize = GET_MODE_BITSIZE (fieldmode);
426 /* -fstrict-volatile-bitfields must be enabled and we must have a
427 volatile MEM. */
428 if (!MEM_P (op0)
429 || !MEM_VOLATILE_P (op0)
430 || flag_strict_volatile_bitfields <= 0)
431 return false;
433 /* Non-integral modes likely only happen with packed structures.
434 Punt. */
435 if (!SCALAR_INT_MODE_P (fieldmode))
436 return false;
438 /* The bit size must not be larger than the field mode, and
439 the field mode must not be larger than a word. */
440 if (bitsize > modesize || modesize > BITS_PER_WORD)
441 return false;
443 /* Check for cases of unaligned fields that must be split. */
444 if (bitnum % BITS_PER_UNIT + bitsize > modesize
445 || (STRICT_ALIGNMENT
446 && bitnum % GET_MODE_ALIGNMENT (fieldmode) + bitsize > modesize))
447 return false;
449 /* Check for cases where the C++ memory model applies. */
450 if (bitregion_end != 0
451 && (bitnum - bitnum % modesize < bitregion_start
452 || bitnum - bitnum % modesize + modesize > bitregion_end))
453 return false;
455 return true;
458 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
459 bit number BITNUM can be treated as a simple value of mode MODE. */
461 static bool
462 simple_mem_bitfield_p (rtx op0, unsigned HOST_WIDE_INT bitsize,
463 unsigned HOST_WIDE_INT bitnum, enum machine_mode mode)
465 return (MEM_P (op0)
466 && bitnum % BITS_PER_UNIT == 0
467 && bitsize == GET_MODE_BITSIZE (mode)
468 && (!SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0))
469 || (bitnum % GET_MODE_ALIGNMENT (mode) == 0
470 && MEM_ALIGN (op0) >= GET_MODE_ALIGNMENT (mode))));
473 /* Try to use instruction INSV to store VALUE into a field of OP0.
474 BITSIZE and BITNUM are as for store_bit_field. */
476 static bool
477 store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
478 unsigned HOST_WIDE_INT bitsize,
479 unsigned HOST_WIDE_INT bitnum,
480 rtx value)
482 struct expand_operand ops[4];
483 rtx value1;
484 rtx xop0 = op0;
485 rtx_insn *last = get_last_insn ();
486 bool copy_back = false;
488 enum machine_mode op_mode = insv->field_mode;
489 unsigned int unit = GET_MODE_BITSIZE (op_mode);
490 if (bitsize == 0 || bitsize > unit)
491 return false;
493 if (MEM_P (xop0))
494 /* Get a reference to the first byte of the field. */
495 xop0 = narrow_bit_field_mem (xop0, insv->struct_mode, bitsize, bitnum,
496 &bitnum);
497 else
499 /* Convert from counting within OP0 to counting in OP_MODE. */
500 if (BYTES_BIG_ENDIAN)
501 bitnum += unit - GET_MODE_BITSIZE (GET_MODE (op0));
503 /* If xop0 is a register, we need it in OP_MODE
504 to make it acceptable to the format of insv. */
505 if (GET_CODE (xop0) == SUBREG)
506 /* We can't just change the mode, because this might clobber op0,
507 and we will need the original value of op0 if insv fails. */
508 xop0 = gen_rtx_SUBREG (op_mode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
509 if (REG_P (xop0) && GET_MODE (xop0) != op_mode)
510 xop0 = gen_lowpart_SUBREG (op_mode, xop0);
513 /* If the destination is a paradoxical subreg such that we need a
514 truncate to the inner mode, perform the insertion on a temporary and
515 truncate the result to the original destination. Note that we can't
516 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
517 X) 0)) is (reg:N X). */
518 if (GET_CODE (xop0) == SUBREG
519 && REG_P (SUBREG_REG (xop0))
520 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0)),
521 op_mode))
523 rtx tem = gen_reg_rtx (op_mode);
524 emit_move_insn (tem, xop0);
525 xop0 = tem;
526 copy_back = true;
529 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
530 "backwards" from the size of the unit we are inserting into.
531 Otherwise, we count bits from the most significant on a
532 BYTES/BITS_BIG_ENDIAN machine. */
534 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
535 bitnum = unit - bitsize - bitnum;
537 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
538 value1 = value;
539 if (GET_MODE (value) != op_mode)
541 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
543 /* Optimization: Don't bother really extending VALUE
544 if it has all the bits we will actually use. However,
545 if we must narrow it, be sure we do it correctly. */
547 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (op_mode))
549 rtx tmp;
551 tmp = simplify_subreg (op_mode, value1, GET_MODE (value), 0);
552 if (! tmp)
553 tmp = simplify_gen_subreg (op_mode,
554 force_reg (GET_MODE (value),
555 value1),
556 GET_MODE (value), 0);
557 value1 = tmp;
559 else
560 value1 = gen_lowpart (op_mode, value1);
562 else if (CONST_INT_P (value))
563 value1 = gen_int_mode (INTVAL (value), op_mode);
564 else
565 /* Parse phase is supposed to make VALUE's data type
566 match that of the component reference, which is a type
567 at least as wide as the field; so VALUE should have
568 a mode that corresponds to that type. */
569 gcc_assert (CONSTANT_P (value));
572 create_fixed_operand (&ops[0], xop0);
573 create_integer_operand (&ops[1], bitsize);
574 create_integer_operand (&ops[2], bitnum);
575 create_input_operand (&ops[3], value1, op_mode);
576 if (maybe_expand_insn (insv->icode, 4, ops))
578 if (copy_back)
579 convert_move (op0, xop0, true);
580 return true;
582 delete_insns_since (last);
583 return false;
586 /* A subroutine of store_bit_field, with the same arguments. Return true
587 if the operation could be implemented.
589 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
590 no other way of implementing the operation. If FALLBACK_P is false,
591 return false instead. */
593 static bool
594 store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
595 unsigned HOST_WIDE_INT bitnum,
596 unsigned HOST_WIDE_INT bitregion_start,
597 unsigned HOST_WIDE_INT bitregion_end,
598 enum machine_mode fieldmode,
599 rtx value, bool fallback_p)
601 rtx op0 = str_rtx;
602 rtx orig_value;
604 while (GET_CODE (op0) == SUBREG)
606 /* The following line once was done only if WORDS_BIG_ENDIAN,
607 but I think that is a mistake. WORDS_BIG_ENDIAN is
608 meaningful at a much higher level; when structures are copied
609 between memory and regs, the higher-numbered regs
610 always get higher addresses. */
611 int inner_mode_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)));
612 int outer_mode_size = GET_MODE_SIZE (GET_MODE (op0));
613 int byte_offset = 0;
615 /* Paradoxical subregs need special handling on big endian machines. */
616 if (SUBREG_BYTE (op0) == 0 && inner_mode_size < outer_mode_size)
618 int difference = inner_mode_size - outer_mode_size;
620 if (WORDS_BIG_ENDIAN)
621 byte_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
622 if (BYTES_BIG_ENDIAN)
623 byte_offset += difference % UNITS_PER_WORD;
625 else
626 byte_offset = SUBREG_BYTE (op0);
628 bitnum += byte_offset * BITS_PER_UNIT;
629 op0 = SUBREG_REG (op0);
632 /* No action is needed if the target is a register and if the field
633 lies completely outside that register. This can occur if the source
634 code contains an out-of-bounds access to a small array. */
635 if (REG_P (op0) && bitnum >= GET_MODE_BITSIZE (GET_MODE (op0)))
636 return true;
638 /* Use vec_set patterns for inserting parts of vectors whenever
639 available. */
640 if (VECTOR_MODE_P (GET_MODE (op0))
641 && !MEM_P (op0)
642 && optab_handler (vec_set_optab, GET_MODE (op0)) != CODE_FOR_nothing
643 && fieldmode == GET_MODE_INNER (GET_MODE (op0))
644 && bitsize == GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
645 && !(bitnum % GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
647 struct expand_operand ops[3];
648 enum machine_mode outermode = GET_MODE (op0);
649 enum machine_mode innermode = GET_MODE_INNER (outermode);
650 enum insn_code icode = optab_handler (vec_set_optab, outermode);
651 int pos = bitnum / GET_MODE_BITSIZE (innermode);
653 create_fixed_operand (&ops[0], op0);
654 create_input_operand (&ops[1], value, innermode);
655 create_integer_operand (&ops[2], pos);
656 if (maybe_expand_insn (icode, 3, ops))
657 return true;
660 /* If the target is a register, overwriting the entire object, or storing
661 a full-word or multi-word field can be done with just a SUBREG. */
662 if (!MEM_P (op0)
663 && bitsize == GET_MODE_BITSIZE (fieldmode)
664 && ((bitsize == GET_MODE_BITSIZE (GET_MODE (op0)) && bitnum == 0)
665 || (bitsize % BITS_PER_WORD == 0 && bitnum % BITS_PER_WORD == 0)))
667 /* Use the subreg machinery either to narrow OP0 to the required
668 words or to cope with mode punning between equal-sized modes.
669 In the latter case, use subreg on the rhs side, not lhs. */
670 rtx sub;
672 if (bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
674 sub = simplify_gen_subreg (GET_MODE (op0), value, fieldmode, 0);
675 if (sub)
677 emit_move_insn (op0, sub);
678 return true;
681 else
683 sub = simplify_gen_subreg (fieldmode, op0, GET_MODE (op0),
684 bitnum / BITS_PER_UNIT);
685 if (sub)
687 emit_move_insn (sub, value);
688 return true;
693 /* If the target is memory, storing any naturally aligned field can be
694 done with a simple store. For targets that support fast unaligned
695 memory, any naturally sized, unit aligned field can be done directly. */
696 if (simple_mem_bitfield_p (op0, bitsize, bitnum, fieldmode))
698 op0 = adjust_bitfield_address (op0, fieldmode, bitnum / BITS_PER_UNIT);
699 emit_move_insn (op0, value);
700 return true;
703 /* Make sure we are playing with integral modes. Pun with subregs
704 if we aren't. This must come after the entire register case above,
705 since that case is valid for any mode. The following cases are only
706 valid for integral modes. */
708 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
709 if (imode != GET_MODE (op0))
711 if (MEM_P (op0))
712 op0 = adjust_bitfield_address_size (op0, imode, 0, MEM_SIZE (op0));
713 else
715 gcc_assert (imode != BLKmode);
716 op0 = gen_lowpart (imode, op0);
721 /* Storing an lsb-aligned field in a register
722 can be done with a movstrict instruction. */
724 if (!MEM_P (op0)
725 && lowpart_bit_field_p (bitnum, bitsize, GET_MODE (op0))
726 && bitsize == GET_MODE_BITSIZE (fieldmode)
727 && optab_handler (movstrict_optab, fieldmode) != CODE_FOR_nothing)
729 struct expand_operand ops[2];
730 enum insn_code icode = optab_handler (movstrict_optab, fieldmode);
731 rtx arg0 = op0;
732 unsigned HOST_WIDE_INT subreg_off;
734 if (GET_CODE (arg0) == SUBREG)
736 /* Else we've got some float mode source being extracted into
737 a different float mode destination -- this combination of
738 subregs results in Severe Tire Damage. */
739 gcc_assert (GET_MODE (SUBREG_REG (arg0)) == fieldmode
740 || GET_MODE_CLASS (fieldmode) == MODE_INT
741 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT);
742 arg0 = SUBREG_REG (arg0);
745 subreg_off = bitnum / BITS_PER_UNIT;
746 if (validate_subreg (fieldmode, GET_MODE (arg0), arg0, subreg_off))
748 arg0 = gen_rtx_SUBREG (fieldmode, arg0, subreg_off);
750 create_fixed_operand (&ops[0], arg0);
751 /* Shrink the source operand to FIELDMODE. */
752 create_convert_operand_to (&ops[1], value, fieldmode, false);
753 if (maybe_expand_insn (icode, 2, ops))
754 return true;
758 /* Handle fields bigger than a word. */
760 if (bitsize > BITS_PER_WORD)
762 /* Here we transfer the words of the field
763 in the order least significant first.
764 This is because the most significant word is the one which may
765 be less than full.
766 However, only do that if the value is not BLKmode. */
768 unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
769 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
770 unsigned int i;
771 rtx_insn *last;
773 /* This is the mode we must force value to, so that there will be enough
774 subwords to extract. Note that fieldmode will often (always?) be
775 VOIDmode, because that is what store_field uses to indicate that this
776 is a bit field, but passing VOIDmode to operand_subword_force
777 is not allowed. */
778 fieldmode = GET_MODE (value);
779 if (fieldmode == VOIDmode)
780 fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT);
782 last = get_last_insn ();
783 for (i = 0; i < nwords; i++)
785 /* If I is 0, use the low-order word in both field and target;
786 if I is 1, use the next to lowest word; and so on. */
787 unsigned int wordnum = (backwards
788 ? GET_MODE_SIZE (fieldmode) / UNITS_PER_WORD
789 - i - 1
790 : i);
791 unsigned int bit_offset = (backwards
792 ? MAX ((int) bitsize - ((int) i + 1)
793 * BITS_PER_WORD,
795 : (int) i * BITS_PER_WORD);
796 rtx value_word = operand_subword_force (value, wordnum, fieldmode);
797 unsigned HOST_WIDE_INT new_bitsize =
798 MIN (BITS_PER_WORD, bitsize - i * BITS_PER_WORD);
800 /* If the remaining chunk doesn't have full wordsize we have
801 to make sure that for big endian machines the higher order
802 bits are used. */
803 if (new_bitsize < BITS_PER_WORD && BYTES_BIG_ENDIAN && !backwards)
804 value_word = simplify_expand_binop (word_mode, lshr_optab,
805 value_word,
806 GEN_INT (BITS_PER_WORD
807 - new_bitsize),
808 NULL_RTX, true,
809 OPTAB_LIB_WIDEN);
811 if (!store_bit_field_1 (op0, new_bitsize,
812 bitnum + bit_offset,
813 bitregion_start, bitregion_end,
814 word_mode,
815 value_word, fallback_p))
817 delete_insns_since (last);
818 return false;
821 return true;
824 /* If VALUE has a floating-point or complex mode, access it as an
825 integer of the corresponding size. This can occur on a machine
826 with 64 bit registers that uses SFmode for float. It can also
827 occur for unaligned float or complex fields. */
828 orig_value = value;
829 if (GET_MODE (value) != VOIDmode
830 && GET_MODE_CLASS (GET_MODE (value)) != MODE_INT
831 && GET_MODE_CLASS (GET_MODE (value)) != MODE_PARTIAL_INT)
833 value = gen_reg_rtx (int_mode_for_mode (GET_MODE (value)));
834 emit_move_insn (gen_lowpart (GET_MODE (orig_value), value), orig_value);
837 /* If OP0 is a multi-word register, narrow it to the affected word.
838 If the region spans two words, defer to store_split_bit_field. */
839 if (!MEM_P (op0) && GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
841 op0 = simplify_gen_subreg (word_mode, op0, GET_MODE (op0),
842 bitnum / BITS_PER_WORD * UNITS_PER_WORD);
843 gcc_assert (op0);
844 bitnum %= BITS_PER_WORD;
845 if (bitnum + bitsize > BITS_PER_WORD)
847 if (!fallback_p)
848 return false;
850 store_split_bit_field (op0, bitsize, bitnum, bitregion_start,
851 bitregion_end, value);
852 return true;
856 /* From here on we can assume that the field to be stored in fits
857 within a word. If the destination is a register, it too fits
858 in a word. */
860 extraction_insn insv;
861 if (!MEM_P (op0)
862 && get_best_reg_extraction_insn (&insv, EP_insv,
863 GET_MODE_BITSIZE (GET_MODE (op0)),
864 fieldmode)
865 && store_bit_field_using_insv (&insv, op0, bitsize, bitnum, value))
866 return true;
868 /* If OP0 is a memory, try copying it to a register and seeing if a
869 cheap register alternative is available. */
870 if (MEM_P (op0))
872 if (get_best_mem_extraction_insn (&insv, EP_insv, bitsize, bitnum,
873 fieldmode)
874 && store_bit_field_using_insv (&insv, op0, bitsize, bitnum, value))
875 return true;
877 rtx_insn *last = get_last_insn ();
879 /* Try loading part of OP0 into a register, inserting the bitfield
880 into that, and then copying the result back to OP0. */
881 unsigned HOST_WIDE_INT bitpos;
882 rtx xop0 = adjust_bit_field_mem_for_reg (EP_insv, op0, bitsize, bitnum,
883 bitregion_start, bitregion_end,
884 fieldmode, &bitpos);
885 if (xop0)
887 rtx tempreg = copy_to_reg (xop0);
888 if (store_bit_field_1 (tempreg, bitsize, bitpos,
889 bitregion_start, bitregion_end,
890 fieldmode, orig_value, false))
892 emit_move_insn (xop0, tempreg);
893 return true;
895 delete_insns_since (last);
899 if (!fallback_p)
900 return false;
902 store_fixed_bit_field (op0, bitsize, bitnum, bitregion_start,
903 bitregion_end, value);
904 return true;
907 /* Generate code to store value from rtx VALUE
908 into a bit-field within structure STR_RTX
909 containing BITSIZE bits starting at bit BITNUM.
911 BITREGION_START is bitpos of the first bitfield in this region.
912 BITREGION_END is the bitpos of the ending bitfield in this region.
913 These two fields are 0, if the C++ memory model does not apply,
914 or we are not interested in keeping track of bitfield regions.
916 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
918 void
919 store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
920 unsigned HOST_WIDE_INT bitnum,
921 unsigned HOST_WIDE_INT bitregion_start,
922 unsigned HOST_WIDE_INT bitregion_end,
923 enum machine_mode fieldmode,
924 rtx value)
926 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
927 if (strict_volatile_bitfield_p (str_rtx, bitsize, bitnum, fieldmode,
928 bitregion_start, bitregion_end))
930 /* Storing any naturally aligned field can be done with a simple
931 store. For targets that support fast unaligned memory, any
932 naturally sized, unit aligned field can be done directly. */
933 if (simple_mem_bitfield_p (str_rtx, bitsize, bitnum, fieldmode))
935 str_rtx = adjust_bitfield_address (str_rtx, fieldmode,
936 bitnum / BITS_PER_UNIT);
937 emit_move_insn (str_rtx, value);
939 else
941 str_rtx = narrow_bit_field_mem (str_rtx, fieldmode, bitsize, bitnum,
942 &bitnum);
943 /* Explicitly override the C/C++ memory model; ignore the
944 bit range so that we can do the access in the mode mandated
945 by -fstrict-volatile-bitfields instead. */
946 store_fixed_bit_field_1 (str_rtx, bitsize, bitnum, value);
949 return;
952 /* Under the C++0x memory model, we must not touch bits outside the
953 bit region. Adjust the address to start at the beginning of the
954 bit region. */
955 if (MEM_P (str_rtx) && bitregion_start > 0)
957 enum machine_mode bestmode;
958 HOST_WIDE_INT offset, size;
960 gcc_assert ((bitregion_start % BITS_PER_UNIT) == 0);
962 offset = bitregion_start / BITS_PER_UNIT;
963 bitnum -= bitregion_start;
964 size = (bitnum + bitsize + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
965 bitregion_end -= bitregion_start;
966 bitregion_start = 0;
967 bestmode = get_best_mode (bitsize, bitnum,
968 bitregion_start, bitregion_end,
969 MEM_ALIGN (str_rtx), VOIDmode,
970 MEM_VOLATILE_P (str_rtx));
971 str_rtx = adjust_bitfield_address_size (str_rtx, bestmode, offset, size);
974 if (!store_bit_field_1 (str_rtx, bitsize, bitnum,
975 bitregion_start, bitregion_end,
976 fieldmode, value, true))
977 gcc_unreachable ();
980 /* Use shifts and boolean operations to store VALUE into a bit field of
981 width BITSIZE in OP0, starting at bit BITNUM. */
983 static void
984 store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
985 unsigned HOST_WIDE_INT bitnum,
986 unsigned HOST_WIDE_INT bitregion_start,
987 unsigned HOST_WIDE_INT bitregion_end,
988 rtx value)
990 /* There is a case not handled here:
991 a structure with a known alignment of just a halfword
992 and a field split across two aligned halfwords within the structure.
993 Or likewise a structure with a known alignment of just a byte
994 and a field split across two bytes.
995 Such cases are not supposed to be able to occur. */
997 if (MEM_P (op0))
999 enum machine_mode mode = GET_MODE (op0);
1000 if (GET_MODE_BITSIZE (mode) == 0
1001 || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode))
1002 mode = word_mode;
1003 mode = get_best_mode (bitsize, bitnum, bitregion_start, bitregion_end,
1004 MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0));
1006 if (mode == VOIDmode)
1008 /* The only way this should occur is if the field spans word
1009 boundaries. */
1010 store_split_bit_field (op0, bitsize, bitnum, bitregion_start,
1011 bitregion_end, value);
1012 return;
1015 op0 = narrow_bit_field_mem (op0, mode, bitsize, bitnum, &bitnum);
1018 store_fixed_bit_field_1 (op0, bitsize, bitnum, value);
1021 /* Helper function for store_fixed_bit_field, stores
1022 the bit field always using the MODE of OP0. */
1024 static void
1025 store_fixed_bit_field_1 (rtx op0, unsigned HOST_WIDE_INT bitsize,
1026 unsigned HOST_WIDE_INT bitnum,
1027 rtx value)
1029 enum machine_mode mode;
1030 rtx temp;
1031 int all_zero = 0;
1032 int all_one = 0;
1034 mode = GET_MODE (op0);
1035 gcc_assert (SCALAR_INT_MODE_P (mode));
1037 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1038 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1040 if (BYTES_BIG_ENDIAN)
1041 /* BITNUM is the distance between our msb
1042 and that of the containing datum.
1043 Convert it to the distance from the lsb. */
1044 bitnum = GET_MODE_BITSIZE (mode) - bitsize - bitnum;
1046 /* Now BITNUM is always the distance between our lsb
1047 and that of OP0. */
1049 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1050 we must first convert its mode to MODE. */
1052 if (CONST_INT_P (value))
1054 HOST_WIDE_INT v = INTVAL (value);
1056 if (bitsize < HOST_BITS_PER_WIDE_INT)
1057 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
1059 if (v == 0)
1060 all_zero = 1;
1061 else if ((bitsize < HOST_BITS_PER_WIDE_INT
1062 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
1063 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
1064 all_one = 1;
1066 value = lshift_value (mode, v, bitnum);
1068 else
1070 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
1071 && bitnum + bitsize != GET_MODE_BITSIZE (mode));
1073 if (GET_MODE (value) != mode)
1074 value = convert_to_mode (mode, value, 1);
1076 if (must_and)
1077 value = expand_binop (mode, and_optab, value,
1078 mask_rtx (mode, 0, bitsize, 0),
1079 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1080 if (bitnum > 0)
1081 value = expand_shift (LSHIFT_EXPR, mode, value,
1082 bitnum, NULL_RTX, 1);
1085 /* Now clear the chosen bits in OP0,
1086 except that if VALUE is -1 we need not bother. */
1087 /* We keep the intermediates in registers to allow CSE to combine
1088 consecutive bitfield assignments. */
1090 temp = force_reg (mode, op0);
1092 if (! all_one)
1094 temp = expand_binop (mode, and_optab, temp,
1095 mask_rtx (mode, bitnum, bitsize, 1),
1096 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1097 temp = force_reg (mode, temp);
1100 /* Now logical-or VALUE into OP0, unless it is zero. */
1102 if (! all_zero)
1104 temp = expand_binop (mode, ior_optab, temp, value,
1105 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1106 temp = force_reg (mode, temp);
1109 if (op0 != temp)
1111 op0 = copy_rtx (op0);
1112 emit_move_insn (op0, temp);
1116 /* Store a bit field that is split across multiple accessible memory objects.
1118 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1119 BITSIZE is the field width; BITPOS the position of its first bit
1120 (within the word).
1121 VALUE is the value to store.
1123 This does not yet handle fields wider than BITS_PER_WORD. */
1125 static void
1126 store_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1127 unsigned HOST_WIDE_INT bitpos,
1128 unsigned HOST_WIDE_INT bitregion_start,
1129 unsigned HOST_WIDE_INT bitregion_end,
1130 rtx value)
1132 unsigned int unit;
1133 unsigned int bitsdone = 0;
1135 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1136 much at a time. */
1137 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
1138 unit = BITS_PER_WORD;
1139 else
1140 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1142 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1143 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1144 again, and we will mutually recurse forever. */
1145 if (MEM_P (op0) && GET_MODE_BITSIZE (GET_MODE (op0)) > 0)
1146 unit = MIN (unit, GET_MODE_BITSIZE (GET_MODE (op0)));
1148 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1149 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1150 that VALUE might be a floating-point constant. */
1151 if (CONSTANT_P (value) && !CONST_INT_P (value))
1153 rtx word = gen_lowpart_common (word_mode, value);
1155 if (word && (value != word))
1156 value = word;
1157 else
1158 value = gen_lowpart_common (word_mode,
1159 force_reg (GET_MODE (value) != VOIDmode
1160 ? GET_MODE (value)
1161 : word_mode, value));
1164 while (bitsdone < bitsize)
1166 unsigned HOST_WIDE_INT thissize;
1167 rtx part, word;
1168 unsigned HOST_WIDE_INT thispos;
1169 unsigned HOST_WIDE_INT offset;
1171 offset = (bitpos + bitsdone) / unit;
1172 thispos = (bitpos + bitsdone) % unit;
1174 /* When region of bytes we can touch is restricted, decrease
1175 UNIT close to the end of the region as needed. If op0 is a REG
1176 or SUBREG of REG, don't do this, as there can't be data races
1177 on a register and we can expand shorter code in some cases. */
1178 if (bitregion_end
1179 && unit > BITS_PER_UNIT
1180 && bitpos + bitsdone - thispos + unit > bitregion_end + 1
1181 && !REG_P (op0)
1182 && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
1184 unit = unit / 2;
1185 continue;
1188 /* THISSIZE must not overrun a word boundary. Otherwise,
1189 store_fixed_bit_field will call us again, and we will mutually
1190 recurse forever. */
1191 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1192 thissize = MIN (thissize, unit - thispos);
1194 if (BYTES_BIG_ENDIAN)
1196 /* Fetch successively less significant portions. */
1197 if (CONST_INT_P (value))
1198 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
1199 >> (bitsize - bitsdone - thissize))
1200 & (((HOST_WIDE_INT) 1 << thissize) - 1));
1201 else
1203 int total_bits = GET_MODE_BITSIZE (GET_MODE (value));
1204 /* The args are chosen so that the last part includes the
1205 lsb. Give extract_bit_field the value it needs (with
1206 endianness compensation) to fetch the piece we want. */
1207 part = extract_fixed_bit_field (word_mode, value, thissize,
1208 total_bits - bitsize + bitsdone,
1209 NULL_RTX, 1);
1212 else
1214 /* Fetch successively more significant portions. */
1215 if (CONST_INT_P (value))
1216 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
1217 >> bitsdone)
1218 & (((HOST_WIDE_INT) 1 << thissize) - 1));
1219 else
1220 part = extract_fixed_bit_field (word_mode, value, thissize,
1221 bitsdone, NULL_RTX, 1);
1224 /* If OP0 is a register, then handle OFFSET here.
1226 When handling multiword bitfields, extract_bit_field may pass
1227 down a word_mode SUBREG of a larger REG for a bitfield that actually
1228 crosses a word boundary. Thus, for a SUBREG, we must find
1229 the current word starting from the base register. */
1230 if (GET_CODE (op0) == SUBREG)
1232 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD)
1233 + (offset * unit / BITS_PER_WORD);
1234 enum machine_mode sub_mode = GET_MODE (SUBREG_REG (op0));
1235 if (sub_mode != BLKmode && GET_MODE_SIZE (sub_mode) < UNITS_PER_WORD)
1236 word = word_offset ? const0_rtx : op0;
1237 else
1238 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1239 GET_MODE (SUBREG_REG (op0)));
1240 offset &= BITS_PER_WORD / unit - 1;
1242 else if (REG_P (op0))
1244 enum machine_mode op0_mode = GET_MODE (op0);
1245 if (op0_mode != BLKmode && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD)
1246 word = offset ? const0_rtx : op0;
1247 else
1248 word = operand_subword_force (op0, offset * unit / BITS_PER_WORD,
1249 GET_MODE (op0));
1250 offset &= BITS_PER_WORD / unit - 1;
1252 else
1253 word = op0;
1255 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1256 it is just an out-of-bounds access. Ignore it. */
1257 if (word != const0_rtx)
1258 store_fixed_bit_field (word, thissize, offset * unit + thispos,
1259 bitregion_start, bitregion_end, part);
1260 bitsdone += thissize;
1264 /* A subroutine of extract_bit_field_1 that converts return value X
1265 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1266 to extract_bit_field. */
1268 static rtx
1269 convert_extracted_bit_field (rtx x, enum machine_mode mode,
1270 enum machine_mode tmode, bool unsignedp)
1272 if (GET_MODE (x) == tmode || GET_MODE (x) == mode)
1273 return x;
1275 /* If the x mode is not a scalar integral, first convert to the
1276 integer mode of that size and then access it as a floating-point
1277 value via a SUBREG. */
1278 if (!SCALAR_INT_MODE_P (tmode))
1280 enum machine_mode smode;
1282 smode = mode_for_size (GET_MODE_BITSIZE (tmode), MODE_INT, 0);
1283 x = convert_to_mode (smode, x, unsignedp);
1284 x = force_reg (smode, x);
1285 return gen_lowpart (tmode, x);
1288 return convert_to_mode (tmode, x, unsignedp);
1291 /* Try to use an ext(z)v pattern to extract a field from OP0.
1292 Return the extracted value on success, otherwise return null.
1293 EXT_MODE is the mode of the extraction and the other arguments
1294 are as for extract_bit_field. */
1296 static rtx
1297 extract_bit_field_using_extv (const extraction_insn *extv, rtx op0,
1298 unsigned HOST_WIDE_INT bitsize,
1299 unsigned HOST_WIDE_INT bitnum,
1300 int unsignedp, rtx target,
1301 enum machine_mode mode, enum machine_mode tmode)
1303 struct expand_operand ops[4];
1304 rtx spec_target = target;
1305 rtx spec_target_subreg = 0;
1306 enum machine_mode ext_mode = extv->field_mode;
1307 unsigned unit = GET_MODE_BITSIZE (ext_mode);
1309 if (bitsize == 0 || unit < bitsize)
1310 return NULL_RTX;
1312 if (MEM_P (op0))
1313 /* Get a reference to the first byte of the field. */
1314 op0 = narrow_bit_field_mem (op0, extv->struct_mode, bitsize, bitnum,
1315 &bitnum);
1316 else
1318 /* Convert from counting within OP0 to counting in EXT_MODE. */
1319 if (BYTES_BIG_ENDIAN)
1320 bitnum += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1322 /* If op0 is a register, we need it in EXT_MODE to make it
1323 acceptable to the format of ext(z)v. */
1324 if (GET_CODE (op0) == SUBREG && GET_MODE (op0) != ext_mode)
1325 return NULL_RTX;
1326 if (REG_P (op0) && GET_MODE (op0) != ext_mode)
1327 op0 = gen_lowpart_SUBREG (ext_mode, op0);
1330 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1331 "backwards" from the size of the unit we are extracting from.
1332 Otherwise, we count bits from the most significant on a
1333 BYTES/BITS_BIG_ENDIAN machine. */
1335 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1336 bitnum = unit - bitsize - bitnum;
1338 if (target == 0)
1339 target = spec_target = gen_reg_rtx (tmode);
1341 if (GET_MODE (target) != ext_mode)
1343 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1344 between the mode of the extraction (word_mode) and the target
1345 mode. Instead, create a temporary and use convert_move to set
1346 the target. */
1347 if (REG_P (target)
1348 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (target), ext_mode))
1350 target = gen_lowpart (ext_mode, target);
1351 if (GET_MODE_PRECISION (ext_mode)
1352 > GET_MODE_PRECISION (GET_MODE (spec_target)))
1353 spec_target_subreg = target;
1355 else
1356 target = gen_reg_rtx (ext_mode);
1359 create_output_operand (&ops[0], target, ext_mode);
1360 create_fixed_operand (&ops[1], op0);
1361 create_integer_operand (&ops[2], bitsize);
1362 create_integer_operand (&ops[3], bitnum);
1363 if (maybe_expand_insn (extv->icode, 4, ops))
1365 target = ops[0].value;
1366 if (target == spec_target)
1367 return target;
1368 if (target == spec_target_subreg)
1369 return spec_target;
1370 return convert_extracted_bit_field (target, mode, tmode, unsignedp);
1372 return NULL_RTX;
1375 /* A subroutine of extract_bit_field, with the same arguments.
1376 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1377 if we can find no other means of implementing the operation.
1378 if FALLBACK_P is false, return NULL instead. */
1380 static rtx
1381 extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1382 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1383 enum machine_mode mode, enum machine_mode tmode,
1384 bool fallback_p)
1386 rtx op0 = str_rtx;
1387 enum machine_mode int_mode;
1388 enum machine_mode mode1;
1390 if (tmode == VOIDmode)
1391 tmode = mode;
1393 while (GET_CODE (op0) == SUBREG)
1395 bitnum += SUBREG_BYTE (op0) * BITS_PER_UNIT;
1396 op0 = SUBREG_REG (op0);
1399 /* If we have an out-of-bounds access to a register, just return an
1400 uninitialized register of the required mode. This can occur if the
1401 source code contains an out-of-bounds access to a small array. */
1402 if (REG_P (op0) && bitnum >= GET_MODE_BITSIZE (GET_MODE (op0)))
1403 return gen_reg_rtx (tmode);
1405 if (REG_P (op0)
1406 && mode == GET_MODE (op0)
1407 && bitnum == 0
1408 && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
1410 /* We're trying to extract a full register from itself. */
1411 return op0;
1414 /* See if we can get a better vector mode before extracting. */
1415 if (VECTOR_MODE_P (GET_MODE (op0))
1416 && !MEM_P (op0)
1417 && GET_MODE_INNER (GET_MODE (op0)) != tmode)
1419 enum machine_mode new_mode;
1421 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1422 new_mode = MIN_MODE_VECTOR_FLOAT;
1423 else if (GET_MODE_CLASS (tmode) == MODE_FRACT)
1424 new_mode = MIN_MODE_VECTOR_FRACT;
1425 else if (GET_MODE_CLASS (tmode) == MODE_UFRACT)
1426 new_mode = MIN_MODE_VECTOR_UFRACT;
1427 else if (GET_MODE_CLASS (tmode) == MODE_ACCUM)
1428 new_mode = MIN_MODE_VECTOR_ACCUM;
1429 else if (GET_MODE_CLASS (tmode) == MODE_UACCUM)
1430 new_mode = MIN_MODE_VECTOR_UACCUM;
1431 else
1432 new_mode = MIN_MODE_VECTOR_INT;
1434 for (; new_mode != VOIDmode ; new_mode = GET_MODE_WIDER_MODE (new_mode))
1435 if (GET_MODE_SIZE (new_mode) == GET_MODE_SIZE (GET_MODE (op0))
1436 && targetm.vector_mode_supported_p (new_mode))
1437 break;
1438 if (new_mode != VOIDmode)
1439 op0 = gen_lowpart (new_mode, op0);
1442 /* Use vec_extract patterns for extracting parts of vectors whenever
1443 available. */
1444 if (VECTOR_MODE_P (GET_MODE (op0))
1445 && !MEM_P (op0)
1446 && optab_handler (vec_extract_optab, GET_MODE (op0)) != CODE_FOR_nothing
1447 && ((bitnum + bitsize - 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
1448 == bitnum / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
1450 struct expand_operand ops[3];
1451 enum machine_mode outermode = GET_MODE (op0);
1452 enum machine_mode innermode = GET_MODE_INNER (outermode);
1453 enum insn_code icode = optab_handler (vec_extract_optab, outermode);
1454 unsigned HOST_WIDE_INT pos = bitnum / GET_MODE_BITSIZE (innermode);
1456 create_output_operand (&ops[0], target, innermode);
1457 create_input_operand (&ops[1], op0, outermode);
1458 create_integer_operand (&ops[2], pos);
1459 if (maybe_expand_insn (icode, 3, ops))
1461 target = ops[0].value;
1462 if (GET_MODE (target) != mode)
1463 return gen_lowpart (tmode, target);
1464 return target;
1468 /* Make sure we are playing with integral modes. Pun with subregs
1469 if we aren't. */
1471 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1472 if (imode != GET_MODE (op0))
1474 if (MEM_P (op0))
1475 op0 = adjust_bitfield_address_size (op0, imode, 0, MEM_SIZE (op0));
1476 else if (imode != BLKmode)
1478 op0 = gen_lowpart (imode, op0);
1480 /* If we got a SUBREG, force it into a register since we
1481 aren't going to be able to do another SUBREG on it. */
1482 if (GET_CODE (op0) == SUBREG)
1483 op0 = force_reg (imode, op0);
1485 else if (REG_P (op0))
1487 rtx reg, subreg;
1488 imode = smallest_mode_for_size (GET_MODE_BITSIZE (GET_MODE (op0)),
1489 MODE_INT);
1490 reg = gen_reg_rtx (imode);
1491 subreg = gen_lowpart_SUBREG (GET_MODE (op0), reg);
1492 emit_move_insn (subreg, op0);
1493 op0 = reg;
1494 bitnum += SUBREG_BYTE (subreg) * BITS_PER_UNIT;
1496 else
1498 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (op0));
1499 rtx mem = assign_stack_temp (GET_MODE (op0), size);
1500 emit_move_insn (mem, op0);
1501 op0 = adjust_bitfield_address_size (mem, BLKmode, 0, size);
1506 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1507 If that's wrong, the solution is to test for it and set TARGET to 0
1508 if needed. */
1510 /* Get the mode of the field to use for atomic access or subreg
1511 conversion. */
1512 mode1 = mode;
1513 if (SCALAR_INT_MODE_P (tmode))
1515 enum machine_mode try_mode = mode_for_size (bitsize,
1516 GET_MODE_CLASS (tmode), 0);
1517 if (try_mode != BLKmode)
1518 mode1 = try_mode;
1520 gcc_assert (mode1 != BLKmode);
1522 /* Extraction of a full MODE1 value can be done with a subreg as long
1523 as the least significant bit of the value is the least significant
1524 bit of either OP0 or a word of OP0. */
1525 if (!MEM_P (op0)
1526 && lowpart_bit_field_p (bitnum, bitsize, GET_MODE (op0))
1527 && bitsize == GET_MODE_BITSIZE (mode1)
1528 && TRULY_NOOP_TRUNCATION_MODES_P (mode1, GET_MODE (op0)))
1530 rtx sub = simplify_gen_subreg (mode1, op0, GET_MODE (op0),
1531 bitnum / BITS_PER_UNIT);
1532 if (sub)
1533 return convert_extracted_bit_field (sub, mode, tmode, unsignedp);
1536 /* Extraction of a full MODE1 value can be done with a load as long as
1537 the field is on a byte boundary and is sufficiently aligned. */
1538 if (simple_mem_bitfield_p (op0, bitsize, bitnum, mode1))
1540 op0 = adjust_bitfield_address (op0, mode1, bitnum / BITS_PER_UNIT);
1541 return convert_extracted_bit_field (op0, mode, tmode, unsignedp);
1544 /* Handle fields bigger than a word. */
1546 if (bitsize > BITS_PER_WORD)
1548 /* Here we transfer the words of the field
1549 in the order least significant first.
1550 This is because the most significant word is the one which may
1551 be less than full. */
1553 unsigned int backwards = WORDS_BIG_ENDIAN;
1554 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1555 unsigned int i;
1556 rtx_insn *last;
1558 if (target == 0 || !REG_P (target) || !valid_multiword_target_p (target))
1559 target = gen_reg_rtx (mode);
1561 /* Indicate for flow that the entire target reg is being set. */
1562 emit_clobber (target);
1564 last = get_last_insn ();
1565 for (i = 0; i < nwords; i++)
1567 /* If I is 0, use the low-order word in both field and target;
1568 if I is 1, use the next to lowest word; and so on. */
1569 /* Word number in TARGET to use. */
1570 unsigned int wordnum
1571 = (backwards
1572 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1573 : i);
1574 /* Offset from start of field in OP0. */
1575 unsigned int bit_offset = (backwards
1576 ? MAX ((int) bitsize - ((int) i + 1)
1577 * BITS_PER_WORD,
1579 : (int) i * BITS_PER_WORD);
1580 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1581 rtx result_part
1582 = extract_bit_field_1 (op0, MIN (BITS_PER_WORD,
1583 bitsize - i * BITS_PER_WORD),
1584 bitnum + bit_offset, 1, target_part,
1585 mode, word_mode, fallback_p);
1587 gcc_assert (target_part);
1588 if (!result_part)
1590 delete_insns_since (last);
1591 return NULL;
1594 if (result_part != target_part)
1595 emit_move_insn (target_part, result_part);
1598 if (unsignedp)
1600 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1601 need to be zero'd out. */
1602 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1604 unsigned int i, total_words;
1606 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1607 for (i = nwords; i < total_words; i++)
1608 emit_move_insn
1609 (operand_subword (target,
1610 backwards ? total_words - i - 1 : i,
1611 1, VOIDmode),
1612 const0_rtx);
1614 return target;
1617 /* Signed bit field: sign-extend with two arithmetic shifts. */
1618 target = expand_shift (LSHIFT_EXPR, mode, target,
1619 GET_MODE_BITSIZE (mode) - bitsize, NULL_RTX, 0);
1620 return expand_shift (RSHIFT_EXPR, mode, target,
1621 GET_MODE_BITSIZE (mode) - bitsize, NULL_RTX, 0);
1624 /* If OP0 is a multi-word register, narrow it to the affected word.
1625 If the region spans two words, defer to extract_split_bit_field. */
1626 if (!MEM_P (op0) && GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1628 op0 = simplify_gen_subreg (word_mode, op0, GET_MODE (op0),
1629 bitnum / BITS_PER_WORD * UNITS_PER_WORD);
1630 bitnum %= BITS_PER_WORD;
1631 if (bitnum + bitsize > BITS_PER_WORD)
1633 if (!fallback_p)
1634 return NULL_RTX;
1635 target = extract_split_bit_field (op0, bitsize, bitnum, unsignedp);
1636 return convert_extracted_bit_field (target, mode, tmode, unsignedp);
1640 /* From here on we know the desired field is smaller than a word.
1641 If OP0 is a register, it too fits within a word. */
1642 enum extraction_pattern pattern = unsignedp ? EP_extzv : EP_extv;
1643 extraction_insn extv;
1644 if (!MEM_P (op0)
1645 /* ??? We could limit the structure size to the part of OP0 that
1646 contains the field, with appropriate checks for endianness
1647 and TRULY_NOOP_TRUNCATION. */
1648 && get_best_reg_extraction_insn (&extv, pattern,
1649 GET_MODE_BITSIZE (GET_MODE (op0)),
1650 tmode))
1652 rtx result = extract_bit_field_using_extv (&extv, op0, bitsize, bitnum,
1653 unsignedp, target, mode,
1654 tmode);
1655 if (result)
1656 return result;
1659 /* If OP0 is a memory, try copying it to a register and seeing if a
1660 cheap register alternative is available. */
1661 if (MEM_P (op0))
1663 if (get_best_mem_extraction_insn (&extv, pattern, bitsize, bitnum,
1664 tmode))
1666 rtx result = extract_bit_field_using_extv (&extv, op0, bitsize,
1667 bitnum, unsignedp,
1668 target, mode,
1669 tmode);
1670 if (result)
1671 return result;
1674 rtx_insn *last = get_last_insn ();
1676 /* Try loading part of OP0 into a register and extracting the
1677 bitfield from that. */
1678 unsigned HOST_WIDE_INT bitpos;
1679 rtx xop0 = adjust_bit_field_mem_for_reg (pattern, op0, bitsize, bitnum,
1680 0, 0, tmode, &bitpos);
1681 if (xop0)
1683 xop0 = copy_to_reg (xop0);
1684 rtx result = extract_bit_field_1 (xop0, bitsize, bitpos,
1685 unsignedp, target,
1686 mode, tmode, false);
1687 if (result)
1688 return result;
1689 delete_insns_since (last);
1693 if (!fallback_p)
1694 return NULL;
1696 /* Find a correspondingly-sized integer field, so we can apply
1697 shifts and masks to it. */
1698 int_mode = int_mode_for_mode (tmode);
1699 if (int_mode == BLKmode)
1700 int_mode = int_mode_for_mode (mode);
1701 /* Should probably push op0 out to memory and then do a load. */
1702 gcc_assert (int_mode != BLKmode);
1704 target = extract_fixed_bit_field (int_mode, op0, bitsize, bitnum,
1705 target, unsignedp);
1706 return convert_extracted_bit_field (target, mode, tmode, unsignedp);
1709 /* Generate code to extract a byte-field from STR_RTX
1710 containing BITSIZE bits, starting at BITNUM,
1711 and put it in TARGET if possible (if TARGET is nonzero).
1712 Regardless of TARGET, we return the rtx for where the value is placed.
1714 STR_RTX is the structure containing the byte (a REG or MEM).
1715 UNSIGNEDP is nonzero if this is an unsigned bit field.
1716 MODE is the natural mode of the field value once extracted.
1717 TMODE is the mode the caller would like the value to have;
1718 but the value may be returned with type MODE instead.
1720 If a TARGET is specified and we can store in it at no extra cost,
1721 we do so, and return TARGET.
1722 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1723 if they are equally easy. */
1726 extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1727 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1728 enum machine_mode mode, enum machine_mode tmode)
1730 enum machine_mode mode1;
1732 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1733 if (GET_MODE_BITSIZE (GET_MODE (str_rtx)) > 0)
1734 mode1 = GET_MODE (str_rtx);
1735 else if (target && GET_MODE_BITSIZE (GET_MODE (target)) > 0)
1736 mode1 = GET_MODE (target);
1737 else
1738 mode1 = tmode;
1740 if (strict_volatile_bitfield_p (str_rtx, bitsize, bitnum, mode1, 0, 0))
1742 rtx result;
1744 /* Extraction of a full MODE1 value can be done with a load as long as
1745 the field is on a byte boundary and is sufficiently aligned. */
1746 if (simple_mem_bitfield_p (str_rtx, bitsize, bitnum, mode1))
1747 result = adjust_bitfield_address (str_rtx, mode1,
1748 bitnum / BITS_PER_UNIT);
1749 else
1751 str_rtx = narrow_bit_field_mem (str_rtx, mode1, bitsize, bitnum,
1752 &bitnum);
1753 result = extract_fixed_bit_field_1 (mode, str_rtx, bitsize, bitnum,
1754 target, unsignedp);
1757 return convert_extracted_bit_field (result, mode, tmode, unsignedp);
1760 return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp,
1761 target, mode, tmode, true);
1764 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1765 from bit BITNUM of OP0.
1767 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1768 If TARGET is nonzero, attempts to store the value there
1769 and return TARGET, but this is not guaranteed.
1770 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1772 static rtx
1773 extract_fixed_bit_field (enum machine_mode tmode, rtx op0,
1774 unsigned HOST_WIDE_INT bitsize,
1775 unsigned HOST_WIDE_INT bitnum, rtx target,
1776 int unsignedp)
1778 if (MEM_P (op0))
1780 enum machine_mode mode
1781 = get_best_mode (bitsize, bitnum, 0, 0, MEM_ALIGN (op0), word_mode,
1782 MEM_VOLATILE_P (op0));
1784 if (mode == VOIDmode)
1785 /* The only way this should occur is if the field spans word
1786 boundaries. */
1787 return extract_split_bit_field (op0, bitsize, bitnum, unsignedp);
1789 op0 = narrow_bit_field_mem (op0, mode, bitsize, bitnum, &bitnum);
1792 return extract_fixed_bit_field_1 (tmode, op0, bitsize, bitnum,
1793 target, unsignedp);
1796 /* Helper function for extract_fixed_bit_field, extracts
1797 the bit field always using the MODE of OP0. */
1799 static rtx
1800 extract_fixed_bit_field_1 (enum machine_mode tmode, rtx op0,
1801 unsigned HOST_WIDE_INT bitsize,
1802 unsigned HOST_WIDE_INT bitnum, rtx target,
1803 int unsignedp)
1805 enum machine_mode mode = GET_MODE (op0);
1806 gcc_assert (SCALAR_INT_MODE_P (mode));
1808 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1809 for invalid input, such as extract equivalent of f5 from
1810 gcc.dg/pr48335-2.c. */
1812 if (BYTES_BIG_ENDIAN)
1813 /* BITNUM is the distance between our msb and that of OP0.
1814 Convert it to the distance from the lsb. */
1815 bitnum = GET_MODE_BITSIZE (mode) - bitsize - bitnum;
1817 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
1818 We have reduced the big-endian case to the little-endian case. */
1820 if (unsignedp)
1822 if (bitnum)
1824 /* If the field does not already start at the lsb,
1825 shift it so it does. */
1826 /* Maybe propagate the target for the shift. */
1827 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
1828 if (tmode != mode)
1829 subtarget = 0;
1830 op0 = expand_shift (RSHIFT_EXPR, mode, op0, bitnum, subtarget, 1);
1832 /* Convert the value to the desired mode. */
1833 if (mode != tmode)
1834 op0 = convert_to_mode (tmode, op0, 1);
1836 /* Unless the msb of the field used to be the msb when we shifted,
1837 mask out the upper bits. */
1839 if (GET_MODE_BITSIZE (mode) != bitnum + bitsize)
1840 return expand_binop (GET_MODE (op0), and_optab, op0,
1841 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1842 target, 1, OPTAB_LIB_WIDEN);
1843 return op0;
1846 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1847 then arithmetic-shift its lsb to the lsb of the word. */
1848 op0 = force_reg (mode, op0);
1850 /* Find the narrowest integer mode that contains the field. */
1852 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1853 mode = GET_MODE_WIDER_MODE (mode))
1854 if (GET_MODE_BITSIZE (mode) >= bitsize + bitnum)
1856 op0 = convert_to_mode (mode, op0, 0);
1857 break;
1860 if (mode != tmode)
1861 target = 0;
1863 if (GET_MODE_BITSIZE (mode) != (bitsize + bitnum))
1865 int amount = GET_MODE_BITSIZE (mode) - (bitsize + bitnum);
1866 /* Maybe propagate the target for the shift. */
1867 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
1868 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1871 return expand_shift (RSHIFT_EXPR, mode, op0,
1872 GET_MODE_BITSIZE (mode) - bitsize, target, 0);
1875 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1876 VALUE << BITPOS. */
1878 static rtx
1879 lshift_value (enum machine_mode mode, unsigned HOST_WIDE_INT value,
1880 int bitpos)
1882 return immed_wide_int_const (wi::lshift (value, bitpos), mode);
1885 /* Extract a bit field that is split across two words
1886 and return an RTX for the result.
1888 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1889 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1890 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1892 static rtx
1893 extract_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1894 unsigned HOST_WIDE_INT bitpos, int unsignedp)
1896 unsigned int unit;
1897 unsigned int bitsdone = 0;
1898 rtx result = NULL_RTX;
1899 int first = 1;
1901 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1902 much at a time. */
1903 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
1904 unit = BITS_PER_WORD;
1905 else
1906 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1908 while (bitsdone < bitsize)
1910 unsigned HOST_WIDE_INT thissize;
1911 rtx part, word;
1912 unsigned HOST_WIDE_INT thispos;
1913 unsigned HOST_WIDE_INT offset;
1915 offset = (bitpos + bitsdone) / unit;
1916 thispos = (bitpos + bitsdone) % unit;
1918 /* THISSIZE must not overrun a word boundary. Otherwise,
1919 extract_fixed_bit_field will call us again, and we will mutually
1920 recurse forever. */
1921 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1922 thissize = MIN (thissize, unit - thispos);
1924 /* If OP0 is a register, then handle OFFSET here.
1926 When handling multiword bitfields, extract_bit_field may pass
1927 down a word_mode SUBREG of a larger REG for a bitfield that actually
1928 crosses a word boundary. Thus, for a SUBREG, we must find
1929 the current word starting from the base register. */
1930 if (GET_CODE (op0) == SUBREG)
1932 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1933 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1934 GET_MODE (SUBREG_REG (op0)));
1935 offset = 0;
1937 else if (REG_P (op0))
1939 word = operand_subword_force (op0, offset, GET_MODE (op0));
1940 offset = 0;
1942 else
1943 word = op0;
1945 /* Extract the parts in bit-counting order,
1946 whose meaning is determined by BYTES_PER_UNIT.
1947 OFFSET is in UNITs, and UNIT is in bits. */
1948 part = extract_fixed_bit_field (word_mode, word, thissize,
1949 offset * unit + thispos, 0, 1);
1950 bitsdone += thissize;
1952 /* Shift this part into place for the result. */
1953 if (BYTES_BIG_ENDIAN)
1955 if (bitsize != bitsdone)
1956 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1957 bitsize - bitsdone, 0, 1);
1959 else
1961 if (bitsdone != thissize)
1962 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1963 bitsdone - thissize, 0, 1);
1966 if (first)
1967 result = part;
1968 else
1969 /* Combine the parts with bitwise or. This works
1970 because we extracted each part as an unsigned bit field. */
1971 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1972 OPTAB_LIB_WIDEN);
1974 first = 0;
1977 /* Unsigned bit field: we are done. */
1978 if (unsignedp)
1979 return result;
1980 /* Signed bit field: sign-extend with two arithmetic shifts. */
1981 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1982 BITS_PER_WORD - bitsize, NULL_RTX, 0);
1983 return expand_shift (RSHIFT_EXPR, word_mode, result,
1984 BITS_PER_WORD - bitsize, NULL_RTX, 0);
1987 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
1988 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
1989 MODE, fill the upper bits with zeros. Fail if the layout of either
1990 mode is unknown (as for CC modes) or if the extraction would involve
1991 unprofitable mode punning. Return the value on success, otherwise
1992 return null.
1994 This is different from gen_lowpart* in these respects:
1996 - the returned value must always be considered an rvalue
1998 - when MODE is wider than SRC_MODE, the extraction involves
1999 a zero extension
2001 - when MODE is smaller than SRC_MODE, the extraction involves
2002 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2004 In other words, this routine performs a computation, whereas the
2005 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2006 operations. */
2009 extract_low_bits (enum machine_mode mode, enum machine_mode src_mode, rtx src)
2011 enum machine_mode int_mode, src_int_mode;
2013 if (mode == src_mode)
2014 return src;
2016 if (CONSTANT_P (src))
2018 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2019 fails, it will happily create (subreg (symbol_ref)) or similar
2020 invalid SUBREGs. */
2021 unsigned int byte = subreg_lowpart_offset (mode, src_mode);
2022 rtx ret = simplify_subreg (mode, src, src_mode, byte);
2023 if (ret)
2024 return ret;
2026 if (GET_MODE (src) == VOIDmode
2027 || !validate_subreg (mode, src_mode, src, byte))
2028 return NULL_RTX;
2030 src = force_reg (GET_MODE (src), src);
2031 return gen_rtx_SUBREG (mode, src, byte);
2034 if (GET_MODE_CLASS (mode) == MODE_CC || GET_MODE_CLASS (src_mode) == MODE_CC)
2035 return NULL_RTX;
2037 if (GET_MODE_BITSIZE (mode) == GET_MODE_BITSIZE (src_mode)
2038 && MODES_TIEABLE_P (mode, src_mode))
2040 rtx x = gen_lowpart_common (mode, src);
2041 if (x)
2042 return x;
2045 src_int_mode = int_mode_for_mode (src_mode);
2046 int_mode = int_mode_for_mode (mode);
2047 if (src_int_mode == BLKmode || int_mode == BLKmode)
2048 return NULL_RTX;
2050 if (!MODES_TIEABLE_P (src_int_mode, src_mode))
2051 return NULL_RTX;
2052 if (!MODES_TIEABLE_P (int_mode, mode))
2053 return NULL_RTX;
2055 src = gen_lowpart (src_int_mode, src);
2056 src = convert_modes (int_mode, src_int_mode, src, true);
2057 src = gen_lowpart (mode, src);
2058 return src;
2061 /* Add INC into TARGET. */
2063 void
2064 expand_inc (rtx target, rtx inc)
2066 rtx value = expand_binop (GET_MODE (target), add_optab,
2067 target, inc,
2068 target, 0, OPTAB_LIB_WIDEN);
2069 if (value != target)
2070 emit_move_insn (target, value);
2073 /* Subtract DEC from TARGET. */
2075 void
2076 expand_dec (rtx target, rtx dec)
2078 rtx value = expand_binop (GET_MODE (target), sub_optab,
2079 target, dec,
2080 target, 0, OPTAB_LIB_WIDEN);
2081 if (value != target)
2082 emit_move_insn (target, value);
2085 /* Output a shift instruction for expression code CODE,
2086 with SHIFTED being the rtx for the value to shift,
2087 and AMOUNT the rtx for the amount to shift by.
2088 Store the result in the rtx TARGET, if that is convenient.
2089 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2090 Return the rtx for where the value is. */
2092 static rtx
2093 expand_shift_1 (enum tree_code code, enum machine_mode mode, rtx shifted,
2094 rtx amount, rtx target, int unsignedp)
2096 rtx op1, temp = 0;
2097 int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
2098 int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
2099 optab lshift_optab = ashl_optab;
2100 optab rshift_arith_optab = ashr_optab;
2101 optab rshift_uns_optab = lshr_optab;
2102 optab lrotate_optab = rotl_optab;
2103 optab rrotate_optab = rotr_optab;
2104 enum machine_mode op1_mode;
2105 enum machine_mode scalar_mode = mode;
2106 int attempt;
2107 bool speed = optimize_insn_for_speed_p ();
2109 if (VECTOR_MODE_P (mode))
2110 scalar_mode = GET_MODE_INNER (mode);
2111 op1 = amount;
2112 op1_mode = GET_MODE (op1);
2114 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2115 shift amount is a vector, use the vector/vector shift patterns. */
2116 if (VECTOR_MODE_P (mode) && VECTOR_MODE_P (op1_mode))
2118 lshift_optab = vashl_optab;
2119 rshift_arith_optab = vashr_optab;
2120 rshift_uns_optab = vlshr_optab;
2121 lrotate_optab = vrotl_optab;
2122 rrotate_optab = vrotr_optab;
2125 /* Previously detected shift-counts computed by NEGATE_EXPR
2126 and shifted in the other direction; but that does not work
2127 on all machines. */
2129 if (SHIFT_COUNT_TRUNCATED)
2131 if (CONST_INT_P (op1)
2132 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
2133 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (scalar_mode)))
2134 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
2135 % GET_MODE_BITSIZE (scalar_mode));
2136 else if (GET_CODE (op1) == SUBREG
2137 && subreg_lowpart_p (op1)
2138 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1)))
2139 && SCALAR_INT_MODE_P (GET_MODE (op1)))
2140 op1 = SUBREG_REG (op1);
2143 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2144 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2145 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2146 amount instead. */
2147 if (rotate
2148 && CONST_INT_P (op1)
2149 && IN_RANGE (INTVAL (op1), GET_MODE_BITSIZE (scalar_mode) / 2 + left,
2150 GET_MODE_BITSIZE (scalar_mode) - 1))
2152 op1 = GEN_INT (GET_MODE_BITSIZE (scalar_mode) - INTVAL (op1));
2153 left = !left;
2154 code = left ? LROTATE_EXPR : RROTATE_EXPR;
2157 if (op1 == const0_rtx)
2158 return shifted;
2160 /* Check whether its cheaper to implement a left shift by a constant
2161 bit count by a sequence of additions. */
2162 if (code == LSHIFT_EXPR
2163 && CONST_INT_P (op1)
2164 && INTVAL (op1) > 0
2165 && INTVAL (op1) < GET_MODE_PRECISION (scalar_mode)
2166 && INTVAL (op1) < MAX_BITS_PER_WORD
2167 && (shift_cost (speed, mode, INTVAL (op1))
2168 > INTVAL (op1) * add_cost (speed, mode))
2169 && shift_cost (speed, mode, INTVAL (op1)) != MAX_COST)
2171 int i;
2172 for (i = 0; i < INTVAL (op1); i++)
2174 temp = force_reg (mode, shifted);
2175 shifted = expand_binop (mode, add_optab, temp, temp, NULL_RTX,
2176 unsignedp, OPTAB_LIB_WIDEN);
2178 return shifted;
2181 for (attempt = 0; temp == 0 && attempt < 3; attempt++)
2183 enum optab_methods methods;
2185 if (attempt == 0)
2186 methods = OPTAB_DIRECT;
2187 else if (attempt == 1)
2188 methods = OPTAB_WIDEN;
2189 else
2190 methods = OPTAB_LIB_WIDEN;
2192 if (rotate)
2194 /* Widening does not work for rotation. */
2195 if (methods == OPTAB_WIDEN)
2196 continue;
2197 else if (methods == OPTAB_LIB_WIDEN)
2199 /* If we have been unable to open-code this by a rotation,
2200 do it as the IOR of two shifts. I.e., to rotate A
2201 by N bits, compute
2202 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2203 where C is the bitsize of A.
2205 It is theoretically possible that the target machine might
2206 not be able to perform either shift and hence we would
2207 be making two libcalls rather than just the one for the
2208 shift (similarly if IOR could not be done). We will allow
2209 this extremely unlikely lossage to avoid complicating the
2210 code below. */
2212 rtx subtarget = target == shifted ? 0 : target;
2213 rtx new_amount, other_amount;
2214 rtx temp1;
2216 new_amount = op1;
2217 if (op1 == const0_rtx)
2218 return shifted;
2219 else if (CONST_INT_P (op1))
2220 other_amount = GEN_INT (GET_MODE_BITSIZE (scalar_mode)
2221 - INTVAL (op1));
2222 else
2224 other_amount
2225 = simplify_gen_unary (NEG, GET_MODE (op1),
2226 op1, GET_MODE (op1));
2227 HOST_WIDE_INT mask = GET_MODE_PRECISION (scalar_mode) - 1;
2228 other_amount
2229 = simplify_gen_binary (AND, GET_MODE (op1), other_amount,
2230 gen_int_mode (mask, GET_MODE (op1)));
2233 shifted = force_reg (mode, shifted);
2235 temp = expand_shift_1 (left ? LSHIFT_EXPR : RSHIFT_EXPR,
2236 mode, shifted, new_amount, 0, 1);
2237 temp1 = expand_shift_1 (left ? RSHIFT_EXPR : LSHIFT_EXPR,
2238 mode, shifted, other_amount,
2239 subtarget, 1);
2240 return expand_binop (mode, ior_optab, temp, temp1, target,
2241 unsignedp, methods);
2244 temp = expand_binop (mode,
2245 left ? lrotate_optab : rrotate_optab,
2246 shifted, op1, target, unsignedp, methods);
2248 else if (unsignedp)
2249 temp = expand_binop (mode,
2250 left ? lshift_optab : rshift_uns_optab,
2251 shifted, op1, target, unsignedp, methods);
2253 /* Do arithmetic shifts.
2254 Also, if we are going to widen the operand, we can just as well
2255 use an arithmetic right-shift instead of a logical one. */
2256 if (temp == 0 && ! rotate
2257 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2259 enum optab_methods methods1 = methods;
2261 /* If trying to widen a log shift to an arithmetic shift,
2262 don't accept an arithmetic shift of the same size. */
2263 if (unsignedp)
2264 methods1 = OPTAB_MUST_WIDEN;
2266 /* Arithmetic shift */
2268 temp = expand_binop (mode,
2269 left ? lshift_optab : rshift_arith_optab,
2270 shifted, op1, target, unsignedp, methods1);
2273 /* We used to try extzv here for logical right shifts, but that was
2274 only useful for one machine, the VAX, and caused poor code
2275 generation there for lshrdi3, so the code was deleted and a
2276 define_expand for lshrsi3 was added to vax.md. */
2279 gcc_assert (temp);
2280 return temp;
2283 /* Output a shift instruction for expression code CODE,
2284 with SHIFTED being the rtx for the value to shift,
2285 and AMOUNT the amount to shift by.
2286 Store the result in the rtx TARGET, if that is convenient.
2287 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2288 Return the rtx for where the value is. */
2291 expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
2292 int amount, rtx target, int unsignedp)
2294 return expand_shift_1 (code, mode,
2295 shifted, GEN_INT (amount), target, unsignedp);
2298 /* Output a shift instruction for expression code CODE,
2299 with SHIFTED being the rtx for the value to shift,
2300 and AMOUNT the tree for the amount to shift by.
2301 Store the result in the rtx TARGET, if that is convenient.
2302 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2303 Return the rtx for where the value is. */
2306 expand_variable_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
2307 tree amount, rtx target, int unsignedp)
2309 return expand_shift_1 (code, mode,
2310 shifted, expand_normal (amount), target, unsignedp);
2314 /* Indicates the type of fixup needed after a constant multiplication.
2315 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2316 the result should be negated, and ADD_VARIANT means that the
2317 multiplicand should be added to the result. */
2318 enum mult_variant {basic_variant, negate_variant, add_variant};
2320 static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT,
2321 const struct mult_cost *, enum machine_mode mode);
2322 static bool choose_mult_variant (enum machine_mode, HOST_WIDE_INT,
2323 struct algorithm *, enum mult_variant *, int);
2324 static rtx expand_mult_const (enum machine_mode, rtx, HOST_WIDE_INT, rtx,
2325 const struct algorithm *, enum mult_variant);
2326 static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
2327 static rtx extract_high_half (enum machine_mode, rtx);
2328 static rtx expmed_mult_highpart (enum machine_mode, rtx, rtx, rtx, int, int);
2329 static rtx expmed_mult_highpart_optab (enum machine_mode, rtx, rtx, rtx,
2330 int, int);
2331 /* Compute and return the best algorithm for multiplying by T.
2332 The algorithm must cost less than cost_limit
2333 If retval.cost >= COST_LIMIT, no algorithm was found and all
2334 other field of the returned struct are undefined.
2335 MODE is the machine mode of the multiplication. */
2337 static void
2338 synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
2339 const struct mult_cost *cost_limit, enum machine_mode mode)
2341 int m;
2342 struct algorithm *alg_in, *best_alg;
2343 struct mult_cost best_cost;
2344 struct mult_cost new_limit;
2345 int op_cost, op_latency;
2346 unsigned HOST_WIDE_INT orig_t = t;
2347 unsigned HOST_WIDE_INT q;
2348 int maxm, hash_index;
2349 bool cache_hit = false;
2350 enum alg_code cache_alg = alg_zero;
2351 bool speed = optimize_insn_for_speed_p ();
2352 enum machine_mode imode;
2353 struct alg_hash_entry *entry_ptr;
2355 /* Indicate that no algorithm is yet found. If no algorithm
2356 is found, this value will be returned and indicate failure. */
2357 alg_out->cost.cost = cost_limit->cost + 1;
2358 alg_out->cost.latency = cost_limit->latency + 1;
2360 if (cost_limit->cost < 0
2361 || (cost_limit->cost == 0 && cost_limit->latency <= 0))
2362 return;
2364 /* Be prepared for vector modes. */
2365 imode = GET_MODE_INNER (mode);
2366 if (imode == VOIDmode)
2367 imode = mode;
2369 maxm = MIN (BITS_PER_WORD, GET_MODE_BITSIZE (imode));
2371 /* Restrict the bits of "t" to the multiplication's mode. */
2372 t &= GET_MODE_MASK (imode);
2374 /* t == 1 can be done in zero cost. */
2375 if (t == 1)
2377 alg_out->ops = 1;
2378 alg_out->cost.cost = 0;
2379 alg_out->cost.latency = 0;
2380 alg_out->op[0] = alg_m;
2381 return;
2384 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2385 fail now. */
2386 if (t == 0)
2388 if (MULT_COST_LESS (cost_limit, zero_cost (speed)))
2389 return;
2390 else
2392 alg_out->ops = 1;
2393 alg_out->cost.cost = zero_cost (speed);
2394 alg_out->cost.latency = zero_cost (speed);
2395 alg_out->op[0] = alg_zero;
2396 return;
2400 /* We'll be needing a couple extra algorithm structures now. */
2402 alg_in = XALLOCA (struct algorithm);
2403 best_alg = XALLOCA (struct algorithm);
2404 best_cost = *cost_limit;
2406 /* Compute the hash index. */
2407 hash_index = (t ^ (unsigned int) mode ^ (speed * 256)) % NUM_ALG_HASH_ENTRIES;
2409 /* See if we already know what to do for T. */
2410 entry_ptr = alg_hash_entry_ptr (hash_index);
2411 if (entry_ptr->t == t
2412 && entry_ptr->mode == mode
2413 && entry_ptr->mode == mode
2414 && entry_ptr->speed == speed
2415 && entry_ptr->alg != alg_unknown)
2417 cache_alg = entry_ptr->alg;
2419 if (cache_alg == alg_impossible)
2421 /* The cache tells us that it's impossible to synthesize
2422 multiplication by T within entry_ptr->cost. */
2423 if (!CHEAPER_MULT_COST (&entry_ptr->cost, cost_limit))
2424 /* COST_LIMIT is at least as restrictive as the one
2425 recorded in the hash table, in which case we have no
2426 hope of synthesizing a multiplication. Just
2427 return. */
2428 return;
2430 /* If we get here, COST_LIMIT is less restrictive than the
2431 one recorded in the hash table, so we may be able to
2432 synthesize a multiplication. Proceed as if we didn't
2433 have the cache entry. */
2435 else
2437 if (CHEAPER_MULT_COST (cost_limit, &entry_ptr->cost))
2438 /* The cached algorithm shows that this multiplication
2439 requires more cost than COST_LIMIT. Just return. This
2440 way, we don't clobber this cache entry with
2441 alg_impossible but retain useful information. */
2442 return;
2444 cache_hit = true;
2446 switch (cache_alg)
2448 case alg_shift:
2449 goto do_alg_shift;
2451 case alg_add_t_m2:
2452 case alg_sub_t_m2:
2453 goto do_alg_addsub_t_m2;
2455 case alg_add_factor:
2456 case alg_sub_factor:
2457 goto do_alg_addsub_factor;
2459 case alg_add_t2_m:
2460 goto do_alg_add_t2_m;
2462 case alg_sub_t2_m:
2463 goto do_alg_sub_t2_m;
2465 default:
2466 gcc_unreachable ();
2471 /* If we have a group of zero bits at the low-order part of T, try
2472 multiplying by the remaining bits and then doing a shift. */
2474 if ((t & 1) == 0)
2476 do_alg_shift:
2477 m = floor_log2 (t & -t); /* m = number of low zero bits */
2478 if (m < maxm)
2480 q = t >> m;
2481 /* The function expand_shift will choose between a shift and
2482 a sequence of additions, so the observed cost is given as
2483 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2484 op_cost = m * add_cost (speed, mode);
2485 if (shift_cost (speed, mode, m) < op_cost)
2486 op_cost = shift_cost (speed, mode, m);
2487 new_limit.cost = best_cost.cost - op_cost;
2488 new_limit.latency = best_cost.latency - op_cost;
2489 synth_mult (alg_in, q, &new_limit, mode);
2491 alg_in->cost.cost += op_cost;
2492 alg_in->cost.latency += op_cost;
2493 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2495 struct algorithm *x;
2496 best_cost = alg_in->cost;
2497 x = alg_in, alg_in = best_alg, best_alg = x;
2498 best_alg->log[best_alg->ops] = m;
2499 best_alg->op[best_alg->ops] = alg_shift;
2502 /* See if treating ORIG_T as a signed number yields a better
2503 sequence. Try this sequence only for a negative ORIG_T
2504 as it would be useless for a non-negative ORIG_T. */
2505 if ((HOST_WIDE_INT) orig_t < 0)
2507 /* Shift ORIG_T as follows because a right shift of a
2508 negative-valued signed type is implementation
2509 defined. */
2510 q = ~(~orig_t >> m);
2511 /* The function expand_shift will choose between a shift
2512 and a sequence of additions, so the observed cost is
2513 given as MIN (m * add_cost(speed, mode),
2514 shift_cost(speed, mode, m)). */
2515 op_cost = m * add_cost (speed, mode);
2516 if (shift_cost (speed, mode, m) < op_cost)
2517 op_cost = shift_cost (speed, mode, m);
2518 new_limit.cost = best_cost.cost - op_cost;
2519 new_limit.latency = best_cost.latency - op_cost;
2520 synth_mult (alg_in, q, &new_limit, mode);
2522 alg_in->cost.cost += op_cost;
2523 alg_in->cost.latency += op_cost;
2524 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2526 struct algorithm *x;
2527 best_cost = alg_in->cost;
2528 x = alg_in, alg_in = best_alg, best_alg = x;
2529 best_alg->log[best_alg->ops] = m;
2530 best_alg->op[best_alg->ops] = alg_shift;
2534 if (cache_hit)
2535 goto done;
2538 /* If we have an odd number, add or subtract one. */
2539 if ((t & 1) != 0)
2541 unsigned HOST_WIDE_INT w;
2543 do_alg_addsub_t_m2:
2544 for (w = 1; (w & t) != 0; w <<= 1)
2546 /* If T was -1, then W will be zero after the loop. This is another
2547 case where T ends with ...111. Handling this with (T + 1) and
2548 subtract 1 produces slightly better code and results in algorithm
2549 selection much faster than treating it like the ...0111 case
2550 below. */
2551 if (w == 0
2552 || (w > 2
2553 /* Reject the case where t is 3.
2554 Thus we prefer addition in that case. */
2555 && t != 3))
2557 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2559 op_cost = add_cost (speed, mode);
2560 new_limit.cost = best_cost.cost - op_cost;
2561 new_limit.latency = best_cost.latency - op_cost;
2562 synth_mult (alg_in, t + 1, &new_limit, mode);
2564 alg_in->cost.cost += op_cost;
2565 alg_in->cost.latency += op_cost;
2566 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2568 struct algorithm *x;
2569 best_cost = alg_in->cost;
2570 x = alg_in, alg_in = best_alg, best_alg = x;
2571 best_alg->log[best_alg->ops] = 0;
2572 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2575 else
2577 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2579 op_cost = add_cost (speed, mode);
2580 new_limit.cost = best_cost.cost - op_cost;
2581 new_limit.latency = best_cost.latency - op_cost;
2582 synth_mult (alg_in, t - 1, &new_limit, mode);
2584 alg_in->cost.cost += op_cost;
2585 alg_in->cost.latency += op_cost;
2586 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2588 struct algorithm *x;
2589 best_cost = alg_in->cost;
2590 x = alg_in, alg_in = best_alg, best_alg = x;
2591 best_alg->log[best_alg->ops] = 0;
2592 best_alg->op[best_alg->ops] = alg_add_t_m2;
2596 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2597 quickly with a - a * n for some appropriate constant n. */
2598 m = exact_log2 (-orig_t + 1);
2599 if (m >= 0 && m < maxm)
2601 op_cost = shiftsub1_cost (speed, mode, m);
2602 new_limit.cost = best_cost.cost - op_cost;
2603 new_limit.latency = best_cost.latency - op_cost;
2604 synth_mult (alg_in, (unsigned HOST_WIDE_INT) (-orig_t + 1) >> m,
2605 &new_limit, mode);
2607 alg_in->cost.cost += op_cost;
2608 alg_in->cost.latency += op_cost;
2609 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2611 struct algorithm *x;
2612 best_cost = alg_in->cost;
2613 x = alg_in, alg_in = best_alg, best_alg = x;
2614 best_alg->log[best_alg->ops] = m;
2615 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2619 if (cache_hit)
2620 goto done;
2623 /* Look for factors of t of the form
2624 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2625 If we find such a factor, we can multiply by t using an algorithm that
2626 multiplies by q, shift the result by m and add/subtract it to itself.
2628 We search for large factors first and loop down, even if large factors
2629 are less probable than small; if we find a large factor we will find a
2630 good sequence quickly, and therefore be able to prune (by decreasing
2631 COST_LIMIT) the search. */
2633 do_alg_addsub_factor:
2634 for (m = floor_log2 (t - 1); m >= 2; m--)
2636 unsigned HOST_WIDE_INT d;
2638 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2639 if (t % d == 0 && t > d && m < maxm
2640 && (!cache_hit || cache_alg == alg_add_factor))
2642 /* If the target has a cheap shift-and-add instruction use
2643 that in preference to a shift insn followed by an add insn.
2644 Assume that the shift-and-add is "atomic" with a latency
2645 equal to its cost, otherwise assume that on superscalar
2646 hardware the shift may be executed concurrently with the
2647 earlier steps in the algorithm. */
2648 op_cost = add_cost (speed, mode) + shift_cost (speed, mode, m);
2649 if (shiftadd_cost (speed, mode, m) < op_cost)
2651 op_cost = shiftadd_cost (speed, mode, m);
2652 op_latency = op_cost;
2654 else
2655 op_latency = add_cost (speed, mode);
2657 new_limit.cost = best_cost.cost - op_cost;
2658 new_limit.latency = best_cost.latency - op_latency;
2659 synth_mult (alg_in, t / d, &new_limit, mode);
2661 alg_in->cost.cost += op_cost;
2662 alg_in->cost.latency += op_latency;
2663 if (alg_in->cost.latency < op_cost)
2664 alg_in->cost.latency = op_cost;
2665 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2667 struct algorithm *x;
2668 best_cost = alg_in->cost;
2669 x = alg_in, alg_in = best_alg, best_alg = x;
2670 best_alg->log[best_alg->ops] = m;
2671 best_alg->op[best_alg->ops] = alg_add_factor;
2673 /* Other factors will have been taken care of in the recursion. */
2674 break;
2677 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2678 if (t % d == 0 && t > d && m < maxm
2679 && (!cache_hit || cache_alg == alg_sub_factor))
2681 /* If the target has a cheap shift-and-subtract insn use
2682 that in preference to a shift insn followed by a sub insn.
2683 Assume that the shift-and-sub is "atomic" with a latency
2684 equal to it's cost, otherwise assume that on superscalar
2685 hardware the shift may be executed concurrently with the
2686 earlier steps in the algorithm. */
2687 op_cost = add_cost (speed, mode) + shift_cost (speed, mode, m);
2688 if (shiftsub0_cost (speed, mode, m) < op_cost)
2690 op_cost = shiftsub0_cost (speed, mode, m);
2691 op_latency = op_cost;
2693 else
2694 op_latency = add_cost (speed, mode);
2696 new_limit.cost = best_cost.cost - op_cost;
2697 new_limit.latency = best_cost.latency - op_latency;
2698 synth_mult (alg_in, t / d, &new_limit, mode);
2700 alg_in->cost.cost += op_cost;
2701 alg_in->cost.latency += op_latency;
2702 if (alg_in->cost.latency < op_cost)
2703 alg_in->cost.latency = op_cost;
2704 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2706 struct algorithm *x;
2707 best_cost = alg_in->cost;
2708 x = alg_in, alg_in = best_alg, best_alg = x;
2709 best_alg->log[best_alg->ops] = m;
2710 best_alg->op[best_alg->ops] = alg_sub_factor;
2712 break;
2715 if (cache_hit)
2716 goto done;
2718 /* Try shift-and-add (load effective address) instructions,
2719 i.e. do a*3, a*5, a*9. */
2720 if ((t & 1) != 0)
2722 do_alg_add_t2_m:
2723 q = t - 1;
2724 q = q & -q;
2725 m = exact_log2 (q);
2726 if (m >= 0 && m < maxm)
2728 op_cost = shiftadd_cost (speed, mode, m);
2729 new_limit.cost = best_cost.cost - op_cost;
2730 new_limit.latency = best_cost.latency - op_cost;
2731 synth_mult (alg_in, (t - 1) >> m, &new_limit, mode);
2733 alg_in->cost.cost += op_cost;
2734 alg_in->cost.latency += op_cost;
2735 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2737 struct algorithm *x;
2738 best_cost = alg_in->cost;
2739 x = alg_in, alg_in = best_alg, best_alg = x;
2740 best_alg->log[best_alg->ops] = m;
2741 best_alg->op[best_alg->ops] = alg_add_t2_m;
2744 if (cache_hit)
2745 goto done;
2747 do_alg_sub_t2_m:
2748 q = t + 1;
2749 q = q & -q;
2750 m = exact_log2 (q);
2751 if (m >= 0 && m < maxm)
2753 op_cost = shiftsub0_cost (speed, mode, m);
2754 new_limit.cost = best_cost.cost - op_cost;
2755 new_limit.latency = best_cost.latency - op_cost;
2756 synth_mult (alg_in, (t + 1) >> m, &new_limit, mode);
2758 alg_in->cost.cost += op_cost;
2759 alg_in->cost.latency += op_cost;
2760 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2762 struct algorithm *x;
2763 best_cost = alg_in->cost;
2764 x = alg_in, alg_in = best_alg, best_alg = x;
2765 best_alg->log[best_alg->ops] = m;
2766 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2769 if (cache_hit)
2770 goto done;
2773 done:
2774 /* If best_cost has not decreased, we have not found any algorithm. */
2775 if (!CHEAPER_MULT_COST (&best_cost, cost_limit))
2777 /* We failed to find an algorithm. Record alg_impossible for
2778 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2779 we are asked to find an algorithm for T within the same or
2780 lower COST_LIMIT, we can immediately return to the
2781 caller. */
2782 entry_ptr->t = t;
2783 entry_ptr->mode = mode;
2784 entry_ptr->speed = speed;
2785 entry_ptr->alg = alg_impossible;
2786 entry_ptr->cost = *cost_limit;
2787 return;
2790 /* Cache the result. */
2791 if (!cache_hit)
2793 entry_ptr->t = t;
2794 entry_ptr->mode = mode;
2795 entry_ptr->speed = speed;
2796 entry_ptr->alg = best_alg->op[best_alg->ops];
2797 entry_ptr->cost.cost = best_cost.cost;
2798 entry_ptr->cost.latency = best_cost.latency;
2801 /* If we are getting a too long sequence for `struct algorithm'
2802 to record, make this search fail. */
2803 if (best_alg->ops == MAX_BITS_PER_WORD)
2804 return;
2806 /* Copy the algorithm from temporary space to the space at alg_out.
2807 We avoid using structure assignment because the majority of
2808 best_alg is normally undefined, and this is a critical function. */
2809 alg_out->ops = best_alg->ops + 1;
2810 alg_out->cost = best_cost;
2811 memcpy (alg_out->op, best_alg->op,
2812 alg_out->ops * sizeof *alg_out->op);
2813 memcpy (alg_out->log, best_alg->log,
2814 alg_out->ops * sizeof *alg_out->log);
2817 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2818 Try three variations:
2820 - a shift/add sequence based on VAL itself
2821 - a shift/add sequence based on -VAL, followed by a negation
2822 - a shift/add sequence based on VAL - 1, followed by an addition.
2824 Return true if the cheapest of these cost less than MULT_COST,
2825 describing the algorithm in *ALG and final fixup in *VARIANT. */
2827 static bool
2828 choose_mult_variant (enum machine_mode mode, HOST_WIDE_INT val,
2829 struct algorithm *alg, enum mult_variant *variant,
2830 int mult_cost)
2832 struct algorithm alg2;
2833 struct mult_cost limit;
2834 int op_cost;
2835 bool speed = optimize_insn_for_speed_p ();
2837 /* Fail quickly for impossible bounds. */
2838 if (mult_cost < 0)
2839 return false;
2841 /* Ensure that mult_cost provides a reasonable upper bound.
2842 Any constant multiplication can be performed with less
2843 than 2 * bits additions. */
2844 op_cost = 2 * GET_MODE_UNIT_BITSIZE (mode) * add_cost (speed, mode);
2845 if (mult_cost > op_cost)
2846 mult_cost = op_cost;
2848 *variant = basic_variant;
2849 limit.cost = mult_cost;
2850 limit.latency = mult_cost;
2851 synth_mult (alg, val, &limit, mode);
2853 /* This works only if the inverted value actually fits in an
2854 `unsigned int' */
2855 if (HOST_BITS_PER_INT >= GET_MODE_UNIT_BITSIZE (mode))
2857 op_cost = neg_cost (speed, mode);
2858 if (MULT_COST_LESS (&alg->cost, mult_cost))
2860 limit.cost = alg->cost.cost - op_cost;
2861 limit.latency = alg->cost.latency - op_cost;
2863 else
2865 limit.cost = mult_cost - op_cost;
2866 limit.latency = mult_cost - op_cost;
2869 synth_mult (&alg2, -val, &limit, mode);
2870 alg2.cost.cost += op_cost;
2871 alg2.cost.latency += op_cost;
2872 if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost))
2873 *alg = alg2, *variant = negate_variant;
2876 /* This proves very useful for division-by-constant. */
2877 op_cost = add_cost (speed, mode);
2878 if (MULT_COST_LESS (&alg->cost, mult_cost))
2880 limit.cost = alg->cost.cost - op_cost;
2881 limit.latency = alg->cost.latency - op_cost;
2883 else
2885 limit.cost = mult_cost - op_cost;
2886 limit.latency = mult_cost - op_cost;
2889 synth_mult (&alg2, val - 1, &limit, mode);
2890 alg2.cost.cost += op_cost;
2891 alg2.cost.latency += op_cost;
2892 if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost))
2893 *alg = alg2, *variant = add_variant;
2895 return MULT_COST_LESS (&alg->cost, mult_cost);
2898 /* A subroutine of expand_mult, used for constant multiplications.
2899 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2900 convenient. Use the shift/add sequence described by ALG and apply
2901 the final fixup specified by VARIANT. */
2903 static rtx
2904 expand_mult_const (enum machine_mode mode, rtx op0, HOST_WIDE_INT val,
2905 rtx target, const struct algorithm *alg,
2906 enum mult_variant variant)
2908 HOST_WIDE_INT val_so_far;
2909 rtx_insn *insn;
2910 rtx accum, tem;
2911 int opno;
2912 enum machine_mode nmode;
2914 /* Avoid referencing memory over and over and invalid sharing
2915 on SUBREGs. */
2916 op0 = force_reg (mode, op0);
2918 /* ACCUM starts out either as OP0 or as a zero, depending on
2919 the first operation. */
2921 if (alg->op[0] == alg_zero)
2923 accum = copy_to_mode_reg (mode, CONST0_RTX (mode));
2924 val_so_far = 0;
2926 else if (alg->op[0] == alg_m)
2928 accum = copy_to_mode_reg (mode, op0);
2929 val_so_far = 1;
2931 else
2932 gcc_unreachable ();
2934 for (opno = 1; opno < alg->ops; opno++)
2936 int log = alg->log[opno];
2937 rtx shift_subtarget = optimize ? 0 : accum;
2938 rtx add_target
2939 = (opno == alg->ops - 1 && target != 0 && variant != add_variant
2940 && !optimize)
2941 ? target : 0;
2942 rtx accum_target = optimize ? 0 : accum;
2943 rtx accum_inner;
2945 switch (alg->op[opno])
2947 case alg_shift:
2948 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
2949 /* REG_EQUAL note will be attached to the following insn. */
2950 emit_move_insn (accum, tem);
2951 val_so_far <<= log;
2952 break;
2954 case alg_add_t_m2:
2955 tem = expand_shift (LSHIFT_EXPR, mode, op0, log, NULL_RTX, 0);
2956 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2957 add_target ? add_target : accum_target);
2958 val_so_far += (HOST_WIDE_INT) 1 << log;
2959 break;
2961 case alg_sub_t_m2:
2962 tem = expand_shift (LSHIFT_EXPR, mode, op0, log, NULL_RTX, 0);
2963 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2964 add_target ? add_target : accum_target);
2965 val_so_far -= (HOST_WIDE_INT) 1 << log;
2966 break;
2968 case alg_add_t2_m:
2969 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2970 log, shift_subtarget, 0);
2971 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2972 add_target ? add_target : accum_target);
2973 val_so_far = (val_so_far << log) + 1;
2974 break;
2976 case alg_sub_t2_m:
2977 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2978 log, shift_subtarget, 0);
2979 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2980 add_target ? add_target : accum_target);
2981 val_so_far = (val_so_far << log) - 1;
2982 break;
2984 case alg_add_factor:
2985 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
2986 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2987 add_target ? add_target : accum_target);
2988 val_so_far += val_so_far << log;
2989 break;
2991 case alg_sub_factor:
2992 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
2993 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
2994 (add_target
2995 ? add_target : (optimize ? 0 : tem)));
2996 val_so_far = (val_so_far << log) - val_so_far;
2997 break;
2999 default:
3000 gcc_unreachable ();
3003 if (SCALAR_INT_MODE_P (mode))
3005 /* Write a REG_EQUAL note on the last insn so that we can cse
3006 multiplication sequences. Note that if ACCUM is a SUBREG,
3007 we've set the inner register and must properly indicate that. */
3008 tem = op0, nmode = mode;
3009 accum_inner = accum;
3010 if (GET_CODE (accum) == SUBREG)
3012 accum_inner = SUBREG_REG (accum);
3013 nmode = GET_MODE (accum_inner);
3014 tem = gen_lowpart (nmode, op0);
3017 insn = get_last_insn ();
3018 set_dst_reg_note (insn, REG_EQUAL,
3019 gen_rtx_MULT (nmode, tem,
3020 gen_int_mode (val_so_far, nmode)),
3021 accum_inner);
3025 if (variant == negate_variant)
3027 val_so_far = -val_so_far;
3028 accum = expand_unop (mode, neg_optab, accum, target, 0);
3030 else if (variant == add_variant)
3032 val_so_far = val_so_far + 1;
3033 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
3036 /* Compare only the bits of val and val_so_far that are significant
3037 in the result mode, to avoid sign-/zero-extension confusion. */
3038 nmode = GET_MODE_INNER (mode);
3039 if (nmode == VOIDmode)
3040 nmode = mode;
3041 val &= GET_MODE_MASK (nmode);
3042 val_so_far &= GET_MODE_MASK (nmode);
3043 gcc_assert (val == val_so_far);
3045 return accum;
3048 /* Perform a multiplication and return an rtx for the result.
3049 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3050 TARGET is a suggestion for where to store the result (an rtx).
3052 We check specially for a constant integer as OP1.
3053 If you want this check for OP0 as well, then before calling
3054 you should swap the two operands if OP0 would be constant. */
3057 expand_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
3058 int unsignedp)
3060 enum mult_variant variant;
3061 struct algorithm algorithm;
3062 rtx scalar_op1;
3063 int max_cost;
3064 bool speed = optimize_insn_for_speed_p ();
3065 bool do_trapv = flag_trapv && SCALAR_INT_MODE_P (mode) && !unsignedp;
3067 if (CONSTANT_P (op0))
3069 rtx temp = op0;
3070 op0 = op1;
3071 op1 = temp;
3074 /* For vectors, there are several simplifications that can be made if
3075 all elements of the vector constant are identical. */
3076 scalar_op1 = op1;
3077 if (GET_CODE (op1) == CONST_VECTOR)
3079 int i, n = CONST_VECTOR_NUNITS (op1);
3080 scalar_op1 = CONST_VECTOR_ELT (op1, 0);
3081 for (i = 1; i < n; ++i)
3082 if (!rtx_equal_p (scalar_op1, CONST_VECTOR_ELT (op1, i)))
3083 goto skip_scalar;
3086 if (INTEGRAL_MODE_P (mode))
3088 rtx fake_reg;
3089 HOST_WIDE_INT coeff;
3090 bool is_neg;
3091 int mode_bitsize;
3093 if (op1 == CONST0_RTX (mode))
3094 return op1;
3095 if (op1 == CONST1_RTX (mode))
3096 return op0;
3097 if (op1 == CONSTM1_RTX (mode))
3098 return expand_unop (mode, do_trapv ? negv_optab : neg_optab,
3099 op0, target, 0);
3101 if (do_trapv)
3102 goto skip_synth;
3104 /* If mode is integer vector mode, check if the backend supports
3105 vector lshift (by scalar or vector) at all. If not, we can't use
3106 synthetized multiply. */
3107 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
3108 && optab_handler (vashl_optab, mode) == CODE_FOR_nothing
3109 && optab_handler (ashl_optab, mode) == CODE_FOR_nothing)
3110 goto skip_synth;
3112 /* These are the operations that are potentially turned into
3113 a sequence of shifts and additions. */
3114 mode_bitsize = GET_MODE_UNIT_BITSIZE (mode);
3116 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3117 less than or equal in size to `unsigned int' this doesn't matter.
3118 If the mode is larger than `unsigned int', then synth_mult works
3119 only if the constant value exactly fits in an `unsigned int' without
3120 any truncation. This means that multiplying by negative values does
3121 not work; results are off by 2^32 on a 32 bit machine. */
3122 if (CONST_INT_P (scalar_op1))
3124 coeff = INTVAL (scalar_op1);
3125 is_neg = coeff < 0;
3127 #if TARGET_SUPPORTS_WIDE_INT
3128 else if (CONST_WIDE_INT_P (scalar_op1))
3129 #else
3130 else if (CONST_DOUBLE_AS_INT_P (scalar_op1))
3131 #endif
3133 int shift = wi::exact_log2 (std::make_pair (scalar_op1, mode));
3134 /* Perfect power of 2 (other than 1, which is handled above). */
3135 if (shift > 0)
3136 return expand_shift (LSHIFT_EXPR, mode, op0,
3137 shift, target, unsignedp);
3138 else
3139 goto skip_synth;
3141 else
3142 goto skip_synth;
3144 /* We used to test optimize here, on the grounds that it's better to
3145 produce a smaller program when -O is not used. But this causes
3146 such a terrible slowdown sometimes that it seems better to always
3147 use synth_mult. */
3149 /* Special case powers of two. */
3150 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff)
3151 && !(is_neg && mode_bitsize > HOST_BITS_PER_WIDE_INT))
3152 return expand_shift (LSHIFT_EXPR, mode, op0,
3153 floor_log2 (coeff), target, unsignedp);
3155 fake_reg = gen_raw_REG (mode, LAST_VIRTUAL_REGISTER + 1);
3157 /* Attempt to handle multiplication of DImode values by negative
3158 coefficients, by performing the multiplication by a positive
3159 multiplier and then inverting the result. */
3160 if (is_neg && mode_bitsize > HOST_BITS_PER_WIDE_INT)
3162 /* Its safe to use -coeff even for INT_MIN, as the
3163 result is interpreted as an unsigned coefficient.
3164 Exclude cost of op0 from max_cost to match the cost
3165 calculation of the synth_mult. */
3166 coeff = -(unsigned HOST_WIDE_INT) coeff;
3167 max_cost = (set_src_cost (gen_rtx_MULT (mode, fake_reg, op1), speed)
3168 - neg_cost (speed, mode));
3169 if (max_cost <= 0)
3170 goto skip_synth;
3172 /* Special case powers of two. */
3173 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
3175 rtx temp = expand_shift (LSHIFT_EXPR, mode, op0,
3176 floor_log2 (coeff), target, unsignedp);
3177 return expand_unop (mode, neg_optab, temp, target, 0);
3180 if (choose_mult_variant (mode, coeff, &algorithm, &variant,
3181 max_cost))
3183 rtx temp = expand_mult_const (mode, op0, coeff, NULL_RTX,
3184 &algorithm, variant);
3185 return expand_unop (mode, neg_optab, temp, target, 0);
3187 goto skip_synth;
3190 /* Exclude cost of op0 from max_cost to match the cost
3191 calculation of the synth_mult. */
3192 max_cost = set_src_cost (gen_rtx_MULT (mode, fake_reg, op1), speed);
3193 if (choose_mult_variant (mode, coeff, &algorithm, &variant, max_cost))
3194 return expand_mult_const (mode, op0, coeff, target,
3195 &algorithm, variant);
3197 skip_synth:
3199 /* Expand x*2.0 as x+x. */
3200 if (CONST_DOUBLE_AS_FLOAT_P (scalar_op1))
3202 REAL_VALUE_TYPE d;
3203 REAL_VALUE_FROM_CONST_DOUBLE (d, scalar_op1);
3205 if (REAL_VALUES_EQUAL (d, dconst2))
3207 op0 = force_reg (GET_MODE (op0), op0);
3208 return expand_binop (mode, add_optab, op0, op0,
3209 target, unsignedp, OPTAB_LIB_WIDEN);
3212 skip_scalar:
3214 /* This used to use umul_optab if unsigned, but for non-widening multiply
3215 there is no difference between signed and unsigned. */
3216 op0 = expand_binop (mode, do_trapv ? smulv_optab : smul_optab,
3217 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
3218 gcc_assert (op0);
3219 return op0;
3222 /* Return a cost estimate for multiplying a register by the given
3223 COEFFicient in the given MODE and SPEED. */
3226 mult_by_coeff_cost (HOST_WIDE_INT coeff, enum machine_mode mode, bool speed)
3228 int max_cost;
3229 struct algorithm algorithm;
3230 enum mult_variant variant;
3232 rtx fake_reg = gen_raw_REG (mode, LAST_VIRTUAL_REGISTER + 1);
3233 max_cost = set_src_cost (gen_rtx_MULT (mode, fake_reg, fake_reg), speed);
3234 if (choose_mult_variant (mode, coeff, &algorithm, &variant, max_cost))
3235 return algorithm.cost.cost;
3236 else
3237 return max_cost;
3240 /* Perform a widening multiplication and return an rtx for the result.
3241 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3242 TARGET is a suggestion for where to store the result (an rtx).
3243 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3244 or smul_widen_optab.
3246 We check specially for a constant integer as OP1, comparing the
3247 cost of a widening multiply against the cost of a sequence of shifts
3248 and adds. */
3251 expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
3252 int unsignedp, optab this_optab)
3254 bool speed = optimize_insn_for_speed_p ();
3255 rtx cop1;
3257 if (CONST_INT_P (op1)
3258 && GET_MODE (op0) != VOIDmode
3259 && (cop1 = convert_modes (mode, GET_MODE (op0), op1,
3260 this_optab == umul_widen_optab))
3261 && CONST_INT_P (cop1)
3262 && (INTVAL (cop1) >= 0
3263 || HWI_COMPUTABLE_MODE_P (mode)))
3265 HOST_WIDE_INT coeff = INTVAL (cop1);
3266 int max_cost;
3267 enum mult_variant variant;
3268 struct algorithm algorithm;
3270 /* Special case powers of two. */
3271 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
3273 op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
3274 return expand_shift (LSHIFT_EXPR, mode, op0,
3275 floor_log2 (coeff), target, unsignedp);
3278 /* Exclude cost of op0 from max_cost to match the cost
3279 calculation of the synth_mult. */
3280 max_cost = mul_widen_cost (speed, mode);
3281 if (choose_mult_variant (mode, coeff, &algorithm, &variant,
3282 max_cost))
3284 op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
3285 return expand_mult_const (mode, op0, coeff, target,
3286 &algorithm, variant);
3289 return expand_binop (mode, this_optab, op0, op1, target,
3290 unsignedp, OPTAB_LIB_WIDEN);
3293 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3294 replace division by D, and put the least significant N bits of the result
3295 in *MULTIPLIER_PTR and return the most significant bit.
3297 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3298 needed precision is in PRECISION (should be <= N).
3300 PRECISION should be as small as possible so this function can choose
3301 multiplier more freely.
3303 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3304 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3306 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3307 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3309 unsigned HOST_WIDE_INT
3310 choose_multiplier (unsigned HOST_WIDE_INT d, int n, int precision,
3311 unsigned HOST_WIDE_INT *multiplier_ptr,
3312 int *post_shift_ptr, int *lgup_ptr)
3314 int lgup, post_shift;
3315 int pow, pow2;
3317 /* lgup = ceil(log2(divisor)); */
3318 lgup = ceil_log2 (d);
3320 gcc_assert (lgup <= n);
3322 pow = n + lgup;
3323 pow2 = n + lgup - precision;
3325 /* mlow = 2^(N + lgup)/d */
3326 wide_int val = wi::set_bit_in_zero (pow, HOST_BITS_PER_DOUBLE_INT);
3327 wide_int mlow = wi::udiv_trunc (val, d);
3329 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3330 val |= wi::set_bit_in_zero (pow2, HOST_BITS_PER_DOUBLE_INT);
3331 wide_int mhigh = wi::udiv_trunc (val, d);
3333 /* If precision == N, then mlow, mhigh exceed 2^N
3334 (but they do not exceed 2^(N+1)). */
3336 /* Reduce to lowest terms. */
3337 for (post_shift = lgup; post_shift > 0; post_shift--)
3339 unsigned HOST_WIDE_INT ml_lo = wi::extract_uhwi (mlow, 1,
3340 HOST_BITS_PER_WIDE_INT);
3341 unsigned HOST_WIDE_INT mh_lo = wi::extract_uhwi (mhigh, 1,
3342 HOST_BITS_PER_WIDE_INT);
3343 if (ml_lo >= mh_lo)
3344 break;
3346 mlow = wi::uhwi (ml_lo, HOST_BITS_PER_DOUBLE_INT);
3347 mhigh = wi::uhwi (mh_lo, HOST_BITS_PER_DOUBLE_INT);
3350 *post_shift_ptr = post_shift;
3351 *lgup_ptr = lgup;
3352 if (n < HOST_BITS_PER_WIDE_INT)
3354 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
3355 *multiplier_ptr = mhigh.to_uhwi () & mask;
3356 return mhigh.to_uhwi () >= mask;
3358 else
3360 *multiplier_ptr = mhigh.to_uhwi ();
3361 return wi::extract_uhwi (mhigh, HOST_BITS_PER_WIDE_INT, 1);
3365 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3366 congruent to 1 (mod 2**N). */
3368 static unsigned HOST_WIDE_INT
3369 invert_mod2n (unsigned HOST_WIDE_INT x, int n)
3371 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3373 /* The algorithm notes that the choice y = x satisfies
3374 x*y == 1 mod 2^3, since x is assumed odd.
3375 Each iteration doubles the number of bits of significance in y. */
3377 unsigned HOST_WIDE_INT mask;
3378 unsigned HOST_WIDE_INT y = x;
3379 int nbit = 3;
3381 mask = (n == HOST_BITS_PER_WIDE_INT
3382 ? ~(unsigned HOST_WIDE_INT) 0
3383 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
3385 while (nbit < n)
3387 y = y * (2 - x*y) & mask; /* Modulo 2^N */
3388 nbit *= 2;
3390 return y;
3393 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3394 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3395 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3396 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3397 become signed.
3399 The result is put in TARGET if that is convenient.
3401 MODE is the mode of operation. */
3404 expand_mult_highpart_adjust (enum machine_mode mode, rtx adj_operand, rtx op0,
3405 rtx op1, rtx target, int unsignedp)
3407 rtx tem;
3408 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
3410 tem = expand_shift (RSHIFT_EXPR, mode, op0,
3411 GET_MODE_BITSIZE (mode) - 1, NULL_RTX, 0);
3412 tem = expand_and (mode, tem, op1, NULL_RTX);
3413 adj_operand
3414 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
3415 adj_operand);
3417 tem = expand_shift (RSHIFT_EXPR, mode, op1,
3418 GET_MODE_BITSIZE (mode) - 1, NULL_RTX, 0);
3419 tem = expand_and (mode, tem, op0, NULL_RTX);
3420 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
3421 target);
3423 return target;
3426 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3428 static rtx
3429 extract_high_half (enum machine_mode mode, rtx op)
3431 enum machine_mode wider_mode;
3433 if (mode == word_mode)
3434 return gen_highpart (mode, op);
3436 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3438 wider_mode = GET_MODE_WIDER_MODE (mode);
3439 op = expand_shift (RSHIFT_EXPR, wider_mode, op,
3440 GET_MODE_BITSIZE (mode), 0, 1);
3441 return convert_modes (mode, wider_mode, op, 0);
3444 /* Like expmed_mult_highpart, but only consider using a multiplication
3445 optab. OP1 is an rtx for the constant operand. */
3447 static rtx
3448 expmed_mult_highpart_optab (enum machine_mode mode, rtx op0, rtx op1,
3449 rtx target, int unsignedp, int max_cost)
3451 rtx narrow_op1 = gen_int_mode (INTVAL (op1), mode);
3452 enum machine_mode wider_mode;
3453 optab moptab;
3454 rtx tem;
3455 int size;
3456 bool speed = optimize_insn_for_speed_p ();
3458 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3460 wider_mode = GET_MODE_WIDER_MODE (mode);
3461 size = GET_MODE_BITSIZE (mode);
3463 /* Firstly, try using a multiplication insn that only generates the needed
3464 high part of the product, and in the sign flavor of unsignedp. */
3465 if (mul_highpart_cost (speed, mode) < max_cost)
3467 moptab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
3468 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
3469 unsignedp, OPTAB_DIRECT);
3470 if (tem)
3471 return tem;
3474 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3475 Need to adjust the result after the multiplication. */
3476 if (size - 1 < BITS_PER_WORD
3477 && (mul_highpart_cost (speed, mode)
3478 + 2 * shift_cost (speed, mode, size-1)
3479 + 4 * add_cost (speed, mode) < max_cost))
3481 moptab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
3482 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
3483 unsignedp, OPTAB_DIRECT);
3484 if (tem)
3485 /* We used the wrong signedness. Adjust the result. */
3486 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3487 tem, unsignedp);
3490 /* Try widening multiplication. */
3491 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
3492 if (widening_optab_handler (moptab, wider_mode, mode) != CODE_FOR_nothing
3493 && mul_widen_cost (speed, wider_mode) < max_cost)
3495 tem = expand_binop (wider_mode, moptab, op0, narrow_op1, 0,
3496 unsignedp, OPTAB_WIDEN);
3497 if (tem)
3498 return extract_high_half (mode, tem);
3501 /* Try widening the mode and perform a non-widening multiplication. */
3502 if (optab_handler (smul_optab, wider_mode) != CODE_FOR_nothing
3503 && size - 1 < BITS_PER_WORD
3504 && (mul_cost (speed, wider_mode) + shift_cost (speed, mode, size-1)
3505 < max_cost))
3507 rtx_insn *insns;
3508 rtx wop0, wop1;
3510 /* We need to widen the operands, for example to ensure the
3511 constant multiplier is correctly sign or zero extended.
3512 Use a sequence to clean-up any instructions emitted by
3513 the conversions if things don't work out. */
3514 start_sequence ();
3515 wop0 = convert_modes (wider_mode, mode, op0, unsignedp);
3516 wop1 = convert_modes (wider_mode, mode, op1, unsignedp);
3517 tem = expand_binop (wider_mode, smul_optab, wop0, wop1, 0,
3518 unsignedp, OPTAB_WIDEN);
3519 insns = get_insns ();
3520 end_sequence ();
3522 if (tem)
3524 emit_insn (insns);
3525 return extract_high_half (mode, tem);
3529 /* Try widening multiplication of opposite signedness, and adjust. */
3530 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
3531 if (widening_optab_handler (moptab, wider_mode, mode) != CODE_FOR_nothing
3532 && size - 1 < BITS_PER_WORD
3533 && (mul_widen_cost (speed, wider_mode)
3534 + 2 * shift_cost (speed, mode, size-1)
3535 + 4 * add_cost (speed, mode) < max_cost))
3537 tem = expand_binop (wider_mode, moptab, op0, narrow_op1,
3538 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
3539 if (tem != 0)
3541 tem = extract_high_half (mode, tem);
3542 /* We used the wrong signedness. Adjust the result. */
3543 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3544 target, unsignedp);
3548 return 0;
3551 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3552 putting the high half of the result in TARGET if that is convenient,
3553 and return where the result is. If the operation can not be performed,
3554 0 is returned.
3556 MODE is the mode of operation and result.
3558 UNSIGNEDP nonzero means unsigned multiply.
3560 MAX_COST is the total allowed cost for the expanded RTL. */
3562 static rtx
3563 expmed_mult_highpart (enum machine_mode mode, rtx op0, rtx op1,
3564 rtx target, int unsignedp, int max_cost)
3566 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
3567 unsigned HOST_WIDE_INT cnst1;
3568 int extra_cost;
3569 bool sign_adjust = false;
3570 enum mult_variant variant;
3571 struct algorithm alg;
3572 rtx tem;
3573 bool speed = optimize_insn_for_speed_p ();
3575 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3576 /* We can't support modes wider than HOST_BITS_PER_INT. */
3577 gcc_assert (HWI_COMPUTABLE_MODE_P (mode));
3579 cnst1 = INTVAL (op1) & GET_MODE_MASK (mode);
3581 /* We can't optimize modes wider than BITS_PER_WORD.
3582 ??? We might be able to perform double-word arithmetic if
3583 mode == word_mode, however all the cost calculations in
3584 synth_mult etc. assume single-word operations. */
3585 if (GET_MODE_BITSIZE (wider_mode) > BITS_PER_WORD)
3586 return expmed_mult_highpart_optab (mode, op0, op1, target,
3587 unsignedp, max_cost);
3589 extra_cost = shift_cost (speed, mode, GET_MODE_BITSIZE (mode) - 1);
3591 /* Check whether we try to multiply by a negative constant. */
3592 if (!unsignedp && ((cnst1 >> (GET_MODE_BITSIZE (mode) - 1)) & 1))
3594 sign_adjust = true;
3595 extra_cost += add_cost (speed, mode);
3598 /* See whether shift/add multiplication is cheap enough. */
3599 if (choose_mult_variant (wider_mode, cnst1, &alg, &variant,
3600 max_cost - extra_cost))
3602 /* See whether the specialized multiplication optabs are
3603 cheaper than the shift/add version. */
3604 tem = expmed_mult_highpart_optab (mode, op0, op1, target, unsignedp,
3605 alg.cost.cost + extra_cost);
3606 if (tem)
3607 return tem;
3609 tem = convert_to_mode (wider_mode, op0, unsignedp);
3610 tem = expand_mult_const (wider_mode, tem, cnst1, 0, &alg, variant);
3611 tem = extract_high_half (mode, tem);
3613 /* Adjust result for signedness. */
3614 if (sign_adjust)
3615 tem = force_operand (gen_rtx_MINUS (mode, tem, op0), tem);
3617 return tem;
3619 return expmed_mult_highpart_optab (mode, op0, op1, target,
3620 unsignedp, max_cost);
3624 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3626 static rtx
3627 expand_smod_pow2 (enum machine_mode mode, rtx op0, HOST_WIDE_INT d)
3629 rtx result, temp, shift;
3630 rtx_code_label *label;
3631 int logd;
3632 int prec = GET_MODE_PRECISION (mode);
3634 logd = floor_log2 (d);
3635 result = gen_reg_rtx (mode);
3637 /* Avoid conditional branches when they're expensive. */
3638 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3639 && optimize_insn_for_speed_p ())
3641 rtx signmask = emit_store_flag (result, LT, op0, const0_rtx,
3642 mode, 0, -1);
3643 if (signmask)
3645 HOST_WIDE_INT masklow = ((HOST_WIDE_INT) 1 << logd) - 1;
3646 signmask = force_reg (mode, signmask);
3647 shift = GEN_INT (GET_MODE_BITSIZE (mode) - logd);
3649 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3650 which instruction sequence to use. If logical right shifts
3651 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3652 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3654 temp = gen_rtx_LSHIFTRT (mode, result, shift);
3655 if (optab_handler (lshr_optab, mode) == CODE_FOR_nothing
3656 || (set_src_cost (temp, optimize_insn_for_speed_p ())
3657 > COSTS_N_INSNS (2)))
3659 temp = expand_binop (mode, xor_optab, op0, signmask,
3660 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3661 temp = expand_binop (mode, sub_optab, temp, signmask,
3662 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3663 temp = expand_binop (mode, and_optab, temp,
3664 gen_int_mode (masklow, mode),
3665 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3666 temp = expand_binop (mode, xor_optab, temp, signmask,
3667 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3668 temp = expand_binop (mode, sub_optab, temp, signmask,
3669 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3671 else
3673 signmask = expand_binop (mode, lshr_optab, signmask, shift,
3674 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3675 signmask = force_reg (mode, signmask);
3677 temp = expand_binop (mode, add_optab, op0, signmask,
3678 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3679 temp = expand_binop (mode, and_optab, temp,
3680 gen_int_mode (masklow, mode),
3681 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3682 temp = expand_binop (mode, sub_optab, temp, signmask,
3683 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3685 return temp;
3689 /* Mask contains the mode's signbit and the significant bits of the
3690 modulus. By including the signbit in the operation, many targets
3691 can avoid an explicit compare operation in the following comparison
3692 against zero. */
3693 wide_int mask = wi::mask (logd, false, prec);
3694 mask = wi::set_bit (mask, prec - 1);
3696 temp = expand_binop (mode, and_optab, op0,
3697 immed_wide_int_const (mask, mode),
3698 result, 1, OPTAB_LIB_WIDEN);
3699 if (temp != result)
3700 emit_move_insn (result, temp);
3702 label = gen_label_rtx ();
3703 do_cmp_and_jump (result, const0_rtx, GE, mode, label);
3705 temp = expand_binop (mode, sub_optab, result, const1_rtx, result,
3706 0, OPTAB_LIB_WIDEN);
3708 mask = wi::mask (logd, true, prec);
3709 temp = expand_binop (mode, ior_optab, temp,
3710 immed_wide_int_const (mask, mode),
3711 result, 1, OPTAB_LIB_WIDEN);
3712 temp = expand_binop (mode, add_optab, temp, const1_rtx, result,
3713 0, OPTAB_LIB_WIDEN);
3714 if (temp != result)
3715 emit_move_insn (result, temp);
3716 emit_label (label);
3717 return result;
3720 /* Expand signed division of OP0 by a power of two D in mode MODE.
3721 This routine is only called for positive values of D. */
3723 static rtx
3724 expand_sdiv_pow2 (enum machine_mode mode, rtx op0, HOST_WIDE_INT d)
3726 rtx temp;
3727 rtx_code_label *label;
3728 int logd;
3730 logd = floor_log2 (d);
3732 if (d == 2
3733 && BRANCH_COST (optimize_insn_for_speed_p (),
3734 false) >= 1)
3736 temp = gen_reg_rtx (mode);
3737 temp = emit_store_flag (temp, LT, op0, const0_rtx, mode, 0, 1);
3738 temp = expand_binop (mode, add_optab, temp, op0, NULL_RTX,
3739 0, OPTAB_LIB_WIDEN);
3740 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
3743 #ifdef HAVE_conditional_move
3744 if (BRANCH_COST (optimize_insn_for_speed_p (), false)
3745 >= 2)
3747 rtx temp2;
3749 start_sequence ();
3750 temp2 = copy_to_mode_reg (mode, op0);
3751 temp = expand_binop (mode, add_optab, temp2, gen_int_mode (d - 1, mode),
3752 NULL_RTX, 0, OPTAB_LIB_WIDEN);
3753 temp = force_reg (mode, temp);
3755 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3756 temp2 = emit_conditional_move (temp2, LT, temp2, const0_rtx,
3757 mode, temp, temp2, mode, 0);
3758 if (temp2)
3760 rtx_insn *seq = get_insns ();
3761 end_sequence ();
3762 emit_insn (seq);
3763 return expand_shift (RSHIFT_EXPR, mode, temp2, logd, NULL_RTX, 0);
3765 end_sequence ();
3767 #endif
3769 if (BRANCH_COST (optimize_insn_for_speed_p (),
3770 false) >= 2)
3772 int ushift = GET_MODE_BITSIZE (mode) - logd;
3774 temp = gen_reg_rtx (mode);
3775 temp = emit_store_flag (temp, LT, op0, const0_rtx, mode, 0, -1);
3776 if (GET_MODE_BITSIZE (mode) >= BITS_PER_WORD
3777 || shift_cost (optimize_insn_for_speed_p (), mode, ushift)
3778 > COSTS_N_INSNS (1))
3779 temp = expand_binop (mode, and_optab, temp, gen_int_mode (d - 1, mode),
3780 NULL_RTX, 0, OPTAB_LIB_WIDEN);
3781 else
3782 temp = expand_shift (RSHIFT_EXPR, mode, temp,
3783 ushift, NULL_RTX, 1);
3784 temp = expand_binop (mode, add_optab, temp, op0, NULL_RTX,
3785 0, OPTAB_LIB_WIDEN);
3786 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
3789 label = gen_label_rtx ();
3790 temp = copy_to_mode_reg (mode, op0);
3791 do_cmp_and_jump (temp, const0_rtx, GE, mode, label);
3792 expand_inc (temp, gen_int_mode (d - 1, mode));
3793 emit_label (label);
3794 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
3797 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3798 if that is convenient, and returning where the result is.
3799 You may request either the quotient or the remainder as the result;
3800 specify REM_FLAG nonzero to get the remainder.
3802 CODE is the expression code for which kind of division this is;
3803 it controls how rounding is done. MODE is the machine mode to use.
3804 UNSIGNEDP nonzero means do unsigned division. */
3806 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3807 and then correct it by or'ing in missing high bits
3808 if result of ANDI is nonzero.
3809 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3810 This could optimize to a bfexts instruction.
3811 But C doesn't use these operations, so their optimizations are
3812 left for later. */
3813 /* ??? For modulo, we don't actually need the highpart of the first product,
3814 the low part will do nicely. And for small divisors, the second multiply
3815 can also be a low-part only multiply or even be completely left out.
3816 E.g. to calculate the remainder of a division by 3 with a 32 bit
3817 multiply, multiply with 0x55555556 and extract the upper two bits;
3818 the result is exact for inputs up to 0x1fffffff.
3819 The input range can be reduced by using cross-sum rules.
3820 For odd divisors >= 3, the following table gives right shift counts
3821 so that if a number is shifted by an integer multiple of the given
3822 amount, the remainder stays the same:
3823 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3824 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3825 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3826 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3827 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3829 Cross-sum rules for even numbers can be derived by leaving as many bits
3830 to the right alone as the divisor has zeros to the right.
3831 E.g. if x is an unsigned 32 bit number:
3832 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3836 expand_divmod (int rem_flag, enum tree_code code, enum machine_mode mode,
3837 rtx op0, rtx op1, rtx target, int unsignedp)
3839 enum machine_mode compute_mode;
3840 rtx tquotient;
3841 rtx quotient = 0, remainder = 0;
3842 rtx_insn *last;
3843 int size;
3844 rtx_insn *insn;
3845 optab optab1, optab2;
3846 int op1_is_constant, op1_is_pow2 = 0;
3847 int max_cost, extra_cost;
3848 static HOST_WIDE_INT last_div_const = 0;
3849 bool speed = optimize_insn_for_speed_p ();
3851 op1_is_constant = CONST_INT_P (op1);
3852 if (op1_is_constant)
3854 unsigned HOST_WIDE_INT ext_op1 = UINTVAL (op1);
3855 if (unsignedp)
3856 ext_op1 &= GET_MODE_MASK (mode);
3857 op1_is_pow2 = ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1)
3858 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1))));
3862 This is the structure of expand_divmod:
3864 First comes code to fix up the operands so we can perform the operations
3865 correctly and efficiently.
3867 Second comes a switch statement with code specific for each rounding mode.
3868 For some special operands this code emits all RTL for the desired
3869 operation, for other cases, it generates only a quotient and stores it in
3870 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3871 to indicate that it has not done anything.
3873 Last comes code that finishes the operation. If QUOTIENT is set and
3874 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3875 QUOTIENT is not set, it is computed using trunc rounding.
3877 We try to generate special code for division and remainder when OP1 is a
3878 constant. If |OP1| = 2**n we can use shifts and some other fast
3879 operations. For other values of OP1, we compute a carefully selected
3880 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3881 by m.
3883 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3884 half of the product. Different strategies for generating the product are
3885 implemented in expmed_mult_highpart.
3887 If what we actually want is the remainder, we generate that by another
3888 by-constant multiplication and a subtraction. */
3890 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3891 code below will malfunction if we are, so check here and handle
3892 the special case if so. */
3893 if (op1 == const1_rtx)
3894 return rem_flag ? const0_rtx : op0;
3896 /* When dividing by -1, we could get an overflow.
3897 negv_optab can handle overflows. */
3898 if (! unsignedp && op1 == constm1_rtx)
3900 if (rem_flag)
3901 return const0_rtx;
3902 return expand_unop (mode, flag_trapv && GET_MODE_CLASS (mode) == MODE_INT
3903 ? negv_optab : neg_optab, op0, target, 0);
3906 if (target
3907 /* Don't use the function value register as a target
3908 since we have to read it as well as write it,
3909 and function-inlining gets confused by this. */
3910 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
3911 /* Don't clobber an operand while doing a multi-step calculation. */
3912 || ((rem_flag || op1_is_constant)
3913 && (reg_mentioned_p (target, op0)
3914 || (MEM_P (op0) && MEM_P (target))))
3915 || reg_mentioned_p (target, op1)
3916 || (MEM_P (op1) && MEM_P (target))))
3917 target = 0;
3919 /* Get the mode in which to perform this computation. Normally it will
3920 be MODE, but sometimes we can't do the desired operation in MODE.
3921 If so, pick a wider mode in which we can do the operation. Convert
3922 to that mode at the start to avoid repeated conversions.
3924 First see what operations we need. These depend on the expression
3925 we are evaluating. (We assume that divxx3 insns exist under the
3926 same conditions that modxx3 insns and that these insns don't normally
3927 fail. If these assumptions are not correct, we may generate less
3928 efficient code in some cases.)
3930 Then see if we find a mode in which we can open-code that operation
3931 (either a division, modulus, or shift). Finally, check for the smallest
3932 mode for which we can do the operation with a library call. */
3934 /* We might want to refine this now that we have division-by-constant
3935 optimization. Since expmed_mult_highpart tries so many variants, it is
3936 not straightforward to generalize this. Maybe we should make an array
3937 of possible modes in init_expmed? Save this for GCC 2.7. */
3939 optab1 = ((op1_is_pow2 && op1 != const0_rtx)
3940 ? (unsignedp ? lshr_optab : ashr_optab)
3941 : (unsignedp ? udiv_optab : sdiv_optab));
3942 optab2 = ((op1_is_pow2 && op1 != const0_rtx)
3943 ? optab1
3944 : (unsignedp ? udivmod_optab : sdivmod_optab));
3946 for (compute_mode = mode; compute_mode != VOIDmode;
3947 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3948 if (optab_handler (optab1, compute_mode) != CODE_FOR_nothing
3949 || optab_handler (optab2, compute_mode) != CODE_FOR_nothing)
3950 break;
3952 if (compute_mode == VOIDmode)
3953 for (compute_mode = mode; compute_mode != VOIDmode;
3954 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3955 if (optab_libfunc (optab1, compute_mode)
3956 || optab_libfunc (optab2, compute_mode))
3957 break;
3959 /* If we still couldn't find a mode, use MODE, but expand_binop will
3960 probably die. */
3961 if (compute_mode == VOIDmode)
3962 compute_mode = mode;
3964 if (target && GET_MODE (target) == compute_mode)
3965 tquotient = target;
3966 else
3967 tquotient = gen_reg_rtx (compute_mode);
3969 size = GET_MODE_BITSIZE (compute_mode);
3970 #if 0
3971 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3972 (mode), and thereby get better code when OP1 is a constant. Do that
3973 later. It will require going over all usages of SIZE below. */
3974 size = GET_MODE_BITSIZE (mode);
3975 #endif
3977 /* Only deduct something for a REM if the last divide done was
3978 for a different constant. Then set the constant of the last
3979 divide. */
3980 max_cost = (unsignedp
3981 ? udiv_cost (speed, compute_mode)
3982 : sdiv_cost (speed, compute_mode));
3983 if (rem_flag && ! (last_div_const != 0 && op1_is_constant
3984 && INTVAL (op1) == last_div_const))
3985 max_cost -= (mul_cost (speed, compute_mode)
3986 + add_cost (speed, compute_mode));
3988 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3990 /* Now convert to the best mode to use. */
3991 if (compute_mode != mode)
3993 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3994 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3996 /* convert_modes may have placed op1 into a register, so we
3997 must recompute the following. */
3998 op1_is_constant = CONST_INT_P (op1);
3999 op1_is_pow2 = (op1_is_constant
4000 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
4001 || (! unsignedp
4002 && EXACT_POWER_OF_2_OR_ZERO_P (-UINTVAL (op1))))));
4005 /* If one of the operands is a volatile MEM, copy it into a register. */
4007 if (MEM_P (op0) && MEM_VOLATILE_P (op0))
4008 op0 = force_reg (compute_mode, op0);
4009 if (MEM_P (op1) && MEM_VOLATILE_P (op1))
4010 op1 = force_reg (compute_mode, op1);
4012 /* If we need the remainder or if OP1 is constant, we need to
4013 put OP0 in a register in case it has any queued subexpressions. */
4014 if (rem_flag || op1_is_constant)
4015 op0 = force_reg (compute_mode, op0);
4017 last = get_last_insn ();
4019 /* Promote floor rounding to trunc rounding for unsigned operations. */
4020 if (unsignedp)
4022 if (code == FLOOR_DIV_EXPR)
4023 code = TRUNC_DIV_EXPR;
4024 if (code == FLOOR_MOD_EXPR)
4025 code = TRUNC_MOD_EXPR;
4026 if (code == EXACT_DIV_EXPR && op1_is_pow2)
4027 code = TRUNC_DIV_EXPR;
4030 if (op1 != const0_rtx)
4031 switch (code)
4033 case TRUNC_MOD_EXPR:
4034 case TRUNC_DIV_EXPR:
4035 if (op1_is_constant)
4037 if (unsignedp)
4039 unsigned HOST_WIDE_INT mh, ml;
4040 int pre_shift, post_shift;
4041 int dummy;
4042 unsigned HOST_WIDE_INT d = (INTVAL (op1)
4043 & GET_MODE_MASK (compute_mode));
4045 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
4047 pre_shift = floor_log2 (d);
4048 if (rem_flag)
4050 unsigned HOST_WIDE_INT mask
4051 = ((unsigned HOST_WIDE_INT) 1 << pre_shift) - 1;
4052 remainder
4053 = expand_binop (compute_mode, and_optab, op0,
4054 gen_int_mode (mask, compute_mode),
4055 remainder, 1,
4056 OPTAB_LIB_WIDEN);
4057 if (remainder)
4058 return gen_lowpart (mode, remainder);
4060 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4061 pre_shift, tquotient, 1);
4063 else if (size <= HOST_BITS_PER_WIDE_INT)
4065 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
4067 /* Most significant bit of divisor is set; emit an scc
4068 insn. */
4069 quotient = emit_store_flag_force (tquotient, GEU, op0, op1,
4070 compute_mode, 1, 1);
4072 else
4074 /* Find a suitable multiplier and right shift count
4075 instead of multiplying with D. */
4077 mh = choose_multiplier (d, size, size,
4078 &ml, &post_shift, &dummy);
4080 /* If the suggested multiplier is more than SIZE bits,
4081 we can do better for even divisors, using an
4082 initial right shift. */
4083 if (mh != 0 && (d & 1) == 0)
4085 pre_shift = floor_log2 (d & -d);
4086 mh = choose_multiplier (d >> pre_shift, size,
4087 size - pre_shift,
4088 &ml, &post_shift, &dummy);
4089 gcc_assert (!mh);
4091 else
4092 pre_shift = 0;
4094 if (mh != 0)
4096 rtx t1, t2, t3, t4;
4098 if (post_shift - 1 >= BITS_PER_WORD)
4099 goto fail1;
4101 extra_cost
4102 = (shift_cost (speed, compute_mode, post_shift - 1)
4103 + shift_cost (speed, compute_mode, 1)
4104 + 2 * add_cost (speed, compute_mode));
4105 t1 = expmed_mult_highpart
4106 (compute_mode, op0,
4107 gen_int_mode (ml, compute_mode),
4108 NULL_RTX, 1, max_cost - extra_cost);
4109 if (t1 == 0)
4110 goto fail1;
4111 t2 = force_operand (gen_rtx_MINUS (compute_mode,
4112 op0, t1),
4113 NULL_RTX);
4114 t3 = expand_shift (RSHIFT_EXPR, compute_mode,
4115 t2, 1, NULL_RTX, 1);
4116 t4 = force_operand (gen_rtx_PLUS (compute_mode,
4117 t1, t3),
4118 NULL_RTX);
4119 quotient = expand_shift
4120 (RSHIFT_EXPR, compute_mode, t4,
4121 post_shift - 1, tquotient, 1);
4123 else
4125 rtx t1, t2;
4127 if (pre_shift >= BITS_PER_WORD
4128 || post_shift >= BITS_PER_WORD)
4129 goto fail1;
4131 t1 = expand_shift
4132 (RSHIFT_EXPR, compute_mode, op0,
4133 pre_shift, NULL_RTX, 1);
4134 extra_cost
4135 = (shift_cost (speed, compute_mode, pre_shift)
4136 + shift_cost (speed, compute_mode, post_shift));
4137 t2 = expmed_mult_highpart
4138 (compute_mode, t1,
4139 gen_int_mode (ml, compute_mode),
4140 NULL_RTX, 1, max_cost - extra_cost);
4141 if (t2 == 0)
4142 goto fail1;
4143 quotient = expand_shift
4144 (RSHIFT_EXPR, compute_mode, t2,
4145 post_shift, tquotient, 1);
4149 else /* Too wide mode to use tricky code */
4150 break;
4152 insn = get_last_insn ();
4153 if (insn != last)
4154 set_dst_reg_note (insn, REG_EQUAL,
4155 gen_rtx_UDIV (compute_mode, op0, op1),
4156 quotient);
4158 else /* TRUNC_DIV, signed */
4160 unsigned HOST_WIDE_INT ml;
4161 int lgup, post_shift;
4162 rtx mlr;
4163 HOST_WIDE_INT d = INTVAL (op1);
4164 unsigned HOST_WIDE_INT abs_d;
4166 /* Since d might be INT_MIN, we have to cast to
4167 unsigned HOST_WIDE_INT before negating to avoid
4168 undefined signed overflow. */
4169 abs_d = (d >= 0
4170 ? (unsigned HOST_WIDE_INT) d
4171 : - (unsigned HOST_WIDE_INT) d);
4173 /* n rem d = n rem -d */
4174 if (rem_flag && d < 0)
4176 d = abs_d;
4177 op1 = gen_int_mode (abs_d, compute_mode);
4180 if (d == 1)
4181 quotient = op0;
4182 else if (d == -1)
4183 quotient = expand_unop (compute_mode, neg_optab, op0,
4184 tquotient, 0);
4185 else if (HOST_BITS_PER_WIDE_INT >= size
4186 && abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
4188 /* This case is not handled correctly below. */
4189 quotient = emit_store_flag (tquotient, EQ, op0, op1,
4190 compute_mode, 1, 1);
4191 if (quotient == 0)
4192 goto fail1;
4194 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
4195 && (rem_flag
4196 ? smod_pow2_cheap (speed, compute_mode)
4197 : sdiv_pow2_cheap (speed, compute_mode))
4198 /* We assume that cheap metric is true if the
4199 optab has an expander for this mode. */
4200 && ((optab_handler ((rem_flag ? smod_optab
4201 : sdiv_optab),
4202 compute_mode)
4203 != CODE_FOR_nothing)
4204 || (optab_handler (sdivmod_optab,
4205 compute_mode)
4206 != CODE_FOR_nothing)))
4208 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
4210 if (rem_flag)
4212 remainder = expand_smod_pow2 (compute_mode, op0, d);
4213 if (remainder)
4214 return gen_lowpart (mode, remainder);
4217 if (sdiv_pow2_cheap (speed, compute_mode)
4218 && ((optab_handler (sdiv_optab, compute_mode)
4219 != CODE_FOR_nothing)
4220 || (optab_handler (sdivmod_optab, compute_mode)
4221 != CODE_FOR_nothing)))
4222 quotient = expand_divmod (0, TRUNC_DIV_EXPR,
4223 compute_mode, op0,
4224 gen_int_mode (abs_d,
4225 compute_mode),
4226 NULL_RTX, 0);
4227 else
4228 quotient = expand_sdiv_pow2 (compute_mode, op0, abs_d);
4230 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4231 negate the quotient. */
4232 if (d < 0)
4234 insn = get_last_insn ();
4235 if (insn != last
4236 && abs_d < ((unsigned HOST_WIDE_INT) 1
4237 << (HOST_BITS_PER_WIDE_INT - 1)))
4238 set_dst_reg_note (insn, REG_EQUAL,
4239 gen_rtx_DIV (compute_mode, op0,
4240 gen_int_mode
4241 (abs_d,
4242 compute_mode)),
4243 quotient);
4245 quotient = expand_unop (compute_mode, neg_optab,
4246 quotient, quotient, 0);
4249 else if (size <= HOST_BITS_PER_WIDE_INT)
4251 choose_multiplier (abs_d, size, size - 1,
4252 &ml, &post_shift, &lgup);
4253 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
4255 rtx t1, t2, t3;
4257 if (post_shift >= BITS_PER_WORD
4258 || size - 1 >= BITS_PER_WORD)
4259 goto fail1;
4261 extra_cost = (shift_cost (speed, compute_mode, post_shift)
4262 + shift_cost (speed, compute_mode, size - 1)
4263 + add_cost (speed, compute_mode));
4264 t1 = expmed_mult_highpart
4265 (compute_mode, op0, gen_int_mode (ml, compute_mode),
4266 NULL_RTX, 0, max_cost - extra_cost);
4267 if (t1 == 0)
4268 goto fail1;
4269 t2 = expand_shift
4270 (RSHIFT_EXPR, compute_mode, t1,
4271 post_shift, NULL_RTX, 0);
4272 t3 = expand_shift
4273 (RSHIFT_EXPR, compute_mode, op0,
4274 size - 1, NULL_RTX, 0);
4275 if (d < 0)
4276 quotient
4277 = force_operand (gen_rtx_MINUS (compute_mode,
4278 t3, t2),
4279 tquotient);
4280 else
4281 quotient
4282 = force_operand (gen_rtx_MINUS (compute_mode,
4283 t2, t3),
4284 tquotient);
4286 else
4288 rtx t1, t2, t3, t4;
4290 if (post_shift >= BITS_PER_WORD
4291 || size - 1 >= BITS_PER_WORD)
4292 goto fail1;
4294 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
4295 mlr = gen_int_mode (ml, compute_mode);
4296 extra_cost = (shift_cost (speed, compute_mode, post_shift)
4297 + shift_cost (speed, compute_mode, size - 1)
4298 + 2 * add_cost (speed, compute_mode));
4299 t1 = expmed_mult_highpart (compute_mode, op0, mlr,
4300 NULL_RTX, 0,
4301 max_cost - extra_cost);
4302 if (t1 == 0)
4303 goto fail1;
4304 t2 = force_operand (gen_rtx_PLUS (compute_mode,
4305 t1, op0),
4306 NULL_RTX);
4307 t3 = expand_shift
4308 (RSHIFT_EXPR, compute_mode, t2,
4309 post_shift, NULL_RTX, 0);
4310 t4 = expand_shift
4311 (RSHIFT_EXPR, compute_mode, op0,
4312 size - 1, NULL_RTX, 0);
4313 if (d < 0)
4314 quotient
4315 = force_operand (gen_rtx_MINUS (compute_mode,
4316 t4, t3),
4317 tquotient);
4318 else
4319 quotient
4320 = force_operand (gen_rtx_MINUS (compute_mode,
4321 t3, t4),
4322 tquotient);
4325 else /* Too wide mode to use tricky code */
4326 break;
4328 insn = get_last_insn ();
4329 if (insn != last)
4330 set_dst_reg_note (insn, REG_EQUAL,
4331 gen_rtx_DIV (compute_mode, op0, op1),
4332 quotient);
4334 break;
4336 fail1:
4337 delete_insns_since (last);
4338 break;
4340 case FLOOR_DIV_EXPR:
4341 case FLOOR_MOD_EXPR:
4342 /* We will come here only for signed operations. */
4343 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
4345 unsigned HOST_WIDE_INT mh, ml;
4346 int pre_shift, lgup, post_shift;
4347 HOST_WIDE_INT d = INTVAL (op1);
4349 if (d > 0)
4351 /* We could just as easily deal with negative constants here,
4352 but it does not seem worth the trouble for GCC 2.6. */
4353 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
4355 pre_shift = floor_log2 (d);
4356 if (rem_flag)
4358 unsigned HOST_WIDE_INT mask
4359 = ((unsigned HOST_WIDE_INT) 1 << pre_shift) - 1;
4360 remainder = expand_binop
4361 (compute_mode, and_optab, op0,
4362 gen_int_mode (mask, compute_mode),
4363 remainder, 0, OPTAB_LIB_WIDEN);
4364 if (remainder)
4365 return gen_lowpart (mode, remainder);
4367 quotient = expand_shift
4368 (RSHIFT_EXPR, compute_mode, op0,
4369 pre_shift, tquotient, 0);
4371 else
4373 rtx t1, t2, t3, t4;
4375 mh = choose_multiplier (d, size, size - 1,
4376 &ml, &post_shift, &lgup);
4377 gcc_assert (!mh);
4379 if (post_shift < BITS_PER_WORD
4380 && size - 1 < BITS_PER_WORD)
4382 t1 = expand_shift
4383 (RSHIFT_EXPR, compute_mode, op0,
4384 size - 1, NULL_RTX, 0);
4385 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
4386 NULL_RTX, 0, OPTAB_WIDEN);
4387 extra_cost = (shift_cost (speed, compute_mode, post_shift)
4388 + shift_cost (speed, compute_mode, size - 1)
4389 + 2 * add_cost (speed, compute_mode));
4390 t3 = expmed_mult_highpart
4391 (compute_mode, t2, gen_int_mode (ml, compute_mode),
4392 NULL_RTX, 1, max_cost - extra_cost);
4393 if (t3 != 0)
4395 t4 = expand_shift
4396 (RSHIFT_EXPR, compute_mode, t3,
4397 post_shift, NULL_RTX, 1);
4398 quotient = expand_binop (compute_mode, xor_optab,
4399 t4, t1, tquotient, 0,
4400 OPTAB_WIDEN);
4405 else
4407 rtx nsign, t1, t2, t3, t4;
4408 t1 = force_operand (gen_rtx_PLUS (compute_mode,
4409 op0, constm1_rtx), NULL_RTX);
4410 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
4411 0, OPTAB_WIDEN);
4412 nsign = expand_shift
4413 (RSHIFT_EXPR, compute_mode, t2,
4414 size - 1, NULL_RTX, 0);
4415 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
4416 NULL_RTX);
4417 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
4418 NULL_RTX, 0);
4419 if (t4)
4421 rtx t5;
4422 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
4423 NULL_RTX, 0);
4424 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4425 t4, t5),
4426 tquotient);
4431 if (quotient != 0)
4432 break;
4433 delete_insns_since (last);
4435 /* Try using an instruction that produces both the quotient and
4436 remainder, using truncation. We can easily compensate the quotient
4437 or remainder to get floor rounding, once we have the remainder.
4438 Notice that we compute also the final remainder value here,
4439 and return the result right away. */
4440 if (target == 0 || GET_MODE (target) != compute_mode)
4441 target = gen_reg_rtx (compute_mode);
4443 if (rem_flag)
4445 remainder
4446 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
4447 quotient = gen_reg_rtx (compute_mode);
4449 else
4451 quotient
4452 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
4453 remainder = gen_reg_rtx (compute_mode);
4456 if (expand_twoval_binop (sdivmod_optab, op0, op1,
4457 quotient, remainder, 0))
4459 /* This could be computed with a branch-less sequence.
4460 Save that for later. */
4461 rtx tem;
4462 rtx_code_label *label = gen_label_rtx ();
4463 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
4464 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4465 NULL_RTX, 0, OPTAB_WIDEN);
4466 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
4467 expand_dec (quotient, const1_rtx);
4468 expand_inc (remainder, op1);
4469 emit_label (label);
4470 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4473 /* No luck with division elimination or divmod. Have to do it
4474 by conditionally adjusting op0 *and* the result. */
4476 rtx_code_label *label1, *label2, *label3, *label4, *label5;
4477 rtx adjusted_op0;
4478 rtx tem;
4480 quotient = gen_reg_rtx (compute_mode);
4481 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4482 label1 = gen_label_rtx ();
4483 label2 = gen_label_rtx ();
4484 label3 = gen_label_rtx ();
4485 label4 = gen_label_rtx ();
4486 label5 = gen_label_rtx ();
4487 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4488 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
4489 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4490 quotient, 0, OPTAB_LIB_WIDEN);
4491 if (tem != quotient)
4492 emit_move_insn (quotient, tem);
4493 emit_jump_insn (gen_jump (label5));
4494 emit_barrier ();
4495 emit_label (label1);
4496 expand_inc (adjusted_op0, const1_rtx);
4497 emit_jump_insn (gen_jump (label4));
4498 emit_barrier ();
4499 emit_label (label2);
4500 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
4501 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4502 quotient, 0, OPTAB_LIB_WIDEN);
4503 if (tem != quotient)
4504 emit_move_insn (quotient, tem);
4505 emit_jump_insn (gen_jump (label5));
4506 emit_barrier ();
4507 emit_label (label3);
4508 expand_dec (adjusted_op0, const1_rtx);
4509 emit_label (label4);
4510 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4511 quotient, 0, OPTAB_LIB_WIDEN);
4512 if (tem != quotient)
4513 emit_move_insn (quotient, tem);
4514 expand_dec (quotient, const1_rtx);
4515 emit_label (label5);
4517 break;
4519 case CEIL_DIV_EXPR:
4520 case CEIL_MOD_EXPR:
4521 if (unsignedp)
4523 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
4525 rtx t1, t2, t3;
4526 unsigned HOST_WIDE_INT d = INTVAL (op1);
4527 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4528 floor_log2 (d), tquotient, 1);
4529 t2 = expand_binop (compute_mode, and_optab, op0,
4530 gen_int_mode (d - 1, compute_mode),
4531 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4532 t3 = gen_reg_rtx (compute_mode);
4533 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
4534 compute_mode, 1, 1);
4535 if (t3 == 0)
4537 rtx_code_label *lab;
4538 lab = gen_label_rtx ();
4539 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
4540 expand_inc (t1, const1_rtx);
4541 emit_label (lab);
4542 quotient = t1;
4544 else
4545 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4546 t1, t3),
4547 tquotient);
4548 break;
4551 /* Try using an instruction that produces both the quotient and
4552 remainder, using truncation. We can easily compensate the
4553 quotient or remainder to get ceiling rounding, once we have the
4554 remainder. Notice that we compute also the final remainder
4555 value here, and return the result right away. */
4556 if (target == 0 || GET_MODE (target) != compute_mode)
4557 target = gen_reg_rtx (compute_mode);
4559 if (rem_flag)
4561 remainder = (REG_P (target)
4562 ? target : gen_reg_rtx (compute_mode));
4563 quotient = gen_reg_rtx (compute_mode);
4565 else
4567 quotient = (REG_P (target)
4568 ? target : gen_reg_rtx (compute_mode));
4569 remainder = gen_reg_rtx (compute_mode);
4572 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
4573 remainder, 1))
4575 /* This could be computed with a branch-less sequence.
4576 Save that for later. */
4577 rtx_code_label *label = gen_label_rtx ();
4578 do_cmp_and_jump (remainder, const0_rtx, EQ,
4579 compute_mode, label);
4580 expand_inc (quotient, const1_rtx);
4581 expand_dec (remainder, op1);
4582 emit_label (label);
4583 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4586 /* No luck with division elimination or divmod. Have to do it
4587 by conditionally adjusting op0 *and* the result. */
4589 rtx_code_label *label1, *label2;
4590 rtx adjusted_op0, tem;
4592 quotient = gen_reg_rtx (compute_mode);
4593 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4594 label1 = gen_label_rtx ();
4595 label2 = gen_label_rtx ();
4596 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
4597 compute_mode, label1);
4598 emit_move_insn (quotient, const0_rtx);
4599 emit_jump_insn (gen_jump (label2));
4600 emit_barrier ();
4601 emit_label (label1);
4602 expand_dec (adjusted_op0, const1_rtx);
4603 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
4604 quotient, 1, OPTAB_LIB_WIDEN);
4605 if (tem != quotient)
4606 emit_move_insn (quotient, tem);
4607 expand_inc (quotient, const1_rtx);
4608 emit_label (label2);
4611 else /* signed */
4613 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
4614 && INTVAL (op1) >= 0)
4616 /* This is extremely similar to the code for the unsigned case
4617 above. For 2.7 we should merge these variants, but for
4618 2.6.1 I don't want to touch the code for unsigned since that
4619 get used in C. The signed case will only be used by other
4620 languages (Ada). */
4622 rtx t1, t2, t3;
4623 unsigned HOST_WIDE_INT d = INTVAL (op1);
4624 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4625 floor_log2 (d), tquotient, 0);
4626 t2 = expand_binop (compute_mode, and_optab, op0,
4627 gen_int_mode (d - 1, compute_mode),
4628 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4629 t3 = gen_reg_rtx (compute_mode);
4630 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
4631 compute_mode, 1, 1);
4632 if (t3 == 0)
4634 rtx_code_label *lab;
4635 lab = gen_label_rtx ();
4636 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
4637 expand_inc (t1, const1_rtx);
4638 emit_label (lab);
4639 quotient = t1;
4641 else
4642 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4643 t1, t3),
4644 tquotient);
4645 break;
4648 /* Try using an instruction that produces both the quotient and
4649 remainder, using truncation. We can easily compensate the
4650 quotient or remainder to get ceiling rounding, once we have the
4651 remainder. Notice that we compute also the final remainder
4652 value here, and return the result right away. */
4653 if (target == 0 || GET_MODE (target) != compute_mode)
4654 target = gen_reg_rtx (compute_mode);
4655 if (rem_flag)
4657 remainder= (REG_P (target)
4658 ? target : gen_reg_rtx (compute_mode));
4659 quotient = gen_reg_rtx (compute_mode);
4661 else
4663 quotient = (REG_P (target)
4664 ? target : gen_reg_rtx (compute_mode));
4665 remainder = gen_reg_rtx (compute_mode);
4668 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
4669 remainder, 0))
4671 /* This could be computed with a branch-less sequence.
4672 Save that for later. */
4673 rtx tem;
4674 rtx_code_label *label = gen_label_rtx ();
4675 do_cmp_and_jump (remainder, const0_rtx, EQ,
4676 compute_mode, label);
4677 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4678 NULL_RTX, 0, OPTAB_WIDEN);
4679 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
4680 expand_inc (quotient, const1_rtx);
4681 expand_dec (remainder, op1);
4682 emit_label (label);
4683 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4686 /* No luck with division elimination or divmod. Have to do it
4687 by conditionally adjusting op0 *and* the result. */
4689 rtx_code_label *label1, *label2, *label3, *label4, *label5;
4690 rtx adjusted_op0;
4691 rtx tem;
4693 quotient = gen_reg_rtx (compute_mode);
4694 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4695 label1 = gen_label_rtx ();
4696 label2 = gen_label_rtx ();
4697 label3 = gen_label_rtx ();
4698 label4 = gen_label_rtx ();
4699 label5 = gen_label_rtx ();
4700 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4701 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
4702 compute_mode, label1);
4703 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4704 quotient, 0, OPTAB_LIB_WIDEN);
4705 if (tem != quotient)
4706 emit_move_insn (quotient, tem);
4707 emit_jump_insn (gen_jump (label5));
4708 emit_barrier ();
4709 emit_label (label1);
4710 expand_dec (adjusted_op0, const1_rtx);
4711 emit_jump_insn (gen_jump (label4));
4712 emit_barrier ();
4713 emit_label (label2);
4714 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
4715 compute_mode, label3);
4716 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4717 quotient, 0, OPTAB_LIB_WIDEN);
4718 if (tem != quotient)
4719 emit_move_insn (quotient, tem);
4720 emit_jump_insn (gen_jump (label5));
4721 emit_barrier ();
4722 emit_label (label3);
4723 expand_inc (adjusted_op0, const1_rtx);
4724 emit_label (label4);
4725 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4726 quotient, 0, OPTAB_LIB_WIDEN);
4727 if (tem != quotient)
4728 emit_move_insn (quotient, tem);
4729 expand_inc (quotient, const1_rtx);
4730 emit_label (label5);
4733 break;
4735 case EXACT_DIV_EXPR:
4736 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
4738 HOST_WIDE_INT d = INTVAL (op1);
4739 unsigned HOST_WIDE_INT ml;
4740 int pre_shift;
4741 rtx t1;
4743 pre_shift = floor_log2 (d & -d);
4744 ml = invert_mod2n (d >> pre_shift, size);
4745 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4746 pre_shift, NULL_RTX, unsignedp);
4747 quotient = expand_mult (compute_mode, t1,
4748 gen_int_mode (ml, compute_mode),
4749 NULL_RTX, 1);
4751 insn = get_last_insn ();
4752 set_dst_reg_note (insn, REG_EQUAL,
4753 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4754 compute_mode, op0, op1),
4755 quotient);
4757 break;
4759 case ROUND_DIV_EXPR:
4760 case ROUND_MOD_EXPR:
4761 if (unsignedp)
4763 rtx tem;
4764 rtx_code_label *label;
4765 label = gen_label_rtx ();
4766 quotient = gen_reg_rtx (compute_mode);
4767 remainder = gen_reg_rtx (compute_mode);
4768 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
4770 rtx tem;
4771 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
4772 quotient, 1, OPTAB_LIB_WIDEN);
4773 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
4774 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4775 remainder, 1, OPTAB_LIB_WIDEN);
4777 tem = plus_constant (compute_mode, op1, -1);
4778 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem, 1, NULL_RTX, 1);
4779 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
4780 expand_inc (quotient, const1_rtx);
4781 expand_dec (remainder, op1);
4782 emit_label (label);
4784 else
4786 rtx abs_rem, abs_op1, tem, mask;
4787 rtx_code_label *label;
4788 label = gen_label_rtx ();
4789 quotient = gen_reg_rtx (compute_mode);
4790 remainder = gen_reg_rtx (compute_mode);
4791 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
4793 rtx tem;
4794 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
4795 quotient, 0, OPTAB_LIB_WIDEN);
4796 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
4797 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4798 remainder, 0, OPTAB_LIB_WIDEN);
4800 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 1, 0);
4801 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 1, 0);
4802 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
4803 1, NULL_RTX, 1);
4804 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
4805 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4806 NULL_RTX, 0, OPTAB_WIDEN);
4807 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4808 size - 1, NULL_RTX, 0);
4809 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
4810 NULL_RTX, 0, OPTAB_WIDEN);
4811 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4812 NULL_RTX, 0, OPTAB_WIDEN);
4813 expand_inc (quotient, tem);
4814 tem = expand_binop (compute_mode, xor_optab, mask, op1,
4815 NULL_RTX, 0, OPTAB_WIDEN);
4816 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4817 NULL_RTX, 0, OPTAB_WIDEN);
4818 expand_dec (remainder, tem);
4819 emit_label (label);
4821 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4823 default:
4824 gcc_unreachable ();
4827 if (quotient == 0)
4829 if (target && GET_MODE (target) != compute_mode)
4830 target = 0;
4832 if (rem_flag)
4834 /* Try to produce the remainder without producing the quotient.
4835 If we seem to have a divmod pattern that does not require widening,
4836 don't try widening here. We should really have a WIDEN argument
4837 to expand_twoval_binop, since what we'd really like to do here is
4838 1) try a mod insn in compute_mode
4839 2) try a divmod insn in compute_mode
4840 3) try a div insn in compute_mode and multiply-subtract to get
4841 remainder
4842 4) try the same things with widening allowed. */
4843 remainder
4844 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4845 op0, op1, target,
4846 unsignedp,
4847 ((optab_handler (optab2, compute_mode)
4848 != CODE_FOR_nothing)
4849 ? OPTAB_DIRECT : OPTAB_WIDEN));
4850 if (remainder == 0)
4852 /* No luck there. Can we do remainder and divide at once
4853 without a library call? */
4854 remainder = gen_reg_rtx (compute_mode);
4855 if (! expand_twoval_binop ((unsignedp
4856 ? udivmod_optab
4857 : sdivmod_optab),
4858 op0, op1,
4859 NULL_RTX, remainder, unsignedp))
4860 remainder = 0;
4863 if (remainder)
4864 return gen_lowpart (mode, remainder);
4867 /* Produce the quotient. Try a quotient insn, but not a library call.
4868 If we have a divmod in this mode, use it in preference to widening
4869 the div (for this test we assume it will not fail). Note that optab2
4870 is set to the one of the two optabs that the call below will use. */
4871 quotient
4872 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
4873 op0, op1, rem_flag ? NULL_RTX : target,
4874 unsignedp,
4875 ((optab_handler (optab2, compute_mode)
4876 != CODE_FOR_nothing)
4877 ? OPTAB_DIRECT : OPTAB_WIDEN));
4879 if (quotient == 0)
4881 /* No luck there. Try a quotient-and-remainder insn,
4882 keeping the quotient alone. */
4883 quotient = gen_reg_rtx (compute_mode);
4884 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
4885 op0, op1,
4886 quotient, NULL_RTX, unsignedp))
4888 quotient = 0;
4889 if (! rem_flag)
4890 /* Still no luck. If we are not computing the remainder,
4891 use a library call for the quotient. */
4892 quotient = sign_expand_binop (compute_mode,
4893 udiv_optab, sdiv_optab,
4894 op0, op1, target,
4895 unsignedp, OPTAB_LIB_WIDEN);
4900 if (rem_flag)
4902 if (target && GET_MODE (target) != compute_mode)
4903 target = 0;
4905 if (quotient == 0)
4907 /* No divide instruction either. Use library for remainder. */
4908 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4909 op0, op1, target,
4910 unsignedp, OPTAB_LIB_WIDEN);
4911 /* No remainder function. Try a quotient-and-remainder
4912 function, keeping the remainder. */
4913 if (!remainder)
4915 remainder = gen_reg_rtx (compute_mode);
4916 if (!expand_twoval_binop_libfunc
4917 (unsignedp ? udivmod_optab : sdivmod_optab,
4918 op0, op1,
4919 NULL_RTX, remainder,
4920 unsignedp ? UMOD : MOD))
4921 remainder = NULL_RTX;
4924 else
4926 /* We divided. Now finish doing X - Y * (X / Y). */
4927 remainder = expand_mult (compute_mode, quotient, op1,
4928 NULL_RTX, unsignedp);
4929 remainder = expand_binop (compute_mode, sub_optab, op0,
4930 remainder, target, unsignedp,
4931 OPTAB_LIB_WIDEN);
4935 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4938 /* Return a tree node with data type TYPE, describing the value of X.
4939 Usually this is an VAR_DECL, if there is no obvious better choice.
4940 X may be an expression, however we only support those expressions
4941 generated by loop.c. */
4943 tree
4944 make_tree (tree type, rtx x)
4946 tree t;
4948 switch (GET_CODE (x))
4950 case CONST_INT:
4951 case CONST_WIDE_INT:
4952 t = wide_int_to_tree (type, std::make_pair (x, TYPE_MODE (type)));
4953 return t;
4955 case CONST_DOUBLE:
4956 STATIC_ASSERT (HOST_BITS_PER_WIDE_INT * 2 <= MAX_BITSIZE_MODE_ANY_INT);
4957 if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (x) == VOIDmode)
4958 t = wide_int_to_tree (type,
4959 wide_int::from_array (&CONST_DOUBLE_LOW (x), 2,
4960 HOST_BITS_PER_WIDE_INT * 2));
4961 else
4963 REAL_VALUE_TYPE d;
4965 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
4966 t = build_real (type, d);
4969 return t;
4971 case CONST_VECTOR:
4973 int units = CONST_VECTOR_NUNITS (x);
4974 tree itype = TREE_TYPE (type);
4975 tree *elts;
4976 int i;
4978 /* Build a tree with vector elements. */
4979 elts = XALLOCAVEC (tree, units);
4980 for (i = units - 1; i >= 0; --i)
4982 rtx elt = CONST_VECTOR_ELT (x, i);
4983 elts[i] = make_tree (itype, elt);
4986 return build_vector (type, elts);
4989 case PLUS:
4990 return fold_build2 (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4991 make_tree (type, XEXP (x, 1)));
4993 case MINUS:
4994 return fold_build2 (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4995 make_tree (type, XEXP (x, 1)));
4997 case NEG:
4998 return fold_build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)));
5000 case MULT:
5001 return fold_build2 (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
5002 make_tree (type, XEXP (x, 1)));
5004 case ASHIFT:
5005 return fold_build2 (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
5006 make_tree (type, XEXP (x, 1)));
5008 case LSHIFTRT:
5009 t = unsigned_type_for (type);
5010 return fold_convert (type, build2 (RSHIFT_EXPR, t,
5011 make_tree (t, XEXP (x, 0)),
5012 make_tree (type, XEXP (x, 1))));
5014 case ASHIFTRT:
5015 t = signed_type_for (type);
5016 return fold_convert (type, build2 (RSHIFT_EXPR, t,
5017 make_tree (t, XEXP (x, 0)),
5018 make_tree (type, XEXP (x, 1))));
5020 case DIV:
5021 if (TREE_CODE (type) != REAL_TYPE)
5022 t = signed_type_for (type);
5023 else
5024 t = type;
5026 return fold_convert (type, build2 (TRUNC_DIV_EXPR, t,
5027 make_tree (t, XEXP (x, 0)),
5028 make_tree (t, XEXP (x, 1))));
5029 case UDIV:
5030 t = unsigned_type_for (type);
5031 return fold_convert (type, build2 (TRUNC_DIV_EXPR, t,
5032 make_tree (t, XEXP (x, 0)),
5033 make_tree (t, XEXP (x, 1))));
5035 case SIGN_EXTEND:
5036 case ZERO_EXTEND:
5037 t = lang_hooks.types.type_for_mode (GET_MODE (XEXP (x, 0)),
5038 GET_CODE (x) == ZERO_EXTEND);
5039 return fold_convert (type, make_tree (t, XEXP (x, 0)));
5041 case CONST:
5042 return make_tree (type, XEXP (x, 0));
5044 case SYMBOL_REF:
5045 t = SYMBOL_REF_DECL (x);
5046 if (t)
5047 return fold_convert (type, build_fold_addr_expr (t));
5048 /* else fall through. */
5050 default:
5051 t = build_decl (RTL_LOCATION (x), VAR_DECL, NULL_TREE, type);
5053 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5054 address mode to pointer mode. */
5055 if (POINTER_TYPE_P (type))
5056 x = convert_memory_address_addr_space
5057 (TYPE_MODE (type), x, TYPE_ADDR_SPACE (TREE_TYPE (type)));
5059 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5060 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5061 t->decl_with_rtl.rtl = x;
5063 return t;
5067 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5068 and returning TARGET.
5070 If TARGET is 0, a pseudo-register or constant is returned. */
5073 expand_and (enum machine_mode mode, rtx op0, rtx op1, rtx target)
5075 rtx tem = 0;
5077 if (GET_MODE (op0) == VOIDmode && GET_MODE (op1) == VOIDmode)
5078 tem = simplify_binary_operation (AND, mode, op0, op1);
5079 if (tem == 0)
5080 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
5082 if (target == 0)
5083 target = tem;
5084 else if (tem != target)
5085 emit_move_insn (target, tem);
5086 return target;
5089 /* Helper function for emit_store_flag. */
5090 static rtx
5091 emit_cstore (rtx target, enum insn_code icode, enum rtx_code code,
5092 enum machine_mode mode, enum machine_mode compare_mode,
5093 int unsignedp, rtx x, rtx y, int normalizep,
5094 enum machine_mode target_mode)
5096 struct expand_operand ops[4];
5097 rtx op0, comparison, subtarget;
5098 rtx_insn *last;
5099 enum machine_mode result_mode = targetm.cstore_mode (icode);
5101 last = get_last_insn ();
5102 x = prepare_operand (icode, x, 2, mode, compare_mode, unsignedp);
5103 y = prepare_operand (icode, y, 3, mode, compare_mode, unsignedp);
5104 if (!x || !y)
5106 delete_insns_since (last);
5107 return NULL_RTX;
5110 if (target_mode == VOIDmode)
5111 target_mode = result_mode;
5112 if (!target)
5113 target = gen_reg_rtx (target_mode);
5115 comparison = gen_rtx_fmt_ee (code, result_mode, x, y);
5117 create_output_operand (&ops[0], optimize ? NULL_RTX : target, result_mode);
5118 create_fixed_operand (&ops[1], comparison);
5119 create_fixed_operand (&ops[2], x);
5120 create_fixed_operand (&ops[3], y);
5121 if (!maybe_expand_insn (icode, 4, ops))
5123 delete_insns_since (last);
5124 return NULL_RTX;
5126 subtarget = ops[0].value;
5128 /* If we are converting to a wider mode, first convert to
5129 TARGET_MODE, then normalize. This produces better combining
5130 opportunities on machines that have a SIGN_EXTRACT when we are
5131 testing a single bit. This mostly benefits the 68k.
5133 If STORE_FLAG_VALUE does not have the sign bit set when
5134 interpreted in MODE, we can do this conversion as unsigned, which
5135 is usually more efficient. */
5136 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (result_mode))
5138 convert_move (target, subtarget,
5139 val_signbit_known_clear_p (result_mode,
5140 STORE_FLAG_VALUE));
5141 op0 = target;
5142 result_mode = target_mode;
5144 else
5145 op0 = subtarget;
5147 /* If we want to keep subexpressions around, don't reuse our last
5148 target. */
5149 if (optimize)
5150 subtarget = 0;
5152 /* Now normalize to the proper value in MODE. Sometimes we don't
5153 have to do anything. */
5154 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
5156 /* STORE_FLAG_VALUE might be the most negative number, so write
5157 the comparison this way to avoid a compiler-time warning. */
5158 else if (- normalizep == STORE_FLAG_VALUE)
5159 op0 = expand_unop (result_mode, neg_optab, op0, subtarget, 0);
5161 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5162 it hard to use a value of just the sign bit due to ANSI integer
5163 constant typing rules. */
5164 else if (val_signbit_known_set_p (result_mode, STORE_FLAG_VALUE))
5165 op0 = expand_shift (RSHIFT_EXPR, result_mode, op0,
5166 GET_MODE_BITSIZE (result_mode) - 1, subtarget,
5167 normalizep == 1);
5168 else
5170 gcc_assert (STORE_FLAG_VALUE & 1);
5172 op0 = expand_and (result_mode, op0, const1_rtx, subtarget);
5173 if (normalizep == -1)
5174 op0 = expand_unop (result_mode, neg_optab, op0, op0, 0);
5177 /* If we were converting to a smaller mode, do the conversion now. */
5178 if (target_mode != result_mode)
5180 convert_move (target, op0, 0);
5181 return target;
5183 else
5184 return op0;
5188 /* A subroutine of emit_store_flag only including "tricks" that do not
5189 need a recursive call. These are kept separate to avoid infinite
5190 loops. */
5192 static rtx
5193 emit_store_flag_1 (rtx target, enum rtx_code code, rtx op0, rtx op1,
5194 enum machine_mode mode, int unsignedp, int normalizep,
5195 enum machine_mode target_mode)
5197 rtx subtarget;
5198 enum insn_code icode;
5199 enum machine_mode compare_mode;
5200 enum mode_class mclass;
5201 enum rtx_code scode;
5202 rtx tem;
5204 if (unsignedp)
5205 code = unsigned_condition (code);
5206 scode = swap_condition (code);
5208 /* If one operand is constant, make it the second one. Only do this
5209 if the other operand is not constant as well. */
5211 if (swap_commutative_operands_p (op0, op1))
5213 tem = op0;
5214 op0 = op1;
5215 op1 = tem;
5216 code = swap_condition (code);
5219 if (mode == VOIDmode)
5220 mode = GET_MODE (op0);
5222 /* For some comparisons with 1 and -1, we can convert this to
5223 comparisons with zero. This will often produce more opportunities for
5224 store-flag insns. */
5226 switch (code)
5228 case LT:
5229 if (op1 == const1_rtx)
5230 op1 = const0_rtx, code = LE;
5231 break;
5232 case LE:
5233 if (op1 == constm1_rtx)
5234 op1 = const0_rtx, code = LT;
5235 break;
5236 case GE:
5237 if (op1 == const1_rtx)
5238 op1 = const0_rtx, code = GT;
5239 break;
5240 case GT:
5241 if (op1 == constm1_rtx)
5242 op1 = const0_rtx, code = GE;
5243 break;
5244 case GEU:
5245 if (op1 == const1_rtx)
5246 op1 = const0_rtx, code = NE;
5247 break;
5248 case LTU:
5249 if (op1 == const1_rtx)
5250 op1 = const0_rtx, code = EQ;
5251 break;
5252 default:
5253 break;
5256 /* If we are comparing a double-word integer with zero or -1, we can
5257 convert the comparison into one involving a single word. */
5258 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2
5259 && GET_MODE_CLASS (mode) == MODE_INT
5260 && (!MEM_P (op0) || ! MEM_VOLATILE_P (op0)))
5262 if ((code == EQ || code == NE)
5263 && (op1 == const0_rtx || op1 == constm1_rtx))
5265 rtx op00, op01;
5267 /* Do a logical OR or AND of the two words and compare the
5268 result. */
5269 op00 = simplify_gen_subreg (word_mode, op0, mode, 0);
5270 op01 = simplify_gen_subreg (word_mode, op0, mode, UNITS_PER_WORD);
5271 tem = expand_binop (word_mode,
5272 op1 == const0_rtx ? ior_optab : and_optab,
5273 op00, op01, NULL_RTX, unsignedp,
5274 OPTAB_DIRECT);
5276 if (tem != 0)
5277 tem = emit_store_flag (NULL_RTX, code, tem, op1, word_mode,
5278 unsignedp, normalizep);
5280 else if ((code == LT || code == GE) && op1 == const0_rtx)
5282 rtx op0h;
5284 /* If testing the sign bit, can just test on high word. */
5285 op0h = simplify_gen_subreg (word_mode, op0, mode,
5286 subreg_highpart_offset (word_mode,
5287 mode));
5288 tem = emit_store_flag (NULL_RTX, code, op0h, op1, word_mode,
5289 unsignedp, normalizep);
5291 else
5292 tem = NULL_RTX;
5294 if (tem)
5296 if (target_mode == VOIDmode || GET_MODE (tem) == target_mode)
5297 return tem;
5298 if (!target)
5299 target = gen_reg_rtx (target_mode);
5301 convert_move (target, tem,
5302 !val_signbit_known_set_p (word_mode,
5303 (normalizep ? normalizep
5304 : STORE_FLAG_VALUE)));
5305 return target;
5309 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5310 complement of A (for GE) and shifting the sign bit to the low bit. */
5311 if (op1 == const0_rtx && (code == LT || code == GE)
5312 && GET_MODE_CLASS (mode) == MODE_INT
5313 && (normalizep || STORE_FLAG_VALUE == 1
5314 || val_signbit_p (mode, STORE_FLAG_VALUE)))
5316 subtarget = target;
5318 if (!target)
5319 target_mode = mode;
5321 /* If the result is to be wider than OP0, it is best to convert it
5322 first. If it is to be narrower, it is *incorrect* to convert it
5323 first. */
5324 else if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
5326 op0 = convert_modes (target_mode, mode, op0, 0);
5327 mode = target_mode;
5330 if (target_mode != mode)
5331 subtarget = 0;
5333 if (code == GE)
5334 op0 = expand_unop (mode, one_cmpl_optab, op0,
5335 ((STORE_FLAG_VALUE == 1 || normalizep)
5336 ? 0 : subtarget), 0);
5338 if (STORE_FLAG_VALUE == 1 || normalizep)
5339 /* If we are supposed to produce a 0/1 value, we want to do
5340 a logical shift from the sign bit to the low-order bit; for
5341 a -1/0 value, we do an arithmetic shift. */
5342 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
5343 GET_MODE_BITSIZE (mode) - 1,
5344 subtarget, normalizep != -1);
5346 if (mode != target_mode)
5347 op0 = convert_modes (target_mode, mode, op0, 0);
5349 return op0;
5352 mclass = GET_MODE_CLASS (mode);
5353 for (compare_mode = mode; compare_mode != VOIDmode;
5354 compare_mode = GET_MODE_WIDER_MODE (compare_mode))
5356 enum machine_mode optab_mode = mclass == MODE_CC ? CCmode : compare_mode;
5357 icode = optab_handler (cstore_optab, optab_mode);
5358 if (icode != CODE_FOR_nothing)
5360 do_pending_stack_adjust ();
5361 tem = emit_cstore (target, icode, code, mode, compare_mode,
5362 unsignedp, op0, op1, normalizep, target_mode);
5363 if (tem)
5364 return tem;
5366 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5368 tem = emit_cstore (target, icode, scode, mode, compare_mode,
5369 unsignedp, op1, op0, normalizep, target_mode);
5370 if (tem)
5371 return tem;
5373 break;
5377 return 0;
5380 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5381 and storing in TARGET. Normally return TARGET.
5382 Return 0 if that cannot be done.
5384 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5385 it is VOIDmode, they cannot both be CONST_INT.
5387 UNSIGNEDP is for the case where we have to widen the operands
5388 to perform the operation. It says to use zero-extension.
5390 NORMALIZEP is 1 if we should convert the result to be either zero
5391 or one. Normalize is -1 if we should convert the result to be
5392 either zero or -1. If NORMALIZEP is zero, the result will be left
5393 "raw" out of the scc insn. */
5396 emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
5397 enum machine_mode mode, int unsignedp, int normalizep)
5399 enum machine_mode target_mode = target ? GET_MODE (target) : VOIDmode;
5400 enum rtx_code rcode;
5401 rtx subtarget;
5402 rtx tem, trueval;
5403 rtx_insn *last;
5405 /* If we compare constants, we shouldn't use a store-flag operation,
5406 but a constant load. We can get there via the vanilla route that
5407 usually generates a compare-branch sequence, but will in this case
5408 fold the comparison to a constant, and thus elide the branch. */
5409 if (CONSTANT_P (op0) && CONSTANT_P (op1))
5410 return NULL_RTX;
5412 tem = emit_store_flag_1 (target, code, op0, op1, mode, unsignedp, normalizep,
5413 target_mode);
5414 if (tem)
5415 return tem;
5417 /* If we reached here, we can't do this with a scc insn, however there
5418 are some comparisons that can be done in other ways. Don't do any
5419 of these cases if branches are very cheap. */
5420 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5421 return 0;
5423 /* See what we need to return. We can only return a 1, -1, or the
5424 sign bit. */
5426 if (normalizep == 0)
5428 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5429 normalizep = STORE_FLAG_VALUE;
5431 else if (val_signbit_p (mode, STORE_FLAG_VALUE))
5433 else
5434 return 0;
5437 last = get_last_insn ();
5439 /* If optimizing, use different pseudo registers for each insn, instead
5440 of reusing the same pseudo. This leads to better CSE, but slows
5441 down the compiler, since there are more pseudos */
5442 subtarget = (!optimize
5443 && (target_mode == mode)) ? target : NULL_RTX;
5444 trueval = GEN_INT (normalizep ? normalizep : STORE_FLAG_VALUE);
5446 /* For floating-point comparisons, try the reverse comparison or try
5447 changing the "orderedness" of the comparison. */
5448 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5450 enum rtx_code first_code;
5451 bool and_them;
5453 rcode = reverse_condition_maybe_unordered (code);
5454 if (can_compare_p (rcode, mode, ccp_store_flag)
5455 && (code == ORDERED || code == UNORDERED
5456 || (! HONOR_NANS (mode) && (code == LTGT || code == UNEQ))
5457 || (! HONOR_SNANS (mode) && (code == EQ || code == NE))))
5459 int want_add = ((STORE_FLAG_VALUE == 1 && normalizep == -1)
5460 || (STORE_FLAG_VALUE == -1 && normalizep == 1));
5462 /* For the reverse comparison, use either an addition or a XOR. */
5463 if (want_add
5464 && rtx_cost (GEN_INT (normalizep), PLUS, 1,
5465 optimize_insn_for_speed_p ()) == 0)
5467 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5468 STORE_FLAG_VALUE, target_mode);
5469 if (tem)
5470 return expand_binop (target_mode, add_optab, tem,
5471 gen_int_mode (normalizep, target_mode),
5472 target, 0, OPTAB_WIDEN);
5474 else if (!want_add
5475 && rtx_cost (trueval, XOR, 1,
5476 optimize_insn_for_speed_p ()) == 0)
5478 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5479 normalizep, target_mode);
5480 if (tem)
5481 return expand_binop (target_mode, xor_optab, tem, trueval,
5482 target, INTVAL (trueval) >= 0, OPTAB_WIDEN);
5486 delete_insns_since (last);
5488 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5489 if (code == ORDERED || code == UNORDERED)
5490 return 0;
5492 and_them = split_comparison (code, mode, &first_code, &code);
5494 /* If there are no NaNs, the first comparison should always fall through.
5495 Effectively change the comparison to the other one. */
5496 if (!HONOR_NANS (mode))
5498 gcc_assert (first_code == (and_them ? ORDERED : UNORDERED));
5499 return emit_store_flag_1 (target, code, op0, op1, mode, 0, normalizep,
5500 target_mode);
5503 #ifdef HAVE_conditional_move
5504 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5505 conditional move. */
5506 tem = emit_store_flag_1 (subtarget, first_code, op0, op1, mode, 0,
5507 normalizep, target_mode);
5508 if (tem == 0)
5509 return 0;
5511 if (and_them)
5512 tem = emit_conditional_move (target, code, op0, op1, mode,
5513 tem, const0_rtx, GET_MODE (tem), 0);
5514 else
5515 tem = emit_conditional_move (target, code, op0, op1, mode,
5516 trueval, tem, GET_MODE (tem), 0);
5518 if (tem == 0)
5519 delete_insns_since (last);
5520 return tem;
5521 #else
5522 return 0;
5523 #endif
5526 /* The remaining tricks only apply to integer comparisons. */
5528 if (GET_MODE_CLASS (mode) != MODE_INT)
5529 return 0;
5531 /* If this is an equality comparison of integers, we can try to exclusive-or
5532 (or subtract) the two operands and use a recursive call to try the
5533 comparison with zero. Don't do any of these cases if branches are
5534 very cheap. */
5536 if ((code == EQ || code == NE) && op1 != const0_rtx)
5538 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
5539 OPTAB_WIDEN);
5541 if (tem == 0)
5542 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
5543 OPTAB_WIDEN);
5544 if (tem != 0)
5545 tem = emit_store_flag (target, code, tem, const0_rtx,
5546 mode, unsignedp, normalizep);
5547 if (tem != 0)
5548 return tem;
5550 delete_insns_since (last);
5553 /* For integer comparisons, try the reverse comparison. However, for
5554 small X and if we'd have anyway to extend, implementing "X != 0"
5555 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5556 rcode = reverse_condition (code);
5557 if (can_compare_p (rcode, mode, ccp_store_flag)
5558 && ! (optab_handler (cstore_optab, mode) == CODE_FOR_nothing
5559 && code == NE
5560 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5561 && op1 == const0_rtx))
5563 int want_add = ((STORE_FLAG_VALUE == 1 && normalizep == -1)
5564 || (STORE_FLAG_VALUE == -1 && normalizep == 1));
5566 /* Again, for the reverse comparison, use either an addition or a XOR. */
5567 if (want_add
5568 && rtx_cost (GEN_INT (normalizep), PLUS, 1,
5569 optimize_insn_for_speed_p ()) == 0)
5571 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5572 STORE_FLAG_VALUE, target_mode);
5573 if (tem != 0)
5574 tem = expand_binop (target_mode, add_optab, tem,
5575 gen_int_mode (normalizep, target_mode),
5576 target, 0, OPTAB_WIDEN);
5578 else if (!want_add
5579 && rtx_cost (trueval, XOR, 1,
5580 optimize_insn_for_speed_p ()) == 0)
5582 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5583 normalizep, target_mode);
5584 if (tem != 0)
5585 tem = expand_binop (target_mode, xor_optab, tem, trueval, target,
5586 INTVAL (trueval) >= 0, OPTAB_WIDEN);
5589 if (tem != 0)
5590 return tem;
5591 delete_insns_since (last);
5594 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5595 the constant zero. Reject all other comparisons at this point. Only
5596 do LE and GT if branches are expensive since they are expensive on
5597 2-operand machines. */
5599 if (op1 != const0_rtx
5600 || (code != EQ && code != NE
5601 && (BRANCH_COST (optimize_insn_for_speed_p (),
5602 false) <= 1 || (code != LE && code != GT))))
5603 return 0;
5605 /* Try to put the result of the comparison in the sign bit. Assume we can't
5606 do the necessary operation below. */
5608 tem = 0;
5610 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5611 the sign bit set. */
5613 if (code == LE)
5615 /* This is destructive, so SUBTARGET can't be OP0. */
5616 if (rtx_equal_p (subtarget, op0))
5617 subtarget = 0;
5619 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
5620 OPTAB_WIDEN);
5621 if (tem)
5622 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
5623 OPTAB_WIDEN);
5626 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5627 number of bits in the mode of OP0, minus one. */
5629 if (code == GT)
5631 if (rtx_equal_p (subtarget, op0))
5632 subtarget = 0;
5634 tem = expand_shift (RSHIFT_EXPR, mode, op0,
5635 GET_MODE_BITSIZE (mode) - 1,
5636 subtarget, 0);
5637 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
5638 OPTAB_WIDEN);
5641 if (code == EQ || code == NE)
5643 /* For EQ or NE, one way to do the comparison is to apply an operation
5644 that converts the operand into a positive number if it is nonzero
5645 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5646 for NE we negate. This puts the result in the sign bit. Then we
5647 normalize with a shift, if needed.
5649 Two operations that can do the above actions are ABS and FFS, so try
5650 them. If that doesn't work, and MODE is smaller than a full word,
5651 we can use zero-extension to the wider mode (an unsigned conversion)
5652 as the operation. */
5654 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5655 that is compensated by the subsequent overflow when subtracting
5656 one / negating. */
5658 if (optab_handler (abs_optab, mode) != CODE_FOR_nothing)
5659 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
5660 else if (optab_handler (ffs_optab, mode) != CODE_FOR_nothing)
5661 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
5662 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5664 tem = convert_modes (word_mode, mode, op0, 1);
5665 mode = word_mode;
5668 if (tem != 0)
5670 if (code == EQ)
5671 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
5672 0, OPTAB_WIDEN);
5673 else
5674 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
5677 /* If we couldn't do it that way, for NE we can "or" the two's complement
5678 of the value with itself. For EQ, we take the one's complement of
5679 that "or", which is an extra insn, so we only handle EQ if branches
5680 are expensive. */
5682 if (tem == 0
5683 && (code == NE
5684 || BRANCH_COST (optimize_insn_for_speed_p (),
5685 false) > 1))
5687 if (rtx_equal_p (subtarget, op0))
5688 subtarget = 0;
5690 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
5691 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
5692 OPTAB_WIDEN);
5694 if (tem && code == EQ)
5695 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
5699 if (tem && normalizep)
5700 tem = expand_shift (RSHIFT_EXPR, mode, tem,
5701 GET_MODE_BITSIZE (mode) - 1,
5702 subtarget, normalizep == 1);
5704 if (tem)
5706 if (!target)
5708 else if (GET_MODE (tem) != target_mode)
5710 convert_move (target, tem, 0);
5711 tem = target;
5713 else if (!subtarget)
5715 emit_move_insn (target, tem);
5716 tem = target;
5719 else
5720 delete_insns_since (last);
5722 return tem;
5725 /* Like emit_store_flag, but always succeeds. */
5728 emit_store_flag_force (rtx target, enum rtx_code code, rtx op0, rtx op1,
5729 enum machine_mode mode, int unsignedp, int normalizep)
5731 rtx tem;
5732 rtx_code_label *label;
5733 rtx trueval, falseval;
5735 /* First see if emit_store_flag can do the job. */
5736 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
5737 if (tem != 0)
5738 return tem;
5740 if (!target)
5741 target = gen_reg_rtx (word_mode);
5743 /* If this failed, we have to do this with set/compare/jump/set code.
5744 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5745 trueval = normalizep ? GEN_INT (normalizep) : const1_rtx;
5746 if (code == NE
5747 && GET_MODE_CLASS (mode) == MODE_INT
5748 && REG_P (target)
5749 && op0 == target
5750 && op1 == const0_rtx)
5752 label = gen_label_rtx ();
5753 do_compare_rtx_and_jump (target, const0_rtx, EQ, unsignedp,
5754 mode, NULL_RTX, NULL_RTX, label, -1);
5755 emit_move_insn (target, trueval);
5756 emit_label (label);
5757 return target;
5760 if (!REG_P (target)
5761 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
5762 target = gen_reg_rtx (GET_MODE (target));
5764 /* Jump in the right direction if the target cannot implement CODE
5765 but can jump on its reverse condition. */
5766 falseval = const0_rtx;
5767 if (! can_compare_p (code, mode, ccp_jump)
5768 && (! FLOAT_MODE_P (mode)
5769 || code == ORDERED || code == UNORDERED
5770 || (! HONOR_NANS (mode) && (code == LTGT || code == UNEQ))
5771 || (! HONOR_SNANS (mode) && (code == EQ || code == NE))))
5773 enum rtx_code rcode;
5774 if (FLOAT_MODE_P (mode))
5775 rcode = reverse_condition_maybe_unordered (code);
5776 else
5777 rcode = reverse_condition (code);
5779 /* Canonicalize to UNORDERED for the libcall. */
5780 if (can_compare_p (rcode, mode, ccp_jump)
5781 || (code == ORDERED && ! can_compare_p (ORDERED, mode, ccp_jump)))
5783 falseval = trueval;
5784 trueval = const0_rtx;
5785 code = rcode;
5789 emit_move_insn (target, trueval);
5790 label = gen_label_rtx ();
5791 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX,
5792 NULL_RTX, label, -1);
5794 emit_move_insn (target, falseval);
5795 emit_label (label);
5797 return target;
5800 /* Perform possibly multi-word comparison and conditional jump to LABEL
5801 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5802 now a thin wrapper around do_compare_rtx_and_jump. */
5804 static void
5805 do_cmp_and_jump (rtx arg1, rtx arg2, enum rtx_code op, enum machine_mode mode,
5806 rtx_code_label *label)
5808 int unsignedp = (op == LTU || op == LEU || op == GTU || op == GEU);
5809 do_compare_rtx_and_jump (arg1, arg2, op, unsignedp, mode,
5810 NULL_RTX, NULL_RTX, label, -1);