gcc/doc/arm-neon-intrinsics.texi

   1 @c Copyright (C) 2006-2013 Free Software Foundation, Inc.
   2 @c This is part of the GCC manual.
   3 @c For copying conditions, see the file gcc.texi.
   4
   5 @c This file is generated automatically using gcc/config/arm/neon-docgen.ml
   6 @c Please do not edit manually.
   7 @subsubsection Addition
   8
   9 @itemize @bullet
  10 @item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
  11 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
  12 @end itemize
  13
  14
  15 @itemize @bullet
  16 @item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
  17 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
  18 @end itemize
  19
  20
  21 @itemize @bullet
  22 @item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
  23 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
  24 @end itemize
  25
  26
  27 @itemize @bullet
  28 @item int32x2_t vadd_s32 (int32x2_t, int32x2_t)
  29 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
  30 @end itemize
  31
  32
  33 @itemize @bullet
  34 @item int16x4_t vadd_s16 (int16x4_t, int16x4_t)
  35 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
  36 @end itemize
  37
  38
  39 @itemize @bullet
  40 @item int8x8_t vadd_s8 (int8x8_t, int8x8_t)
  41 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
  42 @end itemize
  43
  44
  45 @itemize @bullet
  46 @item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
  47 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
  48 @end itemize
  49
  50
  51 @itemize @bullet
  52 @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
  53 @end itemize
  54
  55
  56 @itemize @bullet
  57 @item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
  58 @end itemize
  59
  60
  61 @itemize @bullet
  62 @item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
  63 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
  64 @end itemize
  65
  66
  67 @itemize @bullet
  68 @item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
  69 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
  70 @end itemize
  71
  72
  73 @itemize @bullet
  74 @item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
  75 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
  76 @end itemize
  77
  78
  79 @itemize @bullet
  80 @item int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
  81 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
  82 @end itemize
  83
  84
  85 @itemize @bullet
  86 @item int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
  87 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
  88 @end itemize
  89
  90
  91 @itemize @bullet
  92 @item int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
  93 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
  94 @end itemize
  95
  96
  97 @itemize @bullet
  98 @item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
  99 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
 100 @end itemize
 101
 102
 103 @itemize @bullet
 104 @item int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
 105 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
 106 @end itemize
 107
 108
 109 @itemize @bullet
 110 @item float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
 111 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}}
 112 @end itemize
 113
 114
 115 @itemize @bullet
 116 @item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
 117 @*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}}
 118 @end itemize
 119
 120
 121 @itemize @bullet
 122 @item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
 123 @*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}}
 124 @end itemize
 125
 126
 127 @itemize @bullet
 128 @item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
 129 @*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}}
 130 @end itemize
 131
 132
 133 @itemize @bullet
 134 @item int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
 135 @*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}}
 136 @end itemize
 137
 138
 139 @itemize @bullet
 140 @item int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
 141 @*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}}
 142 @end itemize
 143
 144
 145 @itemize @bullet
 146 @item int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
 147 @*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}}
 148 @end itemize
 149
 150
 151 @itemize @bullet
 152 @item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
 153 @*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}}
 154 @end itemize
 155
 156
 157 @itemize @bullet
 158 @item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
 159 @*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}}
 160 @end itemize
 161
 162
 163 @itemize @bullet
 164 @item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
 165 @*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}}
 166 @end itemize
 167
 168
 169 @itemize @bullet
 170 @item int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
 171 @*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}}
 172 @end itemize
 173
 174
 175 @itemize @bullet
 176 @item int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
 177 @*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}}
 178 @end itemize
 179
 180
 181 @itemize @bullet
 182 @item int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
 183 @*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}}
 184 @end itemize
 185
 186
 187 @itemize @bullet
 188 @item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
 189 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}}
 190 @end itemize
 191
 192
 193 @itemize @bullet
 194 @item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
 195 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}}
 196 @end itemize
 197
 198
 199 @itemize @bullet
 200 @item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
 201 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}}
 202 @end itemize
 203
 204
 205 @itemize @bullet
 206 @item int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
 207 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}}
 208 @end itemize
 209
 210
 211 @itemize @bullet
 212 @item int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
 213 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}}
 214 @end itemize
 215
 216
 217 @itemize @bullet
 218 @item int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
 219 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}}
 220 @end itemize
 221
 222
 223 @itemize @bullet
 224 @item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
 225 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}}
 226 @end itemize
 227
 228
 229 @itemize @bullet
 230 @item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
 231 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}}
 232 @end itemize
 233
 234
 235 @itemize @bullet
 236 @item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
 237 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}}
 238 @end itemize
 239
 240
 241 @itemize @bullet
 242 @item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
 243 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}}
 244 @end itemize
 245
 246
 247 @itemize @bullet
 248 @item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
 249 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}}
 250 @end itemize
 251
 252
 253 @itemize @bullet
 254 @item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
 255 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}}
 256 @end itemize
 257
 258
 259 @itemize @bullet
 260 @item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
 261 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}}
 262 @end itemize
 263
 264
 265 @itemize @bullet
 266 @item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
 267 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}}
 268 @end itemize
 269
 270
 271 @itemize @bullet
 272 @item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
 273 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}}
 274 @end itemize
 275
 276
 277 @itemize @bullet
 278 @item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
 279 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}}
 280 @end itemize
 281
 282
 283 @itemize @bullet
 284 @item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
 285 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}}
 286 @end itemize
 287
 288
 289 @itemize @bullet
 290 @item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
 291 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}}
 292 @end itemize
 293
 294
 295 @itemize @bullet
 296 @item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
 297 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}}
 298 @end itemize
 299
 300
 301 @itemize @bullet
 302 @item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
 303 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}}
 304 @end itemize
 305
 306
 307 @itemize @bullet
 308 @item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
 309 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}}
 310 @end itemize
 311
 312
 313 @itemize @bullet
 314 @item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
 315 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}}
 316 @end itemize
 317
 318
 319 @itemize @bullet
 320 @item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
 321 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}}
 322 @end itemize
 323
 324
 325 @itemize @bullet
 326 @item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
 327 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}}
 328 @end itemize
 329
 330
 331 @itemize @bullet
 332 @item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
 333 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}}
 334 @end itemize
 335
 336
 337 @itemize @bullet
 338 @item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
 339 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}}
 340 @end itemize
 341
 342
 343 @itemize @bullet
 344 @item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
 345 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}}
 346 @end itemize
 347
 348
 349 @itemize @bullet
 350 @item int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
 351 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}}
 352 @end itemize
 353
 354
 355 @itemize @bullet
 356 @item int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
 357 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}}
 358 @end itemize
 359
 360
 361 @itemize @bullet
 362 @item int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
 363 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}}
 364 @end itemize
 365
 366
 367 @itemize @bullet
 368 @item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
 369 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}}
 370 @end itemize
 371
 372
 373 @itemize @bullet
 374 @item int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
 375 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}}
 376 @end itemize
 377
 378
 379 @itemize @bullet
 380 @item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
 381 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}}
 382 @end itemize
 383
 384
 385 @itemize @bullet
 386 @item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
 387 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}}
 388 @end itemize
 389
 390
 391 @itemize @bullet
 392 @item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
 393 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}}
 394 @end itemize
 395
 396
 397 @itemize @bullet
 398 @item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
 399 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}}
 400 @end itemize
 401
 402
 403 @itemize @bullet
 404 @item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
 405 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}}
 406 @end itemize
 407
 408
 409 @itemize @bullet
 410 @item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
 411 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}}
 412 @end itemize
 413
 414
 415 @itemize @bullet
 416 @item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
 417 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}}
 418 @end itemize
 419
 420
 421 @itemize @bullet
 422 @item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
 423 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}}
 424 @end itemize
 425
 426
 427 @itemize @bullet
 428 @item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
 429 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 430 @end itemize
 431
 432
 433 @itemize @bullet
 434 @item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
 435 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 436 @end itemize
 437
 438
 439 @itemize @bullet
 440 @item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
 441 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 442 @end itemize
 443
 444
 445 @itemize @bullet
 446 @item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
 447 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 448 @end itemize
 449
 450
 451 @itemize @bullet
 452 @item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
 453 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 454 @end itemize
 455
 456
 457 @itemize @bullet
 458 @item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
 459 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 460 @end itemize
 461
 462
 463 @itemize @bullet
 464 @item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
 465 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 466 @end itemize
 467
 468
 469 @itemize @bullet
 470 @item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
 471 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 472 @end itemize
 473
 474
 475 @itemize @bullet
 476 @item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
 477 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 478 @end itemize
 479
 480
 481 @itemize @bullet
 482 @item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
 483 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 484 @end itemize
 485
 486
 487 @itemize @bullet
 488 @item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
 489 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 490 @end itemize
 491
 492
 493 @itemize @bullet
 494 @item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
 495 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 496 @end itemize
 497
 498
 499
 500
 501 @subsubsection Multiplication
 502
 503 @itemize @bullet
 504 @item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
 505 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
 506 @end itemize
 507
 508
 509 @itemize @bullet
 510 @item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
 511 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
 512 @end itemize
 513
 514
 515 @itemize @bullet
 516 @item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
 517 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
 518 @end itemize
 519
 520
 521 @itemize @bullet
 522 @item int32x2_t vmul_s32 (int32x2_t, int32x2_t)
 523 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
 524 @end itemize
 525
 526
 527 @itemize @bullet
 528 @item int16x4_t vmul_s16 (int16x4_t, int16x4_t)
 529 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
 530 @end itemize
 531
 532
 533 @itemize @bullet
 534 @item int8x8_t vmul_s8 (int8x8_t, int8x8_t)
 535 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
 536 @end itemize
 537
 538
 539 @itemize @bullet
 540 @item float32x2_t vmul_f32 (float32x2_t, float32x2_t)
 541 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}}
 542 @end itemize
 543
 544
 545 @itemize @bullet
 546 @item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
 547 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}}
 548 @end itemize
 549
 550
 551 @itemize @bullet
 552 @item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
 553 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
 554 @end itemize
 555
 556
 557 @itemize @bullet
 558 @item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
 559 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
 560 @end itemize
 561
 562
 563 @itemize @bullet
 564 @item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
 565 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
 566 @end itemize
 567
 568
 569 @itemize @bullet
 570 @item int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
 571 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
 572 @end itemize
 573
 574
 575 @itemize @bullet
 576 @item int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
 577 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
 578 @end itemize
 579
 580
 581 @itemize @bullet
 582 @item int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
 583 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
 584 @end itemize
 585
 586
 587 @itemize @bullet
 588 @item float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
 589 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}}
 590 @end itemize
 591
 592
 593 @itemize @bullet
 594 @item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
 595 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}}
 596 @end itemize
 597
 598
 599 @itemize @bullet
 600 @item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
 601 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
 602 @end itemize
 603
 604
 605 @itemize @bullet
 606 @item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
 607 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
 608 @end itemize
 609
 610
 611 @itemize @bullet
 612 @item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
 613 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
 614 @end itemize
 615
 616
 617 @itemize @bullet
 618 @item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
 619 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
 620 @end itemize
 621
 622
 623 @itemize @bullet
 624 @item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
 625 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
 626 @end itemize
 627
 628
 629 @itemize @bullet
 630 @item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
 631 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
 632 @end itemize
 633
 634
 635 @itemize @bullet
 636 @item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
 637 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
 638 @end itemize
 639
 640
 641 @itemize @bullet
 642 @item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
 643 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
 644 @end itemize
 645
 646
 647 @itemize @bullet
 648 @item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
 649 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}}
 650 @end itemize
 651
 652
 653 @itemize @bullet
 654 @item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
 655 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}}
 656 @end itemize
 657
 658
 659 @itemize @bullet
 660 @item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
 661 @*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}}
 662 @end itemize
 663
 664
 665 @itemize @bullet
 666 @item int64x2_t vmull_s32 (int32x2_t, int32x2_t)
 667 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}}
 668 @end itemize
 669
 670
 671 @itemize @bullet
 672 @item int32x4_t vmull_s16 (int16x4_t, int16x4_t)
 673 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}}
 674 @end itemize
 675
 676
 677 @itemize @bullet
 678 @item int16x8_t vmull_s8 (int8x8_t, int8x8_t)
 679 @*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}}
 680 @end itemize
 681
 682
 683 @itemize @bullet
 684 @item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
 685 @*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}}
 686 @end itemize
 687
 688
 689 @itemize @bullet
 690 @item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
 691 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}}
 692 @end itemize
 693
 694
 695 @itemize @bullet
 696 @item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
 697 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}}
 698 @end itemize
 699
 700
 701
 702
 703 @subsubsection Multiply-accumulate
 704
 705 @itemize @bullet
 706 @item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 707 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
 708 @end itemize
 709
 710
 711 @itemize @bullet
 712 @item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 713 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
 714 @end itemize
 715
 716
 717 @itemize @bullet
 718 @item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 719 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
 720 @end itemize
 721
 722
 723 @itemize @bullet
 724 @item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
 725 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
 726 @end itemize
 727
 728
 729 @itemize @bullet
 730 @item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
 731 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
 732 @end itemize
 733
 734
 735 @itemize @bullet
 736 @item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
 737 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
 738 @end itemize
 739
 740
 741 @itemize @bullet
 742 @item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
 743 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}}
 744 @end itemize
 745
 746
 747 @itemize @bullet
 748 @item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 749 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
 750 @end itemize
 751
 752
 753 @itemize @bullet
 754 @item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 755 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
 756 @end itemize
 757
 758
 759 @itemize @bullet
 760 @item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 761 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
 762 @end itemize
 763
 764
 765 @itemize @bullet
 766 @item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
 767 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
 768 @end itemize
 769
 770
 771 @itemize @bullet
 772 @item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
 773 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
 774 @end itemize
 775
 776
 777 @itemize @bullet
 778 @item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
 779 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
 780 @end itemize
 781
 782
 783 @itemize @bullet
 784 @item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
 785 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}}
 786 @end itemize
 787
 788
 789 @itemize @bullet
 790 @item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 791 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}}
 792 @end itemize
 793
 794
 795 @itemize @bullet
 796 @item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 797 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}}
 798 @end itemize
 799
 800
 801 @itemize @bullet
 802 @item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 803 @*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}}
 804 @end itemize
 805
 806
 807 @itemize @bullet
 808 @item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
 809 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}}
 810 @end itemize
 811
 812
 813 @itemize @bullet
 814 @item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
 815 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}}
 816 @end itemize
 817
 818
 819 @itemize @bullet
 820 @item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
 821 @*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}}
 822 @end itemize
 823
 824
 825 @itemize @bullet
 826 @item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
 827 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}}
 828 @end itemize
 829
 830
 831 @itemize @bullet
 832 @item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
 833 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}}
 834 @end itemize
 835
 836
 837
 838
 839 @subsubsection Multiply-subtract
 840
 841 @itemize @bullet
 842 @item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 843 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
 844 @end itemize
 845
 846
 847 @itemize @bullet
 848 @item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 849 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
 850 @end itemize
 851
 852
 853 @itemize @bullet
 854 @item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 855 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
 856 @end itemize
 857
 858
 859 @itemize @bullet
 860 @item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
 861 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
 862 @end itemize
 863
 864
 865 @itemize @bullet
 866 @item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
 867 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
 868 @end itemize
 869
 870
 871 @itemize @bullet
 872 @item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
 873 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
 874 @end itemize
 875
 876
 877 @itemize @bullet
 878 @item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
 879 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}}
 880 @end itemize
 881
 882
 883 @itemize @bullet
 884 @item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 885 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
 886 @end itemize
 887
 888
 889 @itemize @bullet
 890 @item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 891 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
 892 @end itemize
 893
 894
 895 @itemize @bullet
 896 @item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 897 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
 898 @end itemize
 899
 900
 901 @itemize @bullet
 902 @item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
 903 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
 904 @end itemize
 905
 906
 907 @itemize @bullet
 908 @item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
 909 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
 910 @end itemize
 911
 912
 913 @itemize @bullet
 914 @item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
 915 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
 916 @end itemize
 917
 918
 919 @itemize @bullet
 920 @item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
 921 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}}
 922 @end itemize
 923
 924
 925 @itemize @bullet
 926 @item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 927 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}}
 928 @end itemize
 929
 930
 931 @itemize @bullet
 932 @item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 933 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}}
 934 @end itemize
 935
 936
 937 @itemize @bullet
 938 @item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 939 @*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
 940 @end itemize
 941
 942
 943 @itemize @bullet
 944 @item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
 945 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
 946 @end itemize
 947
 948
 949 @itemize @bullet
 950 @item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
 951 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
 952 @end itemize
 953
 954
 955 @itemize @bullet
 956 @item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
 957 @*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
 958 @end itemize
 959
 960
 961 @itemize @bullet
 962 @item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
 963 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
 964 @end itemize
 965
 966
 967 @itemize @bullet
 968 @item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
 969 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
 970 @end itemize
 971
 972
 973
 974
 975 @subsubsection Fused-multiply-accumulate
 976
 977 @itemize @bullet
 978 @item float32x2_t vfma_f32 (float32x2_t, float32x2_t, float32x2_t)
 979 @*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{d0}, @var{d0}, @var{d0}}
 980 @end itemize
 981
 982
 983 @itemize @bullet
 984 @item float32x4_t vfmaq_f32 (float32x4_t, float32x4_t, float32x4_t)
 985 @*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{q0}, @var{q0}, @var{q0}}
 986 @end itemize
 987
 988
 989
 990
 991 @subsubsection Fused-multiply-subtract
 992
 993 @itemize @bullet
 994 @item float32x2_t vfms_f32 (float32x2_t, float32x2_t, float32x2_t)
 995 @*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{d0}, @var{d0}, @var{d0}}
 996 @end itemize
 997
 998
 999 @itemize @bullet
1000 @item float32x4_t vfmsq_f32 (float32x4_t, float32x4_t, float32x4_t)
1001 @*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{q0}, @var{q0}, @var{q0}}
1002 @end itemize
1003
1004
1005
1006
1007 @subsubsection Round to integral (to nearest, ties to even)
1008
1009 @itemize @bullet
1010 @item float32x2_t vrndn_f32 (float32x2_t)
1011 @*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{d0}, @var{d0}}
1012 @end itemize
1013
1014
1015 @itemize @bullet
1016 @item float32x4_t vrndqn_f32 (float32x4_t)
1017 @*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{q0}, @var{q0}}
1018 @end itemize
1019
1020
1021
1022
1023 @subsubsection Round to integral (to nearest, ties away from zero)
1024
1025 @itemize @bullet
1026 @item float32x2_t vrnda_f32 (float32x2_t)
1027 @*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{d0}, @var{d0}}
1028 @end itemize
1029
1030
1031 @itemize @bullet
1032 @item float32x4_t vrndqa_f32 (float32x4_t)
1033 @*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{q0}, @var{q0}}
1034 @end itemize
1035
1036
1037
1038
1039 @subsubsection Round to integral (towards +Inf)
1040
1041 @itemize @bullet
1042 @item float32x2_t vrndp_f32 (float32x2_t)
1043 @*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{d0}, @var{d0}}
1044 @end itemize
1045
1046
1047 @itemize @bullet
1048 @item float32x4_t vrndqp_f32 (float32x4_t)
1049 @*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{q0}, @var{q0}}
1050 @end itemize
1051
1052
1053
1054
1055 @subsubsection Round to integral (towards -Inf)
1056
1057 @itemize @bullet
1058 @item float32x2_t vrndm_f32 (float32x2_t)
1059 @*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{d0}, @var{d0}}
1060 @end itemize
1061
1062
1063 @itemize @bullet
1064 @item float32x4_t vrndqm_f32 (float32x4_t)
1065 @*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{q0}, @var{q0}}
1066 @end itemize
1067
1068
1069
1070
1071 @subsubsection Round to integral (towards 0)
1072
1073 @itemize @bullet
1074 @item float32x2_t vrnd_f32 (float32x2_t)
1075 @*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{d0}, @var{d0}}
1076 @end itemize
1077
1078
1079 @itemize @bullet
1080 @item float32x4_t vrndq_f32 (float32x4_t)
1081 @*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{q0}, @var{q0}}
1082 @end itemize
1083
1084
1085
1086
1087 @subsubsection Subtraction
1088
1089 @itemize @bullet
1090 @item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
1091 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1092 @end itemize
1093
1094
1095 @itemize @bullet
1096 @item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
1097 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1098 @end itemize
1099
1100
1101 @itemize @bullet
1102 @item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
1103 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1104 @end itemize
1105
1106
1107 @itemize @bullet
1108 @item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
1109 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1110 @end itemize
1111
1112
1113 @itemize @bullet
1114 @item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
1115 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1116 @end itemize
1117
1118
1119 @itemize @bullet
1120 @item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
1121 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1122 @end itemize
1123
1124
1125 @itemize @bullet
1126 @item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1127 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1128 @end itemize
1129
1130
1131 @itemize @bullet
1132 @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
1133 @end itemize
1134
1135
1136 @itemize @bullet
1137 @item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
1138 @end itemize
1139
1140
1141 @itemize @bullet
1142 @item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
1143 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1144 @end itemize
1145
1146
1147 @itemize @bullet
1148 @item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
1149 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1150 @end itemize
1151
1152
1153 @itemize @bullet
1154 @item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
1155 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1156 @end itemize
1157
1158
1159 @itemize @bullet
1160 @item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
1161 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1162 @end itemize
1163
1164
1165 @itemize @bullet
1166 @item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
1167 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1168 @end itemize
1169
1170
1171 @itemize @bullet
1172 @item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
1173 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1174 @end itemize
1175
1176
1177 @itemize @bullet
1178 @item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
1179 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1180 @end itemize
1181
1182
1183 @itemize @bullet
1184 @item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
1185 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1186 @end itemize
1187
1188
1189 @itemize @bullet
1190 @item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
1191 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
1192 @end itemize
1193
1194
1195 @itemize @bullet
1196 @item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
1197 @*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
1198 @end itemize
1199
1200
1201 @itemize @bullet
1202 @item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
1203 @*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
1204 @end itemize
1205
1206
1207 @itemize @bullet
1208 @item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
1209 @*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
1210 @end itemize
1211
1212
1213 @itemize @bullet
1214 @item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
1215 @*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
1216 @end itemize
1217
1218
1219 @itemize @bullet
1220 @item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
1221 @*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
1222 @end itemize
1223
1224
1225 @itemize @bullet
1226 @item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
1227 @*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
1228 @end itemize
1229
1230
1231 @itemize @bullet
1232 @item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
1233 @*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
1234 @end itemize
1235
1236
1237 @itemize @bullet
1238 @item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
1239 @*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
1240 @end itemize
1241
1242
1243 @itemize @bullet
1244 @item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
1245 @*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
1246 @end itemize
1247
1248
1249 @itemize @bullet
1250 @item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
1251 @*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
1252 @end itemize
1253
1254
1255 @itemize @bullet
1256 @item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
1257 @*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
1258 @end itemize
1259
1260
1261 @itemize @bullet
1262 @item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
1263 @*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
1264 @end itemize
1265
1266
1267 @itemize @bullet
1268 @item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
1269 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
1270 @end itemize
1271
1272
1273 @itemize @bullet
1274 @item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
1275 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
1276 @end itemize
1277
1278
1279 @itemize @bullet
1280 @item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
1281 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
1282 @end itemize
1283
1284
1285 @itemize @bullet
1286 @item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
1287 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
1288 @end itemize
1289
1290
1291 @itemize @bullet
1292 @item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
1293 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
1294 @end itemize
1295
1296
1297 @itemize @bullet
1298 @item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
1299 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
1300 @end itemize
1301
1302
1303 @itemize @bullet
1304 @item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
1305 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
1306 @end itemize
1307
1308
1309 @itemize @bullet
1310 @item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
1311 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
1312 @end itemize
1313
1314
1315 @itemize @bullet
1316 @item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
1317 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
1318 @end itemize
1319
1320
1321 @itemize @bullet
1322 @item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
1323 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
1324 @end itemize
1325
1326
1327 @itemize @bullet
1328 @item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
1329 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
1330 @end itemize
1331
1332
1333 @itemize @bullet
1334 @item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
1335 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
1336 @end itemize
1337
1338
1339 @itemize @bullet
1340 @item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
1341 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
1342 @end itemize
1343
1344
1345 @itemize @bullet
1346 @item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
1347 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
1348 @end itemize
1349
1350
1351 @itemize @bullet
1352 @item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
1353 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
1354 @end itemize
1355
1356
1357 @itemize @bullet
1358 @item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
1359 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
1360 @end itemize
1361
1362
1363 @itemize @bullet
1364 @item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
1365 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
1366 @end itemize
1367
1368
1369 @itemize @bullet
1370 @item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
1371 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
1372 @end itemize
1373
1374
1375 @itemize @bullet
1376 @item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
1377 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
1378 @end itemize
1379
1380
1381 @itemize @bullet
1382 @item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
1383 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
1384 @end itemize
1385
1386
1387 @itemize @bullet
1388 @item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
1389 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
1390 @end itemize
1391
1392
1393 @itemize @bullet
1394 @item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
1395 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
1396 @end itemize
1397
1398
1399 @itemize @bullet
1400 @item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
1401 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
1402 @end itemize
1403
1404
1405 @itemize @bullet
1406 @item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
1407 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
1408 @end itemize
1409
1410
1411 @itemize @bullet
1412 @item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
1413 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
1414 @end itemize
1415
1416
1417 @itemize @bullet
1418 @item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
1419 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
1420 @end itemize
1421
1422
1423 @itemize @bullet
1424 @item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
1425 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
1426 @end itemize
1427
1428
1429 @itemize @bullet
1430 @item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
1431 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
1432 @end itemize
1433
1434
1435 @itemize @bullet
1436 @item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
1437 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1438 @end itemize
1439
1440
1441 @itemize @bullet
1442 @item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
1443 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1444 @end itemize
1445
1446
1447 @itemize @bullet
1448 @item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
1449 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1450 @end itemize
1451
1452
1453 @itemize @bullet
1454 @item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
1455 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1456 @end itemize
1457
1458
1459 @itemize @bullet
1460 @item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
1461 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1462 @end itemize
1463
1464
1465 @itemize @bullet
1466 @item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
1467 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1468 @end itemize
1469
1470
1471 @itemize @bullet
1472 @item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
1473 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1474 @end itemize
1475
1476
1477 @itemize @bullet
1478 @item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
1479 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1480 @end itemize
1481
1482
1483 @itemize @bullet
1484 @item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
1485 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1486 @end itemize
1487
1488
1489 @itemize @bullet
1490 @item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
1491 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1492 @end itemize
1493
1494
1495 @itemize @bullet
1496 @item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
1497 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1498 @end itemize
1499
1500
1501 @itemize @bullet
1502 @item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
1503 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1504 @end itemize
1505
1506
1507
1508
1509 @subsubsection Comparison (equal-to)
1510
1511 @itemize @bullet
1512 @item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
1513 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1514 @end itemize
1515
1516
1517 @itemize @bullet
1518 @item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
1519 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1520 @end itemize
1521
1522
1523 @itemize @bullet
1524 @item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
1525 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1526 @end itemize
1527
1528
1529 @itemize @bullet
1530 @item uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
1531 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1532 @end itemize
1533
1534
1535 @itemize @bullet
1536 @item uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
1537 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1538 @end itemize
1539
1540
1541 @itemize @bullet
1542 @item uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
1543 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1544 @end itemize
1545
1546
1547 @itemize @bullet
1548 @item uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
1549 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}}
1550 @end itemize
1551
1552
1553 @itemize @bullet
1554 @item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
1555 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1556 @end itemize
1557
1558
1559 @itemize @bullet
1560 @item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
1561 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1562 @end itemize
1563
1564
1565 @itemize @bullet
1566 @item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
1567 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1568 @end itemize
1569
1570
1571 @itemize @bullet
1572 @item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
1573 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1574 @end itemize
1575
1576
1577 @itemize @bullet
1578 @item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
1579 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1580 @end itemize
1581
1582
1583 @itemize @bullet
1584 @item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
1585 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1586 @end itemize
1587
1588
1589 @itemize @bullet
1590 @item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
1591 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1592 @end itemize
1593
1594
1595 @itemize @bullet
1596 @item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
1597 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}}
1598 @end itemize
1599
1600
1601 @itemize @bullet
1602 @item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
1603 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1604 @end itemize
1605
1606
1607
1608
1609 @subsubsection Comparison (greater-than-or-equal-to)
1610
1611 @itemize @bullet
1612 @item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
1613 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1614 @end itemize
1615
1616
1617 @itemize @bullet
1618 @item uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
1619 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1620 @end itemize
1621
1622
1623 @itemize @bullet
1624 @item uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
1625 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1626 @end itemize
1627
1628
1629 @itemize @bullet
1630 @item uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
1631 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1632 @end itemize
1633
1634
1635 @itemize @bullet
1636 @item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
1637 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1638 @end itemize
1639
1640
1641 @itemize @bullet
1642 @item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
1643 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1644 @end itemize
1645
1646
1647 @itemize @bullet
1648 @item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
1649 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1650 @end itemize
1651
1652
1653 @itemize @bullet
1654 @item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
1655 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1656 @end itemize
1657
1658
1659 @itemize @bullet
1660 @item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
1661 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1662 @end itemize
1663
1664
1665 @itemize @bullet
1666 @item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
1667 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1668 @end itemize
1669
1670
1671 @itemize @bullet
1672 @item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
1673 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1674 @end itemize
1675
1676
1677 @itemize @bullet
1678 @item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
1679 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1680 @end itemize
1681
1682
1683 @itemize @bullet
1684 @item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
1685 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1686 @end itemize
1687
1688
1689 @itemize @bullet
1690 @item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
1691 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1692 @end itemize
1693
1694
1695
1696
1697 @subsubsection Comparison (less-than-or-equal-to)
1698
1699 @itemize @bullet
1700 @item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
1701 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1702 @end itemize
1703
1704
1705 @itemize @bullet
1706 @item uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
1707 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1708 @end itemize
1709
1710
1711 @itemize @bullet
1712 @item uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
1713 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1714 @end itemize
1715
1716
1717 @itemize @bullet
1718 @item uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
1719 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1720 @end itemize
1721
1722
1723 @itemize @bullet
1724 @item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
1725 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1726 @end itemize
1727
1728
1729 @itemize @bullet
1730 @item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
1731 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1732 @end itemize
1733
1734
1735 @itemize @bullet
1736 @item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
1737 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1738 @end itemize
1739
1740
1741 @itemize @bullet
1742 @item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
1743 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1744 @end itemize
1745
1746
1747 @itemize @bullet
1748 @item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
1749 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1750 @end itemize
1751
1752
1753 @itemize @bullet
1754 @item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
1755 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1756 @end itemize
1757
1758
1759 @itemize @bullet
1760 @item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
1761 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1762 @end itemize
1763
1764
1765 @itemize @bullet
1766 @item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
1767 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1768 @end itemize
1769
1770
1771 @itemize @bullet
1772 @item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
1773 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1774 @end itemize
1775
1776
1777 @itemize @bullet
1778 @item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
1779 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1780 @end itemize
1781
1782
1783
1784
1785 @subsubsection Comparison (greater-than)
1786
1787 @itemize @bullet
1788 @item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
1789 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1790 @end itemize
1791
1792
1793 @itemize @bullet
1794 @item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
1795 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1796 @end itemize
1797
1798
1799 @itemize @bullet
1800 @item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
1801 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1802 @end itemize
1803
1804
1805 @itemize @bullet
1806 @item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
1807 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1808 @end itemize
1809
1810
1811 @itemize @bullet
1812 @item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
1813 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1814 @end itemize
1815
1816
1817 @itemize @bullet
1818 @item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
1819 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1820 @end itemize
1821
1822
1823 @itemize @bullet
1824 @item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
1825 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1826 @end itemize
1827
1828
1829 @itemize @bullet
1830 @item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
1831 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1832 @end itemize
1833
1834
1835 @itemize @bullet
1836 @item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
1837 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1838 @end itemize
1839
1840
1841 @itemize @bullet
1842 @item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
1843 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1844 @end itemize
1845
1846
1847 @itemize @bullet
1848 @item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
1849 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1850 @end itemize
1851
1852
1853 @itemize @bullet
1854 @item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
1855 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1856 @end itemize
1857
1858
1859 @itemize @bullet
1860 @item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
1861 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1862 @end itemize
1863
1864
1865 @itemize @bullet
1866 @item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
1867 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1868 @end itemize
1869
1870
1871
1872
1873 @subsubsection Comparison (less-than)
1874
1875 @itemize @bullet
1876 @item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
1877 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1878 @end itemize
1879
1880
1881 @itemize @bullet
1882 @item uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
1883 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1884 @end itemize
1885
1886
1887 @itemize @bullet
1888 @item uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
1889 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1890 @end itemize
1891
1892
1893 @itemize @bullet
1894 @item uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
1895 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1896 @end itemize
1897
1898
1899 @itemize @bullet
1900 @item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
1901 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1902 @end itemize
1903
1904
1905 @itemize @bullet
1906 @item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
1907 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1908 @end itemize
1909
1910
1911 @itemize @bullet
1912 @item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
1913 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1914 @end itemize
1915
1916
1917 @itemize @bullet
1918 @item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
1919 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1920 @end itemize
1921
1922
1923 @itemize @bullet
1924 @item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
1925 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1926 @end itemize
1927
1928
1929 @itemize @bullet
1930 @item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
1931 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1932 @end itemize
1933
1934
1935 @itemize @bullet
1936 @item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
1937 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1938 @end itemize
1939
1940
1941 @itemize @bullet
1942 @item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
1943 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1944 @end itemize
1945
1946
1947 @itemize @bullet
1948 @item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
1949 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1950 @end itemize
1951
1952
1953 @itemize @bullet
1954 @item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
1955 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1956 @end itemize
1957
1958
1959
1960
1961 @subsubsection Comparison (absolute greater-than-or-equal-to)
1962
1963 @itemize @bullet
1964 @item uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
1965 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1966 @end itemize
1967
1968
1969 @itemize @bullet
1970 @item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
1971 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1972 @end itemize
1973
1974
1975
1976
1977 @subsubsection Comparison (absolute less-than-or-equal-to)
1978
1979 @itemize @bullet
1980 @item uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
1981 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1982 @end itemize
1983
1984
1985 @itemize @bullet
1986 @item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
1987 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1988 @end itemize
1989
1990
1991
1992
1993 @subsubsection Comparison (absolute greater-than)
1994
1995 @itemize @bullet
1996 @item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
1997 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1998 @end itemize
1999
2000
2001 @itemize @bullet
2002 @item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
2003 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
2004 @end itemize
2005
2006
2007
2008
2009 @subsubsection Comparison (absolute less-than)
2010
2011 @itemize @bullet
2012 @item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
2013 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
2014 @end itemize
2015
2016
2017 @itemize @bullet
2018 @item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
2019 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
2020 @end itemize
2021
2022
2023
2024
2025 @subsubsection Test bits
2026
2027 @itemize @bullet
2028 @item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
2029 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
2030 @end itemize
2031
2032
2033 @itemize @bullet
2034 @item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
2035 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
2036 @end itemize
2037
2038
2039 @itemize @bullet
2040 @item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
2041 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2042 @end itemize
2043
2044
2045 @itemize @bullet
2046 @item uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
2047 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
2048 @end itemize
2049
2050
2051 @itemize @bullet
2052 @item uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
2053 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
2054 @end itemize
2055
2056
2057 @itemize @bullet
2058 @item uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
2059 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2060 @end itemize
2061
2062
2063 @itemize @bullet
2064 @item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
2065 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2066 @end itemize
2067
2068
2069 @itemize @bullet
2070 @item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
2071 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
2072 @end itemize
2073
2074
2075 @itemize @bullet
2076 @item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
2077 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
2078 @end itemize
2079
2080
2081 @itemize @bullet
2082 @item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
2083 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2084 @end itemize
2085
2086
2087 @itemize @bullet
2088 @item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
2089 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
2090 @end itemize
2091
2092
2093 @itemize @bullet
2094 @item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
2095 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
2096 @end itemize
2097
2098
2099 @itemize @bullet
2100 @item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
2101 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2102 @end itemize
2103
2104
2105 @itemize @bullet
2106 @item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
2107 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2108 @end itemize
2109
2110
2111
2112
2113 @subsubsection Absolute difference
2114
2115 @itemize @bullet
2116 @item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
2117 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}}
2118 @end itemize
2119
2120
2121 @itemize @bullet
2122 @item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
2123 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}}
2124 @end itemize
2125
2126
2127 @itemize @bullet
2128 @item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
2129 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}}
2130 @end itemize
2131
2132
2133 @itemize @bullet
2134 @item int32x2_t vabd_s32 (int32x2_t, int32x2_t)
2135 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}}
2136 @end itemize
2137
2138
2139 @itemize @bullet
2140 @item int16x4_t vabd_s16 (int16x4_t, int16x4_t)
2141 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}}
2142 @end itemize
2143
2144
2145 @itemize @bullet
2146 @item int8x8_t vabd_s8 (int8x8_t, int8x8_t)
2147 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}}
2148 @end itemize
2149
2150
2151 @itemize @bullet
2152 @item float32x2_t vabd_f32 (float32x2_t, float32x2_t)
2153 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}}
2154 @end itemize
2155
2156
2157 @itemize @bullet
2158 @item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
2159 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}}
2160 @end itemize
2161
2162
2163 @itemize @bullet
2164 @item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
2165 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}}
2166 @end itemize
2167
2168
2169 @itemize @bullet
2170 @item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
2171 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}}
2172 @end itemize
2173
2174
2175 @itemize @bullet
2176 @item int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
2177 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}}
2178 @end itemize
2179
2180
2181 @itemize @bullet
2182 @item int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
2183 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}}
2184 @end itemize
2185
2186
2187 @itemize @bullet
2188 @item int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
2189 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}}
2190 @end itemize
2191
2192
2193 @itemize @bullet
2194 @item float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
2195 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}}
2196 @end itemize
2197
2198
2199 @itemize @bullet
2200 @item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
2201 @*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}}
2202 @end itemize
2203
2204
2205 @itemize @bullet
2206 @item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
2207 @*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}}
2208 @end itemize
2209
2210
2211 @itemize @bullet
2212 @item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
2213 @*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}}
2214 @end itemize
2215
2216
2217 @itemize @bullet
2218 @item int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
2219 @*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}}
2220 @end itemize
2221
2222
2223 @itemize @bullet
2224 @item int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
2225 @*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}}
2226 @end itemize
2227
2228
2229 @itemize @bullet
2230 @item int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
2231 @*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}}
2232 @end itemize
2233
2234
2235
2236
2237 @subsubsection Absolute difference and accumulate
2238
2239 @itemize @bullet
2240 @item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
2241 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}}
2242 @end itemize
2243
2244
2245 @itemize @bullet
2246 @item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
2247 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}}
2248 @end itemize
2249
2250
2251 @itemize @bullet
2252 @item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
2253 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}}
2254 @end itemize
2255
2256
2257 @itemize @bullet
2258 @item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
2259 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}}
2260 @end itemize
2261
2262
2263 @itemize @bullet
2264 @item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
2265 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}}
2266 @end itemize
2267
2268
2269 @itemize @bullet
2270 @item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
2271 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}}
2272 @end itemize
2273
2274
2275 @itemize @bullet
2276 @item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2277 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}}
2278 @end itemize
2279
2280
2281 @itemize @bullet
2282 @item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
2283 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}}
2284 @end itemize
2285
2286
2287 @itemize @bullet
2288 @item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
2289 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}}
2290 @end itemize
2291
2292
2293 @itemize @bullet
2294 @item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
2295 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}}
2296 @end itemize
2297
2298
2299 @itemize @bullet
2300 @item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
2301 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}}
2302 @end itemize
2303
2304
2305 @itemize @bullet
2306 @item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
2307 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}}
2308 @end itemize
2309
2310
2311 @itemize @bullet
2312 @item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
2313 @*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}}
2314 @end itemize
2315
2316
2317 @itemize @bullet
2318 @item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
2319 @*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}}
2320 @end itemize
2321
2322
2323 @itemize @bullet
2324 @item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
2325 @*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}}
2326 @end itemize
2327
2328
2329 @itemize @bullet
2330 @item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
2331 @*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}}
2332 @end itemize
2333
2334
2335 @itemize @bullet
2336 @item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
2337 @*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}}
2338 @end itemize
2339
2340
2341 @itemize @bullet
2342 @item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
2343 @*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}}
2344 @end itemize
2345
2346
2347
2348
2349 @subsubsection Maximum
2350
2351 @itemize @bullet
2352 @item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
2353 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}}
2354 @end itemize
2355
2356
2357 @itemize @bullet
2358 @item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
2359 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}}
2360 @end itemize
2361
2362
2363 @itemize @bullet
2364 @item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
2365 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}}
2366 @end itemize
2367
2368
2369 @itemize @bullet
2370 @item int32x2_t vmax_s32 (int32x2_t, int32x2_t)
2371 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}}
2372 @end itemize
2373
2374
2375 @itemize @bullet
2376 @item int16x4_t vmax_s16 (int16x4_t, int16x4_t)
2377 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}}
2378 @end itemize
2379
2380
2381 @itemize @bullet
2382 @item int8x8_t vmax_s8 (int8x8_t, int8x8_t)
2383 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}}
2384 @end itemize
2385
2386
2387 @itemize @bullet
2388 @item float32x2_t vmax_f32 (float32x2_t, float32x2_t)
2389 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}}
2390 @end itemize
2391
2392
2393 @itemize @bullet
2394 @item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
2395 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}}
2396 @end itemize
2397
2398
2399 @itemize @bullet
2400 @item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
2401 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}}
2402 @end itemize
2403
2404
2405 @itemize @bullet
2406 @item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
2407 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}}
2408 @end itemize
2409
2410
2411 @itemize @bullet
2412 @item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
2413 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}}
2414 @end itemize
2415
2416
2417 @itemize @bullet
2418 @item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
2419 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}}
2420 @end itemize
2421
2422
2423 @itemize @bullet
2424 @item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
2425 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}}
2426 @end itemize
2427
2428
2429 @itemize @bullet
2430 @item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
2431 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}}
2432 @end itemize
2433
2434
2435
2436
2437 @subsubsection Minimum
2438
2439 @itemize @bullet
2440 @item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
2441 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}}
2442 @end itemize
2443
2444
2445 @itemize @bullet
2446 @item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
2447 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}}
2448 @end itemize
2449
2450
2451 @itemize @bullet
2452 @item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
2453 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}}
2454 @end itemize
2455
2456
2457 @itemize @bullet
2458 @item int32x2_t vmin_s32 (int32x2_t, int32x2_t)
2459 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}}
2460 @end itemize
2461
2462
2463 @itemize @bullet
2464 @item int16x4_t vmin_s16 (int16x4_t, int16x4_t)
2465 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}}
2466 @end itemize
2467
2468
2469 @itemize @bullet
2470 @item int8x8_t vmin_s8 (int8x8_t, int8x8_t)
2471 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}}
2472 @end itemize
2473
2474
2475 @itemize @bullet
2476 @item float32x2_t vmin_f32 (float32x2_t, float32x2_t)
2477 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}}
2478 @end itemize
2479
2480
2481 @itemize @bullet
2482 @item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
2483 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}}
2484 @end itemize
2485
2486
2487 @itemize @bullet
2488 @item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
2489 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}}
2490 @end itemize
2491
2492
2493 @itemize @bullet
2494 @item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
2495 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}}
2496 @end itemize
2497
2498
2499 @itemize @bullet
2500 @item int32x4_t vminq_s32 (int32x4_t, int32x4_t)
2501 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}}
2502 @end itemize
2503
2504
2505 @itemize @bullet
2506 @item int16x8_t vminq_s16 (int16x8_t, int16x8_t)
2507 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}}
2508 @end itemize
2509
2510
2511 @itemize @bullet
2512 @item int8x16_t vminq_s8 (int8x16_t, int8x16_t)
2513 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}}
2514 @end itemize
2515
2516
2517 @itemize @bullet
2518 @item float32x4_t vminq_f32 (float32x4_t, float32x4_t)
2519 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}}
2520 @end itemize
2521
2522
2523
2524
2525 @subsubsection Pairwise add
2526
2527 @itemize @bullet
2528 @item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
2529 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2530 @end itemize
2531
2532
2533 @itemize @bullet
2534 @item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
2535 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2536 @end itemize
2537
2538
2539 @itemize @bullet
2540 @item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
2541 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2542 @end itemize
2543
2544
2545 @itemize @bullet
2546 @item int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
2547 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2548 @end itemize
2549
2550
2551 @itemize @bullet
2552 @item int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
2553 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2554 @end itemize
2555
2556
2557 @itemize @bullet
2558 @item int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
2559 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2560 @end itemize
2561
2562
2563 @itemize @bullet
2564 @item float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
2565 @*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}}
2566 @end itemize
2567
2568
2569 @itemize @bullet
2570 @item uint64x1_t vpaddl_u32 (uint32x2_t)
2571 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}}
2572 @end itemize
2573
2574
2575 @itemize @bullet
2576 @item uint32x2_t vpaddl_u16 (uint16x4_t)
2577 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}}
2578 @end itemize
2579
2580
2581 @itemize @bullet
2582 @item uint16x4_t vpaddl_u8 (uint8x8_t)
2583 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}}
2584 @end itemize
2585
2586
2587 @itemize @bullet
2588 @item int64x1_t vpaddl_s32 (int32x2_t)
2589 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}}
2590 @end itemize
2591
2592
2593 @itemize @bullet
2594 @item int32x2_t vpaddl_s16 (int16x4_t)
2595 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}}
2596 @end itemize
2597
2598
2599 @itemize @bullet
2600 @item int16x4_t vpaddl_s8 (int8x8_t)
2601 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}}
2602 @end itemize
2603
2604
2605 @itemize @bullet
2606 @item uint64x2_t vpaddlq_u32 (uint32x4_t)
2607 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}}
2608 @end itemize
2609
2610
2611 @itemize @bullet
2612 @item uint32x4_t vpaddlq_u16 (uint16x8_t)
2613 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}}
2614 @end itemize
2615
2616
2617 @itemize @bullet
2618 @item uint16x8_t vpaddlq_u8 (uint8x16_t)
2619 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}}
2620 @end itemize
2621
2622
2623 @itemize @bullet
2624 @item int64x2_t vpaddlq_s32 (int32x4_t)
2625 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}}
2626 @end itemize
2627
2628
2629 @itemize @bullet
2630 @item int32x4_t vpaddlq_s16 (int16x8_t)
2631 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}}
2632 @end itemize
2633
2634
2635 @itemize @bullet
2636 @item int16x8_t vpaddlq_s8 (int8x16_t)
2637 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}}
2638 @end itemize
2639
2640
2641
2642
2643 @subsubsection Pairwise add, single_opcode widen and accumulate
2644
2645 @itemize @bullet
2646 @item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
2647 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}}
2648 @end itemize
2649
2650
2651 @itemize @bullet
2652 @item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
2653 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}}
2654 @end itemize
2655
2656
2657 @itemize @bullet
2658 @item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
2659 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}}
2660 @end itemize
2661
2662
2663 @itemize @bullet
2664 @item int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
2665 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}}
2666 @end itemize
2667
2668
2669 @itemize @bullet
2670 @item int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
2671 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}}
2672 @end itemize
2673
2674
2675 @itemize @bullet
2676 @item int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
2677 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}}
2678 @end itemize
2679
2680
2681 @itemize @bullet
2682 @item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
2683 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}}
2684 @end itemize
2685
2686
2687 @itemize @bullet
2688 @item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
2689 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}}
2690 @end itemize
2691
2692
2693 @itemize @bullet
2694 @item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
2695 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}}
2696 @end itemize
2697
2698
2699 @itemize @bullet
2700 @item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
2701 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}}
2702 @end itemize
2703
2704
2705 @itemize @bullet
2706 @item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
2707 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}}
2708 @end itemize
2709
2710
2711 @itemize @bullet
2712 @item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
2713 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}}
2714 @end itemize
2715
2716
2717
2718
2719 @subsubsection Folding maximum
2720
2721 @itemize @bullet
2722 @item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
2723 @*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}}
2724 @end itemize
2725
2726
2727 @itemize @bullet
2728 @item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
2729 @*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}}
2730 @end itemize
2731
2732
2733 @itemize @bullet
2734 @item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
2735 @*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}}
2736 @end itemize
2737
2738
2739 @itemize @bullet
2740 @item int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
2741 @*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}}
2742 @end itemize
2743
2744
2745 @itemize @bullet
2746 @item int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
2747 @*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}}
2748 @end itemize
2749
2750
2751 @itemize @bullet
2752 @item int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
2753 @*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}}
2754 @end itemize
2755
2756
2757 @itemize @bullet
2758 @item float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
2759 @*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}}
2760 @end itemize
2761
2762
2763
2764
2765 @subsubsection Folding minimum
2766
2767 @itemize @bullet
2768 @item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
2769 @*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}}
2770 @end itemize
2771
2772
2773 @itemize @bullet
2774 @item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
2775 @*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}}
2776 @end itemize
2777
2778
2779 @itemize @bullet
2780 @item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
2781 @*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}}
2782 @end itemize
2783
2784
2785 @itemize @bullet
2786 @item int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
2787 @*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}}
2788 @end itemize
2789
2790
2791 @itemize @bullet
2792 @item int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
2793 @*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}}
2794 @end itemize
2795
2796
2797 @itemize @bullet
2798 @item int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
2799 @*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}}
2800 @end itemize
2801
2802
2803 @itemize @bullet
2804 @item float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
2805 @*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}}
2806 @end itemize
2807
2808
2809
2810
2811 @subsubsection Reciprocal step
2812
2813 @itemize @bullet
2814 @item float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
2815 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}}
2816 @end itemize
2817
2818
2819 @itemize @bullet
2820 @item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
2821 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}}
2822 @end itemize
2823
2824
2825 @itemize @bullet
2826 @item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
2827 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}}
2828 @end itemize
2829
2830
2831 @itemize @bullet
2832 @item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
2833 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}}
2834 @end itemize
2835
2836
2837
2838
2839 @subsubsection Vector shift left
2840
2841 @itemize @bullet
2842 @item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
2843 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}}
2844 @end itemize
2845
2846
2847 @itemize @bullet
2848 @item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
2849 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}}
2850 @end itemize
2851
2852
2853 @itemize @bullet
2854 @item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
2855 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}}
2856 @end itemize
2857
2858
2859 @itemize @bullet
2860 @item int32x2_t vshl_s32 (int32x2_t, int32x2_t)
2861 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}}
2862 @end itemize
2863
2864
2865 @itemize @bullet
2866 @item int16x4_t vshl_s16 (int16x4_t, int16x4_t)
2867 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}}
2868 @end itemize
2869
2870
2871 @itemize @bullet
2872 @item int8x8_t vshl_s8 (int8x8_t, int8x8_t)
2873 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}}
2874 @end itemize
2875
2876
2877 @itemize @bullet
2878 @item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
2879 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}}
2880 @end itemize
2881
2882
2883 @itemize @bullet
2884 @item int64x1_t vshl_s64 (int64x1_t, int64x1_t)
2885 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}}
2886 @end itemize
2887
2888
2889 @itemize @bullet
2890 @item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
2891 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}}
2892 @end itemize
2893
2894
2895 @itemize @bullet
2896 @item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
2897 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}}
2898 @end itemize
2899
2900
2901 @itemize @bullet
2902 @item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
2903 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}}
2904 @end itemize
2905
2906
2907 @itemize @bullet
2908 @item int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
2909 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}}
2910 @end itemize
2911
2912
2913 @itemize @bullet
2914 @item int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
2915 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}}
2916 @end itemize
2917
2918
2919 @itemize @bullet
2920 @item int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
2921 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}}
2922 @end itemize
2923
2924
2925 @itemize @bullet
2926 @item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
2927 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}}
2928 @end itemize
2929
2930
2931 @itemize @bullet
2932 @item int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
2933 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}}
2934 @end itemize
2935
2936
2937 @itemize @bullet
2938 @item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
2939 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}}
2940 @end itemize
2941
2942
2943 @itemize @bullet
2944 @item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
2945 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}}
2946 @end itemize
2947
2948
2949 @itemize @bullet
2950 @item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
2951 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}}
2952 @end itemize
2953
2954
2955 @itemize @bullet
2956 @item int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
2957 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}}
2958 @end itemize
2959
2960
2961 @itemize @bullet
2962 @item int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
2963 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}}
2964 @end itemize
2965
2966
2967 @itemize @bullet
2968 @item int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
2969 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}}
2970 @end itemize
2971
2972
2973 @itemize @bullet
2974 @item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
2975 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}}
2976 @end itemize
2977
2978
2979 @itemize @bullet
2980 @item int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
2981 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}}
2982 @end itemize
2983
2984
2985 @itemize @bullet
2986 @item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
2987 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}}
2988 @end itemize
2989
2990
2991 @itemize @bullet
2992 @item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
2993 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}}
2994 @end itemize
2995
2996
2997 @itemize @bullet
2998 @item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
2999 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3000 @end itemize
3001
3002
3003 @itemize @bullet
3004 @item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
3005 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3006 @end itemize
3007
3008
3009 @itemize @bullet
3010 @item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
3011 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3012 @end itemize
3013
3014
3015 @itemize @bullet
3016 @item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
3017 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3018 @end itemize
3019
3020
3021 @itemize @bullet
3022 @item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
3023 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3024 @end itemize
3025
3026
3027 @itemize @bullet
3028 @item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
3029 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3030 @end itemize
3031
3032
3033 @itemize @bullet
3034 @item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
3035 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}}
3036 @end itemize
3037
3038
3039 @itemize @bullet
3040 @item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
3041 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}}
3042 @end itemize
3043
3044
3045 @itemize @bullet
3046 @item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
3047 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}}
3048 @end itemize
3049
3050
3051 @itemize @bullet
3052 @item int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
3053 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}}
3054 @end itemize
3055
3056
3057 @itemize @bullet
3058 @item int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
3059 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}}
3060 @end itemize
3061
3062
3063 @itemize @bullet
3064 @item int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
3065 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}}
3066 @end itemize
3067
3068
3069 @itemize @bullet
3070 @item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
3071 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}}
3072 @end itemize
3073
3074
3075 @itemize @bullet
3076 @item int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
3077 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}}
3078 @end itemize
3079
3080
3081 @itemize @bullet
3082 @item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
3083 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}}
3084 @end itemize
3085
3086
3087 @itemize @bullet
3088 @item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
3089 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}}
3090 @end itemize
3091
3092
3093 @itemize @bullet
3094 @item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
3095 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}}
3096 @end itemize
3097
3098
3099 @itemize @bullet
3100 @item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
3101 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}}
3102 @end itemize
3103
3104
3105 @itemize @bullet
3106 @item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
3107 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}}
3108 @end itemize
3109
3110
3111 @itemize @bullet
3112 @item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
3113 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}}
3114 @end itemize
3115
3116
3117 @itemize @bullet
3118 @item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
3119 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}}
3120 @end itemize
3121
3122
3123 @itemize @bullet
3124 @item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
3125 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}}
3126 @end itemize
3127
3128
3129 @itemize @bullet
3130 @item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
3131 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}}
3132 @end itemize
3133
3134
3135 @itemize @bullet
3136 @item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
3137 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}}
3138 @end itemize
3139
3140
3141 @itemize @bullet
3142 @item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
3143 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}}
3144 @end itemize
3145
3146
3147 @itemize @bullet
3148 @item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
3149 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}}
3150 @end itemize
3151
3152
3153 @itemize @bullet
3154 @item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
3155 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}}
3156 @end itemize
3157
3158
3159 @itemize @bullet
3160 @item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
3161 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}}
3162 @end itemize
3163
3164
3165 @itemize @bullet
3166 @item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
3167 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}}
3168 @end itemize
3169
3170
3171 @itemize @bullet
3172 @item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
3173 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}}
3174 @end itemize
3175
3176
3177 @itemize @bullet
3178 @item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
3179 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}}
3180 @end itemize
3181
3182
3183 @itemize @bullet
3184 @item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
3185 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}}
3186 @end itemize
3187
3188
3189 @itemize @bullet
3190 @item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
3191 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3192 @end itemize
3193
3194
3195 @itemize @bullet
3196 @item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
3197 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3198 @end itemize
3199
3200
3201 @itemize @bullet
3202 @item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
3203 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3204 @end itemize
3205
3206
3207 @itemize @bullet
3208 @item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
3209 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3210 @end itemize
3211
3212
3213 @itemize @bullet
3214 @item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
3215 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3216 @end itemize
3217
3218
3219 @itemize @bullet
3220 @item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
3221 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3222 @end itemize
3223
3224
3225
3226
3227 @subsubsection Vector shift left by constant
3228
3229 @itemize @bullet
3230 @item uint32x2_t vshl_n_u32 (uint32x2_t, const int)
3231 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3232 @end itemize
3233
3234
3235 @itemize @bullet
3236 @item uint16x4_t vshl_n_u16 (uint16x4_t, const int)
3237 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3238 @end itemize
3239
3240
3241 @itemize @bullet
3242 @item uint8x8_t vshl_n_u8 (uint8x8_t, const int)
3243 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3244 @end itemize
3245
3246
3247 @itemize @bullet
3248 @item int32x2_t vshl_n_s32 (int32x2_t, const int)
3249 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3250 @end itemize
3251
3252
3253 @itemize @bullet
3254 @item int16x4_t vshl_n_s16 (int16x4_t, const int)
3255 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3256 @end itemize
3257
3258
3259 @itemize @bullet
3260 @item int8x8_t vshl_n_s8 (int8x8_t, const int)
3261 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3262 @end itemize
3263
3264
3265 @itemize @bullet
3266 @item uint64x1_t vshl_n_u64 (uint64x1_t, const int)
3267 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3268 @end itemize
3269
3270
3271 @itemize @bullet
3272 @item int64x1_t vshl_n_s64 (int64x1_t, const int)
3273 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3274 @end itemize
3275
3276
3277 @itemize @bullet
3278 @item uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
3279 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3280 @end itemize
3281
3282
3283 @itemize @bullet
3284 @item uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
3285 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3286 @end itemize
3287
3288
3289 @itemize @bullet
3290 @item uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
3291 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3292 @end itemize
3293
3294
3295 @itemize @bullet
3296 @item int32x4_t vshlq_n_s32 (int32x4_t, const int)
3297 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3298 @end itemize
3299
3300
3301 @itemize @bullet
3302 @item int16x8_t vshlq_n_s16 (int16x8_t, const int)
3303 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3304 @end itemize
3305
3306
3307 @itemize @bullet
3308 @item int8x16_t vshlq_n_s8 (int8x16_t, const int)
3309 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3310 @end itemize
3311
3312
3313 @itemize @bullet
3314 @item uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
3315 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3316 @end itemize
3317
3318
3319 @itemize @bullet
3320 @item int64x2_t vshlq_n_s64 (int64x2_t, const int)
3321 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3322 @end itemize
3323
3324
3325 @itemize @bullet
3326 @item uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
3327 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}}
3328 @end itemize
3329
3330
3331 @itemize @bullet
3332 @item uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
3333 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}}
3334 @end itemize
3335
3336
3337 @itemize @bullet
3338 @item uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
3339 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}}
3340 @end itemize
3341
3342
3343 @itemize @bullet
3344 @item int32x2_t vqshl_n_s32 (int32x2_t, const int)
3345 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}}
3346 @end itemize
3347
3348
3349 @itemize @bullet
3350 @item int16x4_t vqshl_n_s16 (int16x4_t, const int)
3351 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}}
3352 @end itemize
3353
3354
3355 @itemize @bullet
3356 @item int8x8_t vqshl_n_s8 (int8x8_t, const int)
3357 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}}
3358 @end itemize
3359
3360
3361 @itemize @bullet
3362 @item uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
3363 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}}
3364 @end itemize
3365
3366
3367 @itemize @bullet
3368 @item int64x1_t vqshl_n_s64 (int64x1_t, const int)
3369 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}}
3370 @end itemize
3371
3372
3373 @itemize @bullet
3374 @item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
3375 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}}
3376 @end itemize
3377
3378
3379 @itemize @bullet
3380 @item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
3381 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}}
3382 @end itemize
3383
3384
3385 @itemize @bullet
3386 @item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
3387 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}}
3388 @end itemize
3389
3390
3391 @itemize @bullet
3392 @item int32x4_t vqshlq_n_s32 (int32x4_t, const int)
3393 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}}
3394 @end itemize
3395
3396
3397 @itemize @bullet
3398 @item int16x8_t vqshlq_n_s16 (int16x8_t, const int)
3399 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}}
3400 @end itemize
3401
3402
3403 @itemize @bullet
3404 @item int8x16_t vqshlq_n_s8 (int8x16_t, const int)
3405 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}}
3406 @end itemize
3407
3408
3409 @itemize @bullet
3410 @item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
3411 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}}
3412 @end itemize
3413
3414
3415 @itemize @bullet
3416 @item int64x2_t vqshlq_n_s64 (int64x2_t, const int)
3417 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}}
3418 @end itemize
3419
3420
3421 @itemize @bullet
3422 @item uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
3423 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}}
3424 @end itemize
3425
3426
3427 @itemize @bullet
3428 @item uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
3429 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}}
3430 @end itemize
3431
3432
3433 @itemize @bullet
3434 @item uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
3435 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}}
3436 @end itemize
3437
3438
3439 @itemize @bullet
3440 @item uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
3441 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}}
3442 @end itemize
3443
3444
3445 @itemize @bullet
3446 @item uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
3447 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}}
3448 @end itemize
3449
3450
3451 @itemize @bullet
3452 @item uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
3453 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}}
3454 @end itemize
3455
3456
3457 @itemize @bullet
3458 @item uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
3459 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}}
3460 @end itemize
3461
3462
3463 @itemize @bullet
3464 @item uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
3465 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}}
3466 @end itemize
3467
3468
3469 @itemize @bullet
3470 @item uint64x2_t vshll_n_u32 (uint32x2_t, const int)
3471 @*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}}
3472 @end itemize
3473
3474
3475 @itemize @bullet
3476 @item uint32x4_t vshll_n_u16 (uint16x4_t, const int)
3477 @*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}}
3478 @end itemize
3479
3480
3481 @itemize @bullet
3482 @item uint16x8_t vshll_n_u8 (uint8x8_t, const int)
3483 @*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}}
3484 @end itemize
3485
3486
3487 @itemize @bullet
3488 @item int64x2_t vshll_n_s32 (int32x2_t, const int)
3489 @*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}}
3490 @end itemize
3491
3492
3493 @itemize @bullet
3494 @item int32x4_t vshll_n_s16 (int16x4_t, const int)
3495 @*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}}
3496 @end itemize
3497
3498
3499 @itemize @bullet
3500 @item int16x8_t vshll_n_s8 (int8x8_t, const int)
3501 @*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}}
3502 @end itemize
3503
3504
3505
3506
3507 @subsubsection Vector shift right by constant
3508
3509 @itemize @bullet
3510 @item uint32x2_t vshr_n_u32 (uint32x2_t, const int)
3511 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}}
3512 @end itemize
3513
3514
3515 @itemize @bullet
3516 @item uint16x4_t vshr_n_u16 (uint16x4_t, const int)
3517 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}}
3518 @end itemize
3519
3520
3521 @itemize @bullet
3522 @item uint8x8_t vshr_n_u8 (uint8x8_t, const int)
3523 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}}
3524 @end itemize
3525
3526
3527 @itemize @bullet
3528 @item int32x2_t vshr_n_s32 (int32x2_t, const int)
3529 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}}
3530 @end itemize
3531
3532
3533 @itemize @bullet
3534 @item int16x4_t vshr_n_s16 (int16x4_t, const int)
3535 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}}
3536 @end itemize
3537
3538
3539 @itemize @bullet
3540 @item int8x8_t vshr_n_s8 (int8x8_t, const int)
3541 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}}
3542 @end itemize
3543
3544
3545 @itemize @bullet
3546 @item uint64x1_t vshr_n_u64 (uint64x1_t, const int)
3547 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}}
3548 @end itemize
3549
3550
3551 @itemize @bullet
3552 @item int64x1_t vshr_n_s64 (int64x1_t, const int)
3553 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}}
3554 @end itemize
3555
3556
3557 @itemize @bullet
3558 @item uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
3559 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}}
3560 @end itemize
3561
3562
3563 @itemize @bullet
3564 @item uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
3565 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}}
3566 @end itemize
3567
3568
3569 @itemize @bullet
3570 @item uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
3571 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}}
3572 @end itemize
3573
3574
3575 @itemize @bullet
3576 @item int32x4_t vshrq_n_s32 (int32x4_t, const int)
3577 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}}
3578 @end itemize
3579
3580
3581 @itemize @bullet
3582 @item int16x8_t vshrq_n_s16 (int16x8_t, const int)
3583 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}}
3584 @end itemize
3585
3586
3587 @itemize @bullet
3588 @item int8x16_t vshrq_n_s8 (int8x16_t, const int)
3589 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}}
3590 @end itemize
3591
3592
3593 @itemize @bullet
3594 @item uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
3595 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}}
3596 @end itemize
3597
3598
3599 @itemize @bullet
3600 @item int64x2_t vshrq_n_s64 (int64x2_t, const int)
3601 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}}
3602 @end itemize
3603
3604
3605 @itemize @bullet
3606 @item uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
3607 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}}
3608 @end itemize
3609
3610
3611 @itemize @bullet
3612 @item uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
3613 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}}
3614 @end itemize
3615
3616
3617 @itemize @bullet
3618 @item uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
3619 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}}
3620 @end itemize
3621
3622
3623 @itemize @bullet
3624 @item int32x2_t vrshr_n_s32 (int32x2_t, const int)
3625 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}}
3626 @end itemize
3627
3628
3629 @itemize @bullet
3630 @item int16x4_t vrshr_n_s16 (int16x4_t, const int)
3631 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}}
3632 @end itemize
3633
3634
3635 @itemize @bullet
3636 @item int8x8_t vrshr_n_s8 (int8x8_t, const int)
3637 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}}
3638 @end itemize
3639
3640
3641 @itemize @bullet
3642 @item uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
3643 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}}
3644 @end itemize
3645
3646
3647 @itemize @bullet
3648 @item int64x1_t vrshr_n_s64 (int64x1_t, const int)
3649 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}}
3650 @end itemize
3651
3652
3653 @itemize @bullet
3654 @item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
3655 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}}
3656 @end itemize
3657
3658
3659 @itemize @bullet
3660 @item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
3661 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}}
3662 @end itemize
3663
3664
3665 @itemize @bullet
3666 @item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
3667 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}}
3668 @end itemize
3669
3670
3671 @itemize @bullet
3672 @item int32x4_t vrshrq_n_s32 (int32x4_t, const int)
3673 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}}
3674 @end itemize
3675
3676
3677 @itemize @bullet
3678 @item int16x8_t vrshrq_n_s16 (int16x8_t, const int)
3679 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}}
3680 @end itemize
3681
3682
3683 @itemize @bullet
3684 @item int8x16_t vrshrq_n_s8 (int8x16_t, const int)
3685 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}}
3686 @end itemize
3687
3688
3689 @itemize @bullet
3690 @item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
3691 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}}
3692 @end itemize
3693
3694
3695 @itemize @bullet
3696 @item int64x2_t vrshrq_n_s64 (int64x2_t, const int)
3697 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}}
3698 @end itemize
3699
3700
3701 @itemize @bullet
3702 @item uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
3703 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3704 @end itemize
3705
3706
3707 @itemize @bullet
3708 @item uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
3709 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3710 @end itemize
3711
3712
3713 @itemize @bullet
3714 @item uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
3715 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3716 @end itemize
3717
3718
3719 @itemize @bullet
3720 @item int32x2_t vshrn_n_s64 (int64x2_t, const int)
3721 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3722 @end itemize
3723
3724
3725 @itemize @bullet
3726 @item int16x4_t vshrn_n_s32 (int32x4_t, const int)
3727 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3728 @end itemize
3729
3730
3731 @itemize @bullet
3732 @item int8x8_t vshrn_n_s16 (int16x8_t, const int)
3733 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3734 @end itemize
3735
3736
3737 @itemize @bullet
3738 @item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
3739 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3740 @end itemize
3741
3742
3743 @itemize @bullet
3744 @item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
3745 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3746 @end itemize
3747
3748
3749 @itemize @bullet
3750 @item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
3751 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3752 @end itemize
3753
3754
3755 @itemize @bullet
3756 @item int32x2_t vrshrn_n_s64 (int64x2_t, const int)
3757 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3758 @end itemize
3759
3760
3761 @itemize @bullet
3762 @item int16x4_t vrshrn_n_s32 (int32x4_t, const int)
3763 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3764 @end itemize
3765
3766
3767 @itemize @bullet
3768 @item int8x8_t vrshrn_n_s16 (int16x8_t, const int)
3769 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3770 @end itemize
3771
3772
3773 @itemize @bullet
3774 @item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
3775 @*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3776 @end itemize
3777
3778
3779 @itemize @bullet
3780 @item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
3781 @*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3782 @end itemize
3783
3784
3785 @itemize @bullet
3786 @item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
3787 @*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3788 @end itemize
3789
3790
3791 @itemize @bullet
3792 @item int32x2_t vqshrn_n_s64 (int64x2_t, const int)
3793 @*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3794 @end itemize
3795
3796
3797 @itemize @bullet
3798 @item int16x4_t vqshrn_n_s32 (int32x4_t, const int)
3799 @*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3800 @end itemize
3801
3802
3803 @itemize @bullet
3804 @item int8x8_t vqshrn_n_s16 (int16x8_t, const int)
3805 @*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3806 @end itemize
3807
3808
3809 @itemize @bullet
3810 @item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
3811 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3812 @end itemize
3813
3814
3815 @itemize @bullet
3816 @item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
3817 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3818 @end itemize
3819
3820
3821 @itemize @bullet
3822 @item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
3823 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3824 @end itemize
3825
3826
3827 @itemize @bullet
3828 @item int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
3829 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3830 @end itemize
3831
3832
3833 @itemize @bullet
3834 @item int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
3835 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3836 @end itemize
3837
3838
3839 @itemize @bullet
3840 @item int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
3841 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3842 @end itemize
3843
3844
3845 @itemize @bullet
3846 @item uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
3847 @*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3848 @end itemize
3849
3850
3851 @itemize @bullet
3852 @item uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
3853 @*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3854 @end itemize
3855
3856
3857 @itemize @bullet
3858 @item uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
3859 @*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3860 @end itemize
3861
3862
3863 @itemize @bullet
3864 @item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
3865 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3866 @end itemize
3867
3868
3869 @itemize @bullet
3870 @item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
3871 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3872 @end itemize
3873
3874
3875 @itemize @bullet
3876 @item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
3877 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3878 @end itemize
3879
3880
3881
3882
3883 @subsubsection Vector shift right by constant and accumulate
3884
3885 @itemize @bullet
3886 @item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3887 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}}
3888 @end itemize
3889
3890
3891 @itemize @bullet
3892 @item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3893 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}}
3894 @end itemize
3895
3896
3897 @itemize @bullet
3898 @item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3899 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}}
3900 @end itemize
3901
3902
3903 @itemize @bullet
3904 @item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
3905 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}}
3906 @end itemize
3907
3908
3909 @itemize @bullet
3910 @item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
3911 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}}
3912 @end itemize
3913
3914
3915 @itemize @bullet
3916 @item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
3917 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}}
3918 @end itemize
3919
3920
3921 @itemize @bullet
3922 @item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3923 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}}
3924 @end itemize
3925
3926
3927 @itemize @bullet
3928 @item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
3929 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}}
3930 @end itemize
3931
3932
3933 @itemize @bullet
3934 @item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3935 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}}
3936 @end itemize
3937
3938
3939 @itemize @bullet
3940 @item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3941 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}}
3942 @end itemize
3943
3944
3945 @itemize @bullet
3946 @item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3947 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}}
3948 @end itemize
3949
3950
3951 @itemize @bullet
3952 @item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
3953 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}}
3954 @end itemize
3955
3956
3957 @itemize @bullet
3958 @item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
3959 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}}
3960 @end itemize
3961
3962
3963 @itemize @bullet
3964 @item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
3965 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}}
3966 @end itemize
3967
3968
3969 @itemize @bullet
3970 @item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3971 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}}
3972 @end itemize
3973
3974
3975 @itemize @bullet
3976 @item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
3977 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}}
3978 @end itemize
3979
3980
3981 @itemize @bullet
3982 @item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3983 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}}
3984 @end itemize
3985
3986
3987 @itemize @bullet
3988 @item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3989 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}}
3990 @end itemize
3991
3992
3993 @itemize @bullet
3994 @item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3995 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}}
3996 @end itemize
3997
3998
3999 @itemize @bullet
4000 @item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
4001 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}}
4002 @end itemize
4003
4004
4005 @itemize @bullet
4006 @item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
4007 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}}
4008 @end itemize
4009
4010
4011 @itemize @bullet
4012 @item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
4013 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}}
4014 @end itemize
4015
4016
4017 @itemize @bullet
4018 @item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
4019 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}}
4020 @end itemize
4021
4022
4023 @itemize @bullet
4024 @item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
4025 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}}
4026 @end itemize
4027
4028
4029 @itemize @bullet
4030 @item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
4031 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}}
4032 @end itemize
4033
4034
4035 @itemize @bullet
4036 @item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
4037 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}}
4038 @end itemize
4039
4040
4041 @itemize @bullet
4042 @item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
4043 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}}
4044 @end itemize
4045
4046
4047 @itemize @bullet
4048 @item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
4049 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}}
4050 @end itemize
4051
4052
4053 @itemize @bullet
4054 @item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
4055 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}}
4056 @end itemize
4057
4058
4059 @itemize @bullet
4060 @item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
4061 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}}
4062 @end itemize
4063
4064
4065 @itemize @bullet
4066 @item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
4067 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}}
4068 @end itemize
4069
4070
4071 @itemize @bullet
4072 @item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
4073 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}}
4074 @end itemize
4075
4076
4077
4078
4079 @subsubsection Vector shift right and insert
4080
4081 @itemize @bullet
4082 @item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
4083 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
4084 @end itemize
4085
4086
4087 @itemize @bullet
4088 @item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
4089 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4090 @end itemize
4091
4092
4093 @itemize @bullet
4094 @item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
4095 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4096 @end itemize
4097
4098
4099 @itemize @bullet
4100 @item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
4101 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
4102 @end itemize
4103
4104
4105 @itemize @bullet
4106 @item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
4107 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4108 @end itemize
4109
4110
4111 @itemize @bullet
4112 @item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
4113 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4114 @end itemize
4115
4116
4117 @itemize @bullet
4118 @item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
4119 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4120 @end itemize
4121
4122
4123 @itemize @bullet
4124 @item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
4125 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4126 @end itemize
4127
4128
4129 @itemize @bullet
4130 @item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
4131 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4132 @end itemize
4133
4134
4135 @itemize @bullet
4136 @item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
4137 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4138 @end itemize
4139
4140
4141 @itemize @bullet
4142 @item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
4143 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4144 @end itemize
4145
4146
4147 @itemize @bullet
4148 @item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
4149 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4150 @end itemize
4151
4152
4153 @itemize @bullet
4154 @item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
4155 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4156 @end itemize
4157
4158
4159 @itemize @bullet
4160 @item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
4161 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4162 @end itemize
4163
4164
4165 @itemize @bullet
4166 @item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
4167 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4168 @end itemize
4169
4170
4171 @itemize @bullet
4172 @item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
4173 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4174 @end itemize
4175
4176
4177 @itemize @bullet
4178 @item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
4179 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4180 @end itemize
4181
4182
4183 @itemize @bullet
4184 @item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
4185 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4186 @end itemize
4187
4188
4189 @itemize @bullet
4190 @item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
4191 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4192 @end itemize
4193
4194
4195 @itemize @bullet
4196 @item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
4197 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4198 @end itemize
4199
4200
4201
4202
4203 @subsubsection Vector shift left and insert
4204
4205 @itemize @bullet
4206 @item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
4207 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4208 @end itemize
4209
4210
4211 @itemize @bullet
4212 @item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
4213 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4214 @end itemize
4215
4216
4217 @itemize @bullet
4218 @item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
4219 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4220 @end itemize
4221
4222
4223 @itemize @bullet
4224 @item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
4225 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4226 @end itemize
4227
4228
4229 @itemize @bullet
4230 @item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
4231 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4232 @end itemize
4233
4234
4235 @itemize @bullet
4236 @item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
4237 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4238 @end itemize
4239
4240
4241 @itemize @bullet
4242 @item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
4243 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4244 @end itemize
4245
4246
4247 @itemize @bullet
4248 @item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
4249 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4250 @end itemize
4251
4252
4253 @itemize @bullet
4254 @item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
4255 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4256 @end itemize
4257
4258
4259 @itemize @bullet
4260 @item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
4261 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4262 @end itemize
4263
4264
4265 @itemize @bullet
4266 @item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
4267 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4268 @end itemize
4269
4270
4271 @itemize @bullet
4272 @item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
4273 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4274 @end itemize
4275
4276
4277 @itemize @bullet
4278 @item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
4279 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4280 @end itemize
4281
4282
4283 @itemize @bullet
4284 @item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
4285 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4286 @end itemize
4287
4288
4289 @itemize @bullet
4290 @item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
4291 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4292 @end itemize
4293
4294
4295 @itemize @bullet
4296 @item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
4297 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4298 @end itemize
4299
4300
4301 @itemize @bullet
4302 @item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
4303 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4304 @end itemize
4305
4306
4307 @itemize @bullet
4308 @item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
4309 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4310 @end itemize
4311
4312
4313 @itemize @bullet
4314 @item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
4315 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4316 @end itemize
4317
4318
4319 @itemize @bullet
4320 @item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
4321 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4322 @end itemize
4323
4324
4325
4326
4327 @subsubsection Absolute value
4328
4329 @itemize @bullet
4330 @item float32x2_t vabs_f32 (float32x2_t)
4331 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}}
4332 @end itemize
4333
4334
4335 @itemize @bullet
4336 @item int32x2_t vabs_s32 (int32x2_t)
4337 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}}
4338 @end itemize
4339
4340
4341 @itemize @bullet
4342 @item int16x4_t vabs_s16 (int16x4_t)
4343 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}}
4344 @end itemize
4345
4346
4347 @itemize @bullet
4348 @item int8x8_t vabs_s8 (int8x8_t)
4349 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}}
4350 @end itemize
4351
4352
4353 @itemize @bullet
4354 @item float32x4_t vabsq_f32 (float32x4_t)
4355 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}}
4356 @end itemize
4357
4358
4359 @itemize @bullet
4360 @item int32x4_t vabsq_s32 (int32x4_t)
4361 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}}
4362 @end itemize
4363
4364
4365 @itemize @bullet
4366 @item int16x8_t vabsq_s16 (int16x8_t)
4367 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}}
4368 @end itemize
4369
4370
4371 @itemize @bullet
4372 @item int8x16_t vabsq_s8 (int8x16_t)
4373 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}}
4374 @end itemize
4375
4376
4377 @itemize @bullet
4378 @item int32x2_t vqabs_s32 (int32x2_t)
4379 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}}
4380 @end itemize
4381
4382
4383 @itemize @bullet
4384 @item int16x4_t vqabs_s16 (int16x4_t)
4385 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}}
4386 @end itemize
4387
4388
4389 @itemize @bullet
4390 @item int8x8_t vqabs_s8 (int8x8_t)
4391 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}}
4392 @end itemize
4393
4394
4395 @itemize @bullet
4396 @item int32x4_t vqabsq_s32 (int32x4_t)
4397 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}}
4398 @end itemize
4399
4400
4401 @itemize @bullet
4402 @item int16x8_t vqabsq_s16 (int16x8_t)
4403 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}}
4404 @end itemize
4405
4406
4407 @itemize @bullet
4408 @item int8x16_t vqabsq_s8 (int8x16_t)
4409 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}}
4410 @end itemize
4411
4412
4413
4414
4415 @subsubsection Negation
4416
4417 @itemize @bullet
4418 @item float32x2_t vneg_f32 (float32x2_t)
4419 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}}
4420 @end itemize
4421
4422
4423 @itemize @bullet
4424 @item int32x2_t vneg_s32 (int32x2_t)
4425 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}}
4426 @end itemize
4427
4428
4429 @itemize @bullet
4430 @item int16x4_t vneg_s16 (int16x4_t)
4431 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}}
4432 @end itemize
4433
4434
4435 @itemize @bullet
4436 @item int8x8_t vneg_s8 (int8x8_t)
4437 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}}
4438 @end itemize
4439
4440
4441 @itemize @bullet
4442 @item float32x4_t vnegq_f32 (float32x4_t)
4443 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}}
4444 @end itemize
4445
4446
4447 @itemize @bullet
4448 @item int32x4_t vnegq_s32 (int32x4_t)
4449 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}}
4450 @end itemize
4451
4452
4453 @itemize @bullet
4454 @item int16x8_t vnegq_s16 (int16x8_t)
4455 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}}
4456 @end itemize
4457
4458
4459 @itemize @bullet
4460 @item int8x16_t vnegq_s8 (int8x16_t)
4461 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}}
4462 @end itemize
4463
4464
4465 @itemize @bullet
4466 @item int32x2_t vqneg_s32 (int32x2_t)
4467 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
4468 @end itemize
4469
4470
4471 @itemize @bullet
4472 @item int16x4_t vqneg_s16 (int16x4_t)
4473 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
4474 @end itemize
4475
4476
4477 @itemize @bullet
4478 @item int8x8_t vqneg_s8 (int8x8_t)
4479 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
4480 @end itemize
4481
4482
4483 @itemize @bullet
4484 @item int32x4_t vqnegq_s32 (int32x4_t)
4485 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
4486 @end itemize
4487
4488
4489 @itemize @bullet
4490 @item int16x8_t vqnegq_s16 (int16x8_t)
4491 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
4492 @end itemize
4493
4494
4495 @itemize @bullet
4496 @item int8x16_t vqnegq_s8 (int8x16_t)
4497 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
4498 @end itemize
4499
4500
4501
4502
4503 @subsubsection Bitwise not
4504
4505 @itemize @bullet
4506 @item uint32x2_t vmvn_u32 (uint32x2_t)
4507 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4508 @end itemize
4509
4510
4511 @itemize @bullet
4512 @item uint16x4_t vmvn_u16 (uint16x4_t)
4513 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4514 @end itemize
4515
4516
4517 @itemize @bullet
4518 @item uint8x8_t vmvn_u8 (uint8x8_t)
4519 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4520 @end itemize
4521
4522
4523 @itemize @bullet
4524 @item int32x2_t vmvn_s32 (int32x2_t)
4525 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4526 @end itemize
4527
4528
4529 @itemize @bullet
4530 @item int16x4_t vmvn_s16 (int16x4_t)
4531 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4532 @end itemize
4533
4534
4535 @itemize @bullet
4536 @item int8x8_t vmvn_s8 (int8x8_t)
4537 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4538 @end itemize
4539
4540
4541 @itemize @bullet
4542 @item poly8x8_t vmvn_p8 (poly8x8_t)
4543 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4544 @end itemize
4545
4546
4547 @itemize @bullet
4548 @item uint32x4_t vmvnq_u32 (uint32x4_t)
4549 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4550 @end itemize
4551
4552
4553 @itemize @bullet
4554 @item uint16x8_t vmvnq_u16 (uint16x8_t)
4555 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4556 @end itemize
4557
4558
4559 @itemize @bullet
4560 @item uint8x16_t vmvnq_u8 (uint8x16_t)
4561 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4562 @end itemize
4563
4564
4565 @itemize @bullet
4566 @item int32x4_t vmvnq_s32 (int32x4_t)
4567 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4568 @end itemize
4569
4570
4571 @itemize @bullet
4572 @item int16x8_t vmvnq_s16 (int16x8_t)
4573 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4574 @end itemize
4575
4576
4577 @itemize @bullet
4578 @item int8x16_t vmvnq_s8 (int8x16_t)
4579 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4580 @end itemize
4581
4582
4583 @itemize @bullet
4584 @item poly8x16_t vmvnq_p8 (poly8x16_t)
4585 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4586 @end itemize
4587
4588
4589
4590
4591 @subsubsection Count leading sign bits
4592
4593 @itemize @bullet
4594 @item int32x2_t vcls_s32 (int32x2_t)
4595 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}}
4596 @end itemize
4597
4598
4599 @itemize @bullet
4600 @item int16x4_t vcls_s16 (int16x4_t)
4601 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}}
4602 @end itemize
4603
4604
4605 @itemize @bullet
4606 @item int8x8_t vcls_s8 (int8x8_t)
4607 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}}
4608 @end itemize
4609
4610
4611 @itemize @bullet
4612 @item int32x4_t vclsq_s32 (int32x4_t)
4613 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}}
4614 @end itemize
4615
4616
4617 @itemize @bullet
4618 @item int16x8_t vclsq_s16 (int16x8_t)
4619 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}}
4620 @end itemize
4621
4622
4623 @itemize @bullet
4624 @item int8x16_t vclsq_s8 (int8x16_t)
4625 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}}
4626 @end itemize
4627
4628
4629
4630
4631 @subsubsection Count leading zeros
4632
4633 @itemize @bullet
4634 @item uint32x2_t vclz_u32 (uint32x2_t)
4635 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4636 @end itemize
4637
4638
4639 @itemize @bullet
4640 @item uint16x4_t vclz_u16 (uint16x4_t)
4641 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4642 @end itemize
4643
4644
4645 @itemize @bullet
4646 @item uint8x8_t vclz_u8 (uint8x8_t)
4647 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4648 @end itemize
4649
4650
4651 @itemize @bullet
4652 @item int32x2_t vclz_s32 (int32x2_t)
4653 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4654 @end itemize
4655
4656
4657 @itemize @bullet
4658 @item int16x4_t vclz_s16 (int16x4_t)
4659 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4660 @end itemize
4661
4662
4663 @itemize @bullet
4664 @item int8x8_t vclz_s8 (int8x8_t)
4665 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4666 @end itemize
4667
4668
4669 @itemize @bullet
4670 @item uint32x4_t vclzq_u32 (uint32x4_t)
4671 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4672 @end itemize
4673
4674
4675 @itemize @bullet
4676 @item uint16x8_t vclzq_u16 (uint16x8_t)
4677 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4678 @end itemize
4679
4680
4681 @itemize @bullet
4682 @item uint8x16_t vclzq_u8 (uint8x16_t)
4683 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4684 @end itemize
4685
4686
4687 @itemize @bullet
4688 @item int32x4_t vclzq_s32 (int32x4_t)
4689 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4690 @end itemize
4691
4692
4693 @itemize @bullet
4694 @item int16x8_t vclzq_s16 (int16x8_t)
4695 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4696 @end itemize
4697
4698
4699 @itemize @bullet
4700 @item int8x16_t vclzq_s8 (int8x16_t)
4701 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4702 @end itemize
4703
4704
4705
4706
4707 @subsubsection Count number of set bits
4708
4709 @itemize @bullet
4710 @item uint8x8_t vcnt_u8 (uint8x8_t)
4711 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4712 @end itemize
4713
4714
4715 @itemize @bullet
4716 @item int8x8_t vcnt_s8 (int8x8_t)
4717 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4718 @end itemize
4719
4720
4721 @itemize @bullet
4722 @item poly8x8_t vcnt_p8 (poly8x8_t)
4723 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4724 @end itemize
4725
4726
4727 @itemize @bullet
4728 @item uint8x16_t vcntq_u8 (uint8x16_t)
4729 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4730 @end itemize
4731
4732
4733 @itemize @bullet
4734 @item int8x16_t vcntq_s8 (int8x16_t)
4735 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4736 @end itemize
4737
4738
4739 @itemize @bullet
4740 @item poly8x16_t vcntq_p8 (poly8x16_t)
4741 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4742 @end itemize
4743
4744
4745
4746
4747 @subsubsection Reciprocal estimate
4748
4749 @itemize @bullet
4750 @item float32x2_t vrecpe_f32 (float32x2_t)
4751 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}}
4752 @end itemize
4753
4754
4755 @itemize @bullet
4756 @item uint32x2_t vrecpe_u32 (uint32x2_t)
4757 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}}
4758 @end itemize
4759
4760
4761 @itemize @bullet
4762 @item float32x4_t vrecpeq_f32 (float32x4_t)
4763 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}}
4764 @end itemize
4765
4766
4767 @itemize @bullet
4768 @item uint32x4_t vrecpeq_u32 (uint32x4_t)
4769 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}}
4770 @end itemize
4771
4772
4773
4774
4775 @subsubsection Reciprocal square-root estimate
4776
4777 @itemize @bullet
4778 @item float32x2_t vrsqrte_f32 (float32x2_t)
4779 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}}
4780 @end itemize
4781
4782
4783 @itemize @bullet
4784 @item uint32x2_t vrsqrte_u32 (uint32x2_t)
4785 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}}
4786 @end itemize
4787
4788
4789 @itemize @bullet
4790 @item float32x4_t vrsqrteq_f32 (float32x4_t)
4791 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}}
4792 @end itemize
4793
4794
4795 @itemize @bullet
4796 @item uint32x4_t vrsqrteq_u32 (uint32x4_t)
4797 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}}
4798 @end itemize
4799
4800
4801
4802
4803 @subsubsection Get lanes from a vector
4804
4805 @itemize @bullet
4806 @item uint32_t vget_lane_u32 (uint32x2_t, const int)
4807 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4808 @end itemize
4809
4810
4811 @itemize @bullet
4812 @item uint16_t vget_lane_u16 (uint16x4_t, const int)
4813 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4814 @end itemize
4815
4816
4817 @itemize @bullet
4818 @item uint8_t vget_lane_u8 (uint8x8_t, const int)
4819 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4820 @end itemize
4821
4822
4823 @itemize @bullet
4824 @item int32_t vget_lane_s32 (int32x2_t, const int)
4825 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4826 @end itemize
4827
4828
4829 @itemize @bullet
4830 @item int16_t vget_lane_s16 (int16x4_t, const int)
4831 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4832 @end itemize
4833
4834
4835 @itemize @bullet
4836 @item int8_t vget_lane_s8 (int8x8_t, const int)
4837 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4838 @end itemize
4839
4840
4841 @itemize @bullet
4842 @item float32_t vget_lane_f32 (float32x2_t, const int)
4843 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4844 @end itemize
4845
4846
4847 @itemize @bullet
4848 @item poly16_t vget_lane_p16 (poly16x4_t, const int)
4849 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4850 @end itemize
4851
4852
4853 @itemize @bullet
4854 @item poly8_t vget_lane_p8 (poly8x8_t, const int)
4855 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4856 @end itemize
4857
4858
4859 @itemize @bullet
4860 @item uint64_t vget_lane_u64 (uint64x1_t, const int)
4861 @end itemize
4862
4863
4864 @itemize @bullet
4865 @item int64_t vget_lane_s64 (int64x1_t, const int)
4866 @end itemize
4867
4868
4869 @itemize @bullet
4870 @item uint32_t vgetq_lane_u32 (uint32x4_t, const int)
4871 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4872 @end itemize
4873
4874
4875 @itemize @bullet
4876 @item uint16_t vgetq_lane_u16 (uint16x8_t, const int)
4877 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4878 @end itemize
4879
4880
4881 @itemize @bullet
4882 @item uint8_t vgetq_lane_u8 (uint8x16_t, const int)
4883 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4884 @end itemize
4885
4886
4887 @itemize @bullet
4888 @item int32_t vgetq_lane_s32 (int32x4_t, const int)
4889 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4890 @end itemize
4891
4892
4893 @itemize @bullet
4894 @item int16_t vgetq_lane_s16 (int16x8_t, const int)
4895 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4896 @end itemize
4897
4898
4899 @itemize @bullet
4900 @item int8_t vgetq_lane_s8 (int8x16_t, const int)
4901 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4902 @end itemize
4903
4904
4905 @itemize @bullet
4906 @item float32_t vgetq_lane_f32 (float32x4_t, const int)
4907 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4908 @end itemize
4909
4910
4911 @itemize @bullet
4912 @item poly16_t vgetq_lane_p16 (poly16x8_t, const int)
4913 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4914 @end itemize
4915
4916
4917 @itemize @bullet
4918 @item poly8_t vgetq_lane_p8 (poly8x16_t, const int)
4919 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4920 @end itemize
4921
4922
4923 @itemize @bullet
4924 @item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
4925 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}}
4926 @end itemize
4927
4928
4929 @itemize @bullet
4930 @item int64_t vgetq_lane_s64 (int64x2_t, const int)
4931 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}}
4932 @end itemize
4933
4934
4935
4936
4937 @subsubsection Set lanes in a vector
4938
4939 @itemize @bullet
4940 @item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
4941 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4942 @end itemize
4943
4944
4945 @itemize @bullet
4946 @item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
4947 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4948 @end itemize
4949
4950
4951 @itemize @bullet
4952 @item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
4953 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4954 @end itemize
4955
4956
4957 @itemize @bullet
4958 @item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
4959 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4960 @end itemize
4961
4962
4963 @itemize @bullet
4964 @item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
4965 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4966 @end itemize
4967
4968
4969 @itemize @bullet
4970 @item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
4971 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4972 @end itemize
4973
4974
4975 @itemize @bullet
4976 @item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
4977 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4978 @end itemize
4979
4980
4981 @itemize @bullet
4982 @item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
4983 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4984 @end itemize
4985
4986
4987 @itemize @bullet
4988 @item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
4989 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4990 @end itemize
4991
4992
4993 @itemize @bullet
4994 @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
4995 @end itemize
4996
4997
4998 @itemize @bullet
4999 @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
5000 @end itemize
5001
5002
5003 @itemize @bullet
5004 @item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
5005 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5006 @end itemize
5007
5008
5009 @itemize @bullet
5010 @item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
5011 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5012 @end itemize
5013
5014
5015 @itemize @bullet
5016 @item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
5017 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5018 @end itemize
5019
5020
5021 @itemize @bullet
5022 @item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
5023 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5024 @end itemize
5025
5026
5027 @itemize @bullet
5028 @item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
5029 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5030 @end itemize
5031
5032
5033 @itemize @bullet
5034 @item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
5035 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5036 @end itemize
5037
5038
5039 @itemize @bullet
5040 @item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
5041 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5042 @end itemize
5043
5044
5045 @itemize @bullet
5046 @item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
5047 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5048 @end itemize
5049
5050
5051 @itemize @bullet
5052 @item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
5053 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5054 @end itemize
5055
5056
5057 @itemize @bullet
5058 @item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
5059 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5060 @end itemize
5061
5062
5063 @itemize @bullet
5064 @item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
5065 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5066 @end itemize
5067
5068
5069
5070
5071 @subsubsection Create vector from literal bit pattern
5072
5073 @itemize @bullet
5074 @item uint32x2_t vcreate_u32 (uint64_t)
5075 @end itemize
5076
5077
5078 @itemize @bullet
5079 @item uint16x4_t vcreate_u16 (uint64_t)
5080 @end itemize
5081
5082
5083 @itemize @bullet
5084 @item uint8x8_t vcreate_u8 (uint64_t)
5085 @end itemize
5086
5087
5088 @itemize @bullet
5089 @item int32x2_t vcreate_s32 (uint64_t)
5090 @end itemize
5091
5092
5093 @itemize @bullet
5094 @item int16x4_t vcreate_s16 (uint64_t)
5095 @end itemize
5096
5097
5098 @itemize @bullet
5099 @item int8x8_t vcreate_s8 (uint64_t)
5100 @end itemize
5101
5102
5103 @itemize @bullet
5104 @item uint64x1_t vcreate_u64 (uint64_t)
5105 @end itemize
5106
5107
5108 @itemize @bullet
5109 @item int64x1_t vcreate_s64 (uint64_t)
5110 @end itemize
5111
5112
5113 @itemize @bullet
5114 @item float32x2_t vcreate_f32 (uint64_t)
5115 @end itemize
5116
5117
5118 @itemize @bullet
5119 @item poly16x4_t vcreate_p16 (uint64_t)
5120 @end itemize
5121
5122
5123 @itemize @bullet
5124 @item poly8x8_t vcreate_p8 (uint64_t)
5125 @end itemize
5126
5127
5128
5129
5130 @subsubsection Set all lanes to the same value
5131
5132 @itemize @bullet
5133 @item uint32x2_t vdup_n_u32 (uint32_t)
5134 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5135 @end itemize
5136
5137
5138 @itemize @bullet
5139 @item uint16x4_t vdup_n_u16 (uint16_t)
5140 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5141 @end itemize
5142
5143
5144 @itemize @bullet
5145 @item uint8x8_t vdup_n_u8 (uint8_t)
5146 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5147 @end itemize
5148
5149
5150 @itemize @bullet
5151 @item int32x2_t vdup_n_s32 (int32_t)
5152 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5153 @end itemize
5154
5155
5156 @itemize @bullet
5157 @item int16x4_t vdup_n_s16 (int16_t)
5158 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5159 @end itemize
5160
5161
5162 @itemize @bullet
5163 @item int8x8_t vdup_n_s8 (int8_t)
5164 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5165 @end itemize
5166
5167
5168 @itemize @bullet
5169 @item float32x2_t vdup_n_f32 (float32_t)
5170 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5171 @end itemize
5172
5173
5174 @itemize @bullet
5175 @item poly16x4_t vdup_n_p16 (poly16_t)
5176 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5177 @end itemize
5178
5179
5180 @itemize @bullet
5181 @item poly8x8_t vdup_n_p8 (poly8_t)
5182 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5183 @end itemize
5184
5185
5186 @itemize @bullet
5187 @item uint64x1_t vdup_n_u64 (uint64_t)
5188 @end itemize
5189
5190
5191 @itemize @bullet
5192 @item int64x1_t vdup_n_s64 (int64_t)
5193 @end itemize
5194
5195
5196 @itemize @bullet
5197 @item uint32x4_t vdupq_n_u32 (uint32_t)
5198 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5199 @end itemize
5200
5201
5202 @itemize @bullet
5203 @item uint16x8_t vdupq_n_u16 (uint16_t)
5204 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5205 @end itemize
5206
5207
5208 @itemize @bullet
5209 @item uint8x16_t vdupq_n_u8 (uint8_t)
5210 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5211 @end itemize
5212
5213
5214 @itemize @bullet
5215 @item int32x4_t vdupq_n_s32 (int32_t)
5216 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5217 @end itemize
5218
5219
5220 @itemize @bullet
5221 @item int16x8_t vdupq_n_s16 (int16_t)
5222 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5223 @end itemize
5224
5225
5226 @itemize @bullet
5227 @item int8x16_t vdupq_n_s8 (int8_t)
5228 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5229 @end itemize
5230
5231
5232 @itemize @bullet
5233 @item float32x4_t vdupq_n_f32 (float32_t)
5234 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5235 @end itemize
5236
5237
5238 @itemize @bullet
5239 @item poly16x8_t vdupq_n_p16 (poly16_t)
5240 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5241 @end itemize
5242
5243
5244 @itemize @bullet
5245 @item poly8x16_t vdupq_n_p8 (poly8_t)
5246 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5247 @end itemize
5248
5249
5250 @itemize @bullet
5251 @item uint64x2_t vdupq_n_u64 (uint64_t)
5252 @end itemize
5253
5254
5255 @itemize @bullet
5256 @item int64x2_t vdupq_n_s64 (int64_t)
5257 @end itemize
5258
5259
5260 @itemize @bullet
5261 @item uint32x2_t vmov_n_u32 (uint32_t)
5262 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5263 @end itemize
5264
5265
5266 @itemize @bullet
5267 @item uint16x4_t vmov_n_u16 (uint16_t)
5268 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5269 @end itemize
5270
5271
5272 @itemize @bullet
5273 @item uint8x8_t vmov_n_u8 (uint8_t)
5274 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5275 @end itemize
5276
5277
5278 @itemize @bullet
5279 @item int32x2_t vmov_n_s32 (int32_t)
5280 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5281 @end itemize
5282
5283
5284 @itemize @bullet
5285 @item int16x4_t vmov_n_s16 (int16_t)
5286 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5287 @end itemize
5288
5289
5290 @itemize @bullet
5291 @item int8x8_t vmov_n_s8 (int8_t)
5292 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5293 @end itemize
5294
5295
5296 @itemize @bullet
5297 @item float32x2_t vmov_n_f32 (float32_t)
5298 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5299 @end itemize
5300
5301
5302 @itemize @bullet
5303 @item poly16x4_t vmov_n_p16 (poly16_t)
5304 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5305 @end itemize
5306
5307
5308 @itemize @bullet
5309 @item poly8x8_t vmov_n_p8 (poly8_t)
5310 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5311 @end itemize
5312
5313
5314 @itemize @bullet
5315 @item uint64x1_t vmov_n_u64 (uint64_t)
5316 @end itemize
5317
5318
5319 @itemize @bullet
5320 @item int64x1_t vmov_n_s64 (int64_t)
5321 @end itemize
5322
5323
5324 @itemize @bullet
5325 @item uint32x4_t vmovq_n_u32 (uint32_t)
5326 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5327 @end itemize
5328
5329
5330 @itemize @bullet
5331 @item uint16x8_t vmovq_n_u16 (uint16_t)
5332 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5333 @end itemize
5334
5335
5336 @itemize @bullet
5337 @item uint8x16_t vmovq_n_u8 (uint8_t)
5338 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5339 @end itemize
5340
5341
5342 @itemize @bullet
5343 @item int32x4_t vmovq_n_s32 (int32_t)
5344 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5345 @end itemize
5346
5347
5348 @itemize @bullet
5349 @item int16x8_t vmovq_n_s16 (int16_t)
5350 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5351 @end itemize
5352
5353
5354 @itemize @bullet
5355 @item int8x16_t vmovq_n_s8 (int8_t)
5356 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5357 @end itemize
5358
5359
5360 @itemize @bullet
5361 @item float32x4_t vmovq_n_f32 (float32_t)
5362 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5363 @end itemize
5364
5365
5366 @itemize @bullet
5367 @item poly16x8_t vmovq_n_p16 (poly16_t)
5368 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5369 @end itemize
5370
5371
5372 @itemize @bullet
5373 @item poly8x16_t vmovq_n_p8 (poly8_t)
5374 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5375 @end itemize
5376
5377
5378 @itemize @bullet
5379 @item uint64x2_t vmovq_n_u64 (uint64_t)
5380 @end itemize
5381
5382
5383 @itemize @bullet
5384 @item int64x2_t vmovq_n_s64 (int64_t)
5385 @end itemize
5386
5387
5388 @itemize @bullet
5389 @item uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
5390 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5391 @end itemize
5392
5393
5394 @itemize @bullet
5395 @item uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
5396 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5397 @end itemize
5398
5399
5400 @itemize @bullet
5401 @item uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
5402 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5403 @end itemize
5404
5405
5406 @itemize @bullet
5407 @item int32x2_t vdup_lane_s32 (int32x2_t, const int)
5408 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5409 @end itemize
5410
5411
5412 @itemize @bullet
5413 @item int16x4_t vdup_lane_s16 (int16x4_t, const int)
5414 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5415 @end itemize
5416
5417
5418 @itemize @bullet
5419 @item int8x8_t vdup_lane_s8 (int8x8_t, const int)
5420 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5421 @end itemize
5422
5423
5424 @itemize @bullet
5425 @item float32x2_t vdup_lane_f32 (float32x2_t, const int)
5426 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5427 @end itemize
5428
5429
5430 @itemize @bullet
5431 @item poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
5432 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5433 @end itemize
5434
5435
5436 @itemize @bullet
5437 @item poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
5438 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5439 @end itemize
5440
5441
5442 @itemize @bullet
5443 @item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
5444 @end itemize
5445
5446
5447 @itemize @bullet
5448 @item int64x1_t vdup_lane_s64 (int64x1_t, const int)
5449 @end itemize
5450
5451
5452 @itemize @bullet
5453 @item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
5454 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5455 @end itemize
5456
5457
5458 @itemize @bullet
5459 @item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
5460 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5461 @end itemize
5462
5463
5464 @itemize @bullet
5465 @item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
5466 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5467 @end itemize
5468
5469
5470 @itemize @bullet
5471 @item int32x4_t vdupq_lane_s32 (int32x2_t, const int)
5472 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5473 @end itemize
5474
5475
5476 @itemize @bullet
5477 @item int16x8_t vdupq_lane_s16 (int16x4_t, const int)
5478 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5479 @end itemize
5480
5481
5482 @itemize @bullet
5483 @item int8x16_t vdupq_lane_s8 (int8x8_t, const int)
5484 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5485 @end itemize
5486
5487
5488 @itemize @bullet
5489 @item float32x4_t vdupq_lane_f32 (float32x2_t, const int)
5490 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5491 @end itemize
5492
5493
5494 @itemize @bullet
5495 @item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
5496 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5497 @end itemize
5498
5499
5500 @itemize @bullet
5501 @item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
5502 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5503 @end itemize
5504
5505
5506 @itemize @bullet
5507 @item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
5508 @end itemize
5509
5510
5511 @itemize @bullet
5512 @item int64x2_t vdupq_lane_s64 (int64x1_t, const int)
5513 @end itemize
5514
5515
5516
5517
5518 @subsubsection Combining vectors
5519
5520 @itemize @bullet
5521 @item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
5522 @end itemize
5523
5524
5525 @itemize @bullet
5526 @item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
5527 @end itemize
5528
5529
5530 @itemize @bullet
5531 @item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
5532 @end itemize
5533
5534
5535 @itemize @bullet
5536 @item int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
5537 @end itemize
5538
5539
5540 @itemize @bullet
5541 @item int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
5542 @end itemize
5543
5544
5545 @itemize @bullet
5546 @item int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
5547 @end itemize
5548
5549
5550 @itemize @bullet
5551 @item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
5552 @end itemize
5553
5554
5555 @itemize @bullet
5556 @item int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
5557 @end itemize
5558
5559
5560 @itemize @bullet
5561 @item float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
5562 @end itemize
5563
5564
5565 @itemize @bullet
5566 @item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
5567 @end itemize
5568
5569
5570 @itemize @bullet
5571 @item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
5572 @end itemize
5573
5574
5575
5576
5577 @subsubsection Splitting vectors
5578
5579 @itemize @bullet
5580 @item uint32x2_t vget_high_u32 (uint32x4_t)
5581 @end itemize
5582
5583
5584 @itemize @bullet
5585 @item uint16x4_t vget_high_u16 (uint16x8_t)
5586 @end itemize
5587
5588
5589 @itemize @bullet
5590 @item uint8x8_t vget_high_u8 (uint8x16_t)
5591 @end itemize
5592
5593
5594 @itemize @bullet
5595 @item int32x2_t vget_high_s32 (int32x4_t)
5596 @end itemize
5597
5598
5599 @itemize @bullet
5600 @item int16x4_t vget_high_s16 (int16x8_t)
5601 @end itemize
5602
5603
5604 @itemize @bullet
5605 @item int8x8_t vget_high_s8 (int8x16_t)
5606 @end itemize
5607
5608
5609 @itemize @bullet
5610 @item uint64x1_t vget_high_u64 (uint64x2_t)
5611 @end itemize
5612
5613
5614 @itemize @bullet
5615 @item int64x1_t vget_high_s64 (int64x2_t)
5616 @end itemize
5617
5618
5619 @itemize @bullet
5620 @item float32x2_t vget_high_f32 (float32x4_t)
5621 @end itemize
5622
5623
5624 @itemize @bullet
5625 @item poly16x4_t vget_high_p16 (poly16x8_t)
5626 @end itemize
5627
5628
5629 @itemize @bullet
5630 @item poly8x8_t vget_high_p8 (poly8x16_t)
5631 @end itemize
5632
5633
5634 @itemize @bullet
5635 @item uint32x2_t vget_low_u32 (uint32x4_t)
5636 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5637 @end itemize
5638
5639
5640 @itemize @bullet
5641 @item uint16x4_t vget_low_u16 (uint16x8_t)
5642 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5643 @end itemize
5644
5645
5646 @itemize @bullet
5647 @item uint8x8_t vget_low_u8 (uint8x16_t)
5648 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5649 @end itemize
5650
5651
5652 @itemize @bullet
5653 @item int32x2_t vget_low_s32 (int32x4_t)
5654 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5655 @end itemize
5656
5657
5658 @itemize @bullet
5659 @item int16x4_t vget_low_s16 (int16x8_t)
5660 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5661 @end itemize
5662
5663
5664 @itemize @bullet
5665 @item int8x8_t vget_low_s8 (int8x16_t)
5666 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5667 @end itemize
5668
5669
5670 @itemize @bullet
5671 @item float32x2_t vget_low_f32 (float32x4_t)
5672 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5673 @end itemize
5674
5675
5676 @itemize @bullet
5677 @item poly16x4_t vget_low_p16 (poly16x8_t)
5678 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5679 @end itemize
5680
5681
5682 @itemize @bullet
5683 @item poly8x8_t vget_low_p8 (poly8x16_t)
5684 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5685 @end itemize
5686
5687
5688 @itemize @bullet
5689 @item uint64x1_t vget_low_u64 (uint64x2_t)
5690 @end itemize
5691
5692
5693 @itemize @bullet
5694 @item int64x1_t vget_low_s64 (int64x2_t)
5695 @end itemize
5696
5697
5698
5699
5700 @subsubsection Conversions
5701
5702 @itemize @bullet
5703 @item float32x2_t vcvt_f32_u32 (uint32x2_t)
5704 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}}
5705 @end itemize
5706
5707
5708 @itemize @bullet
5709 @item float32x2_t vcvt_f32_s32 (int32x2_t)
5710 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}}
5711 @end itemize
5712
5713
5714 @itemize @bullet
5715 @item uint32x2_t vcvt_u32_f32 (float32x2_t)
5716 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}}
5717 @end itemize
5718
5719
5720 @itemize @bullet
5721 @item int32x2_t vcvt_s32_f32 (float32x2_t)
5722 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}}
5723 @end itemize
5724
5725
5726 @itemize @bullet
5727 @item float32x4_t vcvtq_f32_u32 (uint32x4_t)
5728 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}}
5729 @end itemize
5730
5731
5732 @itemize @bullet
5733 @item float32x4_t vcvtq_f32_s32 (int32x4_t)
5734 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}}
5735 @end itemize
5736
5737
5738 @itemize @bullet
5739 @item uint32x4_t vcvtq_u32_f32 (float32x4_t)
5740 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}}
5741 @end itemize
5742
5743
5744 @itemize @bullet
5745 @item int32x4_t vcvtq_s32_f32 (float32x4_t)
5746 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}}
5747 @end itemize
5748
5749
5750 @itemize @bullet
5751 @item float16x4_t vcvt_f16_f32 (float32x4_t)
5752 @*@emph{Form of expected instruction(s):} @code{vcvt.f16.f32 @var{d0}, @var{q0}}
5753 @end itemize
5754
5755
5756 @itemize @bullet
5757 @item float32x4_t vcvt_f32_f16 (float16x4_t)
5758 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.f16 @var{q0}, @var{d0}}
5759 @end itemize
5760
5761
5762 @itemize @bullet
5763 @item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
5764 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
5765 @end itemize
5766
5767
5768 @itemize @bullet
5769 @item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
5770 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}}
5771 @end itemize
5772
5773
5774 @itemize @bullet
5775 @item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
5776 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}}
5777 @end itemize
5778
5779
5780 @itemize @bullet
5781 @item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
5782 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}}
5783 @end itemize
5784
5785
5786 @itemize @bullet
5787 @item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
5788 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}}
5789 @end itemize
5790
5791
5792 @itemize @bullet
5793 @item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
5794 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}}
5795 @end itemize
5796
5797
5798 @itemize @bullet
5799 @item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
5800 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}}
5801 @end itemize
5802
5803
5804 @itemize @bullet
5805 @item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
5806 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}}
5807 @end itemize
5808
5809
5810
5811
5812 @subsubsection Move, single_opcode narrowing
5813
5814 @itemize @bullet
5815 @item uint32x2_t vmovn_u64 (uint64x2_t)
5816 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5817 @end itemize
5818
5819
5820 @itemize @bullet
5821 @item uint16x4_t vmovn_u32 (uint32x4_t)
5822 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5823 @end itemize
5824
5825
5826 @itemize @bullet
5827 @item uint8x8_t vmovn_u16 (uint16x8_t)
5828 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5829 @end itemize
5830
5831
5832 @itemize @bullet
5833 @item int32x2_t vmovn_s64 (int64x2_t)
5834 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5835 @end itemize
5836
5837
5838 @itemize @bullet
5839 @item int16x4_t vmovn_s32 (int32x4_t)
5840 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5841 @end itemize
5842
5843
5844 @itemize @bullet
5845 @item int8x8_t vmovn_s16 (int16x8_t)
5846 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5847 @end itemize
5848
5849
5850 @itemize @bullet
5851 @item uint32x2_t vqmovn_u64 (uint64x2_t)
5852 @*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}}
5853 @end itemize
5854
5855
5856 @itemize @bullet
5857 @item uint16x4_t vqmovn_u32 (uint32x4_t)
5858 @*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}}
5859 @end itemize
5860
5861
5862 @itemize @bullet
5863 @item uint8x8_t vqmovn_u16 (uint16x8_t)
5864 @*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}}
5865 @end itemize
5866
5867
5868 @itemize @bullet
5869 @item int32x2_t vqmovn_s64 (int64x2_t)
5870 @*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}}
5871 @end itemize
5872
5873
5874 @itemize @bullet
5875 @item int16x4_t vqmovn_s32 (int32x4_t)
5876 @*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}}
5877 @end itemize
5878
5879
5880 @itemize @bullet
5881 @item int8x8_t vqmovn_s16 (int16x8_t)
5882 @*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}}
5883 @end itemize
5884
5885
5886 @itemize @bullet
5887 @item uint32x2_t vqmovun_s64 (int64x2_t)
5888 @*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}}
5889 @end itemize
5890
5891
5892 @itemize @bullet
5893 @item uint16x4_t vqmovun_s32 (int32x4_t)
5894 @*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}}
5895 @end itemize
5896
5897
5898 @itemize @bullet
5899 @item uint8x8_t vqmovun_s16 (int16x8_t)
5900 @*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}}
5901 @end itemize
5902
5903
5904
5905
5906 @subsubsection Move, single_opcode long
5907
5908 @itemize @bullet
5909 @item uint64x2_t vmovl_u32 (uint32x2_t)
5910 @*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}}
5911 @end itemize
5912
5913
5914 @itemize @bullet
5915 @item uint32x4_t vmovl_u16 (uint16x4_t)
5916 @*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}}
5917 @end itemize
5918
5919
5920 @itemize @bullet
5921 @item uint16x8_t vmovl_u8 (uint8x8_t)
5922 @*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}}
5923 @end itemize
5924
5925
5926 @itemize @bullet
5927 @item int64x2_t vmovl_s32 (int32x2_t)
5928 @*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}}
5929 @end itemize
5930
5931
5932 @itemize @bullet
5933 @item int32x4_t vmovl_s16 (int16x4_t)
5934 @*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}}
5935 @end itemize
5936
5937
5938 @itemize @bullet
5939 @item int16x8_t vmovl_s8 (int8x8_t)
5940 @*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}}
5941 @end itemize
5942
5943
5944
5945
5946 @subsubsection Table lookup
5947
5948 @itemize @bullet
5949 @item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
5950 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5951 @end itemize
5952
5953
5954 @itemize @bullet
5955 @item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
5956 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5957 @end itemize
5958
5959
5960 @itemize @bullet
5961 @item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
5962 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5963 @end itemize
5964
5965
5966 @itemize @bullet
5967 @item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
5968 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5969 @end itemize
5970
5971
5972 @itemize @bullet
5973 @item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
5974 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5975 @end itemize
5976
5977
5978 @itemize @bullet
5979 @item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
5980 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5981 @end itemize
5982
5983
5984 @itemize @bullet
5985 @item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
5986 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5987 @end itemize
5988
5989
5990 @itemize @bullet
5991 @item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
5992 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5993 @end itemize
5994
5995
5996 @itemize @bullet
5997 @item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
5998 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5999 @end itemize
6000
6001
6002 @itemize @bullet
6003 @item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
6004 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6005 @end itemize
6006
6007
6008 @itemize @bullet
6009 @item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
6010 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6011 @end itemize
6012
6013
6014 @itemize @bullet
6015 @item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
6016 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6017 @end itemize
6018
6019
6020
6021
6022 @subsubsection Extended table lookup
6023
6024 @itemize @bullet
6025 @item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
6026 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6027 @end itemize
6028
6029
6030 @itemize @bullet
6031 @item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
6032 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6033 @end itemize
6034
6035
6036 @itemize @bullet
6037 @item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
6038 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6039 @end itemize
6040
6041
6042 @itemize @bullet
6043 @item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
6044 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6045 @end itemize
6046
6047
6048 @itemize @bullet
6049 @item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
6050 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6051 @end itemize
6052
6053
6054 @itemize @bullet
6055 @item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
6056 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6057 @end itemize
6058
6059
6060 @itemize @bullet
6061 @item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
6062 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6063 @end itemize
6064
6065
6066 @itemize @bullet
6067 @item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
6068 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6069 @end itemize
6070
6071
6072 @itemize @bullet
6073 @item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
6074 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6075 @end itemize
6076
6077
6078 @itemize @bullet
6079 @item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
6080 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6081 @end itemize
6082
6083
6084 @itemize @bullet
6085 @item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
6086 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6087 @end itemize
6088
6089
6090 @itemize @bullet
6091 @item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
6092 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6093 @end itemize
6094
6095
6096
6097
6098 @subsubsection Multiply, lane
6099
6100 @itemize @bullet
6101 @item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
6102 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6103 @end itemize
6104
6105
6106 @itemize @bullet
6107 @item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
6108 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6109 @end itemize
6110
6111
6112 @itemize @bullet
6113 @item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
6114 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6115 @end itemize
6116
6117
6118 @itemize @bullet
6119 @item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
6120 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6121 @end itemize
6122
6123
6124 @itemize @bullet
6125 @item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
6126 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6127 @end itemize
6128
6129
6130 @itemize @bullet
6131 @item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
6132 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6133 @end itemize
6134
6135
6136 @itemize @bullet
6137 @item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
6138 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6139 @end itemize
6140
6141
6142 @itemize @bullet
6143 @item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
6144 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6145 @end itemize
6146
6147
6148 @itemize @bullet
6149 @item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
6150 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6151 @end itemize
6152
6153
6154 @itemize @bullet
6155 @item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
6156 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6157 @end itemize
6158
6159
6160
6161
6162 @subsubsection Long multiply, lane
6163
6164 @itemize @bullet
6165 @item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
6166 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6167 @end itemize
6168
6169
6170 @itemize @bullet
6171 @item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
6172 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6173 @end itemize
6174
6175
6176 @itemize @bullet
6177 @item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
6178 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6179 @end itemize
6180
6181
6182 @itemize @bullet
6183 @item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
6184 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6185 @end itemize
6186
6187
6188
6189
6190 @subsubsection Saturating doubling long multiply, lane
6191
6192 @itemize @bullet
6193 @item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
6194 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6195 @end itemize
6196
6197
6198 @itemize @bullet
6199 @item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
6200 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6201 @end itemize
6202
6203
6204
6205
6206 @subsubsection Saturating doubling multiply high, lane
6207
6208 @itemize @bullet
6209 @item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6210 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6211 @end itemize
6212
6213
6214 @itemize @bullet
6215 @item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6216 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6217 @end itemize
6218
6219
6220 @itemize @bullet
6221 @item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6222 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6223 @end itemize
6224
6225
6226 @itemize @bullet
6227 @item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6228 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6229 @end itemize
6230
6231
6232 @itemize @bullet
6233 @item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6234 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6235 @end itemize
6236
6237
6238 @itemize @bullet
6239 @item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6240 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6241 @end itemize
6242
6243
6244 @itemize @bullet
6245 @item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6246 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6247 @end itemize
6248
6249
6250 @itemize @bullet
6251 @item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6252 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6253 @end itemize
6254
6255
6256
6257
6258 @subsubsection Multiply-accumulate, lane
6259
6260 @itemize @bullet
6261 @item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6262 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6263 @end itemize
6264
6265
6266 @itemize @bullet
6267 @item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6268 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6269 @end itemize
6270
6271
6272 @itemize @bullet
6273 @item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6274 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6275 @end itemize
6276
6277
6278 @itemize @bullet
6279 @item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6280 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6281 @end itemize
6282
6283
6284 @itemize @bullet
6285 @item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6286 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6287 @end itemize
6288
6289
6290 @itemize @bullet
6291 @item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6292 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6293 @end itemize
6294
6295
6296 @itemize @bullet
6297 @item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6298 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6299 @end itemize
6300
6301
6302 @itemize @bullet
6303 @item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6304 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6305 @end itemize
6306
6307
6308 @itemize @bullet
6309 @item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6310 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6311 @end itemize
6312
6313
6314 @itemize @bullet
6315 @item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6316 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6317 @end itemize
6318
6319
6320 @itemize @bullet
6321 @item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6322 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6323 @end itemize
6324
6325
6326 @itemize @bullet
6327 @item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6328 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6329 @end itemize
6330
6331
6332 @itemize @bullet
6333 @item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6334 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6335 @end itemize
6336
6337
6338 @itemize @bullet
6339 @item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6340 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6341 @end itemize
6342
6343
6344 @itemize @bullet
6345 @item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6346 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6347 @end itemize
6348
6349
6350 @itemize @bullet
6351 @item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6352 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6353 @end itemize
6354
6355
6356
6357
6358 @subsubsection Multiply-subtract, lane
6359
6360 @itemize @bullet
6361 @item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6362 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6363 @end itemize
6364
6365
6366 @itemize @bullet
6367 @item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6368 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6369 @end itemize
6370
6371
6372 @itemize @bullet
6373 @item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6374 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6375 @end itemize
6376
6377
6378 @itemize @bullet
6379 @item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6380 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6381 @end itemize
6382
6383
6384 @itemize @bullet
6385 @item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6386 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6387 @end itemize
6388
6389
6390 @itemize @bullet
6391 @item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6392 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6393 @end itemize
6394
6395
6396 @itemize @bullet
6397 @item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6398 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6399 @end itemize
6400
6401
6402 @itemize @bullet
6403 @item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6404 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6405 @end itemize
6406
6407
6408 @itemize @bullet
6409 @item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6410 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6411 @end itemize
6412
6413
6414 @itemize @bullet
6415 @item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6416 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6417 @end itemize
6418
6419
6420 @itemize @bullet
6421 @item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6422 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6423 @end itemize
6424
6425
6426 @itemize @bullet
6427 @item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6428 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6429 @end itemize
6430
6431
6432 @itemize @bullet
6433 @item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6434 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6435 @end itemize
6436
6437
6438 @itemize @bullet
6439 @item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6440 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6441 @end itemize
6442
6443
6444 @itemize @bullet
6445 @item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6446 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6447 @end itemize
6448
6449
6450 @itemize @bullet
6451 @item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6452 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6453 @end itemize
6454
6455
6456
6457
6458 @subsubsection Vector multiply by scalar
6459
6460 @itemize @bullet
6461 @item float32x2_t vmul_n_f32 (float32x2_t, float32_t)
6462 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6463 @end itemize
6464
6465
6466 @itemize @bullet
6467 @item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
6468 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6469 @end itemize
6470
6471
6472 @itemize @bullet
6473 @item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
6474 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6475 @end itemize
6476
6477
6478 @itemize @bullet
6479 @item int32x2_t vmul_n_s32 (int32x2_t, int32_t)
6480 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6481 @end itemize
6482
6483
6484 @itemize @bullet
6485 @item int16x4_t vmul_n_s16 (int16x4_t, int16_t)
6486 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6487 @end itemize
6488
6489
6490 @itemize @bullet
6491 @item float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
6492 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6493 @end itemize
6494
6495
6496 @itemize @bullet
6497 @item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
6498 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6499 @end itemize
6500
6501
6502 @itemize @bullet
6503 @item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
6504 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6505 @end itemize
6506
6507
6508 @itemize @bullet
6509 @item int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
6510 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6511 @end itemize
6512
6513
6514 @itemize @bullet
6515 @item int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
6516 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6517 @end itemize
6518
6519
6520
6521
6522 @subsubsection Vector long multiply by scalar
6523
6524 @itemize @bullet
6525 @item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
6526 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6527 @end itemize
6528
6529
6530 @itemize @bullet
6531 @item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
6532 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6533 @end itemize
6534
6535
6536 @itemize @bullet
6537 @item int64x2_t vmull_n_s32 (int32x2_t, int32_t)
6538 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6539 @end itemize
6540
6541
6542 @itemize @bullet
6543 @item int32x4_t vmull_n_s16 (int16x4_t, int16_t)
6544 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6545 @end itemize
6546
6547
6548
6549
6550 @subsubsection Vector saturating doubling long multiply by scalar
6551
6552 @itemize @bullet
6553 @item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
6554 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6555 @end itemize
6556
6557
6558 @itemize @bullet
6559 @item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
6560 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6561 @end itemize
6562
6563
6564
6565
6566 @subsubsection Vector saturating doubling multiply high by scalar
6567
6568 @itemize @bullet
6569 @item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
6570 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6571 @end itemize
6572
6573
6574 @itemize @bullet
6575 @item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
6576 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6577 @end itemize
6578
6579
6580 @itemize @bullet
6581 @item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
6582 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6583 @end itemize
6584
6585
6586 @itemize @bullet
6587 @item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
6588 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6589 @end itemize
6590
6591
6592 @itemize @bullet
6593 @item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
6594 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6595 @end itemize
6596
6597
6598 @itemize @bullet
6599 @item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
6600 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6601 @end itemize
6602
6603
6604 @itemize @bullet
6605 @item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
6606 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6607 @end itemize
6608
6609
6610 @itemize @bullet
6611 @item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
6612 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6613 @end itemize
6614
6615
6616
6617
6618 @subsubsection Vector multiply-accumulate by scalar
6619
6620 @itemize @bullet
6621 @item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
6622 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6623 @end itemize
6624
6625
6626 @itemize @bullet
6627 @item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6628 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6629 @end itemize
6630
6631
6632 @itemize @bullet
6633 @item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6634 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6635 @end itemize
6636
6637
6638 @itemize @bullet
6639 @item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
6640 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6641 @end itemize
6642
6643
6644 @itemize @bullet
6645 @item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
6646 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6647 @end itemize
6648
6649
6650 @itemize @bullet
6651 @item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
6652 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6653 @end itemize
6654
6655
6656 @itemize @bullet
6657 @item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6658 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6659 @end itemize
6660
6661
6662 @itemize @bullet
6663 @item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6664 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6665 @end itemize
6666
6667
6668 @itemize @bullet
6669 @item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
6670 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6671 @end itemize
6672
6673
6674 @itemize @bullet
6675 @item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
6676 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6677 @end itemize
6678
6679
6680 @itemize @bullet
6681 @item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6682 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6683 @end itemize
6684
6685
6686 @itemize @bullet
6687 @item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6688 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6689 @end itemize
6690
6691
6692 @itemize @bullet
6693 @item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6694 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6695 @end itemize
6696
6697
6698 @itemize @bullet
6699 @item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6700 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6701 @end itemize
6702
6703
6704 @itemize @bullet
6705 @item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6706 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6707 @end itemize
6708
6709
6710 @itemize @bullet
6711 @item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6712 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6713 @end itemize
6714
6715
6716
6717
6718 @subsubsection Vector multiply-subtract by scalar
6719
6720 @itemize @bullet
6721 @item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
6722 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6723 @end itemize
6724
6725
6726 @itemize @bullet
6727 @item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6728 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6729 @end itemize
6730
6731
6732 @itemize @bullet
6733 @item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6734 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6735 @end itemize
6736
6737
6738 @itemize @bullet
6739 @item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
6740 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6741 @end itemize
6742
6743
6744 @itemize @bullet
6745 @item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
6746 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6747 @end itemize
6748
6749
6750 @itemize @bullet
6751 @item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
6752 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6753 @end itemize
6754
6755
6756 @itemize @bullet
6757 @item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6758 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6759 @end itemize
6760
6761
6762 @itemize @bullet
6763 @item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6764 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6765 @end itemize
6766
6767
6768 @itemize @bullet
6769 @item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
6770 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6771 @end itemize
6772
6773
6774 @itemize @bullet
6775 @item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
6776 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6777 @end itemize
6778
6779
6780 @itemize @bullet
6781 @item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6782 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6783 @end itemize
6784
6785
6786 @itemize @bullet
6787 @item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6788 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6789 @end itemize
6790
6791
6792 @itemize @bullet
6793 @item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6794 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6795 @end itemize
6796
6797
6798 @itemize @bullet
6799 @item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6800 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6801 @end itemize
6802
6803
6804 @itemize @bullet
6805 @item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6806 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6807 @end itemize
6808
6809
6810 @itemize @bullet
6811 @item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6812 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6813 @end itemize
6814
6815
6816
6817
6818 @subsubsection Vector extract
6819
6820 @itemize @bullet
6821 @item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
6822 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6823 @end itemize
6824
6825
6826 @itemize @bullet
6827 @item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
6828 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6829 @end itemize
6830
6831
6832 @itemize @bullet
6833 @item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
6834 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6835 @end itemize
6836
6837
6838 @itemize @bullet
6839 @item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
6840 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6841 @end itemize
6842
6843
6844 @itemize @bullet
6845 @item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
6846 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6847 @end itemize
6848
6849
6850 @itemize @bullet
6851 @item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
6852 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6853 @end itemize
6854
6855
6856 @itemize @bullet
6857 @item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
6858 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6859 @end itemize
6860
6861
6862 @itemize @bullet
6863 @item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
6864 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6865 @end itemize
6866
6867
6868 @itemize @bullet
6869 @item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
6870 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6871 @end itemize
6872
6873
6874 @itemize @bullet
6875 @item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
6876 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6877 @end itemize
6878
6879
6880 @itemize @bullet
6881 @item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
6882 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6883 @end itemize
6884
6885
6886 @itemize @bullet
6887 @item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
6888 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6889 @end itemize
6890
6891
6892 @itemize @bullet
6893 @item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
6894 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6895 @end itemize
6896
6897
6898 @itemize @bullet
6899 @item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
6900 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6901 @end itemize
6902
6903
6904 @itemize @bullet
6905 @item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
6906 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6907 @end itemize
6908
6909
6910 @itemize @bullet
6911 @item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
6912 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6913 @end itemize
6914
6915
6916 @itemize @bullet
6917 @item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
6918 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6919 @end itemize
6920
6921
6922 @itemize @bullet
6923 @item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
6924 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6925 @end itemize
6926
6927
6928 @itemize @bullet
6929 @item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
6930 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6931 @end itemize
6932
6933
6934 @itemize @bullet
6935 @item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
6936 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6937 @end itemize
6938
6939
6940 @itemize @bullet
6941 @item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
6942 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6943 @end itemize
6944
6945
6946 @itemize @bullet
6947 @item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
6948 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6949 @end itemize
6950
6951
6952
6953
6954 @subsubsection Reverse elements
6955
6956 @itemize @bullet
6957 @item uint32x2_t vrev64_u32 (uint32x2_t)
6958 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6959 @end itemize
6960
6961
6962 @itemize @bullet
6963 @item uint16x4_t vrev64_u16 (uint16x4_t)
6964 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6965 @end itemize
6966
6967
6968 @itemize @bullet
6969 @item uint8x8_t vrev64_u8 (uint8x8_t)
6970 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6971 @end itemize
6972
6973
6974 @itemize @bullet
6975 @item int32x2_t vrev64_s32 (int32x2_t)
6976 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6977 @end itemize
6978
6979
6980 @itemize @bullet
6981 @item int16x4_t vrev64_s16 (int16x4_t)
6982 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6983 @end itemize
6984
6985
6986 @itemize @bullet
6987 @item int8x8_t vrev64_s8 (int8x8_t)
6988 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6989 @end itemize
6990
6991
6992 @itemize @bullet
6993 @item float32x2_t vrev64_f32 (float32x2_t)
6994 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6995 @end itemize
6996
6997
6998 @itemize @bullet
6999 @item poly16x4_t vrev64_p16 (poly16x4_t)
7000 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
7001 @end itemize
7002
7003
7004 @itemize @bullet
7005 @item poly8x8_t vrev64_p8 (poly8x8_t)
7006 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
7007 @end itemize
7008
7009
7010 @itemize @bullet
7011 @item uint32x4_t vrev64q_u32 (uint32x4_t)
7012 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7013 @end itemize
7014
7015
7016 @itemize @bullet
7017 @item uint16x8_t vrev64q_u16 (uint16x8_t)
7018 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7019 @end itemize
7020
7021
7022 @itemize @bullet
7023 @item uint8x16_t vrev64q_u8 (uint8x16_t)
7024 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7025 @end itemize
7026
7027
7028 @itemize @bullet
7029 @item int32x4_t vrev64q_s32 (int32x4_t)
7030 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7031 @end itemize
7032
7033
7034 @itemize @bullet
7035 @item int16x8_t vrev64q_s16 (int16x8_t)
7036 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7037 @end itemize
7038
7039
7040 @itemize @bullet
7041 @item int8x16_t vrev64q_s8 (int8x16_t)
7042 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7043 @end itemize
7044
7045
7046 @itemize @bullet
7047 @item float32x4_t vrev64q_f32 (float32x4_t)
7048 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7049 @end itemize
7050
7051
7052 @itemize @bullet
7053 @item poly16x8_t vrev64q_p16 (poly16x8_t)
7054 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7055 @end itemize
7056
7057
7058 @itemize @bullet
7059 @item poly8x16_t vrev64q_p8 (poly8x16_t)
7060 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7061 @end itemize
7062
7063
7064 @itemize @bullet
7065 @item uint16x4_t vrev32_u16 (uint16x4_t)
7066 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7067 @end itemize
7068
7069
7070 @itemize @bullet
7071 @item int16x4_t vrev32_s16 (int16x4_t)
7072 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7073 @end itemize
7074
7075
7076 @itemize @bullet
7077 @item uint8x8_t vrev32_u8 (uint8x8_t)
7078 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7079 @end itemize
7080
7081
7082 @itemize @bullet
7083 @item int8x8_t vrev32_s8 (int8x8_t)
7084 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7085 @end itemize
7086
7087
7088 @itemize @bullet
7089 @item poly16x4_t vrev32_p16 (poly16x4_t)
7090 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7091 @end itemize
7092
7093
7094 @itemize @bullet
7095 @item poly8x8_t vrev32_p8 (poly8x8_t)
7096 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7097 @end itemize
7098
7099
7100 @itemize @bullet
7101 @item uint16x8_t vrev32q_u16 (uint16x8_t)
7102 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7103 @end itemize
7104
7105
7106 @itemize @bullet
7107 @item int16x8_t vrev32q_s16 (int16x8_t)
7108 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7109 @end itemize
7110
7111
7112 @itemize @bullet
7113 @item uint8x16_t vrev32q_u8 (uint8x16_t)
7114 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7115 @end itemize
7116
7117
7118 @itemize @bullet
7119 @item int8x16_t vrev32q_s8 (int8x16_t)
7120 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7121 @end itemize
7122
7123
7124 @itemize @bullet
7125 @item poly16x8_t vrev32q_p16 (poly16x8_t)
7126 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7127 @end itemize
7128
7129
7130 @itemize @bullet
7131 @item poly8x16_t vrev32q_p8 (poly8x16_t)
7132 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7133 @end itemize
7134
7135
7136 @itemize @bullet
7137 @item uint8x8_t vrev16_u8 (uint8x8_t)
7138 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7139 @end itemize
7140
7141
7142 @itemize @bullet
7143 @item int8x8_t vrev16_s8 (int8x8_t)
7144 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7145 @end itemize
7146
7147
7148 @itemize @bullet
7149 @item poly8x8_t vrev16_p8 (poly8x8_t)
7150 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7151 @end itemize
7152
7153
7154 @itemize @bullet
7155 @item uint8x16_t vrev16q_u8 (uint8x16_t)
7156 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7157 @end itemize
7158
7159
7160 @itemize @bullet
7161 @item int8x16_t vrev16q_s8 (int8x16_t)
7162 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7163 @end itemize
7164
7165
7166 @itemize @bullet
7167 @item poly8x16_t vrev16q_p8 (poly8x16_t)
7168 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7169 @end itemize
7170
7171
7172
7173
7174 @subsubsection Bit selection
7175
7176 @itemize @bullet
7177 @item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
7178 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7179 @end itemize
7180
7181
7182 @itemize @bullet
7183 @item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
7184 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7185 @end itemize
7186
7187
7188 @itemize @bullet
7189 @item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
7190 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7191 @end itemize
7192
7193
7194 @itemize @bullet
7195 @item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
7196 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7197 @end itemize
7198
7199
7200 @itemize @bullet
7201 @item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
7202 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7203 @end itemize
7204
7205
7206 @itemize @bullet
7207 @item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
7208 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7209 @end itemize
7210
7211
7212 @itemize @bullet
7213 @item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
7214 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7215 @end itemize
7216
7217
7218 @itemize @bullet
7219 @item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
7220 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7221 @end itemize
7222
7223
7224 @itemize @bullet
7225 @item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
7226 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7227 @end itemize
7228
7229
7230 @itemize @bullet
7231 @item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
7232 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7233 @end itemize
7234
7235
7236 @itemize @bullet
7237 @item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
7238 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7239 @end itemize
7240
7241
7242 @itemize @bullet
7243 @item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
7244 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7245 @end itemize
7246
7247
7248 @itemize @bullet
7249 @item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
7250 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7251 @end itemize
7252
7253
7254 @itemize @bullet
7255 @item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
7256 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7257 @end itemize
7258
7259
7260 @itemize @bullet
7261 @item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
7262 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7263 @end itemize
7264
7265
7266 @itemize @bullet
7267 @item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
7268 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7269 @end itemize
7270
7271
7272 @itemize @bullet
7273 @item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
7274 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7275 @end itemize
7276
7277
7278 @itemize @bullet
7279 @item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
7280 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7281 @end itemize
7282
7283
7284 @itemize @bullet
7285 @item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
7286 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7287 @end itemize
7288
7289
7290 @itemize @bullet
7291 @item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
7292 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7293 @end itemize
7294
7295
7296 @itemize @bullet
7297 @item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
7298 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7299 @end itemize
7300
7301
7302 @itemize @bullet
7303 @item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
7304 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7305 @end itemize
7306
7307
7308
7309
7310 @subsubsection Transpose elements
7311
7312 @itemize @bullet
7313 @item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
7314 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7315 @end itemize
7316
7317
7318 @itemize @bullet
7319 @item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
7320 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7321 @end itemize
7322
7323
7324 @itemize @bullet
7325 @item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
7326 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7327 @end itemize
7328
7329
7330 @itemize @bullet
7331 @item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
7332 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7333 @end itemize
7334
7335
7336 @itemize @bullet
7337 @item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
7338 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7339 @end itemize
7340
7341
7342 @itemize @bullet
7343 @item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
7344 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7345 @end itemize
7346
7347
7348 @itemize @bullet
7349 @item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
7350 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7351 @end itemize
7352
7353
7354 @itemize @bullet
7355 @item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
7356 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7357 @end itemize
7358
7359
7360 @itemize @bullet
7361 @item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
7362 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7363 @end itemize
7364
7365
7366 @itemize @bullet
7367 @item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
7368 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7369 @end itemize
7370
7371
7372 @itemize @bullet
7373 @item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
7374 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7375 @end itemize
7376
7377
7378 @itemize @bullet
7379 @item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
7380 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7381 @end itemize
7382
7383
7384 @itemize @bullet
7385 @item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
7386 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7387 @end itemize
7388
7389
7390 @itemize @bullet
7391 @item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
7392 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7393 @end itemize
7394
7395
7396 @itemize @bullet
7397 @item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
7398 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7399 @end itemize
7400
7401
7402 @itemize @bullet
7403 @item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
7404 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7405 @end itemize
7406
7407
7408 @itemize @bullet
7409 @item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
7410 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7411 @end itemize
7412
7413
7414 @itemize @bullet
7415 @item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
7416 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7417 @end itemize
7418
7419
7420
7421
7422 @subsubsection Zip elements
7423
7424 @itemize @bullet
7425 @item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
7426 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7427 @end itemize
7428
7429
7430 @itemize @bullet
7431 @item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
7432 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7433 @end itemize
7434
7435
7436 @itemize @bullet
7437 @item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
7438 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7439 @end itemize
7440
7441
7442 @itemize @bullet
7443 @item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
7444 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7445 @end itemize
7446
7447
7448 @itemize @bullet
7449 @item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
7450 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7451 @end itemize
7452
7453
7454 @itemize @bullet
7455 @item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
7456 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7457 @end itemize
7458
7459
7460 @itemize @bullet
7461 @item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
7462 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7463 @end itemize
7464
7465
7466 @itemize @bullet
7467 @item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
7468 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7469 @end itemize
7470
7471
7472 @itemize @bullet
7473 @item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
7474 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7475 @end itemize
7476
7477
7478 @itemize @bullet
7479 @item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
7480 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7481 @end itemize
7482
7483
7484 @itemize @bullet
7485 @item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
7486 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7487 @end itemize
7488
7489
7490 @itemize @bullet
7491 @item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
7492 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7493 @end itemize
7494
7495
7496 @itemize @bullet
7497 @item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
7498 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7499 @end itemize
7500
7501
7502 @itemize @bullet
7503 @item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
7504 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7505 @end itemize
7506
7507
7508 @itemize @bullet
7509 @item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
7510 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7511 @end itemize
7512
7513
7514 @itemize @bullet
7515 @item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
7516 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7517 @end itemize
7518
7519
7520 @itemize @bullet
7521 @item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
7522 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7523 @end itemize
7524
7525
7526 @itemize @bullet
7527 @item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
7528 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7529 @end itemize
7530
7531
7532
7533
7534 @subsubsection Unzip elements
7535
7536 @itemize @bullet
7537 @item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
7538 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7539 @end itemize
7540
7541
7542 @itemize @bullet
7543 @item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
7544 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7545 @end itemize
7546
7547
7548 @itemize @bullet
7549 @item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
7550 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7551 @end itemize
7552
7553
7554 @itemize @bullet
7555 @item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
7556 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7557 @end itemize
7558
7559
7560 @itemize @bullet
7561 @item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
7562 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7563 @end itemize
7564
7565
7566 @itemize @bullet
7567 @item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
7568 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7569 @end itemize
7570
7571
7572 @itemize @bullet
7573 @item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
7574 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7575 @end itemize
7576
7577
7578 @itemize @bullet
7579 @item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
7580 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7581 @end itemize
7582
7583
7584 @itemize @bullet
7585 @item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
7586 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7587 @end itemize
7588
7589
7590 @itemize @bullet
7591 @item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
7592 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7593 @end itemize
7594
7595
7596 @itemize @bullet
7597 @item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
7598 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7599 @end itemize
7600
7601
7602 @itemize @bullet
7603 @item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
7604 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7605 @end itemize
7606
7607
7608 @itemize @bullet
7609 @item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
7610 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7611 @end itemize
7612
7613
7614 @itemize @bullet
7615 @item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
7616 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7617 @end itemize
7618
7619
7620 @itemize @bullet
7621 @item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
7622 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7623 @end itemize
7624
7625
7626 @itemize @bullet
7627 @item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
7628 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7629 @end itemize
7630
7631
7632 @itemize @bullet
7633 @item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
7634 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7635 @end itemize
7636
7637
7638 @itemize @bullet
7639 @item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
7640 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7641 @end itemize
7642
7643
7644
7645
7646 @subsubsection Element/structure loads, VLD1 variants
7647
7648 @itemize @bullet
7649 @item uint32x2_t vld1_u32 (const uint32_t *)
7650 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7651 @end itemize
7652
7653
7654 @itemize @bullet
7655 @item uint16x4_t vld1_u16 (const uint16_t *)
7656 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7657 @end itemize
7658
7659
7660 @itemize @bullet
7661 @item uint8x8_t vld1_u8 (const uint8_t *)
7662 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7663 @end itemize
7664
7665
7666 @itemize @bullet
7667 @item int32x2_t vld1_s32 (const int32_t *)
7668 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7669 @end itemize
7670
7671
7672 @itemize @bullet
7673 @item int16x4_t vld1_s16 (const int16_t *)
7674 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7675 @end itemize
7676
7677
7678 @itemize @bullet
7679 @item int8x8_t vld1_s8 (const int8_t *)
7680 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7681 @end itemize
7682
7683
7684 @itemize @bullet
7685 @item uint64x1_t vld1_u64 (const uint64_t *)
7686 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7687 @end itemize
7688
7689
7690 @itemize @bullet
7691 @item int64x1_t vld1_s64 (const int64_t *)
7692 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7693 @end itemize
7694
7695
7696 @itemize @bullet
7697 @item float32x2_t vld1_f32 (const float32_t *)
7698 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7699 @end itemize
7700
7701
7702 @itemize @bullet
7703 @item poly16x4_t vld1_p16 (const poly16_t *)
7704 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7705 @end itemize
7706
7707
7708 @itemize @bullet
7709 @item poly8x8_t vld1_p8 (const poly8_t *)
7710 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7711 @end itemize
7712
7713
7714 @itemize @bullet
7715 @item uint32x4_t vld1q_u32 (const uint32_t *)
7716 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7717 @end itemize
7718
7719
7720 @itemize @bullet
7721 @item uint16x8_t vld1q_u16 (const uint16_t *)
7722 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7723 @end itemize
7724
7725
7726 @itemize @bullet
7727 @item uint8x16_t vld1q_u8 (const uint8_t *)
7728 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7729 @end itemize
7730
7731
7732 @itemize @bullet
7733 @item int32x4_t vld1q_s32 (const int32_t *)
7734 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7735 @end itemize
7736
7737
7738 @itemize @bullet
7739 @item int16x8_t vld1q_s16 (const int16_t *)
7740 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7741 @end itemize
7742
7743
7744 @itemize @bullet
7745 @item int8x16_t vld1q_s8 (const int8_t *)
7746 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7747 @end itemize
7748
7749
7750 @itemize @bullet
7751 @item uint64x2_t vld1q_u64 (const uint64_t *)
7752 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7753 @end itemize
7754
7755
7756 @itemize @bullet
7757 @item int64x2_t vld1q_s64 (const int64_t *)
7758 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7759 @end itemize
7760
7761
7762 @itemize @bullet
7763 @item float32x4_t vld1q_f32 (const float32_t *)
7764 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7765 @end itemize
7766
7767
7768 @itemize @bullet
7769 @item poly16x8_t vld1q_p16 (const poly16_t *)
7770 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7771 @end itemize
7772
7773
7774 @itemize @bullet
7775 @item poly8x16_t vld1q_p8 (const poly8_t *)
7776 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7777 @end itemize
7778
7779
7780 @itemize @bullet
7781 @item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
7782 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7783 @end itemize
7784
7785
7786 @itemize @bullet
7787 @item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
7788 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7789 @end itemize
7790
7791
7792 @itemize @bullet
7793 @item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
7794 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7795 @end itemize
7796
7797
7798 @itemize @bullet
7799 @item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
7800 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7801 @end itemize
7802
7803
7804 @itemize @bullet
7805 @item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
7806 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7807 @end itemize
7808
7809
7810 @itemize @bullet
7811 @item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
7812 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7813 @end itemize
7814
7815
7816 @itemize @bullet
7817 @item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
7818 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7819 @end itemize
7820
7821
7822 @itemize @bullet
7823 @item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
7824 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7825 @end itemize
7826
7827
7828 @itemize @bullet
7829 @item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
7830 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7831 @end itemize
7832
7833
7834 @itemize @bullet
7835 @item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
7836 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7837 @end itemize
7838
7839
7840 @itemize @bullet
7841 @item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
7842 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7843 @end itemize
7844
7845
7846 @itemize @bullet
7847 @item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
7848 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7849 @end itemize
7850
7851
7852 @itemize @bullet
7853 @item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
7854 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7855 @end itemize
7856
7857
7858 @itemize @bullet
7859 @item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
7860 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7861 @end itemize
7862
7863
7864 @itemize @bullet
7865 @item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
7866 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7867 @end itemize
7868
7869
7870 @itemize @bullet
7871 @item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
7872 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7873 @end itemize
7874
7875
7876 @itemize @bullet
7877 @item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
7878 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7879 @end itemize
7880
7881
7882 @itemize @bullet
7883 @item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
7884 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7885 @end itemize
7886
7887
7888 @itemize @bullet
7889 @item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
7890 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7891 @end itemize
7892
7893
7894 @itemize @bullet
7895 @item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
7896 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7897 @end itemize
7898
7899
7900 @itemize @bullet
7901 @item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
7902 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7903 @end itemize
7904
7905
7906 @itemize @bullet
7907 @item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
7908 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7909 @end itemize
7910
7911
7912 @itemize @bullet
7913 @item uint32x2_t vld1_dup_u32 (const uint32_t *)
7914 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7915 @end itemize
7916
7917
7918 @itemize @bullet
7919 @item uint16x4_t vld1_dup_u16 (const uint16_t *)
7920 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7921 @end itemize
7922
7923
7924 @itemize @bullet
7925 @item uint8x8_t vld1_dup_u8 (const uint8_t *)
7926 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7927 @end itemize
7928
7929
7930 @itemize @bullet
7931 @item int32x2_t vld1_dup_s32 (const int32_t *)
7932 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7933 @end itemize
7934
7935
7936 @itemize @bullet
7937 @item int16x4_t vld1_dup_s16 (const int16_t *)
7938 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7939 @end itemize
7940
7941
7942 @itemize @bullet
7943 @item int8x8_t vld1_dup_s8 (const int8_t *)
7944 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7945 @end itemize
7946
7947
7948 @itemize @bullet
7949 @item float32x2_t vld1_dup_f32 (const float32_t *)
7950 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7951 @end itemize
7952
7953
7954 @itemize @bullet
7955 @item poly16x4_t vld1_dup_p16 (const poly16_t *)
7956 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7957 @end itemize
7958
7959
7960 @itemize @bullet
7961 @item poly8x8_t vld1_dup_p8 (const poly8_t *)
7962 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7963 @end itemize
7964
7965
7966 @itemize @bullet
7967 @item uint64x1_t vld1_dup_u64 (const uint64_t *)
7968 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7969 @end itemize
7970
7971
7972 @itemize @bullet
7973 @item int64x1_t vld1_dup_s64 (const int64_t *)
7974 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7975 @end itemize
7976
7977
7978 @itemize @bullet
7979 @item uint32x4_t vld1q_dup_u32 (const uint32_t *)
7980 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7981 @end itemize
7982
7983
7984 @itemize @bullet
7985 @item uint16x8_t vld1q_dup_u16 (const uint16_t *)
7986 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7987 @end itemize
7988
7989
7990 @itemize @bullet
7991 @item uint8x16_t vld1q_dup_u8 (const uint8_t *)
7992 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7993 @end itemize
7994
7995
7996 @itemize @bullet
7997 @item int32x4_t vld1q_dup_s32 (const int32_t *)
7998 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7999 @end itemize
8000
8001
8002 @itemize @bullet
8003 @item int16x8_t vld1q_dup_s16 (const int16_t *)
8004 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8005 @end itemize
8006
8007
8008 @itemize @bullet
8009 @item int8x16_t vld1q_dup_s8 (const int8_t *)
8010 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8011 @end itemize
8012
8013
8014 @itemize @bullet
8015 @item float32x4_t vld1q_dup_f32 (const float32_t *)
8016 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8017 @end itemize
8018
8019
8020 @itemize @bullet
8021 @item poly16x8_t vld1q_dup_p16 (const poly16_t *)
8022 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8023 @end itemize
8024
8025
8026 @itemize @bullet
8027 @item poly8x16_t vld1q_dup_p8 (const poly8_t *)
8028 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8029 @end itemize
8030
8031
8032 @itemize @bullet
8033 @item uint64x2_t vld1q_dup_u64 (const uint64_t *)
8034 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8035 @end itemize
8036
8037
8038 @itemize @bullet
8039 @item int64x2_t vld1q_dup_s64 (const int64_t *)
8040 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8041 @end itemize
8042
8043
8044
8045
8046 @subsubsection Element/structure stores, VST1 variants
8047
8048 @itemize @bullet
8049 @item void vst1_u32 (uint32_t *, uint32x2_t)
8050 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8051 @end itemize
8052
8053
8054 @itemize @bullet
8055 @item void vst1_u16 (uint16_t *, uint16x4_t)
8056 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8057 @end itemize
8058
8059
8060 @itemize @bullet
8061 @item void vst1_u8 (uint8_t *, uint8x8_t)
8062 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8063 @end itemize
8064
8065
8066 @itemize @bullet
8067 @item void vst1_s32 (int32_t *, int32x2_t)
8068 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8069 @end itemize
8070
8071
8072 @itemize @bullet
8073 @item void vst1_s16 (int16_t *, int16x4_t)
8074 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8075 @end itemize
8076
8077
8078 @itemize @bullet
8079 @item void vst1_s8 (int8_t *, int8x8_t)
8080 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8081 @end itemize
8082
8083
8084 @itemize @bullet
8085 @item void vst1_u64 (uint64_t *, uint64x1_t)
8086 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8087 @end itemize
8088
8089
8090 @itemize @bullet
8091 @item void vst1_s64 (int64_t *, int64x1_t)
8092 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8093 @end itemize
8094
8095
8096 @itemize @bullet
8097 @item void vst1_f32 (float32_t *, float32x2_t)
8098 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8099 @end itemize
8100
8101
8102 @itemize @bullet
8103 @item void vst1_p16 (poly16_t *, poly16x4_t)
8104 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8105 @end itemize
8106
8107
8108 @itemize @bullet
8109 @item void vst1_p8 (poly8_t *, poly8x8_t)
8110 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8111 @end itemize
8112
8113
8114 @itemize @bullet
8115 @item void vst1q_u32 (uint32_t *, uint32x4_t)
8116 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8117 @end itemize
8118
8119
8120 @itemize @bullet
8121 @item void vst1q_u16 (uint16_t *, uint16x8_t)
8122 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8123 @end itemize
8124
8125
8126 @itemize @bullet
8127 @item void vst1q_u8 (uint8_t *, uint8x16_t)
8128 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8129 @end itemize
8130
8131
8132 @itemize @bullet
8133 @item void vst1q_s32 (int32_t *, int32x4_t)
8134 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8135 @end itemize
8136
8137
8138 @itemize @bullet
8139 @item void vst1q_s16 (int16_t *, int16x8_t)
8140 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8141 @end itemize
8142
8143
8144 @itemize @bullet
8145 @item void vst1q_s8 (int8_t *, int8x16_t)
8146 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8147 @end itemize
8148
8149
8150 @itemize @bullet
8151 @item void vst1q_u64 (uint64_t *, uint64x2_t)
8152 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8153 @end itemize
8154
8155
8156 @itemize @bullet
8157 @item void vst1q_s64 (int64_t *, int64x2_t)
8158 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8159 @end itemize
8160
8161
8162 @itemize @bullet
8163 @item void vst1q_f32 (float32_t *, float32x4_t)
8164 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8165 @end itemize
8166
8167
8168 @itemize @bullet
8169 @item void vst1q_p16 (poly16_t *, poly16x8_t)
8170 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8171 @end itemize
8172
8173
8174 @itemize @bullet
8175 @item void vst1q_p8 (poly8_t *, poly8x16_t)
8176 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8177 @end itemize
8178
8179
8180 @itemize @bullet
8181 @item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
8182 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8183 @end itemize
8184
8185
8186 @itemize @bullet
8187 @item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
8188 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8189 @end itemize
8190
8191
8192 @itemize @bullet
8193 @item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
8194 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8195 @end itemize
8196
8197
8198 @itemize @bullet
8199 @item void vst1_lane_s32 (int32_t *, int32x2_t, const int)
8200 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8201 @end itemize
8202
8203
8204 @itemize @bullet
8205 @item void vst1_lane_s16 (int16_t *, int16x4_t, const int)
8206 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8207 @end itemize
8208
8209
8210 @itemize @bullet
8211 @item void vst1_lane_s8 (int8_t *, int8x8_t, const int)
8212 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8213 @end itemize
8214
8215
8216 @itemize @bullet
8217 @item void vst1_lane_f32 (float32_t *, float32x2_t, const int)
8218 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8219 @end itemize
8220
8221
8222 @itemize @bullet
8223 @item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
8224 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8225 @end itemize
8226
8227
8228 @itemize @bullet
8229 @item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
8230 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8231 @end itemize
8232
8233
8234 @itemize @bullet
8235 @item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
8236 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8237 @end itemize
8238
8239
8240 @itemize @bullet
8241 @item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
8242 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8243 @end itemize
8244
8245
8246 @itemize @bullet
8247 @item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
8248 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8249 @end itemize
8250
8251
8252 @itemize @bullet
8253 @item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
8254 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8255 @end itemize
8256
8257
8258 @itemize @bullet
8259 @item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
8260 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8261 @end itemize
8262
8263
8264 @itemize @bullet
8265 @item void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
8266 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8267 @end itemize
8268
8269
8270 @itemize @bullet
8271 @item void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
8272 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8273 @end itemize
8274
8275
8276 @itemize @bullet
8277 @item void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
8278 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8279 @end itemize
8280
8281
8282 @itemize @bullet
8283 @item void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
8284 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8285 @end itemize
8286
8287
8288 @itemize @bullet
8289 @item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
8290 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8291 @end itemize
8292
8293
8294 @itemize @bullet
8295 @item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
8296 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8297 @end itemize
8298
8299
8300 @itemize @bullet
8301 @item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
8302 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8303 @end itemize
8304
8305
8306 @itemize @bullet
8307 @item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
8308 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8309 @end itemize
8310
8311
8312
8313
8314 @subsubsection Element/structure loads, VLD2 variants
8315
8316 @itemize @bullet
8317 @item uint32x2x2_t vld2_u32 (const uint32_t *)
8318 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8319 @end itemize
8320
8321
8322 @itemize @bullet
8323 @item uint16x4x2_t vld2_u16 (const uint16_t *)
8324 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8325 @end itemize
8326
8327
8328 @itemize @bullet
8329 @item uint8x8x2_t vld2_u8 (const uint8_t *)
8330 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8331 @end itemize
8332
8333
8334 @itemize @bullet
8335 @item int32x2x2_t vld2_s32 (const int32_t *)
8336 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8337 @end itemize
8338
8339
8340 @itemize @bullet
8341 @item int16x4x2_t vld2_s16 (const int16_t *)
8342 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8343 @end itemize
8344
8345
8346 @itemize @bullet
8347 @item int8x8x2_t vld2_s8 (const int8_t *)
8348 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8349 @end itemize
8350
8351
8352 @itemize @bullet
8353 @item float32x2x2_t vld2_f32 (const float32_t *)
8354 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8355 @end itemize
8356
8357
8358 @itemize @bullet
8359 @item poly16x4x2_t vld2_p16 (const poly16_t *)
8360 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8361 @end itemize
8362
8363
8364 @itemize @bullet
8365 @item poly8x8x2_t vld2_p8 (const poly8_t *)
8366 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8367 @end itemize
8368
8369
8370 @itemize @bullet
8371 @item uint64x1x2_t vld2_u64 (const uint64_t *)
8372 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8373 @end itemize
8374
8375
8376 @itemize @bullet
8377 @item int64x1x2_t vld2_s64 (const int64_t *)
8378 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8379 @end itemize
8380
8381
8382 @itemize @bullet
8383 @item uint32x4x2_t vld2q_u32 (const uint32_t *)
8384 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8385 @end itemize
8386
8387
8388 @itemize @bullet
8389 @item uint16x8x2_t vld2q_u16 (const uint16_t *)
8390 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8391 @end itemize
8392
8393
8394 @itemize @bullet
8395 @item uint8x16x2_t vld2q_u8 (const uint8_t *)
8396 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8397 @end itemize
8398
8399
8400 @itemize @bullet
8401 @item int32x4x2_t vld2q_s32 (const int32_t *)
8402 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8403 @end itemize
8404
8405
8406 @itemize @bullet
8407 @item int16x8x2_t vld2q_s16 (const int16_t *)
8408 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8409 @end itemize
8410
8411
8412 @itemize @bullet
8413 @item int8x16x2_t vld2q_s8 (const int8_t *)
8414 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8415 @end itemize
8416
8417
8418 @itemize @bullet
8419 @item float32x4x2_t vld2q_f32 (const float32_t *)
8420 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8421 @end itemize
8422
8423
8424 @itemize @bullet
8425 @item poly16x8x2_t vld2q_p16 (const poly16_t *)
8426 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8427 @end itemize
8428
8429
8430 @itemize @bullet
8431 @item poly8x16x2_t vld2q_p8 (const poly8_t *)
8432 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8433 @end itemize
8434
8435
8436 @itemize @bullet
8437 @item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
8438 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8439 @end itemize
8440
8441
8442 @itemize @bullet
8443 @item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
8444 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8445 @end itemize
8446
8447
8448 @itemize @bullet
8449 @item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
8450 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8451 @end itemize
8452
8453
8454 @itemize @bullet
8455 @item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
8456 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8457 @end itemize
8458
8459
8460 @itemize @bullet
8461 @item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
8462 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8463 @end itemize
8464
8465
8466 @itemize @bullet
8467 @item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
8468 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8469 @end itemize
8470
8471
8472 @itemize @bullet
8473 @item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
8474 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8475 @end itemize
8476
8477
8478 @itemize @bullet
8479 @item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
8480 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8481 @end itemize
8482
8483
8484 @itemize @bullet
8485 @item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
8486 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8487 @end itemize
8488
8489
8490 @itemize @bullet
8491 @item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
8492 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8493 @end itemize
8494
8495
8496 @itemize @bullet
8497 @item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
8498 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8499 @end itemize
8500
8501
8502 @itemize @bullet
8503 @item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
8504 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8505 @end itemize
8506
8507
8508 @itemize @bullet
8509 @item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
8510 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8511 @end itemize
8512
8513
8514 @itemize @bullet
8515 @item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
8516 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8517 @end itemize
8518
8519
8520 @itemize @bullet
8521 @item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
8522 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8523 @end itemize
8524
8525
8526 @itemize @bullet
8527 @item uint32x2x2_t vld2_dup_u32 (const uint32_t *)
8528 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8529 @end itemize
8530
8531
8532 @itemize @bullet
8533 @item uint16x4x2_t vld2_dup_u16 (const uint16_t *)
8534 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8535 @end itemize
8536
8537
8538 @itemize @bullet
8539 @item uint8x8x2_t vld2_dup_u8 (const uint8_t *)
8540 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8541 @end itemize
8542
8543
8544 @itemize @bullet
8545 @item int32x2x2_t vld2_dup_s32 (const int32_t *)
8546 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8547 @end itemize
8548
8549
8550 @itemize @bullet
8551 @item int16x4x2_t vld2_dup_s16 (const int16_t *)
8552 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8553 @end itemize
8554
8555
8556 @itemize @bullet
8557 @item int8x8x2_t vld2_dup_s8 (const int8_t *)
8558 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8559 @end itemize
8560
8561
8562 @itemize @bullet
8563 @item float32x2x2_t vld2_dup_f32 (const float32_t *)
8564 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8565 @end itemize
8566
8567
8568 @itemize @bullet
8569 @item poly16x4x2_t vld2_dup_p16 (const poly16_t *)
8570 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8571 @end itemize
8572
8573
8574 @itemize @bullet
8575 @item poly8x8x2_t vld2_dup_p8 (const poly8_t *)
8576 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8577 @end itemize
8578
8579
8580 @itemize @bullet
8581 @item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
8582 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8583 @end itemize
8584
8585
8586 @itemize @bullet
8587 @item int64x1x2_t vld2_dup_s64 (const int64_t *)
8588 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8589 @end itemize
8590
8591
8592
8593
8594 @subsubsection Element/structure stores, VST2 variants
8595
8596 @itemize @bullet
8597 @item void vst2_u32 (uint32_t *, uint32x2x2_t)
8598 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8599 @end itemize
8600
8601
8602 @itemize @bullet
8603 @item void vst2_u16 (uint16_t *, uint16x4x2_t)
8604 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8605 @end itemize
8606
8607
8608 @itemize @bullet
8609 @item void vst2_u8 (uint8_t *, uint8x8x2_t)
8610 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8611 @end itemize
8612
8613
8614 @itemize @bullet
8615 @item void vst2_s32 (int32_t *, int32x2x2_t)
8616 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8617 @end itemize
8618
8619
8620 @itemize @bullet
8621 @item void vst2_s16 (int16_t *, int16x4x2_t)
8622 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8623 @end itemize
8624
8625
8626 @itemize @bullet
8627 @item void vst2_s8 (int8_t *, int8x8x2_t)
8628 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8629 @end itemize
8630
8631
8632 @itemize @bullet
8633 @item void vst2_f32 (float32_t *, float32x2x2_t)
8634 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8635 @end itemize
8636
8637
8638 @itemize @bullet
8639 @item void vst2_p16 (poly16_t *, poly16x4x2_t)
8640 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8641 @end itemize
8642
8643
8644 @itemize @bullet
8645 @item void vst2_p8 (poly8_t *, poly8x8x2_t)
8646 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8647 @end itemize
8648
8649
8650 @itemize @bullet
8651 @item void vst2_u64 (uint64_t *, uint64x1x2_t)
8652 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8653 @end itemize
8654
8655
8656 @itemize @bullet
8657 @item void vst2_s64 (int64_t *, int64x1x2_t)
8658 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8659 @end itemize
8660
8661
8662 @itemize @bullet
8663 @item void vst2q_u32 (uint32_t *, uint32x4x2_t)
8664 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8665 @end itemize
8666
8667
8668 @itemize @bullet
8669 @item void vst2q_u16 (uint16_t *, uint16x8x2_t)
8670 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8671 @end itemize
8672
8673
8674 @itemize @bullet
8675 @item void vst2q_u8 (uint8_t *, uint8x16x2_t)
8676 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8677 @end itemize
8678
8679
8680 @itemize @bullet
8681 @item void vst2q_s32 (int32_t *, int32x4x2_t)
8682 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8683 @end itemize
8684
8685
8686 @itemize @bullet
8687 @item void vst2q_s16 (int16_t *, int16x8x2_t)
8688 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8689 @end itemize
8690
8691
8692 @itemize @bullet
8693 @item void vst2q_s8 (int8_t *, int8x16x2_t)
8694 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8695 @end itemize
8696
8697
8698 @itemize @bullet
8699 @item void vst2q_f32 (float32_t *, float32x4x2_t)
8700 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8701 @end itemize
8702
8703
8704 @itemize @bullet
8705 @item void vst2q_p16 (poly16_t *, poly16x8x2_t)
8706 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8707 @end itemize
8708
8709
8710 @itemize @bullet
8711 @item void vst2q_p8 (poly8_t *, poly8x16x2_t)
8712 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8713 @end itemize
8714
8715
8716 @itemize @bullet
8717 @item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
8718 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8719 @end itemize
8720
8721
8722 @itemize @bullet
8723 @item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
8724 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8725 @end itemize
8726
8727
8728 @itemize @bullet
8729 @item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
8730 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8731 @end itemize
8732
8733
8734 @itemize @bullet
8735 @item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
8736 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8737 @end itemize
8738
8739
8740 @itemize @bullet
8741 @item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
8742 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8743 @end itemize
8744
8745
8746 @itemize @bullet
8747 @item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
8748 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8749 @end itemize
8750
8751
8752 @itemize @bullet
8753 @item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
8754 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8755 @end itemize
8756
8757
8758 @itemize @bullet
8759 @item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
8760 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8761 @end itemize
8762
8763
8764 @itemize @bullet
8765 @item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
8766 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8767 @end itemize
8768
8769
8770 @itemize @bullet
8771 @item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
8772 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8773 @end itemize
8774
8775
8776 @itemize @bullet
8777 @item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
8778 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8779 @end itemize
8780
8781
8782 @itemize @bullet
8783 @item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
8784 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8785 @end itemize
8786
8787
8788 @itemize @bullet
8789 @item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
8790 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8791 @end itemize
8792
8793
8794 @itemize @bullet
8795 @item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
8796 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8797 @end itemize
8798
8799
8800 @itemize @bullet
8801 @item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
8802 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8803 @end itemize
8804
8805
8806
8807
8808 @subsubsection Element/structure loads, VLD3 variants
8809
8810 @itemize @bullet
8811 @item uint32x2x3_t vld3_u32 (const uint32_t *)
8812 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8813 @end itemize
8814
8815
8816 @itemize @bullet
8817 @item uint16x4x3_t vld3_u16 (const uint16_t *)
8818 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8819 @end itemize
8820
8821
8822 @itemize @bullet
8823 @item uint8x8x3_t vld3_u8 (const uint8_t *)
8824 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8825 @end itemize
8826
8827
8828 @itemize @bullet
8829 @item int32x2x3_t vld3_s32 (const int32_t *)
8830 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8831 @end itemize
8832
8833
8834 @itemize @bullet
8835 @item int16x4x3_t vld3_s16 (const int16_t *)
8836 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8837 @end itemize
8838
8839
8840 @itemize @bullet
8841 @item int8x8x3_t vld3_s8 (const int8_t *)
8842 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8843 @end itemize
8844
8845
8846 @itemize @bullet
8847 @item float32x2x3_t vld3_f32 (const float32_t *)
8848 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8849 @end itemize
8850
8851
8852 @itemize @bullet
8853 @item poly16x4x3_t vld3_p16 (const poly16_t *)
8854 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8855 @end itemize
8856
8857
8858 @itemize @bullet
8859 @item poly8x8x3_t vld3_p8 (const poly8_t *)
8860 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8861 @end itemize
8862
8863
8864 @itemize @bullet
8865 @item uint64x1x3_t vld3_u64 (const uint64_t *)
8866 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8867 @end itemize
8868
8869
8870 @itemize @bullet
8871 @item int64x1x3_t vld3_s64 (const int64_t *)
8872 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8873 @end itemize
8874
8875
8876 @itemize @bullet
8877 @item uint32x4x3_t vld3q_u32 (const uint32_t *)
8878 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8879 @end itemize
8880
8881
8882 @itemize @bullet
8883 @item uint16x8x3_t vld3q_u16 (const uint16_t *)
8884 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8885 @end itemize
8886
8887
8888 @itemize @bullet
8889 @item uint8x16x3_t vld3q_u8 (const uint8_t *)
8890 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8891 @end itemize
8892
8893
8894 @itemize @bullet
8895 @item int32x4x3_t vld3q_s32 (const int32_t *)
8896 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8897 @end itemize
8898
8899
8900 @itemize @bullet
8901 @item int16x8x3_t vld3q_s16 (const int16_t *)
8902 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8903 @end itemize
8904
8905
8906 @itemize @bullet
8907 @item int8x16x3_t vld3q_s8 (const int8_t *)
8908 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8909 @end itemize
8910
8911
8912 @itemize @bullet
8913 @item float32x4x3_t vld3q_f32 (const float32_t *)
8914 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8915 @end itemize
8916
8917
8918 @itemize @bullet
8919 @item poly16x8x3_t vld3q_p16 (const poly16_t *)
8920 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8921 @end itemize
8922
8923
8924 @itemize @bullet
8925 @item poly8x16x3_t vld3q_p8 (const poly8_t *)
8926 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8927 @end itemize
8928
8929
8930 @itemize @bullet
8931 @item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
8932 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8933 @end itemize
8934
8935
8936 @itemize @bullet
8937 @item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
8938 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8939 @end itemize
8940
8941
8942 @itemize @bullet
8943 @item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
8944 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8945 @end itemize
8946
8947
8948 @itemize @bullet
8949 @item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
8950 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8951 @end itemize
8952
8953
8954 @itemize @bullet
8955 @item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
8956 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8957 @end itemize
8958
8959
8960 @itemize @bullet
8961 @item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
8962 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8963 @end itemize
8964
8965
8966 @itemize @bullet
8967 @item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
8968 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8969 @end itemize
8970
8971
8972 @itemize @bullet
8973 @item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
8974 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8975 @end itemize
8976
8977
8978 @itemize @bullet
8979 @item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
8980 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8981 @end itemize
8982
8983
8984 @itemize @bullet
8985 @item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
8986 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8987 @end itemize
8988
8989
8990 @itemize @bullet
8991 @item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
8992 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8993 @end itemize
8994
8995
8996 @itemize @bullet
8997 @item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
8998 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8999 @end itemize
9000
9001
9002 @itemize @bullet
9003 @item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
9004 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9005 @end itemize
9006
9007
9008 @itemize @bullet
9009 @item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
9010 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9011 @end itemize
9012
9013
9014 @itemize @bullet
9015 @item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
9016 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9017 @end itemize
9018
9019
9020 @itemize @bullet
9021 @item uint32x2x3_t vld3_dup_u32 (const uint32_t *)
9022 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9023 @end itemize
9024
9025
9026 @itemize @bullet
9027 @item uint16x4x3_t vld3_dup_u16 (const uint16_t *)
9028 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9029 @end itemize
9030
9031
9032 @itemize @bullet
9033 @item uint8x8x3_t vld3_dup_u8 (const uint8_t *)
9034 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9035 @end itemize
9036
9037
9038 @itemize @bullet
9039 @item int32x2x3_t vld3_dup_s32 (const int32_t *)
9040 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9041 @end itemize
9042
9043
9044 @itemize @bullet
9045 @item int16x4x3_t vld3_dup_s16 (const int16_t *)
9046 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9047 @end itemize
9048
9049
9050 @itemize @bullet
9051 @item int8x8x3_t vld3_dup_s8 (const int8_t *)
9052 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9053 @end itemize
9054
9055
9056 @itemize @bullet
9057 @item float32x2x3_t vld3_dup_f32 (const float32_t *)
9058 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9059 @end itemize
9060
9061
9062 @itemize @bullet
9063 @item poly16x4x3_t vld3_dup_p16 (const poly16_t *)
9064 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9065 @end itemize
9066
9067
9068 @itemize @bullet
9069 @item poly8x8x3_t vld3_dup_p8 (const poly8_t *)
9070 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9071 @end itemize
9072
9073
9074 @itemize @bullet
9075 @item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
9076 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9077 @end itemize
9078
9079
9080 @itemize @bullet
9081 @item int64x1x3_t vld3_dup_s64 (const int64_t *)
9082 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9083 @end itemize
9084
9085
9086
9087
9088 @subsubsection Element/structure stores, VST3 variants
9089
9090 @itemize @bullet
9091 @item void vst3_u32 (uint32_t *, uint32x2x3_t)
9092 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9093 @end itemize
9094
9095
9096 @itemize @bullet
9097 @item void vst3_u16 (uint16_t *, uint16x4x3_t)
9098 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9099 @end itemize
9100
9101
9102 @itemize @bullet
9103 @item void vst3_u8 (uint8_t *, uint8x8x3_t)
9104 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9105 @end itemize
9106
9107
9108 @itemize @bullet
9109 @item void vst3_s32 (int32_t *, int32x2x3_t)
9110 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9111 @end itemize
9112
9113
9114 @itemize @bullet
9115 @item void vst3_s16 (int16_t *, int16x4x3_t)
9116 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9117 @end itemize
9118
9119
9120 @itemize @bullet
9121 @item void vst3_s8 (int8_t *, int8x8x3_t)
9122 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9123 @end itemize
9124
9125
9126 @itemize @bullet
9127 @item void vst3_f32 (float32_t *, float32x2x3_t)
9128 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9129 @end itemize
9130
9131
9132 @itemize @bullet
9133 @item void vst3_p16 (poly16_t *, poly16x4x3_t)
9134 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9135 @end itemize
9136
9137
9138 @itemize @bullet
9139 @item void vst3_p8 (poly8_t *, poly8x8x3_t)
9140 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9141 @end itemize
9142
9143
9144 @itemize @bullet
9145 @item void vst3_u64 (uint64_t *, uint64x1x3_t)
9146 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9147 @end itemize
9148
9149
9150 @itemize @bullet
9151 @item void vst3_s64 (int64_t *, int64x1x3_t)
9152 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9153 @end itemize
9154
9155
9156 @itemize @bullet
9157 @item void vst3q_u32 (uint32_t *, uint32x4x3_t)
9158 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9159 @end itemize
9160
9161
9162 @itemize @bullet
9163 @item void vst3q_u16 (uint16_t *, uint16x8x3_t)
9164 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9165 @end itemize
9166
9167
9168 @itemize @bullet
9169 @item void vst3q_u8 (uint8_t *, uint8x16x3_t)
9170 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9171 @end itemize
9172
9173
9174 @itemize @bullet
9175 @item void vst3q_s32 (int32_t *, int32x4x3_t)
9176 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9177 @end itemize
9178
9179
9180 @itemize @bullet
9181 @item void vst3q_s16 (int16_t *, int16x8x3_t)
9182 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9183 @end itemize
9184
9185
9186 @itemize @bullet
9187 @item void vst3q_s8 (int8_t *, int8x16x3_t)
9188 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9189 @end itemize
9190
9191
9192 @itemize @bullet
9193 @item void vst3q_f32 (float32_t *, float32x4x3_t)
9194 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9195 @end itemize
9196
9197
9198 @itemize @bullet
9199 @item void vst3q_p16 (poly16_t *, poly16x8x3_t)
9200 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9201 @end itemize
9202
9203
9204 @itemize @bullet
9205 @item void vst3q_p8 (poly8_t *, poly8x16x3_t)
9206 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9207 @end itemize
9208
9209
9210 @itemize @bullet
9211 @item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
9212 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9213 @end itemize
9214
9215
9216 @itemize @bullet
9217 @item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
9218 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9219 @end itemize
9220
9221
9222 @itemize @bullet
9223 @item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
9224 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9225 @end itemize
9226
9227
9228 @itemize @bullet
9229 @item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
9230 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9231 @end itemize
9232
9233
9234 @itemize @bullet
9235 @item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
9236 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9237 @end itemize
9238
9239
9240 @itemize @bullet
9241 @item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
9242 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9243 @end itemize
9244
9245
9246 @itemize @bullet
9247 @item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
9248 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9249 @end itemize
9250
9251
9252 @itemize @bullet
9253 @item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
9254 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9255 @end itemize
9256
9257
9258 @itemize @bullet
9259 @item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
9260 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9261 @end itemize
9262
9263
9264 @itemize @bullet
9265 @item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
9266 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9267 @end itemize
9268
9269
9270 @itemize @bullet
9271 @item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
9272 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9273 @end itemize
9274
9275
9276 @itemize @bullet
9277 @item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
9278 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9279 @end itemize
9280
9281
9282 @itemize @bullet
9283 @item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
9284 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9285 @end itemize
9286
9287
9288 @itemize @bullet
9289 @item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
9290 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9291 @end itemize
9292
9293
9294 @itemize @bullet
9295 @item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
9296 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9297 @end itemize
9298
9299
9300
9301
9302 @subsubsection Element/structure loads, VLD4 variants
9303
9304 @itemize @bullet
9305 @item uint32x2x4_t vld4_u32 (const uint32_t *)
9306 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9307 @end itemize
9308
9309
9310 @itemize @bullet
9311 @item uint16x4x4_t vld4_u16 (const uint16_t *)
9312 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9313 @end itemize
9314
9315
9316 @itemize @bullet
9317 @item uint8x8x4_t vld4_u8 (const uint8_t *)
9318 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9319 @end itemize
9320
9321
9322 @itemize @bullet
9323 @item int32x2x4_t vld4_s32 (const int32_t *)
9324 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9325 @end itemize
9326
9327
9328 @itemize @bullet
9329 @item int16x4x4_t vld4_s16 (const int16_t *)
9330 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9331 @end itemize
9332
9333
9334 @itemize @bullet
9335 @item int8x8x4_t vld4_s8 (const int8_t *)
9336 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9337 @end itemize
9338
9339
9340 @itemize @bullet
9341 @item float32x2x4_t vld4_f32 (const float32_t *)
9342 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9343 @end itemize
9344
9345
9346 @itemize @bullet
9347 @item poly16x4x4_t vld4_p16 (const poly16_t *)
9348 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9349 @end itemize
9350
9351
9352 @itemize @bullet
9353 @item poly8x8x4_t vld4_p8 (const poly8_t *)
9354 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9355 @end itemize
9356
9357
9358 @itemize @bullet
9359 @item uint64x1x4_t vld4_u64 (const uint64_t *)
9360 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9361 @end itemize
9362
9363
9364 @itemize @bullet
9365 @item int64x1x4_t vld4_s64 (const int64_t *)
9366 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9367 @end itemize
9368
9369
9370 @itemize @bullet
9371 @item uint32x4x4_t vld4q_u32 (const uint32_t *)
9372 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9373 @end itemize
9374
9375
9376 @itemize @bullet
9377 @item uint16x8x4_t vld4q_u16 (const uint16_t *)
9378 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9379 @end itemize
9380
9381
9382 @itemize @bullet
9383 @item uint8x16x4_t vld4q_u8 (const uint8_t *)
9384 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9385 @end itemize
9386
9387
9388 @itemize @bullet
9389 @item int32x4x4_t vld4q_s32 (const int32_t *)
9390 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9391 @end itemize
9392
9393
9394 @itemize @bullet
9395 @item int16x8x4_t vld4q_s16 (const int16_t *)
9396 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9397 @end itemize
9398
9399
9400 @itemize @bullet
9401 @item int8x16x4_t vld4q_s8 (const int8_t *)
9402 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9403 @end itemize
9404
9405
9406 @itemize @bullet
9407 @item float32x4x4_t vld4q_f32 (const float32_t *)
9408 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9409 @end itemize
9410
9411
9412 @itemize @bullet
9413 @item poly16x8x4_t vld4q_p16 (const poly16_t *)
9414 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9415 @end itemize
9416
9417
9418 @itemize @bullet
9419 @item poly8x16x4_t vld4q_p8 (const poly8_t *)
9420 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9421 @end itemize
9422
9423
9424 @itemize @bullet
9425 @item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
9426 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9427 @end itemize
9428
9429
9430 @itemize @bullet
9431 @item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
9432 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9433 @end itemize
9434
9435
9436 @itemize @bullet
9437 @item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
9438 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9439 @end itemize
9440
9441
9442 @itemize @bullet
9443 @item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
9444 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9445 @end itemize
9446
9447
9448 @itemize @bullet
9449 @item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
9450 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9451 @end itemize
9452
9453
9454 @itemize @bullet
9455 @item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
9456 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9457 @end itemize
9458
9459
9460 @itemize @bullet
9461 @item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
9462 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9463 @end itemize
9464
9465
9466 @itemize @bullet
9467 @item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
9468 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9469 @end itemize
9470
9471
9472 @itemize @bullet
9473 @item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
9474 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9475 @end itemize
9476
9477
9478 @itemize @bullet
9479 @item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
9480 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9481 @end itemize
9482
9483
9484 @itemize @bullet
9485 @item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
9486 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9487 @end itemize
9488
9489
9490 @itemize @bullet
9491 @item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
9492 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9493 @end itemize
9494
9495
9496 @itemize @bullet
9497 @item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
9498 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9499 @end itemize
9500
9501
9502 @itemize @bullet
9503 @item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
9504 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9505 @end itemize
9506
9507
9508 @itemize @bullet
9509 @item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
9510 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9511 @end itemize
9512
9513
9514 @itemize @bullet
9515 @item uint32x2x4_t vld4_dup_u32 (const uint32_t *)
9516 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9517 @end itemize
9518
9519
9520 @itemize @bullet
9521 @item uint16x4x4_t vld4_dup_u16 (const uint16_t *)
9522 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9523 @end itemize
9524
9525
9526 @itemize @bullet
9527 @item uint8x8x4_t vld4_dup_u8 (const uint8_t *)
9528 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9529 @end itemize
9530
9531
9532 @itemize @bullet
9533 @item int32x2x4_t vld4_dup_s32 (const int32_t *)
9534 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9535 @end itemize
9536
9537
9538 @itemize @bullet
9539 @item int16x4x4_t vld4_dup_s16 (const int16_t *)
9540 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9541 @end itemize
9542
9543
9544 @itemize @bullet
9545 @item int8x8x4_t vld4_dup_s8 (const int8_t *)
9546 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9547 @end itemize
9548
9549
9550 @itemize @bullet
9551 @item float32x2x4_t vld4_dup_f32 (const float32_t *)
9552 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9553 @end itemize
9554
9555
9556 @itemize @bullet
9557 @item poly16x4x4_t vld4_dup_p16 (const poly16_t *)
9558 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9559 @end itemize
9560
9561
9562 @itemize @bullet
9563 @item poly8x8x4_t vld4_dup_p8 (const poly8_t *)
9564 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9565 @end itemize
9566
9567
9568 @itemize @bullet
9569 @item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
9570 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9571 @end itemize
9572
9573
9574 @itemize @bullet
9575 @item int64x1x4_t vld4_dup_s64 (const int64_t *)
9576 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9577 @end itemize
9578
9579
9580
9581
9582 @subsubsection Element/structure stores, VST4 variants
9583
9584 @itemize @bullet
9585 @item void vst4_u32 (uint32_t *, uint32x2x4_t)
9586 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9587 @end itemize
9588
9589
9590 @itemize @bullet
9591 @item void vst4_u16 (uint16_t *, uint16x4x4_t)
9592 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9593 @end itemize
9594
9595
9596 @itemize @bullet
9597 @item void vst4_u8 (uint8_t *, uint8x8x4_t)
9598 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9599 @end itemize
9600
9601
9602 @itemize @bullet
9603 @item void vst4_s32 (int32_t *, int32x2x4_t)
9604 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9605 @end itemize
9606
9607
9608 @itemize @bullet
9609 @item void vst4_s16 (int16_t *, int16x4x4_t)
9610 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9611 @end itemize
9612
9613
9614 @itemize @bullet
9615 @item void vst4_s8 (int8_t *, int8x8x4_t)
9616 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9617 @end itemize
9618
9619
9620 @itemize @bullet
9621 @item void vst4_f32 (float32_t *, float32x2x4_t)
9622 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9623 @end itemize
9624
9625
9626 @itemize @bullet
9627 @item void vst4_p16 (poly16_t *, poly16x4x4_t)
9628 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9629 @end itemize
9630
9631
9632 @itemize @bullet
9633 @item void vst4_p8 (poly8_t *, poly8x8x4_t)
9634 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9635 @end itemize
9636
9637
9638 @itemize @bullet
9639 @item void vst4_u64 (uint64_t *, uint64x1x4_t)
9640 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9641 @end itemize
9642
9643
9644 @itemize @bullet
9645 @item void vst4_s64 (int64_t *, int64x1x4_t)
9646 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9647 @end itemize
9648
9649
9650 @itemize @bullet
9651 @item void vst4q_u32 (uint32_t *, uint32x4x4_t)
9652 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9653 @end itemize
9654
9655
9656 @itemize @bullet
9657 @item void vst4q_u16 (uint16_t *, uint16x8x4_t)
9658 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9659 @end itemize
9660
9661
9662 @itemize @bullet
9663 @item void vst4q_u8 (uint8_t *, uint8x16x4_t)
9664 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9665 @end itemize
9666
9667
9668 @itemize @bullet
9669 @item void vst4q_s32 (int32_t *, int32x4x4_t)
9670 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9671 @end itemize
9672
9673
9674 @itemize @bullet
9675 @item void vst4q_s16 (int16_t *, int16x8x4_t)
9676 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9677 @end itemize
9678
9679
9680 @itemize @bullet
9681 @item void vst4q_s8 (int8_t *, int8x16x4_t)
9682 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9683 @end itemize
9684
9685
9686 @itemize @bullet
9687 @item void vst4q_f32 (float32_t *, float32x4x4_t)
9688 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9689 @end itemize
9690
9691
9692 @itemize @bullet
9693 @item void vst4q_p16 (poly16_t *, poly16x8x4_t)
9694 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9695 @end itemize
9696
9697
9698 @itemize @bullet
9699 @item void vst4q_p8 (poly8_t *, poly8x16x4_t)
9700 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9701 @end itemize
9702
9703
9704 @itemize @bullet
9705 @item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
9706 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9707 @end itemize
9708
9709
9710 @itemize @bullet
9711 @item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
9712 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9713 @end itemize
9714
9715
9716 @itemize @bullet
9717 @item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
9718 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9719 @end itemize
9720
9721
9722 @itemize @bullet
9723 @item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
9724 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9725 @end itemize
9726
9727
9728 @itemize @bullet
9729 @item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
9730 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9731 @end itemize
9732
9733
9734 @itemize @bullet
9735 @item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
9736 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9737 @end itemize
9738
9739
9740 @itemize @bullet
9741 @item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
9742 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9743 @end itemize
9744
9745
9746 @itemize @bullet
9747 @item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
9748 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9749 @end itemize
9750
9751
9752 @itemize @bullet
9753 @item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
9754 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9755 @end itemize
9756
9757
9758 @itemize @bullet
9759 @item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
9760 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9761 @end itemize
9762
9763
9764 @itemize @bullet
9765 @item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
9766 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9767 @end itemize
9768
9769
9770 @itemize @bullet
9771 @item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
9772 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9773 @end itemize
9774
9775
9776 @itemize @bullet
9777 @item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
9778 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9779 @end itemize
9780
9781
9782 @itemize @bullet
9783 @item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
9784 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9785 @end itemize
9786
9787
9788 @itemize @bullet
9789 @item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
9790 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9791 @end itemize
9792
9793
9794
9795
9796 @subsubsection Logical operations (AND)
9797
9798 @itemize @bullet
9799 @item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
9800 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9801 @end itemize
9802
9803
9804 @itemize @bullet
9805 @item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
9806 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9807 @end itemize
9808
9809
9810 @itemize @bullet
9811 @item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
9812 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9813 @end itemize
9814
9815
9816 @itemize @bullet
9817 @item int32x2_t vand_s32 (int32x2_t, int32x2_t)
9818 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9819 @end itemize
9820
9821
9822 @itemize @bullet
9823 @item int16x4_t vand_s16 (int16x4_t, int16x4_t)
9824 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9825 @end itemize
9826
9827
9828 @itemize @bullet
9829 @item int8x8_t vand_s8 (int8x8_t, int8x8_t)
9830 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9831 @end itemize
9832
9833
9834 @itemize @bullet
9835 @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
9836 @end itemize
9837
9838
9839 @itemize @bullet
9840 @item int64x1_t vand_s64 (int64x1_t, int64x1_t)
9841 @end itemize
9842
9843
9844 @itemize @bullet
9845 @item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
9846 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9847 @end itemize
9848
9849
9850 @itemize @bullet
9851 @item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
9852 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9853 @end itemize
9854
9855
9856 @itemize @bullet
9857 @item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
9858 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9859 @end itemize
9860
9861
9862 @itemize @bullet
9863 @item int32x4_t vandq_s32 (int32x4_t, int32x4_t)
9864 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9865 @end itemize
9866
9867
9868 @itemize @bullet
9869 @item int16x8_t vandq_s16 (int16x8_t, int16x8_t)
9870 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9871 @end itemize
9872
9873
9874 @itemize @bullet
9875 @item int8x16_t vandq_s8 (int8x16_t, int8x16_t)
9876 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9877 @end itemize
9878
9879
9880 @itemize @bullet
9881 @item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
9882 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9883 @end itemize
9884
9885
9886 @itemize @bullet
9887 @item int64x2_t vandq_s64 (int64x2_t, int64x2_t)
9888 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9889 @end itemize
9890
9891
9892
9893
9894 @subsubsection Logical operations (OR)
9895
9896 @itemize @bullet
9897 @item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
9898 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9899 @end itemize
9900
9901
9902 @itemize @bullet
9903 @item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
9904 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9905 @end itemize
9906
9907
9908 @itemize @bullet
9909 @item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
9910 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9911 @end itemize
9912
9913
9914 @itemize @bullet
9915 @item int32x2_t vorr_s32 (int32x2_t, int32x2_t)
9916 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9917 @end itemize
9918
9919
9920 @itemize @bullet
9921 @item int16x4_t vorr_s16 (int16x4_t, int16x4_t)
9922 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9923 @end itemize
9924
9925
9926 @itemize @bullet
9927 @item int8x8_t vorr_s8 (int8x8_t, int8x8_t)
9928 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9929 @end itemize
9930
9931
9932 @itemize @bullet
9933 @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
9934 @end itemize
9935
9936
9937 @itemize @bullet
9938 @item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
9939 @end itemize
9940
9941
9942 @itemize @bullet
9943 @item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
9944 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9945 @end itemize
9946
9947
9948 @itemize @bullet
9949 @item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
9950 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9951 @end itemize
9952
9953
9954 @itemize @bullet
9955 @item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
9956 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9957 @end itemize
9958
9959
9960 @itemize @bullet
9961 @item int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
9962 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9963 @end itemize
9964
9965
9966 @itemize @bullet
9967 @item int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
9968 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9969 @end itemize
9970
9971
9972 @itemize @bullet
9973 @item int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
9974 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9975 @end itemize
9976
9977
9978 @itemize @bullet
9979 @item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
9980 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9981 @end itemize
9982
9983
9984 @itemize @bullet
9985 @item int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
9986 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9987 @end itemize
9988
9989
9990
9991
9992 @subsubsection Logical operations (exclusive OR)
9993
9994 @itemize @bullet
9995 @item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
9996 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9997 @end itemize
9998
9999
10000 @itemize @bullet
10001 @item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
10002 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10003 @end itemize
10004
10005
10006 @itemize @bullet
10007 @item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
10008 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10009 @end itemize
10010
10011
10012 @itemize @bullet
10013 @item int32x2_t veor_s32 (int32x2_t, int32x2_t)
10014 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10015 @end itemize
10016
10017
10018 @itemize @bullet
10019 @item int16x4_t veor_s16 (int16x4_t, int16x4_t)
10020 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10021 @end itemize
10022
10023
10024 @itemize @bullet
10025 @item int8x8_t veor_s8 (int8x8_t, int8x8_t)
10026 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10027 @end itemize
10028
10029
10030 @itemize @bullet
10031 @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
10032 @end itemize
10033
10034
10035 @itemize @bullet
10036 @item int64x1_t veor_s64 (int64x1_t, int64x1_t)
10037 @end itemize
10038
10039
10040 @itemize @bullet
10041 @item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
10042 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10043 @end itemize
10044
10045
10046 @itemize @bullet
10047 @item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
10048 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10049 @end itemize
10050
10051
10052 @itemize @bullet
10053 @item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
10054 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10055 @end itemize
10056
10057
10058 @itemize @bullet
10059 @item int32x4_t veorq_s32 (int32x4_t, int32x4_t)
10060 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10061 @end itemize
10062
10063
10064 @itemize @bullet
10065 @item int16x8_t veorq_s16 (int16x8_t, int16x8_t)
10066 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10067 @end itemize
10068
10069
10070 @itemize @bullet
10071 @item int8x16_t veorq_s8 (int8x16_t, int8x16_t)
10072 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10073 @end itemize
10074
10075
10076 @itemize @bullet
10077 @item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
10078 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10079 @end itemize
10080
10081
10082 @itemize @bullet
10083 @item int64x2_t veorq_s64 (int64x2_t, int64x2_t)
10084 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10085 @end itemize
10086
10087
10088
10089
10090 @subsubsection Logical operations (AND-NOT)
10091
10092 @itemize @bullet
10093 @item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
10094 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10095 @end itemize
10096
10097
10098 @itemize @bullet
10099 @item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
10100 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10101 @end itemize
10102
10103
10104 @itemize @bullet
10105 @item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
10106 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10107 @end itemize
10108
10109
10110 @itemize @bullet
10111 @item int32x2_t vbic_s32 (int32x2_t, int32x2_t)
10112 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10113 @end itemize
10114
10115
10116 @itemize @bullet
10117 @item int16x4_t vbic_s16 (int16x4_t, int16x4_t)
10118 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10119 @end itemize
10120
10121
10122 @itemize @bullet
10123 @item int8x8_t vbic_s8 (int8x8_t, int8x8_t)
10124 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10125 @end itemize
10126
10127
10128 @itemize @bullet
10129 @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
10130 @end itemize
10131
10132
10133 @itemize @bullet
10134 @item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
10135 @end itemize
10136
10137
10138 @itemize @bullet
10139 @item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
10140 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10141 @end itemize
10142
10143
10144 @itemize @bullet
10145 @item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
10146 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10147 @end itemize
10148
10149
10150 @itemize @bullet
10151 @item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
10152 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10153 @end itemize
10154
10155
10156 @itemize @bullet
10157 @item int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
10158 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10159 @end itemize
10160
10161
10162 @itemize @bullet
10163 @item int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
10164 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10165 @end itemize
10166
10167
10168 @itemize @bullet
10169 @item int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
10170 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10171 @end itemize
10172
10173
10174 @itemize @bullet
10175 @item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
10176 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10177 @end itemize
10178
10179
10180 @itemize @bullet
10181 @item int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
10182 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10183 @end itemize
10184
10185
10186
10187
10188 @subsubsection Logical operations (OR-NOT)
10189
10190 @itemize @bullet
10191 @item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
10192 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10193 @end itemize
10194
10195
10196 @itemize @bullet
10197 @item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
10198 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10199 @end itemize
10200
10201
10202 @itemize @bullet
10203 @item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
10204 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10205 @end itemize
10206
10207
10208 @itemize @bullet
10209 @item int32x2_t vorn_s32 (int32x2_t, int32x2_t)
10210 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10211 @end itemize
10212
10213
10214 @itemize @bullet
10215 @item int16x4_t vorn_s16 (int16x4_t, int16x4_t)
10216 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10217 @end itemize
10218
10219
10220 @itemize @bullet
10221 @item int8x8_t vorn_s8 (int8x8_t, int8x8_t)
10222 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10223 @end itemize
10224
10225
10226 @itemize @bullet
10227 @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
10228 @end itemize
10229
10230
10231 @itemize @bullet
10232 @item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
10233 @end itemize
10234
10235
10236 @itemize @bullet
10237 @item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
10238 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10239 @end itemize
10240
10241
10242 @itemize @bullet
10243 @item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
10244 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10245 @end itemize
10246
10247
10248 @itemize @bullet
10249 @item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
10250 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10251 @end itemize
10252
10253
10254 @itemize @bullet
10255 @item int32x4_t vornq_s32 (int32x4_t, int32x4_t)
10256 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10257 @end itemize
10258
10259
10260 @itemize @bullet
10261 @item int16x8_t vornq_s16 (int16x8_t, int16x8_t)
10262 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10263 @end itemize
10264
10265
10266 @itemize @bullet
10267 @item int8x16_t vornq_s8 (int8x16_t, int8x16_t)
10268 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10269 @end itemize
10270
10271
10272 @itemize @bullet
10273 @item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
10274 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10275 @end itemize
10276
10277
10278 @itemize @bullet
10279 @item int64x2_t vornq_s64 (int64x2_t, int64x2_t)
10280 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10281 @end itemize
10282
10283
10284
10285
10286 @subsubsection Reinterpret casts
10287
10288 @itemize @bullet
10289 @item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
10290 @end itemize
10291
10292
10293 @itemize @bullet
10294 @item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
10295 @end itemize
10296
10297
10298 @itemize @bullet
10299 @item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
10300 @end itemize
10301
10302
10303 @itemize @bullet
10304 @item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
10305 @end itemize
10306
10307
10308 @itemize @bullet
10309 @item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
10310 @end itemize
10311
10312
10313 @itemize @bullet
10314 @item poly8x8_t vreinterpret_p8_s8 (int8x8_t)
10315 @end itemize
10316
10317
10318 @itemize @bullet
10319 @item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
10320 @end itemize
10321
10322
10323 @itemize @bullet
10324 @item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
10325 @end itemize
10326
10327
10328 @itemize @bullet
10329 @item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
10330 @end itemize
10331
10332
10333 @itemize @bullet
10334 @item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
10335 @end itemize
10336
10337
10338 @itemize @bullet
10339 @item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
10340 @end itemize
10341
10342
10343 @itemize @bullet
10344 @item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
10345 @end itemize
10346
10347
10348 @itemize @bullet
10349 @item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
10350 @end itemize
10351
10352
10353 @itemize @bullet
10354 @item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
10355 @end itemize
10356
10357
10358 @itemize @bullet
10359 @item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
10360 @end itemize
10361
10362
10363 @itemize @bullet
10364 @item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
10365 @end itemize
10366
10367
10368 @itemize @bullet
10369 @item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
10370 @end itemize
10371
10372
10373 @itemize @bullet
10374 @item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
10375 @end itemize
10376
10377
10378 @itemize @bullet
10379 @item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
10380 @end itemize
10381
10382
10383 @itemize @bullet
10384 @item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
10385 @end itemize
10386
10387
10388 @itemize @bullet
10389 @item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
10390 @end itemize
10391
10392
10393 @itemize @bullet
10394 @item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
10395 @end itemize
10396
10397
10398 @itemize @bullet
10399 @item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
10400 @end itemize
10401
10402
10403 @itemize @bullet
10404 @item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
10405 @end itemize
10406
10407
10408 @itemize @bullet
10409 @item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
10410 @end itemize
10411
10412
10413 @itemize @bullet
10414 @item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
10415 @end itemize
10416
10417
10418 @itemize @bullet
10419 @item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
10420 @end itemize
10421
10422
10423 @itemize @bullet
10424 @item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
10425 @end itemize
10426
10427
10428 @itemize @bullet
10429 @item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
10430 @end itemize
10431
10432
10433 @itemize @bullet
10434 @item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
10435 @end itemize
10436
10437
10438 @itemize @bullet
10439 @item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
10440 @end itemize
10441
10442
10443 @itemize @bullet
10444 @item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
10445 @end itemize
10446
10447
10448 @itemize @bullet
10449 @item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
10450 @end itemize
10451
10452
10453 @itemize @bullet
10454 @item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
10455 @end itemize
10456
10457
10458 @itemize @bullet
10459 @item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
10460 @end itemize
10461
10462
10463 @itemize @bullet
10464 @item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
10465 @end itemize
10466
10467
10468 @itemize @bullet
10469 @item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
10470 @end itemize
10471
10472
10473 @itemize @bullet
10474 @item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
10475 @end itemize
10476
10477
10478 @itemize @bullet
10479 @item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
10480 @end itemize
10481
10482
10483 @itemize @bullet
10484 @item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
10485 @end itemize
10486
10487
10488 @itemize @bullet
10489 @item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
10490 @end itemize
10491
10492
10493 @itemize @bullet
10494 @item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
10495 @end itemize
10496
10497
10498 @itemize @bullet
10499 @item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
10500 @end itemize
10501
10502
10503 @itemize @bullet
10504 @item float32x2_t vreinterpret_f32_s32 (int32x2_t)
10505 @end itemize
10506
10507
10508 @itemize @bullet
10509 @item float32x2_t vreinterpret_f32_s16 (int16x4_t)
10510 @end itemize
10511
10512
10513 @itemize @bullet
10514 @item float32x2_t vreinterpret_f32_s8 (int8x8_t)
10515 @end itemize
10516
10517
10518 @itemize @bullet
10519 @item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
10520 @end itemize
10521
10522
10523 @itemize @bullet
10524 @item float32x2_t vreinterpret_f32_s64 (int64x1_t)
10525 @end itemize
10526
10527
10528 @itemize @bullet
10529 @item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
10530 @end itemize
10531
10532
10533 @itemize @bullet
10534 @item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
10535 @end itemize
10536
10537
10538 @itemize @bullet
10539 @item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
10540 @end itemize
10541
10542
10543 @itemize @bullet
10544 @item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
10545 @end itemize
10546
10547
10548 @itemize @bullet
10549 @item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
10550 @end itemize
10551
10552
10553 @itemize @bullet
10554 @item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
10555 @end itemize
10556
10557
10558 @itemize @bullet
10559 @item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
10560 @end itemize
10561
10562
10563 @itemize @bullet
10564 @item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
10565 @end itemize
10566
10567
10568 @itemize @bullet
10569 @item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
10570 @end itemize
10571
10572
10573 @itemize @bullet
10574 @item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
10575 @end itemize
10576
10577
10578 @itemize @bullet
10579 @item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
10580 @end itemize
10581
10582
10583 @itemize @bullet
10584 @item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
10585 @end itemize
10586
10587
10588 @itemize @bullet
10589 @item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
10590 @end itemize
10591
10592
10593 @itemize @bullet
10594 @item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
10595 @end itemize
10596
10597
10598 @itemize @bullet
10599 @item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
10600 @end itemize
10601
10602
10603 @itemize @bullet
10604 @item int64x1_t vreinterpret_s64_s32 (int32x2_t)
10605 @end itemize
10606
10607
10608 @itemize @bullet
10609 @item int64x1_t vreinterpret_s64_s16 (int16x4_t)
10610 @end itemize
10611
10612
10613 @itemize @bullet
10614 @item int64x1_t vreinterpret_s64_s8 (int8x8_t)
10615 @end itemize
10616
10617
10618 @itemize @bullet
10619 @item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
10620 @end itemize
10621
10622
10623 @itemize @bullet
10624 @item int64x1_t vreinterpret_s64_f32 (float32x2_t)
10625 @end itemize
10626
10627
10628 @itemize @bullet
10629 @item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
10630 @end itemize
10631
10632
10633 @itemize @bullet
10634 @item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
10635 @end itemize
10636
10637
10638 @itemize @bullet
10639 @item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
10640 @end itemize
10641
10642
10643 @itemize @bullet
10644 @item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
10645 @end itemize
10646
10647
10648 @itemize @bullet
10649 @item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
10650 @end itemize
10651
10652
10653 @itemize @bullet
10654 @item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
10655 @end itemize
10656
10657
10658 @itemize @bullet
10659 @item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
10660 @end itemize
10661
10662
10663 @itemize @bullet
10664 @item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
10665 @end itemize
10666
10667
10668 @itemize @bullet
10669 @item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
10670 @end itemize
10671
10672
10673 @itemize @bullet
10674 @item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
10675 @end itemize
10676
10677
10678 @itemize @bullet
10679 @item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
10680 @end itemize
10681
10682
10683 @itemize @bullet
10684 @item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
10685 @end itemize
10686
10687
10688 @itemize @bullet
10689 @item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
10690 @end itemize
10691
10692
10693 @itemize @bullet
10694 @item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
10695 @end itemize
10696
10697
10698 @itemize @bullet
10699 @item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
10700 @end itemize
10701
10702
10703 @itemize @bullet
10704 @item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
10705 @end itemize
10706
10707
10708 @itemize @bullet
10709 @item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
10710 @end itemize
10711
10712
10713 @itemize @bullet
10714 @item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
10715 @end itemize
10716
10717
10718 @itemize @bullet
10719 @item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
10720 @end itemize
10721
10722
10723 @itemize @bullet
10724 @item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
10725 @end itemize
10726
10727
10728 @itemize @bullet
10729 @item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
10730 @end itemize
10731
10732
10733 @itemize @bullet
10734 @item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
10735 @end itemize
10736
10737
10738 @itemize @bullet
10739 @item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
10740 @end itemize
10741
10742
10743 @itemize @bullet
10744 @item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
10745 @end itemize
10746
10747
10748 @itemize @bullet
10749 @item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
10750 @end itemize
10751
10752
10753 @itemize @bullet
10754 @item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
10755 @end itemize
10756
10757
10758 @itemize @bullet
10759 @item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
10760 @end itemize
10761
10762
10763 @itemize @bullet
10764 @item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
10765 @end itemize
10766
10767
10768 @itemize @bullet
10769 @item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
10770 @end itemize
10771
10772
10773 @itemize @bullet
10774 @item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
10775 @end itemize
10776
10777
10778 @itemize @bullet
10779 @item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
10780 @end itemize
10781
10782
10783 @itemize @bullet
10784 @item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
10785 @end itemize
10786
10787
10788 @itemize @bullet
10789 @item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
10790 @end itemize
10791
10792
10793 @itemize @bullet
10794 @item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
10795 @end itemize
10796
10797
10798 @itemize @bullet
10799 @item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
10800 @end itemize
10801
10802
10803 @itemize @bullet
10804 @item int8x8_t vreinterpret_s8_s32 (int32x2_t)
10805 @end itemize
10806
10807
10808 @itemize @bullet
10809 @item int8x8_t vreinterpret_s8_s16 (int16x4_t)
10810 @end itemize
10811
10812
10813 @itemize @bullet
10814 @item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
10815 @end itemize
10816
10817
10818 @itemize @bullet
10819 @item int8x8_t vreinterpret_s8_s64 (int64x1_t)
10820 @end itemize
10821
10822
10823 @itemize @bullet
10824 @item int8x8_t vreinterpret_s8_f32 (float32x2_t)
10825 @end itemize
10826
10827
10828 @itemize @bullet
10829 @item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
10830 @end itemize
10831
10832
10833 @itemize @bullet
10834 @item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
10835 @end itemize
10836
10837
10838 @itemize @bullet
10839 @item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
10840 @end itemize
10841
10842
10843 @itemize @bullet
10844 @item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
10845 @end itemize
10846
10847
10848 @itemize @bullet
10849 @item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
10850 @end itemize
10851
10852
10853 @itemize @bullet
10854 @item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
10855 @end itemize
10856
10857
10858 @itemize @bullet
10859 @item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
10860 @end itemize
10861
10862
10863 @itemize @bullet
10864 @item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
10865 @end itemize
10866
10867
10868 @itemize @bullet
10869 @item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
10870 @end itemize
10871
10872
10873 @itemize @bullet
10874 @item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
10875 @end itemize
10876
10877
10878 @itemize @bullet
10879 @item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
10880 @end itemize
10881
10882
10883 @itemize @bullet
10884 @item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
10885 @end itemize
10886
10887
10888 @itemize @bullet
10889 @item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
10890 @end itemize
10891
10892
10893 @itemize @bullet
10894 @item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
10895 @end itemize
10896
10897
10898 @itemize @bullet
10899 @item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
10900 @end itemize
10901
10902
10903 @itemize @bullet
10904 @item int16x4_t vreinterpret_s16_s32 (int32x2_t)
10905 @end itemize
10906
10907
10908 @itemize @bullet
10909 @item int16x4_t vreinterpret_s16_s8 (int8x8_t)
10910 @end itemize
10911
10912
10913 @itemize @bullet
10914 @item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
10915 @end itemize
10916
10917
10918 @itemize @bullet
10919 @item int16x4_t vreinterpret_s16_s64 (int64x1_t)
10920 @end itemize
10921
10922
10923 @itemize @bullet
10924 @item int16x4_t vreinterpret_s16_f32 (float32x2_t)
10925 @end itemize
10926
10927
10928 @itemize @bullet
10929 @item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
10930 @end itemize
10931
10932
10933 @itemize @bullet
10934 @item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
10935 @end itemize
10936
10937
10938 @itemize @bullet
10939 @item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
10940 @end itemize
10941
10942
10943 @itemize @bullet
10944 @item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
10945 @end itemize
10946
10947
10948 @itemize @bullet
10949 @item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
10950 @end itemize
10951
10952
10953 @itemize @bullet
10954 @item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
10955 @end itemize
10956
10957
10958 @itemize @bullet
10959 @item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
10960 @end itemize
10961
10962
10963 @itemize @bullet
10964 @item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
10965 @end itemize
10966
10967
10968 @itemize @bullet
10969 @item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
10970 @end itemize
10971
10972
10973 @itemize @bullet
10974 @item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
10975 @end itemize
10976
10977
10978 @itemize @bullet
10979 @item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
10980 @end itemize
10981
10982
10983 @itemize @bullet
10984 @item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
10985 @end itemize
10986
10987
10988 @itemize @bullet
10989 @item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
10990 @end itemize
10991
10992
10993 @itemize @bullet
10994 @item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
10995 @end itemize
10996
10997
10998 @itemize @bullet
10999 @item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
11000 @end itemize
11001
11002
11003 @itemize @bullet
11004 @item int32x2_t vreinterpret_s32_s16 (int16x4_t)
11005 @end itemize
11006
11007
11008 @itemize @bullet
11009 @item int32x2_t vreinterpret_s32_s8 (int8x8_t)
11010 @end itemize
11011
11012
11013 @itemize @bullet
11014 @item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
11015 @end itemize
11016
11017
11018 @itemize @bullet
11019 @item int32x2_t vreinterpret_s32_s64 (int64x1_t)
11020 @end itemize
11021
11022
11023 @itemize @bullet
11024 @item int32x2_t vreinterpret_s32_f32 (float32x2_t)
11025 @end itemize
11026
11027
11028 @itemize @bullet
11029 @item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
11030 @end itemize
11031
11032
11033 @itemize @bullet
11034 @item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
11035 @end itemize
11036
11037
11038 @itemize @bullet
11039 @item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
11040 @end itemize
11041
11042
11043 @itemize @bullet
11044 @item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
11045 @end itemize
11046
11047
11048 @itemize @bullet
11049 @item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
11050 @end itemize
11051
11052
11053 @itemize @bullet
11054 @item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
11055 @end itemize
11056
11057
11058 @itemize @bullet
11059 @item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
11060 @end itemize
11061
11062
11063 @itemize @bullet
11064 @item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
11065 @end itemize
11066
11067
11068 @itemize @bullet
11069 @item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
11070 @end itemize
11071
11072
11073 @itemize @bullet
11074 @item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
11075 @end itemize
11076
11077
11078 @itemize @bullet
11079 @item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
11080 @end itemize
11081
11082
11083 @itemize @bullet
11084 @item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
11085 @end itemize
11086
11087
11088 @itemize @bullet
11089 @item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
11090 @end itemize
11091
11092
11093 @itemize @bullet
11094 @item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
11095 @end itemize
11096
11097
11098 @itemize @bullet
11099 @item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
11100 @end itemize
11101
11102
11103 @itemize @bullet
11104 @item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
11105 @end itemize
11106
11107
11108 @itemize @bullet
11109 @item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
11110 @end itemize
11111
11112
11113 @itemize @bullet
11114 @item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
11115 @end itemize
11116
11117
11118 @itemize @bullet
11119 @item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
11120 @end itemize
11121
11122
11123 @itemize @bullet
11124 @item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
11125 @end itemize
11126
11127
11128 @itemize @bullet
11129 @item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
11130 @end itemize
11131
11132
11133 @itemize @bullet
11134 @item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
11135 @end itemize
11136
11137
11138 @itemize @bullet
11139 @item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
11140 @end itemize
11141
11142
11143 @itemize @bullet
11144 @item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
11145 @end itemize
11146
11147
11148 @itemize @bullet
11149 @item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
11150 @end itemize
11151
11152
11153 @itemize @bullet
11154 @item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
11155 @end itemize
11156
11157
11158 @itemize @bullet
11159 @item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
11160 @end itemize
11161
11162
11163 @itemize @bullet
11164 @item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
11165 @end itemize
11166
11167
11168 @itemize @bullet
11169 @item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
11170 @end itemize
11171
11172
11173 @itemize @bullet
11174 @item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
11175 @end itemize
11176
11177
11178 @itemize @bullet
11179 @item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
11180 @end itemize
11181
11182
11183 @itemize @bullet
11184 @item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
11185 @end itemize
11186
11187
11188 @itemize @bullet
11189 @item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
11190 @end itemize
11191
11192
11193 @itemize @bullet
11194 @item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
11195 @end itemize
11196
11197
11198 @itemize @bullet
11199 @item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
11200 @end itemize
11201
11202
11203 @itemize @bullet
11204 @item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
11205 @end itemize
11206
11207
11208 @itemize @bullet
11209 @item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
11210 @end itemize
11211
11212
11213 @itemize @bullet
11214 @item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
11215 @end itemize
11216
11217
11218 @itemize @bullet
11219 @item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
11220 @end itemize
11221
11222
11223 @itemize @bullet
11224 @item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
11225 @end itemize
11226
11227
11228 @itemize @bullet
11229 @item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
11230 @end itemize
11231
11232
11233 @itemize @bullet
11234 @item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
11235 @end itemize
11236
11237
11238 @itemize @bullet
11239 @item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
11240 @end itemize
11241
11242
11243 @itemize @bullet
11244 @item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
11245 @end itemize
11246
11247
11248 @itemize @bullet
11249 @item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
11250 @end itemize
11251
11252
11253 @itemize @bullet
11254 @item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
11255 @end itemize
11256
11257
11258 @itemize @bullet
11259 @item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
11260 @end itemize
11261
11262
11263 @itemize @bullet
11264 @item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
11265 @end itemize
11266
11267
11268 @itemize @bullet
11269 @item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
11270 @end itemize
11271
11272
11273 @itemize @bullet
11274 @item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
11275 @end itemize
11276
11277
11278 @itemize @bullet
11279 @item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
11280 @end itemize
11281
11282
11283 @itemize @bullet
11284 @item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
11285 @end itemize
11286
11287
11288 @itemize @bullet
11289 @item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
11290 @end itemize
11291
11292
11293 @itemize @bullet
11294 @item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
11295 @end itemize
11296
11297
11298 @itemize @bullet
11299 @item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
11300 @end itemize
11301
11302
11303 @itemize @bullet
11304 @item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
11305 @end itemize
11306
11307
11308 @itemize @bullet
11309 @item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
11310 @end itemize
11311
11312
11313 @itemize @bullet
11314 @item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
11315 @end itemize
11316
11317
11318 @itemize @bullet
11319 @item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
11320 @end itemize
11321
11322
11323 @itemize @bullet
11324 @item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
11325 @end itemize
11326
11327
11328 @itemize @bullet
11329 @item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
11330 @end itemize
11331
11332
11333 @itemize @bullet
11334 @item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
11335 @end itemize
11336
11337
11338 @itemize @bullet
11339 @item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
11340 @end itemize
11341
11342
11343 @itemize @bullet
11344 @item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
11345 @end itemize
11346
11347
11348 @itemize @bullet
11349 @item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
11350 @end itemize
11351
11352
11353 @itemize @bullet
11354 @item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
11355 @end itemize
11356
11357
11358 @itemize @bullet
11359 @item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
11360 @end itemize
11361
11362
11363 @itemize @bullet
11364 @item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
11365 @end itemize
11366
11367
11368 @itemize @bullet
11369 @item uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
11370 @end itemize
11371
11372
11373 @itemize @bullet
11374 @item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
11375 @end itemize
11376
11377
11378 @itemize @bullet
11379 @item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
11380 @end itemize
11381
11382
11383 @itemize @bullet
11384 @item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
11385 @end itemize
11386
11387
11388
11389