1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
32 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 #include "insn-config.h"
45 #ifndef REGISTER_MOVE_COST
46 #define REGISTER_MOVE_COST(m, x, y) 2
49 static void init_reg_sets_1
PARAMS ((void));
50 static void init_reg_modes
PARAMS ((void));
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set
;
75 /* Data for initializing the above. */
77 static const char initial_fixed_regs
[] = FIXED_REGISTERS
;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set
;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set
;
94 /* Data for initializing the above. */
96 static const char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
98 /* This is much like call_used_regs, except it doesn't have to
99 be a superset of FIXED_REGISTERS. This vector indicates
100 what is really call clobbered, and is used when defining
101 regs_invalidated_by_call. */
103 #ifdef CALL_REALLY_USED_REGISTERS
104 char call_really_used_regs
[] = CALL_REALLY_USED_REGISTERS
;
107 /* Indexed by hard register number, contains 1 for registers that are
108 fixed use or call used registers that cannot hold quantities across
109 calls even if we are willing to save and restore them. call fixed
110 registers are a subset of call used registers. */
112 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
114 /* The same info as a HARD_REG_SET. */
116 HARD_REG_SET call_fixed_reg_set
;
118 /* Number of non-fixed registers. */
120 int n_non_fixed_regs
;
122 /* Indexed by hard register number, contains 1 for registers
123 that are being used for global register decls.
124 These must be exempt from ordinary flow analysis
125 and are also considered fixed. */
127 char global_regs
[FIRST_PSEUDO_REGISTER
];
129 /* Contains 1 for registers that are set or clobbered by calls. */
130 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
131 for someone's bright idea to have call_used_regs strictly include
132 fixed_regs. Which leaves us guessing as to the set of fixed_regs
133 that are actually preserved. We know for sure that those associated
134 with the local stack frame are safe, but scant others. */
136 HARD_REG_SET regs_invalidated_by_call
;
138 /* Table of register numbers in the order in which to try to use them. */
139 #ifdef REG_ALLOC_ORDER
140 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
142 /* The inverse of reg_alloc_order. */
143 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
146 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
148 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
150 /* The same information, but as an array of unsigned ints. We copy from
151 these unsigned ints to the table above. We do this so the tm.h files
152 do not have to be aware of the wordsize for machines with <= 64 regs.
153 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
156 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
158 static const unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
159 = REG_CLASS_CONTENTS
;
161 /* For each reg class, number of regs it contains. */
163 unsigned int reg_class_size
[N_REG_CLASSES
];
165 /* For each reg class, table listing all the containing classes. */
167 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
169 /* For each reg class, table listing all the classes contained in it. */
171 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
173 /* For each pair of reg classes,
174 a largest reg class contained in their union. */
176 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
178 /* For each pair of reg classes,
179 the smallest reg class containing their union. */
181 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
183 /* Array containing all of the register names. Unless
184 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
186 #ifdef DEBUG_REGISTER_NAMES
187 const char * reg_names
[] = REGISTER_NAMES
;
190 /* For each hard register, the widest mode object that it can contain.
191 This will be a MODE_INT mode if the register can hold integers. Otherwise
192 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
195 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
197 /* 1 if class does contain register of given mode. */
199 static char contains_reg_of_mode
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
201 /* Maximum cost of moving from a register in one class to a register in
202 another class. Based on REGISTER_MOVE_COST. */
204 static int move_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
206 /* Similar, but here we don't have to move if the first index is a subset
207 of the second so in that case the cost is zero. */
209 static int may_move_in_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
211 /* Similar, but here we don't have to move if the first index is a superset
212 of the second so in that case the cost is zero. */
214 static int may_move_out_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
216 #ifdef FORBIDDEN_INC_DEC_CLASSES
218 /* These are the classes that regs which are auto-incremented or decremented
221 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
223 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
226 static char *in_inc_dec
;
228 #endif /* FORBIDDEN_INC_DEC_CLASSES */
230 #ifdef CLASS_CANNOT_CHANGE_MODE
232 /* These are the classes containing only registers that can be used in
233 a SUBREG expression that changes the mode of the register in some
234 way that is illegal. */
236 static int class_can_change_mode
[N_REG_CLASSES
];
238 /* Registers, including pseudos, which change modes in some way that
241 static regset reg_changes_mode
;
243 #endif /* CLASS_CANNOT_CHANGE_MODE */
245 /* Sample MEM values for use by memory_move_secondary_cost. */
247 static GTY(()) rtx top_of_stack
[MAX_MACHINE_MODE
];
249 /* Linked list of reg_info structures allocated for reg_n_info array.
250 Grouping all of the allocated structures together in one lump
251 means only one call to bzero to clear them, rather than n smaller
253 struct reg_info_data
{
254 struct reg_info_data
*next
; /* next set of reg_info structures */
255 size_t min_index
; /* minimum index # */
256 size_t max_index
; /* maximum index # */
257 char used_p
; /* nonzero if this has been used previously */
258 reg_info data
[1]; /* beginning of the reg_info data */
261 static struct reg_info_data
*reg_info_head
;
263 /* No more global register variables may be declared; true once
264 regclass has been initialized. */
266 static int no_global_reg_vars
= 0;
269 /* Function called only once to initialize the above data on reg usage.
270 Once this is done, various switches may override. */
277 /* First copy the register information from the initial int form into
280 for (i
= 0; i
< N_REG_CLASSES
; i
++)
282 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
284 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
285 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
286 if (int_reg_class_contents
[i
][j
/ 32]
287 & ((unsigned) 1 << (j
% 32)))
288 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
291 memcpy (fixed_regs
, initial_fixed_regs
, sizeof fixed_regs
);
292 memcpy (call_used_regs
, initial_call_used_regs
, sizeof call_used_regs
);
293 memset (global_regs
, 0, sizeof global_regs
);
295 /* Do any additional initialization regsets may need */
296 INIT_ONCE_REG_SET ();
298 #ifdef REG_ALLOC_ORDER
299 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
300 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
304 /* After switches have been processed, which perhaps alter
305 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
311 unsigned int /* enum machine_mode */ m
;
312 char allocatable_regs_of_mode
[MAX_MACHINE_MODE
];
314 /* This macro allows the fixed or call-used registers
315 and the register classes to depend on target flags. */
317 #ifdef CONDITIONAL_REGISTER_USAGE
318 CONDITIONAL_REGISTER_USAGE
;
321 /* Compute number of hard regs in each class. */
323 memset ((char *) reg_class_size
, 0, sizeof reg_class_size
);
324 for (i
= 0; i
< N_REG_CLASSES
; i
++)
325 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
326 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
329 /* Initialize the table of subunions.
330 reg_class_subunion[I][J] gets the largest-numbered reg-class
331 that is contained in the union of classes I and J. */
333 for (i
= 0; i
< N_REG_CLASSES
; i
++)
335 for (j
= 0; j
< N_REG_CLASSES
; j
++)
338 register /* Declare it register if it's a scalar. */
343 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
344 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
345 for (k
= 0; k
< N_REG_CLASSES
; k
++)
347 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
352 /* keep the largest subclass */ /* SPEE 900308 */
353 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
354 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
356 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
363 /* Initialize the table of superunions.
364 reg_class_superunion[I][J] gets the smallest-numbered reg-class
365 containing the union of classes I and J. */
367 for (i
= 0; i
< N_REG_CLASSES
; i
++)
369 for (j
= 0; j
< N_REG_CLASSES
; j
++)
372 register /* Declare it register if it's a scalar. */
377 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
378 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
379 for (k
= 0; k
< N_REG_CLASSES
; k
++)
380 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
383 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
387 /* Initialize the tables of subclasses and superclasses of each reg class.
388 First clear the whole table, then add the elements as they are found. */
390 for (i
= 0; i
< N_REG_CLASSES
; i
++)
392 for (j
= 0; j
< N_REG_CLASSES
; j
++)
394 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
395 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
399 for (i
= 0; i
< N_REG_CLASSES
; i
++)
401 if (i
== (int) NO_REGS
)
404 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
408 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
412 /* Reg class I is a subclass of J.
413 Add J to the table of superclasses of I. */
414 p
= ®_class_superclasses
[i
][0];
415 while (*p
!= LIM_REG_CLASSES
) p
++;
416 *p
= (enum reg_class
) j
;
417 /* Add I to the table of superclasses of J. */
418 p
= ®_class_subclasses
[j
][0];
419 while (*p
!= LIM_REG_CLASSES
) p
++;
420 *p
= (enum reg_class
) i
;
424 /* Initialize "constant" tables. */
426 CLEAR_HARD_REG_SET (fixed_reg_set
);
427 CLEAR_HARD_REG_SET (call_used_reg_set
);
428 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
429 CLEAR_HARD_REG_SET (regs_invalidated_by_call
);
431 memcpy (call_fixed_regs
, fixed_regs
, sizeof call_fixed_regs
);
433 n_non_fixed_regs
= 0;
435 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
438 SET_HARD_REG_BIT (fixed_reg_set
, i
);
442 if (call_used_regs
[i
])
443 SET_HARD_REG_BIT (call_used_reg_set
, i
);
444 if (call_fixed_regs
[i
])
445 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
446 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
447 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
449 /* There are a couple of fixed registers that we know are safe to
450 exclude from being clobbered by calls:
452 The frame pointer is always preserved across calls. The arg pointer
453 is if it is fixed. The stack pointer usually is, unless
454 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
455 If we are generating PIC code, the PIC offset table register is
456 preserved across calls, though the target can override that. */
458 if (i
== STACK_POINTER_REGNUM
|| i
== FRAME_POINTER_REGNUM
)
460 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
461 else if (i
== HARD_FRAME_POINTER_REGNUM
)
464 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
465 else if (i
== ARG_POINTER_REGNUM
&& fixed_regs
[i
])
468 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
469 else if (i
== PIC_OFFSET_TABLE_REGNUM
&& fixed_regs
[i
])
473 #ifdef CALL_REALLY_USED_REGISTERS
474 || call_really_used_regs
[i
]
479 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
482 memset (contains_reg_of_mode
, 0, sizeof (contains_reg_of_mode
));
483 memset (allocatable_regs_of_mode
, 0, sizeof (allocatable_regs_of_mode
));
484 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
485 for (i
= 0; i
< N_REG_CLASSES
; i
++)
486 if ((unsigned) CLASS_MAX_NREGS (i
, m
) <= reg_class_size
[i
])
487 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
488 if (!fixed_regs
[j
] && TEST_HARD_REG_BIT (reg_class_contents
[i
], j
)
489 && HARD_REGNO_MODE_OK (j
, m
))
491 contains_reg_of_mode
[i
][m
] = 1;
492 allocatable_regs_of_mode
[m
] = 1;
496 /* Initialize the move cost table. Find every subset of each class
497 and take the maximum cost of moving any subset to any other. */
499 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
500 if (allocatable_regs_of_mode
[m
])
502 for (i
= 0; i
< N_REG_CLASSES
; i
++)
503 if (contains_reg_of_mode
[i
][m
])
504 for (j
= 0; j
< N_REG_CLASSES
; j
++)
507 enum reg_class
*p1
, *p2
;
509 if (!contains_reg_of_mode
[j
][m
])
511 move_cost
[m
][i
][j
] = 65536;
512 may_move_in_cost
[m
][i
][j
] = 65536;
513 may_move_out_cost
[m
][i
][j
] = 65536;
517 cost
= REGISTER_MOVE_COST (m
, i
, j
);
519 for (p2
= ®_class_subclasses
[j
][0];
520 *p2
!= LIM_REG_CLASSES
;
522 if (*p2
!= i
&& contains_reg_of_mode
[*p2
][m
])
523 cost
= MAX (cost
, move_cost
[m
][i
][*p2
]);
525 for (p1
= ®_class_subclasses
[i
][0];
526 *p1
!= LIM_REG_CLASSES
;
528 if (*p1
!= j
&& contains_reg_of_mode
[*p1
][m
])
529 cost
= MAX (cost
, move_cost
[m
][*p1
][j
]);
531 move_cost
[m
][i
][j
] = cost
;
533 if (reg_class_subset_p (i
, j
))
534 may_move_in_cost
[m
][i
][j
] = 0;
536 may_move_in_cost
[m
][i
][j
] = cost
;
538 if (reg_class_subset_p (j
, i
))
539 may_move_out_cost
[m
][i
][j
] = 0;
541 may_move_out_cost
[m
][i
][j
] = cost
;
545 for (j
= 0; j
< N_REG_CLASSES
; j
++)
547 move_cost
[m
][i
][j
] = 65536;
548 may_move_in_cost
[m
][i
][j
] = 65536;
549 may_move_out_cost
[m
][i
][j
] = 65536;
553 #ifdef CLASS_CANNOT_CHANGE_MODE
556 COMPL_HARD_REG_SET (c
, reg_class_contents
[CLASS_CANNOT_CHANGE_MODE
]);
558 for (i
= 0; i
< N_REG_CLASSES
; i
++)
560 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], c
, ok_class
);
561 class_can_change_mode
[i
] = 0;
564 class_can_change_mode
[i
] = 1;
567 #endif /* CLASS_CANNOT_CHANGE_MODE */
570 /* Compute the table of register modes.
571 These values are used to record death information for individual registers
572 (as opposed to a multi-register mode). */
579 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
581 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1);
583 /* If we couldn't find a valid mode, just use the previous mode.
584 ??? One situation in which we need to do this is on the mips where
585 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
586 to use DF mode for the even registers and VOIDmode for the odd
587 (for the cpu models where the odd ones are inaccessible). */
588 if (reg_raw_mode
[i
] == VOIDmode
)
589 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
593 /* Finish initializing the register sets and
594 initialize the register modes. */
599 /* This finishes what was started by init_reg_sets, but couldn't be done
600 until after register usage was specified. */
606 /* Initialize some fake stack-frame MEM references for use in
607 memory_move_secondary_cost. */
610 init_fake_stack_mems ()
612 #ifdef HAVE_SECONDARY_RELOADS
616 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
617 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
622 #ifdef HAVE_SECONDARY_RELOADS
624 /* Compute extra cost of moving registers to/from memory due to reloads.
625 Only needed if secondary reloads are required for memory moves. */
628 memory_move_secondary_cost (mode
, class, in
)
629 enum machine_mode mode
;
630 enum reg_class
class;
633 enum reg_class altclass
;
634 int partial_cost
= 0;
635 /* We need a memory reference to feed to SECONDARY... macros. */
636 /* mem may be unused even if the SECONDARY_ macros are defined. */
637 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
642 #ifdef SECONDARY_INPUT_RELOAD_CLASS
643 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
650 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
651 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
657 if (altclass
== NO_REGS
)
661 partial_cost
= REGISTER_MOVE_COST (mode
, altclass
, class);
663 partial_cost
= REGISTER_MOVE_COST (mode
, class, altclass
);
665 if (class == altclass
)
666 /* This isn't simply a copy-to-temporary situation. Can't guess
667 what it is, so MEMORY_MOVE_COST really ought not to be calling
670 I'm tempted to put in an abort here, but returning this will
671 probably only give poor estimates, which is what we would've
672 had before this code anyways. */
675 /* Check if the secondary reload register will also need a
677 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
681 /* Return a machine mode that is legitimate for hard reg REGNO and large
682 enough to save nregs. If we can't find one, return VOIDmode. */
685 choose_hard_reg_mode (regno
, nregs
)
686 unsigned int regno ATTRIBUTE_UNUSED
;
689 unsigned int /* enum machine_mode */ m
;
690 enum machine_mode found_mode
= VOIDmode
, mode
;
692 /* We first look for the largest integer mode that can be validly
693 held in REGNO. If none, we look for the largest floating-point mode.
694 If we still didn't find a valid mode, try CCmode. */
696 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
698 mode
= GET_MODE_WIDER_MODE (mode
))
699 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
700 && HARD_REGNO_MODE_OK (regno
, mode
))
703 if (found_mode
!= VOIDmode
)
706 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
708 mode
= GET_MODE_WIDER_MODE (mode
))
709 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
710 && HARD_REGNO_MODE_OK (regno
, mode
))
713 if (found_mode
!= VOIDmode
)
716 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT
);
718 mode
= GET_MODE_WIDER_MODE (mode
))
719 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
720 && HARD_REGNO_MODE_OK (regno
, mode
))
723 if (found_mode
!= VOIDmode
)
726 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT
);
728 mode
= GET_MODE_WIDER_MODE (mode
))
729 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
730 && HARD_REGNO_MODE_OK (regno
, mode
))
733 if (found_mode
!= VOIDmode
)
736 /* Iterate over all of the CCmodes. */
737 for (m
= (unsigned int) CCmode
; m
< (unsigned int) NUM_MACHINE_MODES
; ++m
)
739 mode
= (enum machine_mode
) m
;
740 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
741 && HARD_REGNO_MODE_OK (regno
, mode
))
745 /* We can't find a mode valid for this register. */
749 /* Specify the usage characteristics of the register named NAME.
750 It should be a fixed register if FIXED and a
751 call-used register if CALL_USED. */
754 fix_register (name
, fixed
, call_used
)
756 int fixed
, call_used
;
760 /* Decode the name and update the primary form of
761 the register info. */
763 if ((i
= decode_reg_name (name
)) >= 0)
765 if ((i
== STACK_POINTER_REGNUM
766 #ifdef HARD_FRAME_POINTER_REGNUM
767 || i
== HARD_FRAME_POINTER_REGNUM
769 || i
== FRAME_POINTER_REGNUM
772 && (fixed
== 0 || call_used
== 0))
774 static const char * const what_option
[2][2] = {
775 { "call-saved", "call-used" },
776 { "no-such-option", "fixed" }};
778 error ("can't use '%s' as a %s register", name
,
779 what_option
[fixed
][call_used
]);
783 fixed_regs
[i
] = fixed
;
784 call_used_regs
[i
] = call_used
;
785 #ifdef CALL_REALLY_USED_REGISTERS
787 call_really_used_regs
[i
] = call_used
;
793 warning ("unknown register name: %s", name
);
797 /* Mark register number I as global. */
803 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
804 error ("global register variable follows a function definition");
808 warning ("register used for two global register variables");
812 if (call_used_regs
[i
] && ! fixed_regs
[i
])
813 warning ("call-clobbered register used for global register variable");
817 /* If already fixed, nothing else to do. */
821 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
824 SET_HARD_REG_BIT (fixed_reg_set
, i
);
825 SET_HARD_REG_BIT (call_used_reg_set
, i
);
826 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
827 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
830 /* Now the data and code for the `regclass' pass, which happens
831 just before local-alloc. */
833 /* The `costs' struct records the cost of using a hard register of each class
834 and of using memory for each pseudo. We use this data to set up
835 register class preferences. */
839 int cost
[N_REG_CLASSES
];
843 /* Structure used to record preferrences of given pseudo. */
846 /* (enum reg_class) prefclass is the preferred class. */
849 /* altclass is a register class that we should use for allocating
850 pseudo if no register in the preferred class is available.
851 If no register in this class is available, memory is preferred.
853 It might appear to be more general to have a bitmask of classes here,
854 but since it is recommended that there be a class corresponding to the
855 union of most major pair of classes, that generality is not required. */
859 /* Record the cost of each class for each pseudo. */
861 static struct costs
*costs
;
863 /* Initialized once, and used to initialize cost values for each insn. */
865 static struct costs init_cost
;
867 /* Record preferrences of each pseudo.
868 This is available after `regclass' is run. */
870 static struct reg_pref
*reg_pref
;
872 /* Allocated buffers for reg_pref. */
874 static struct reg_pref
*reg_pref_buffer
;
876 /* Frequency of executions of current insn. */
878 static int frequency
;
880 static rtx scan_one_insn
PARAMS ((rtx
, int));
881 static void record_operand_costs
PARAMS ((rtx
, struct costs
*, struct reg_pref
*));
882 static void dump_regclass
PARAMS ((FILE *));
883 static void record_reg_classes
PARAMS ((int, int, rtx
*, enum machine_mode
*,
885 struct costs
*, struct reg_pref
*));
886 static int copy_cost
PARAMS ((rtx
, enum machine_mode
,
887 enum reg_class
, int));
888 static void record_address_regs
PARAMS ((rtx
, enum reg_class
, int));
889 #ifdef FORBIDDEN_INC_DEC_CLASSES
890 static int auto_inc_dec_reg_p
PARAMS ((rtx
, enum machine_mode
));
892 static void reg_scan_mark_refs
PARAMS ((rtx
, rtx
, int, unsigned int));
894 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
895 This function is sometimes called before the info has been computed.
896 When that happens, just return GENERAL_REGS, which is innocuous. */
899 reg_preferred_class (regno
)
904 return (enum reg_class
) reg_pref
[regno
].prefclass
;
908 reg_alternate_class (regno
)
914 return (enum reg_class
) reg_pref
[regno
].altclass
;
917 /* Initialize some global data for this pass. */
924 init_cost
.mem_cost
= 10000;
925 for (i
= 0; i
< N_REG_CLASSES
; i
++)
926 init_cost
.cost
[i
] = 10000;
928 /* This prevents dump_flow_info from losing if called
929 before regclass is run. */
932 /* No more global register variables may be declared. */
933 no_global_reg_vars
= 1;
936 /* Dump register costs. */
941 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
943 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
945 int /* enum reg_class */ class;
948 fprintf (dump
, " Register %i costs:", i
);
949 for (class = 0; class < (int) N_REG_CLASSES
; class++)
950 if (contains_reg_of_mode
[(enum reg_class
) class][PSEUDO_REGNO_MODE (i
)]
951 #ifdef FORBIDDEN_INC_DEC_CLASSES
953 || !forbidden_inc_dec_class
[(enum reg_class
) class])
955 #ifdef CLASS_CANNOT_CHANGE_MODE
956 && (!REGNO_REG_SET_P (reg_changes_mode
, i
)
957 || class_can_change_mode
[(enum reg_class
) class])
960 fprintf (dump
, " %s:%i", reg_class_names
[class],
961 costs
[i
].cost
[(enum reg_class
) class]);
962 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
968 /* Calculate the costs of insn operands. */
971 record_operand_costs (insn
, op_costs
, reg_pref
)
973 struct costs
*op_costs
;
974 struct reg_pref
*reg_pref
;
976 const char *constraints
[MAX_RECOG_OPERANDS
];
977 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
980 for (i
= 0; i
< recog_data
.n_operands
; i
++)
982 constraints
[i
] = recog_data
.constraints
[i
];
983 modes
[i
] = recog_data
.operand_mode
[i
];
986 /* If we get here, we are set up to record the costs of all the
987 operands for this insn. Start by initializing the costs.
988 Then handle any address registers. Finally record the desired
989 classes for any pseudos, doing it twice if some pair of
990 operands are commutative. */
992 for (i
= 0; i
< recog_data
.n_operands
; i
++)
994 op_costs
[i
] = init_cost
;
996 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
998 rtx inner
= SUBREG_REG (recog_data
.operand
[i
]);
999 #ifdef CLASS_CANNOT_CHANGE_MODE
1000 if (GET_CODE (inner
) == REG
1001 && CLASS_CANNOT_CHANGE_MODE_P (modes
[i
], GET_MODE (inner
)))
1002 SET_REGNO_REG_SET (reg_changes_mode
, REGNO (inner
));
1004 recog_data
.operand
[i
] = inner
;
1007 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
1008 record_address_regs (XEXP (recog_data
.operand
[i
], 0),
1009 MODE_BASE_REG_CLASS (modes
[i
]), frequency
* 2);
1010 else if (constraints
[i
][0] == 'p'
1011 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0]))
1012 record_address_regs (recog_data
.operand
[i
],
1013 MODE_BASE_REG_CLASS (modes
[i
]), frequency
* 2);
1016 /* Check for commutative in a separate loop so everything will
1017 have been initialized. We must do this even if one operand
1018 is a constant--see addsi3 in m68k.md. */
1020 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1021 if (constraints
[i
][0] == '%')
1023 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1026 /* Handle commutative operands by swapping the constraints.
1027 We assume the modes are the same. */
1029 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1030 xconstraints
[j
] = constraints
[j
];
1032 xconstraints
[i
] = constraints
[i
+1];
1033 xconstraints
[i
+1] = constraints
[i
];
1034 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1035 recog_data
.operand
, modes
,
1036 xconstraints
, insn
, op_costs
, reg_pref
);
1039 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1040 recog_data
.operand
, modes
,
1041 constraints
, insn
, op_costs
, reg_pref
);
1044 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1045 time it would save code to put a certain register in a certain class.
1046 PASS, when nonzero, inhibits some optimizations which need only be done
1048 Return the last insn processed, so that the scan can be continued from
1052 scan_one_insn (insn
, pass
)
1056 enum rtx_code code
= GET_CODE (insn
);
1057 enum rtx_code pat_code
;
1060 struct costs op_costs
[MAX_RECOG_OPERANDS
];
1062 if (GET_RTX_CLASS (code
) != 'i')
1065 pat_code
= GET_CODE (PATTERN (insn
));
1067 || pat_code
== CLOBBER
1068 || pat_code
== ASM_INPUT
1069 || pat_code
== ADDR_VEC
1070 || pat_code
== ADDR_DIFF_VEC
)
1073 set
= single_set (insn
);
1074 extract_insn (insn
);
1076 /* If this insn loads a parameter from its stack slot, then
1077 it represents a savings, rather than a cost, if the
1078 parameter is stored in memory. Record this fact. */
1080 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
1081 && GET_CODE (SET_SRC (set
)) == MEM
1082 && (note
= find_reg_note (insn
, REG_EQUIV
,
1084 && GET_CODE (XEXP (note
, 0)) == MEM
)
1086 costs
[REGNO (SET_DEST (set
))].mem_cost
1087 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
1090 record_address_regs (XEXP (SET_SRC (set
), 0),
1091 MODE_BASE_REG_CLASS (VOIDmode
), frequency
* 2);
1095 /* Improve handling of two-address insns such as
1096 (set X (ashift CONST Y)) where CONST must be made to
1097 match X. Change it into two insns: (set X CONST)
1098 (set X (ashift X Y)). If we left this for reloading, it
1099 would probably get three insns because X and Y might go
1100 in the same place. This prevents X and Y from receiving
1103 We can only do this if the modes of operands 0 and 1
1104 (which might not be the same) are tieable and we only need
1105 do this during our first pass. */
1107 if (pass
== 0 && optimize
1108 && recog_data
.n_operands
>= 3
1109 && recog_data
.constraints
[1][0] == '0'
1110 && recog_data
.constraints
[1][1] == 0
1111 && CONSTANT_P (recog_data
.operand
[1])
1112 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
1113 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
1114 && GET_CODE (recog_data
.operand
[0]) == REG
1115 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
1116 recog_data
.operand_mode
[1]))
1118 rtx previnsn
= prev_real_insn (insn
);
1120 = gen_lowpart (recog_data
.operand_mode
[1],
1121 recog_data
.operand
[0]);
1123 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
1125 /* If this insn was the start of a basic block,
1126 include the new insn in that block.
1127 We need not check for code_label here;
1128 while a basic block can start with a code_label,
1129 INSN could not be at the beginning of that block. */
1130 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
1134 if (insn
== b
->head
)
1138 /* This makes one more setting of new insns's dest. */
1139 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
1140 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1141 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1143 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
1144 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1145 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1146 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
1147 if (recog_data
.dup_num
[i
] == 1)
1149 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
1150 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1151 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1154 return PREV_INSN (newinsn
);
1157 record_operand_costs (insn
, op_costs
, reg_pref
);
1159 /* Now add the cost for each operand to the total costs for
1162 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1163 if (GET_CODE (recog_data
.operand
[i
]) == REG
1164 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1166 int regno
= REGNO (recog_data
.operand
[i
]);
1167 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1169 p
->mem_cost
+= q
->mem_cost
* frequency
;
1170 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1171 p
->cost
[j
] += q
->cost
[j
] * frequency
;
1177 /* This is a pass of the compiler that scans all instructions
1178 and calculates the preferred class for each pseudo-register.
1179 This information can be accessed later by calling `reg_preferred_class'.
1180 This pass comes just before local register allocation. */
1183 regclass (f
, nregs
, dump
)
1194 costs
= (struct costs
*) xmalloc (nregs
* sizeof (struct costs
));
1196 #ifdef CLASS_CANNOT_CHANGE_MODE
1197 reg_changes_mode
= BITMAP_XMALLOC ();
1200 #ifdef FORBIDDEN_INC_DEC_CLASSES
1202 in_inc_dec
= (char *) xmalloc (nregs
);
1204 /* Initialize information about which register classes can be used for
1205 pseudos that are auto-incremented or auto-decremented. It would
1206 seem better to put this in init_reg_sets, but we need to be able
1207 to allocate rtx, which we can't do that early. */
1209 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1211 rtx r
= gen_rtx_REG (VOIDmode
, 0);
1212 enum machine_mode m
;
1215 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1216 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1220 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1221 m
= (enum machine_mode
) ((int) m
+ 1))
1222 if (HARD_REGNO_MODE_OK (j
, m
))
1226 /* If a register is not directly suitable for an
1227 auto-increment or decrement addressing mode and
1228 requires secondary reloads, disallow its class from
1229 being used in such addresses. */
1232 #ifdef SECONDARY_RELOAD_CLASS
1233 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1236 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1237 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1240 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1241 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1246 && ! auto_inc_dec_reg_p (r
, m
))
1247 forbidden_inc_dec_class
[i
] = 1;
1251 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1253 /* Normally we scan the insns once and determine the best class to use for
1254 each register. However, if -fexpensive_optimizations are on, we do so
1255 twice, the second time using the tentative best classes to guide the
1258 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1263 fprintf (dump
, "\n\nPass %i\n\n",pass
);
1264 /* Zero out our accumulation of the cost of each class for each reg. */
1266 memset ((char *) costs
, 0, nregs
* sizeof (struct costs
));
1268 #ifdef FORBIDDEN_INC_DEC_CLASSES
1269 memset (in_inc_dec
, 0, nregs
);
1272 /* Scan the instructions and record each time it would
1273 save code to put a certain register in a certain class. */
1277 frequency
= REG_FREQ_MAX
;
1278 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1279 insn
= scan_one_insn (insn
, pass
);
1284 /* Show that an insn inside a loop is likely to be executed three
1285 times more than insns outside a loop. This is much more
1286 aggressive than the assumptions made elsewhere and is being
1287 tried as an experiment. */
1288 frequency
= REG_FREQ_FROM_BB (bb
);
1289 for (insn
= bb
->head
; ; insn
= NEXT_INSN (insn
))
1291 insn
= scan_one_insn (insn
, pass
);
1292 if (insn
== bb
->end
)
1297 /* Now for each register look at how desirable each class is
1298 and find which class is preferred. Store that in
1299 `prefclass'. Record in `altclass' the largest register
1300 class any of whose registers is better than memory. */
1303 reg_pref
= reg_pref_buffer
;
1307 dump_regclass (dump
);
1308 fprintf (dump
,"\n");
1310 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1312 int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1313 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1314 /* This is an enum reg_class, but we call it an int
1315 to save lots of casts. */
1317 struct costs
*p
= &costs
[i
];
1319 /* In non-optimizing compilation REG_N_REFS is not initialized
1321 if (optimize
&& !REG_N_REFS (i
) && !REG_N_SETS (i
))
1324 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1326 /* Ignore classes that are too small for this operand or
1327 invalid for an operand that was auto-incremented. */
1328 if (!contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1329 #ifdef FORBIDDEN_INC_DEC_CLASSES
1330 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1332 #ifdef CLASS_CANNOT_CHANGE_MODE
1333 || (REGNO_REG_SET_P (reg_changes_mode
, i
)
1334 && ! class_can_change_mode
[class])
1338 else if (p
->cost
[class] < best_cost
)
1340 best_cost
= p
->cost
[class];
1341 best
= (enum reg_class
) class;
1343 else if (p
->cost
[class] == best_cost
)
1344 best
= reg_class_subunion
[(int) best
][class];
1347 /* Record the alternate register class; i.e., a class for which
1348 every register in it is better than using memory. If adding a
1349 class would make a smaller class (i.e., no union of just those
1350 classes exists), skip that class. The major unions of classes
1351 should be provided as a register class. Don't do this if we
1352 will be doing it again later. */
1354 if ((pass
== 1 || dump
) || ! flag_expensive_optimizations
)
1355 for (class = 0; class < N_REG_CLASSES
; class++)
1356 if (p
->cost
[class] < p
->mem_cost
1357 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1358 > reg_class_size
[(int) alt
])
1359 #ifdef FORBIDDEN_INC_DEC_CLASSES
1360 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1362 #ifdef CLASS_CANNOT_CHANGE_MODE
1363 && ! (REGNO_REG_SET_P (reg_changes_mode
, i
)
1364 && ! class_can_change_mode
[class])
1367 alt
= reg_class_subunion
[(int) alt
][class];
1369 /* If we don't add any classes, nothing to try. */
1374 && (reg_pref
[i
].prefclass
!= (int) best
1375 || reg_pref
[i
].altclass
!= (int) alt
))
1377 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1378 fprintf (dump
, " Register %i", i
);
1379 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1380 fprintf (dump
, " pref %s\n", reg_class_names
[(int) best
]);
1381 else if (alt
== NO_REGS
)
1382 fprintf (dump
, " pref %s or none\n", reg_class_names
[(int) best
]);
1384 fprintf (dump
, " pref %s, else %s\n",
1385 reg_class_names
[(int) best
],
1386 reg_class_names
[(int) alt
]);
1389 /* We cast to (int) because (char) hits bugs in some compilers. */
1390 reg_pref
[i
].prefclass
= (int) best
;
1391 reg_pref
[i
].altclass
= (int) alt
;
1395 #ifdef FORBIDDEN_INC_DEC_CLASSES
1398 #ifdef CLASS_CANNOT_CHANGE_MODE
1399 BITMAP_XFREE (reg_changes_mode
);
1404 /* Record the cost of using memory or registers of various classes for
1405 the operands in INSN.
1407 N_ALTS is the number of alternatives.
1409 N_OPS is the number of operands.
1411 OPS is an array of the operands.
1413 MODES are the modes of the operands, in case any are VOIDmode.
1415 CONSTRAINTS are the constraints to use for the operands. This array
1416 is modified by this procedure.
1418 This procedure works alternative by alternative. For each alternative
1419 we assume that we will be able to allocate all pseudos to their ideal
1420 register class and calculate the cost of using that alternative. Then
1421 we compute for each operand that is a pseudo-register, the cost of
1422 having the pseudo allocated to each register class and using it in that
1423 alternative. To this cost is added the cost of the alternative.
1425 The cost of each class for this insn is its lowest cost among all the
1429 record_reg_classes (n_alts
, n_ops
, ops
, modes
,
1430 constraints
, insn
, op_costs
, reg_pref
)
1434 enum machine_mode
*modes
;
1435 const char **constraints
;
1437 struct costs
*op_costs
;
1438 struct reg_pref
*reg_pref
;
1444 /* Process each alternative, each time minimizing an operand's cost with
1445 the cost for each operand in that alternative. */
1447 for (alt
= 0; alt
< n_alts
; alt
++)
1449 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1452 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1453 int allows_mem
[MAX_RECOG_OPERANDS
];
1456 for (i
= 0; i
< n_ops
; i
++)
1458 const char *p
= constraints
[i
];
1460 enum machine_mode mode
= modes
[i
];
1461 int allows_addr
= 0;
1465 /* Initially show we know nothing about the register class. */
1466 classes
[i
] = NO_REGS
;
1469 /* If this operand has no constraints at all, we can conclude
1470 nothing about it since anything is valid. */
1474 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1475 memset ((char *) &this_op_costs
[i
], 0, sizeof this_op_costs
[i
]);
1480 /* If this alternative is only relevant when this operand
1481 matches a previous operand, we do different things depending
1482 on whether this operand is a pseudo-reg or not. We must process
1483 any modifiers for the operand before we can make this test. */
1485 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1488 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1490 /* Copy class and whether memory is allowed from the matching
1491 alternative. Then perform any needed cost computations
1492 and/or adjustments. */
1494 classes
[i
] = classes
[j
];
1495 allows_mem
[i
] = allows_mem
[j
];
1497 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1499 /* If this matches the other operand, we have no added
1501 if (rtx_equal_p (ops
[j
], op
))
1504 /* If we can put the other operand into a register, add to
1505 the cost of this alternative the cost to copy this
1506 operand to the register used for the other operand. */
1508 else if (classes
[j
] != NO_REGS
)
1509 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1511 else if (GET_CODE (ops
[j
]) != REG
1512 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1514 /* This op is a pseudo but the one it matches is not. */
1516 /* If we can't put the other operand into a register, this
1517 alternative can't be used. */
1519 if (classes
[j
] == NO_REGS
)
1522 /* Otherwise, add to the cost of this alternative the cost
1523 to copy the other operand to the register used for this
1527 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1531 /* The costs of this operand are not the same as the other
1532 operand since move costs are not symmetric. Moreover,
1533 if we cannot tie them, this alternative needs to do a
1534 copy, which is one instruction. */
1536 struct costs
*pp
= &this_op_costs
[i
];
1538 for (class = 0; class < N_REG_CLASSES
; class++)
1540 = ((recog_data
.operand_type
[i
] != OP_OUT
1541 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1543 + (recog_data
.operand_type
[i
] != OP_IN
1544 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1547 /* If the alternative actually allows memory, make things
1548 a bit cheaper since we won't need an extra insn to
1552 = ((recog_data
.operand_type
[i
] != OP_IN
1553 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1555 + (recog_data
.operand_type
[i
] != OP_OUT
1556 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1557 : 0) - allows_mem
[i
]);
1559 /* If we have assigned a class to this register in our
1560 first pass, add a cost to this alternative corresponding
1561 to what we would add if this register were not in the
1562 appropriate class. */
1566 += (may_move_in_cost
[mode
]
1567 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1568 [(int) classes
[i
]]);
1570 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1571 && ! find_reg_note (insn
, REG_DEAD
, op
))
1574 /* This is in place of ordinary cost computation
1575 for this operand, so skip to the end of the
1576 alternative (should be just one character). */
1577 while (*p
&& *p
++ != ',')
1585 /* Scan all the constraint letters. See if the operand matches
1586 any of the constraints. Collect the valid register classes
1587 and see if this operand accepts memory. */
1589 while (*p
&& (c
= *p
++) != ',')
1593 /* Ignore the next letter for this pass. */
1599 case '!': case '#': case '&':
1600 case '0': case '1': case '2': case '3': case '4':
1601 case '5': case '6': case '7': case '8': case '9':
1606 win
= address_operand (op
, GET_MODE (op
));
1607 /* We know this operand is an address, so we want it to be
1608 allocated to a register that can be the base of an
1609 address, ie BASE_REG_CLASS. */
1611 = reg_class_subunion
[(int) classes
[i
]]
1612 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1615 case 'm': case 'o': case 'V':
1616 /* It doesn't seem worth distinguishing between offsettable
1617 and non-offsettable addresses here. */
1619 if (GET_CODE (op
) == MEM
)
1624 if (GET_CODE (op
) == MEM
1625 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1626 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1631 if (GET_CODE (op
) == MEM
1632 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1633 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1639 if (GET_CODE (op
) == CONST_DOUBLE
1640 || (GET_CODE (op
) == CONST_VECTOR
1641 && (GET_MODE_CLASS (GET_MODE (op
))
1642 == MODE_VECTOR_FLOAT
)))
1648 if (GET_CODE (op
) == CONST_DOUBLE
1649 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1654 if (GET_CODE (op
) == CONST_INT
1655 || (GET_CODE (op
) == CONST_DOUBLE
1656 && GET_MODE (op
) == VOIDmode
))
1660 #ifdef LEGITIMATE_PIC_OPERAND_P
1661 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1668 if (GET_CODE (op
) == CONST_INT
1669 || (GET_CODE (op
) == CONST_DOUBLE
1670 && GET_MODE (op
) == VOIDmode
))
1682 if (GET_CODE (op
) == CONST_INT
1683 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1692 if (GET_CODE (op
) == MEM
1694 #ifdef LEGITIMATE_PIC_OPERAND_P
1695 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1702 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1706 if (REG_CLASS_FROM_LETTER (c
) != NO_REGS
)
1708 = reg_class_subunion
[(int) classes
[i
]]
1709 [(int) REG_CLASS_FROM_LETTER (c
)];
1710 #ifdef EXTRA_CONSTRAINT
1711 else if (EXTRA_CONSTRAINT (op
, c
))
1714 if (EXTRA_MEMORY_CONSTRAINT (c
))
1716 /* Every MEM can be reloaded to fit. */
1718 if (GET_CODE (op
) == MEM
)
1721 if (EXTRA_ADDRESS_CONSTRAINT (op
))
1723 /* Every address can be reloaded to fit. */
1725 if (address_operand (op
, GET_MODE (op
)))
1727 /* We know this operand is an address, so we want it to be
1728 allocated to a register that can be the base of an
1729 address, ie BASE_REG_CLASS. */
1731 = reg_class_subunion
[(int) classes
[i
]]
1732 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1740 /* How we account for this operand now depends on whether it is a
1741 pseudo register or not. If it is, we first check if any
1742 register classes are valid. If not, we ignore this alternative,
1743 since we want to assume that all pseudos get allocated for
1744 register preferencing. If some register class is valid, compute
1745 the costs of moving the pseudo into that class. */
1747 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1749 if (classes
[i
] == NO_REGS
)
1751 /* We must always fail if the operand is a REG, but
1752 we did not find a suitable class.
1754 Otherwise we may perform an uninitialized read
1755 from this_op_costs after the `continue' statement
1761 struct costs
*pp
= &this_op_costs
[i
];
1763 for (class = 0; class < N_REG_CLASSES
; class++)
1765 = ((recog_data
.operand_type
[i
] != OP_OUT
1766 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1768 + (recog_data
.operand_type
[i
] != OP_IN
1769 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1772 /* If the alternative actually allows memory, make things
1773 a bit cheaper since we won't need an extra insn to
1777 = ((recog_data
.operand_type
[i
] != OP_IN
1778 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1780 + (recog_data
.operand_type
[i
] != OP_OUT
1781 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1782 : 0) - allows_mem
[i
]);
1784 /* If we have assigned a class to this register in our
1785 first pass, add a cost to this alternative corresponding
1786 to what we would add if this register were not in the
1787 appropriate class. */
1791 += (may_move_in_cost
[mode
]
1792 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1793 [(int) classes
[i
]]);
1797 /* Otherwise, if this alternative wins, either because we
1798 have already determined that or if we have a hard register of
1799 the proper class, there is no cost for this alternative. */
1802 || (GET_CODE (op
) == REG
1803 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1806 /* If registers are valid, the cost of this alternative includes
1807 copying the object to and/or from a register. */
1809 else if (classes
[i
] != NO_REGS
)
1811 if (recog_data
.operand_type
[i
] != OP_OUT
)
1812 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1814 if (recog_data
.operand_type
[i
] != OP_IN
)
1815 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1818 /* The only other way this alternative can be used is if this is a
1819 constant that could be placed into memory. */
1821 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1822 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1830 /* Finally, update the costs with the information we've calculated
1831 about this alternative. */
1833 for (i
= 0; i
< n_ops
; i
++)
1834 if (GET_CODE (ops
[i
]) == REG
1835 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1837 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1838 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1840 pp
->mem_cost
= MIN (pp
->mem_cost
,
1841 (qq
->mem_cost
+ alt_cost
) * scale
);
1843 for (class = 0; class < N_REG_CLASSES
; class++)
1844 pp
->cost
[class] = MIN (pp
->cost
[class],
1845 (qq
->cost
[class] + alt_cost
) * scale
);
1849 /* If this insn is a single set copying operand 1 to operand 0
1850 and one operand is a pseudo with the other a hard reg or a pseudo
1851 that prefers a register that is in its own register class then
1852 we may want to adjust the cost of that register class to -1.
1854 Avoid the adjustment if the source does not die to avoid stressing of
1855 register allocator by preferrencing two coliding registers into single
1858 Also avoid the adjustment if a copy between registers of the class
1859 is expensive (ten times the cost of a default copy is considered
1860 arbitrarily expensive). This avoids losing when the preferred class
1861 is very expensive as the source of a copy instruction. */
1863 if ((set
= single_set (insn
)) != 0
1864 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1865 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
1866 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1867 for (i
= 0; i
<= 1; i
++)
1868 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1870 unsigned int regno
= REGNO (ops
[!i
]);
1871 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1875 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0)
1877 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1879 if ((reg_class_size
[(unsigned char) pref
]
1880 == (unsigned) CLASS_MAX_NREGS (pref
, mode
))
1881 && REGISTER_MOVE_COST (mode
, pref
, pref
) < 10 * 2)
1882 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1884 else if (regno
< FIRST_PSEUDO_REGISTER
)
1885 for (class = 0; class < N_REG_CLASSES
; class++)
1886 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1887 && reg_class_size
[class] == (unsigned) CLASS_MAX_NREGS (class, mode
))
1889 if (reg_class_size
[class] == 1)
1890 op_costs
[i
].cost
[class] = -1;
1893 for (nr
= 0; nr
< (unsigned) HARD_REGNO_NREGS (regno
, mode
); nr
++)
1895 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
1900 if (nr
== (unsigned) HARD_REGNO_NREGS (regno
,mode
))
1901 op_costs
[i
].cost
[class] = -1;
1907 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1908 TO_P is zero) a register of class CLASS in mode MODE.
1910 X must not be a pseudo. */
1913 copy_cost (x
, mode
, class, to_p
)
1915 enum machine_mode mode ATTRIBUTE_UNUSED
;
1916 enum reg_class
class;
1917 int to_p ATTRIBUTE_UNUSED
;
1919 #ifdef HAVE_SECONDARY_RELOADS
1920 enum reg_class secondary_class
= NO_REGS
;
1923 /* If X is a SCRATCH, there is actually nothing to move since we are
1924 assuming optimal allocation. */
1926 if (GET_CODE (x
) == SCRATCH
)
1929 /* Get the class we will actually use for a reload. */
1930 class = PREFERRED_RELOAD_CLASS (x
, class);
1932 #ifdef HAVE_SECONDARY_RELOADS
1933 /* If we need a secondary reload (we assume here that we are using
1934 the secondary reload as an intermediate, not a scratch register), the
1935 cost is that to load the input into the intermediate register, then
1936 to copy them. We use a special value of TO_P to avoid recursion. */
1938 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1940 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1943 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1945 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1948 if (secondary_class
!= NO_REGS
)
1949 return (move_cost
[mode
][(int) secondary_class
][(int) class]
1950 + copy_cost (x
, mode
, secondary_class
, 2));
1951 #endif /* HAVE_SECONDARY_RELOADS */
1953 /* For memory, use the memory move cost, for (hard) registers, use the
1954 cost to move between the register classes, and use 2 for everything
1955 else (constants). */
1957 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1958 return MEMORY_MOVE_COST (mode
, class, to_p
);
1960 else if (GET_CODE (x
) == REG
)
1961 return move_cost
[mode
][(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1964 /* If this is a constant, we may eventually want to call rtx_cost here. */
1965 return COSTS_N_INSNS (1);
1968 /* Record the pseudo registers we must reload into hard registers
1969 in a subexpression of a memory address, X.
1971 CLASS is the class that the register needs to be in and is either
1972 BASE_REG_CLASS or INDEX_REG_CLASS.
1974 SCALE is twice the amount to multiply the cost by (it is twice so we
1975 can represent half-cost adjustments). */
1978 record_address_regs (x
, class, scale
)
1980 enum reg_class
class;
1983 enum rtx_code code
= GET_CODE (x
);
1996 /* When we have an address that is a sum,
1997 we must determine whether registers are "base" or "index" regs.
1998 If there is a sum of two registers, we must choose one to be
1999 the "base". Luckily, we can use the REG_POINTER to make a good
2000 choice most of the time. We only need to do this on machines
2001 that can have two registers in an address and where the base
2002 and index register classes are different.
2004 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
2005 that seems bogus since it should only be set when we are sure
2006 the register is being used as a pointer. */
2009 rtx arg0
= XEXP (x
, 0);
2010 rtx arg1
= XEXP (x
, 1);
2011 enum rtx_code code0
= GET_CODE (arg0
);
2012 enum rtx_code code1
= GET_CODE (arg1
);
2014 /* Look inside subregs. */
2015 if (code0
== SUBREG
)
2016 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
2017 if (code1
== SUBREG
)
2018 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
2020 /* If this machine only allows one register per address, it must
2021 be in the first operand. */
2023 if (MAX_REGS_PER_ADDRESS
== 1)
2024 record_address_regs (arg0
, class, scale
);
2026 /* If index and base registers are the same on this machine, just
2027 record registers in any non-constant operands. We assume here,
2028 as well as in the tests below, that all addresses are in
2031 else if (INDEX_REG_CLASS
== MODE_BASE_REG_CLASS (VOIDmode
))
2033 record_address_regs (arg0
, class, scale
);
2034 if (! CONSTANT_P (arg1
))
2035 record_address_regs (arg1
, class, scale
);
2038 /* If the second operand is a constant integer, it doesn't change
2039 what class the first operand must be. */
2041 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
2042 record_address_regs (arg0
, class, scale
);
2044 /* If the second operand is a symbolic constant, the first operand
2045 must be an index register. */
2047 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
2048 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
2050 /* If both operands are registers but one is already a hard register
2051 of index or base class, give the other the class that the hard
2054 #ifdef REG_OK_FOR_BASE_P
2055 else if (code0
== REG
&& code1
== REG
2056 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
2057 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
2058 record_address_regs (arg1
,
2059 REG_OK_FOR_BASE_P (arg0
)
2060 ? INDEX_REG_CLASS
: MODE_BASE_REG_CLASS (VOIDmode
),
2062 else if (code0
== REG
&& code1
== REG
2063 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
2064 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
2065 record_address_regs (arg0
,
2066 REG_OK_FOR_BASE_P (arg1
)
2067 ? INDEX_REG_CLASS
: MODE_BASE_REG_CLASS (VOIDmode
),
2071 /* If one operand is known to be a pointer, it must be the base
2072 with the other operand the index. Likewise if the other operand
2075 else if ((code0
== REG
&& REG_POINTER (arg0
))
2078 record_address_regs (arg0
, MODE_BASE_REG_CLASS (VOIDmode
), scale
);
2079 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
2081 else if ((code1
== REG
&& REG_POINTER (arg1
))
2084 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
2085 record_address_regs (arg1
, MODE_BASE_REG_CLASS (VOIDmode
), scale
);
2088 /* Otherwise, count equal chances that each might be a base
2089 or index register. This case should be rare. */
2093 record_address_regs (arg0
, MODE_BASE_REG_CLASS (VOIDmode
),
2095 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
2096 record_address_regs (arg1
, MODE_BASE_REG_CLASS (VOIDmode
),
2098 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
2103 /* Double the importance of a pseudo register that is incremented
2104 or decremented, since it would take two extra insns
2105 if it ends up in the wrong place. */
2108 record_address_regs (XEXP (x
, 0), MODE_BASE_REG_CLASS (VOIDmode
),
2110 if (REG_P (XEXP (XEXP (x
, 1), 1)))
2111 record_address_regs (XEXP (XEXP (x
, 1), 1),
2112 INDEX_REG_CLASS
, 2 * scale
);
2119 /* Double the importance of a pseudo register that is incremented
2120 or decremented, since it would take two extra insns
2121 if it ends up in the wrong place. If the operand is a pseudo,
2122 show it is being used in an INC_DEC context. */
2124 #ifdef FORBIDDEN_INC_DEC_CLASSES
2125 if (GET_CODE (XEXP (x
, 0)) == REG
2126 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
2127 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
2130 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
2135 struct costs
*pp
= &costs
[REGNO (x
)];
2138 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
2140 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2141 pp
->cost
[i
] += (may_move_in_cost
[Pmode
][i
][(int) class] * scale
) / 2;
2147 const char *fmt
= GET_RTX_FORMAT (code
);
2149 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2151 record_address_regs (XEXP (x
, i
), class, scale
);
2156 #ifdef FORBIDDEN_INC_DEC_CLASSES
2158 /* Return 1 if REG is valid as an auto-increment memory reference
2159 to an object of MODE. */
2162 auto_inc_dec_reg_p (reg
, mode
)
2164 enum machine_mode mode
;
2166 if (HAVE_POST_INCREMENT
2167 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2170 if (HAVE_POST_DECREMENT
2171 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2174 if (HAVE_PRE_INCREMENT
2175 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2178 if (HAVE_PRE_DECREMENT
2179 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2186 static short *renumber
;
2187 static size_t regno_allocated
;
2188 static unsigned int reg_n_max
;
2190 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2191 reg_scan and flow_analysis that are indexed by the register number. If
2192 NEW_P is nonzero, initialize all of the registers, otherwise only
2193 initialize the new registers allocated. The same table is kept from
2194 function to function, only reallocating it when we need more room. If
2195 RENUMBER_P is nonzero, allocate the reg_renumber array also. */
2198 allocate_reg_info (num_regs
, new_p
, renumber_p
)
2204 size_t size_renumber
;
2205 size_t min
= (new_p
) ? 0 : reg_n_max
;
2206 struct reg_info_data
*reg_data
;
2208 if (num_regs
> regno_allocated
)
2210 size_t old_allocated
= regno_allocated
;
2212 regno_allocated
= num_regs
+ (num_regs
/ 20); /* add some slop space */
2213 size_renumber
= regno_allocated
* sizeof (short);
2217 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
2218 renumber
= (short *) xmalloc (size_renumber
);
2219 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2220 * sizeof (struct reg_pref
));
2225 VARRAY_GROW (reg_n_info
, regno_allocated
);
2227 if (new_p
) /* if we're zapping everything, no need to realloc */
2229 free ((char *) renumber
);
2230 free ((char *) reg_pref
);
2231 renumber
= (short *) xmalloc (size_renumber
);
2232 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2233 * sizeof (struct reg_pref
));
2238 renumber
= (short *) xrealloc ((char *) renumber
, size_renumber
);
2239 reg_pref_buffer
= (struct reg_pref
*) xrealloc ((char *) reg_pref_buffer
,
2241 * sizeof (struct reg_pref
));
2245 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
2246 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
2247 reg_data
= (struct reg_info_data
*) xcalloc (size_info
, 1);
2248 reg_data
->min_index
= old_allocated
;
2249 reg_data
->max_index
= regno_allocated
- 1;
2250 reg_data
->next
= reg_info_head
;
2251 reg_info_head
= reg_data
;
2254 reg_n_max
= num_regs
;
2257 /* Loop through each of the segments allocated for the actual
2258 reg_info pages, and set up the pointers, zero the pages, etc. */
2259 for (reg_data
= reg_info_head
;
2260 reg_data
&& reg_data
->max_index
>= min
;
2261 reg_data
= reg_data
->next
)
2263 size_t min_index
= reg_data
->min_index
;
2264 size_t max_index
= reg_data
->max_index
;
2265 size_t max
= MIN (max_index
, num_regs
);
2266 size_t local_min
= min
- min_index
;
2269 if (reg_data
->min_index
> num_regs
)
2272 if (min
< min_index
)
2274 if (!reg_data
->used_p
) /* page just allocated with calloc */
2275 reg_data
->used_p
= 1; /* no need to zero */
2277 memset ((char *) ®_data
->data
[local_min
], 0,
2278 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
2280 for (i
= min_index
+local_min
; i
<= max
; i
++)
2282 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
2283 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
2285 reg_pref_buffer
[i
].prefclass
= (char) NO_REGS
;
2286 reg_pref_buffer
[i
].altclass
= (char) NO_REGS
;
2291 /* If {pref,alt}class have already been allocated, update the pointers to
2292 the newly realloced ones. */
2294 reg_pref
= reg_pref_buffer
;
2297 reg_renumber
= renumber
;
2299 /* Tell the regset code about the new number of registers */
2300 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
2303 /* Free up the space allocated by allocate_reg_info. */
2309 struct reg_info_data
*reg_data
;
2310 struct reg_info_data
*reg_next
;
2312 VARRAY_FREE (reg_n_info
);
2313 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
2315 reg_next
= reg_data
->next
;
2316 free ((char *) reg_data
);
2319 free (reg_pref_buffer
);
2320 reg_pref_buffer
= (struct reg_pref
*) 0;
2321 reg_info_head
= (struct reg_info_data
*) 0;
2322 renumber
= (short *) 0;
2324 regno_allocated
= 0;
2328 /* This is the `regscan' pass of the compiler, run just before cse
2329 and again just before loop.
2331 It finds the first and last use of each pseudo-register
2332 and records them in the vectors regno_first_uid, regno_last_uid
2333 and counts the number of sets in the vector reg_n_sets.
2335 REPEAT is nonzero the second time this is called. */
2337 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2338 Always at least 3, since the combiner could put that many together
2339 and we want this to remain correct for all the remaining passes.
2340 This corresponds to the maximum number of times note_stores will call
2341 a function for any insn. */
2345 /* Used as a temporary to record the largest number of registers in
2346 PARALLEL in a SET_DEST. This is added to max_parallel. */
2348 static int max_set_parallel
;
2351 reg_scan (f
, nregs
, repeat
)
2354 int repeat ATTRIBUTE_UNUSED
;
2358 allocate_reg_info (nregs
, TRUE
, FALSE
);
2360 max_set_parallel
= 0;
2362 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2363 if (GET_CODE (insn
) == INSN
2364 || GET_CODE (insn
) == CALL_INSN
2365 || GET_CODE (insn
) == JUMP_INSN
)
2367 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2368 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2369 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2370 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, 0);
2372 if (REG_NOTES (insn
))
2373 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
2376 max_parallel
+= max_set_parallel
;
2379 /* Update 'regscan' information by looking at the insns
2380 from FIRST to LAST. Some new REGs have been created,
2381 and any REG with number greater than OLD_MAX_REGNO is
2382 such a REG. We only update information for those. */
2385 reg_scan_update (first
, last
, old_max_regno
)
2388 unsigned int old_max_regno
;
2392 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
2394 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
2395 if (GET_CODE (insn
) == INSN
2396 || GET_CODE (insn
) == CALL_INSN
2397 || GET_CODE (insn
) == JUMP_INSN
)
2399 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2400 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2401 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2402 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, old_max_regno
);
2404 if (REG_NOTES (insn
))
2405 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2409 /* X is the expression to scan. INSN is the insn it appears in.
2410 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2411 We should only record information for REGs with numbers
2412 greater than or equal to MIN_REGNO. */
2415 reg_scan_mark_refs (x
, insn
, note_flag
, min_regno
)
2419 unsigned int min_regno
;
2427 code
= GET_CODE (x
);
2444 unsigned int regno
= REGNO (x
);
2446 if (regno
>= min_regno
)
2448 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2450 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2451 if (REGNO_FIRST_UID (regno
) == 0)
2452 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2453 /* If we are called by reg_scan_update() (indicated by min_regno
2454 being set), we also need to update the reference count. */
2456 REG_N_REFS (regno
)++;
2463 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2465 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2470 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2475 rtx reg
= XEXP (x
, 0);
2477 && REGNO (reg
) >= min_regno
)
2479 REG_N_SETS (REGNO (reg
))++;
2480 REG_N_REFS (REGNO (reg
))++;
2486 /* Count a set of the destination if it is a register. */
2487 for (dest
= SET_DEST (x
);
2488 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2489 || GET_CODE (dest
) == ZERO_EXTEND
;
2490 dest
= XEXP (dest
, 0))
2493 /* For a PARALLEL, record the number of things (less the usual one for a
2494 SET) that are set. */
2495 if (GET_CODE (dest
) == PARALLEL
)
2496 max_set_parallel
= MAX (max_set_parallel
, XVECLEN (dest
, 0) - 1);
2498 if (GET_CODE (dest
) == REG
2499 && REGNO (dest
) >= min_regno
)
2501 REG_N_SETS (REGNO (dest
))++;
2502 REG_N_REFS (REGNO (dest
))++;
2505 /* If this is setting a pseudo from another pseudo or the sum of a
2506 pseudo and a constant integer and the other pseudo is known to be
2507 a pointer, set the destination to be a pointer as well.
2509 Likewise if it is setting the destination from an address or from a
2510 value equivalent to an address or to the sum of an address and
2513 But don't do any of this if the pseudo corresponds to a user
2514 variable since it should have already been set as a pointer based
2517 if (GET_CODE (SET_DEST (x
)) == REG
2518 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2519 && REGNO (SET_DEST (x
)) >= min_regno
2520 /* If the destination pseudo is set more than once, then other
2521 sets might not be to a pointer value (consider access to a
2522 union in two threads of control in the presense of global
2523 optimizations). So only set REG_POINTER on the destination
2524 pseudo if this is the only set of that pseudo. */
2525 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2526 && ! REG_USERVAR_P (SET_DEST (x
))
2527 && ! REG_POINTER (SET_DEST (x
))
2528 && ((GET_CODE (SET_SRC (x
)) == REG
2529 && REG_POINTER (SET_SRC (x
)))
2530 || ((GET_CODE (SET_SRC (x
)) == PLUS
2531 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2532 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2533 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2534 && REG_POINTER (XEXP (SET_SRC (x
), 0)))
2535 || GET_CODE (SET_SRC (x
)) == CONST
2536 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2537 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2538 || (GET_CODE (SET_SRC (x
)) == HIGH
2539 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2540 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2541 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2542 || ((GET_CODE (SET_SRC (x
)) == PLUS
2543 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2544 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2545 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2546 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2547 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2548 && (GET_CODE (XEXP (note
, 0)) == CONST
2549 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2550 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2551 REG_POINTER (SET_DEST (x
)) = 1;
2553 /* If this is setting a register from a register or from a simple
2554 conversion of a register, propagate REG_DECL. */
2555 if (GET_CODE (dest
) == REG
)
2557 rtx src
= SET_SRC (x
);
2559 while (GET_CODE (src
) == SIGN_EXTEND
2560 || GET_CODE (src
) == ZERO_EXTEND
2561 || GET_CODE (src
) == TRUNCATE
2562 || (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)))
2563 src
= XEXP (src
, 0);
2565 if (GET_CODE (src
) == REG
&& REGNO_DECL (REGNO (src
)) == 0)
2566 REGNO_DECL (REGNO (src
)) = REGNO_DECL (REGNO (dest
));
2567 else if (GET_CODE (src
) == REG
&& REGNO_DECL (REGNO (dest
)) == 0)
2568 REGNO_DECL (REGNO (dest
)) = REGNO_DECL (REGNO (src
));
2571 /* ... fall through ... */
2575 const char *fmt
= GET_RTX_FORMAT (code
);
2577 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2580 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2581 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2584 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2585 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2592 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2596 reg_class_subset_p (c1
, c2
)
2600 if (c1
== c2
) return 1;
2605 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) c1
],
2606 reg_class_contents
[(int) c2
],
2611 /* Return nonzero if there is a register that is in both C1 and C2. */
2614 reg_classes_intersect_p (c1
, c2
)
2623 if (c1
== c2
) return 1;
2625 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2628 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2629 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2631 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2638 /* Release any memory allocated by register sets. */
2641 regset_release_memory ()
2643 bitmap_release_memory ();
2646 #include "gt-regclass.h"