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PR libstdc++/3584
[official-gcc.git] / gcc / longlong.h
blob83ce96564b6c5ecc6af66afd0e476096af4d3a54
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 2, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
19
20 /* You have to define the following before including this file:
21
22 UWtype -- An unsigned type, default type for operations (typically a "word")
23 UHWtype -- An unsigned type, at least half the size of UWtype.
24 UDWtype -- An unsigned type, at least twice as large a UWtype
25 W_TYPE_SIZE -- size in bits of UWtype
26
27 UQItype -- Unsigned 8 bit type.
28 SItype, USItype -- Signed and unsigned 32 bit types.
29 DItype, UDItype -- Signed and unsigned 64 bit types.
30
31 On a 32 bit machine UWtype should typically be USItype;
32 on a 64 bit machine, UWtype should typically be UDItype.
33 */
34
35 #define __BITS4 (W_TYPE_SIZE / 4)
36 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
37 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
38 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
39
40 #ifndef W_TYPE_SIZE
41 #define W_TYPE_SIZE 32
42 #define UWtype USItype
43 #define UHWtype USItype
44 #define UDWtype UDItype
45 #endif
46
47 /* Define auxiliary asm macros.
48
49 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
50 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
52
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
55
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
63
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
66 is rounded towards 0.
67
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first nonzero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
72
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
75
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
81
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
87 and is lost.
88
89 If any of these macros are left undefined for a particular CPU,
90 C macros are used. */
91
92 /* The CPUs come in alphabetical order below.
93
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below!
96 (E.g. WE32100, IBM360.) */
97
98 #if defined (__GNUC__) && !defined (NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 #if defined (__alpha) && W_TYPE_SIZE == 64
111 #define umul_ppmm(ph, pl, m0, m1) \
112 do { \
113 UDItype __m0 = (m0), __m1 = (m1); \
114 __asm__ ("umulh %r1,%2,%0" \
115 : "=r" ((UDItype) ph) \
116 : "%rJ" (__m0), \
117 "rI" (__m1)); \
118 (pl) = __m0 * __m1; \
119 } while (0)
120 #define UMUL_TIME 46
121 #ifndef LONGLONG_STANDALONE
122 #define udiv_qrnnd(q, r, n1, n0, d) \
123 do { UDItype __r; \
124 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
125 (r) = __r; \
126 } while (0)
127 extern UDItype __udiv_qrnnd PARAMS ((UDItype *, UDItype, UDItype, UDItype));
128 #define UDIV_TIME 220
129 #endif /* LONGLONG_STANDALONE */
130 #ifdef __alpha_cix__
131 #define count_leading_zeros(COUNT,X) \
132 __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
133 #define count_trailing_zeros(COUNT,X) \
134 __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
135 #define COUNT_LEADING_ZEROS_0 64
136 #else
137 extern const UQItype __clz_tab[];
138 #define count_leading_zeros(COUNT,X) \
139 do { \
140 UDItype __xr = (X), __t, __a; \
141 __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \
142 __a = __clz_tab[__t ^ 0xff] - 1; \
143 __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \
144 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
145 } while (0)
146 #define count_trailing_zeros(COUNT,X) \
147 do { \
148 UDItype __xr = (X), __t, __a; \
149 __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \
150 __t = ~__t & -~__t; \
151 __a = ((__t & 0xCC) != 0) * 2; \
152 __a += ((__t & 0xF0) != 0) * 4; \
153 __a += ((__t & 0xAA) != 0); \
154 __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \
155 __a <<= 3; \
156 __t &= -__t; \
157 __a += ((__t & 0xCC) != 0) * 2; \
158 __a += ((__t & 0xF0) != 0) * 4; \
159 __a += ((__t & 0xAA) != 0); \
160 (COUNT) = __a; \
161 } while (0)
162 #endif /* __alpha_cix__ */
163 #endif /* __alpha */
164
165 #if defined (__arc__) && W_TYPE_SIZE == 32
166 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
167 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
168 : "=r" ((USItype) (sh)), \
169 "=&r" ((USItype) (sl)) \
170 : "%r" ((USItype) (ah)), \
171 "rIJ" ((USItype) (bh)), \
172 "%r" ((USItype) (al)), \
173 "rIJ" ((USItype) (bl)))
174 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
175 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
176 : "=r" ((USItype) (sh)), \
177 "=&r" ((USItype) (sl)) \
178 : "r" ((USItype) (ah)), \
179 "rIJ" ((USItype) (bh)), \
180 "r" ((USItype) (al)), \
181 "rIJ" ((USItype) (bl)))
182 /* Call libgcc routine. */
183 #define umul_ppmm(w1, w0, u, v) \
184 do { \
185 DWunion __w; \
186 __w.ll = __umulsidi3 (u, v); \
187 w1 = __w.s.high; \
188 w0 = __w.s.low; \
189 } while (0)
190 #define __umulsidi3 __umulsidi3
191 UDItype __umulsidi3 (USItype, USItype);
192 #endif
193
194 #if defined (__arm__) && W_TYPE_SIZE == 32
195 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
196 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
197 : "=r" ((USItype) (sh)), \
198 "=&r" ((USItype) (sl)) \
199 : "%r" ((USItype) (ah)), \
200 "rI" ((USItype) (bh)), \
201 "%r" ((USItype) (al)), \
202 "rI" ((USItype) (bl)))
203 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
204 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
205 : "=r" ((USItype) (sh)), \
206 "=&r" ((USItype) (sl)) \
207 : "r" ((USItype) (ah)), \
208 "rI" ((USItype) (bh)), \
209 "r" ((USItype) (al)), \
210 "rI" ((USItype) (bl)))
211 #define umul_ppmm(xh, xl, a, b) \
212 {register USItype __t0, __t1, __t2; \
213 __asm__ ("%@ Inlined umul_ppmm\n" \
214 " mov %2, %5, lsr #16\n" \
215 " mov %0, %6, lsr #16\n" \
216 " bic %3, %5, %2, lsl #16\n" \
217 " bic %4, %6, %0, lsl #16\n" \
218 " mul %1, %3, %4\n" \
219 " mul %4, %2, %4\n" \
220 " mul %3, %0, %3\n" \
221 " mul %0, %2, %0\n" \
222 " adds %3, %4, %3\n" \
223 " addcs %0, %0, #65536\n" \
224 " adds %1, %1, %3, lsl #16\n" \
225 " adc %0, %0, %3, lsr #16" \
226 : "=&r" ((USItype) (xh)), \
227 "=r" ((USItype) (xl)), \
228 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
229 : "r" ((USItype) (a)), \
230 "r" ((USItype) (b)));}
231 #define UMUL_TIME 20
232 #define UDIV_TIME 100
233 #endif /* __arm__ */
234
235 #if defined (__hppa) && W_TYPE_SIZE == 32
236 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
237 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
238 : "=r" ((USItype) (sh)), \
239 "=&r" ((USItype) (sl)) \
240 : "%rM" ((USItype) (ah)), \
241 "rM" ((USItype) (bh)), \
242 "%rM" ((USItype) (al)), \
243 "rM" ((USItype) (bl)))
244 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
245 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
246 : "=r" ((USItype) (sh)), \
247 "=&r" ((USItype) (sl)) \
248 : "rM" ((USItype) (ah)), \
249 "rM" ((USItype) (bh)), \
250 "rM" ((USItype) (al)), \
251 "rM" ((USItype) (bl)))
252 #if defined (_PA_RISC1_1)
253 #define umul_ppmm(w1, w0, u, v) \
254 do { \
255 union \
256 { \
257 UDItype __f; \
258 struct {USItype __w1, __w0;} __w1w0; \
259 } __t; \
260 __asm__ ("xmpyu %1,%2,%0" \
261 : "=x" (__t.__f) \
262 : "x" ((USItype) (u)), \
263 "x" ((USItype) (v))); \
264 (w1) = __t.__w1w0.__w1; \
265 (w0) = __t.__w1w0.__w0; \
266 } while (0)
267 #define UMUL_TIME 8
268 #else
269 #define UMUL_TIME 30
270 #endif
271 #define UDIV_TIME 40
272 #define count_leading_zeros(count, x) \
273 do { \
274 USItype __tmp; \
275 __asm__ ( \
276 "ldi 1,%0\n" \
277 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
278 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
279 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
280 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
281 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
282 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
283 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
284 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
285 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
286 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
287 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
288 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
289 " extru %1,30,1,%1 ; Extract bit 1.\n" \
290 " sub %0,%1,%0 ; Subtract it.\n" \
291 : "=r" (count), "=r" (__tmp) : "1" (x)); \
292 } while (0)
293 #endif
294
295 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
296 #define smul_ppmm(xh, xl, m0, m1) \
297 do { \
298 union {DItype __ll; \
299 struct {USItype __h, __l;} __i; \
300 } __x; \
301 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
302 : "=&r" (__x.__ll) \
303 : "r" (m0), "r" (m1)); \
304 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
305 } while (0)
306 #define sdiv_qrnnd(q, r, n1, n0, d) \
307 do { \
308 union {DItype __ll; \
309 struct {USItype __h, __l;} __i; \
310 } __x; \
311 __x.__i.__h = n1; __x.__i.__l = n0; \
312 __asm__ ("dr %0,%2" \
313 : "=r" (__x.__ll) \
314 : "0" (__x.__ll), "r" (d)); \
315 (q) = __x.__i.__l; (r) = __x.__i.__h; \
316 } while (0)
317 #endif
318
319 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
320 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
321 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
322 : "=r" ((USItype) (sh)), \
323 "=&r" ((USItype) (sl)) \
324 : "%0" ((USItype) (ah)), \
325 "g" ((USItype) (bh)), \
326 "%1" ((USItype) (al)), \
327 "g" ((USItype) (bl)))
328 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
329 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
330 : "=r" ((USItype) (sh)), \
331 "=&r" ((USItype) (sl)) \
332 : "0" ((USItype) (ah)), \
333 "g" ((USItype) (bh)), \
334 "1" ((USItype) (al)), \
335 "g" ((USItype) (bl)))
336 #define umul_ppmm(w1, w0, u, v) \
337 __asm__ ("mull %3" \
338 : "=a" ((USItype) (w0)), \
339 "=d" ((USItype) (w1)) \
340 : "%0" ((USItype) (u)), \
341 "rm" ((USItype) (v)))
342 #define udiv_qrnnd(q, r, n1, n0, dv) \
343 __asm__ ("divl %4" \
344 : "=a" ((USItype) (q)), \
345 "=d" ((USItype) (r)) \
346 : "0" ((USItype) (n0)), \
347 "1" ((USItype) (n1)), \
348 "rm" ((USItype) (dv)))
349 #define count_leading_zeros(count, x) \
350 do { \
351 USItype __cbtmp; \
352 __asm__ ("bsrl %1,%0" \
353 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
354 (count) = __cbtmp ^ 31; \
355 } while (0)
356 #define count_trailing_zeros(count, x) \
357 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
358 #define UMUL_TIME 40
359 #define UDIV_TIME 40
360 #endif /* 80x86 */
361
362 #if defined (__i960__) && W_TYPE_SIZE == 32
363 #define umul_ppmm(w1, w0, u, v) \
364 ({union {UDItype __ll; \
365 struct {USItype __l, __h;} __i; \
366 } __xx; \
367 __asm__ ("emul %2,%1,%0" \
368 : "=d" (__xx.__ll) \
369 : "%dI" ((USItype) (u)), \
370 "dI" ((USItype) (v))); \
371 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
372 #define __umulsidi3(u, v) \
373 ({UDItype __w; \
374 __asm__ ("emul %2,%1,%0" \
375 : "=d" (__w) \
376 : "%dI" ((USItype) (u)), \
377 "dI" ((USItype) (v))); \
378 __w; })
379 #endif /* __i960__ */
380
381 #if defined (__M32R__) && W_TYPE_SIZE == 32
382 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
383 /* The cmp clears the condition bit. */ \
384 __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0" \
385 : "=r" ((USItype) (sh)), \
386 "=&r" ((USItype) (sl)) \
387 : "%0" ((USItype) (ah)), \
388 "r" ((USItype) (bh)), \
389 "%1" ((USItype) (al)), \
390 "r" ((USItype) (bl)) \
391 : "cbit")
392 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
393 /* The cmp clears the condition bit. */ \
394 __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0" \
395 : "=r" ((USItype) (sh)), \
396 "=&r" ((USItype) (sl)) \
397 : "0" ((USItype) (ah)), \
398 "r" ((USItype) (bh)), \
399 "1" ((USItype) (al)), \
400 "r" ((USItype) (bl)) \
401 : "cbit")
402 #endif /* __M32R__ */
403
404 #if defined (__mc68000__) && W_TYPE_SIZE == 32
405 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
406 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
407 : "=d" ((USItype) (sh)), \
408 "=&d" ((USItype) (sl)) \
409 : "%0" ((USItype) (ah)), \
410 "d" ((USItype) (bh)), \
411 "%1" ((USItype) (al)), \
412 "g" ((USItype) (bl)))
413 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
414 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
415 : "=d" ((USItype) (sh)), \
416 "=&d" ((USItype) (sl)) \
417 : "0" ((USItype) (ah)), \
418 "d" ((USItype) (bh)), \
419 "1" ((USItype) (al)), \
420 "g" ((USItype) (bl)))
421
422 /* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
423 #if defined (__mc68020__) || defined(mc68020) \
424 || defined(__mc68030__) || defined(mc68030) \
425 || defined(__mc68040__) || defined(mc68040) \
426 || defined(__mcpu32__) || defined(mcpu32)
427 #define umul_ppmm(w1, w0, u, v) \
428 __asm__ ("mulu%.l %3,%1:%0" \
429 : "=d" ((USItype) (w0)), \
430 "=d" ((USItype) (w1)) \
431 : "%0" ((USItype) (u)), \
432 "dmi" ((USItype) (v)))
433 #define UMUL_TIME 45
434 #define udiv_qrnnd(q, r, n1, n0, d) \
435 __asm__ ("divu%.l %4,%1:%0" \
436 : "=d" ((USItype) (q)), \
437 "=d" ((USItype) (r)) \
438 : "0" ((USItype) (n0)), \
439 "1" ((USItype) (n1)), \
440 "dmi" ((USItype) (d)))
441 #define UDIV_TIME 90
442 #define sdiv_qrnnd(q, r, n1, n0, d) \
443 __asm__ ("divs%.l %4,%1:%0" \
444 : "=d" ((USItype) (q)), \
445 "=d" ((USItype) (r)) \
446 : "0" ((USItype) (n0)), \
447 "1" ((USItype) (n1)), \
448 "dmi" ((USItype) (d)))
449
450 #else /* not mc68020 */
451 #if !defined(__mcf5200__)
452 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
453 #define umul_ppmm(xh, xl, a, b) \
454 __asm__ ("| Inlined umul_ppmm\n" \
455 " move%.l %2,%/d0\n" \
456 " move%.l %3,%/d1\n" \
457 " move%.l %/d0,%/d2\n" \
458 " swap %/d0\n" \
459 " move%.l %/d1,%/d3\n" \
460 " swap %/d1\n" \
461 " move%.w %/d2,%/d4\n" \
462 " mulu %/d3,%/d4\n" \
463 " mulu %/d1,%/d2\n" \
464 " mulu %/d0,%/d3\n" \
465 " mulu %/d0,%/d1\n" \
466 " move%.l %/d4,%/d0\n" \
467 " eor%.w %/d0,%/d0\n" \
468 " swap %/d0\n" \
469 " add%.l %/d0,%/d2\n" \
470 " add%.l %/d3,%/d2\n" \
471 " jcc 1f\n" \
472 " add%.l %#65536,%/d1\n" \
473 "1: swap %/d2\n" \
474 " moveq %#0,%/d0\n" \
475 " move%.w %/d2,%/d0\n" \
476 " move%.w %/d4,%/d2\n" \
477 " move%.l %/d2,%1\n" \
478 " add%.l %/d1,%/d0\n" \
479 " move%.l %/d0,%0" \
480 : "=g" ((USItype) (xh)), \
481 "=g" ((USItype) (xl)) \
482 : "g" ((USItype) (a)), \
483 "g" ((USItype) (b)) \
484 : "d0", "d1", "d2", "d3", "d4")
485 #define UMUL_TIME 100
486 #define UDIV_TIME 400
487 #endif /* not mcf5200 */
488 #endif /* not mc68020 */
489
490 /* The '020, '030, '040 and '060 have bitfield insns. */
491 #if defined (__mc68020__) || defined(mc68020) \
492 || defined(__mc68030__) || defined(mc68030) \
493 || defined(__mc68040__) || defined(mc68040) \
494 || defined(__mc68060__) || defined(mc68060)
495 #define count_leading_zeros(count, x) \
496 __asm__ ("bfffo %1{%b2:%b2},%0" \
497 : "=d" ((USItype) (count)) \
498 : "od" ((USItype) (x)), "n" (0))
499 #endif
500 #endif /* mc68000 */
501
502 #if defined (__m88000__) && W_TYPE_SIZE == 32
503 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
504 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
505 : "=r" ((USItype) (sh)), \
506 "=&r" ((USItype) (sl)) \
507 : "%rJ" ((USItype) (ah)), \
508 "rJ" ((USItype) (bh)), \
509 "%rJ" ((USItype) (al)), \
510 "rJ" ((USItype) (bl)))
511 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
512 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
513 : "=r" ((USItype) (sh)), \
514 "=&r" ((USItype) (sl)) \
515 : "rJ" ((USItype) (ah)), \
516 "rJ" ((USItype) (bh)), \
517 "rJ" ((USItype) (al)), \
518 "rJ" ((USItype) (bl)))
519 #define count_leading_zeros(count, x) \
520 do { \
521 USItype __cbtmp; \
522 __asm__ ("ff1 %0,%1" \
523 : "=r" (__cbtmp) \
524 : "r" ((USItype) (x))); \
525 (count) = __cbtmp ^ 31; \
526 } while (0)
527 #define COUNT_LEADING_ZEROS_0 63 /* sic */
528 #if defined (__mc88110__)
529 #define umul_ppmm(wh, wl, u, v) \
530 do { \
531 union {UDItype __ll; \
532 struct {USItype __h, __l;} __i; \
533 } __xx; \
534 __asm__ ("mulu.d %0,%1,%2" \
535 : "=r" (__xx.__ll) \
536 : "r" ((USItype) (u)), \
537 "r" ((USItype) (v))); \
538 (wh) = __xx.__i.__h; \
539 (wl) = __xx.__i.__l; \
540 } while (0)
541 #define udiv_qrnnd(q, r, n1, n0, d) \
542 ({union {UDItype __ll; \
543 struct {USItype __h, __l;} __i; \
544 } __xx; \
545 USItype __q; \
546 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
547 __asm__ ("divu.d %0,%1,%2" \
548 : "=r" (__q) \
549 : "r" (__xx.__ll), \
550 "r" ((USItype) (d))); \
551 (r) = (n0) - __q * (d); (q) = __q; })
552 #define UMUL_TIME 5
553 #define UDIV_TIME 25
554 #else
555 #define UMUL_TIME 17
556 #define UDIV_TIME 150
557 #endif /* __mc88110__ */
558 #endif /* __m88000__ */
559
560 #if defined (__mips__) && W_TYPE_SIZE == 32
561 #define umul_ppmm(w1, w0, u, v) \
562 __asm__ ("multu %2,%3" \
563 : "=l" ((USItype) (w0)), \
564 "=h" ((USItype) (w1)) \
565 : "d" ((USItype) (u)), \
566 "d" ((USItype) (v)))
567 #define UMUL_TIME 10
568 #define UDIV_TIME 100
569 #endif /* __mips__ */
570
571 #if defined (__ns32000__) && W_TYPE_SIZE == 32
572 #define umul_ppmm(w1, w0, u, v) \
573 ({union {UDItype __ll; \
574 struct {USItype __l, __h;} __i; \
575 } __xx; \
576 __asm__ ("meid %2,%0" \
577 : "=g" (__xx.__ll) \
578 : "%0" ((USItype) (u)), \
579 "g" ((USItype) (v))); \
580 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
581 #define __umulsidi3(u, v) \
582 ({UDItype __w; \
583 __asm__ ("meid %2,%0" \
584 : "=g" (__w) \
585 : "%0" ((USItype) (u)), \
586 "g" ((USItype) (v))); \
587 __w; })
588 #define udiv_qrnnd(q, r, n1, n0, d) \
589 ({union {UDItype __ll; \
590 struct {USItype __l, __h;} __i; \
591 } __xx; \
592 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
593 __asm__ ("deid %2,%0" \
594 : "=g" (__xx.__ll) \
595 : "0" (__xx.__ll), \
596 "g" ((USItype) (d))); \
597 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
598 #define count_trailing_zeros(count,x) \
599 do { \
600 __asm__ ("ffsd %2,%0" \
601 : "=r" ((USItype) (count)) \
602 : "0" ((USItype) 0), \
603 "r" ((USItype) (x))); \
604 } while (0)
605 #endif /* __ns32000__ */
606
607 /* FIXME: We should test _IBMR2 here when we add assembly support for the
608 system vendor compilers.
609 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
610 enough, since that hits ARM and m68k too. */
611 #if (defined (_ARCH_PPC) /* AIX */ \
612 || defined (_ARCH_PWR) /* AIX */ \
613 || defined (_ARCH_COM) /* AIX */ \
614 || defined (__powerpc__) /* gcc */ \
615 || defined (__POWERPC__) /* BEOS */ \
616 || defined (__ppc__) /* Darwin */ \
617 || defined (PPC) /* GNU/Linux, SysV */ \
618 ) && W_TYPE_SIZE == 32
619 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
620 do { \
621 if (__builtin_constant_p (bh) && (bh) == 0) \
622 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
623 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
624 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
625 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
626 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
627 else \
628 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
629 : "=r" (sh), "=&r" (sl) \
630 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
631 } while (0)
632 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
633 do { \
634 if (__builtin_constant_p (ah) && (ah) == 0) \
635 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
636 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
637 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
638 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
639 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
640 else if (__builtin_constant_p (bh) && (bh) == 0) \
641 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
642 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
643 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
644 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
645 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
646 else \
647 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
648 : "=r" (sh), "=&r" (sl) \
649 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
650 } while (0)
651 #define count_leading_zeros(count, x) \
652 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
653 #define COUNT_LEADING_ZEROS_0 32
654 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
655 || defined (__ppc__) || defined (PPC) || defined (__vxworks__)
656 #define umul_ppmm(ph, pl, m0, m1) \
657 do { \
658 USItype __m0 = (m0), __m1 = (m1); \
659 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
660 (pl) = __m0 * __m1; \
661 } while (0)
662 #define UMUL_TIME 15
663 #define smul_ppmm(ph, pl, m0, m1) \
664 do { \
665 SItype __m0 = (m0), __m1 = (m1); \
666 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
667 (pl) = __m0 * __m1; \
668 } while (0)
669 #define SMUL_TIME 14
670 #define UDIV_TIME 120
671 #elif defined (_ARCH_PWR)
672 #define UMUL_TIME 8
673 #define smul_ppmm(xh, xl, m0, m1) \
674 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
675 #define SMUL_TIME 4
676 #define sdiv_qrnnd(q, r, nh, nl, d) \
677 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
678 #define UDIV_TIME 100
679 #endif
680 #endif /* 32-bit POWER architecture variants. */
681
682 /* We should test _IBMR2 here when we add assembly support for the system
683 vendor compilers. */
684 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
685 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
686 do { \
687 if (__builtin_constant_p (bh) && (bh) == 0) \
688 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
689 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
690 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
691 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
692 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
693 else \
694 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
695 : "=r" (sh), "=&r" (sl) \
696 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
697 } while (0)
698 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
699 do { \
700 if (__builtin_constant_p (ah) && (ah) == 0) \
701 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
702 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
703 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
704 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
705 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
706 else if (__builtin_constant_p (bh) && (bh) == 0) \
707 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
708 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
709 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
710 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
711 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
712 else \
713 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
714 : "=r" (sh), "=&r" (sl) \
715 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
716 } while (0)
717 #define count_leading_zeros(count, x) \
718 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
719 #define COUNT_LEADING_ZEROS_0 64
720 #define umul_ppmm(ph, pl, m0, m1) \
721 do { \
722 UDItype __m0 = (m0), __m1 = (m1); \
723 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
724 (pl) = __m0 * __m1; \
725 } while (0)
726 #define UMUL_TIME 15
727 #define smul_ppmm(ph, pl, m0, m1) \
728 do { \
729 DItype __m0 = (m0), __m1 = (m1); \
730 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
731 (pl) = __m0 * __m1; \
732 } while (0)
733 #define SMUL_TIME 14 /* ??? */
734 #define UDIV_TIME 120 /* ??? */
735 #endif /* 64-bit PowerPC. */
736
737 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
738 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
739 __asm__ ("a %1,%5\n\tae %0,%3" \
740 : "=r" ((USItype) (sh)), \
741 "=&r" ((USItype) (sl)) \
742 : "%0" ((USItype) (ah)), \
743 "r" ((USItype) (bh)), \
744 "%1" ((USItype) (al)), \
745 "r" ((USItype) (bl)))
746 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
747 __asm__ ("s %1,%5\n\tse %0,%3" \
748 : "=r" ((USItype) (sh)), \
749 "=&r" ((USItype) (sl)) \
750 : "0" ((USItype) (ah)), \
751 "r" ((USItype) (bh)), \
752 "1" ((USItype) (al)), \
753 "r" ((USItype) (bl)))
754 #define umul_ppmm(ph, pl, m0, m1) \
755 do { \
756 USItype __m0 = (m0), __m1 = (m1); \
757 __asm__ ( \
758 "s r2,r2\n" \
759 " mts r10,%2\n" \
760 " m r2,%3\n" \
761 " m r2,%3\n" \
762 " m r2,%3\n" \
763 " m r2,%3\n" \
764 " m r2,%3\n" \
765 " m r2,%3\n" \
766 " m r2,%3\n" \
767 " m r2,%3\n" \
768 " m r2,%3\n" \
769 " m r2,%3\n" \
770 " m r2,%3\n" \
771 " m r2,%3\n" \
772 " m r2,%3\n" \
773 " m r2,%3\n" \
774 " m r2,%3\n" \
775 " m r2,%3\n" \
776 " cas %0,r2,r0\n" \
777 " mfs r10,%1" \
778 : "=r" ((USItype) (ph)), \
779 "=r" ((USItype) (pl)) \
780 : "%r" (__m0), \
781 "r" (__m1) \
782 : "r2"); \
783 (ph) += ((((SItype) __m0 >> 31) & __m1) \
784 + (((SItype) __m1 >> 31) & __m0)); \
785 } while (0)
786 #define UMUL_TIME 20
787 #define UDIV_TIME 200
788 #define count_leading_zeros(count, x) \
789 do { \
790 if ((x) >= 0x10000) \
791 __asm__ ("clz %0,%1" \
792 : "=r" ((USItype) (count)) \
793 : "r" ((USItype) (x) >> 16)); \
794 else \
795 { \
796 __asm__ ("clz %0,%1" \
797 : "=r" ((USItype) (count)) \
798 : "r" ((USItype) (x))); \
799 (count) += 16; \
800 } \
801 } while (0)
802 #endif
803
804 #if defined (__sh2__) && W_TYPE_SIZE == 32
805 #define umul_ppmm(w1, w0, u, v) \
806 __asm__ ( \
807 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
808 : "=r" ((USItype)(w1)), \
809 "=r" ((USItype)(w0)) \
810 : "r" ((USItype)(u)), \
811 "r" ((USItype)(v)) \
812 : "macl", "mach")
813 #define UMUL_TIME 5
814 #endif
815
816 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
817 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
818 #define count_leading_zeros(count, x) \
819 do \
820 { \
821 UDItype x_ = (USItype)(x); \
822 SItype c_; \
823 \
824 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
825 (count) = c_ - 31; \
826 } \
827 while (0)
828 #define COUNT_LEADING_ZEROS_0 32
829 #endif
830
831 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
832 && W_TYPE_SIZE == 32
833 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
834 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
835 : "=r" ((USItype) (sh)), \
836 "=&r" ((USItype) (sl)) \
837 : "%rJ" ((USItype) (ah)), \
838 "rI" ((USItype) (bh)), \
839 "%rJ" ((USItype) (al)), \
840 "rI" ((USItype) (bl)) \
841 __CLOBBER_CC)
842 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
843 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
844 : "=r" ((USItype) (sh)), \
845 "=&r" ((USItype) (sl)) \
846 : "rJ" ((USItype) (ah)), \
847 "rI" ((USItype) (bh)), \
848 "rJ" ((USItype) (al)), \
849 "rI" ((USItype) (bl)) \
850 __CLOBBER_CC)
851 #if defined (__sparc_v8__)
852 #define umul_ppmm(w1, w0, u, v) \
853 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
854 : "=r" ((USItype) (w1)), \
855 "=r" ((USItype) (w0)) \
856 : "r" ((USItype) (u)), \
857 "r" ((USItype) (v)))
858 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
859 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
860 : "=&r" ((USItype) (__q)), \
861 "=&r" ((USItype) (__r)) \
862 : "r" ((USItype) (__n1)), \
863 "r" ((USItype) (__n0)), \
864 "r" ((USItype) (__d)))
865 #else
866 #if defined (__sparclite__)
867 /* This has hardware multiply but not divide. It also has two additional
868 instructions scan (ffs from high bit) and divscc. */
869 #define umul_ppmm(w1, w0, u, v) \
870 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
871 : "=r" ((USItype) (w1)), \
872 "=r" ((USItype) (w0)) \
873 : "r" ((USItype) (u)), \
874 "r" ((USItype) (v)))
875 #define udiv_qrnnd(q, r, n1, n0, d) \
876 __asm__ ("! Inlined udiv_qrnnd\n" \
877 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
878 " tst %%g0\n" \
879 " divscc %3,%4,%%g1\n" \
880 " divscc %%g1,%4,%%g1\n" \
881 " divscc %%g1,%4,%%g1\n" \
882 " divscc %%g1,%4,%%g1\n" \
883 " divscc %%g1,%4,%%g1\n" \
884 " divscc %%g1,%4,%%g1\n" \
885 " divscc %%g1,%4,%%g1\n" \
886 " divscc %%g1,%4,%%g1\n" \
887 " divscc %%g1,%4,%%g1\n" \
888 " divscc %%g1,%4,%%g1\n" \
889 " divscc %%g1,%4,%%g1\n" \
890 " divscc %%g1,%4,%%g1\n" \
891 " divscc %%g1,%4,%%g1\n" \
892 " divscc %%g1,%4,%%g1\n" \
893 " divscc %%g1,%4,%%g1\n" \
894 " divscc %%g1,%4,%%g1\n" \
895 " divscc %%g1,%4,%%g1\n" \
896 " divscc %%g1,%4,%%g1\n" \
897 " divscc %%g1,%4,%%g1\n" \
898 " divscc %%g1,%4,%%g1\n" \
899 " divscc %%g1,%4,%%g1\n" \
900 " divscc %%g1,%4,%%g1\n" \
901 " divscc %%g1,%4,%%g1\n" \
902 " divscc %%g1,%4,%%g1\n" \
903 " divscc %%g1,%4,%%g1\n" \
904 " divscc %%g1,%4,%%g1\n" \
905 " divscc %%g1,%4,%%g1\n" \
906 " divscc %%g1,%4,%%g1\n" \
907 " divscc %%g1,%4,%%g1\n" \
908 " divscc %%g1,%4,%%g1\n" \
909 " divscc %%g1,%4,%%g1\n" \
910 " divscc %%g1,%4,%0\n" \
911 " rd %%y,%1\n" \
912 " bl,a 1f\n" \
913 " add %1,%4,%1\n" \
914 "1: ! End of inline udiv_qrnnd" \
915 : "=r" ((USItype) (q)), \
916 "=r" ((USItype) (r)) \
917 : "r" ((USItype) (n1)), \
918 "r" ((USItype) (n0)), \
919 "rI" ((USItype) (d)) \
920 : "g1" __AND_CLOBBER_CC)
921 #define UDIV_TIME 37
922 #define count_leading_zeros(count, x) \
923 do { \
924 __asm__ ("scan %1,1,%0" \
925 : "=r" ((USItype) (count)) \
926 : "r" ((USItype) (x))); \
927 } while (0)
928 /* Early sparclites return 63 for an argument of 0, but they warn that future
929 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
930 undefined. */
931 #else
932 /* SPARC without integer multiplication and divide instructions.
933 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
934 #define umul_ppmm(w1, w0, u, v) \
935 __asm__ ("! Inlined umul_ppmm\n" \
936 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
937 " sra %3,31,%%o5 ! Don't move this insn\n" \
938 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
939 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
940 " mulscc %%g1,%3,%%g1\n" \
941 " mulscc %%g1,%3,%%g1\n" \
942 " mulscc %%g1,%3,%%g1\n" \
943 " mulscc %%g1,%3,%%g1\n" \
944 " mulscc %%g1,%3,%%g1\n" \
945 " mulscc %%g1,%3,%%g1\n" \
946 " mulscc %%g1,%3,%%g1\n" \
947 " mulscc %%g1,%3,%%g1\n" \
948 " mulscc %%g1,%3,%%g1\n" \
949 " mulscc %%g1,%3,%%g1\n" \
950 " mulscc %%g1,%3,%%g1\n" \
951 " mulscc %%g1,%3,%%g1\n" \
952 " mulscc %%g1,%3,%%g1\n" \
953 " mulscc %%g1,%3,%%g1\n" \
954 " mulscc %%g1,%3,%%g1\n" \
955 " mulscc %%g1,%3,%%g1\n" \
956 " mulscc %%g1,%3,%%g1\n" \
957 " mulscc %%g1,%3,%%g1\n" \
958 " mulscc %%g1,%3,%%g1\n" \
959 " mulscc %%g1,%3,%%g1\n" \
960 " mulscc %%g1,%3,%%g1\n" \
961 " mulscc %%g1,%3,%%g1\n" \
962 " mulscc %%g1,%3,%%g1\n" \
963 " mulscc %%g1,%3,%%g1\n" \
964 " mulscc %%g1,%3,%%g1\n" \
965 " mulscc %%g1,%3,%%g1\n" \
966 " mulscc %%g1,%3,%%g1\n" \
967 " mulscc %%g1,%3,%%g1\n" \
968 " mulscc %%g1,%3,%%g1\n" \
969 " mulscc %%g1,%3,%%g1\n" \
970 " mulscc %%g1,%3,%%g1\n" \
971 " mulscc %%g1,%3,%%g1\n" \
972 " mulscc %%g1,0,%%g1\n" \
973 " add %%g1,%%o5,%0\n" \
974 " rd %%y,%1" \
975 : "=r" ((USItype) (w1)), \
976 "=r" ((USItype) (w0)) \
977 : "%rI" ((USItype) (u)), \
978 "r" ((USItype) (v)) \
979 : "g1", "o5" __AND_CLOBBER_CC)
980 #define UMUL_TIME 39 /* 39 instructions */
981 /* It's quite necessary to add this much assembler for the sparc.
982 The default udiv_qrnnd (in C) is more than 10 times slower! */
983 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
984 __asm__ ("! Inlined udiv_qrnnd\n" \
985 " mov 32,%%g1\n" \
986 " subcc %1,%2,%%g0\n" \
987 "1: bcs 5f\n" \
988 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
989 " sub %1,%2,%1 ! this kills msb of n\n" \
990 " addx %1,%1,%1 ! so this can't give carry\n" \
991 " subcc %%g1,1,%%g1\n" \
992 "2: bne 1b\n" \
993 " subcc %1,%2,%%g0\n" \
994 " bcs 3f\n" \
995 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
996 " b 3f\n" \
997 " sub %1,%2,%1 ! this kills msb of n\n" \
998 "4: sub %1,%2,%1\n" \
999 "5: addxcc %1,%1,%1\n" \
1000 " bcc 2b\n" \
1001 " subcc %%g1,1,%%g1\n" \
1002 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1003 " bne 4b\n" \
1004 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1005 " sub %1,%2,%1\n" \
1006 "3: xnor %0,0,%0\n" \
1007 " ! End of inline udiv_qrnnd" \
1008 : "=&r" ((USItype) (__q)), \
1009 "=&r" ((USItype) (__r)) \
1010 : "r" ((USItype) (__d)), \
1011 "1" ((USItype) (__n1)), \
1012 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1013 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1014 #endif /* __sparclite__ */
1015 #endif /* __sparc_v8__ */
1016 #endif /* sparc32 */
1017
1018 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1019 && W_TYPE_SIZE == 64
1020 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1021 __asm__ ("addcc %r4,%5,%1\n\t" \
1022 "add %r2,%3,%0\n\t" \
1023 "bcs,a,pn %%xcc, 1f\n\t" \
1024 "add %0, 1, %0\n" \
1025 "1:" \
1026 : "=r" ((UDItype)(sh)), \
1027 "=&r" ((UDItype)(sl)) \
1028 : "%rJ" ((UDItype)(ah)), \
1029 "rI" ((UDItype)(bh)), \
1030 "%rJ" ((UDItype)(al)), \
1031 "rI" ((UDItype)(bl)) \
1032 __CLOBBER_CC)
1033
1034 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1035 __asm__ ("subcc %r4,%5,%1\n\t" \
1036 "sub %r2,%3,%0\n\t" \
1037 "bcs,a,pn %%xcc, 1f\n\t" \
1038 "sub %0, 1, %0\n\t" \
1039 "1:" \
1040 : "=r" ((UDItype)(sh)), \
1041 "=&r" ((UDItype)(sl)) \
1042 : "rJ" ((UDItype)(ah)), \
1043 "rI" ((UDItype)(bh)), \
1044 "rJ" ((UDItype)(al)), \
1045 "rI" ((UDItype)(bl)) \
1046 __CLOBBER_CC)
1047
1048 #define umul_ppmm(wh, wl, u, v) \
1049 do { \
1050 UDItype tmp1, tmp2, tmp3, tmp4; \
1051 __asm__ __volatile__ ( \
1052 "srl %7,0,%3\n\t" \
1053 "mulx %3,%6,%1\n\t" \
1054 "srlx %6,32,%2\n\t" \
1055 "mulx %2,%3,%4\n\t" \
1056 "sllx %4,32,%5\n\t" \
1057 "srl %6,0,%3\n\t" \
1058 "sub %1,%5,%5\n\t" \
1059 "srlx %5,32,%5\n\t" \
1060 "addcc %4,%5,%4\n\t" \
1061 "srlx %7,32,%5\n\t" \
1062 "mulx %3,%5,%3\n\t" \
1063 "mulx %2,%5,%5\n\t" \
1064 "sethi %%hi(0x80000000),%2\n\t" \
1065 "addcc %4,%3,%4\n\t" \
1066 "srlx %4,32,%4\n\t" \
1067 "add %2,%2,%2\n\t" \
1068 "movcc %%xcc,%%g0,%2\n\t" \
1069 "addcc %5,%4,%5\n\t" \
1070 "sllx %3,32,%3\n\t" \
1071 "add %1,%3,%1\n\t" \
1072 "add %5,%2,%0" \
1073 : "=r" ((UDItype)(wh)), \
1074 "=&r" ((UDItype)(wl)), \
1075 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1076 : "r" ((UDItype)(u)), \
1077 "r" ((UDItype)(v)) \
1078 __CLOBBER_CC); \
1079 } while (0)
1080 #define UMUL_TIME 96
1081 #define UDIV_TIME 230
1082 #endif /* sparc64 */
1083
1084 #if defined (__vax__) && W_TYPE_SIZE == 32
1085 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1086 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1087 : "=g" ((USItype) (sh)), \
1088 "=&g" ((USItype) (sl)) \
1089 : "%0" ((USItype) (ah)), \
1090 "g" ((USItype) (bh)), \
1091 "%1" ((USItype) (al)), \
1092 "g" ((USItype) (bl)))
1093 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1094 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1095 : "=g" ((USItype) (sh)), \
1096 "=&g" ((USItype) (sl)) \
1097 : "0" ((USItype) (ah)), \
1098 "g" ((USItype) (bh)), \
1099 "1" ((USItype) (al)), \
1100 "g" ((USItype) (bl)))
1101 #define umul_ppmm(xh, xl, m0, m1) \
1102 do { \
1103 union { \
1104 UDItype __ll; \
1105 struct {USItype __l, __h;} __i; \
1106 } __xx; \
1107 USItype __m0 = (m0), __m1 = (m1); \
1108 __asm__ ("emul %1,%2,$0,%0" \
1109 : "=r" (__xx.__ll) \
1110 : "g" (__m0), \
1111 "g" (__m1)); \
1112 (xh) = __xx.__i.__h; \
1113 (xl) = __xx.__i.__l; \
1114 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1115 + (((SItype) __m1 >> 31) & __m0)); \
1116 } while (0)
1117 #define sdiv_qrnnd(q, r, n1, n0, d) \
1118 do { \
1119 union {DItype __ll; \
1120 struct {SItype __l, __h;} __i; \
1121 } __xx; \
1122 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1123 __asm__ ("ediv %3,%2,%0,%1" \
1124 : "=g" (q), "=g" (r) \
1125 : "g" (__xx.__ll), "g" (d)); \
1126 } while (0)
1127 #endif /* __vax__ */
1128
1129 #if defined (__z8000__) && W_TYPE_SIZE == 16
1130 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1131 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1132 : "=r" ((unsigned int)(sh)), \
1133 "=&r" ((unsigned int)(sl)) \
1134 : "%0" ((unsigned int)(ah)), \
1135 "r" ((unsigned int)(bh)), \
1136 "%1" ((unsigned int)(al)), \
1137 "rQR" ((unsigned int)(bl)))
1138 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1139 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1140 : "=r" ((unsigned int)(sh)), \
1141 "=&r" ((unsigned int)(sl)) \
1142 : "0" ((unsigned int)(ah)), \
1143 "r" ((unsigned int)(bh)), \
1144 "1" ((unsigned int)(al)), \
1145 "rQR" ((unsigned int)(bl)))
1146 #define umul_ppmm(xh, xl, m0, m1) \
1147 do { \
1148 union {long int __ll; \
1149 struct {unsigned int __h, __l;} __i; \
1150 } __xx; \
1151 unsigned int __m0 = (m0), __m1 = (m1); \
1152 __asm__ ("mult %S0,%H3" \
1153 : "=r" (__xx.__i.__h), \
1154 "=r" (__xx.__i.__l) \
1155 : "%1" (__m0), \
1156 "rQR" (__m1)); \
1157 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1158 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1159 + (((signed int) __m1 >> 15) & __m0)); \
1160 } while (0)
1161 #endif /* __z8000__ */
1162
1163 #endif /* __GNUC__ */
1164
1165 /* If this machine has no inline assembler, use C macros. */
1166
1167 #if !defined (add_ssaaaa)
1168 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1169 do { \
1170 UWtype __x; \
1171 __x = (al) + (bl); \
1172 (sh) = (ah) + (bh) + (__x < (al)); \
1173 (sl) = __x; \
1174 } while (0)
1175 #endif
1176
1177 #if !defined (sub_ddmmss)
1178 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1179 do { \
1180 UWtype __x; \
1181 __x = (al) - (bl); \
1182 (sh) = (ah) - (bh) - (__x > (al)); \
1183 (sl) = __x; \
1184 } while (0)
1185 #endif
1186
1187 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1188 smul_ppmm. */
1189 #if !defined (umul_ppmm) && defined (smul_ppmm)
1190 #define umul_ppmm(w1, w0, u, v) \
1191 do { \
1192 UWtype __w1; \
1193 UWtype __xm0 = (u), __xm1 = (v); \
1194 smul_ppmm (__w1, w0, __xm0, __xm1); \
1195 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1196 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1197 } while (0)
1198 #endif
1199
1200 /* If we still don't have umul_ppmm, define it using plain C. */
1201 #if !defined (umul_ppmm)
1202 #define umul_ppmm(w1, w0, u, v) \
1203 do { \
1204 UWtype __x0, __x1, __x2, __x3; \
1205 UHWtype __ul, __vl, __uh, __vh; \
1206 \
1207 __ul = __ll_lowpart (u); \
1208 __uh = __ll_highpart (u); \
1209 __vl = __ll_lowpart (v); \
1210 __vh = __ll_highpart (v); \
1211 \
1212 __x0 = (UWtype) __ul * __vl; \
1213 __x1 = (UWtype) __ul * __vh; \
1214 __x2 = (UWtype) __uh * __vl; \
1215 __x3 = (UWtype) __uh * __vh; \
1216 \
1217 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1218 __x1 += __x2; /* but this indeed can */ \
1219 if (__x1 < __x2) /* did we get it? */ \
1220 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1221 \
1222 (w1) = __x3 + __ll_highpart (__x1); \
1223 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1224 } while (0)
1225 #endif
1226
1227 #if !defined (__umulsidi3)
1228 #define __umulsidi3(u, v) \
1229 ({DWunion __w; \
1230 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1231 __w.ll; })
1232 #endif
1233
1234 /* Define this unconditionally, so it can be used for debugging. */
1235 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1236 do { \
1237 UWtype __d1, __d0, __q1, __q0; \
1238 UWtype __r1, __r0, __m; \
1239 __d1 = __ll_highpart (d); \
1240 __d0 = __ll_lowpart (d); \
1241 \
1242 __r1 = (n1) % __d1; \
1243 __q1 = (n1) / __d1; \
1244 __m = (UWtype) __q1 * __d0; \
1245 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1246 if (__r1 < __m) \
1247 { \
1248 __q1--, __r1 += (d); \
1249 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1250 if (__r1 < __m) \
1251 __q1--, __r1 += (d); \
1252 } \
1253 __r1 -= __m; \
1254 \
1255 __r0 = __r1 % __d1; \
1256 __q0 = __r1 / __d1; \
1257 __m = (UWtype) __q0 * __d0; \
1258 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1259 if (__r0 < __m) \
1260 { \
1261 __q0--, __r0 += (d); \
1262 if (__r0 >= (d)) \
1263 if (__r0 < __m) \
1264 __q0--, __r0 += (d); \
1265 } \
1266 __r0 -= __m; \
1267 \
1268 (q) = (UWtype) __q1 * __ll_B | __q0; \
1269 (r) = __r0; \
1270 } while (0)
1271
1272 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1273 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1274 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1275 #define udiv_qrnnd(q, r, nh, nl, d) \
1276 do { \
1277 USItype __r; \
1278 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1279 (r) = __r; \
1280 } while (0)
1281 #endif
1282
1283 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1284 #if !defined (udiv_qrnnd)
1285 #define UDIV_NEEDS_NORMALIZATION 1
1286 #define udiv_qrnnd __udiv_qrnnd_c
1287 #endif
1288
1289 #if !defined (count_leading_zeros)
1290 extern const UQItype __clz_tab[];
1291 #define count_leading_zeros(count, x) \
1292 do { \
1293 UWtype __xr = (x); \
1294 UWtype __a; \
1295 \
1296 if (W_TYPE_SIZE <= 32) \
1297 { \
1298 __a = __xr < ((UWtype)1<<2*__BITS4) \
1299 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1300 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1301 } \
1302 else \
1303 { \
1304 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1305 if (((__xr >> __a) & 0xff) != 0) \
1306 break; \
1307 } \
1308 \
1309 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1310 } while (0)
1311 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1312 #endif
1313
1314 #if !defined (count_trailing_zeros)
1315 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1316 defined in asm, but if it is not, the C version above is good enough. */
1317 #define count_trailing_zeros(count, x) \
1318 do { \
1319 UWtype __ctz_x = (x); \
1320 UWtype __ctz_c; \
1321 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1322 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1323 } while (0)
1324 #endif
1325
1326 #ifndef UDIV_NEEDS_NORMALIZATION
1327 #define UDIV_NEEDS_NORMALIZATION 0
1328 #endif
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