| blob | be4b12d0d74cdddb28f1de22a28ee775194c4a56 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
58 /* Not really meaningful values, but at least something. */
59 #ifndef SIMULTANEOUS_PREFETCHES
60 #define SIMULTANEOUS_PREFETCHES 3
61 #endif
62 #ifndef PREFETCH_BLOCK
63 #define PREFETCH_BLOCK 32
64 #endif
65 #ifndef HAVE_prefetch
66 #define HAVE_prefetch 0
67 #define CODE_FOR_prefetch 0
68 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
69 #endif
71 /* Give up the prefetch optimizations once we exceed a given threshhold.
72 It is unlikely that we would be able to optimize something in a loop
73 with so many detected prefetches. */
74 #define MAX_PREFETCHES 100
75 /* The number of prefetch blocks that are beneficial to fetch at once before
76 a loop with a known (and low) iteration count. */
77 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
78 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
79 since it is likely that the data are already in the cache. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
82 /* Parameterize some prefetch heuristics so they can be turned on and off
83 easily for performance testing on new architecures. These can be
84 defined in target-dependent files. */
86 /* Prefetch is worthwhile only when loads/stores are dense. */
87 #ifndef PREFETCH_ONLY_DENSE_MEM
88 #define PREFETCH_ONLY_DENSE_MEM 1
89 #endif
91 /* Define what we mean by "dense" loads and stores; This value divided by 256
92 is the minimum percentage of memory references that worth prefetching. */
93 #ifndef PREFETCH_DENSE_MEM
94 #define PREFETCH_DENSE_MEM 220
95 #endif
97 /* Do not prefetch for a loop whose iteration count is known to be low. */
98 #ifndef PREFETCH_NO_LOW_LOOPCNT
99 #define PREFETCH_NO_LOW_LOOPCNT 1
100 #endif
102 /* Define what we mean by a "low" iteration count. */
103 #ifndef PREFETCH_LOW_LOOPCNT
104 #define PREFETCH_LOW_LOOPCNT 32
105 #endif
107 /* Do not prefetch for a loop that contains a function call; such a loop is
108 probably not an internal loop. */
109 #ifndef PREFETCH_NO_CALL
110 #define PREFETCH_NO_CALL 1
111 #endif
113 /* Do not prefetch accesses with an extreme stride. */
114 #ifndef PREFETCH_NO_EXTREME_STRIDE
115 #define PREFETCH_NO_EXTREME_STRIDE 1
116 #endif
118 /* Define what we mean by an "extreme" stride. */
119 #ifndef PREFETCH_EXTREME_STRIDE
120 #define PREFETCH_EXTREME_STRIDE 4096
121 #endif
123 /* Define a limit to how far apart indices can be and still be merged
124 into a single prefetch. */
125 #ifndef PREFETCH_EXTREME_DIFFERENCE
126 #define PREFETCH_EXTREME_DIFFERENCE 4096
127 #endif
129 /* Issue prefetch instructions before the loop to fetch data to be used
130 in the first few loop iterations. */
131 #ifndef PREFETCH_BEFORE_LOOP
132 #define PREFETCH_BEFORE_LOOP 1
133 #endif
135 /* Do not handle reversed order prefetches (negative stride). */
136 #ifndef PREFETCH_NO_REVERSE_ORDER
137 #define PREFETCH_NO_REVERSE_ORDER 1
138 #endif
140 /* Prefetch even if the GIV is in conditional code. */
141 #ifndef PREFETCH_CONDITIONAL
142 #define PREFETCH_CONDITIONAL 1
143 #endif
145 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
146 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
148 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
150 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
152 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
153 ((REGNO) < FIRST_PSEUDO_REGISTER \
154 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
157 /* Vector mapping INSN_UIDs to luids.
158 The luids are like uids but increase monotonically always.
159 We use them to see whether a jump comes from outside a given loop. */
163 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
164 number the insn is contained in. */
168 /* 1 + largest uid of any insn. */
172 /* 1 + luid of last insn. */
176 /* Number of loops detected in current function. Used as index to the
177 next few tables. */
181 /* Bound on pseudo register number before loop optimization.
182 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
185 /* The value to pass to the next call of reg_scan_update. */
187 \f
188 /* During the analysis of a loop, a chain of `struct movable's
189 is made to record all the movable insns found.
190 Then the entire chain can be scanned to decide which to move. */
192 struct movable
193 {
198 of any registers used within the LIBCALL. */
200 that must be moved with this one. */
203 may be adjusted when matching movables
204 that load the same value are found. */
206 including other movables that force this
207 or match this one. */
211 /* If PARTIAL is 1, GLOBAL means something different:
212 that the reg is live outside the range from where it is set
213 to the following label. */
217 In particular, moving it does not make it
218 invariant. */
220 load SRC, rather than copying INSN. */
222 first insn of a consecutive sets group. */
225 that we should avoid changing when clearing
226 the rest of the reg. */
230 };
235 /* Forward declarations. */
250 #if 0
252 #endif
282 rtx *));
365 {
366 rtx r1;
367 rtx r2;
371 {
372 rtx match;
373 rtx replacement;
374 rtx insn;
377 /* Nonzero iff INSN is between START and END, inclusive. */
378 #define INSN_IN_RANGE_P(INSN, START, END) \
379 (INSN_UID (INSN) < max_uid_for_loop \
380 && INSN_LUID (INSN) >= INSN_LUID (START) \
381 && INSN_LUID (INSN) <= INSN_LUID (END))
383 /* Indirect_jump_in_function is computed once per function. */
391 rtx));
392 \f
393 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
394 copy the value of the strength reduced giv to its original register. */
397 /* Cost of using a register, to normalize the benefits of a giv. */
400 void
402 {
408 }
409 \f
410 /* Compute the mapping from uids to luids.
411 LUIDs are numbers assigned to insns, like uids,
412 except that luids increase monotonically through the code.
413 Start at insn START and stop just before END. Assign LUIDs
414 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
415 static int
419 {
421 rtx insn;
424 {
427 /* Don't assign luids to line-number NOTEs, so that the distance in
428 luids between two insns is not affected by -g. */
432 else
433 /* Give a line number note the same luid as preceding insn. */
435 }
437 }
438 \f
439 /* Entry point of this file. Perform loop optimization
440 on the current function. F is the first insn of the function
441 and DUMPFILE is a stream for output of a trace of actions taken
442 (or 0 if none should be output). */
444 void
446 /* f is the first instruction of a chain of insns for one function */
447 rtx f;
450 {
451 rtx insn;
466 /* Count the number of loops. */
470 {
473 max_loop_num++;
474 }
476 /* Don't waste time if no loops. */
482 /* Get size to use for tables indexed by uids.
483 Leave some space for labels allocated by find_and_verify_loops. */
490 /* Allocate storage for array of loops. */
494 /* Find and process each loop.
495 First, find them, and record them in order of their beginnings. */
498 /* Allocate and initialize auxiliary loop information. */
503 /* Now find all register lifetimes. This must be done after
504 find_and_verify_loops, because it might reorder the insns in the
505 function. */
508 /* This must occur after reg_scan so that registers created by gcse
509 will have entries in the register tables.
511 We could have added a call to reg_scan after gcse_main in toplev.c,
512 but moving this call to init_alias_analysis is more efficient. */
515 /* See if we went too far. Note that get_max_uid already returns
516 one more that the maximum uid of all insn. */
519 /* Now reset it to the actual size we need. See above. */
522 /* find_and_verify_loops has already called compute_luids, but it
523 might have rearranged code afterwards, so we need to recompute
524 the luids now. */
527 /* Don't leave gaps in uid_luid for insns that have been
528 deleted. It is possible that the first or last insn
529 using some register has been deleted by cross-jumping.
530 Make sure that uid_luid for that former insn's uid
531 points to the general area where that insn used to be. */
533 {
537 }
542 /* Determine if the function has indirect jump. On some systems
543 this prevents low overhead loop instructions from being used. */
546 /* Now scan the loops, last ones first, since this means inner ones are done
547 before outer ones. */
549 {
554 }
558 /* Clean up. */
563 }
564 \f
565 /* Returns the next insn, in execution order, after INSN. START and
566 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
567 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
568 insn-stream; it is used with loops that are entered near the
569 bottom. */
571 static rtx
574 rtx insn;
575 {
579 {
581 /* Go to the top of the loop, and continue there. */
583 else
584 /* We're done. */
586 }
589 /* We're done. */
593 }
595 /* Optimize one loop described by LOOP. */
597 /* ??? Could also move memory writes out of loops if the destination address
598 is invariant, the source is invariant, the memory write is not volatile,
599 and if we can prove that no read inside the loop can read this address
600 before the write occurs. If there is a read of this address after the
601 write, then we can also mark the memory read as invariant. */
603 static void
607 {
613 rtx p;
614 /* 1 if we are scanning insns that could be executed zero times. */
616 /* 1 if we are scanning insns that might never be executed
617 due to a subroutine call which might exit before they are reached. */
619 /* Jump insn that enters the loop, or 0 if control drops in. */
621 /* Number of insns in the loop. */
625 /* The SET from an insn, if it is the only SET in the insn. */
627 /* Chain describing insns movable in current loop. */
629 /* Ratio of extra register life span we can justify
630 for saving an instruction. More if loop doesn't call subroutines
631 since in that case saving an insn makes more difference
632 and more registers are available. */
634 /* Nonzero if we are scanning instructions in a sub-loop. */
643 /* Determine whether this loop starts with a jump down to a test at
644 the end. This will occur for a small number of loops with a test
645 that is too complex to duplicate in front of the loop.
647 We search for the first insn or label in the loop, skipping NOTEs.
648 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
649 (because we might have a loop executed only once that contains a
650 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
651 (in case we have a degenerate loop).
653 Note that if we mistakenly think that a loop is entered at the top
654 when, in fact, it is entered at the exit test, the only effect will be
655 slightly poorer optimization. Making the opposite error can generate
656 incorrect code. Since very few loops now start with a jump to the
657 exit test, the code here to detect that case is very conservative. */
660 p != loop_end
666 ;
670 /* If loop end is the end of the current function, then emit a
671 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
672 note insn. This is the position we use when sinking insns out of
673 the loop. */
676 else
679 /* Set up variables describing this loop. */
683 /* If loop has a jump before the first label,
684 the true entry is the target of that jump.
685 Start scan from there.
686 But record in LOOP->TOP the place where the end-test jumps
687 back to so we can scan that after the end of the loop. */
689 {
692 /* Loop entry must be unconditional jump (and not a RETURN) */
695 /* Check to see whether the jump actually
696 jumps out of the loop (meaning it's no loop).
697 This case can happen for things like
698 do {..} while (0). If this label was generated previously
699 by loop, we can't tell anything about it and have to reject
700 the loop. */
702 {
705 }
706 }
708 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
709 as required by loop_reg_used_before_p. So skip such loops. (This
710 test may never be true, but it's best to play it safe.)
712 Also, skip loops where we do not start scanning at a label. This
713 test also rejects loops starting with a JUMP_INSN that failed the
714 test above. */
718 {
723 }
725 /* Allocate extra space for REGs that might be created by load_mems.
726 We allocate a little extra slop as well, in the hopes that we
727 won't have to reallocate the regs array. */
732 {
738 }
740 /* Scan through the loop finding insns that are safe to move.
741 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
742 this reg will be considered invariant for subsequent insns.
743 We consider whether subsequent insns use the reg
744 in deciding whether it is worth actually moving.
746 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
747 and therefore it is possible that the insns we are scanning
748 would never be executed. At such times, we must make sure
749 that it is safe to execute the insn once instead of zero times.
750 When MAYBE_NEVER is 0, all insns will be executed at least once
751 so that is not a problem. */
756 {
758 in_libcall--;
760 {
763 in_libcall++;
767 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
769 #endif
771 {
778 /* Figure out what to use as a source of this insn. If a
779 REG_EQUIV note is given or if a REG_EQUAL note with a
780 constant operand is specified, use it as the source and
781 mark that we should move this insn by calling
782 emit_move_insn rather that duplicating the insn.
784 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
785 note is present. */
789 else
790 {
795 {
797 /* A libcall block can use regs that don't appear in
798 the equivalent expression. To move the libcall,
799 we must move those regs too. */
801 }
802 }
804 /* For parallels, add any possible uses to the depencies, as
805 we can't move the insn without resolving them first. */
807 {
809 {
812 dependencies
814 dependencies);
815 }
816 }
818 /* Don't try to optimize a register that was made
819 by loop-optimization for an inner loop.
820 We don't know its life-span, so we can't compute
821 the benefit. */
823 ;
825 than the one where it is set (meaning that
826 something after this point in the loop might
827 depend on its value before the set). */
829 /* And the set is not guaranteed to be executed once
830 the loop starts, or the value before the set is
831 needed before the set occurs...
833 ??? Note we have quadratic behavior here, mitigated
834 by the fact that the previous test will often fail for
835 large loops. Rather than re-scanning the entire loop
836 each time for register usage, we should build tables
837 of the register usage and use them here instead. */
838 && (maybe_never
840 /* It is unsafe to move the set.
842 This code used to consider it OK to move a set of a variable
843 which was not created by the user and not used in an exit
844 test.
845 That behavior is incorrect and was removed. */
846 ;
849 || (tem2
852 || (tem1
853 = consec_sets_invariant_p
856 p)))
857 /* If the insn can cause a trap (such as divide by zero),
858 can't move it unless it's guaranteed to be executed
859 once loop is entered. Even a function call might
860 prevent the trap insn from being reached
861 (since it might exit!) */
864 {
868 /* A potential lossage is where we have a case where two insns
869 can be combined as long as they are both in the loop, but
870 we move one of them outside the loop. For large loops,
871 this can lose. The most common case of this is the address
872 of a function being called.
874 Therefore, if this register is marked as being used
875 exactly once if we are in a loop with calls
876 (a "large loop"), see if we can replace the usage of
877 this register with the source of this SET. If we can,
878 delete this insn.
880 Don't do this if P has a REG_RETVAL note or if we have
881 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
893 && (! SMALL_REGISTER_CLASSES
897 /* This test is not redundant; SET_SRC (set) might be
898 a call-clobbered register and the life of REGNO
899 might span a call. */
906 {
907 /* Replace any usage in a REG_EQUAL note. Must copy
908 the new source, so that we don't get rtx sharing
909 between the SET_SOURCE and REG_NOTES of insn p. */
911 = (replace_rtx
917 i++)
920 }
929 m->consec
939 /* Set M->cond if either loop_invariant_p
940 or consec_sets_invariant_p returned 2
941 (only conditionally invariant). */
951 /* Add M to the end of the chain MOVABLES. */
955 {
956 /* It is possible for the first instruction to have a
957 REG_EQUAL note but a non-invariant SET_SRC, so we must
958 remember the status of the first instruction in case
959 the last instruction doesn't have a REG_EQUAL note. */
962 /* Skip this insn, not checking REG_LIBCALL notes. */
964 /* Skip the consecutive insns, if there are any. */
966 /* Back up to the last insn of the consecutive group. */
969 /* We must now reset m->move_insn, m->is_equiv, and
970 possibly m->set_src to correspond to the effects of
971 all the insns. */
975 else
976 {
980 else
983 }
984 m->is_equiv
986 }
987 }
988 /* If this register is always set within a STRICT_LOW_PART
989 or set to zero, then its high bytes are constant.
990 So clear them outside the loop and within the loop
991 just load the low bytes.
992 We must check that the machine has an instruction to do so.
993 Also, if the value loaded into the register
994 depends on the same register, this cannot be done. */
1004 {
1007 {
1021 /* If the insn may not be executed on some cycles,
1022 we can't clear the whole reg; clear just high part.
1023 Not even if the reg is used only within this loop.
1024 Consider this:
1025 while (1)
1026 while (s != t) {
1027 if (foo ()) x = *s;
1028 use (x);
1029 }
1030 Clearing x before the inner loop could clobber a value
1031 being saved from the last time around the outer loop.
1032 However, if the reg is not used outside this loop
1033 and all uses of the register are in the same
1034 basic block as the store, there is no problem.
1036 If this insn was made by loop, we don't know its
1037 INSN_LUID and hence must make a conservative
1038 assumption. */
1041 || (labels_in_range_p
1045 else
1054 i++)
1056 /* Add M to the end of the chain MOVABLES. */
1058 }
1059 }
1060 }
1061 }
1062 /* Past a call insn, we get to insns which might not be executed
1063 because the call might exit. This matters for insns that trap.
1064 Constant and pure call insns always return, so they don't count. */
1067 /* Past a label or a jump, we get to insns for which we
1068 can't count on whether or how many times they will be
1069 executed during each iteration. Therefore, we can
1070 only move out sets of trivial variables
1071 (those not used after the loop). */
1072 /* Similar code appears twice in strength_reduce. */
1074 /* If we enter the loop in the middle, and scan around to the
1075 beginning, don't set maybe_never for that. This must be an
1076 unconditional jump, otherwise the code at the top of the
1077 loop might never be executed. Unconditional jumps are
1078 followed by a barrier then the loop_end. */
1084 {
1085 /* At the virtual top of a converted loop, insns are again known to
1086 be executed: logically, the loop begins here even though the exit
1087 code has been duplicated. */
1091 loop_depth++;
1093 loop_depth--;
1094 }
1095 }
1097 /* If one movable subsumes another, ignore that other. */
1101 /* For each movable insn, see if the reg that it loads
1102 leads when it dies right into another conditionally movable insn.
1103 If so, record that the second insn "forces" the first one,
1104 since the second can be moved only if the first is. */
1108 /* See if there are multiple movable insns that load the same value.
1109 If there are, make all but the first point at the first one
1110 through the `match' field, and add the priorities of them
1111 all together as the priority of the first. */
1115 /* Now consider each movable insn to decide whether it is worth moving.
1116 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1118 Generally this increases code size, so do not move moveables when
1119 optimizing for code size. */
1122 {
1125 /* Recalculate regs->array if move_movables has created new
1126 registers. */
1128 {
1134 ;
1139 }
1140 }
1142 /* Now candidates that still are negative are those not moved.
1143 Change regs->array[I].set_in_loop to indicate that those are not actually
1144 invariant. */
1149 /* Now that we've moved some things out of the loop, we might be able to
1150 hoist even more memory references. */
1153 /* Recalculate regs->array if load_mems has created new registers. */
1161 ;
1168 {
1170 /* Ensure our label doesn't go away. */
1181 }
1184 /* The movable information is required for strength reduction. */
1190 }
1191 \f
1192 /* Add elements to *OUTPUT to record all the pseudo-regs
1193 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1195 void
1199 {
1207 {
1225 }
1229 {
1233 {
1242 }
1243 }
1244 }
1245 \f
1246 /* Check what regs are referred to in the libcall block ending with INSN,
1247 aside from those mentioned in the equivalent value.
1248 If there are none, return 0.
1249 If there are one or more, return an EXPR_LIST containing all of them. */
1251 rtx
1254 {
1259 /* First, find all the regs used in the libcall block
1260 that are not mentioned as inputs to the result. */
1263 {
1268 }
1271 }
1272 \f
1273 /* Return 1 if all uses of REG
1274 are between INSN and the end of the basic block. */
1276 static int
1279 {
1281 rtx p;
1286 /* Search this basic block for the already recorded last use of the reg. */
1288 {
1290 {
1296 /* Ordinary insn: if this is the last use, we win. */
1302 /* Jump insn: if this is the last use, we win. */
1305 /* Otherwise, it's the end of the basic block, so we lose. */
1310 /* It's the end of the basic block, so we lose. */
1315 }
1316 }
1318 /* The "last use" that was recorded can't be found after the first
1319 use. This can happen when the last use was deleted while
1320 processing an inner loop, this inner loop was then completely
1321 unrolled, and the outer loop is always exited after the inner loop,
1322 so that everything after the first use becomes a single basic block. */
1324 }
1325 \f
1326 /* Compute the benefit of eliminating the insns in the block whose
1327 last insn is LAST. This may be a group of insns used to compute a
1328 value directly or can contain a library call. */
1330 static int
1332 rtx last;
1333 {
1334 rtx insn;
1339 {
1342 routine. */
1346 benefit++;
1347 }
1350 }
1351 \f
1352 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1354 static rtx
1356 rtx insn;
1358 {
1360 {
1361 rtx temp;
1363 /* If first insn of libcall sequence, skip to end. */
1364 /* Do this at start of loop, since INSN is guaranteed to
1365 be an insn here. */
1370 do
1373 }
1376 }
1378 /* Ignore any movable whose insn falls within a libcall
1379 which is part of another movable.
1380 We make use of the fact that the movable for the libcall value
1381 was made later and so appears later on the chain. */
1383 static void
1386 {
1390 {
1391 /* Is this a movable for the value of a libcall? */
1394 {
1395 rtx insn;
1396 /* Check for earlier movables inside that range,
1397 and mark them invalid. We cannot use LUIDs here because
1398 insns created by loop.c for prior loops don't have LUIDs.
1399 Rather than reject all such insns from movables, we just
1400 explicitly check each insn in the libcall (since invariant
1401 libcalls aren't that common). */
1406 }
1407 }
1408 }
1410 /* For each movable insn, see if the reg that it loads
1411 leads when it dies right into another conditionally movable insn.
1412 If so, record that the second insn "forces" the first one,
1413 since the second can be moved only if the first is. */
1415 static void
1418 {
1422 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1424 {
1427 /* ??? Could this be a bug? What if CSE caused the
1428 register of M1 to be used after this insn?
1429 Since CSE does not update regno_last_uid,
1430 this insn M->insn might not be where it dies.
1431 But very likely this doesn't matter; what matters is
1432 that M's reg is computed from M1's reg. */
1437 /* If m->consec, m->set_src isn't valid. */
1441 /* Increase the priority of the moving the first insn
1442 since it permits the second to be moved as well. */
1444 {
1448 }
1449 }
1450 }
1451 \f
1452 /* Find invariant expressions that are equal and can be combined into
1453 one register. */
1455 static void
1459 {
1464 /* Regs that are set more than once are not allowed to match
1465 or be matched. I'm no longer sure why not. */
1466 /* Only pseudo registers are allowed to match or be matched,
1467 since move_movables does not validate the change. */
1468 /* Perhaps testing m->consec_sets would be more appropriate here? */
1474 {
1481 /* We want later insns to match the first one. Don't make the first
1482 one match any later ones. So start this loop at m->next. */
1487 /* A reg used outside the loop mustn't be eliminated. */
1489 /* A reg used for zero-extending mustn't be eliminated. */
1492 ||
1493 (
1494 /* Can combine regs with different modes loaded from the
1495 same constant only if the modes are the same or
1496 if both are integer modes with M wider or the same
1497 width as M1. The check for integer is redundant, but
1498 safe, since the only case of differing destination
1499 modes with equal sources is when both sources are
1500 VOIDmode, i.e., CONST_INT. */
1506 /* See if the source of M1 says it matches M. */
1513 {
1519 }
1520 }
1522 /* Now combine the regs used for zero-extension.
1523 This can be done for those not marked `global'
1524 provided their lives don't overlap. */
1528 {
1531 /* Combine all the registers for extension from mode MODE.
1532 Don't combine any that are used outside this loop. */
1536 {
1543 {
1544 /* First one: don't check for overlap, just record it. */
1547 }
1549 /* Make sure they extend to the same mode.
1550 (Almost always true.) */
1554 /* We already have one: check for overlap with those
1555 already combined together. */
1562 /* No overlap: we can combine this with the others. */
1568 overlap:
1569 ;
1570 }
1571 }
1573 /* Clean up. */
1575 }
1577 /* Returns the number of movable instructions in LOOP that were not
1578 moved outside the loop. */
1580 static int
1583 {
1592 }
1594 \f
1595 /* Return 1 if regs X and Y will become the same if moved. */
1597 static int
1601 {
1618 }
1620 /* Return 1 if X and Y are identical-looking rtx's.
1621 This is the Lisp function EQUAL for rtx arguments.
1623 If two registers are matching movables or a movable register and an
1624 equivalent constant, consider them equal. */
1626 static int
1631 {
1645 /* If we have a register and a constant, they may sometimes be
1646 equal. */
1649 {
1654 }
1657 {
1662 }
1664 /* Otherwise, rtx's of different codes cannot be equal. */
1668 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1669 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1674 /* These three types of rtx's can be compared nonrecursively. */
1683 /* Compare the elements. If any pair of corresponding elements
1684 fail to match, return 0 for the whole things. */
1688 {
1690 {
1702 /* Two vectors must have the same length. */
1706 /* And the corresponding elements must match. */
1725 /* These are just backpointers, so they don't matter. */
1731 /* It is believed that rtx's at this level will never
1732 contain anything but integers and other rtx's,
1733 except for within LABEL_REFs and SYMBOL_REFs. */
1736 }
1737 }
1739 }
1740 \f
1741 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1742 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1743 references is incremented once for each added note. */
1745 static void
1747 rtx x;
1748 rtx insns;
1749 {
1753 rtx insn;
1756 {
1757 /* This code used to ignore labels that referred to dispatch tables to
1758 avoid flow generating (slighly) worse code.
1760 We no longer ignore such label references (see LABEL_REF handling in
1761 mark_jump_label for additional information). */
1764 {
1769 }
1770 }
1774 {
1780 }
1781 }
1782 \f
1783 /* Scan MOVABLES, and move the insns that deserve to be moved.
1784 If two matching movables are combined, replace one reg with the
1785 other throughout. */
1787 static void
1793 {
1798 rtx p;
1801 /* Map of pseudo-register replacements to handle combining
1802 when we move several insns that load the same value
1803 into different pseudo-registers. */
1808 {
1809 /* Describe this movable insn. */
1812 {
1833 }
1835 /* Ignore the insn if it's already done (it matched something else).
1836 Otherwise, see if it is now safe to move. */
1848 {
1850 rtx p;
1853 /* We have an insn that is safe to move.
1854 Compute its desirability. */
1865 /* An insn MUST be moved if we already moved something else
1866 which is safe only if this one is moved too: that is,
1867 if already_moved[REGNO] is nonzero. */
1869 /* An insn is desirable to move if the new lifetime of the
1870 register is no more than THRESHOLD times the old lifetime.
1871 If it's not desirable, it means the loop is so big
1872 that moving won't speed things up much,
1873 and it is liable to make register usage worse. */
1875 /* It is also desirable to move if it can be moved at no
1876 extra cost because something else was already moved. */
1879 || flag_move_all_movables
1884 {
1889 /* Now move the insns that set the reg. */
1892 {
1895 /* Find the end of this chain of matching regs.
1896 Thus, we load each reg in the chain from that one reg.
1897 And that reg is loaded with 0 directly,
1898 since it has ->match == 0. */
1904 /* Mark the moved, invariant reg as being allowed to
1905 share a hard reg with the other matching invariant. */
1909 regs_may_share
1912 regs_may_share));
1920 }
1921 /* If we are to re-generate the item being moved with a
1922 new move insn, first delete what we have and then emit
1923 the move insn before the loop. */
1925 {
1929 {
1930 /* If this is the first insn of a library call sequence,
1931 something is very wrong. */
1936 /* If this is the last insn of a libcall sequence, then
1937 delete every insn in the sequence except the last.
1938 The last insn is handled in the normal manner. */
1941 {
1945 }
1950 /* simplify_giv_expr expects that it can walk the insns
1951 at m->insn forwards and see this old sequence we are
1952 tossing here. delete_insn does preserve the next
1953 pointers, but when we skip over a NOTE we must fix
1954 it up. Otherwise that code walks into the non-deleted
1955 insn stream. */
1958 }
1976 /* The more regs we move, the less we like moving them. */
1978 }
1979 else
1980 {
1982 {
1985 /* If first insn of libcall sequence, skip to end. */
1986 /* Do this at start of loop, since p is guaranteed to
1987 be an insn here. */
1992 /* If last insn of libcall sequence, move all
1993 insns except the last before the loop. The last
1994 insn is handled in the normal manner. */
1997 {
2005 {
2006 rtx body;
2007 rtx n;
2008 rtx next;
2015 /* Find the next insn after TEMP,
2016 not counting USE or NOTE insns. */
2024 /* If that is the call, this may be the insn
2025 that loads the function address.
2027 Extract the function address from the insn
2028 that loads it into a register.
2029 If this insn was cse'd, we get incorrect code.
2031 So emit a new move insn that copies the
2032 function address into the register that the
2033 call insn will use. flow.c will delete any
2034 redundant stores that we have created. */
2039 NULL_RTX)))
2040 {
2046 }
2047 /* We have the call insn.
2048 If it uses the register we suspect it might,
2049 load it with the correct address directly. */
2054 gen_move_insn
2058 {
2060 /* Because the USAGE information potentially
2061 contains objects other than hard registers
2062 we need to copy it. */
2066 }
2067 else
2076 }
2079 }
2081 {
2082 /* P sets REG to zero; but we should clear only
2083 the bits that are not covered by the mode
2084 m->savemode. */
2086 rtx sequence;
2087 rtx tem;
2090 tem = expand_simple_binop
2103 }
2105 {
2107 /* Because the USAGE information potentially
2108 contains objects other than hard registers
2109 we need to copy it. */
2113 }
2115 {
2116 rtx seq;
2117 /* The SET_SRC might not be invariant, so we must
2118 use the REG_EQUAL note. */
2130 }
2131 else
2135 {
2139 /* If there is a REG_EQUAL note present whose value
2140 is not loop invariant, then delete it, since it
2141 may cause problems with later optimization passes.
2142 It is possible for cse to create such notes
2143 like this as a result of record_jump_cond. */
2148 }
2157 /* If library call, now fix the REG_NOTES that contain
2158 insn pointers, namely REG_LIBCALL on FIRST
2159 and REG_RETVAL on I1. */
2161 {
2165 }
2171 /* simplify_giv_expr expects that it can walk the insns
2172 at m->insn forwards and see this old sequence we are
2173 tossing here. delete_insn does preserve the next
2174 pointers, but when we skip over a NOTE we must fix
2175 it up. Otherwise that code walks into the non-deleted
2176 insn stream. */
2179 }
2181 /* The more regs we move, the less we like moving them. */
2183 }
2185 /* Any other movable that loads the same register
2186 MUST be moved. */
2189 /* This reg has been moved out of one loop. */
2192 /* The reg set here is now invariant. */
2194 {
2198 }
2202 /* Change the length-of-life info for the register
2203 to say it lives at least the full length of this loop.
2204 This will help guide optimizations in outer loops. */
2207 /* This is the old insn before all the moved insns.
2208 We can't use the moved insn because it is out of range
2209 in uid_luid. Only the old insns have luids. */
2214 /* Combine with this moved insn any other matching movables. */
2219 {
2220 rtx temp;
2222 /* Schedule the reg loaded by M1
2223 for replacement so that shares the reg of M.
2224 If the modes differ (only possible in restricted
2225 circumstances, make a SUBREG.
2227 Note this assumes that the target dependent files
2228 treat REG and SUBREG equally, including within
2229 GO_IF_LEGITIMATE_ADDRESS and in all the
2230 predicates since we never verify that replacing the
2231 original register with a SUBREG results in a
2232 recognizable insn. */
2235 else
2240 /* Get rid of the matching insn
2241 and prevent further processing of it. */
2244 /* if library call, delete all insns. */
2246 NULL_RTX)))
2248 else
2251 /* Any other movable that loads the same register
2252 MUST be moved. */
2255 /* The reg merged here is now invariant,
2256 if the reg it matches is invariant. */
2258 {
2262 i++)
2264 }
2265 }
2266 }
2269 }
2275 }
2280 /* Go through all the instructions in the loop, making
2281 all the register substitutions scheduled in REG_MAP. */
2285 {
2289 }
2291 /* Clean up. */
2294 }
2297 static void
2301 {
2304 else
2307 }
2310 static void
2313 {
2318 {
2321 }
2322 }
2323 \f
2324 #if 0
2325 /* Scan X and replace the address of any MEM in it with ADDR.
2326 REG is the address that MEM should have before the replacement. */
2328 static void
2331 {
2340 {
2352 /* Short cut for very common case. */
2357 /* Short cut for very common case. */
2362 /* If this MEM uses a reg other than the one we expected,
2363 something is wrong. */
2371 }
2375 {
2379 {
2383 }
2384 }
2385 }
2386 #endif
2387 \f
2388 /* Return the number of memory refs to addresses that vary
2389 in the rtx X. */
2391 static int
2394 rtx x;
2395 {
2406 {
2423 }
2428 {
2432 {
2436 }
2437 }
2439 }
2440 \f
2441 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2442 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2443 `unknown_address_altered', `unknown_constant_address_altered', and
2444 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2445 list `store_mems' in LOOP. */
2447 static void
2450 {
2452 rtx insn;
2456 /* The label after END. Jumping here is just like falling off the
2457 end of the loop. We use next_nonnote_insn instead of next_label
2458 as a hedge against the (pathological) case where some actual insn
2459 might end up between the two. */
2478 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2483 {
2485 {
2488 }
2489 }
2493 {
2495 {
2498 {
2500 /* Count number of loops contained in this one. */
2502 }
2509 {
2512 }
2522 {
2526 {
2531 {
2534 }
2535 else
2536 {
2539 }
2541 do
2542 {
2544 {
2546 {
2547 /* Something tricky. */
2550 }
2553 {
2554 /* A jump outside the current loop. */
2557 }
2558 }
2562 }
2564 }
2565 else
2566 {
2567 /* A return, or something tricky. */
2569 }
2570 }
2571 /* FALLTHRU */
2592 }
2593 }
2595 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2597 anywhere. */
2599 /* We don't want loads for MEMs moved to a location before the
2600 one at which their stack memory becomes allocated. (Note
2601 that this is not a problem for malloc, etc., since those
2602 require actual function calls. */
2603 && ! current_function_calls_alloca
2604 /* There are ways to leave the loop other than falling off the
2605 end. */
2611 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2612 that loop_invariant_p and load_mems can use true_dependence
2613 to determine what is really clobbered. */
2615 {
2618 loop_info->store_mems
2620 }
2622 {
2626 loop_info->store_mems
2628 }
2629 }
2630 \f
2631 /* Invalidate all loops containing LABEL. */
2633 static void
2635 rtx label;
2636 {
2640 }
2642 /* Scan the function looking for loops. Record the start and end of each loop.
2643 Also mark as invalid loops any loops that contain a setjmp or are branched
2644 to from outside the loop. */
2646 static void
2648 rtx f;
2650 {
2651 rtx insn;
2652 rtx label;
2662 /* If there are jumps to undefined labels,
2663 treat them as jumps out of any/all loops.
2664 This also avoids writing past end of tables when there are no loops. */
2667 /* Find boundaries of loops, mark which loops are contained within
2668 loops, and invalidate loops that have setjmp. */
2673 {
2676 {
2680 num_loops++;
2704 }
2708 {
2709 /* In this case, we must invalidate our current loop and any
2710 enclosing loop. */
2712 {
2718 }
2719 }
2721 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2722 enclosing loop, but this doesn't matter. */
2724 }
2726 /* Any loop containing a label used in an initializer must be invalidated,
2727 because it can be jumped into from anywhere. */
2731 /* Any loop containing a label used for an exception handler must be
2732 invalidated, because it can be jumped into from anywhere. */
2735 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2736 loop that it is not contained within, that loop is marked invalid.
2737 If any INSN or CALL_INSN uses a label's address, then the loop containing
2738 that label is marked invalid, because it could be jumped into from
2739 anywhere.
2741 Also look for blocks of code ending in an unconditional branch that
2742 exits the loop. If such a block is surrounded by a conditional
2743 branch around the block, move the block elsewhere (see below) and
2744 invert the jump to point to the code block. This may eliminate a
2745 label in our loop and will simplify processing by both us and a
2746 possible second cse pass. */
2750 {
2754 {
2758 }
2765 /* See if this is an unconditional branch outside the loop. */
2773 {
2774 rtx p;
2780 /* Go backwards until we reach the start of the loop, a label,
2781 or a JUMP_INSN. */
2788 ;
2790 /* Check for the case where we have a jump to an inner nested
2791 loop, and do not perform the optimization in that case. */
2794 {
2797 {
2802 }
2803 }
2805 /* Make sure that the target of P is within the current loop. */
2811 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2812 we have a block of code to try to move.
2814 We look backward and then forward from the target of INSN
2815 to find a BARRIER at the same loop depth as the target.
2816 If we find such a BARRIER, we make a new label for the start
2817 of the block, invert the jump in P and point it to that label,
2818 and move the block of code to the spot we found. */
2823 /* Just ignore jumps to labels that were never emitted.
2824 These always indicate compilation errors. */
2828 /* If it's not safe to move the sequence, then we
2829 mustn't try. */
2832 {
2833 rtx target
2837 rtx tmp;
2839 /* Search for possible garbage past the conditional jumps
2840 and look for the last barrier. */
2848 /* Don't move things inside a tablejump. */
2861 /* Don't move things inside a tablejump. */
2872 {
2876 /* Ensure our label doesn't go away. */
2879 /* Verify that uid_loop is large enough and that
2880 we can invert P. */
2882 {
2885 /* If no suitable BARRIER was found, create a suitable
2886 one before TARGET. Since TARGET is a fall through
2887 path, we'll need to insert an jump around our block
2888 and add a BARRIER before TARGET.
2890 This creates an extra unconditional jump outside
2891 the loop. However, the benefits of removing rarely
2892 executed instructions from inside the loop usually
2893 outweighs the cost of the extra unconditional jump
2894 outside the loop. */
2896 {
2897 rtx temp;
2904 }
2906 /* Include the BARRIER after INSN and copy the
2907 block after LOC. */
2912 /* All those insns are now in TARGET_LOOP. */
2918 /* The label jumped to by INSN is no longer a loop
2919 exit. Unless INSN does not have a label (e.g.,
2920 it is a RETURN insn), search loop->exit_labels
2921 to find its label_ref, and remove it. Also turn
2922 off LABEL_OUTSIDE_LOOP_P bit. */
2924 {
2926 r;
2929 {
2933 else
2936 }
2942 /* If we didn't find it, then something is
2943 wrong. */
2946 }
2948 /* P is now a jump outside the loop, so it must be put
2949 in loop->exit_labels, and marked as such.
2950 The easiest way to do this is to just call
2951 mark_loop_jump again for P. */
2954 /* If INSN now jumps to the insn after it,
2955 delete INSN. */
2960 }
2962 /* Continue the loop after where the conditional
2963 branch used to jump, since the only branch insn
2964 in the block (if it still remains) is an inter-loop
2965 branch and hence needs no processing. */
2971 /* This loop will be continued with NEXT_INSN (insn). */
2973 }
2974 }
2975 }
2976 }
2977 }
2979 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2980 loops it is contained in, mark the target loop invalid.
2982 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2984 static void
2986 rtx x;
2988 {
2994 {
3006 /* There could be a label reference in here. */
3018 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3030 /* Link together all labels that branch outside the loop. This
3031 is used by final_[bg]iv_value and the loop unrolling code. Also
3032 mark this LABEL_REF so we know that this branch should predict
3033 false. */
3035 /* A check to make sure the label is not in an inner nested loop,
3036 since this does not count as a loop exit. */
3038 {
3043 }
3044 else
3048 {
3057 }
3059 /* If this is inside a loop, but not in the current loop or one enclosed
3060 by it, it invalidates at least one loop. */
3065 /* We must invalidate every nested loop containing the target of this
3066 label, except those that also contain the jump insn. */
3069 {
3070 /* Stop when we reach a loop that also contains the jump insn. */
3075 /* If we get here, we know we need to invalidate a loop. */
3082 }
3086 /* If this is not setting pc, ignore. */
3108 /* Strictly speaking this is not a jump into the loop, only a possible
3109 jump out of the loop. However, we have no way to link the destination
3110 of this jump onto the list of exit labels. To be safe we mark this
3111 loop and any containing loops as invalid. */
3113 {
3115 {
3121 }
3122 }
3124 }
3125 }
3126 \f
3127 /* Return nonzero if there is a label in the range from
3128 insn INSN to and including the insn whose luid is END
3129 INSN must have an assigned luid (i.e., it must not have
3130 been previously created by loop.c). */
3132 static int
3134 rtx insn;
3136 {
3138 {
3142 }
3145 }
3147 /* Record that a memory reference X is being set. */
3149 static void
3151 rtx x;
3152 rtx y ATTRIBUTE_UNUSED;
3154 {
3160 /* Count number of memory writes.
3161 This affects heuristics in strength_reduce. */
3164 /* BLKmode MEM means all memory is clobbered. */
3166 {
3169 else
3173 }
3177 }
3179 /* X is a value modified by an INSN that references a biv inside a loop
3180 exit test (ie, X is somehow related to the value of the biv). If X
3181 is a pseudo that is used more than once, then the biv is (effectively)
3182 used more than once. DATA is a pointer to a loop_regs structure. */
3184 static void
3186 rtx x;
3187 rtx y ATTRIBUTE_UNUSED;
3189 {
3204 /* If we do not have usage information, or if we know the register
3205 is used more than once, note that fact for check_dbra_loop. */
3210 }
3211 \f
3212 /* Return nonzero if the rtx X is invariant over the current loop.
3214 The value is 2 if we refer to something only conditionally invariant.
3216 A memory ref is invariant if it is not volatile and does not conflict
3217 with anything stored in `loop_info->store_mems'. */
3219 int
3222 rtx x;
3223 {
3230 rtx mem_list_entry;
3236 {
3244 /* A LABEL_REF is normally invariant, however, if we are unrolling
3245 loops, and this label is inside the loop, then it isn't invariant.
3246 This is because each unrolled copy of the loop body will have
3247 a copy of this label. If this was invariant, then an insn loading
3248 the address of this label into a register might get moved outside
3249 the loop, and then each loop body would end up using the same label.
3251 We don't know the loop bounds here though, so just fail for all
3252 labels. */
3255 else
3264 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3265 since the reg might be set by initialization within the loop. */
3282 /* Volatile memory references must be rejected. Do this before
3283 checking for read-only items, so that volatile read-only items
3284 will be rejected also. */
3288 /* See if there is any dependence between a store and this load. */
3291 {
3297 }
3299 /* It's not invalidated by a store in memory
3300 but we must still verify the address is invariant. */
3304 /* Don't mess with insns declared volatile. */
3311 }
3315 {
3317 {
3323 }
3325 {
3328 {
3334 }
3336 }
3337 }
3340 }
3341 \f
3342 /* Return nonzero if all the insns in the loop that set REG
3343 are INSN and the immediately following insns,
3344 and if each of those insns sets REG in an invariant way
3345 (not counting uses of REG in them).
3347 The value is 2 if some of these insns are only conditionally invariant.
3349 We assume that INSN itself is the first set of REG
3350 and that its source is invariant. */
3352 static int
3357 {
3361 rtx temp;
3362 /* Number of sets we have to insist on finding after INSN. */
3368 /* If N_SETS hit the limit, we can't rely on its value. */
3375 {
3377 rtx set;
3382 /* If library call, skip to end of it. */
3391 {
3396 {
3397 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3398 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3399 notes are OK. */
3405 }
3406 }
3408 count--;
3410 {
3413 }
3414 }
3417 /* If loop_invariant_p ever returned 2, we return 2. */
3419 }
3421 #if 0
3422 /* I don't think this condition is sufficient to allow INSN
3423 to be moved, so we no longer test it. */
3425 /* Return 1 if all insns in the basic block of INSN and following INSN
3426 that set REG are invariant according to TABLE. */
3428 static int
3432 {
3437 {
3446 {
3449 }
3450 }
3451 }
3453 \f
3454 /* Look at all uses (not sets) of registers in X. For each, if it is
3455 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3456 a different insn, set USAGE[REGNO] to const0_rtx. */
3458 static void
3461 rtx insn;
3462 rtx x;
3463 {
3475 {
3476 /* Don't count SET_DEST if it is a REG; otherwise count things
3477 in SET_DEST because if a register is partially modified, it won't
3478 show up as a potential movable so we don't care how USAGE is set
3479 for it. */
3483 }
3484 else
3486 {
3492 }
3493 }
3494 \f
3495 /* Count and record any set in X which is contained in INSN. Update
3496 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3497 in X. */
3499 static void
3504 {
3506 /* Don't move a reg that has an explicit clobber.
3507 It's not worth the pain to try to do it correctly. */
3511 {
3519 {
3523 {
3524 /* If this is the first setting of this reg
3525 in current basic block, and it was set before,
3526 it must be set in two basic blocks, so it cannot
3527 be moved out of the loop. */
3531 /* If this is not first setting in current basic block,
3532 see if reg was used in between previous one and this.
3533 If so, neither one can be moved. */
3540 }
3541 }
3542 }
3543 }
3544 \f
3545 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3546 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3547 contained in insn INSN is used by any insn that precedes INSN in
3548 cyclic order starting from the loop entry point.
3550 We don't want to use INSN_LUID here because if we restrict INSN to those
3551 that have a valid INSN_LUID, it means we cannot move an invariant out
3552 from an inner loop past two loops. */
3554 static int
3558 {
3560 rtx p;
3562 /* Scan forward checking for register usage. If we hit INSN, we
3563 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3565 {
3571 }
3574 }
3575 \f
3577 /* Information we collect about arrays that we might want to prefetch. */
3578 struct prefetch_info
3579 {
3583 index. */
3584 HOST_WIDE_INT index;
3586 iteration. */
3588 prefetch area in one iteration. */
3590 This is set only for loops with known
3591 iteration counts and is 0xffffffff
3592 otherwise. */
3596 };
3598 /* Data used by check_store function. */
3599 struct check_store_data
3600 {
3601 rtx mem_address;
3603 };
3609 /* Set mem_write when mem_address is found. Used as callback to
3610 note_stores. */
3611 static void
3615 {
3620 }
3621 \f
3622 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3623 important to get some addresses combined. Later more sophisticated
3624 transformations can be added when necesary.
3626 ??? Same trick with swapping operand is done at several other places.
3627 It can be nice to develop some common way to handle this. */
3629 static int
3632 {
3646 {
3651 }
3652 /* Compare the elements. If any pair of corresponding elements fails to
3653 match, return 0 for the whole thing. */
3657 {
3659 {
3671 /* Two vectors must have the same length. */
3675 /* And the corresponding elements must match. */
3693 /* These are just backpointers, so they don't matter. */
3699 /* It is believed that rtx's at this level will never
3700 contain anything but integers and other rtx's,
3701 except for within LABEL_REFs and SYMBOL_REFs. */
3704 }
3705 }
3707 }
3708 \f
3709 /* Remove constant addition value from the expression X (when present)
3710 and return it. */
3712 static HOST_WIDE_INT
3715 {
3719 /* Avoid clobbering a shared CONST expression. */
3721 {
3725 {
3728 }
3730 }
3733 {
3736 }
3738 /* For plus expression recurse on ourself. */
3740 {
3744 /* In case our parameter was constant, remove extra zero from the
3745 expression. */
3750 }
3753 }
3755 /* Attempt to identify accesses to arrays that are most likely to cause cache
3756 misses, and emit prefetch instructions a few prefetch blocks forward.
3758 To detect the arrays we use the GIV information that was collected by the
3759 strength reduction pass.
3761 The prefetch instructions are generated after the GIV information is done
3762 and before the strength reduction process. The new GIVs are injected into
3763 the strength reduction tables, so the prefetch addresses are optimized as
3764 well.
3766 GIVs are split into base address, stride, and constant addition values.
3767 GIVs with the same address, stride and close addition values are combined
3768 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3769 for write instructions can be used for the block we write to, on machines
3770 that support write prefetches.
3772 Several heuristics are used to determine when to prefetch. They are
3773 controlled by defined symbols that can be overridden for each target. */
3775 static void
3778 {
3794 /* Consider only loops w/o calls. When a call is done, the loop is probably
3795 slow enough to read the memory. */
3797 {
3802 }
3804 /* Don't prefetch in loops known to have few iterations. */
3808 {
3813 }
3815 /* Search all induction variables and pick those interesting for the prefetch
3816 machinery. */
3818 {
3824 /* Expect all BIVs to be executed in each iteration. This makes our
3825 analysis more conservative. */
3827 {
3828 /* Discard non-constant additions that we can't handle well yet, and
3829 BIVs that are executed multiple times; such BIVs ought to be
3830 handled in the nested loop. We accept not_every_iteration BIVs,
3831 since these only result in larger strides and make our
3832 heuristics more conservative. */
3834 {
3836 {
3842 }
3844 }
3847 {
3849 {
3855 }
3857 }
3861 }
3867 {
3868 rtx address;
3869 rtx temp;
3878 /* See whether an induction variable is interesting to us and if
3879 not, report the reason. */
3883 /* We are interested only in constant stride memory references
3884 in order to be able to compute density easily. */
3888 else
3889 {
3892 {
3895 }
3897 /* On some targets, reversed order prefetches are not
3898 worthwhile. */
3902 /* Prefetch of accesses with an extreme stride might not be
3903 worthwhile, either. */
3908 /* Ignore GIVs with varying add values; we can't predict the
3909 value for the next iteration. */
3913 /* Ignore GIVs in the nested loops; they ought to have been
3914 handled already. */
3917 }
3920 {
3926 }
3928 /* Determine the pointer to the basic array we are examining. It is
3929 the sum of the BIV's initial value and the GIV's add_val. */
3939 /* When the GIV is not always executed, we might be better off by
3940 not dirtying the cache pages. */
3943 else
3944 {
3949 }
3951 /* Attempt to find another prefetch to the same array and see if we
3952 can merge this one. */
3956 {
3957 /* In case both access same array (same location
3958 just with small difference in constant indexes), merge
3959 the prefetches. Just do the later and the earlier will
3960 get prefetched from previous iteration.
3961 The artificial threshold should not be too small,
3962 but also not bigger than small portion of memory usually
3963 traversed by single loop. */
3966 {
3975 }
3979 {
3984 }
3985 }
3987 /* Merging failed. */
3989 {
3997 num_prefetches++;
3999 {
4004 }
4005 }
4006 }
4007 }
4010 {
4013 /* Attempt to calculate the total number of bytes fetched by all
4014 iterations of the loop. Avoid overflow. */
4019 else
4024 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4029 {
4034 }
4035 else
4036 {
4042 }
4043 else
4046 /* Find how many prefetch instructions we'll use within the loop. */
4048 {
4054 }
4055 }
4057 /* Determine how many iterations ahead to prefetch within the loop, based
4058 on how many prefetches we currently expect to do within the loop. */
4060 {
4062 {
4068 }
4069 }
4070 /* We'll also use AHEAD to determine how many prefetch instructions to
4071 emit before a loop, so don't leave it zero. */
4076 {
4077 /* Update if we've decided not to prefetch anything within the loop. */
4081 /* Find how many prefetch instructions we'll use before the loop. */
4083 {
4091 }
4094 {
4116 }
4117 }
4120 {
4121 /* Record that this loop uses prefetch instructions. */
4125 {
4130 }
4131 }
4134 {
4138 {
4140 rtx insn;
4144 rtx seq;
4146 /* We can save some effort by offsetting the address on
4147 architectures with offsettable memory references. */
4150 else
4151 {
4157 }
4160 /* Make sure the address operand is valid for prefetch. */
4170 /* Check all insns emitted and record the new GIV
4171 information. */
4174 {
4179 }
4180 }
4183 {
4184 /* Emit insns before the loop to fetch the first cache lines or,
4185 if we're not prefetching within the loop, everything we expect
4186 to need. */
4188 {
4196 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4197 non-constant INIT_VAL to have the same mode as REG, which
4198 in this case we know to be Pmode. */
4206 loop_start);
4207 }
4208 }
4209 }
4212 }
4213 \f
4214 /* A "basic induction variable" or biv is a pseudo reg that is set
4215 (within this loop) only by incrementing or decrementing it. */
4216 /* A "general induction variable" or giv is a pseudo reg whose
4217 value is a linear function of a biv. */
4219 /* Bivs are recognized by `basic_induction_var';
4220 Givs by `general_induction_var'. */
4222 /* Communication with routines called via `note_stores'. */
4226 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4230 /* ??? Unfinished optimizations, and possible future optimizations,
4231 for the strength reduction code. */
4233 /* ??? The interaction of biv elimination, and recognition of 'constant'
4234 bivs, may cause problems. */
4236 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4237 performance problems.
4239 Perhaps don't eliminate things that can be combined with an addressing
4240 mode. Find all givs that have the same biv, mult_val, and add_val;
4241 then for each giv, check to see if its only use dies in a following
4242 memory address. If so, generate a new memory address and check to see
4243 if it is valid. If it is valid, then store the modified memory address,
4244 otherwise, mark the giv as not done so that it will get its own iv. */
4246 /* ??? Could try to optimize branches when it is known that a biv is always
4247 positive. */
4249 /* ??? When replace a biv in a compare insn, we should replace with closest
4250 giv so that an optimized branch can still be recognized by the combiner,
4251 e.g. the VAX acb insn. */
4253 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4254 was rerun in loop_optimize whenever a register was added or moved.
4255 Also, some of the optimizations could be a little less conservative. */
4256 \f
4257 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4258 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4259 callback.
4261 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4262 least once for every loop iteration except for the last one.
4264 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4265 loop iteration.
4266 */
4267 void
4270 loop_insn_callback fncall;
4271 {
4276 rtx p;
4278 /* If loop_scan_start points to the loop exit test, we have to be wary of
4279 subversive use of gotos inside expression statements. */
4283 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4287 {
4290 /* Past CODE_LABEL, we get to insns that may be executed multiple
4291 times. The only way we can be sure that they can't is if every
4292 jump insn between here and the end of the loop either
4293 returns, exits the loop, is a jump to a location that is still
4294 behind the label, or is a jump to the loop start. */
4297 {
4303 {
4308 {
4311 else
4315 }
4323 {
4326 }
4327 }
4328 }
4330 /* Past a jump, we get to insns for which we can't count
4331 on whether they will be executed during each iteration. */
4332 /* This code appears twice in strength_reduce. There is also similar
4333 code in scan_loop. */
4335 /* If we enter the loop in the middle, and scan around to the
4336 beginning, don't set not_every_iteration for that.
4337 This can be any kind of jump, since we want to know if insns
4338 will be executed if the loop is executed. */
4343 {
4346 /* If this is a jump outside the loop, then it also doesn't
4347 matter. Check to see if the target of this branch is on the
4348 loop->exits_labels list. */
4356 }
4359 {
4360 /* At the virtual top of a converted loop, insns are again known to
4361 be executed each iteration: logically, the loop begins here
4362 even though the exit code has been duplicated.
4364 Insns are also again known to be executed each iteration at
4365 the LOOP_CONT note. */
4371 loop_depth++;
4373 loop_depth--;
4374 }
4376 /* Note if we pass a loop latch. If we do, then we can not clear
4377 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4378 a loop since a jump before the last CODE_LABEL may have started
4379 a new loop iteration.
4381 Note that LOOP_TOP is only set for rotated loops and we need
4382 this check for all loops, so compare against the CODE_LABEL
4383 which immediately follows LOOP_START. */
4388 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4389 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4390 or not an insn is known to be executed each iteration of the
4391 loop, whether or not any iterations are known to occur.
4393 Therefore, if we have just passed a label and have no more labels
4394 between here and the test insn of the loop, and we have not passed
4395 a jump to the top of the loop, then we know these insns will be
4396 executed each iteration. */
4399 && !past_loop_latch
4404 }
4405 }
4406 \f
4407 static void
4410 {
4413 /* Temporary list pointers for traversing ivs->list. */
4420 /* Scan ivs->list to remove all regs that proved not to be bivs.
4421 Make a sanity check against regs->n_times_set. */
4423 {
4425 /* Above happens if register modified by subreg, etc. */
4426 /* Make sure it is not recognized as a basic induction var: */
4428 /* If never incremented, it is invariant that we decided not to
4429 move. So leave it alone. */
4431 {
4442 }
4443 else
4444 {
4449 }
4450 }
4451 }
4454 /* Determine how BIVS are initialized by looking through pre-header
4455 extended basic block. */
4456 static void
4459 {
4461 /* Temporary list pointers for traversing ivs->list. */
4464 rtx p;
4466 /* Find initial value for each biv by searching backwards from loop_start,
4467 halting at first label. Also record any test condition. */
4471 {
4472 rtx test;
4482 /* Record any test of a biv that branches around the loop if no store
4483 between it and the start of loop. We only care about tests with
4484 constants and registers and only certain of those. */
4494 {
4495 /* If an NE test, we have an initial value! */
4497 {
4501 }
4502 else
4504 }
4505 }
4506 }
4509 /* Look at the each biv and see if we can say anything better about its
4510 initial value from any initializing insns set up above. (This is done
4511 in two passes to avoid missing SETs in a PARALLEL.) */
4512 static void
4515 {
4517 /* Temporary list pointers for traversing ivs->list. */
4522 {
4523 rtx src;
4524 rtx note;
4529 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4530 is a constant, use the value of that. */
4536 else
4549 {
4553 {
4556 }
4557 }
4558 /* If we can't make it a giv,
4559 let biv keep initial value of "itself". */
4562 }
4563 }
4566 /* Search the loop for general induction variables. */
4568 static void
4571 {
4573 }
4576 /* For each giv for which we still don't know whether or not it is
4577 replaceable, check to see if it is replaceable because its final value
4578 can be calculated. */
4580 static void
4583 {
4588 {
4594 }
4595 }
4598 /* Return nonzero if it is possible to eliminate the biv BL provided
4599 all givs are reduced. This is possible if either the reg is not
4600 used outside the loop, or we can compute what its final value will
4601 be. */
4603 static int
4609 {
4610 /* For architectures with a decrement_and_branch_until_zero insn,
4611 don't do this if we put a REG_NONNEG note on the endtest for this
4612 biv. */
4614 #ifdef HAVE_decrement_and_branch_until_zero
4616 {
4621 }
4622 #endif
4624 /* Check that biv is used outside loop or if it has a final value.
4625 Compare against bl->init_insn rather than loop->start. We aren't
4626 concerned with any uses of the biv between init_insn and
4627 loop->start since these won't be affected by the value of the biv
4628 elsewhere in the function, so long as init_insn doesn't use the
4629 biv itself. */
4640 {
4648 }
4650 }
4653 /* Reduce each giv of BL that we have decided to reduce. */
4655 static void
4659 {
4663 {
4666 {
4669 /* If the code for derived givs immediately below has already
4670 allocated a new_reg, we must keep it. */
4674 #ifdef AUTO_INC_DEC
4675 /* If the target has auto-increment addressing modes, and
4676 this is an address giv, then try to put the increment
4677 immediately after its use, so that flow can create an
4678 auto-increment addressing mode. */
4681 /* We don't handle reversed biv's because bl->biv->insn
4682 does not have a valid INSN_LUID. */
4686 {
4687 /* If other giv's have been combined with this one, then
4688 this will work only if all uses of the other giv's occur
4689 before this giv's insn. This is difficult to check.
4691 We simplify this by looking for the common case where
4692 there is one DEST_REG giv, and this giv's insn is the
4693 last use of the dest_reg of that DEST_REG giv. If the
4694 increment occurs after the address giv, then we can
4695 perform the optimization. (Otherwise, the increment
4696 would have to go before other_giv, and we would not be
4697 able to combine it with the address giv to get an
4698 auto-inc address.) */
4700 {
4705 {
4708 else
4710 }
4717 }
4718 /* Check for case where increment is before the address
4719 giv. Do this test in "loop order". */
4728 else
4731 #ifdef HAVE_cc0
4732 {
4733 rtx prev;
4735 /* We can't put an insn immediately after one setting
4736 cc0, or immediately before one using cc0. */
4743 }
4744 #endif
4748 }
4749 #endif
4751 /* For each place where the biv is incremented, add an insn
4752 to increment the new, reduced reg for the giv. */
4754 {
4755 rtx insert_before;
4761 else
4769 /* A multiply is acceptable here
4770 since this is presumed to be seldom executed. */
4774 }
4776 /* Add code at loop start to initialize giv's reduced reg. */
4781 }
4782 }
4783 }
4786 /* Check for givs whose first use is their definition and whose
4787 last use is the definition of another giv. If so, it is likely
4788 dead and should not be used to derive another giv nor to
4789 eliminate a biv. */
4791 static void
4795 {
4799 {
4806 {
4812 }
4813 }
4814 }
4817 static void
4822 {
4826 {
4833 /* Update expression if this was combined, in case other giv was
4834 replaced. */
4839 /* See if this register is known to be a pointer to something. If
4840 so, see if we can find the alignment. First see if there is a
4841 destination register that is a pointer. If so, this shares the
4842 alignment too. Next see if we can deduce anything from the
4843 computational information. If not, and this is a DEST_ADDR
4844 giv, at least we know that it's a pointer, though we don't know
4845 the alignment. */
4853 {
4862 }
4866 {
4874 }
4879 /* Store reduced reg as the address in the memref where we found
4880 this giv. */
4883 {
4885 }
4886 else
4887 {
4889 rtx note;
4891 /* Not replaceable; emit an insn to set the original giv reg from
4892 the reduced giv, same as above. */
4897 /* The original insn may have a REG_EQUAL note. This note is
4898 now incorrect and may result in invalid substitutions later.
4899 The original insn is dead, but may be part of a libcall
4900 sequence, which doesn't seem worth the bother of handling. */
4904 }
4906 /* When a loop is reversed, givs which depend on the reversed
4907 biv, and which are live outside the loop, must be set to their
4908 correct final value. This insn is only needed if the giv is
4909 not replaceable. The correct final value is the same as the
4910 value that the giv starts the reversed loop with. */
4921 {
4926 }
4927 }
4928 }
4931 static int
4936 rtx test_reg;
4937 {
4946 /* Reduce benefit if not replaceable, since we will insert a
4947 move-insn to replace the insn that calculates this giv. Don't do
4948 this unless the giv is a user variable, since it will often be
4949 marked non-replaceable because of the duplication of the exit
4950 code outside the loop. In such a case, the copies we insert are
4951 dead and will be deleted. So they don't have a cost. Similar
4952 situations exist. */
4953 /* ??? The new final_[bg]iv_value code does a much better job of
4954 finding replaceable giv's, and hence this code may no longer be
4955 necessary. */
4960 /* Decrease the benefit to count the add-insns that we will insert
4961 to increment the reduced reg for the giv. ??? This can
4962 overestimate the run-time cost of the additional insns, e.g. if
4963 there are multiple basic blocks that increment the biv, but only
4964 one of these blocks is executed during each iteration. There is
4965 no good way to detect cases like this with the current structure
4966 of the loop optimizer. This code is more accurate for
4967 determining code size than run-time benefits. */
4970 /* Decide whether to strength-reduce this giv or to leave the code
4971 unchanged (recompute it from the biv each time it is used). This
4972 decision can be made independently for each giv. */
4974 #ifdef AUTO_INC_DEC
4975 /* Attempt to guess whether autoincrement will handle some of the
4976 new add insns; if so, increase BENEFIT (undo the subtraction of
4977 add_cost that was done above). */
4979 /* Increasing the benefit is risky, since this is only a guess.
4980 Avoid increasing register pressure in cases where there would
4981 be no other benefit from reducing this giv. */
4984 {
4999 }
5000 #endif
5003 }
5006 /* Free IV structures for LOOP. */
5008 static void
5011 {
5018 {
5024 {
5027 }
5029 {
5032 }
5036 }
5037 }
5040 /* Perform strength reduction and induction variable elimination.
5042 Pseudo registers created during this function will be beyond the
5043 last valid index in several tables including
5044 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5045 problem here, because the added registers cannot be givs outside of
5046 their loop, and hence will never be reconsidered. But scan_loop
5047 must check regnos to make sure they are in bounds. */
5049 static void
5053 {
5057 rtx p;
5058 /* Temporary list pointer for traversing ivs->list. */
5060 /* Ratio of extra register life span we can justify
5061 for saving an instruction. More if loop doesn't call subroutines
5062 since in that case saving an insn makes more difference
5063 and more registers are available. */
5064 /* ??? could set this to last value of threshold in move_movables */
5066 /* Map of pseudo-register replacements. */
5078 /* Find all BIVs in loop. */
5081 /* Exit if there are no bivs. */
5083 {
5084 /* Can still unroll the loop anyways, but indicate that there is no
5085 strength reduction info available. */
5091 }
5093 /* Determine how BIVS are initialized by looking through pre-header
5094 extended basic block. */
5097 /* Look at the each biv and see if we can say anything better about its
5098 initial value from any initializing insns set up above. */
5101 /* Search the loop for general induction variables. */
5104 /* Try to calculate and save the number of loop iterations. This is
5105 set to zero if the actual number can not be calculated. This must
5106 be called after all giv's have been identified, since otherwise it may
5107 fail if the iteration variable is a giv. */
5110 #ifdef HAVE_prefetch
5113 #endif
5115 /* Now for each giv for which we still don't know whether or not it is
5116 replaceable, check to see if it is replaceable because its final value
5117 can be calculated. This must be done after loop_iterations is called,
5118 so that final_giv_value will work correctly. */
5121 /* Try to prove that the loop counter variable (if any) is always
5122 nonnegative; if so, record that fact with a REG_NONNEG note
5123 so that "decrement and branch until zero" insn can be used. */
5126 /* Create reg_map to hold substitutions for replaceable giv regs.
5127 Some givs might have been made from biv increments, so look at
5128 ivs->reg_iv_type for a suitable size. */
5132 /* Examine each iv class for feasibility of strength reduction/induction
5133 variable elimination. */
5136 {
5140 /* Test whether it will be possible to eliminate this biv
5141 provided all givs are reduced. */
5144 /* This will be true at the end, if all givs which depend on this
5145 biv have been strength reduced.
5146 We can't (currently) eliminate the biv unless this is so. */
5149 /* Check each extension dependent giv in this class to see if its
5150 root biv is safe from wrapping in the interior mode. */
5153 /* Combine all giv's for this iv_class. */
5157 {
5165 /* If an insn is not to be strength reduced, then set its ignore
5166 flag, and clear bl->all_reduced. */
5168 /* A giv that depends on a reversed biv must be reduced if it is
5169 used after the loop exit, otherwise, it would have the wrong
5170 value after the loop exit. To make it simple, just reduce all
5171 of such giv's whether or not we know they are used after the loop
5172 exit. */
5177 {
5185 }
5186 else
5187 {
5188 /* Check that we can increment the reduced giv without a
5189 multiply insn. If not, reject it. */
5194 {
5202 }
5203 }
5204 }
5206 /* Check for givs whose first use is their definition and whose
5207 last use is the definition of another giv. If so, it is likely
5208 dead and should not be used to derive another giv nor to
5209 eliminate a biv. */
5212 /* Reduce each giv that we decided to reduce. */
5215 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5216 as not reduced.
5218 For each giv register that can be reduced now: if replaceable,
5219 substitute reduced reg wherever the old giv occurs;
5220 else add new move insn "giv_reg = reduced_reg". */
5223 /* All the givs based on the biv bl have been reduced if they
5224 merit it. */
5226 /* For each giv not marked as maybe dead that has been combined with a
5227 second giv, clear any "maybe dead" mark on that second giv.
5228 v->new_reg will either be or refer to the register of the giv it
5229 combined with.
5231 Doing this clearing avoids problems in biv elimination where
5232 a giv's new_reg is a complex value that can't be put in the
5233 insn but the giv combined with (with a reg as new_reg) is
5234 marked maybe_dead. Since the register will be used in either
5235 case, we'd prefer it be used from the simpler giv. */
5241 /* Try to eliminate the biv, if it is a candidate.
5242 This won't work if ! bl->all_reduced,
5243 since the givs we planned to use might not have been reduced.
5245 We have to be careful that we didn't initially think we could
5246 eliminate this biv because of a giv that we now think may be
5247 dead and shouldn't be used as a biv replacement.
5249 Also, there is the possibility that we may have a giv that looks
5250 like it can be used to eliminate a biv, but the resulting insn
5251 isn't valid. This can happen, for example, on the 88k, where a
5252 JUMP_INSN can compare a register only with zero. Attempts to
5253 replace it with a compare with a constant will fail.
5255 Note that in cases where this call fails, we may have replaced some
5256 of the occurrences of the biv with a giv, but no harm was done in
5257 doing so in the rare cases where it can occur. */
5261 {
5262 /* ?? If we created a new test to bypass the loop entirely,
5263 or otherwise drop straight in, based on this test, then
5264 we might want to rewrite it also. This way some later
5265 pass has more hope of removing the initialization of this
5266 biv entirely. */
5268 /* If final_value != 0, then the biv may be used after loop end
5269 and we must emit an insn to set it just in case.
5271 Reversed bivs already have an insn after the loop setting their
5272 value, so we don't need another one. We can't calculate the
5273 proper final value for such a biv here anyways. */
5282 }
5283 /* See above note wrt final_value. But since we couldn't eliminate
5284 the biv, we must set the value after the loop instead of before. */
5288 }
5290 /* Go through all the instructions in the loop, making all the
5291 register substitutions scheduled in REG_MAP. */
5296 {
5300 }
5303 {
5304 /* When we completely unroll a loop we will likely not need the increment
5305 of the loop BIV and we will not need the conditional branch at the
5306 end of the loop. */
5309 #ifdef HAVE_cc0
5310 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5311 need the comparison before the conditional branch at the end of the
5312 loop. */
5314 #endif
5316 /* We'll need one copy for each loop iteration. */
5319 /* A little slop to account for the ability to remove initialization
5320 code, better CSE, and other secondary benefits of completely
5321 unrolling some loops. */
5324 /* Clamp the value. */
5327 }
5329 /* Unroll loops from within strength reduction so that we can use the
5330 induction variable information that strength_reduce has already
5331 collected. Always unroll loops that would be as small or smaller
5332 unrolled than when rolled. */
5339 #ifdef HAVE_doloop_end
5344 /* In case number of iterations is known, drop branch prediction note
5345 in the branch. Do that only in second loop pass, as loop unrolling
5346 may change the number of iterations performed. */
5348 {
5349 unsigned HOST_WIDE_INT n
5354 }
5362 }
5363 \f
5364 /*Record all basic induction variables calculated in the insn. */
5365 static rtx
5368 rtx p;
5371 {
5373 rtx set;
5374 rtx dest_reg;
5375 rtx inc_val;
5376 rtx mult_val;
5382 {
5387 {
5392 {
5393 /* It is a possible basic induction variable.
5394 Create and initialize an induction structure for it. */
5402 }
5405 }
5406 }
5408 }
5409 \f
5410 /* Record all givs calculated in the insn.
5411 A register is a giv if: it is only set once, it is a function of a
5412 biv and a constant (or invariant), and it is not a biv. */
5413 static rtx
5416 rtx p;
5419 {
5422 rtx set;
5423 /* Look for a general induction variable in a register. */
5428 {
5429 rtx src_reg;
5430 rtx dest_reg;
5431 rtx add_val;
5432 rtx mult_val;
5433 rtx ext_val;
5436 rtx last_consec_insn;
5445 /* Equivalent expression is a giv. */
5450 /* Don't try to handle any regs made by loop optimization.
5451 We have nothing on them in regno_first_uid, etc. */
5453 /* Don't recognize a BASIC_INDUCT_VAR here. */
5455 /* This must be the only place where the register is set. */
5457 /* or all sets must be consecutive and make a giv. */
5462 {
5466 /* If this is a library call, increase benefit. */
5470 /* Skip the consecutive insns, if there are any. */
5478 }
5479 }
5481 #ifndef DONT_REDUCE_ADDR
5482 /* Look for givs which are memory addresses. */
5483 /* This resulted in worse code on a VAX 8600. I wonder if it
5484 still does. */
5487 maybe_multiple);
5488 #endif
5490 /* Update the status of whether giv can derive other givs. This can
5491 change when we pass a label or an insn that updates a biv. */
5496 }
5497 \f
5498 /* Return 1 if X is a valid source for an initial value (or as value being
5499 compared against in an initial test).
5501 X must be either a register or constant and must not be clobbered between
5502 the current insn and the start of the loop.
5504 INSN is the insn containing X. */
5506 static int
5508 rtx x;
5509 rtx insn;
5511 rtx loop_start;
5512 {
5516 /* Only consider pseudos we know about initialized in insns whose luids
5517 we know. */
5522 /* Don't use call-clobbered registers across a call which clobbers it. On
5523 some machines, don't use any hard registers at all. */
5525 && (SMALL_REGISTER_CLASSES
5529 /* Don't use registers that have been clobbered before the start of the
5530 loop. */
5535 }
5536 \f
5537 /* Scan X for memory refs and check each memory address
5538 as a possible giv. INSN is the insn whose pattern X comes from.
5539 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5540 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5541 more thanonce in each loop iteration. */
5543 static void
5546 rtx x;
5547 rtx insn;
5549 {
5559 {
5575 {
5576 rtx src_reg;
5577 rtx add_val;
5578 rtx mult_val;
5579 rtx ext_val;
5582 /* This code used to disable creating GIVs with mult_val == 1 and
5583 add_val == 0. However, this leads to lost optimizations when
5584 it comes time to combine a set of related DEST_ADDR GIVs, since
5585 this one would not be seen. */
5590 {
5591 /* Found one; record it. */
5600 }
5601 }
5606 }
5608 /* Recursively scan the subexpressions for other mem refs. */
5614 maybe_multiple);
5618 maybe_multiple);
5619 }
5620 \f
5621 /* Fill in the data about one biv update.
5622 V is the `struct induction' in which we record the biv. (It is
5623 allocated by the caller, with alloca.)
5624 INSN is the insn that sets it.
5625 DEST_REG is the biv's reg.
5627 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5628 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5629 being set to INC_VAL.
5631 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5632 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5633 can be executed more than once per iteration. If MAYBE_MULTIPLE
5634 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5635 executed exactly once per iteration. */
5637 static void
5642 rtx insn;
5643 rtx dest_reg;
5644 rtx inc_val;
5645 rtx mult_val;
5649 {
5665 /* Add this to the reg's iv_class, creating a class
5666 if this is the first incrementation of the reg. */
5670 {
5671 /* Create and initialize new iv_class. */
5681 /* Set initial value to the reg itself. */
5684 /* We haven't seen the initializing insn yet */
5694 /* Add this class to ivs->list. */
5698 /* Put it in the array of biv register classes. */
5700 }
5702 /* Update IV_CLASS entry for this biv. */
5711 }
5712 \f
5713 /* Fill in the data about one giv.
5714 V is the `struct induction' in which we record the giv. (It is
5715 allocated by the caller, with alloca.)
5716 INSN is the insn that sets it.
5717 BENEFIT estimates the savings from deleting this insn.
5718 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5719 into a register or is used as a memory address.
5721 SRC_REG is the biv reg which the giv is computed from.
5722 DEST_REG is the giv's reg (if the giv is stored in a reg).
5723 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5724 LOCATION points to the place where this giv's value appears in INSN. */
5726 static void
5731 rtx insn;
5732 rtx src_reg;
5733 rtx dest_reg;
5739 {
5744 rtx temp;
5746 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5747 undo the MULT canonicalization that we performed earlier. */
5777 /* The v->always_computable field is used in update_giv_derive, to
5778 determine whether a giv can be used to derive another giv. For a
5779 DEST_REG giv, INSN computes a new value for the giv, so its value
5780 isn't computable if INSN insn't executed every iteration.
5781 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5782 it does not compute a new value. Hence the value is always computable
5783 regardless of whether INSN is executed each iteration. */
5787 else
5793 {
5796 }
5798 {
5803 /* If the lifetime is zero, it means that this register is
5804 really a dead store. So mark this as a giv that can be
5805 ignored. This will not prevent the biv from being eliminated. */
5811 }
5813 /* Add the giv to the class of givs computed from one biv. */
5817 {
5820 /* Don't count DEST_ADDR. This is supposed to count the number of
5821 insns that calculate givs. */
5825 }
5826 else
5827 /* Fatal error, biv missing for this giv? */
5832 else
5833 {
5834 /* The giv can be replaced outright by the reduced register only if all
5835 of the following conditions are true:
5836 - the insn that sets the giv is always executed on any iteration
5837 on which the giv is used at all
5838 (there are two ways to deduce this:
5839 either the insn is executed on every iteration,
5840 or all uses follow that insn in the same basic block),
5841 - the giv is not used outside the loop
5842 - no assignments to the biv occur during the giv's lifetime. */
5845 /* Previous line always fails if INSN was moved by loop opt. */
5848 && (! not_every_iteration
5850 {
5851 /* Now check that there are no assignments to the biv within the
5852 giv's lifetime. This requires two separate checks. */
5854 /* Check each biv update, and fail if any are between the first
5855 and last use of the giv.
5857 If this loop contains an inner loop that was unrolled, then
5858 the insn modifying the biv may have been emitted by the loop
5859 unrolling code, and hence does not have a valid luid. Just
5860 mark the biv as not replaceable in this case. It is not very
5861 useful as a biv, because it is used in two different loops.
5862 It is very unlikely that we would be able to optimize the giv
5863 using this biv anyways. */
5867 {
5873 {
5877 }
5878 }
5880 /* If there are any backwards branches that go from after the
5881 biv update to before it, then this giv is not replaceable. */
5885 {
5889 }
5890 }
5891 else
5892 {
5893 /* May still be replaceable, we don't have enough info here to
5894 decide. */
5897 }
5898 }
5900 /* Record whether the add_val contains a const_int, for later use by
5901 combine_givs. */
5902 {
5907 ;
5911 {
5913 {
5918 else
5920 }
5923 }
5924 }
5928 }
5930 /* All this does is determine whether a giv can be made replaceable because
5931 its final value can be calculated. This code can not be part of record_giv
5932 above, because final_giv_value requires that the number of loop iterations
5933 be known, and that can not be accurately calculated until after all givs
5934 have been identified. */
5936 static void
5940 {
5947 /* DEST_ADDR givs will never reach here, because they are always marked
5948 replaceable above in record_giv. */
5950 /* The giv can be replaced outright by the reduced register only if all
5951 of the following conditions are true:
5952 - the insn that sets the giv is always executed on any iteration
5953 on which the giv is used at all
5954 (there are two ways to deduce this:
5955 either the insn is executed on every iteration,
5956 or all uses follow that insn in the same basic block),
5957 - its final value can be calculated (this condition is different
5958 than the one above in record_giv)
5959 - it's not used before the it's set
5960 - no assignments to the biv occur during the giv's lifetime. */
5962 #if 0
5963 /* This is only called now when replaceable is known to be false. */
5964 /* Clear replaceable, so that it won't confuse final_giv_value. */
5966 #endif
5971 {
5974 rtx last_giv_use;
5978 /* When trying to determine whether or not a biv increment occurs
5979 during the lifetime of the giv, we can ignore uses of the variable
5980 outside the loop because final_value is true. Hence we can not
5981 use regno_last_uid and regno_first_uid as above in record_giv. */
5983 /* Search the loop to determine whether any assignments to the
5984 biv occur during the giv's lifetime. Start with the insn
5985 that sets the giv, and search around the loop until we come
5986 back to that insn again.
5988 Also fail if there is a jump within the giv's lifetime that jumps
5989 to somewhere outside the lifetime but still within the loop. This
5990 catches spaghetti code where the execution order is not linear, and
5991 hence the above test fails. Here we assume that the giv lifetime
5992 does not extend from one iteration of the loop to the next, so as
5993 to make the test easier. Since the lifetime isn't known yet,
5994 this requires two loops. See also record_giv above. */
5999 {
6002 {
6005 }
6011 {
6012 /* It is possible for the BIV increment to use the GIV if we
6013 have a cycle. Thus we must be sure to check each insn for
6014 both BIV and GIV uses, and we must check for BIV uses
6015 first. */
6022 {
6024 {
6028 }
6030 }
6031 }
6032 }
6034 /* Now that the lifetime of the giv is known, check for branches
6035 from within the lifetime to outside the lifetime if it is still
6036 replaceable. */
6039 {
6042 {
6055 {
6064 }
6065 }
6066 }
6068 /* If it is replaceable, then save the final value. */
6071 }
6076 }
6077 \f
6078 /* Update the status of whether a giv can derive other givs.
6080 We need to do something special if there is or may be an update to the biv
6081 between the time the giv is defined and the time it is used to derive
6082 another giv.
6084 In addition, a giv that is only conditionally set is not allowed to
6085 derive another giv once a label has been passed.
6087 The cases we look at are when a label or an update to a biv is passed. */
6089 static void
6092 rtx p;
6093 {
6097 rtx tem;
6100 /* Search all IV classes, then all bivs, and finally all givs.
6102 There are three cases we are concerned with. First we have the situation
6103 of a giv that is only updated conditionally. In that case, it may not
6104 derive any givs after a label is passed.
6106 The second case is when a biv update occurs, or may occur, after the
6107 definition of a giv. For certain biv updates (see below) that are
6108 known to occur between the giv definition and use, we can adjust the
6109 giv definition. For others, or when the biv update is conditional,
6110 we must prevent the giv from deriving any other givs. There are two
6111 sub-cases within this case.
6113 If this is a label, we are concerned with any biv update that is done
6114 conditionally, since it may be done after the giv is defined followed by
6115 a branch here (actually, we need to pass both a jump and a label, but
6116 this extra tracking doesn't seem worth it).
6118 If this is a jump, we are concerned about any biv update that may be
6119 executed multiple times. We are actually only concerned about
6120 backward jumps, but it is probably not worth performing the test
6121 on the jump again here.
6123 If this is a biv update, we must adjust the giv status to show that a
6124 subsequent biv update was performed. If this adjustment cannot be done,
6125 the giv cannot derive further givs. */
6131 {
6133 {
6134 /* If cant_derive is already true, there is no point in
6135 checking all of these conditions again. */
6139 /* If this giv is conditionally set and we have passed a label,
6140 it cannot derive anything. */
6144 /* Skip givs that have mult_val == 0, since
6145 they are really invariants. Also skip those that are
6146 replaceable, since we know their lifetime doesn't contain
6147 any biv update. */
6151 /* The only way we can allow this giv to derive another
6152 is if this is a biv increment and we can form the product
6153 of biv->add_val and giv->mult_val. In this case, we will
6154 be able to compute a compensation. */
6156 {
6157 rtx ext_val_dummy;
6168 tem = simplify_giv_expr
6175 else
6177 }
6181 }
6182 }
6183 }
6184 \f
6185 /* Check whether an insn is an increment legitimate for a basic induction var.
6186 X is the source of insn P, or a part of it.
6187 MODE is the mode in which X should be interpreted.
6189 DEST_REG is the putative biv, also the destination of the insn.
6190 We accept patterns of these forms:
6191 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6192 REG = INVARIANT + REG
6194 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6195 store the additive term into *INC_VAL, and store the place where
6196 we found the additive term into *LOCATION.
6198 If X is an assignment of an invariant into DEST_REG, we set
6199 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6201 We also want to detect a BIV when it corresponds to a variable
6202 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6203 of the variable may be a PLUS that adds a SUBREG of that variable to
6204 an invariant and then sign- or zero-extends the result of the PLUS
6205 into the variable.
6207 Most GIVs in such cases will be in the promoted mode, since that is the
6208 probably the natural computation mode (and almost certainly the mode
6209 used for addresses) on the machine. So we view the pseudo-reg containing
6210 the variable as the BIV, as if it were simply incremented.
6212 Note that treating the entire pseudo as a BIV will result in making
6213 simple increments to any GIVs based on it. However, if the variable
6214 overflows in its declared mode but not its promoted mode, the result will
6215 be incorrect. This is acceptable if the variable is signed, since
6216 overflows in such cases are undefined, but not if it is unsigned, since
6217 those overflows are defined. So we only check for SIGN_EXTEND and
6218 not ZERO_EXTEND.
6220 If we cannot find a biv, we return 0. */
6222 static int
6225 rtx x;
6227 rtx dest_reg;
6228 rtx p;
6232 {
6240 {
6246 {
6248 }
6253 {
6255 }
6256 else
6269 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6270 handle addition of promoted variables.
6271 ??? The comment at the start of this function is wrong: promoted
6272 variable increments don't look like it says they do. */
6278 /* If this register is assigned in a previous insn, look at its
6279 source, but don't go outside the loop or past a label. */
6281 /* If this sets a register to itself, we would repeat any previous
6282 biv increment if we applied this strategy blindly. */
6288 {
6289 rtx dest;
6290 do
6291 {
6293 }
6322 }
6323 /* Fall through. */
6325 /* Can accept constant setting of biv only when inside inner most loop.
6326 Otherwise, a biv of an inner loop may be incorrectly recognized
6327 as a biv of the outer loop,
6328 causing code to be moved INTO the inner loop. */
6335 /* convert_modes aborts if we try to convert to or from CCmode, so just
6336 exclude that case. It is very unlikely that a condition code value
6337 would be a useful iterator anyways. convert_modes aborts if we try to
6338 convert a float mode to non-float or vice versa too. */
6342 {
6343 /* Possible bug here? Perhaps we don't know the mode of X. */
6347 }
6348 else
6356 /* Similar, since this can be a sign extension. */
6361 ;
6375 location);
6380 }
6381 }
6382 \f
6383 /* A general induction variable (giv) is any quantity that is a linear
6384 function of a basic induction variable,
6385 i.e. giv = biv * mult_val + add_val.
6386 The coefficients can be any loop invariant quantity.
6387 A giv need not be computed directly from the biv;
6388 it can be computed by way of other givs. */
6390 /* Determine whether X computes a giv.
6391 If it does, return a nonzero value
6392 which is the benefit from eliminating the computation of X;
6393 set *SRC_REG to the register of the biv that it is computed from;
6394 set *ADD_VAL and *MULT_VAL to the coefficients,
6395 such that the value of X is biv * mult + add; */
6397 static int
6401 rtx x;
6409 {
6413 /* If this is an invariant, forget it, it isn't a giv. */
6424 {
6427 /* Since this is now an invariant and wasn't before, it must be a giv
6428 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6429 with. */
6436 /* This is equivalent to a BIV. */
6443 /* Either (plus (biv) (invar)) or
6444 (plus (mult (biv) (invar_1)) (invar_2)). */
6446 {
6449 }
6450 else
6451 {
6454 }
6459 /* ADD_VAL is zero. */
6467 }
6469 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6470 unless they are CONST_INT). */
6478 else
6481 /* Always return true if this is a giv so it will be detected as such,
6482 even if the benefit is zero or negative. This allows elimination
6483 of bivs that might otherwise not be eliminated. */
6485 }
6486 \f
6487 /* Given an expression, X, try to form it as a linear function of a biv.
6488 We will canonicalize it to be of the form
6489 (plus (mult (BIV) (invar_1))
6490 (invar_2))
6491 with possible degeneracies.
6493 The invariant expressions must each be of a form that can be used as a
6494 machine operand. We surround then with a USE rtx (a hack, but localized
6495 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6496 routine; it is the caller's responsibility to strip them.
6498 If no such canonicalization is possible (i.e., two biv's are used or an
6499 expression that is neither invariant nor a biv or giv), this routine
6500 returns 0.
6502 For a nonzero return, the result will have a code of CONST_INT, USE,
6503 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6505 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6510 static rtx
6513 rtx x;
6516 {
6521 rtx tem;
6523 /* If this is not an integer mode, or if we cannot do arithmetic in this
6524 mode, this can't be a giv. */
6531 {
6538 /* Put constant last, CONST_INT last if both constant. */
6546 /* Handle addition of zero, then addition of an invariant. */
6551 {
6554 /* Adding two invariants must result in an invariant, so enclose
6555 addition operation inside a USE and return it. */
6565 else
6574 /* biv + invar or mult + invar. Return sum. */
6578 /* (a + invar_1) + invar_2. Associate. */
6579 return
6585 arg1)),
6590 }
6592 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6593 MULT to reduce cases. */
6599 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6600 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6601 Recurse to associate the second PLUS. */
6606 return
6614 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6630 /* Handle "a - b" as "a + b * (-1)". */
6636 constm1_rtx)),
6645 /* Put constant last, CONST_INT last if both constant. */
6650 /* If second argument is not now constant, not giv. */
6654 /* Handle multiply by 0 or 1. */
6662 {
6664 /* biv * invar. Done. */
6668 /* Product of two constants. */
6672 /* invar * invar is a giv, but attempt to simplify it somehow. */
6678 {
6679 /* (invar_0 * invar_1) * invar_2. Associate. */
6686 arg1)),
6688 }
6689 /* Porpagate the MULT expressions to the intermost nodes. */
6691 {
6692 /* (invar_0 + invar_1) * invar_2. Distribute. */
6698 arg1),
6702 arg1)),
6704 }
6708 /* (a * invar_1) * invar_2. Associate. */
6714 arg1)),
6718 /* (a + invar_1) * invar_2. Distribute. */
6723 arg1),
6726 arg1)),
6731 }
6734 /* Shift by constant is multiply by power of two. */
6738 return
6747 /* "-a" is "a * (-1)" */
6753 /* "~a" is "-a - 1". Silly, but easy. */
6757 const1_rtx),
6761 /* Already in proper form for invariant. */
6767 /* Conditionally recognize extensions of simple IVs. After we've
6768 computed loop traversal counts and verified the range of the
6769 source IV, we'll reevaluate this as a GIV. */
6771 {
6774 {
6777 }
6778 }
6782 /* If this is a new register, we can't deal with it. */
6786 /* Check for biv or giv. */
6788 {
6792 {
6795 /* Form expression from giv and add benefit. Ensure this giv
6796 can derive another and subtract any needed adjustment if so. */
6798 /* Increasing the benefit here is risky. The only case in which it
6799 is arguably correct is if this is the only use of V. In other
6800 cases, this will artificially inflate the benefit of the current
6801 giv, and lead to suboptimal code. Thus, it is disabled, since
6802 potentially not reducing an only marginally beneficial giv is
6803 less harmful than reducing many givs that are not really
6804 beneficial. */
6805 {
6809 }
6822 {
6825 }
6826 else
6827 {
6830 }
6832 }
6835 do_default:
6836 /* If it isn't an induction variable, and it is invariant, we
6837 may be able to simplify things further by looking through
6838 the bits we just moved outside the loop. */
6840 {
6846 {
6847 /* Ok, we found a match. Substitute and simplify. */
6849 /* If we match another movable, we must use that, as
6850 this one is going away. */
6855 /* If consec is nonzero, this is a member of a group of
6856 instructions that were moved together. We handle this
6857 case only to the point of seeking to the last insn and
6858 looking for a REG_EQUAL. Fail if we don't find one. */
6860 {
6863 do
6864 {
6866 }
6872 }
6873 else
6874 {
6878 }
6881 {
6882 /* What we are most interested in is pointer
6883 arithmetic on invariants -- only take
6884 patterns we may be able to do something with. */
6890 {
6892 benefit);
6895 }
6900 {
6905 }
6906 }
6908 }
6909 }
6911 }
6913 /* Fall through to general case. */
6915 /* If invariant, return as USE (unless CONST_INT).
6916 Otherwise, not giv. */
6921 {
6930 }
6931 else
6933 }
6934 }
6936 /* This routine folds invariants such that there is only ever one
6937 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6939 static rtx
6942 {
6948 {
6951 }
6954 {
6957 }
6958 else
6959 {
6962 }
6963 }
6965 static rtx
6969 {
6971 {
6975 else
6978 }
6981 else
6984 }
6985 \f
6986 /* Help detect a giv that is calculated by several consecutive insns;
6987 for example,
6988 giv = biv * M
6989 giv = giv + A
6990 The caller has already identified the first insn P as having a giv as dest;
6991 we check that all other insns that set the same register follow
6992 immediately after P, that they alter nothing else,
6993 and that the result of the last is still a giv.
6995 The value is 0 if the reg set in P is not really a giv.
6996 Otherwise, the value is the amount gained by eliminating
6997 all the consecutive insns that compute the value.
6999 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7000 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7002 The coefficients of the ultimate giv value are stored in
7003 *MULT_VAL and *ADD_VAL. */
7005 static int
7010 rtx p;
7011 rtx src_reg;
7012 rtx dest_reg;
7017 {
7023 rtx temp;
7024 rtx set;
7026 /* Indicate that this is a giv so that we can update the value produced in
7027 each insn of the multi-insn sequence.
7029 This induction structure will be used only by the call to
7030 general_induction_var below, so we can allocate it on our stack.
7031 If this is a giv, our caller will replace the induct var entry with
7032 a new induction structure. */
7053 {
7057 /* If libcall, skip to end of call sequence. */
7068 /* Giv created by equivalent expression. */
7074 {
7078 count--;
7082 }
7084 {
7085 /* Allow insns that set something other than this giv to a
7086 constant. Such insns are needed on machines which cannot
7087 include long constants and should not disqualify a giv. */
7096 }
7097 }
7102 }
7103 \f
7104 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7105 represented by G1. If no such expression can be found, or it is clear that
7106 it cannot possibly be a valid address, 0 is returned.
7108 To perform the computation, we note that
7109 G1 = x * v + a and
7110 G2 = y * v + b
7111 where `v' is the biv.
7113 So G2 = (y/b) * G1 + (b - a*y/x).
7115 Note that MULT = y/x.
7117 Update: A and B are now allowed to be additive expressions such that
7118 B contains all variables in A. That is, computing B-A will not require
7119 subtracting variables. */
7121 static rtx
7124 {
7125 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7130 /* If MULT is not 1, we cannot handle A with non-constants, since we
7131 would then be required to subtract multiples of the registers in A.
7132 This is theoretically possible, and may even apply to some Fortran
7133 constructs, but it is a lot of work and we do not attempt it here. */
7138 /* In general these structures are sorted top to bottom (down the PLUS
7139 chain), but not left to right across the PLUS. If B is a higher
7140 order giv than A, we can strip one level and recurse. If A is higher
7141 order, we'll eventually bail out, but won't know that until the end.
7142 If they are the same, we'll strip one level around this loop. */
7145 {
7157 /* We matched: remove one reg completely. */
7160 /* An alternate match. */
7163 /* An alternate match. */
7165 else
7166 {
7167 /* Indicates an extra register in B. Strip one level from B and
7168 recurse, hoping B was the higher order expression. */
7173 }
7174 }
7176 /* Here we are at the last level of A, go through the cases hoping to
7177 get rid of everything but a constant. */
7180 {
7193 }
7195 {
7197 }
7199 {
7204 }
7206 {
7211 else
7213 }
7218 }
7220 rtx
7223 {
7226 /* The value that G1 will be multiplied by must be a constant integer. Also,
7227 the only chance we have of getting a valid address is if b*c/a (see above
7228 for notation) is also an integer. */
7231 {
7236 }
7239 else
7240 {
7241 /* ??? Find out if the one is a multiple of the other? */
7243 }
7247 {
7248 /* Failed. If we've got a multiplication factor between G1 and G2,
7249 scale G1's addend and try again. */
7251 {
7255 {
7256 HOST_WIDE_INT m;
7260 }
7261 else
7262 {
7264 mult);
7265 }
7268 }
7269 }
7273 /* Form simplified final result. */
7278 else
7283 else
7284 {
7287 {
7291 }
7294 }
7295 }
7296 \f
7297 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7298 represented by G1. This indicates that G2 should be combined with G1 and
7299 that G2 can use (either directly or via an address expression) a register
7300 used to represent G1. */
7302 static rtx
7305 {
7308 /* With the introduction of ext dependent givs, we must care for modes.
7309 G2 must not use a wider mode than G1. */
7319 /* If these givs are identical, they can be combined. We use the results
7320 of express_from because the addends are not in a canonical form, so
7321 rtx_equal_p is a weaker test. */
7322 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7323 combination to be the other way round. */
7326 {
7328 }
7330 /* If G2 can be expressed as a function of G1 and that function is valid
7331 as an address and no more expensive than using a register for G2,
7332 the expression of G2 in terms of G1 can be used. */
7336 /* ??? Looses, especially with -fforce-addr, where *g2->location
7337 will always be a register, and so anything more complicated
7338 gets discarded. */
7339 #if 0
7340 #ifdef ADDRESS_COST
7342 #else
7344 #endif
7345 #endif
7346 )
7347 {
7349 }
7352 }
7353 \f
7354 /* Check each extension dependent giv in this class to see if its
7355 root biv is safe from wrapping in the interior mode, which would
7356 make the giv illegal. */
7358 static void
7362 {
7365 HOST_WIDE_INT start_val;
7371 /* Make sure the iteration data is available. We must have
7372 constants in order to be certain of no overflow. */
7373 /* ??? An unknown iteration count with an increment of +-1
7374 combined with friendly exit tests of against an invariant
7375 value is also ameanable to optimization. Not implemented. */
7381 /* Make sure the host can represent the arithmetic. */
7383 {
7385 HOST_WIDE_INT s_end_val;
7397 /* Check for host arithmatic overflow. */
7399 {
7401 HOST_WIDE_INT s_max;
7408 /* Check zero extension of biv ok. */
7410 /* Check for host arithmatic overflow. */
7411 && (neg_incr
7414 /* Check for target arithmetic overflow. */
7415 && (neg_incr
7418 {
7420 }
7422 /* Check sign extension of biv ok. */
7423 /* ??? While it is true that overflow with signed and pointer
7424 arithmetic is undefined, I fear too many programmers don't
7425 keep this fact in mind -- myself included on occasion.
7426 So leave alone with the signed overflow optimizations. */
7428 /* Check for host arithmatic overflow. */
7429 && (neg_incr
7432 /* Check for target arithmetic overflow. */
7433 && (neg_incr
7436 {
7438 }
7439 }
7440 }
7442 /* Invalidate givs that fail the tests. */
7445 {
7450 {
7459 /* We don't know whether this value is being used as either
7460 signed or unsigned, so to safely truncate we must satisfy
7461 both. The initial check here verifies the BIV itself;
7462 once that is successful we may check its range wrt the
7463 derived GIV. */
7465 {
7469 /* We know from the above that both endpoints are nonnegative,
7470 and that there is no wrapping. Verify that both endpoints
7471 are within the (signed) range of the outer mode. */
7474 }
7479 }
7482 {
7484 {
7488 }
7489 }
7490 else
7491 {
7493 {
7498 else
7499 {
7504 else
7506 }
7511 }
7514 }
7515 }
7516 }
7518 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7520 rtx
7523 rtx value;
7524 {
7530 /* Recall that check_ext_dependent_givs verified that the known bounds
7531 of a biv did not overflow or wrap with respect to the extension for
7532 the giv. Therefore, constants need no additional adjustment. */
7536 /* Otherwise, we must adjust the value to compensate for the
7537 differing modes of the biv and the giv. */
7539 }
7540 \f
7541 struct combine_givs_stats
7542 {
7545 };
7547 static int
7551 {
7558 /* Stabilize the sort. */
7562 }
7564 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7565 any other. If so, point SAME to the giv combined with and set NEW_REG to
7566 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7567 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7569 static void
7573 {
7574 /* Additional benefit to add for being combined multiple times. */
7582 /* Count givs, because bl->giv_count is incorrect here. */
7586 giv_count++;
7588 giv_array
7599 {
7601 rtx single_use;
7606 /* If a DEST_REG GIV is used only once, do not allow it to combine
7607 with anything, for in doing so we will gain nothing that cannot
7608 be had by simply letting the GIV with which we would have combined
7609 to be reduced on its own. The losage shows up in particular with
7610 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7611 be seen elsewhere as well. */
7618 /* Add an additional weight for zero addends. */
7623 {
7624 rtx this_combine;
7629 {
7632 }
7633 }
7635 }
7637 /* Iterate, combining until we can't. */
7638 restart:
7642 {
7645 {
7651 }
7653 }
7656 {
7662 /* If it has already been combined, skip. */
7667 {
7670 /* If it has already been combined, skip. */
7672 {
7677 /* For destination, we now may replace by mem expression instead
7678 of register. This changes the costs considerably, so add the
7679 compensation. */
7689 /* ??? The new final_[bg]iv_value code does a much better job
7690 of finding replaceable giv's, and hence this code may no
7691 longer be necessary. */
7695 /* To help optimize the next set of combinations, remove
7696 this giv from the benefits of other potential mates. */
7698 {
7702 }
7709 }
7710 }
7712 /* To help optimize the next set of combinations, remove
7713 this giv from the benefits of other potential mates. */
7715 {
7717 {
7721 }
7725 /* We've finished with this giv, and everything it touched.
7726 Restart the combination so that proper weights for the
7727 rest of the givs are properly taken into account. */
7728 /* ??? Ideally we would compact the arrays at this point, so
7729 as to not cover old ground. But sanely compacting
7730 can_combine is tricky. */
7732 }
7733 }
7735 /* Clean up. */
7738 }
7739 \f
7740 /* Generate sequence for REG = B * M + A. */
7742 static rtx
7748 {
7749 rtx seq;
7750 rtx result;
7753 /* Use unsigned arithmetic. */
7761 }
7764 /* Update registers created in insn sequence SEQ. */
7766 static void
7769 rtx seq;
7770 {
7771 rtx insn;
7773 /* Update register info for alias analysis. */
7779 {
7782 {
7789 }
7790 }
7794 }
7797 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7799 void
7806 basic_block before_bb;
7807 rtx before_insn;
7808 {
7809 rtx seq;
7812 {
7815 }
7817 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7820 /* Increase the lifetime of any invariants moved further in code. */
7827 /* It is possible that the expansion created lots of new registers.
7828 Iterate over the sequence we just created and record them all. */
7830 }
7833 /* Emit insns in loop pre-header to set REG = B * M + A. */
7835 void
7842 {
7843 rtx seq;
7845 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7848 /* Increase the lifetime of any invariants moved further in code.
7849 ???? Is this really necessary? */
7856 /* It is possible that the expansion created lots of new registers.
7857 Iterate over the sequence we just created and record them all. */
7859 }
7862 /* Emit insns after loop to set REG = B * M + A. */
7864 void
7871 {
7872 rtx seq;
7874 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7879 /* It is possible that the expansion created lots of new registers.
7880 Iterate over the sequence we just created and record them all. */
7882 }
7886 /* Similar to gen_add_mult, but compute cost rather than generating
7887 sequence. */
7889 static int
7895 {
7905 {
7910 }
7913 }
7914 \f
7915 /* Test whether A * B can be computed without
7916 an actual multiply insn. Value is 1 if so.
7918 ??? This function stinks because it generates a ton of wasted RTL
7919 ??? and as a result fragments GC memory to no end. There are other
7920 ??? places in the compiler which are invoked a lot and do the same
7921 ??? thing, generate wasted RTL just to see if something is possible. */
7923 static int
7925 rtx a;
7926 rtx b;
7927 {
7928 rtx tmp;
7931 /* If only one is constant, make it B. */
7935 /* If first constant, both constant, so don't need multiply. */
7939 /* If second not constant, neither is constant, so would need multiply. */
7943 /* One operand is constant, so might not need multiply insn. Generate the
7944 code for the multiply and see if a call or multiply, or long sequence
7945 of insns is generated. */
7954 {
7957 {
7967 {
7970 }
7973 }
7974 }
7984 }
7985 \f
7986 /* Check to see if loop can be terminated by a "decrement and branch until
7987 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7988 Also try reversing an increment loop to a decrement loop
7989 to see if the optimization can be performed.
7990 Value is nonzero if optimization was performed. */
7992 /* This is useful even if the architecture doesn't have such an insn,
7993 because it might change a loops which increments from 0 to n to a loop
7994 which decrements from n to 0. A loop that decrements to zero is usually
7995 faster than one that increments from zero. */
7997 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7998 such as approx_final_value, biv_total_increment, loop_iterations, and
7999 final_[bg]iv_value. */
8001 static int
8005 {
8010 rtx reg;
8011 rtx jump_label;
8012 rtx final_value;
8013 rtx start_value;
8014 rtx new_add_val;
8015 rtx comparison;
8016 rtx before_comparison;
8017 rtx p;
8018 rtx jump;
8019 rtx first_compare;
8024 /* If last insn is a conditional branch, and the insn before tests a
8025 register value, try to optimize it. Otherwise, we can't do anything. */
8034 /* Try to compute whether the compare/branch at the loop end is one or
8035 two instructions. */
8041 else
8044 {
8045 /* If more than one condition is present to control the loop, then
8046 do not proceed, as this function does not know how to rewrite
8047 loop tests with more than one condition.
8049 Look backwards from the first insn in the last comparison
8050 sequence and see if we've got another comparison sequence. */
8052 rtx jump1;
8056 }
8058 /* Check all of the bivs to see if the compare uses one of them.
8059 Skip biv's set more than once because we can't guarantee that
8060 it will be zero on the last iteration. Also skip if the biv is
8061 used between its update and the test insn. */
8064 {
8069 first_compare))
8071 }
8076 /* Look for the case where the basic induction variable is always
8077 nonnegative, and equals zero on the last iteration.
8078 In this case, add a reg_note REG_NONNEG, which allows the
8079 m68k DBRA instruction to be used. */
8087 {
8088 /* Initial value must be greater than 0,
8089 init_val % -dec_value == 0 to ensure that it equals zero on
8090 the last iteration */
8096 {
8097 /* register always nonnegative, add REG_NOTE to branch */
8105 }
8107 /* If the decrement is 1 and the value was tested as >= 0 before
8108 the loop, then we can safely optimize. */
8110 {
8123 {
8131 }
8132 }
8133 }
8136 {
8137 /* Try to change inc to dec, so can apply above optimization. */
8138 /* Can do this if:
8139 all registers modified are induction variables or invariant,
8140 all memory references have non-overlapping addresses
8141 (obviously true if only one write)
8142 allow 2 insns for the compare/jump at the end of the loop. */
8143 /* Also, we must avoid any instructions which use both the reversed
8144 biv and another biv. Such instructions will fail if the loop is
8145 reversed. We meet this condition by requiring that either
8146 no_use_except_counting is true, or else that there is only
8147 one biv. */
8149 /* 1 if the iteration var is used only to count iterations. */
8151 /* 1 if the loop has no memory store, or it has a single memory store
8152 which is reversible. */
8158 {
8162 /* If there are no givs for this biv, and the only exit is the
8163 fall through at the end of the loop, then
8164 see if perhaps there are no uses except to count. */
8168 {
8173 /* An insn that sets the biv is okay. */
8174 ;
8178 {
8179 /* If either of these insns uses the biv and sets a pseudo
8180 that has more than one usage, then the biv has uses
8181 other than counting since it's used to derive a value
8182 that is used more than one time. */
8184 regs);
8186 {
8189 }
8190 }
8192 {
8195 }
8196 }
8198 /* A biv has uses besides counting if it is used to set
8199 another biv. */
8203 {
8206 }
8207 }
8210 /* No need to worry about MEMs. */
8211 ;
8213 {
8218 /* If the loop has a single store, and the destination address is
8219 invariant, then we can't reverse the loop, because this address
8220 might then have the wrong value at loop exit.
8221 This would work if the source was invariant also, however, in that
8222 case, the insn should have been moved out of the loop. */
8225 {
8228 /* If we could prove that each of the memory locations
8229 written to was different, then we could reverse the
8230 store -- but we don't presently have any way of
8231 knowing that. */
8234 /* If the store depends on a register that is set after the
8235 store, it depends on the initial value, and is thus not
8236 reversible. */
8238 {
8245 }
8246 }
8247 }
8248 else
8251 /* This code only acts for innermost loops. Also it simplifies
8252 the memory address check by only reversing loops with
8253 zero or one memory access.
8254 Two memory accesses could involve parts of the same array,
8255 and that can't be reversed.
8256 If the biv is used only for counting, than we don't need to worry
8257 about all these things. */
8263 && reversible_mem_store
8268 {
8269 rtx tem;
8271 /* Loop can be reversed. */
8275 /* Now check other conditions:
8277 The increment must be a constant, as must the initial value,
8278 and the comparison code must be LT.
8280 This test can probably be improved since +/- 1 in the constant
8281 can be obtained by changing LT to LE and vice versa; this is
8282 confusing. */
8285 /* for constants, LE gets turned into LT */
8289 {
8300 comparison_const_width
8302 else
8303 comparison_const_width
8307 comparison_sign_mask
8310 /* If the comparison value is not a loop invariant, then we
8311 can not reverse this loop.
8313 ??? If the insns which initialize the comparison value as
8314 a whole compute an invariant result, then we could move
8315 them out of the loop and proceed with loop reversal. */
8323 /* Normalize the initial value if it is an integer and
8324 has no other use except as a counter. This will allow
8325 a few more loops to be reversed. */
8329 {
8331 /* The code below requires comparison_val to be a multiple
8332 of add_val in order to do the loop reversal, so
8333 round up comparison_val to a multiple of add_val.
8334 Since comparison_value is constant, we know that the
8335 current comparison code is LT. */
8337 comparison_val
8339 /* We postpone overflow checks for COMPARISON_VAL here;
8340 even if there is an overflow, we might still be able to
8341 reverse the loop, if converting the loop exit test to
8342 NE is possible. */
8344 }
8346 /* First check if we can do a vanilla loop reversal. */
8348 /* If we have a decrement_and_branch_on_count,
8349 prefer the NE test, since this will allow that
8350 instruction to be generated. Note that we must
8351 use a vanilla loop reversal if the biv is used to
8352 calculate a giv or has a non-counting use. */
8353 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8354 && defined (HAVE_decrement_and_branch_on_count)
8358 #endif
8360 /* Now do postponed overflow checks on COMPARISON_VAL. */
8363 {
8364 /* Register will always be nonnegative, with value
8365 0 on last iteration */
8369 }
8373 {
8376 }
8377 else
8383 /* If the initial value is not zero, or if the comparison
8384 value is not an exact multiple of the increment, then we
8385 can not reverse this loop. */
8388 {
8391 }
8392 else
8393 {
8396 }
8400 /* Reset these in case we normalized the initial value
8401 and comparison value above. */
8404 {
8406 final_value
8408 }
8411 /* Save some info needed to produce the new insns. */
8416 /* Set start_value; if this is not a CONST_INT, we need
8417 to generate a SUB.
8418 Initialize biv to start_value before loop start.
8419 The old initializing insn will be deleted as a
8420 dead store by flow.c. */
8423 {
8426 }
8428 {
8436 start_value
8442 }
8444 {
8447 initial_value);
8451 start_value
8454 }
8455 else
8456 /* We could handle the other cases too, but it'll be
8457 better to have a testcase first. */
8460 /* We may not have a single insn which can increment a reg, so
8461 create a sequence to hold all the insns from expand_inc. */
8470 /* Update biv info to reflect its new status. */
8475 /* Update loop info. */
8484 /* Inc LABEL_NUSES so that delete_insn will
8485 not delete the label. */
8488 /* Emit an insn after the end of the loop to set the biv's
8489 proper exit value if it is used anywhere outside the loop. */
8495 /* Delete compare/branch at end of loop. */
8500 /* Add new compare/branch insn at end of loop. */
8512 ;
8518 {
8520 {
8521 /* Increment of LABEL_NUSES done above. */
8522 /* Register is now always nonnegative,
8523 so add REG_NONNEG note to the branch. */
8526 }
8528 }
8530 /* No insn may reference both the reversed and another biv or it
8531 will fail (see comment near the top of the loop reversal
8532 code).
8533 Earlier on, we have verified that the biv has no use except
8534 counting, or it is the only biv in this function.
8535 However, the code that computes no_use_except_counting does
8536 not verify reg notes. It's possible to have an insn that
8537 references another biv, and has a REG_EQUAL note with an
8538 expression based on the reversed biv. To avoid this case,
8539 remove all REG_EQUAL notes based on the reversed biv
8540 here. */
8543 {
8546 /* If this is a set of a GIV based on the reversed biv, any
8547 REG_EQUAL notes should still be correct. */
8554 {
8559 else
8561 }
8562 }
8564 /* Mark that this biv has been reversed. Each giv which depends
8565 on this biv, and which is also live past the end of the loop
8566 will have to be fixed up. */
8571 {
8575 else
8577 }
8580 }
8581 }
8582 }
8585 }
8586 \f
8587 /* Verify whether the biv BL appears to be eliminable,
8588 based on the insns in the loop that refer to it.
8590 If ELIMINATE_P is nonzero, actually do the elimination.
8592 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8593 determine whether invariant insns should be placed inside or at the
8594 start of the loop. */
8596 static int
8602 {
8605 rtx p;
8607 /* Scan all insns in the loop, stopping if we find one that uses the
8608 biv in a way that we cannot eliminate. */
8611 {
8616 /* If this is a libcall that sets a giv, skip ahead to its end. */
8618 {
8622 {
8627 {
8634 }
8635 }
8636 }
8641 {
8647 }
8648 }
8651 {
8656 }
8659 }
8660 \f
8661 /* INSN and REFERENCE are instructions in the same insn chain.
8662 Return nonzero if INSN is first. */
8664 int
8667 {
8671 {
8672 /* Start with test for not first so that INSN == REFERENCE yields not
8673 first. */
8679 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8680 previous insn, hence the <= comparison below does not work if
8681 P is a note. */
8692 }
8693 }
8695 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8696 the offset that we have to take into account due to auto-increment /
8697 div derivation is zero. */
8698 static int
8701 rtx insn;
8702 {
8703 /* If the giv V had the auto-inc address optimization applied
8704 to it, and INSN occurs between the giv insn and the biv
8705 insn, then we'd have to adjust the value used here.
8706 This is rare, so we don't bother to make this possible. */
8715 }
8717 /* If BL appears in X (part of the pattern of INSN), see if we can
8718 eliminate its use. If so, return 1. If not, return 0.
8720 If BIV does not appear in X, return 1.
8722 If ELIMINATE_P is nonzero, actually do the elimination.
8723 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8724 Depending on how many items have been moved out of the loop, it
8725 will either be before INSN (when WHERE_INSN is nonzero) or at the
8726 start of the loop (when WHERE_INSN is zero). */
8728 static int
8734 basic_block where_bb;
8735 rtx where_insn;
8736 {
8742 #ifdef HAVE_cc0
8744 #endif
8750 {
8752 /* If we haven't already been able to do something with this BIV,
8753 we can't eliminate it. */
8759 /* If this sets the BIV, it is not a problem. */
8763 /* If this is an insn that defines a giv, it is also ok because
8764 it will go away when the giv is reduced. */
8769 #ifdef HAVE_cc0
8771 {
8772 /* Can replace with any giv that was reduced and
8773 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8774 Require a constant for MULT_VAL, so we know it's nonzero.
8775 ??? We disable this optimization to avoid potential
8776 overflows. */
8784 {
8791 /* If the giv has the opposite direction of change,
8792 then reverse the comparison. */
8796 else
8799 /* We can probably test that giv's reduced reg. */
8802 }
8804 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8805 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8806 Require a constant for MULT_VAL, so we know it's nonzero.
8807 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8808 overflow problem. */
8820 {
8827 /* If the giv has the opposite direction of change,
8828 then reverse the comparison. */
8832 else
8836 /* Replace biv with the giv's reduced register. */
8841 /* Insn doesn't support that constant or invariant. Copy it
8842 into a register (it will be a loop invariant.) */
8849 /* Substitute the new register for its invariant value in
8850 the compare expression. */
8854 }
8855 }
8856 #endif
8863 /* See if either argument is the biv. */
8868 else
8872 {
8873 /* First try to replace with any giv that has constant positive
8874 mult_val and constant add_val. We might be able to support
8875 negative mult_val, but it seems complex to do it in general. */
8887 {
8891 /* Don't eliminate if the linear combination that makes up
8892 the giv overflows when it is applied to ARG. */
8894 {
8895 rtx add_val;
8899 else
8905 }
8910 /* Replace biv with the giv's reduced reg. */
8913 /* If all constants are actually constant integers and
8914 the derived constant can be directly placed in the COMPARE,
8915 do so. */
8918 {
8921 }
8922 else
8923 {
8924 /* Otherwise, load it into a register. */
8929 }
8935 }
8937 /* Look for giv with positive constant mult_val and nonconst add_val.
8938 Insert insns to calculate new compare value.
8939 ??? Turn this off due to possible overflow. */
8947 {
8948 rtx tem;
8958 /* Replace biv with giv's reduced register. */
8962 /* Compute value to compare against. */
8966 /* Use it in this insn. */
8970 }
8971 }
8973 {
8975 {
8976 /* Look for giv with constant positive mult_val and nonconst
8977 add_val. Insert insns to compute new compare value.
8978 ??? Turn this off due to possible overflow. */
8985 {
8986 rtx tem;
8996 /* Replace biv with giv's reduced register. */
9000 /* Compute value to compare against. */
9007 }
9008 }
9010 /* This code has problems. Basically, you can't know when
9011 seeing if we will eliminate BL, whether a particular giv
9012 of ARG will be reduced. If it isn't going to be reduced,
9013 we can't eliminate BL. We can try forcing it to be reduced,
9014 but that can generate poor code.
9016 The problem is that the benefit of reducing TV, below should
9017 be increased if BL can actually be eliminated, but this means
9018 we might have to do a topological sort of the order in which
9019 we try to process biv. It doesn't seem worthwhile to do
9020 this sort of thing now. */
9022 #if 0
9023 /* Otherwise the reg compared with had better be a biv. */
9028 /* Look for a pair of givs, one for each biv,
9029 with identical coefficients. */
9031 {
9043 {
9050 /* Replace biv with its giv's reduced reg. */
9052 /* Replace other operand with the other giv's
9053 reduced reg. */
9056 }
9057 }
9058 #endif
9059 }
9061 /* If we get here, the biv can't be eliminated. */
9065 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9066 biv is used in it, since it will be replaced. */
9074 }
9076 /* See if any subexpression fails elimination. */
9079 {
9081 {
9094 }
9095 }
9098 }
9099 \f
9100 /* Return nonzero if the last use of REG
9101 is in an insn following INSN in the same basic block. */
9103 static int
9105 rtx reg;
9106 rtx insn;
9107 {
9108 rtx n;
9112 {
9115 }
9117 }
9118 \f
9119 /* Called via `note_stores' to record the initial value of a biv. Here we
9120 just record the location of the set and process it later. */
9122 static void
9124 rtx dest;
9125 rtx set;
9127 {
9138 /* If this is the first set found, record it. */
9140 {
9143 }
9144 }
9145 \f
9146 /* If any of the registers in X are "old" and currently have a last use earlier
9147 than INSN, update them to have a last use of INSN. Their actual last use
9148 will be the previous insn but it will not have a valid uid_luid so we can't
9149 use it. X must be a source expression only. */
9151 static void
9153 rtx x;
9154 rtx insn;
9155 {
9156 /* Check for the case where INSN does not have a valid luid. In this case,
9157 there is no need to modify the regno_last_uid, as this can only happen
9158 when code is inserted after the loop_end to set a pseudo's final value,
9159 and hence this insn will never be the last use of x.
9160 ???? This comment is not correct. See for example loop_givs_reduce.
9161 This may insert an insn before another new insn. */
9165 {
9167 }
9168 else
9169 {
9173 {
9179 }
9180 }
9181 }
9182 \f
9183 /* Given an insn INSN and condition COND, return the condition in a
9184 canonical form to simplify testing by callers. Specifically:
9186 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9187 (2) Both operands will be machine operands; (cc0) will have been replaced.
9188 (3) If an operand is a constant, it will be the second operand.
9189 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9190 for GE, GEU, and LEU.
9192 If the condition cannot be understood, or is an inequality floating-point
9193 comparison which needs to be reversed, 0 will be returned.
9195 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9197 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9198 insn used in locating the condition was found. If a replacement test
9199 of the condition is desired, it should be placed in front of that
9200 insn and we will be sure that the inputs are still valid.
9202 If WANT_REG is nonzero, we wish the condition to be relative to that
9203 register, if possible. Therefore, do not canonicalize the condition
9204 further. */
9206 rtx
9208 rtx insn;
9209 rtx cond;
9212 rtx want_reg;
9213 {
9216 rtx set;
9217 rtx tem;
9235 /* If we are comparing a register with zero, see if the register is set
9236 in the previous insn to a COMPARE or a comparison operation. Perform
9237 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9238 in cse.c */
9243 {
9244 /* Set nonzero when we find something of interest. */
9247 #ifdef HAVE_cc0
9248 /* If comparison with cc0, import actual comparison from compare
9249 insn. */
9251 {
9262 }
9263 #endif
9265 /* If this is a COMPARE, pick up the two things being compared. */
9267 {
9271 }
9275 /* Go back to the previous insn. Stop if it is not an INSN. We also
9276 stop if it isn't a single set or if it has a REG_INC note because
9277 we don't want to bother dealing with it. */
9291 /* If this is setting OP0, get what it sets it to if it looks
9292 relevant. */
9294 {
9296 #ifdef FLOAT_STORE_FLAG_VALUE
9297 REAL_VALUE_TYPE fsfv;
9298 #endif
9300 /* ??? We may not combine comparisons done in a CCmode with
9301 comparisons not done in a CCmode. This is to aid targets
9302 like Alpha that have an IEEE compliant EQ instruction, and
9303 a non-IEEE compliant BEQ instruction. The use of CCmode is
9304 actually artificial, simply to prevent the combination, but
9305 should not affect other platforms.
9307 However, we must allow VOIDmode comparisons to match either
9308 CCmode or non-CCmode comparison, because some ports have
9309 modeless comparisons inside branch patterns.
9311 ??? This mode check should perhaps look more like the mode check
9312 in simplify_comparison in combine. */
9320 && (STORE_FLAG_VALUE
9323 #ifdef FLOAT_STORE_FLAG_VALUE
9328 #endif
9329 ))
9340 && (STORE_FLAG_VALUE
9343 #ifdef FLOAT_STORE_FLAG_VALUE
9348 #endif
9349 ))
9355 {
9358 }
9359 else
9361 }
9364 /* If this sets OP0, but not directly, we have to give up. */
9368 {
9372 {
9377 }
9382 }
9383 }
9385 /* If constant is first, put it last. */
9389 /* If OP0 is the result of a comparison, we weren't able to find what
9390 was really being compared, so fail. */
9394 /* Canonicalize any ordered comparison with integers involving equality
9395 if we can do computations in the relevant mode and we do not
9396 overflow. */
9401 {
9404 unsigned HOST_WIDE_INT max_val
9408 {
9414 /* When cross-compiling, const_val might be sign-extended from
9415 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9435 }
9436 }
9438 #ifdef HAVE_cc0
9439 /* Never return CC0; return zero instead. */
9442 #endif
9445 }
9447 /* Given a jump insn JUMP, return the condition that will cause it to branch
9448 to its JUMP_LABEL. If the condition cannot be understood, or is an
9449 inequality floating-point comparison which needs to be reversed, 0 will
9450 be returned.
9452 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9453 insn used in locating the condition was found. If a replacement test
9454 of the condition is desired, it should be placed in front of that
9455 insn and we will be sure that the inputs are still valid. */
9457 rtx
9459 rtx jump;
9461 {
9462 rtx cond;
9464 rtx set;
9466 /* If this is not a standard conditional jump, we can't parse it. */
9474 /* If this branches to JUMP_LABEL when the condition is false, reverse
9475 the condition. */
9476 reverse
9481 }
9483 /* Similar to above routine, except that we also put an invariant last
9484 unless both operands are invariants. */
9486 rtx
9489 rtx x;
9490 {
9500 }
9502 /* Scan the function and determine whether it has indirect (computed) jumps.
9504 This is taken mostly from flow.c; similar code exists elsewhere
9505 in the compiler. It may be useful to put this into rtlanal.c. */
9506 static int
9508 rtx start;
9509 {
9510 rtx insn;
9517 }
9519 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9520 documentation for LOOP_MEMS for the definition of `appropriate'.
9521 This function is called from prescan_loop via for_each_rtx. */
9523 static int
9527 {
9536 {
9541 /* We're not interested in MEMs that are only clobbered. */
9545 /* We're not interested in the MEM associated with a
9546 CONST_DOUBLE, so there's no need to traverse into this. */
9550 /* We're not interested in any MEMs that only appear in notes. */
9554 /* This is not a MEM. */
9556 }
9558 /* See if we've already seen this MEM. */
9561 {
9563 /* The modes of the two memory accesses are different. If
9564 this happens, something tricky is going on, and we just
9565 don't optimize accesses to this MEM. */
9569 }
9571 /* Resize the array, if necessary. */
9573 {
9576 else
9582 }
9584 /* Actually insert the MEM. */
9586 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9587 because we can't put it in a register. We still store it in the
9588 table, though, so that if we see the same address later, but in a
9589 non-BLK mode, we'll not think we can optimize it at that point. */
9595 }
9598 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9600 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9601 register that is modified by an insn between FROM and TO. If the
9602 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9603 more, stop incrementing it, to avoid overflow.
9605 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9606 register I is used, if it is only used once. Otherwise, it is set
9607 to 0 (for no uses) or const0_rtx for more than one use. This
9608 parameter may be zero, in which case this processing is not done.
9610 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9611 optimize register I. */
9613 static void
9617 {
9620 /* last_set[n] is nonzero iff reg n has been set in the current
9621 basic block. In that case, it is the insn that last set reg n. */
9623 rtx insn;
9629 /* Grow the regs array if not allocated or too small. */
9631 {
9637 /* Zero the new elements. */
9640 }
9642 /* Clear previously scanned fields but do not clear n_times_set. */
9644 {
9648 }
9652 /* Scan the loop, recording register usage. */
9655 {
9657 {
9658 /* Record registers that have exactly one use. */
9661 /* Include uses in REG_EQUAL notes. */
9669 {
9673 last_set);
9674 }
9675 }
9680 /* Invalidate all registers used for function argument passing.
9681 We check rtx_varies_p for the same reason as below, to allow
9682 optimizing PIC calculations. */
9684 {
9685 rtx link;
9687 link;
9689 {
9696 }
9697 }
9698 }
9700 /* Invalidate all hard registers clobbered by calls. With one exception:
9701 a call-clobbered PIC register is still function-invariant for our
9702 purposes, since we can hoist any PIC calculations out of the loop.
9703 Thus the call to rtx_varies_p. */
9708 {
9711 }
9713 #ifdef AVOID_CCMODE_COPIES
9714 /* Don't try to move insns which set CC registers if we should not
9715 create CCmode register copies. */
9719 #endif
9721 /* Set regs->array[I].n_times_set for the new registers. */
9726 }
9728 /* Returns the number of real INSNs in the LOOP. */
9730 static int
9733 {
9735 rtx insn;
9743 }
9745 /* Move MEMs into registers for the duration of the loop. */
9747 static void
9750 {
9757 rtx end_label;
9758 /* Nonzero if the next instruction may never be executed. */
9765 /* We cannot use next_label here because it skips over normal insns. */
9770 /* Check to see if it's possible that some instructions in the loop are
9771 never executed. Also check if there is a goto out of the loop other
9772 than right after the end of the loop. */
9776 {
9780 /* If we enter the loop in the middle, and scan
9781 around to the beginning, don't set maybe_never
9782 for that. This must be an unconditional jump,
9783 otherwise the code at the top of the loop might
9784 never be executed. Unconditional jumps are
9785 followed a by barrier then loop end. */
9790 {
9791 /* If this is a jump outside of the loop but not right
9792 after the end of the loop, we would have to emit new fixup
9793 sequences for each such label. */
9795 JUMP_INSN is executed, we must be conservative. */
9804 /* Something complicated. */
9806 else
9807 /* If there are any more instructions in the loop, they
9808 might not be reached. */
9810 }
9813 }
9815 /* Find start of the extended basic block that enters the loop. */
9819 ;
9824 /* Build table of mems that get set to constant values before the
9825 loop. */
9829 /* Actually move the MEMs. */
9831 {
9832 regset_head load_copies;
9833 regset_head store_copies;
9835 rtx reg;
9837 rtx mem_list_entry;
9841 /* There's no telling whether or not MEM is modified. */
9844 /* Go through the MEMs written to in the loop to see if this
9845 one is aliased by one of them. */
9848 {
9853 {
9854 /* MEM is indeed aliased by this store. */
9857 }
9859 }
9865 /* If this MEM is written to, we must be sure that there
9866 are no reads from another MEM that aliases this one. */
9868 {
9872 {
9876 VOIDmode,
9878 rtx_varies_p))
9879 {
9880 /* It's not safe to hoist loop_info->mems[i] out of
9881 the loop because writes to it might not be
9882 seen by reads from loop_info->mems[j]. */
9885 }
9886 }
9887 }
9890 /* We can't access the MEM outside the loop; it might
9891 cause a trap that wouldn't have happened otherwise. */
9895 /* We thought we were going to lift this MEM out of the
9896 loop, but later discovered that we could not. */
9902 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9903 order to keep scan_loop from moving stores to this MEM
9904 out of the loop just because this REG is neither a
9905 user-variable nor used in the loop test. */
9910 /* Now, replace all references to the MEM with the
9911 corresponding pseudos. */
9916 {
9918 {
9919 rtx set;
9923 /* See if this copies the mem into a register that isn't
9924 modified afterwards. We'll try to do copy propagation
9925 a little further on. */
9927 /* @@@ This test is _way_ too conservative. */
9928 && ! maybe_never
9936 /* See if this copies the mem from a register that isn't
9937 modified afterwards. We'll try to remove the
9938 redundant copy later on by doing a little register
9939 renaming and copy propagation. This will help
9940 to untangle things for the BIV detection code. */
9942 && ! maybe_never
9950 /* If this is a call which uses / clobbers this memory
9951 location, we must not change the interface here. */
9955 {
9959 }
9960 else
9961 /* Replace the memory reference with the shadow register. */
9964 }
9969 }
9974 /* We couldn't replace all occurrences of the MEM. */
9976 else
9977 {
9978 /* Load the memory immediately before LOOP->START, which is
9979 the NOTE_LOOP_BEG. */
9981 rtx set;
9987 {
9991 {
9995 /* Extending hard register lifetimes causes crash
9996 on SRC targets. Doing so on non-SRC is
9997 probably also not good idea, since we most
9998 probably have pseudoregister equivalence as
9999 well. */
10002 }
10003 /* Use the constant equivalence if that is cheap enough. */
10009 {
10012 }
10014 /* If best_equiv is nonzero, we know that MEM is set to a
10015 constant or register before the loop. We will use this
10016 knowledge to initialize the shadow register with that
10017 constant or reg rather than by loading from MEM. */
10020 }
10025 {
10028 {
10031 }
10032 }
10038 {
10040 {
10043 }
10045 /* Store the memory immediately after END, which is
10046 the NOTE_LOOP_END. */
10049 }
10052 {
10057 }
10059 /* Attempt a bit of copy propagation. This helps untangle the
10060 data flow, and enables {basic,general}_induction_var to find
10061 more bivs/givs. */
10062 EXECUTE_IF_SET_IN_REG_SET
10064 {
10066 });
10069 EXECUTE_IF_SET_IN_REG_SET
10071 {
10073 });
10075 }
10076 }
10079 {
10080 /* Now, we need to replace all references to the previous exit
10081 label with the new one. */
10082 rtx_pair rr;
10087 {
10090 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10091 field. This is not handled by for_each_rtx because it doesn't
10092 handle unprinted ('0') fields. We need to update JUMP_LABEL
10093 because the immediately following unroll pass will use it.
10094 replace_label would not work anyways, because that only handles
10095 LABEL_REFs. */
10098 }
10099 }
10102 }
10104 /* For communication between note_reg_stored and its caller. */
10105 struct note_reg_stored_arg
10106 {
10108 rtx reg;
10109 };
10111 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10112 is equal to ARG. */
10113 static void
10117 {
10121 }
10123 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10124 There must be exactly one insn that sets this pseudo; it will be
10125 deleted if all replacements succeed and we can prove that the register
10126 is not used after the loop. */
10128 static void
10131 rtx replacement;
10133 {
10134 /* This is the reg that we are copying from. */
10137 rtx insn;
10138 /* These help keep track of whether we replaced all uses of the reg. */
10145 {
10146 rtx set;
10148 /* Only substitute within one extended basic block from the initializing
10149 insn. */
10156 /* Is this the initializing insn? */
10161 {
10168 }
10170 /* Only substitute after seeing the initializing insn. */
10172 {
10179 /* Stop replacing when REPLACEMENT is modified. */
10184 {
10187 /* It is possible that we've turned previously valid REG_EQUAL to
10188 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10189 REPLACEMENT is modified, we get different meaning. */
10193 }
10194 }
10195 }
10199 {
10203 {
10204 rtx first;
10205 rtx retval_note;
10207 /* Assume we're just deleting INIT_INSN. */
10209 /* Look for REG_RETVAL note. If we're deleting the end of
10210 the libcall sequence, the whole sequence can go. */
10212 /* If we found a REG_RETVAL note, find the first instruction
10213 in the sequence. */
10217 /* Delete the instructions. */
10219 }
10222 }
10223 }
10225 /* Replace all the instructions from FIRST up to and including LAST
10226 with NOTE_INSN_DELETED notes. */
10228 static void
10230 rtx first;
10231 rtx last;
10232 {
10234 {
10240 /* If this was the LAST instructions we're supposed to delete,
10241 we're done. */
10246 }
10247 }
10249 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10250 loop LOOP if the order of the sets of these registers can be
10251 swapped. There must be exactly one insn within the loop that sets
10252 this pseudo followed immediately by a move insn that sets
10253 REPLACEMENT with REGNO. */
10254 static void
10257 rtx replacement;
10259 {
10260 rtx insn;
10269 {
10270 /* Search for the insn that copies REGNO to NEW_REGNO? */
10278 }
10281 {
10282 rtx prev_insn;
10283 rtx prev_set;
10285 /* Some DEF-USE info would come in handy here to make this
10286 function more general. For now, just check the previous insn
10287 which is the most likely candidate for setting REGNO. */
10295 {
10296 /* We have:
10297 (set (reg regno) (expr))
10298 (set (reg new_regno) (reg regno))
10300 so try converting this to:
10301 (set (reg new_regno) (expr))
10302 (set (reg regno) (reg new_regno))
10304 The former construct is often generated when a global
10305 variable used for an induction variable is shadowed by a
10306 register (NEW_REGNO). The latter construct improves the
10307 chances of GIV replacement and BIV elimination. */
10317 {
10324 /* Update first use of REGNO. */
10328 /* Now perform copy propagation to hopefully
10329 remove all uses of REGNO within the loop. */
10331 }
10332 }
10333 }
10334 }
10336 /* Replace MEM with its associated pseudo register. This function is
10337 called from load_mems via for_each_rtx. DATA is actually a pointer
10338 to a structure describing the instruction currently being scanned
10339 and the MEM we are currently replacing. */
10341 static int
10345 {
10353 {
10358 /* We're not interested in the MEM associated with a
10359 CONST_DOUBLE, so there's no need to traverse into one. */
10363 /* This is not a MEM. */
10365 }
10368 /* This is not the MEM we are currently replacing. */
10371 /* Actually replace the MEM. */
10375 }
10377 static void
10379 rtx insn;
10380 rtx mem;
10381 rtx reg;
10382 {
10383 loop_replace_args args;
10390 }
10392 /* Replace one register with another. Called through for_each_rtx; PX points
10393 to the rtx being scanned. DATA is actually a pointer to
10394 a structure of arguments. */
10396 static int
10400 {
10411 }
10413 static void
10415 rtx insn;
10416 rtx reg;
10417 rtx replacement;
10418 {
10419 loop_replace_args args;
10426 }
10428 /* Replace occurrences of the old exit label for the loop with the new
10429 one. DATA is an rtx_pair containing the old and new labels,
10430 respectively. */
10432 static int
10436 {
10455 }
10456 \f
10457 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10458 (ignored in the interim). */
10460 static rtx
10463 basic_block where_bb ATTRIBUTE_UNUSED;
10464 rtx where_insn;
10465 rtx pattern;
10466 {
10468 }
10471 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10472 in basic block WHERE_BB (ignored in the interim) within the loop
10473 otherwise hoist PATTERN into the loop pre-header. */
10475 rtx
10478 basic_block where_bb ATTRIBUTE_UNUSED;
10479 rtx where_insn;
10480 rtx pattern;
10481 {
10485 }
10488 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10489 WHERE_BB (ignored in the interim) within the loop. */
10491 static rtx
10494 basic_block where_bb ATTRIBUTE_UNUSED;
10495 rtx where_insn;
10496 rtx pattern;
10497 {
10499 }
10502 /* Hoist insn for PATTERN into the loop pre-header. */
10504 rtx
10507 rtx pattern;
10508 {
10510 }
10513 /* Hoist call insn for PATTERN into the loop pre-header. */
10515 static rtx
10518 rtx pattern;
10519 {
10521 }
10524 /* Sink insn for PATTERN after the loop end. */
10526 rtx
10529 rtx pattern;
10530 {
10532 }
10534 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10535 and constant. Emit sequence of intructions to load it into REG */
10536 static rtx
10539 {
10540 rtx seq;
10548 }
10550 /* If the loop has multiple exits, emit insn for PATTERN before the
10551 loop to ensure that it will always be executed no matter how the
10552 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10553 since this is slightly more efficient. */
10555 static rtx
10558 rtx pattern;
10559 {
10562 else
10564 }
10565 \f
10566 static void
10571 {
10579 iv_num++;
10584 {
10587 }
10588 }
10591 static void
10596 {
10598 rtx incr;
10609 {
10612 }
10614 {
10617 }
10621 {
10625 }
10628 {
10632 }
10634 /* List the increments. */
10636 {
10640 }
10642 /* List the givs. */
10644 {
10649 else
10652 }
10653 }
10656 static void
10661 {
10672 {
10676 }
10679 }
10682 static void
10687 {
10694 else
10710 {
10712 {
10724 }
10725 }
10736 {
10740 }
10743 }
10746 void
10749 {
10751 }
10754 void
10757 {
10759 }
10762 void
10765 {
10767 }
10770 void
10773 {
10775 }
10778 #define LOOP_BLOCK_NUM_1(INSN) \
10779 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10781 /* The notes do not have an assigned block, so look at the next insn. */
10782 #define LOOP_BLOCK_NUM(INSN) \
10783 ((INSN) ? (GET_CODE (INSN) == NOTE \
10784 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10785 : LOOP_BLOCK_NUM_1 (INSN)) \
10786 : -1)
10788 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10790 static void
10795 {
10796 rtx label;
10801 /* Print diagnostics to compare our concept of a loop with
10802 what the loop notes say. */
10817 {
10837 {
10840 {
10843 }
10844 }
10847 /* This can happen when a marked loop appears as two nested loops,
10848 say from while (a || b) {}. The inner loop won't match
10849 the loop markers but the outer one will. */
10852 }
10853 }
10855 /* Call this function from the debugger to dump LOOP. */
10857 void
10860 {
10862 }
10864 /* Call this function from the debugger to dump LOOPS. */
10866 void
10869 {
10871 }