gcc/config/aarch64/aarch64-protos.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2020 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_PROTOS_H
  23 #define GCC_AARCH64_PROTOS_H
  24
  25 #include "input.h"
  26
  27 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through
  28    high and lo relocs that calculate the base address using a PC
  29    relative reloc.
  30    So to get the address of foo, we generate
  31    adrp x0, foo
  32    add  x0, x0, :lo12:foo
  33
  34    To load or store something to foo, we could use the corresponding
  35    load store variants that generate an
  36    ldr x0, [x0,:lo12:foo]
  37    or
  38    str x1, [x0, :lo12:foo]
  39
  40    This corresponds to the small code model of the compiler.
  41
  42    SYMBOL_SMALL_GOT_4G: Similar to the one above but this
  43    gives us the GOT entry of the symbol being referred to :
  44    Thus calculating the GOT entry for foo is done using the
  45    following sequence of instructions.  The ADRP instruction
  46    gets us to the page containing the GOT entry of the symbol
  47    and the got_lo12 gets us the actual offset in it, together
  48    the base and offset, we can address 4G size GOT table.
  49
  50    adrp  x0, :got:foo
  51    ldr   x0, [x0, :gotoff_lo12:foo]
  52
  53    This corresponds to the small PIC model of the compiler.
  54
  55    SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol
  56    restricted within 28K GOT table size.
  57
  58    ldr reg, [gp, #:gotpage_lo15:sym]
  59
  60    This corresponds to -fpic model for small memory model of the compiler.
  61
  62    SYMBOL_SMALL_TLSGD
  63    SYMBOL_SMALL_TLSDESC
  64    SYMBOL_SMALL_TLSIE
  65    SYMBOL_TINY_TLSIE
  66    SYMBOL_TLSLE12
  67    SYMBOL_TLSLE24
  68    SYMBOL_TLSLE32
  69    SYMBOL_TLSLE48
  70    Each of these represents a thread-local symbol, and corresponds to the
  71    thread local storage relocation operator for the symbol being referred to.
  72
  73    SYMBOL_TINY_ABSOLUTE
  74
  75    Generate symbol accesses as a PC relative address using a single
  76    instruction.  To compute the address of symbol foo, we generate:
  77
  78    ADR x0, foo
  79
  80    SYMBOL_TINY_GOT
  81
  82    Generate symbol accesses via the GOT using a single PC relative
  83    instruction.  To compute the address of symbol foo, we generate:
  84
  85    ldr t0, :got:foo
  86
  87    The value of foo can subsequently read using:
  88
  89    ldrb    t0, [t0]
  90
  91    SYMBOL_FORCE_TO_MEM : Global variables are addressed using
  92    constant pool.  All variable addresses are spilled into constant
  93    pools.  The constant pools themselves are addressed using PC
  94    relative accesses.  This only works for the large code model.
  95  */
  96 enum aarch64_symbol_type
  97 {
  98   SYMBOL_SMALL_ABSOLUTE,
  99   SYMBOL_SMALL_GOT_28K,
 100   SYMBOL_SMALL_GOT_4G,
 101   SYMBOL_SMALL_TLSGD,
 102   SYMBOL_SMALL_TLSDESC,
 103   SYMBOL_SMALL_TLSIE,
 104   SYMBOL_TINY_ABSOLUTE,
 105   SYMBOL_TINY_GOT,
 106   SYMBOL_TINY_TLSIE,
 107   SYMBOL_TLSLE12,
 108   SYMBOL_TLSLE24,
 109   SYMBOL_TLSLE32,
 110   SYMBOL_TLSLE48,
 111   SYMBOL_FORCE_TO_MEM
 112 };
 113
 114 /* Classifies the type of an address query.
 115
 116    ADDR_QUERY_M
 117       Query what is valid for an "m" constraint and a memory_operand
 118       (the rules are the same for both).
 119
 120    ADDR_QUERY_LDP_STP
 121       Query what is valid for a load/store pair.
 122
 123    ADDR_QUERY_LDP_STP_N
 124       Query what is valid for a load/store pair, but narrow the incoming mode
 125       for address checking.  This is used for the store_pair_lanes patterns.
 126
 127    ADDR_QUERY_ANY
 128       Query what is valid for at least one memory constraint, which may
 129       allow things that "m" doesn't.  For example, the SVE LDR and STR
 130       addressing modes allow a wider range of immediate offsets than "m"
 131       does.  */
 132 enum aarch64_addr_query_type {
 133   ADDR_QUERY_M,
 134   ADDR_QUERY_LDP_STP,
 135   ADDR_QUERY_LDP_STP_N,
 136   ADDR_QUERY_ANY
 137 };
 138
 139 /* A set of tuning parameters contains references to size and time
 140    cost models and vectors for address cost calculations, register
 141    move costs and memory move costs.  */
 142
 143 /* Scaled addressing modes can vary cost depending on the mode of the
 144    value to be loaded/stored.  QImode values cannot use scaled
 145    addressing modes.  */
 146
 147 struct scale_addr_mode_cost
 148 {
 149   const int hi;
 150   const int si;
 151   const int di;
 152   const int ti;
 153 };
 154
 155 /* Additional cost for addresses.  */
 156 struct cpu_addrcost_table
 157 {
 158   const struct scale_addr_mode_cost addr_scale_costs;
 159   const int pre_modify;
 160   const int post_modify;
 161   const int register_offset;
 162   const int register_sextend;
 163   const int register_zextend;
 164   const int imm_offset;
 165 };
 166
 167 /* Additional costs for register copies.  Cost is for one register.  */
 168 struct cpu_regmove_cost
 169 {
 170   const int GP2GP;
 171   const int GP2FP;
 172   const int FP2GP;
 173   const int FP2FP;
 174 };
 175
 176 /* Cost for vector insn classes.  */
 177 struct cpu_vector_cost
 178 {
 179   const int scalar_int_stmt_cost;        /* Cost of any int scalar operation,
 180                                             excluding load and store.  */
 181   const int scalar_fp_stmt_cost;         /* Cost of any fp scalar operation,
 182                                             excluding load and store.  */
 183   const int scalar_load_cost;            /* Cost of scalar load.  */
 184   const int scalar_store_cost;           /* Cost of scalar store.  */
 185   const int vec_int_stmt_cost;           /* Cost of any int vector operation,
 186                                             excluding load, store, permute,
 187                                             vector-to-scalar and
 188                                             scalar-to-vector operation.  */
 189   const int vec_fp_stmt_cost;            /* Cost of any fp vector operation,
 190                                             excluding load, store, permute,
 191                                             vector-to-scalar and
 192                                             scalar-to-vector operation.  */
 193   const int vec_permute_cost;            /* Cost of permute operation.  */
 194   const int vec_to_scalar_cost;          /* Cost of vec-to-scalar operation.  */
 195   const int scalar_to_vec_cost;          /* Cost of scalar-to-vector
 196                                             operation.  */
 197   const int vec_align_load_cost;         /* Cost of aligned vector load.  */
 198   const int vec_unalign_load_cost;       /* Cost of unaligned vector load.  */
 199   const int vec_unalign_store_cost;      /* Cost of unaligned vector store.  */
 200   const int vec_store_cost;              /* Cost of vector store.  */
 201   const int cond_taken_branch_cost;      /* Cost of taken branch.  */
 202   const int cond_not_taken_branch_cost;  /* Cost of not taken branch.  */
 203 };
 204
 205 /* Branch costs.  */
 206 struct cpu_branch_cost
 207 {
 208   const int predictable;    /* Predictable branch or optimizing for size.  */
 209   const int unpredictable;  /* Unpredictable branch or optimizing for speed.  */
 210 };
 211
 212 /* Control approximate alternatives to certain FP operators.  */
 213 #define AARCH64_APPROX_MODE(MODE) \
 214   ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \
 215    ? (1 << ((MODE) - MIN_MODE_FLOAT)) \
 216    : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \
 217      ? (1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \
 218               + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \
 219      : (0))
 220 #define AARCH64_APPROX_NONE (0)
 221 #define AARCH64_APPROX_ALL (-1)
 222
 223 /* Allowed modes for approximations.  */
 224 struct cpu_approx_modes
 225 {
 226   const unsigned int division;          /* Division.  */
 227   const unsigned int sqrt;              /* Square root.  */
 228   const unsigned int recip_sqrt;        /* Reciprocal square root.  */
 229 };
 230
 231 /* Cache prefetch settings for prefetch-loop-arrays.  */
 232 struct cpu_prefetch_tune
 233 {
 234   const int num_slots;
 235   const int l1_cache_size;
 236   const int l1_cache_line_size;
 237   const int l2_cache_size;
 238   /* Whether software prefetch hints should be issued for non-constant
 239      strides.  */
 240   const bool prefetch_dynamic_strides;
 241   /* The minimum constant stride beyond which we should use prefetch
 242      hints for.  */
 243   const int minimum_stride;
 244   const int default_opt_level;
 245 };
 246
 247 struct tune_params
 248 {
 249   const struct cpu_cost_table *insn_extra_cost;
 250   const struct cpu_addrcost_table *addr_cost;
 251   const struct cpu_regmove_cost *regmove_cost;
 252   const struct cpu_vector_cost *vec_costs;
 253   const struct cpu_branch_cost *branch_costs;
 254   const struct cpu_approx_modes *approx_modes;
 255   /* Width of the SVE registers or SVE_NOT_IMPLEMENTED if not applicable.
 256      Only used for tuning decisions, does not disable VLA
 257      vectorization.  */
 258   enum aarch64_sve_vector_bits_enum sve_width;
 259   int memmov_cost;
 260   int issue_rate;
 261   unsigned int fusible_ops;
 262   const char *function_align;
 263   const char *jump_align;
 264   const char *loop_align;
 265   int int_reassoc_width;
 266   int fp_reassoc_width;
 267   int vec_reassoc_width;
 268   int min_div_recip_mul_sf;
 269   int min_div_recip_mul_df;
 270   /* Value for aarch64_case_values_threshold; or 0 for the default.  */
 271   unsigned int max_case_values;
 272 /* An enum specifying how to take into account CPU autoprefetch capabilities
 273    during instruction scheduling:
 274    - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account.
 275    - AUTOPREFETCHER_WEAK: Attempt to sort sequences of loads/store in order of
 276    offsets but allow the pipeline hazard recognizer to alter that order to
 277    maximize multi-issue opportunities.
 278    - AUTOPREFETCHER_STRONG: Attempt to sort sequences of loads/store in order of
 279    offsets and prefer this even if it restricts multi-issue opportunities.  */
 280
 281   enum aarch64_autoprefetch_model
 282   {
 283     AUTOPREFETCHER_OFF,
 284     AUTOPREFETCHER_WEAK,
 285     AUTOPREFETCHER_STRONG
 286   } autoprefetcher_model;
 287
 288   unsigned int extra_tuning_flags;
 289
 290   /* Place prefetch struct pointer at the end to enable type checking
 291      errors when tune_params misses elements (e.g., from erroneous merges).  */
 292   const struct cpu_prefetch_tune *prefetch;
 293 };
 294
 295 /* Classifies an address.
 296
 297    ADDRESS_REG_IMM
 298        A simple base register plus immediate offset.
 299
 300    ADDRESS_REG_WB
 301        A base register indexed by immediate offset with writeback.
 302
 303    ADDRESS_REG_REG
 304        A base register indexed by (optionally scaled) register.
 305
 306    ADDRESS_REG_UXTW
 307        A base register indexed by (optionally scaled) zero-extended register.
 308
 309    ADDRESS_REG_SXTW
 310        A base register indexed by (optionally scaled) sign-extended register.
 311
 312    ADDRESS_LO_SUM
 313        A LO_SUM rtx with a base register and "LO12" symbol relocation.
 314
 315    ADDRESS_SYMBOLIC:
 316        A constant symbolic address, in pc-relative literal pool.  */
 317
 318 enum aarch64_address_type {
 319   ADDRESS_REG_IMM,
 320   ADDRESS_REG_WB,
 321   ADDRESS_REG_REG,
 322   ADDRESS_REG_UXTW,
 323   ADDRESS_REG_SXTW,
 324   ADDRESS_LO_SUM,
 325   ADDRESS_SYMBOLIC
 326 };
 327
 328 /* Address information.  */
 329 struct aarch64_address_info {
 330   enum aarch64_address_type type;
 331   rtx base;
 332   rtx offset;
 333   poly_int64 const_offset;
 334   int shift;
 335   enum aarch64_symbol_type symbol_type;
 336 };
 337
 338 #define AARCH64_FUSION_PAIR(x, name) \
 339   AARCH64_FUSE_##name##_index,
 340 /* Supported fusion operations.  */
 341 enum aarch64_fusion_pairs_index
 342 {
 343 #include "aarch64-fusion-pairs.def"
 344   AARCH64_FUSE_index_END
 345 };
 346
 347 #define AARCH64_FUSION_PAIR(x, name) \
 348   AARCH64_FUSE_##name = (1u << AARCH64_FUSE_##name##_index),
 349 /* Supported fusion operations.  */
 350 enum aarch64_fusion_pairs
 351 {
 352   AARCH64_FUSE_NOTHING = 0,
 353 #include "aarch64-fusion-pairs.def"
 354   AARCH64_FUSE_ALL = (1u << AARCH64_FUSE_index_END) - 1
 355 };
 356
 357 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
 358   AARCH64_EXTRA_TUNE_##name##_index,
 359 /* Supported tuning flags indexes.  */
 360 enum aarch64_extra_tuning_flags_index
 361 {
 362 #include "aarch64-tuning-flags.def"
 363   AARCH64_EXTRA_TUNE_index_END
 364 };
 365
 366
 367 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
 368   AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index),
 369 /* Supported tuning flags.  */
 370 enum aarch64_extra_tuning_flags
 371 {
 372   AARCH64_EXTRA_TUNE_NONE = 0,
 373 #include "aarch64-tuning-flags.def"
 374   AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1
 375 };
 376
 377 /* Enum describing the various ways that the
 378    aarch64_parse_{arch,tune,cpu,extension} functions can fail.
 379    This way their callers can choose what kind of error to give.  */
 380
 381 enum aarch64_parse_opt_result
 382 {
 383   AARCH64_PARSE_OK,                     /* Parsing was successful.  */
 384   AARCH64_PARSE_MISSING_ARG,            /* Missing argument.  */
 385   AARCH64_PARSE_INVALID_FEATURE,        /* Invalid feature modifier.  */
 386   AARCH64_PARSE_INVALID_ARG             /* Invalid arch, tune, cpu arg.  */
 387 };
 388
 389 /* Enum to distinguish which type of check is to be done in
 390    aarch64_simd_valid_immediate.  This is used as a bitmask where
 391    AARCH64_CHECK_MOV has both bits set.  Thus AARCH64_CHECK_MOV will
 392    perform all checks.  Adding new types would require changes accordingly.  */
 393 enum simd_immediate_check {
 394   AARCH64_CHECK_ORR  = 1 << 0,
 395   AARCH64_CHECK_BIC  = 1 << 1,
 396   AARCH64_CHECK_MOV  = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
 397 };
 398
 399 /* The key type that -msign-return-address should use.  */
 400 enum aarch64_key_type {
 401   AARCH64_KEY_A,
 402   AARCH64_KEY_B
 403 };
 404
 405 extern enum aarch64_key_type aarch64_ra_sign_key;
 406
 407 extern struct tune_params aarch64_tune_params;
 408
 409 /* The available SVE predicate patterns, known in the ACLE as "svpattern".  */
 410 #define AARCH64_FOR_SVPATTERN(T) \
 411   T (POW2, pow2, 0) \
 412   T (VL1, vl1, 1) \
 413   T (VL2, vl2, 2) \
 414   T (VL3, vl3, 3) \
 415   T (VL4, vl4, 4) \
 416   T (VL5, vl5, 5) \
 417   T (VL6, vl6, 6) \
 418   T (VL7, vl7, 7) \
 419   T (VL8, vl8, 8) \
 420   T (VL16, vl16, 9) \
 421   T (VL32, vl32, 10) \
 422   T (VL64, vl64, 11) \
 423   T (VL128, vl128, 12) \
 424   T (VL256, vl256, 13) \
 425   T (MUL4, mul4, 29) \
 426   T (MUL3, mul3, 30) \
 427   T (ALL, all, 31)
 428
 429 /* The available SVE prefetch operations, known in the ACLE as "svprfop".  */
 430 #define AARCH64_FOR_SVPRFOP(T) \
 431   T (PLDL1KEEP, pldl1keep, 0) \
 432   T (PLDL1STRM, pldl1strm, 1) \
 433   T (PLDL2KEEP, pldl2keep, 2) \
 434   T (PLDL2STRM, pldl2strm, 3) \
 435   T (PLDL3KEEP, pldl3keep, 4) \
 436   T (PLDL3STRM, pldl3strm, 5) \
 437   T (PSTL1KEEP, pstl1keep, 8) \
 438   T (PSTL1STRM, pstl1strm, 9) \
 439   T (PSTL2KEEP, pstl2keep, 10) \
 440   T (PSTL2STRM, pstl2strm, 11) \
 441   T (PSTL3KEEP, pstl3keep, 12) \
 442   T (PSTL3STRM, pstl3strm, 13)
 443
 444 #define AARCH64_SVENUM(UPPER, LOWER, VALUE) AARCH64_SV_##UPPER = VALUE,
 445 enum aarch64_svpattern {
 446   AARCH64_FOR_SVPATTERN (AARCH64_SVENUM)
 447   AARCH64_NUM_SVPATTERNS
 448 };
 449
 450 enum aarch64_svprfop {
 451   AARCH64_FOR_SVPRFOP (AARCH64_SVENUM)
 452   AARCH64_NUM_SVPRFOPS
 453 };
 454 #undef AARCH64_SVENUM
 455
 456 /* It's convenient to divide the built-in function codes into groups,
 457    rather than having everything in a single enum.  This type enumerates
 458    those groups.  */
 459 enum aarch64_builtin_class
 460 {
 461   AARCH64_BUILTIN_GENERAL,
 462   AARCH64_BUILTIN_SVE
 463 };
 464
 465 /* Built-in function codes are structured so that the low
 466    AARCH64_BUILTIN_SHIFT bits contain the aarch64_builtin_class
 467    and the upper bits contain a group-specific subcode.  */
 468 const unsigned int AARCH64_BUILTIN_SHIFT = 1;
 469
 470 /* Mask that selects the aarch64_builtin_class part of a function code.  */
 471 const unsigned int AARCH64_BUILTIN_CLASS = (1 << AARCH64_BUILTIN_SHIFT) - 1;
 472
 473 void aarch64_post_cfi_startproc (void);
 474 poly_int64 aarch64_initial_elimination_offset (unsigned, unsigned);
 475 int aarch64_get_condition_code (rtx);
 476 bool aarch64_address_valid_for_prefetch_p (rtx, bool);
 477 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
 478 unsigned HOST_WIDE_INT aarch64_and_split_imm1 (HOST_WIDE_INT val_in);
 479 unsigned HOST_WIDE_INT aarch64_and_split_imm2 (HOST_WIDE_INT val_in);
 480 bool aarch64_and_bitmask_imm (unsigned HOST_WIDE_INT val_in, machine_mode mode);
 481 int aarch64_branch_cost (bool, bool);
 482 enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
 483 opt_machine_mode aarch64_vq_mode (scalar_mode);
 484 opt_machine_mode aarch64_full_sve_mode (scalar_mode);
 485 bool aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode);
 486 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
 487 bool aarch64_const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT,
 488                                             HOST_WIDE_INT);
 489 bool aarch64_constant_address_p (rtx);
 490 bool aarch64_emit_approx_div (rtx, rtx, rtx);
 491 bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
 492 void aarch64_expand_call (rtx, rtx, rtx, bool);
 493 bool aarch64_expand_cpymem (rtx *);
 494 bool aarch64_float_const_zero_rtx_p (rtx);
 495 bool aarch64_float_const_rtx_p (rtx);
 496 bool aarch64_function_arg_regno_p (unsigned);
 497 bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs);
 498 bool aarch64_gen_cpymemqi (rtx *);
 499 bool aarch64_is_extend_from_extract (scalar_int_mode, rtx, rtx);
 500 bool aarch64_is_long_call_p (rtx);
 501 bool aarch64_is_noplt_call_p (rtx);
 502 bool aarch64_label_mentioned_p (rtx);
 503 void aarch64_declare_function_name (FILE *, const char*, tree);
 504 void aarch64_asm_output_alias (FILE *, const tree, const tree);
 505 void aarch64_asm_output_external (FILE *, tree, const char*);
 506 bool aarch64_legitimate_pic_operand_p (rtx);
 507 bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx);
 508 bool aarch64_masks_and_shift_for_bfi_p (scalar_int_mode, unsigned HOST_WIDE_INT,
 509                                         unsigned HOST_WIDE_INT,
 510                                         unsigned HOST_WIDE_INT);
 511 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
 512 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
 513 machine_mode aarch64_sve_int_mode (machine_mode);
 514 opt_machine_mode aarch64_sve_pred_mode (unsigned int);
 515 machine_mode aarch64_sve_pred_mode (machine_mode);
 516 opt_machine_mode aarch64_sve_data_mode (scalar_mode, poly_uint64);
 517 bool aarch64_sve_mode_p (machine_mode);
 518 HOST_WIDE_INT aarch64_fold_sve_cnt_pat (aarch64_svpattern, unsigned int);
 519 bool aarch64_sve_cnt_immediate_p (rtx);
 520 bool aarch64_sve_scalar_inc_dec_immediate_p (rtx);
 521 bool aarch64_sve_addvl_addpl_immediate_p (rtx);
 522 bool aarch64_sve_vector_inc_dec_immediate_p (rtx);
 523 int aarch64_add_offset_temporaries (rtx);
 524 void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx);
 525 bool aarch64_mov_operand_p (rtx, machine_mode);
 526 rtx aarch64_reverse_mask (machine_mode, unsigned int);
 527 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, poly_int64);
 528 bool aarch64_offset_9bit_signed_unscaled_p (machine_mode, poly_int64);
 529 char *aarch64_output_sve_prefetch (const char *, rtx, const char *);
 530 char *aarch64_output_sve_cnt_immediate (const char *, const char *, rtx);
 531 char *aarch64_output_sve_cnt_pat_immediate (const char *, const char *, rtx *);
 532 char *aarch64_output_sve_scalar_inc_dec (rtx);
 533 char *aarch64_output_sve_addvl_addpl (rtx);
 534 char *aarch64_output_sve_vector_inc_dec (const char *, rtx);
 535 char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
 536 char *aarch64_output_simd_mov_immediate (rtx, unsigned,
 537                         enum simd_immediate_check w = AARCH64_CHECK_MOV);
 538 char *aarch64_output_sve_mov_immediate (rtx);
 539 char *aarch64_output_sve_ptrues (rtx);
 540 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);
 541 bool aarch64_regno_ok_for_base_p (int, bool);
 542 bool aarch64_regno_ok_for_index_p (int, bool);
 543 bool aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *fail);
 544 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode,
 545                                             bool high);
 546 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode);
 547 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
 548 bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);
 549 bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
 550                         enum simd_immediate_check w = AARCH64_CHECK_MOV);
 551 rtx aarch64_check_zero_based_sve_index_immediate (rtx);
 552 bool aarch64_sve_index_immediate_p (rtx);
 553 bool aarch64_sve_arith_immediate_p (rtx, bool);
 554 bool aarch64_sve_sqadd_sqsub_immediate_p (rtx, bool);
 555 bool aarch64_sve_bitmask_immediate_p (rtx);
 556 bool aarch64_sve_dup_immediate_p (rtx);
 557 bool aarch64_sve_cmp_immediate_p (rtx, bool);
 558 bool aarch64_sve_float_arith_immediate_p (rtx, bool);
 559 bool aarch64_sve_float_mul_immediate_p (rtx);
 560 bool aarch64_split_dimode_const_store (rtx, rtx);
 561 bool aarch64_symbolic_address_p (rtx);
 562 bool aarch64_uimm12_shift (HOST_WIDE_INT);
 563 bool aarch64_use_return_insn_p (void);
 564 const char *aarch64_output_casesi (rtx *);
 565
 566 unsigned int aarch64_tlsdesc_abi_id ();
 567 enum aarch64_symbol_type aarch64_classify_symbol (rtx, HOST_WIDE_INT);
 568 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
 569 enum reg_class aarch64_regno_regclass (unsigned);
 570 int aarch64_asm_preferred_eh_data_format (int, int);
 571 int aarch64_fpconst_pow_of_2 (rtx);
 572 int aarch64_fpconst_pow2_recip (rtx);
 573 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
 574                                                        machine_mode);
 575 int aarch64_uxt_size (int, HOST_WIDE_INT);
 576 int aarch64_vec_fpconst_pow_of_2 (rtx);
 577 rtx aarch64_eh_return_handler_rtx (void);
 578 rtx aarch64_mask_from_zextract_ops (rtx, rtx);
 579 const char *aarch64_output_move_struct (rtx *operands);
 580 rtx aarch64_return_addr (int, rtx);
 581 rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT);
 582 bool aarch64_simd_mem_operand_p (rtx);
 583 bool aarch64_sve_ld1r_operand_p (rtx);
 584 bool aarch64_sve_ld1rq_operand_p (rtx);
 585 bool aarch64_sve_ldff1_operand_p (rtx);
 586 bool aarch64_sve_ldnf1_operand_p (rtx);
 587 bool aarch64_sve_ldr_operand_p (rtx);
 588 bool aarch64_sve_prefetch_operand_p (rtx, machine_mode);
 589 bool aarch64_sve_struct_memory_operand_p (rtx);
 590 rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool);
 591 rtx aarch64_gen_stepped_int_parallel (unsigned int, int, int);
 592 bool aarch64_stepped_int_parallel_p (rtx, int);
 593 rtx aarch64_tls_get_addr (void);
 594 unsigned aarch64_dbx_register_number (unsigned);
 595 unsigned aarch64_trampoline_size (void);
 596 void aarch64_asm_output_labelref (FILE *, const char *);
 597 void aarch64_cpu_cpp_builtins (cpp_reader *);
 598 const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *);
 599 const char * aarch64_output_probe_stack_range (rtx, rtx);
 600 const char * aarch64_output_probe_sve_stack_clash (rtx, rtx, rtx, rtx);
 601 void aarch64_err_no_fpadvsimd (machine_mode);
 602 void aarch64_expand_epilogue (bool);
 603 rtx aarch64_ptrue_all (unsigned int);
 604 opt_machine_mode aarch64_ptrue_all_mode (rtx);
 605 rtx aarch64_convert_sve_data_to_pred (rtx, machine_mode, rtx);
 606 rtx aarch64_expand_sve_dupq (rtx, machine_mode, rtx);
 607 void aarch64_expand_mov_immediate (rtx, rtx);
 608 rtx aarch64_ptrue_reg (machine_mode);
 609 rtx aarch64_pfalse_reg (machine_mode);
 610 bool aarch64_sve_pred_dominates_p (rtx *, rtx);
 611 bool aarch64_sve_same_pred_for_ptest_p (rtx *, rtx *);
 612 void aarch64_emit_sve_pred_move (rtx, rtx, rtx);
 613 void aarch64_expand_sve_mem_move (rtx, rtx, machine_mode);
 614 bool aarch64_maybe_expand_sve_subreg_move (rtx, rtx);
 615 rtx aarch64_replace_reg_mode (rtx, machine_mode);
 616 void aarch64_split_sve_subreg_move (rtx, rtx, rtx);
 617 void aarch64_expand_prologue (void);
 618 void aarch64_expand_vector_init (rtx, rtx);
 619 void aarch64_sve_expand_vector_init (rtx, rtx);
 620 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx,
 621                                    const_tree, unsigned, bool = false);
 622 void aarch64_init_expanders (void);
 623 void aarch64_init_simd_builtins (void);
 624 void aarch64_emit_call_insn (rtx);
 625 void aarch64_register_pragmas (void);
 626 void aarch64_relayout_simd_types (void);
 627 void aarch64_reset_previous_fndecl (void);
 628 bool aarch64_return_address_signing_enabled (void);
 629 bool aarch64_bti_enabled (void);
 630 void aarch64_save_restore_target_globals (tree);
 631 void aarch64_addti_scratch_regs (rtx, rtx, rtx *,
 632                                  rtx *, rtx *,
 633                                  rtx *, rtx *,
 634                                  rtx *);
 635 void aarch64_subvti_scratch_regs (rtx, rtx, rtx *,
 636                                   rtx *, rtx *,
 637                                   rtx *, rtx *, rtx *);
 638 void aarch64_expand_subvti (rtx, rtx, rtx,
 639                             rtx, rtx, rtx, rtx, bool);
 640
 641
 642 /* Initialize builtins for SIMD intrinsics.  */
 643 void init_aarch64_simd_builtins (void);
 644
 645 void aarch64_simd_emit_reg_reg_move (rtx *, machine_mode, unsigned int);
 646
 647 /* Expand builtins for SIMD intrinsics.  */
 648 rtx aarch64_simd_expand_builtin (int, tree, rtx);
 649
 650 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
 651 rtx aarch64_endian_lane_rtx (machine_mode, unsigned int);
 652
 653 void aarch64_split_128bit_move (rtx, rtx);
 654
 655 bool aarch64_split_128bit_move_p (rtx, rtx);
 656
 657 bool aarch64_mov128_immediate (rtx);
 658
 659 void aarch64_split_simd_combine (rtx, rtx, rtx);
 660
 661 void aarch64_split_simd_move (rtx, rtx);
 662
 663 /* Check for a legitimate floating point constant for FMOV.  */
 664 bool aarch64_float_const_representable_p (rtx);
 665
 666 extern int aarch64_epilogue_uses (int);
 667
 668 #if defined (RTX_CODE)
 669 void aarch64_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
 670                                    rtx label_ref);
 671 bool aarch64_legitimate_address_p (machine_mode, rtx, bool,
 672                                    aarch64_addr_query_type = ADDR_QUERY_M);
 673 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx);
 674 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx);
 675 rtx aarch64_load_tp (rtx);
 676
 677 void aarch64_expand_compare_and_swap (rtx op[]);
 678 void aarch64_split_compare_and_swap (rtx op[]);
 679
 680 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 681
 682 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE);
 683
 684 void aarch64_expand_sve_vec_cmp_int (rtx, rtx_code, rtx, rtx);
 685 bool aarch64_expand_sve_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
 686 void aarch64_expand_sve_vcond (machine_mode, machine_mode, rtx *);
 687
 688 bool aarch64_prepare_sve_int_fma (rtx *, rtx_code);
 689 bool aarch64_prepare_sve_cond_int_fma (rtx *, rtx_code);
 690 #endif /* RTX_CODE */
 691
 692 bool aarch64_process_target_attr (tree);
 693 void aarch64_override_options_internal (struct gcc_options *);
 694
 695 const char *aarch64_general_mangle_builtin_type (const_tree);
 696 void aarch64_general_init_builtins (void);
 697 tree aarch64_general_fold_builtin (unsigned int, tree, unsigned int, tree *);
 698 gimple *aarch64_general_gimple_fold_builtin (unsigned int, gcall *);
 699 rtx aarch64_general_expand_builtin (unsigned int, tree, rtx, int);
 700 tree aarch64_general_builtin_decl (unsigned, bool);
 701 tree aarch64_general_builtin_rsqrt (unsigned int);
 702 tree aarch64_builtin_vectorized_function (unsigned int, tree, tree);
 703
 704 namespace aarch64_sve {
 705   void init_builtins ();
 706   void handle_arm_sve_h ();
 707   tree builtin_decl (unsigned, bool);
 708   bool builtin_type_p (const_tree);
 709   bool builtin_type_p (const_tree, unsigned int *, unsigned int *);
 710   const char *mangle_builtin_type (const_tree);
 711   tree resolve_overloaded_builtin (location_t, unsigned int,
 712                                    vec<tree, va_gc> *);
 713   bool check_builtin_call (location_t, vec<location_t>, unsigned int,
 714                            tree, unsigned int, tree *);
 715   gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *);
 716   rtx expand_builtin (unsigned int, tree, rtx);
 717 #ifdef GCC_TARGET_H
 718   bool verify_type_context (location_t, type_context_kind, const_tree, bool);
 719 #endif
 720 }
 721
 722 extern void aarch64_split_combinev16qi (rtx operands[3]);
 723 extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int);
 724 extern void aarch64_expand_sve_vec_perm (rtx, rtx, rtx, rtx);
 725 extern bool aarch64_madd_needs_nop (rtx_insn *);
 726 extern void aarch64_final_prescan_insn (rtx_insn *);
 727 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
 728 int aarch64_ccmp_mode_to_code (machine_mode mode);
 729
 730 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
 731 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);
 732 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode);
 733 void aarch64_swap_ldrstr_operands (rtx *, bool);
 734
 735 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
 736                                               tree, HOST_WIDE_INT);
 737
 738
 739 extern bool aarch64_classify_address (struct aarch64_address_info *, rtx,
 740                                       machine_mode, bool,
 741                                       aarch64_addr_query_type = ADDR_QUERY_M);
 742
 743 /* Defined in common/config/aarch64-common.c.  */
 744 bool aarch64_handle_option (struct gcc_options *, struct gcc_options *,
 745                              const struct cl_decoded_option *, location_t);
 746 const char *aarch64_rewrite_selected_cpu (const char *name);
 747 enum aarch64_parse_opt_result aarch64_parse_extension (const char *,
 748                                                        uint64_t *,
 749                                                        std::string *);
 750 void aarch64_get_all_extension_candidates (auto_vec<const char *> *candidates);
 751 std::string aarch64_get_extension_string_for_isa_flags (uint64_t, uint64_t);
 752
 753 /* Defined in aarch64-d.c  */
 754 extern void aarch64_d_target_versions (void);
 755
 756 rtl_opt_pass *make_pass_fma_steering (gcc::context *);
 757 rtl_opt_pass *make_pass_track_speculation (gcc::context *);
 758 rtl_opt_pass *make_pass_tag_collision_avoidance (gcc::context *);
 759 rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt);
 760
 761 poly_uint64 aarch64_regmode_natural_size (machine_mode);
 762
 763 bool aarch64_high_bits_all_ones_p (HOST_WIDE_INT);
 764
 765 struct atomic_ool_names
 766 {
 767     const char *str[5][4];
 768 };
 769
 770 rtx aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
 771                             const atomic_ool_names *names);
 772 extern const atomic_ool_names aarch64_ool_swp_names;
 773 extern const atomic_ool_names aarch64_ool_ldadd_names;
 774 extern const atomic_ool_names aarch64_ool_ldset_names;
 775 extern const atomic_ool_names aarch64_ool_ldclr_names;
 776 extern const atomic_ool_names aarch64_ool_ldeor_names;
 777
 778 tree aarch64_resolve_overloaded_builtin_general (location_t, tree, void *);
 779
 780 #endif /* GCC_AARCH64_PROTOS_H */