1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
46 #include "target-def.h"
50 /* Usable when we have an amount to add or subtract, and want the
51 optimal size of the insn. */
52 #define ADDITIVE_SIZE_MODIFIER(size) \
53 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
55 #define ASSERT_PLT_UNSPEC(x) \
56 CRIS_ASSERT (XINT (x, 1) == CRIS_UNSPEC_PLT \
57 && ((GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF) \
58 || GET_CODE (XVECEXP (x, 0, 0)) == LABEL_REF))
60 #define LOSE_AND_RETURN(msgid, x) \
63 cris_operand_lossage (msgid, x); \
67 enum cris_retinsn_type
68 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
70 /* Per-function machine data. */
71 struct machine_function
GTY(())
73 int needs_return_address_on_stack
;
75 /* This is the number of registers we save in the prologue due to
79 enum cris_retinsn_type return_type
;
82 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
84 static char cris_output_insn_is_bound
= 0;
86 /* In code for output macros, this is how we know whether e.g. constant
87 goes in code or in a static initializer. */
88 static int in_code
= 0;
90 /* Fix for reg_overlap_mentioned_p. */
91 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
93 static void cris_print_base (rtx
, FILE *);
95 static void cris_print_index (rtx
, FILE *);
97 static void cris_output_addr_const (FILE *, rtx
);
99 static struct machine_function
* cris_init_machine_status (void);
101 static rtx
cris_struct_value_rtx (tree
, int);
103 static void cris_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
104 tree type
, int *, int);
106 static int cris_initial_frame_pointer_offset (void);
108 static int saved_regs_mentioned (rtx
);
110 static void cris_operand_lossage (const char *, rtx
);
112 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
114 static void cris_asm_output_mi_thunk
115 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
117 static void cris_file_start (void);
118 static void cris_init_libfuncs (void);
120 static bool cris_rtx_costs (rtx
, int, int, int *);
121 static int cris_address_cost (rtx
);
122 static bool cris_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
124 static int cris_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
126 static tree
cris_md_asm_clobbers (tree
, tree
, tree
);
128 static bool cris_handle_option (size_t, const char *, int);
130 /* This is the parsed result of the "-max-stack-stackframe=" option. If
131 it (still) is zero, then there was no such option given. */
132 int cris_max_stackframe
= 0;
134 /* This is the parsed result of the "-march=" option, if given. */
135 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
137 #undef TARGET_ASM_ALIGNED_HI_OP
138 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
139 #undef TARGET_ASM_ALIGNED_SI_OP
140 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
141 #undef TARGET_ASM_ALIGNED_DI_OP
142 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
144 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
145 available in ELF. These "normal" pseudos do not have any alignment
146 constraints or side-effects. */
147 #undef TARGET_ASM_UNALIGNED_HI_OP
148 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
150 #undef TARGET_ASM_UNALIGNED_SI_OP
151 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
153 #undef TARGET_ASM_UNALIGNED_DI_OP
154 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
156 #undef TARGET_ASM_OUTPUT_MI_THUNK
157 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
158 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
159 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
161 #undef TARGET_ASM_FILE_START
162 #define TARGET_ASM_FILE_START cris_file_start
164 #undef TARGET_INIT_LIBFUNCS
165 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
167 #undef TARGET_RTX_COSTS
168 #define TARGET_RTX_COSTS cris_rtx_costs
169 #undef TARGET_ADDRESS_COST
170 #define TARGET_ADDRESS_COST cris_address_cost
172 #undef TARGET_PROMOTE_FUNCTION_ARGS
173 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
174 #undef TARGET_STRUCT_VALUE_RTX
175 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
176 #undef TARGET_SETUP_INCOMING_VARARGS
177 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
178 #undef TARGET_PASS_BY_REFERENCE
179 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
180 #undef TARGET_ARG_PARTIAL_BYTES
181 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
182 #undef TARGET_MD_ASM_CLOBBERS
183 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
184 #undef TARGET_DEFAULT_TARGET_FLAGS
185 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
186 #undef TARGET_HANDLE_OPTION
187 #define TARGET_HANDLE_OPTION cris_handle_option
189 struct gcc_target targetm
= TARGET_INITIALIZER
;
191 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
194 cris_movem_load_rest_p (rtx op
, int offs
)
196 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
202 unsigned int regno
= 0;
204 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
205 other than (MEM reg). */
207 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
208 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
209 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
212 /* Check a possible post-inc indicator. */
213 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
215 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
216 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
222 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
223 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
224 || !CONST_INT_P (inc
)
225 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
232 /* FIXME: These two only for pre-v32. */
234 regno
= reg_count
- 1;
236 elt
= XVECEXP (op
, 0, offs
);
237 src_addr
= XEXP (SET_SRC (elt
), 0);
239 if (GET_CODE (elt
) != SET
240 || !REG_P (SET_DEST (elt
))
241 || GET_MODE (SET_DEST (elt
)) != SImode
242 || REGNO (SET_DEST (elt
)) != regno
243 || !MEM_P (SET_SRC (elt
))
244 || GET_MODE (SET_SRC (elt
)) != SImode
245 || !memory_address_p (SImode
, src_addr
))
248 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
250 rtx elt
= XVECEXP (op
, 0, i
);
253 if (GET_CODE (elt
) != SET
254 || !REG_P (SET_DEST (elt
))
255 || GET_MODE (SET_DEST (elt
)) != SImode
256 || REGNO (SET_DEST (elt
)) != regno
257 || !MEM_P (SET_SRC (elt
))
258 || GET_MODE (SET_SRC (elt
)) != SImode
259 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
260 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
261 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
262 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
269 /* Worker function for predicate for the parallel contents in a movem
273 cris_store_multiple_op_p (rtx op
)
275 int reg_count
= XVECLEN (op
, 0);
286 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
287 other than (MEM reg) and (MEM (PLUS reg const)). */
291 elt
= XVECEXP (op
, 0, 0);
293 if (GET_CODE (elt
) != SET
)
296 dest
= SET_DEST (elt
);
298 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
301 dest_addr
= XEXP (dest
, 0);
303 /* Check a possible post-inc indicator. */
304 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
306 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
307 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
313 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
314 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
315 || !CONST_INT_P (inc
)
316 /* Support increment by number of registers, and by the offset
317 of the destination, if it has the form (MEM (PLUS reg
319 || !((REG_P (dest_addr
)
320 && REGNO (dest_addr
) == REGNO (reg
)
321 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
322 || (GET_CODE (dest_addr
) == PLUS
323 && REG_P (XEXP (dest_addr
, 0))
324 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
325 && CONST_INT_P (XEXP (dest_addr
, 1))
326 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
334 /* FIXME: These two only for pre-v32. */
336 regno
= reg_count
- 1;
338 if (GET_CODE (elt
) != SET
339 || !REG_P (SET_SRC (elt
))
340 || GET_MODE (SET_SRC (elt
)) != SImode
341 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
342 || !MEM_P (SET_DEST (elt
))
343 || GET_MODE (SET_DEST (elt
)) != SImode
)
346 if (REG_P (dest_addr
))
348 dest_base
= dest_addr
;
351 else if (GET_CODE (dest_addr
) == PLUS
352 && REG_P (XEXP (dest_addr
, 0))
353 && CONST_INT_P (XEXP (dest_addr
, 1)))
355 dest_base
= XEXP (dest_addr
, 0);
356 offset
= INTVAL (XEXP (dest_addr
, 1));
361 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
363 rtx elt
= XVECEXP (op
, 0, i
);
366 if (GET_CODE (elt
) != SET
367 || !REG_P (SET_SRC (elt
))
368 || GET_MODE (SET_SRC (elt
)) != SImode
369 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
370 || !MEM_P (SET_DEST (elt
))
371 || GET_MODE (SET_DEST (elt
)) != SImode
372 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
373 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
374 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
375 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
382 /* The CONDITIONAL_REGISTER_USAGE worker. */
385 cris_conditional_register_usage (void)
387 /* FIXME: This isn't nice. We should be able to use that register for
388 something else if the PIC table isn't needed. */
390 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
391 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
393 if (TARGET_HAS_MUL_INSNS
)
394 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
396 /* On early versions, we must use the 16-bit condition-code register,
397 which has another name. */
398 if (cris_cpu_version
< 8)
399 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
402 /* Return current_function_uses_pic_offset_table. For use in cris.md,
403 since some generated files do not include function.h. */
406 cris_cfun_uses_pic_table (void)
408 return current_function_uses_pic_offset_table
;
411 /* Given an rtx, return the text string corresponding to the CODE of X.
412 Intended for use in the assembly language output section of a
418 cris_output_insn_is_bound
= 0;
419 switch (GET_CODE (x
))
430 /* This function is for retrieving a part of an instruction name for
431 an operator, for immediate output. If that ever happens for
432 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
434 internal_error ("MULT case in cris_op_str");
470 /* Used to control the sign/zero-extend character for the 'E' modifier.
472 cris_output_insn_is_bound
= 1;
477 return "Unknown operator";
482 /* Emit an error message when we're in an asm, and a fatal error for
483 "normal" insns. Formatted output isn't easily implemented, since we
484 use output_operand_lossage to output the actual message and handle the
485 categorization of the error. */
488 cris_operand_lossage (const char *msgid
, rtx op
)
491 output_operand_lossage ("%s", msgid
);
494 /* Print an index part of an address to file. */
497 cris_print_index (rtx index
, FILE *file
)
499 rtx inner
= XEXP (index
, 0);
501 /* Make the index "additive" unless we'll output a negative number, in
502 which case the sign character is free (as in free beer). */
503 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
507 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
508 else if (CONSTANT_P (index
))
509 cris_output_addr_const (file
, index
);
510 else if (GET_CODE (index
) == MULT
)
512 fprintf (file
, "$%s.",
513 reg_names
[REGNO (XEXP (index
, 0))]);
515 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
517 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (inner
))
519 rtx inner_inner
= XEXP (inner
, 0);
521 if (GET_CODE (inner_inner
) == POST_INC
)
523 fprintf (file
, "[$%s+].",
524 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
525 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
529 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
531 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
534 else if (MEM_P (index
))
536 if (GET_CODE (inner
) == POST_INC
)
537 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
539 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
542 cris_operand_lossage ("unexpected index-type in cris_print_index",
546 /* Print a base rtx of an address to file. */
549 cris_print_base (rtx base
, FILE *file
)
552 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
553 else if (GET_CODE (base
) == POST_INC
)
554 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
556 cris_operand_lossage ("unexpected base-type in cris_print_base",
560 /* Usable as a guard in expressions. */
563 cris_fatal (char *arg
)
565 internal_error (arg
);
567 /* We'll never get here; this is just to appease compilers. */
571 /* Return nonzero if REGNO is an ordinary register that *needs* to be
572 saved together with other registers, possibly by a MOVEM instruction,
573 or is saved for target-independent reasons. There may be
574 target-dependent reasons to save the register anyway; this is just a
575 wrapper for a complicated conditional. */
578 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
581 (((regs_ever_live
[regno
]
582 && !call_used_regs
[regno
])
583 || (regno
== PIC_OFFSET_TABLE_REGNUM
585 /* It is saved anyway, if there would be a gap. */
587 && regs_ever_live
[regno
+ 1]
588 && !call_used_regs
[regno
+ 1]))))
589 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
590 && regno
!= CRIS_SRP_REGNUM
)
591 || (current_function_calls_eh_return
592 && (regno
== EH_RETURN_DATA_REGNO (0)
593 || regno
== EH_RETURN_DATA_REGNO (1)
594 || regno
== EH_RETURN_DATA_REGNO (2)
595 || regno
== EH_RETURN_DATA_REGNO (3)));
598 /* Return nonzero if there are regs mentioned in the insn that are not all
599 in the call_used regs. This is part of the decision whether an insn
600 can be put in the epilogue. */
603 saved_regs_mentioned (rtx x
)
609 /* Mainly stolen from refers_to_regno_p in rtlanal.c. */
617 return !call_used_regs
[i
];
620 /* If this is a SUBREG of a hard reg, we can see exactly which
621 registers are being modified. Otherwise, handle normally. */
622 i
= REGNO (SUBREG_REG (x
));
623 return !call_used_regs
[i
];
629 fmt
= GET_RTX_FORMAT (code
);
630 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
634 if (saved_regs_mentioned (XEXP (x
, i
)))
637 else if (fmt
[i
] == 'E')
640 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
641 if (saved_regs_mentioned (XEXP (x
, i
)))
649 /* The PRINT_OPERAND worker. */
652 cris_print_operand (FILE *file
, rtx x
, int code
)
656 /* Size-strings corresponding to MULT expressions. */
657 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
659 /* New code entries should just be added to the switch below. If
660 handling is finished, just return. If handling was just a
661 modification of the operand, the modified operand should be put in
662 "operand", and then do a break to let default handling
663 (zero-modifier) output the operand. */
668 /* Print the unsigned supplied integer as if it were signed
669 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
671 || ! CONST_OK_FOR_LETTER_P (INTVAL (x
), 'O'))
672 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
673 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
674 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
678 /* Print assembler code for operator. */
679 fprintf (file
, "%s", cris_op_str (operand
));
684 /* A movem modifier working on a parallel; output the register
688 if (GET_CODE (x
) != PARALLEL
)
689 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
691 /* The second item can be (set reg (plus reg const)) to denote a
694 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
696 : XVECLEN (x
, 0) - 1);
698 fprintf (file
, "$%s", reg_names
[regno
]);
704 /* A similar movem modifier; output the memory operand. */
707 if (GET_CODE (x
) != PARALLEL
)
708 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
710 /* The lowest mem operand is in the first item, but perhaps it
711 needs to be output as postincremented. */
712 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
713 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
714 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
716 /* The second item can be a (set reg (plus reg const)) to denote
718 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
720 /* It's a post-increment, if the address is a naked (reg). */
722 addr
= gen_rtx_POST_INC (SImode
, addr
);
725 /* Otherwise, it's a side-effect; RN=RN+M. */
726 fprintf (file
, "[$%s=$%s%s%d]",
727 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
728 reg_names
[REGNO (XEXP (addr
, 0))],
729 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
730 (int) INTVAL (XEXP (addr
, 1)));
734 output_address (addr
);
739 /* Adjust a power of two to its log2. */
740 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
741 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
742 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
746 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
747 respectively. This modifier also terminates the inhibiting
748 effects of the 'x' modifier. */
749 cris_output_insn_is_bound
= 0;
750 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
754 if (INTVAL (x
) <= 255)
756 else if (INTVAL (x
) <= 65535)
766 /* For a non-integer, print the size of the operand. */
767 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
768 ? 'd' : GET_MODE (x
) == HImode
? 'w'
769 : GET_MODE (x
) == QImode
? 'b'
770 /* If none of the above, emit an erroneous size letter. */
776 /* Const_int: print b for -127 <= x <= 255,
777 w for -32768 <= x <= 65535, else die. */
779 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
780 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
781 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
785 /* Output a 'nop' if there's nothing for the delay slot.
786 This method stolen from the sparc files. */
787 if (dbr_sequence_length () == 0)
788 fputs ("\n\tnop", file
);
792 /* Output directive for alignment padded with "nop" insns.
793 Optimizing for size, it's plain 4-byte alignment, otherwise we
794 align the section to a cache-line (32 bytes) and skip at max 2
795 bytes, i.e. we skip if it's the last insn on a cache-line. The
796 latter is faster by a small amount (for two test-programs 99.6%
797 and 99.9%) and larger by a small amount (ditto 100.1% and
798 100.2%). This is supposed to be the simplest yet performance-
799 wise least intrusive way to make sure the immediately following
800 (supposed) muls/mulu insn isn't located at the end of a
804 ? ".p2alignw 2,0x050f\n\t"
805 : ".p2alignw 5,0x050f,2\n\t", file
);
809 /* The PIC register. */
811 internal_error ("invalid use of ':' modifier");
812 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
816 /* Print high (most significant) part of something. */
817 switch (GET_CODE (operand
))
820 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
821 value is kept here, and so may be other than 0 or -1. */
822 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
823 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
827 /* High part of a long long constant. */
828 if (GET_MODE (operand
) == VOIDmode
)
830 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
834 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
837 /* Print reg + 1. Check that there's not an attempt to print
838 high-parts of registers like stack-pointer or higher. */
839 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2)
840 LOSE_AND_RETURN ("bad register", operand
);
841 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
845 /* Adjust memory address to high part. */
847 rtx adj_mem
= operand
;
849 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
851 /* Adjust so we can use two SImode in DImode.
852 Calling adj_offsettable_operand will make sure it is an
853 offsettable address. Don't do this for a postincrement
854 though; it should remain as it was. */
855 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
857 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
859 output_address (XEXP (adj_mem
, 0));
864 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
868 /* Strip the MEM expression. */
869 operand
= XEXP (operand
, 0);
873 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
874 iterators ("code macros") and attributes in cris.md to avoid
875 the need for %x and %E (and %e) and state passed between
877 cris_output_insn_is_bound
= 0;
880 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
881 cris_output_insn_is_bound is nonzero. */
882 if (GET_CODE (operand
) != SIGN_EXTEND
883 && GET_CODE (operand
) != ZERO_EXTEND
884 && !CONST_INT_P (operand
))
885 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
887 if (cris_output_insn_is_bound
)
889 cris_output_insn_is_bound
= 0;
893 putc (GET_CODE (operand
) == SIGN_EXTEND
894 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
899 /* Print the size letter of the inner element. We can do it by
900 calling ourselves with the 's' modifier. */
901 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
902 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
903 cris_print_operand (file
, XEXP (operand
, 0), 's');
907 /* Print the least significant part of operand. */
908 if (GET_CODE (operand
) == CONST_DOUBLE
)
910 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
913 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
915 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
916 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
919 /* Otherwise the least significant part equals the normal part,
920 so handle it normally. */
924 /* When emitting an add for the high part of a DImode constant, we
925 want to use addq for 0 and adds.w for -1. */
926 if (!CONST_INT_P (operand
))
927 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
928 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
932 /* If this is a GOT symbol, force it to be emitted as :GOT and
933 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
934 Avoid making this too much of a special case. */
935 if (flag_pic
== 1 && CONSTANT_P (operand
))
937 int flag_pic_save
= flag_pic
;
940 cris_output_addr_const (file
, operand
);
941 flag_pic
= flag_pic_save
;
947 /* When emitting an sub for the high part of a DImode constant, we
948 want to use subq for 0 and subs.w for -1. */
949 if (!CONST_INT_P (operand
))
950 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
951 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
955 /* Print the operand as the index-part of an address.
956 Easiest way out is to use cris_print_index. */
957 cris_print_index (operand
, file
);
961 /* Print the size letter for an operand to a MULT, which must be a
962 const_int with a suitable value. */
963 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
964 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
965 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
969 /* No code, print as usual. */
973 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
976 /* Print an operand as without a modifier letter. */
977 switch (GET_CODE (operand
))
980 if (REGNO (operand
) > 15
981 && REGNO (operand
) != CRIS_MOF_REGNUM
982 && REGNO (operand
) != CRIS_SRP_REGNUM
983 && REGNO (operand
) != CRIS_CC0_REGNUM
)
984 internal_error ("internal error: bad register: %d", REGNO (operand
));
985 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
989 output_address (XEXP (operand
, 0));
993 if (GET_MODE (operand
) == VOIDmode
)
994 /* A long long constant. */
995 output_addr_const (file
, operand
);
998 /* Only single precision is allowed as plain operands the
999 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1004 /* FIXME: Perhaps check overflow of the "single". */
1005 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1006 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1008 fprintf (file
, "0x%lx", l
);
1015 cris_output_addr_const (file
, operand
);
1021 /* For a (MULT (reg X) const_int) we output "rX.S". */
1022 int i
= CONST_INT_P (XEXP (operand
, 1))
1023 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1024 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1025 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1028 || (!CONST_INT_P (XEXP (operand
, 0))
1029 && !CONST_INT_P (XEXP (operand
, 1))))
1030 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1032 cris_print_base (reg
, file
);
1033 fprintf (file
, ".%c",
1034 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1036 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1042 /* No need to handle all strange variants, let output_addr_const
1044 if (CONSTANT_P (operand
))
1046 cris_output_addr_const (file
, operand
);
1050 LOSE_AND_RETURN ("unexpected operand", x
);
1054 /* The PRINT_OPERAND_ADDRESS worker. */
1057 cris_print_operand_address (FILE *file
, rtx x
)
1059 /* All these were inside MEM:s so output indirection characters. */
1062 if (CONSTANT_ADDRESS_P (x
))
1063 cris_output_addr_const (file
, x
);
1064 else if (BASE_OR_AUTOINCR_P (x
))
1065 cris_print_base (x
, file
);
1066 else if (GET_CODE (x
) == PLUS
)
1074 cris_print_base (x1
, file
);
1075 cris_print_index (x2
, file
);
1077 else if (BASE_P (x2
))
1079 cris_print_base (x2
, file
);
1080 cris_print_index (x1
, file
);
1083 LOSE_AND_RETURN ("unrecognized address", x
);
1087 /* A DIP. Output more indirection characters. */
1089 cris_print_base (XEXP (x
, 0), file
);
1093 LOSE_AND_RETURN ("unrecognized address", x
);
1098 /* The RETURN_ADDR_RTX worker.
1099 We mark that the return address is used, either by EH or
1100 __builtin_return_address, for use by the function prologue and
1101 epilogue. FIXME: This isn't optimal; we just use the mark in the
1102 prologue and epilogue to say that the return address is to be stored
1103 in the stack frame. We could return SRP for leaf-functions and use the
1104 initial-value machinery. */
1107 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1109 cfun
->machine
->needs_return_address_on_stack
= 1;
1111 /* The return-address is stored just above the saved frame-pointer (if
1112 present). Apparently we can't eliminate from the frame-pointer in
1113 that direction, so use the incoming args (maybe pretended) pointer. */
1115 ? gen_rtx_MEM (Pmode
, plus_constant (virtual_incoming_args_rtx
, -4))
1119 /* Accessor used in cris.md:return because cfun->machine isn't available
1123 cris_return_address_on_stack (void)
1125 return regs_ever_live
[CRIS_SRP_REGNUM
]
1126 || cfun
->machine
->needs_return_address_on_stack
;
1129 /* Accessor used in cris.md:return because cfun->machine isn't available
1133 cris_return_address_on_stack_for_return (void)
1135 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1136 : cris_return_address_on_stack ();
1139 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1140 handles FP -> SP elimination offset. */
1143 cris_initial_frame_pointer_offset (void)
1147 /* Initial offset is 0 if we don't have a frame pointer. */
1149 bool got_really_used
= false;
1151 if (current_function_uses_pic_offset_table
)
1153 push_topmost_sequence ();
1155 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1157 pop_topmost_sequence ();
1160 /* And 4 for each register pushed. */
1161 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1162 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1165 /* And then, last, we add the locals allocated. */
1166 offs
+= get_frame_size ();
1168 /* And more; the accumulated args size. */
1169 offs
+= current_function_outgoing_args_size
;
1171 /* Then round it off, in case we use aligned stack. */
1172 if (TARGET_STACK_ALIGN
)
1173 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1178 /* The INITIAL_ELIMINATION_OFFSET worker.
1179 Calculate the difference between imaginary registers such as frame
1180 pointer and the stack pointer. Used to eliminate the frame pointer
1181 and imaginary arg pointer. */
1184 cris_initial_elimination_offset (int fromreg
, int toreg
)
1187 = cris_initial_frame_pointer_offset ();
1189 /* We should be able to use regs_ever_live and related prologue
1190 information here, or alpha should not as well. */
1191 bool return_address_on_stack
= cris_return_address_on_stack ();
1193 /* Here we act as if the frame-pointer were needed. */
1194 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1196 if (fromreg
== ARG_POINTER_REGNUM
1197 && toreg
== FRAME_POINTER_REGNUM
)
1198 return ap_fp_offset
;
1200 /* Between the frame pointer and the stack are only "normal" stack
1201 variables and saved registers. */
1202 if (fromreg
== FRAME_POINTER_REGNUM
1203 && toreg
== STACK_POINTER_REGNUM
)
1204 return fp_sp_offset
;
1206 /* We need to balance out the frame pointer here. */
1207 if (fromreg
== ARG_POINTER_REGNUM
1208 && toreg
== STACK_POINTER_REGNUM
)
1209 return ap_fp_offset
+ fp_sp_offset
- 4;
1214 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1217 cris_reload_address_legitimized (rtx x
,
1218 enum machine_mode mode ATTRIBUTE_UNUSED
,
1219 int opnum ATTRIBUTE_UNUSED
,
1221 int ind_levels ATTRIBUTE_UNUSED
)
1223 enum reload_type type
= itype
;
1228 if (GET_CODE (x
) != PLUS
)
1232 op0p
= &XEXP (x
, 0);
1234 op1p
= &XEXP (x
, 1);
1239 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1241 rtx op00
= XEXP (op0
, 0);
1242 rtx op000
= XEXP (op00
, 0);
1243 rtx
*op000p
= &XEXP (op00
, 0);
1245 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1247 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1249 bool something_reloaded
= false;
1251 if (GET_CODE (op000
) == POST_INC
1252 && REG_P (XEXP (op000
, 0))
1253 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1254 /* No, this gets too complicated and is too rare to care
1255 about trying to improve on the general code Here.
1256 As the return-value is an all-or-nothing indicator, we
1257 punt on the other register too. */
1261 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1263 /* The address of the inner mem is a pseudo or wrong
1264 reg: reload that. */
1265 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1266 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1267 something_reloaded
= true;
1270 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1272 /* Base register is a pseudo or wrong reg: reload it. */
1273 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1274 GET_MODE (x
), VOIDmode
, 0, 0,
1276 something_reloaded
= true;
1279 gcc_assert (something_reloaded
);
1288 /* This function looks into the pattern to see how this insn affects
1291 Used when to eliminate test insns before a condition-code user,
1292 such as a "scc" insn or a conditional branch. This includes
1293 checking if the entities that cc was updated by, are changed by the
1296 Currently a jumble of the old peek-inside-the-insn and the newer
1297 check-cc-attribute methods. */
1300 cris_notice_update_cc (rtx exp
, rtx insn
)
1302 /* Check if user specified "-mcc-init" as a bug-workaround. FIXME:
1303 TARGET_CCINIT does not work; we must set CC_REVERSED as below.
1304 Several testcases will otherwise fail, for example
1305 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1312 /* Slowly, we're converting to using attributes to control the setting
1313 of condition-code status. */
1314 switch (get_attr_cc (insn
))
1317 /* Even if it is "none", a setting may clobber a previous
1318 cc-value, so check. */
1319 if (GET_CODE (exp
) == SET
)
1321 if (cc_status
.value1
1322 && modified_in_p (cc_status
.value1
, insn
))
1323 cc_status
.value1
= 0;
1325 if (cc_status
.value2
1326 && modified_in_p (cc_status
.value2
, insn
))
1327 cc_status
.value2
= 0;
1336 /* Which means, for:
1341 CC is (reg) and (...) - unless (...) is 0, then CC does not change.
1342 CC_NO_OVERFLOW unless (...) is reg or mem.
1351 (set (reg1) (mem (bdap/biap)))
1352 (set (reg2) (bdap/biap))):
1353 CC is (reg1) and (mem (reg2))
1356 (set (mem (bdap/biap)) (reg1)) [or 0]
1357 (set (reg2) (bdap/biap))):
1360 (where reg and mem includes strict_low_parts variants thereof)
1362 For all others, assume CC is clobbered.
1363 Note that we do not have to care about setting CC_NO_OVERFLOW,
1364 since the overflow flag is set to 0 (i.e. right) for
1365 instructions where it does not have any sane sense, but where
1366 other flags have meanings. (This includes shifts; the carry is
1369 Note that there are other parallel constructs we could match,
1370 but we don't do that yet. */
1372 if (GET_CODE (exp
) == SET
)
1374 /* FIXME: Check when this happens. It looks like we should
1375 actually do a CC_STATUS_INIT here to be safe. */
1376 if (SET_DEST (exp
) == pc_rtx
)
1379 /* Record CC0 changes, so we do not have to output multiple
1381 if (SET_DEST (exp
) == cc0_rtx
)
1383 cc_status
.value1
= SET_SRC (exp
);
1384 cc_status
.value2
= 0;
1386 /* Handle flags for the special btstq on one bit. */
1387 if (GET_CODE (SET_SRC (exp
)) == ZERO_EXTRACT
1388 && XEXP (SET_SRC (exp
), 1) == const1_rtx
)
1390 if (CONST_INT_P (XEXP (SET_SRC (exp
), 0)))
1392 cc_status
.flags
= CC_INVERTED
;
1394 /* A one-bit btstq. */
1395 cc_status
.flags
= CC_Z_IN_NOT_N
;
1398 cc_status
.flags
= 0;
1400 if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1402 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1403 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1404 /* For some reason gcc will not canonicalize compare
1405 operations, reversing the sign by itself if
1406 operands are in wrong order. */
1407 /* (But NOT inverted; eq is still eq.) */
1408 cc_status
.flags
= CC_REVERSED
;
1410 /* This seems to be overlooked by gcc. FIXME: Check again.
1411 FIXME: Is it really safe? */
1413 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1414 XEXP (SET_SRC (exp
), 0),
1415 XEXP (SET_SRC (exp
), 1));
1419 else if (REG_P (SET_DEST (exp
))
1420 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1421 && REG_P (XEXP (SET_DEST (exp
), 0))))
1423 /* A register is set; normally CC is set to show that no
1424 test insn is needed. Catch the exceptions. */
1426 /* If not to cc0, then no "set"s in non-natural mode give
1428 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1429 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1431 /* ... except add:s and sub:s in DImode. */
1432 if (GET_MODE (SET_DEST (exp
)) == DImode
1433 && (GET_CODE (SET_SRC (exp
)) == PLUS
1434 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1436 cc_status
.flags
= 0;
1437 cc_status
.value1
= SET_DEST (exp
);
1438 cc_status
.value2
= SET_SRC (exp
);
1440 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1442 cc_status
.value2
= 0;
1444 /* Add and sub may set V, which gets us
1445 unoptimizable results in "gt" and "le" condition
1447 cc_status
.flags
|= CC_NO_OVERFLOW
;
1452 else if (SET_SRC (exp
) == const0_rtx
)
1454 /* There's no CC0 change when clearing a register or
1455 memory. Just check for overlap. */
1456 if (cc_status
.value1
1457 && modified_in_p (cc_status
.value1
, insn
))
1458 cc_status
.value1
= 0;
1460 if (cc_status
.value2
1461 && modified_in_p (cc_status
.value2
, insn
))
1462 cc_status
.value2
= 0;
1468 cc_status
.flags
= 0;
1469 cc_status
.value1
= SET_DEST (exp
);
1470 cc_status
.value2
= SET_SRC (exp
);
1472 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1474 cc_status
.value2
= 0;
1476 /* Some operations may set V, which gets us
1477 unoptimizable results in "gt" and "le" condition
1479 if (GET_CODE (SET_SRC (exp
)) == PLUS
1480 || GET_CODE (SET_SRC (exp
)) == MINUS
1481 || GET_CODE (SET_SRC (exp
)) == NEG
)
1482 cc_status
.flags
|= CC_NO_OVERFLOW
;
1487 else if (MEM_P (SET_DEST (exp
))
1488 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1489 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1491 /* When SET to MEM, then CC is not changed (except for
1493 if (cc_status
.value1
1494 && modified_in_p (cc_status
.value1
, insn
))
1495 cc_status
.value1
= 0;
1497 if (cc_status
.value2
1498 && modified_in_p (cc_status
.value2
, insn
))
1499 cc_status
.value2
= 0;
1504 else if (GET_CODE (exp
) == PARALLEL
)
1506 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1507 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1508 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1510 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1511 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1513 /* For "move.S [rx=ry+o],rz", say CC reflects
1514 value1=rz and value2=[rx] */
1515 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1517 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1518 XEXP (XVECEXP (exp
, 0, 1), 0));
1519 cc_status
.flags
= 0;
1521 /* Huh? A side-effect cannot change the destination
1523 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1525 internal_error ("internal error: sideeffect-insn affecting main effect");
1528 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1529 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1530 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1532 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1533 say flags are not changed, except for overlap. */
1534 if (cc_status
.value1
1535 && modified_in_p (cc_status
.value1
, insn
))
1536 cc_status
.value1
= 0;
1538 if (cc_status
.value2
1539 && modified_in_p (cc_status
.value2
, insn
))
1540 cc_status
.value2
= 0;
1549 internal_error ("unknown cc_attr value");
1555 /* Return != 0 if the return sequence for the current function is short,
1556 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1557 registers must be saved, so return 0 then. */
1560 cris_simple_epilogue (void)
1563 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1564 bool got_really_used
= false;
1566 if (! reload_completed
1567 || frame_pointer_needed
1568 || get_frame_size () != 0
1569 || current_function_pretend_args_size
1570 || current_function_args_size
1571 || current_function_outgoing_args_size
1572 || current_function_calls_eh_return
1574 /* If we're not supposed to emit prologue and epilogue, we must
1575 not emit return-type instructions. */
1576 || !TARGET_PROLOGUE_EPILOGUE
)
1579 if (current_function_uses_pic_offset_table
)
1581 push_topmost_sequence ();
1583 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
1584 pop_topmost_sequence ();
1587 /* No simple epilogue if there are saved registers. */
1588 for (regno
= 0; regno
< reglimit
; regno
++)
1589 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1595 /* Expand a return insn (just one insn) marked as using SRP or stack
1596 slot depending on parameter ON_STACK. */
1599 cris_expand_return (bool on_stack
)
1601 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1602 tell "ret" from "jump [sp+]". Some, but not all, other parts of
1603 GCC expect just (return) to do the right thing when optimizing, so
1604 we do that until they're fixed. Currently, all return insns in a
1605 function must be the same (not really a limiting factor) so we need
1606 to check that it doesn't change half-way through. */
1607 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
1609 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
1610 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
1612 cfun
->machine
->return_type
1613 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
1616 /* Compute a (partial) cost for rtx X. Return true if the complete
1617 cost has been computed, and false if subexpressions should be
1618 scanned. In either case, *TOTAL contains the cost result. */
1621 cris_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1627 HOST_WIDE_INT val
= INTVAL (x
);
1630 else if (val
< 32 && val
>= -32)
1632 /* Eight or 16 bits are a word and cycle more expensive. */
1633 else if (val
<= 32767 && val
>= -32768)
1635 /* A 32 bit constant (or very seldom, unsigned 16 bits) costs
1636 another word. FIXME: This isn't linear to 16 bits. */
1652 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
1655 /* Make 0.0 cheap, else test-insns will not be used. */
1660 /* Identify values that are no powers of two. Powers of 2 are
1661 taken care of already and those values should not be changed. */
1662 if (!CONST_INT_P (XEXP (x
, 1))
1663 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1665 /* If we have a multiply insn, then the cost is between
1666 1 and 2 "fast" instructions. */
1667 if (TARGET_HAS_MUL_INSNS
)
1669 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1673 /* Estimate as 4 + 4 * #ofbits. */
1674 *total
= COSTS_N_INSNS (132);
1683 if (!CONST_INT_P (XEXP (x
, 1))
1684 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1686 /* Estimate this as 4 + 8 * #of bits. */
1687 *total
= COSTS_N_INSNS (260);
1693 if (CONST_INT_P (XEXP (x
, 1))
1694 /* Two constants may actually happen before optimization. */
1695 && !CONST_INT_P (XEXP (x
, 0))
1696 && !CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x
, 1)), 'I'))
1698 *total
= (rtx_cost (XEXP (x
, 0), outer_code
) + 2
1699 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
1704 case ZERO_EXTEND
: case SIGN_EXTEND
:
1705 *total
= rtx_cost (XEXP (x
, 0), outer_code
);
1713 /* The ADDRESS_COST worker. */
1716 cris_address_cost (rtx x
)
1718 /* The metric to use for the cost-macros is unclear.
1719 The metric used here is (the number of cycles needed) / 2,
1720 where we consider equal a cycle for a word of code and a cycle to
1723 /* The cheapest addressing modes get 0, since nothing extra is needed. */
1724 if (BASE_OR_AUTOINCR_P (x
))
1727 /* An indirect mem must be a DIP. This means two bytes extra for code,
1728 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
1732 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1733 an extra DIP prefix and 4 bytes of constant in most cases. */
1737 /* Handle BIAP and BDAP prefixes. */
1738 if (GET_CODE (x
) == PLUS
)
1740 rtx tem1
= XEXP (x
, 0);
1741 rtx tem2
= XEXP (x
, 1);
1743 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
1744 recognize the typical MULT which is always in tem1 because of
1745 insn canonicalization. */
1746 if ((GET_CODE (tem1
) == MULT
&& BIAP_INDEX_P (tem1
))
1750 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
1751 PLUS is always found in tem2. */
1752 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
1755 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1757 if (CONST_INT_P (tem2
) && CONST_OK_FOR_LETTER_P (INTVAL (tem2
), 'L'))
1760 /* A BDAP with some other constant is 2 bytes extra. */
1761 if (CONSTANT_P (tem2
))
1762 return (2 + 2 + 2) / 2;
1764 /* BDAP with something indirect should have a higher cost than
1765 BIAP with register. FIXME: Should it cost like a MEM or more? */
1766 /* Don't need to check it, it's the only one left.
1767 FIXME: There was a REG test missing, perhaps there are others.
1769 return (2 + 2 + 2) / 2;
1772 /* What else? Return a high cost. It matters only for valid
1773 addressing modes. */
1777 /* Check various objections to the side-effect. Used in the test-part
1778 of an anonymous insn describing an insn with a possible side-effect.
1779 Returns nonzero if the implied side-effect is ok.
1782 ops : An array of rtx:es. lreg, rreg, rval,
1783 The variables multop and other_op are indexes into this,
1784 or -1 if they are not applicable.
1785 lreg : The register that gets assigned in the side-effect.
1786 rreg : One register in the side-effect expression
1787 rval : The other register, or an int.
1788 multop : An integer to multiply rval with.
1789 other_op : One of the entities of the main effect,
1790 whose mode we must consider. */
1793 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
1794 int lreg
, int rreg
, int rval
,
1795 int multop
, int other_op
)
1797 /* Find what value to multiply with, for rx =ry + rz * n. */
1798 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
1800 rtx reg_rtx
= ops
[rreg
];
1801 rtx val_rtx
= ops
[rval
];
1803 /* The operands may be swapped. Canonicalize them in reg_rtx and
1804 val_rtx, where reg_rtx always is a reg (for this constraint to
1806 if (! BASE_P (reg_rtx
))
1807 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
1809 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
1810 we have no business. */
1811 if (! BASE_P (reg_rtx
))
1814 /* Don't do this when -mno-split. */
1815 if (!TARGET_SIDE_EFFECT_PREFIXES
)
1818 /* The mult expression may be hidden in lreg. FIXME: Add more
1819 commentary about that. */
1820 if (GET_CODE (val_rtx
) == MULT
)
1822 mult
= INTVAL (XEXP (val_rtx
, 1));
1823 val_rtx
= XEXP (val_rtx
, 0);
1827 /* First check the "other operand". */
1830 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
1833 /* Check if the lvalue register is the same as the "other
1834 operand". If so, the result is undefined and we shouldn't do
1835 this. FIXME: Check again. */
1836 if ((BASE_P (ops
[lreg
])
1837 && BASE_P (ops
[other_op
])
1838 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
1839 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
1843 /* Do not accept frame_pointer_rtx as any operand. */
1844 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
1845 || ops
[rval
] == frame_pointer_rtx
1846 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
1850 && ! BASE_P (val_rtx
))
1853 /* Do not allow rx = rx + n if a normal add or sub with same size
1855 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
1856 && CONST_INT_P (val_rtx
)
1857 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
1860 /* Check allowed cases, like [r(+)?].[bwd] and const. */
1861 if (CONSTANT_P (val_rtx
))
1864 if (MEM_P (val_rtx
) && BASE_OR_AUTOINCR_P (XEXP (val_rtx
, 0)))
1867 if (GET_CODE (val_rtx
) == SIGN_EXTEND
1868 && MEM_P (XEXP (val_rtx
, 0))
1869 && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx
, 0), 0)))
1872 /* If we got here, it's not a valid addressing mode. */
1875 else if (code
== MULT
1876 || (code
== PLUS
&& BASE_P (val_rtx
)))
1878 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
1879 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
1880 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
1883 /* Do not allow bad multiply-values. */
1884 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
1887 /* Only allow r + ... */
1888 if (! BASE_P (reg_rtx
))
1891 /* If we got here, all seems ok.
1892 (All checks need to be done above). */
1896 /* If we get here, the caller got its initial tests wrong. */
1897 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
1900 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
1901 does not handle the case where the IN operand is strict_low_part; it
1902 does handle it for X. Test-case in Axis-20010516. This function takes
1903 care of that for THIS port. FIXME: strict_low_part is going away
1907 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
1909 /* The function reg_overlap_mentioned now handles when X is
1910 strict_low_part, but not when IN is a STRICT_LOW_PART. */
1911 if (GET_CODE (in
) == STRICT_LOW_PART
)
1914 return reg_overlap_mentioned_p (x
, in
);
1917 /* The TARGET_ASM_NAMED_SECTION worker.
1918 We just dispatch to the functions for ELF and a.out. */
1921 cris_target_asm_named_section (const char *name
, unsigned int flags
,
1925 default_no_named_section (name
, flags
, decl
);
1927 default_elf_asm_named_section (name
, flags
, decl
);
1930 /* Return TRUE iff X is a CONST valid for e.g. indexing. */
1933 cris_valid_pic_const (rtx x
)
1935 gcc_assert (flag_pic
);
1937 switch (GET_CODE (x
))
1946 if (GET_CODE (x
) != CONST
)
1951 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
1952 if (GET_CODE (x
) == PLUS
1953 && GET_CODE (XEXP (x
, 0)) == UNSPEC
1954 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
1955 && CONST_INT_P (XEXP (x
, 1)))
1958 if (GET_CODE (x
) == UNSPEC
)
1959 switch (XINT (x
, 1))
1961 case CRIS_UNSPEC_PLT
:
1962 case CRIS_UNSPEC_PLTGOTREAD
:
1963 case CRIS_UNSPEC_GOTREAD
:
1964 case CRIS_UNSPEC_GOTREL
:
1970 return cris_pic_symbol_type_of (x
) == cris_no_symbol
;
1973 /* Helper function to find the right PIC-type symbol to generate,
1974 given the original (non-PIC) representation. */
1976 enum cris_pic_symbol_type
1977 cris_pic_symbol_type_of (rtx x
)
1979 switch (GET_CODE (x
))
1982 return SYMBOL_REF_LOCAL_P (x
)
1983 ? cris_gotrel_symbol
: cris_got_symbol
;
1986 return cris_gotrel_symbol
;
1989 return cris_pic_symbol_type_of (XEXP (x
, 0));
1994 enum cris_pic_symbol_type t1
= cris_pic_symbol_type_of (XEXP (x
, 0));
1995 enum cris_pic_symbol_type t2
= cris_pic_symbol_type_of (XEXP (x
, 1));
1997 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
1999 if (t1
== cris_got_symbol
|| t1
== cris_got_symbol
)
2000 return cris_got_symbol_needing_fixup
;
2002 return t1
!= cris_no_symbol
? t1
: t2
;
2007 return cris_no_symbol
;
2010 /* Likely an offsettability-test attempting to add a constant to
2011 a GOTREAD symbol, which can't be handled. */
2012 return cris_invalid_pic_symbol
;
2015 fatal_insn ("unrecognized supposed constant", x
);
2021 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2024 cris_legitimate_pic_operand (rtx x
)
2026 /* Symbols are not valid PIC operands as-is; just constants. */
2027 return cris_valid_pic_const (x
);
2030 /* TARGET_HANDLE_OPTION worker. We just store the values into local
2031 variables here. Checks for correct semantics are in
2032 cris_override_options. */
2035 cris_handle_option (size_t code
, const char *arg ATTRIBUTE_UNUSED
,
2036 int value ATTRIBUTE_UNUSED
)
2044 + MASK_ALIGN_BY_32
);
2047 case OPT_mno_etrax100
:
2051 + MASK_ALIGN_BY_32
);
2057 |= (MASK_STACK_ALIGN
2060 + MASK_ALIGN_BY_32
);
2066 |= (MASK_STACK_ALIGN
2074 &= ~(MASK_STACK_ALIGN
2083 CRIS_SUBTARGET_HANDLE_OPTION(code
, arg
, value
);
2088 /* The OVERRIDE_OPTIONS worker.
2089 As is the norm, this also parses -mfoo=bar type parameters. */
2092 cris_override_options (void)
2094 if (cris_max_stackframe_str
)
2096 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2098 /* Do some sanity checking. */
2099 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2100 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2101 cris_max_stackframe
, 0x20000000);
2104 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2105 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2106 cris_cpu_version
= CRIS_CPU_SVINTO
;
2107 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2108 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2110 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2114 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2116 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2117 cris_cpu_version
= 3;
2119 if (strcmp ("svinto", cris_cpu_str
) == 0
2120 || strcmp ("etrax100", cris_cpu_str
) == 0)
2121 cris_cpu_version
= 8;
2123 if (strcmp ("ng", cris_cpu_str
) == 0
2124 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2125 cris_cpu_version
= 10;
2127 if (cris_cpu_version
< 0 || cris_cpu_version
> 10)
2128 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2131 /* Set the target flags. */
2132 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2133 target_flags
|= MASK_ETRAX4_ADD
;
2135 /* If this is Svinto or higher, align for 32 bit accesses. */
2136 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2138 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2139 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2142 /* Note that we do not add new flags when it can be completely
2143 described with a macro that uses -mcpu=X. So
2144 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2150 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2152 if (strcmp ("etrax4", cris_tune_str
) == 0)
2155 if (strcmp ("svinto", cris_tune_str
) == 0
2156 || strcmp ("etrax100", cris_tune_str
) == 0)
2159 if (strcmp ("ng", cris_tune_str
) == 0
2160 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2163 if (cris_tune
< 0 || cris_tune
> 10)
2164 error ("unknown CRIS cpu version specification in -mtune= : %s",
2167 if (cris_tune
>= CRIS_CPU_SVINTO
)
2168 /* We have currently nothing more to tune than alignment for
2171 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2172 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2177 /* Use error rather than warning, so invalid use is easily
2178 detectable. Still change to the values we expect, to avoid
2182 error ("-fPIC and -fpic are not supported in this configuration");
2186 /* Turn off function CSE. We need to have the addresses reach the
2187 call expanders to get PLT-marked, as they could otherwise be
2188 compared against zero directly or indirectly. After visiting the
2189 call expanders they will then be cse:ed, as the call expanders
2190 force_reg the addresses, effectively forcing flag_no_function_cse
2192 flag_no_function_cse
= 1;
2195 if (write_symbols
== DWARF2_DEBUG
&& ! TARGET_ELF
)
2197 warning (0, "that particular -g option is invalid with -maout and -melinux");
2198 write_symbols
= DBX_DEBUG
;
2201 /* Set the per-function-data initializer. */
2202 init_machine_status
= cris_init_machine_status
;
2205 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2208 cris_asm_output_mi_thunk (FILE *stream
,
2209 tree thunkdecl ATTRIBUTE_UNUSED
,
2210 HOST_WIDE_INT delta
,
2211 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2215 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2216 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2217 reg_names
[CRIS_FIRST_ARG_REG
]);
2219 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2220 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2221 reg_names
[CRIS_FIRST_ARG_REG
]);
2225 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2227 name
= (* targetm
.strip_name_encoding
) (name
);
2228 fprintf (stream
, "add.d ");
2229 assemble_name (stream
, name
);
2230 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2234 fprintf (stream
, "jump ");
2235 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2236 fprintf (stream
, "\n");
2240 /* Boilerplate emitted at start of file.
2242 NO_APP *only at file start* means faster assembly. It also means
2243 comments are not allowed. In some cases comments will be output
2244 for debugging purposes. Make sure they are allowed then.
2246 We want a .file directive only if TARGET_ELF. */
2248 cris_file_start (void)
2250 /* These expressions can vary at run time, so we cannot put
2251 them into TARGET_INITIALIZER. */
2252 targetm
.file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2253 targetm
.file_start_file_directive
= TARGET_ELF
;
2255 default_file_start ();
2258 /* Rename the function calls for integer multiply and divide. */
2260 cris_init_libfuncs (void)
2262 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2263 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2264 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2265 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2266 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2269 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2273 cris_init_expanders (void)
2275 /* Nothing here at the moment. */
2278 /* Zero initialization is OK for all current fields. */
2280 static struct machine_function
*
2281 cris_init_machine_status (void)
2283 return ggc_alloc_cleared (sizeof (struct machine_function
));
2286 /* Split a 2 word move (DI or presumably DF) into component parts.
2287 Originally a copy of gen_split_move_double in m32r.c. */
2290 cris_split_movdx (rtx
*operands
)
2292 enum machine_mode mode
= GET_MODE (operands
[0]);
2293 rtx dest
= operands
[0];
2294 rtx src
= operands
[1];
2297 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2298 longer happen; after reload there are no SUBREGs any more, and we're
2299 only called after reload. */
2300 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2305 int dregno
= REGNO (dest
);
2307 /* Reg-to-reg copy. */
2310 int sregno
= REGNO (src
);
2312 int reverse
= (dregno
== sregno
+ 1);
2314 /* We normally copy the low-numbered register first. However, if
2315 the first register operand 0 is the same as the second register of
2316 operand 1, we must copy in the opposite order. */
2317 emit_insn (gen_rtx_SET (VOIDmode
,
2318 operand_subword (dest
, reverse
, TRUE
, mode
),
2319 operand_subword (src
, reverse
, TRUE
, mode
)));
2321 emit_insn (gen_rtx_SET (VOIDmode
,
2322 operand_subword (dest
, !reverse
, TRUE
, mode
),
2323 operand_subword (src
, !reverse
, TRUE
, mode
)));
2325 /* Constant-to-reg copy. */
2326 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2329 split_double (src
, &words
[0], &words
[1]);
2330 emit_insn (gen_rtx_SET (VOIDmode
,
2331 operand_subword (dest
, 0, TRUE
, mode
),
2334 emit_insn (gen_rtx_SET (VOIDmode
,
2335 operand_subword (dest
, 1, TRUE
, mode
),
2338 /* Mem-to-reg copy. */
2339 else if (MEM_P (src
))
2341 /* If the high-address word is used in the address, we must load it
2342 last. Otherwise, load it first. */
2343 rtx addr
= XEXP (src
, 0);
2345 = (refers_to_regno_p (dregno
, dregno
+ 1, addr
, NULL
) != 0);
2347 /* The original code implies that we can't do
2348 move.x [rN+],rM move.x [rN],rM+1
2349 when rN is dead, because of REG_NOTES damage. That is
2350 consistent with what I've seen, so don't try it.
2352 We have two different cases here; if the addr is POST_INC,
2353 just pass it through, otherwise add constants. */
2355 if (GET_CODE (addr
) == POST_INC
)
2360 /* Whenever we emit insns with post-incremented
2361 addresses ourselves, we must add a post-inc note
2363 mem
= change_address (src
, SImode
, addr
);
2365 = gen_rtx_SET (VOIDmode
,
2366 operand_subword (dest
, 0, TRUE
, mode
), mem
);
2367 insn
= emit_insn (insn
);
2368 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2370 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2373 mem
= change_address (src
, SImode
, addr
);
2375 = gen_rtx_SET (VOIDmode
,
2376 operand_subword (dest
, 1, TRUE
, mode
), mem
);
2377 insn
= emit_insn (insn
);
2378 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2380 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2385 /* Make sure we don't get any other addresses with
2386 embedded postincrements. They should be stopped in
2387 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2389 if (side_effects_p (addr
))
2390 fatal_insn ("unexpected side-effects in address", addr
);
2392 emit_insn (gen_rtx_SET
2394 operand_subword (dest
, reverse
, TRUE
, mode
),
2397 plus_constant (addr
,
2398 reverse
* UNITS_PER_WORD
))));
2399 emit_insn (gen_rtx_SET
2401 operand_subword (dest
, ! reverse
, TRUE
, mode
),
2404 plus_constant (addr
,
2410 internal_error ("Unknown src");
2412 /* Reg-to-mem copy or clear mem. */
2413 else if (MEM_P (dest
)
2415 || src
== const0_rtx
2416 || src
== CONST0_RTX (DFmode
)))
2418 rtx addr
= XEXP (dest
, 0);
2420 if (GET_CODE (addr
) == POST_INC
)
2425 /* Whenever we emit insns with post-incremented addresses
2426 ourselves, we must add a post-inc note manually. */
2427 mem
= change_address (dest
, SImode
, addr
);
2429 = gen_rtx_SET (VOIDmode
,
2430 mem
, operand_subword (src
, 0, TRUE
, mode
));
2431 insn
= emit_insn (insn
);
2432 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2434 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2437 mem
= change_address (dest
, SImode
, addr
);
2439 = gen_rtx_SET (VOIDmode
,
2441 operand_subword (src
, 1, TRUE
, mode
));
2442 insn
= emit_insn (insn
);
2443 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2445 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2450 /* Make sure we don't get any other addresses with embedded
2451 postincrements. They should be stopped in
2452 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2453 if (side_effects_p (addr
))
2454 fatal_insn ("unexpected side-effects in address", addr
);
2456 emit_insn (gen_rtx_SET
2458 change_address (dest
, SImode
, addr
),
2459 operand_subword (src
, 0, TRUE
, mode
)));
2461 emit_insn (gen_rtx_SET
2463 change_address (dest
, SImode
,
2464 plus_constant (addr
,
2466 operand_subword (src
, 1, TRUE
, mode
)));
2471 internal_error ("Unknown dest");
2478 /* The expander for the prologue pattern name. */
2481 cris_expand_prologue (void)
2484 int size
= get_frame_size ();
2485 /* Shorten the used name for readability. */
2486 int cfoa_size
= current_function_outgoing_args_size
;
2487 int last_movem_reg
= -1;
2490 int return_address_on_stack
= cris_return_address_on_stack ();
2491 int got_really_used
= false;
2492 int n_movem_regs
= 0;
2493 int pretend
= current_function_pretend_args_size
;
2495 /* Don't do anything if no prologues or epilogues are wanted. */
2496 if (!TARGET_PROLOGUE_EPILOGUE
)
2499 CRIS_ASSERT (size
>= 0);
2501 if (current_function_uses_pic_offset_table
)
2503 /* A reference may have been optimized out (like the abort () in
2504 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2506 push_topmost_sequence ();
2508 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
2509 pop_topmost_sequence ();
2512 /* Align the size to what's best for the CPU model. */
2513 if (TARGET_STACK_ALIGN
)
2514 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
2518 /* See also cris_setup_incoming_varargs where
2519 cfun->machine->stdarg_regs is set. There are other setters of
2520 current_function_pretend_args_size than stdarg handling, like
2521 for an argument passed with parts in R13 and stack. We must
2522 not store R13 into the pretend-area for that case, as GCC does
2523 that itself. "Our" store would be marked as redundant and GCC
2524 will attempt to remove it, which will then be flagged as an
2525 internal error; trying to remove a frame-related insn. */
2526 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
2528 framesize
+= pretend
;
2530 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
2532 regno
--, pretend
-= 4, stdarg_regs
--)
2534 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2536 plus_constant (stack_pointer_rtx
,
2538 /* FIXME: When dwarf2 frame output and unless asynchronous
2539 exceptions, make dwarf2 bundle together all stack
2540 adjustments like it does for registers between stack
2542 RTX_FRAME_RELATED_P (insn
) = 1;
2544 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2545 set_mem_alias_set (mem
, get_varargs_alias_set ());
2546 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
2548 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2549 the value isn't restored, so we don't want to tell dwarf2
2550 that it's been stored to stack, else EH handling info would
2554 /* For other setters of current_function_pretend_args_size, we
2555 just adjust the stack by leaving the remaining size in
2556 "pretend", handled below. */
2559 /* Save SRP if not a leaf function. */
2560 if (return_address_on_stack
)
2562 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2564 plus_constant (stack_pointer_rtx
,
2567 RTX_FRAME_RELATED_P (insn
) = 1;
2569 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2570 set_mem_alias_set (mem
, get_frame_alias_set ());
2571 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
));
2572 RTX_FRAME_RELATED_P (insn
) = 1;
2576 /* Set up the frame pointer, if needed. */
2577 if (frame_pointer_needed
)
2579 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2581 plus_constant (stack_pointer_rtx
,
2584 RTX_FRAME_RELATED_P (insn
) = 1;
2586 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2587 set_mem_alias_set (mem
, get_frame_alias_set ());
2588 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
2589 RTX_FRAME_RELATED_P (insn
) = 1;
2591 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
2592 RTX_FRAME_RELATED_P (insn
) = 1;
2597 /* Between frame-pointer and saved registers lie the area for local
2598 variables. If we get here with "pretended" size remaining, count
2599 it into the general stack size. */
2602 /* Get a contiguous sequence of registers, starting with R0, that need
2604 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2606 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2610 /* Check if movem may be used for registers so far. */
2611 if (regno
== last_movem_reg
+ 1)
2612 /* Yes, update next expected register. */
2613 last_movem_reg
= regno
;
2616 /* We cannot use movem for all registers. We have to flush
2617 any movem:ed registers we got so far. */
2618 if (last_movem_reg
!= -1)
2621 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
2623 /* It is a win to use a side-effect assignment for
2624 64 <= size <= 128. But side-effect on movem was
2625 not usable for CRIS v0..3. Also only do it if
2626 side-effects insns are allowed. */
2627 if ((last_movem_reg
+ 1) * 4 + size
>= 64
2628 && (last_movem_reg
+ 1) * 4 + size
<= 128
2629 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
2630 && TARGET_SIDE_EFFECT_PREFIXES
)
2633 = gen_rtx_MEM (SImode
,
2634 plus_constant (stack_pointer_rtx
,
2635 -(n_saved
* 4 + size
)));
2636 set_mem_alias_set (mem
, get_frame_alias_set ());
2638 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2639 -(n_saved
* 4 + size
),
2645 = gen_rtx_SET (VOIDmode
,
2647 plus_constant (stack_pointer_rtx
,
2648 -(n_saved
* 4 + size
)));
2649 insn
= emit_insn (insn
);
2650 RTX_FRAME_RELATED_P (insn
) = 1;
2652 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2653 set_mem_alias_set (mem
, get_frame_alias_set ());
2654 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2658 framesize
+= n_saved
* 4 + size
;
2659 last_movem_reg
= -1;
2663 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2665 plus_constant (stack_pointer_rtx
,
2667 RTX_FRAME_RELATED_P (insn
) = 1;
2669 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2670 set_mem_alias_set (mem
, get_frame_alias_set ());
2671 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
2672 RTX_FRAME_RELATED_P (insn
) = 1;
2674 framesize
+= 4 + size
;
2680 /* Check after, if we could movem all registers. This is the normal case. */
2681 if (last_movem_reg
!= -1)
2684 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
2686 /* Side-effect on movem was not usable for CRIS v0..3. Also only
2687 do it if side-effects insns are allowed. */
2688 if ((last_movem_reg
+ 1) * 4 + size
>= 64
2689 && (last_movem_reg
+ 1) * 4 + size
<= 128
2690 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
2691 && TARGET_SIDE_EFFECT_PREFIXES
)
2694 = gen_rtx_MEM (SImode
,
2695 plus_constant (stack_pointer_rtx
,
2696 -(n_saved
* 4 + size
)));
2697 set_mem_alias_set (mem
, get_frame_alias_set ());
2698 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2699 -(n_saved
* 4 + size
), true);
2704 = gen_rtx_SET (VOIDmode
,
2706 plus_constant (stack_pointer_rtx
,
2707 -(n_saved
* 4 + size
)));
2708 insn
= emit_insn (insn
);
2709 RTX_FRAME_RELATED_P (insn
) = 1;
2711 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2712 set_mem_alias_set (mem
, get_frame_alias_set ());
2713 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
2716 framesize
+= n_saved
* 4 + size
;
2717 /* We have to put outgoing argument space after regs. */
2720 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2722 plus_constant (stack_pointer_rtx
,
2724 RTX_FRAME_RELATED_P (insn
) = 1;
2725 framesize
+= cfoa_size
;
2728 else if ((size
+ cfoa_size
) > 0)
2730 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2732 plus_constant (stack_pointer_rtx
,
2733 -(cfoa_size
+ size
))));
2734 RTX_FRAME_RELATED_P (insn
) = 1;
2735 framesize
+= size
+ cfoa_size
;
2738 /* Set up the PIC register, if it is used. */
2739 if (got_really_used
)
2742 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
2743 emit_move_insn (pic_offset_table_rtx
, got
);
2745 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
2746 follow exceptional paths and tries to delete the GOT load as
2747 unused, if it isn't used on the non-exceptional paths. Other
2748 ports have similar or other cover-ups, or plain bugs marking
2749 the GOT register load as maybe-dead. To see this, remove the
2750 line below and try libsupc++/vec.cc or a trivial
2751 "static void y (); void x () {try {y ();} catch (...) {}}". */
2752 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2755 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
2756 warning (0, "stackframe too big: %d bytes", framesize
);
2759 /* The expander for the epilogue pattern. */
2762 cris_expand_epilogue (void)
2765 int size
= get_frame_size ();
2766 int last_movem_reg
= -1;
2767 int argspace_offset
= current_function_outgoing_args_size
;
2768 int pretend
= current_function_pretend_args_size
;
2770 bool return_address_on_stack
= cris_return_address_on_stack ();
2771 /* A reference may have been optimized out
2772 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
2773 so check that it's still used. */
2774 int got_really_used
= false;
2775 int n_movem_regs
= 0;
2777 if (!TARGET_PROLOGUE_EPILOGUE
)
2780 if (current_function_uses_pic_offset_table
)
2782 /* A reference may have been optimized out (like the abort () in
2783 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2785 push_topmost_sequence ();
2787 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
2788 pop_topmost_sequence ();
2791 /* Align byte count of stack frame. */
2792 if (TARGET_STACK_ALIGN
)
2793 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
2795 /* Check how many saved regs we can movem. They start at r0 and must
2798 regno
< FIRST_PSEUDO_REGISTER
;
2800 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2804 if (regno
== last_movem_reg
+ 1)
2805 last_movem_reg
= regno
;
2810 /* If there was only one register that really needed to be saved
2811 through movem, don't use movem. */
2812 if (n_movem_regs
== 1)
2813 last_movem_reg
= -1;
2815 /* Now emit "normal" move insns for all regs higher than the movem
2817 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
2818 regno
> last_movem_reg
;
2820 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2824 if (argspace_offset
)
2826 /* There is an area for outgoing parameters located before
2827 the saved registers. We have to adjust for that. */
2828 emit_insn (gen_rtx_SET (VOIDmode
,
2830 plus_constant (stack_pointer_rtx
,
2832 /* Make sure we only do this once. */
2833 argspace_offset
= 0;
2836 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
2837 stack_pointer_rtx
));
2838 set_mem_alias_set (mem
, get_frame_alias_set ());
2839 insn
= emit_move_insn (gen_rtx_raw_REG (SImode
, regno
), mem
);
2841 /* Whenever we emit insns with post-incremented addresses
2842 ourselves, we must add a post-inc note manually. */
2844 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
2847 /* If we have any movem-restore, do it now. */
2848 if (last_movem_reg
!= -1)
2852 if (argspace_offset
)
2854 emit_insn (gen_rtx_SET (VOIDmode
,
2856 plus_constant (stack_pointer_rtx
,
2858 argspace_offset
= 0;
2861 mem
= gen_rtx_MEM (SImode
,
2862 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
2863 set_mem_alias_set (mem
, get_frame_alias_set ());
2865 = emit_insn (cris_gen_movem_load (mem
,
2866 GEN_INT (last_movem_reg
+ 1), 0));
2867 /* Whenever we emit insns with post-incremented addresses
2868 ourselves, we must add a post-inc note manually. */
2869 if (side_effects_p (PATTERN (insn
)))
2871 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
2874 /* If we don't clobber all of the allocated stack area (we've already
2875 deallocated saved registers), GCC might want to schedule loads from
2876 the stack to *after* the stack-pointer restore, which introduces an
2877 interrupt race condition. This happened for the initial-value
2878 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
2879 other failure for that test). It also happened for the stack slot
2880 for the return value in (one version of)
2881 linux/fs/dcache.c:__d_lookup, at least with "-O2
2882 -fno-omit-frame-pointer". */
2884 /* Restore frame pointer if necessary. */
2885 if (frame_pointer_needed
)
2889 emit_insn (gen_cris_frame_deallocated_barrier ());
2891 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
2892 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
2893 stack_pointer_rtx
));
2894 set_mem_alias_set (mem
, get_frame_alias_set ());
2895 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
2897 /* Whenever we emit insns with post-incremented addresses
2898 ourselves, we must add a post-inc note manually. */
2900 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
2902 else if ((size
+ argspace_offset
) != 0)
2904 emit_insn (gen_cris_frame_deallocated_barrier ());
2906 /* If there was no frame-pointer to restore sp from, we must
2907 explicitly deallocate local variables. */
2909 /* Handle space for outgoing parameters that hasn't been handled
2911 size
+= argspace_offset
;
2913 emit_insn (gen_rtx_SET (VOIDmode
,
2915 plus_constant (stack_pointer_rtx
, size
)));
2918 /* If this function has no pushed register parameters
2919 (stdargs/varargs), and if it is not a leaf function, then we have
2920 the return address on the stack. */
2921 if (return_address_on_stack
&& pretend
== 0)
2923 if (current_function_calls_eh_return
)
2927 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
2928 mem
= gen_rtx_MEM (SImode
,
2929 gen_rtx_POST_INC (SImode
,
2930 stack_pointer_rtx
));
2931 set_mem_alias_set (mem
, get_frame_alias_set ());
2932 insn
= emit_move_insn (srpreg
, mem
);
2934 /* Whenever we emit insns with post-incremented addresses
2935 ourselves, we must add a post-inc note manually. */
2937 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
2939 emit_insn (gen_addsi3 (stack_pointer_rtx
,
2941 gen_rtx_raw_REG (SImode
,
2942 CRIS_STACKADJ_REG
)));
2943 cris_expand_return (false);
2946 cris_expand_return (true);
2951 /* If we pushed some register parameters, then adjust the stack for
2955 /* If SRP is stored on the way, we need to restore it first. */
2956 if (return_address_on_stack
)
2959 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
2962 mem
= gen_rtx_MEM (SImode
,
2963 gen_rtx_POST_INC (SImode
,
2964 stack_pointer_rtx
));
2965 set_mem_alias_set (mem
, get_frame_alias_set ());
2966 insn
= emit_move_insn (srpreg
, mem
);
2968 /* Whenever we emit insns with post-incremented addresses
2969 ourselves, we must add a post-inc note manually. */
2971 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
2974 emit_insn (gen_rtx_SET (VOIDmode
,
2976 plus_constant (stack_pointer_rtx
, pretend
)));
2979 /* Perform the "physical" unwinding that the EH machinery calculated. */
2980 if (current_function_calls_eh_return
)
2981 emit_insn (gen_addsi3 (stack_pointer_rtx
,
2983 gen_rtx_raw_REG (SImode
,
2984 CRIS_STACKADJ_REG
)));
2985 cris_expand_return (false);
2988 /* Worker function for generating movem from mem for load_multiple. */
2991 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
2993 int nregs
= INTVAL (nregs_rtx
);
2997 rtx srcreg
= XEXP (src
, 0);
2998 unsigned int regno
= nregs
- 1;
3001 if (GET_CODE (srcreg
) == POST_INC
)
3002 srcreg
= XEXP (srcreg
, 0);
3004 CRIS_ASSERT (REG_P (srcreg
));
3006 /* Don't use movem for just one insn. The insns are equivalent except
3007 for the pipeline hazard (on v32); movem does not forward the loaded
3008 registers so there's a three cycles penalty for their use. */
3010 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3012 vec
= rtvec_alloc (nprefix
+ nregs
3013 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3015 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3017 RTVEC_ELT (vec
, nprefix
+ 1)
3018 = gen_rtx_SET (VOIDmode
, srcreg
, plus_constant (srcreg
, nregs
* 4));
3022 src
= replace_equiv_address (src
, srcreg
);
3023 RTVEC_ELT (vec
, nprefix
)
3024 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
), src
);
3027 for (i
= 1; i
< nregs
; i
++, eltno
++)
3029 RTVEC_ELT (vec
, nprefix
+ eltno
)
3030 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
),
3031 adjust_address_nv (src
, SImode
, i
* 4));
3035 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3038 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3039 are added that the dwarf2 machinery understands. */
3042 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3045 int nregs
= INTVAL (nregs_rtx
);
3050 rtx destreg
= XEXP (dest
, 0);
3051 unsigned int regno
= nregs
- 1;
3054 if (GET_CODE (destreg
) == POST_INC
)
3055 increment
+= nregs
* 4;
3057 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3058 destreg
= XEXP (destreg
, 0);
3060 CRIS_ASSERT (REG_P (destreg
));
3062 /* Don't use movem for just one insn. The insns are equivalent except
3063 for the pipeline hazard (on v32); movem does not forward the loaded
3064 registers so there's a three cycles penalty for use. */
3067 rtx mov
= gen_rtx_SET (VOIDmode
, dest
, gen_rtx_REG (SImode
, 0));
3071 insn
= emit_insn (mov
);
3073 RTX_FRAME_RELATED_P (insn
) = 1;
3077 /* If there was a request for a side-effect, create the ordinary
3079 vec
= rtvec_alloc (2);
3081 RTVEC_ELT (vec
, 0) = mov
;
3082 RTVEC_ELT (vec
, 1) = gen_rtx_SET (VOIDmode
, destreg
,
3083 plus_constant (destreg
, increment
));
3086 RTX_FRAME_RELATED_P (mov
) = 1;
3087 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3092 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3094 = gen_rtx_SET (VOIDmode
,
3095 replace_equiv_address (dest
,
3096 plus_constant (destreg
,
3098 gen_rtx_REG (SImode
, regno
));
3101 /* The dwarf2 info wants this mark on each component in a parallel
3102 that's part of the prologue (though it's optional on the first
3105 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3110 = gen_rtx_SET (VOIDmode
, destreg
,
3111 plus_constant (destreg
,
3113 ? increment
: nregs
* 4));
3117 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3119 /* Don't call adjust_address_nv on a post-incremented address if
3121 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3122 dest
= replace_equiv_address (dest
, destreg
);
3125 for (i
= 1; i
< nregs
; i
++, eltno
++)
3127 RTVEC_ELT (vec
, eltno
)
3128 = gen_rtx_SET (VOIDmode
, adjust_address_nv (dest
, SImode
, i
* 4),
3129 gen_rtx_REG (SImode
, regno
));
3131 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3136 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3138 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3139 we need to keep the stack adjustment separate, after the
3140 MEM-setters. Else the stack-adjustment in the second component of
3141 the parallel would be mishandled; the offsets for the SETs that
3142 follow it would be wrong. We prepare for this by adding a
3143 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3144 followed by the increment. Note that we have FRAME_RELATED_P on
3145 all the SETs, including the original stack adjustment SET in the
3151 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3152 XVECEXP (seq
, 0, 0) = XVECEXP (PATTERN (insn
), 0, 0);
3153 for (i
= 1; i
< nregs
; i
++)
3154 XVECEXP (seq
, 0, i
) = XVECEXP (PATTERN (insn
), 0, i
+ 1);
3155 XVECEXP (seq
, 0, nregs
) = XVECEXP (PATTERN (insn
), 0, 1);
3157 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, seq
,
3161 RTX_FRAME_RELATED_P (insn
) = 1;
3167 /* Worker function for expanding the address for PIC function calls. */
3170 cris_expand_pic_call_address (rtx
*opp
)
3174 gcc_assert (MEM_P (op
));
3177 /* It might be that code can be generated that jumps to 0 (or to a
3178 specific address). Don't die on that. (There is a
3180 if (CONSTANT_ADDRESS_P (op
) && CONST_INT_P (op
))
3182 enum cris_pic_symbol_type t
= cris_pic_symbol_type_of (op
);
3184 CRIS_ASSERT (!no_new_pseudos
);
3186 /* For local symbols (non-PLT), just get the plain symbol
3187 reference into a register. For symbols that can be PLT, make
3189 if (t
== cris_gotrel_symbol
)
3190 op
= force_reg (Pmode
, op
);
3191 else if (t
== cris_got_symbol
)
3193 if (TARGET_AVOID_GOTPLT
)
3195 /* Change a "jsr sym" into (allocate register rM, rO)
3196 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT)),rM"
3197 "add.d rPIC,rM,rO", "jsr rO". */
3199 gcc_assert (! no_new_pseudos
);
3200 current_function_uses_pic_offset_table
= 1;
3201 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
), CRIS_UNSPEC_PLT
);
3202 rm
= gen_reg_rtx (Pmode
);
3203 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3204 ro
= gen_reg_rtx (Pmode
);
3205 if (expand_binop (Pmode
, add_optab
, rm
,
3206 pic_offset_table_rtx
,
3207 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3208 internal_error ("expand_binop failed in movsi got");
3213 /* Change a "jsr sym" into (allocate register rM, rO)
3214 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOT)),rM"
3215 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3216 marked as not trapping and not aliasing. No "move.d
3217 [rO],rP" as that would invite to re-use of a value
3218 that should not be reused. FIXME: Need a peephole2
3219 for cases when this is cse:d from the call, to change
3220 back to just get the PLT entry address, so we don't
3221 resolve the same symbol over and over (the memory
3222 access of the PLTGOT isn't constant). */
3223 rtx tem
, mem
, rm
, ro
;
3225 gcc_assert (! no_new_pseudos
);
3226 current_function_uses_pic_offset_table
= 1;
3227 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3228 CRIS_UNSPEC_PLTGOTREAD
);
3229 rm
= gen_reg_rtx (Pmode
);
3230 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3231 ro
= gen_reg_rtx (Pmode
);
3232 if (expand_binop (Pmode
, add_optab
, rm
,
3233 pic_offset_table_rtx
,
3234 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3235 internal_error ("expand_binop failed in movsi got");
3236 mem
= gen_rtx_MEM (Pmode
, ro
);
3238 /* This MEM doesn't alias anything. Whether it aliases
3239 other same symbols is unimportant. */
3240 set_mem_alias_set (mem
, new_alias_set ());
3241 MEM_NOTRAP_P (mem
) = 1;
3246 /* Can't possibly get a GOT-needing-fixup for a function-call,
3248 fatal_insn ("Unidentifiable call op", op
);
3250 *opp
= replace_equiv_address (*opp
, op
);
3254 /* Make sure operands are in the right order for an addsi3 insn as
3255 generated by a define_split. A MEM as the first operand isn't
3256 recognized by addsi3 after reload. OPERANDS contains the operands,
3257 with the first at OPERANDS[N] and the second at OPERANDS[N+1]. */
3260 cris_order_for_addsi3 (rtx
*operands
, int n
)
3262 if (MEM_P (operands
[n
]))
3264 rtx tem
= operands
[n
];
3265 operands
[n
] = operands
[n
+ 1];
3266 operands
[n
+ 1] = tem
;
3270 /* Use from within code, from e.g. PRINT_OPERAND and
3271 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3272 different things depending on whether code operand or constant is
3276 cris_output_addr_const (FILE *file
, rtx x
)
3279 output_addr_const (file
, x
);
3283 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3286 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3288 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3290 if (flag_pic
&& in_code
> 0)
3292 const char *origstr
= XSTR (x
, 0);
3294 str
= (* targetm
.strip_name_encoding
) (origstr
);
3295 assemble_name (file
, str
);
3298 if (! current_function_uses_pic_offset_table
)
3299 output_operand_lossage ("PIC register isn't set up");
3302 assemble_name (file
, XSTR (x
, 0));
3305 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3308 cris_asm_output_label_ref (FILE *file
, char *buf
)
3310 if (flag_pic
&& in_code
> 0)
3312 assemble_name (file
, buf
);
3315 if (! current_function_uses_pic_offset_table
)
3316 internal_error ("emitting PIC operand, but PIC register isn't set up");
3319 assemble_name (file
, buf
);
3322 /* Worker function for OUTPUT_ADDR_CONST_EXTRA. */
3325 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3327 switch (GET_CODE (xconst
))
3332 x
= XVECEXP (xconst
, 0, 0);
3333 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3334 || GET_CODE (x
) == LABEL_REF
3335 || GET_CODE (x
) == CONST
);
3336 output_addr_const (file
, x
);
3337 switch (XINT (xconst
, 1))
3339 case CRIS_UNSPEC_PLT
:
3340 fprintf (file
, ":PLTG");
3343 case CRIS_UNSPEC_GOTREL
:
3344 fprintf (file
, ":GOTOFF");
3347 case CRIS_UNSPEC_GOTREAD
:
3349 fprintf (file
, ":GOT16");
3351 fprintf (file
, ":GOT");
3354 case CRIS_UNSPEC_PLTGOTREAD
:
3356 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
3358 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
3371 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3374 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3375 int incoming ATTRIBUTE_UNUSED
)
3377 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
3380 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3383 cris_setup_incoming_varargs (CUMULATIVE_ARGS
*ca
,
3384 enum machine_mode mode ATTRIBUTE_UNUSED
,
3385 tree type ATTRIBUTE_UNUSED
,
3386 int *pretend_arg_size
,
3389 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3391 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
3392 cfun
->machine
->stdarg_regs
= stdarg_regs
;
3393 *pretend_arg_size
= stdarg_regs
* 4;
3397 fprintf (asm_out_file
,
3398 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3399 ca
->regs
, *pretend_arg_size
, second_time
);
3402 /* Return true if TYPE must be passed by invisible reference.
3403 For cris, we pass <= 8 bytes by value, others by reference. */
3406 cris_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
3407 enum machine_mode mode
, tree type
,
3408 bool named ATTRIBUTE_UNUSED
)
3410 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
3411 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
3416 cris_arg_partial_bytes (CUMULATIVE_ARGS
*ca
, enum machine_mode mode
,
3417 tree type
, bool named ATTRIBUTE_UNUSED
)
3419 if (ca
->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
3420 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
3421 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
3422 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
3423 return UNITS_PER_WORD
;
3428 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
3431 cris_md_asm_clobbers (tree outputs
, tree inputs
, tree in_clobbers
)
3433 HARD_REG_SET mof_set
;
3437 CLEAR_HARD_REG_SET (mof_set
);
3438 SET_HARD_REG_BIT (mof_set
, CRIS_MOF_REGNUM
);
3440 /* For the time being, all asms clobber condition codes. Revisit when
3441 there's a reasonable use for inputs/outputs that mention condition
3444 = tree_cons (NULL_TREE
,
3445 build_string (strlen (reg_names
[CRIS_CC0_REGNUM
]),
3446 reg_names
[CRIS_CC0_REGNUM
]),
3449 for (t
= outputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
3451 tree val
= TREE_VALUE (t
);
3453 /* The constraint letter for the singleton register class of MOF
3454 is 'h'. If it's mentioned in the constraints, the asm is
3455 MOF-aware and adding it to the clobbers would cause it to have
3456 impossible constraints. */
3457 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
3459 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
3463 for (t
= inputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
3465 tree val
= TREE_VALUE (t
);
3467 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
3469 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
3473 return tree_cons (NULL_TREE
,
3474 build_string (strlen (reg_names
[CRIS_MOF_REGNUM
]),
3475 reg_names
[CRIS_MOF_REGNUM
]),
3480 /* Various small functions to replace macros. Only called from a
3481 debugger. They might collide with gcc functions or system functions,
3482 so only emit them when '#if 1' above. */
3484 enum rtx_code
Get_code (rtx
);
3489 return GET_CODE (x
);
3492 const char *Get_mode (rtx
);
3497 return GET_MODE_NAME (GET_MODE (x
));
3500 rtx
Xexp (rtx
, int);
3508 rtx
Xvecexp (rtx
, int, int);
3511 Xvecexp (rtx x
, int n
, int m
)
3513 return XVECEXP (x
, n
, m
);
3516 int Get_rtx_len (rtx
);
3521 return GET_RTX_LENGTH (GET_CODE (x
));
3524 /* Use upper-case to distinguish from local variables that are sometimes
3525 called next_insn and prev_insn. */
3527 rtx
Next_insn (rtx
);
3530 Next_insn (rtx insn
)
3532 return NEXT_INSN (insn
);
3535 rtx
Prev_insn (rtx
);
3538 Prev_insn (rtx insn
)
3540 return PREV_INSN (insn
);
3544 #include "gt-cris.h"
3548 * eval: (c-set-style "gnu")
3549 * indent-tabs-mode: t