1 /* { dg-do compile { target lp64 } } */
2 /* { dg-require-effective-target powerpc_p9vector_ok } */
3 /* { dg-require-effective-target float128 } */
4 /* { dg-options "-mpower9-vector -O2 -mabi=ieeelongdouble -Wno-psabi" } */
6 /* Insure that the ISA 3.0 IEEE 128-bit floating point built-in functions can
7 be used with long double when the default is IEEE 128-bit. */
10 #define TYPE long double
14 get_double_exponent (double a
)
16 return __builtin_vec_scalar_extract_exp (a
);
20 get_float128_exponent (TYPE a
)
22 return __builtin_vec_scalar_extract_exp (a
);
26 get_double_mantissa (double a
)
28 return __builtin_vec_scalar_extract_sig (a
);
32 get_float128_mantissa (TYPE a
)
34 return __builtin_vec_scalar_extract_sig (a
);
38 set_double_exponent_ulong (unsigned long a
, unsigned long e
)
40 return __builtin_vec_scalar_insert_exp (a
, e
);
44 set_float128_exponent_uint128 (__uint128_t a
, unsigned long e
)
46 return __builtin_vec_scalar_insert_exp (a
, e
);
50 set_double_exponent_double (double a
, unsigned long e
)
52 return __builtin_vec_scalar_insert_exp (a
, e
);
56 set_float128_exponent_float128 (TYPE a
, __uint128_t e
)
58 return __builtin_vec_scalar_insert_exp (a
, e
);
64 return __builtin_sqrtf128_round_to_odd (a
);
70 return __builtin_truncf128_round_to_odd (a
);
74 add_odd (TYPE a
, TYPE b
)
76 return __builtin_addf128_round_to_odd (a
, b
);
80 sub_odd (TYPE a
, TYPE b
)
82 return __builtin_subf128_round_to_odd (a
, b
);
86 mul_odd (TYPE a
, TYPE b
)
88 return __builtin_mulf128_round_to_odd (a
, b
);
92 div_odd (TYPE a
, TYPE b
)
94 return __builtin_divf128_round_to_odd (a
, b
);
98 fma_odd (TYPE a
, TYPE b
, TYPE c
)
100 return __builtin_fmaf128_round_to_odd (a
, b
, c
);
104 fms_odd (TYPE a
, TYPE b
, TYPE c
)
106 return __builtin_fmaf128_round_to_odd (a
, b
, -c
);
110 nfma_odd (TYPE a
, TYPE b
, TYPE c
)
112 return -__builtin_fmaf128_round_to_odd (a
, b
, c
);
116 nfms_odd (TYPE a
, TYPE b
, TYPE c
)
118 return -__builtin_fmaf128_round_to_odd (a
, b
, -c
);
121 /* { dg-final { scan-assembler {\mxsiexpdp\M} } } */
122 /* { dg-final { scan-assembler {\mxsiexpqp\M} } } */
123 /* { dg-final { scan-assembler {\mxsxexpdp\M} } } */
124 /* { dg-final { scan-assembler {\mxsxexpqp\M} } } */
125 /* { dg-final { scan-assembler {\mxsxsigdp\M} } } */
126 /* { dg-final { scan-assembler {\mxsxsigqp\M} } } */
127 /* { dg-final { scan-assembler {\mxsaddqpo\M} } } */
128 /* { dg-final { scan-assembler {\mxsdivqpo\M} } } */
129 /* { dg-final { scan-assembler {\mxsmaddqpo\M} } } */
130 /* { dg-final { scan-assembler {\mxsmsubqpo\M} } } */
131 /* { dg-final { scan-assembler {\mxsmulqpo\M} } } */
132 /* { dg-final { scan-assembler {\mxsnmaddqpo\M} } } */
133 /* { dg-final { scan-assembler {\mxsnmsubqpo\M} } } */
134 /* { dg-final { scan-assembler {\mxssqrtqpo\M} } } */
135 /* { dg-final { scan-assembler {\mxssubqpo\M} } } */
136 /* { dg-final { scan-assembler-not {\mbl\M} } } */