1 /* Test vneg works correctly. */
3 /* { dg-options "-std=gnu99 -O3 -Wno-div-by-zero --save-temps" } */
8 /* Used to force a variable to a SIMD register. Also acts as a stronger
9 inhibitor of optimization than the below - necessary for int64x1_t
10 because more of the implementation is in terms of gcc vector extensions
11 (which support constant propagation) than for other types. */
12 #define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \
16 #define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
32 extern void abort (void);
34 #define CONCAT(a, b) a##b
35 #define CONCAT1(a, b) CONCAT (a, b)
37 #define REG_INFEX128 q_
38 #define REG_INFEX(reg_len) REG_INFEX##reg_len
39 #define POSTFIX(reg_len, data_len) \
40 CONCAT1 (REG_INFEX (reg_len), s##data_len)
41 #define DATA_TYPE_32 float
42 #define DATA_TYPE_64 double
43 #define DATA_TYPE(data_len) DATA_TYPE_##data_len
45 #define FORCE_SIMD_INST64_8(data)
46 #define FORCE_SIMD_INST64_16(data)
47 #define FORCE_SIMD_INST64_32(data)
48 #define FORCE_SIMD_INST64_64(data) force_simd (data)
49 #define FORCE_SIMD_INST128_8(data)
50 #define FORCE_SIMD_INST128_16(data)
51 #define FORCE_SIMD_INST128_32(data)
52 #define FORCE_SIMD_INST128_64(data)
54 #define FORCE_SIMD_INST(reg_len, data_len, data) \
55 CONCAT1 (FORCE_SIMD_INST, reg_len##_##data_len) (data)
56 #define LOAD_INST(reg_len, data_len) \
57 CONCAT1 (vld1, POSTFIX (reg_len, data_len))
58 #define NEG_INST(reg_len, data_len) \
59 CONCAT1 (vneg, POSTFIX (reg_len, data_len))
61 #define RUN_TEST(test_set, answ_set, reg_len, data_len, n, a, b) \
65 (a) = LOAD_INST (reg_len, data_len) (test_set); \
66 (b) = LOAD_INST (reg_len, data_len) (answ_set); \
67 FORCE_SIMD_INST (reg_len, data_len, a) \
68 a = NEG_INST (reg_len, data_len) (a); \
69 FORCE_SIMD_INST (reg_len, data_len, a) \
70 for (i = 0; i < n; i++) \
84 int8_t test_set0
[8] = {
85 TEST0
, TEST1
, TEST2
, TEST3
, TEST4
, TEST5
, SCHAR_MAX
, SCHAR_MIN
87 int8_t answ_set0
[8] = {
88 ANSW0
, ANSW1
, ANSW2
, ANSW3
, ANSW4
, ANSW5
, SCHAR_MIN
+ 1, SCHAR_MIN
91 RUN_TEST (test_set0
, answ_set0
, 64, 8, 8, a
, b
);
96 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
104 int16_t test_set0
[4] = { TEST0
, TEST1
, TEST2
, TEST3
};
105 int16_t test_set1
[4] = { TEST4
, TEST5
, SHRT_MAX
, SHRT_MIN
};
107 int16_t answ_set0
[4] = { ANSW0
, ANSW1
, ANSW2
, ANSW3
};
108 int16_t answ_set1
[4] = { ANSW4
, ANSW5
, SHRT_MIN
+ 1, SHRT_MIN
};
110 RUN_TEST (test_set0
, answ_set0
, 64, 16, 4, a
, b
);
111 RUN_TEST (test_set1
, answ_set1
, 64, 16, 4, a
, b
);
116 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 2 } } */
124 int32_t test_set0
[2] = { TEST0
, TEST1
};
125 int32_t test_set1
[2] = { TEST2
, TEST3
};
126 int32_t test_set2
[2] = { TEST4
, TEST5
};
127 int32_t test_set3
[2] = { INT_MAX
, INT_MIN
};
129 int32_t answ_set0
[2] = { ANSW0
, ANSW1
};
130 int32_t answ_set1
[2] = { ANSW2
, ANSW3
};
131 int32_t answ_set2
[2] = { ANSW4
, ANSW5
};
132 int32_t answ_set3
[2] = { INT_MIN
+ 1, INT_MIN
};
134 RUN_TEST (test_set0
, answ_set0
, 64, 32, 2, a
, b
);
135 RUN_TEST (test_set1
, answ_set1
, 64, 32, 2, a
, b
);
136 RUN_TEST (test_set2
, answ_set2
, 64, 32, 2, a
, b
);
137 RUN_TEST (test_set3
, answ_set3
, 64, 32, 2, a
, b
);
142 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 4 } } */
150 int64_t test_set0
[1] = { TEST0
};
151 int64_t test_set1
[1] = { TEST1
};
152 int64_t test_set2
[1] = { TEST2
};
153 int64_t test_set3
[1] = { TEST3
};
154 int64_t test_set4
[1] = { TEST4
};
155 int64_t test_set5
[1] = { TEST5
};
156 int64_t test_set6
[1] = { LLONG_MAX
};
157 int64_t test_set7
[1] = { LLONG_MIN
};
159 int64_t answ_set0
[1] = { ANSW0
};
160 int64_t answ_set1
[1] = { ANSW1
};
161 int64_t answ_set2
[1] = { ANSW2
};
162 int64_t answ_set3
[1] = { ANSW3
};
163 int64_t answ_set4
[1] = { ANSW4
};
164 int64_t answ_set5
[1] = { ANSW5
};
165 int64_t answ_set6
[1] = { LLONG_MIN
+ 1 };
166 int64_t answ_set7
[1] = { LLONG_MIN
};
168 RUN_TEST (test_set0
, answ_set0
, 64, 64, 1, a
, b
);
169 RUN_TEST (test_set1
, answ_set1
, 64, 64, 1, a
, b
);
170 RUN_TEST (test_set2
, answ_set2
, 64, 64, 1, a
, b
);
171 RUN_TEST (test_set3
, answ_set3
, 64, 64, 1, a
, b
);
172 RUN_TEST (test_set4
, answ_set4
, 64, 64, 1, a
, b
);
173 RUN_TEST (test_set5
, answ_set5
, 64, 64, 1, a
, b
);
174 RUN_TEST (test_set6
, answ_set6
, 64, 64, 1, a
, b
);
175 RUN_TEST (test_set7
, answ_set7
, 64, 64, 1, a
, b
);
180 /* { dg-final { scan-assembler-times "neg\\td\[0-9\]+, d\[0-9\]+" 8 } } */
188 int8_t test_set0
[16] = {
189 TEST0
, TEST1
, TEST2
, TEST3
, TEST4
, TEST5
, SCHAR_MAX
, SCHAR_MIN
,
190 4, 8, 15, 16, 23, 42, -1, -2
193 int8_t answ_set0
[16] = {
194 ANSW0
, ANSW1
, ANSW2
, ANSW3
, ANSW4
, ANSW5
, SCHAR_MIN
+ 1, SCHAR_MIN
,
195 -4, -8, -15, -16, -23, -42, 1, 2
198 RUN_TEST (test_set0
, answ_set0
, 128, 8, 8, a
, b
);
203 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
211 int16_t test_set0
[8] = {
212 TEST0
, TEST1
, TEST2
, TEST3
, TEST4
, TEST5
, SHRT_MAX
, SHRT_MIN
214 int16_t answ_set0
[8] = {
215 ANSW0
, ANSW1
, ANSW2
, ANSW3
, ANSW4
, ANSW5
, SHRT_MIN
+ 1, SHRT_MIN
218 RUN_TEST (test_set0
, answ_set0
, 128, 16, 8, a
, b
);
223 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
231 int32_t test_set0
[4] = { TEST0
, TEST1
, TEST2
, TEST3
};
232 int32_t test_set1
[4] = { TEST4
, TEST5
, INT_MAX
, INT_MIN
};
234 int32_t answ_set0
[4] = { ANSW0
, ANSW1
, ANSW2
, ANSW3
};
235 int32_t answ_set1
[4] = { ANSW4
, ANSW5
, INT_MIN
+ 1, INT_MIN
};
237 RUN_TEST (test_set0
, answ_set0
, 128, 32, 4, a
, b
);
238 RUN_TEST (test_set1
, answ_set1
, 128, 32, 4, a
, b
);
243 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
251 int64_t test_set0
[2] = { TEST0
, TEST1
};
252 int64_t test_set1
[2] = { TEST2
, TEST3
};
253 int64_t test_set2
[2] = { TEST4
, TEST5
};
254 int64_t test_set3
[2] = { LLONG_MAX
, LLONG_MIN
};
256 int64_t answ_set0
[2] = { ANSW0
, ANSW1
};
257 int64_t answ_set1
[2] = { ANSW2
, ANSW3
};
258 int64_t answ_set2
[2] = { ANSW4
, ANSW5
};
259 int64_t answ_set3
[2] = { LLONG_MIN
+ 1, LLONG_MIN
};
261 RUN_TEST (test_set0
, answ_set0
, 128, 64, 2, a
, b
);
262 RUN_TEST (test_set1
, answ_set1
, 128, 64, 2, a
, b
);
263 RUN_TEST (test_set2
, answ_set2
, 128, 64, 2, a
, b
);
264 RUN_TEST (test_set3
, answ_set3
, 128, 64, 2, a
, b
);
269 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 4 } } */
272 main (int argc
, char **argv
)
277 if (test_vneg_s16 ())
280 if (test_vneg_s32 ())
283 if (test_vneg_s64 ())
286 if (test_vnegq_s8 ())
289 if (test_vnegq_s16 ())
292 if (test_vnegq_s32 ())
295 if (test_vnegq_s64 ())
301 /* { dg-final { cleanup-saved-temps } } */