[ARM,AArch64][testsuite] AdvSIMD intrinsics tests cleanup: remove useless expected...
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / advsimd-intrinsics / vtrn.c
blob2c4a09c1c4e00282db97e216438ff2248d6f7477
1 #include <arm_neon.h>
2 #include "arm-neon-ref.h"
3 #include "compute-ref-data.h"
5 /* Expected results splitted in several chunks. */
6 /* Chunk 0. */
7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11,
8 0xf2, 0xf3, 0x11, 0x11 };
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 };
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
12 0xf2, 0xf3, 0x55, 0x55 };
13 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
16 0xf2, 0xf3, 0x55, 0x55 };
17 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
18 VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
19 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11,
20 0xf2, 0xf3, 0x11, 0x11,
21 0xf4, 0xf5, 0x11, 0x11,
22 0xf6, 0xf7, 0x11, 0x11 };
23 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, 0x22, 0x22,
24 0xfff2, 0xfff3, 0x22, 0x22 };
25 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x33, 0x33 };
26 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
27 0xf2, 0xf3, 0x55, 0x55,
28 0xf4, 0xf5, 0x55, 0x55,
29 0xf6, 0xf7, 0x55, 0x55 };
30 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
31 0xfff2, 0xfff3, 0x66, 0x66 };
32 VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x77, 0x77 };
33 VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
34 0xf2, 0xf3, 0x55, 0x55,
35 0xf4, 0xf5, 0x55, 0x55,
36 0xf6, 0xf7, 0x55, 0x55 };
37 VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
38 0xfff2, 0xfff3, 0x66, 0x66 };
39 VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
40 0x42073333, 0x42073333 };
42 /* Chunk 1. */
43 VECT_VAR_DECL(expected1,int,8,8) [] = { 0xf4, 0xf5, 0x11, 0x11,
44 0xf6, 0xf7, 0x11, 0x11 };
45 VECT_VAR_DECL(expected1,int,16,4) [] = { 0xfff2, 0xfff3, 0x22, 0x22 };
46 VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 };
47 VECT_VAR_DECL(expected1,uint,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
48 0xf6, 0xf7, 0x55, 0x55 };
49 VECT_VAR_DECL(expected1,uint,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
50 VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
51 VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
52 0xf6, 0xf7, 0x55, 0x55 };
53 VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
54 VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
55 VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf8, 0xf9, 0x11, 0x11,
56 0xfa, 0xfb, 0x11, 0x11,
57 0xfc, 0xfd, 0x11, 0x11,
58 0xfe, 0xff, 0x11, 0x11 };
59 VECT_VAR_DECL(expected1,int,16,8) [] = { 0xfff4, 0xfff5, 0x22, 0x22,
60 0xfff6, 0xfff7, 0x22, 0x22 };
61 VECT_VAR_DECL(expected1,int,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x33, 0x33 };
62 VECT_VAR_DECL(expected1,uint,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
63 0xfa, 0xfb, 0x55, 0x55,
64 0xfc, 0xfd, 0x55, 0x55,
65 0xfe, 0xff, 0x55, 0x55 };
66 VECT_VAR_DECL(expected1,uint,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
67 0xfff6, 0xfff7, 0x66, 0x66 };
68 VECT_VAR_DECL(expected1,uint,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x77, 0x77 };
69 VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
70 0xfa, 0xfb, 0x55, 0x55,
71 0xfc, 0xfd, 0x55, 0x55,
72 0xfe, 0xff, 0x55, 0x55 };
73 VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
74 0xfff6, 0xfff7, 0x66, 0x66 };
75 VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1600000, 0xc1500000,
76 0x42073333, 0x42073333 };
78 #define INSN_NAME vtrn
79 #define TEST_MSG "VTRN/VTRNQ"
81 #include "vshuffle.inc"