1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Return 1 if ADDR is a valid memory address for mode MODE in address
321 space AS, and check that each pseudo has the proper kind of hard
324 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
325 rtx addr
, addr_space_t as
)
327 #ifdef GO_IF_LEGITIMATE_ADDRESS
328 lra_assert (ADDR_SPACE_GENERIC_P (as
));
329 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
335 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
340 /* Temporarily eliminates registers in an address (for the lifetime of
342 class address_eliminator
{
344 address_eliminator (struct address_info
*ad
);
345 ~address_eliminator ();
348 struct address_info
*m_ad
;
356 address_eliminator::address_eliminator (struct address_info
*ad
)
358 m_base_loc (strip_subreg (ad
->base_term
)),
359 m_base_reg (NULL_RTX
),
360 m_index_loc (strip_subreg (ad
->index_term
)),
361 m_index_reg (NULL_RTX
)
363 if (m_base_loc
!= NULL
)
365 m_base_reg
= *m_base_loc
;
366 lra_eliminate_reg_if_possible (m_base_loc
);
367 if (m_ad
->base_term2
!= NULL
)
368 *m_ad
->base_term2
= *m_ad
->base_term
;
370 if (m_index_loc
!= NULL
)
372 m_index_reg
= *m_index_loc
;
373 lra_eliminate_reg_if_possible (m_index_loc
);
377 address_eliminator::~address_eliminator ()
379 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
381 *m_base_loc
= m_base_reg
;
382 if (m_ad
->base_term2
!= NULL
)
383 *m_ad
->base_term2
= *m_ad
->base_term
;
385 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
386 *m_index_loc
= m_index_reg
;
389 /* Return true if the eliminated form of AD is a legitimate target address. */
391 valid_address_p (struct address_info
*ad
)
393 address_eliminator
eliminator (ad
);
394 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
397 #ifdef EXTRA_CONSTRAINT_STR
398 /* Return true if the eliminated form of memory reference OP satisfies
399 extra memory constraint CONSTRAINT. */
401 satisfies_memory_constraint_p (rtx op
, const char *constraint
)
403 struct address_info ad
;
405 decompose_mem_address (&ad
, op
);
406 address_eliminator
eliminator (&ad
);
407 return EXTRA_CONSTRAINT_STR (op
, *constraint
, constraint
);
410 /* Return true if the eliminated form of address AD satisfies extra
411 address constraint CONSTRAINT. */
413 satisfies_address_constraint_p (struct address_info
*ad
,
414 const char *constraint
)
416 address_eliminator
eliminator (ad
);
417 return EXTRA_CONSTRAINT_STR (*ad
->outer
, *constraint
, constraint
);
420 /* Return true if the eliminated form of address OP satisfies extra
421 address constraint CONSTRAINT. */
423 satisfies_address_constraint_p (rtx op
, const char *constraint
)
425 struct address_info ad
;
427 decompose_lea_address (&ad
, &op
);
428 return satisfies_address_constraint_p (&ad
, constraint
);
432 /* Initiate equivalences for LRA. As we keep original equivalences
433 before any elimination, we need to make copies otherwise any change
434 in insns might change the equivalences. */
436 lra_init_equiv (void)
438 ira_expand_reg_equiv ();
439 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
443 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
444 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
445 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
446 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
450 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
452 /* Update equivalence for REGNO. We need to this as the equivalence
453 might contain other pseudos which are changed by their
456 update_equiv (int regno
)
460 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
461 ira_reg_equiv
[regno
].memory
462 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
465 ira_reg_equiv
[regno
].invariant
466 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
470 /* If we have decided to substitute X with another value, return that
471 value, otherwise return X. */
478 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
479 || ! ira_reg_equiv
[regno
].defined_p
480 || ! ira_reg_equiv
[regno
].profitable_p
481 || lra_get_regno_hard_regno (regno
) >= 0)
483 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
487 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
492 /* If we have decided to substitute X with the equivalent value,
493 return that value after elimination for INSN, otherwise return
496 get_equiv_with_elimination (rtx x
, rtx insn
)
498 rtx res
= get_equiv (x
);
500 if (x
== res
|| CONSTANT_P (res
))
502 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
505 /* Set up curr_operand_mode. */
507 init_curr_operand_mode (void)
509 int nop
= curr_static_id
->n_operands
;
510 for (int i
= 0; i
< nop
; i
++)
512 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
513 if (mode
== VOIDmode
)
515 /* The .md mode for address operands is the mode of the
516 addressed value rather than the mode of the address itself. */
517 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
520 mode
= curr_static_id
->operand
[i
].mode
;
522 curr_operand_mode
[i
] = mode
;
528 /* The page contains code to reuse input reloads. */
530 /* Structure describes input reload of the current insns. */
533 /* Reloaded value. */
535 /* Reload pseudo used. */
539 /* The number of elements in the following array. */
540 static int curr_insn_input_reloads_num
;
541 /* Array containing info about input reloads. It is used to find the
542 same input reload and reuse the reload pseudo in this case. */
543 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
545 /* Initiate data concerning reuse of input reloads for the current
548 init_curr_insn_input_reloads (void)
550 curr_insn_input_reloads_num
= 0;
553 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
554 created input reload pseudo (only if TYPE is not OP_OUT). Don't
555 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
556 wrapped up in SUBREG. The result pseudo is returned through
557 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
558 reused the already created input reload pseudo. Use TITLE to
559 describe new registers for debug purposes. */
561 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
562 enum reg_class rclass
, bool in_subreg_p
,
563 const char *title
, rtx
*result_reg
)
566 enum reg_class new_class
;
571 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
574 /* Prevent reuse value of expression with side effects,
575 e.g. volatile memory. */
576 if (! side_effects_p (original
))
577 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
578 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
579 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
581 rtx reg
= curr_insn_input_reloads
[i
].reg
;
583 /* If input is equal to original and both are VOIDmode,
584 GET_MODE (reg) might be still different from mode.
585 Ensure we don't return *result_reg with wrong mode. */
586 if (GET_MODE (reg
) != mode
)
590 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
592 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
593 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
597 if (lra_dump_file
!= NULL
)
599 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
600 dump_value_slim (lra_dump_file
, original
, 1);
602 if (new_class
!= lra_get_allocno_class (regno
))
603 lra_change_class (regno
, new_class
, ", change to", false);
604 if (lra_dump_file
!= NULL
)
605 fprintf (lra_dump_file
, "\n");
608 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
609 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
610 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
611 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
617 /* The page contains code to extract memory address parts. */
619 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
621 ok_for_index_p_nonstrict (rtx reg
)
623 unsigned regno
= REGNO (reg
);
625 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
628 /* A version of regno_ok_for_base_p for use here, when all pseudos
629 should count as OK. Arguments as for regno_ok_for_base_p. */
631 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
632 enum rtx_code outer_code
, enum rtx_code index_code
)
634 unsigned regno
= REGNO (reg
);
636 if (regno
>= FIRST_PSEUDO_REGISTER
)
638 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
643 /* The page contains major code to choose the current insn alternative
644 and generate reloads for it. */
646 /* Return the offset from REGNO of the least significant register
649 This function is used to tell whether two registers satisfy
650 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
652 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
653 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
655 lra_constraint_offset (int regno
, enum machine_mode mode
)
657 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
658 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
659 && SCALAR_INT_MODE_P (mode
))
660 return hard_regno_nregs
[regno
][mode
] - 1;
664 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
665 if they are the same hard reg, and has special hacks for
666 auto-increment and auto-decrement. This is specifically intended for
667 process_alt_operands to use in determining whether two operands
668 match. X is the operand whose number is the lower of the two.
670 It is supposed that X is the output operand and Y is the input
671 operand. Y_HARD_REGNO is the final hard regno of register Y or
672 register in subreg Y as we know it now. Otherwise, it is a
675 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
678 RTX_CODE code
= GET_CODE (x
);
683 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
684 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
688 i
= get_hard_regno (x
);
692 if ((j
= y_hard_regno
) < 0)
695 i
+= lra_constraint_offset (i
, GET_MODE (x
));
696 j
+= lra_constraint_offset (j
, GET_MODE (y
));
701 /* If two operands must match, because they are really a single
702 operand of an assembler insn, then two post-increments are invalid
703 because the assembler insn would increment only once. On the
704 other hand, a post-increment matches ordinary indexing if the
705 post-increment is the output operand. */
706 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
707 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
709 /* Two pre-increments are invalid because the assembler insn would
710 increment only once. On the other hand, a pre-increment matches
711 ordinary indexing if the pre-increment is the input operand. */
712 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
713 || GET_CODE (y
) == PRE_MODIFY
)
714 return operands_match_p (x
, XEXP (y
, 0), -1);
718 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
719 && x
== SUBREG_REG (y
))
721 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
722 && SUBREG_REG (x
) == y
)
725 /* Now we have disposed of all the cases in which different rtx
727 if (code
!= GET_CODE (y
))
730 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
731 if (GET_MODE (x
) != GET_MODE (y
))
740 return XEXP (x
, 0) == XEXP (y
, 0);
742 return XSTR (x
, 0) == XSTR (y
, 0);
748 /* Compare the elements. If any pair of corresponding elements fail
749 to match, return false for the whole things. */
751 fmt
= GET_RTX_FORMAT (code
);
752 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
758 if (XWINT (x
, i
) != XWINT (y
, i
))
763 if (XINT (x
, i
) != XINT (y
, i
))
768 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
777 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
779 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
781 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
787 /* It is believed that rtx's at this level will never
788 contain anything but integers and other rtx's, except for
789 within LABEL_REFs and SYMBOL_REFs. */
797 /* True if X is a constant that can be forced into the constant pool.
798 MODE is the mode of the operand, or VOIDmode if not known. */
799 #define CONST_POOL_OK_P(MODE, X) \
800 ((MODE) != VOIDmode \
802 && GET_CODE (X) != HIGH \
803 && !targetm.cannot_force_const_mem (MODE, X))
805 /* True if C is a non-empty register class that has too few registers
806 to be safely used as a reload target class. */
807 #define SMALL_REGISTER_CLASS_P(C) \
808 (ira_class_hard_regs_num [(C)] == 1 \
809 || (ira_class_hard_regs_num [(C)] >= 1 \
810 && targetm.class_likely_spilled_p (C)))
812 /* If REG is a reload pseudo, try to make its class satisfying CL. */
814 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
816 enum reg_class rclass
;
818 /* Do not make more accurate class from reloads generated. They are
819 mostly moves with a lot of constraints. Making more accurate
820 class may results in very narrow class and impossibility of find
821 registers for several reloads of one insn. */
822 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
824 if (GET_CODE (reg
) == SUBREG
)
825 reg
= SUBREG_REG (reg
);
826 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
828 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
829 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
832 /* Generate reloads for matching OUT and INS (array of input operand
833 numbers with end marker -1) with reg class GOAL_CLASS. Add input
834 and output reloads correspondingly to the lists *BEFORE and *AFTER.
835 OUT might be negative. In this case we generate input reloads for
836 matched input operands INS. */
838 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
839 rtx
*before
, rtx
*after
)
842 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
843 enum machine_mode inmode
, outmode
;
844 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
845 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
847 inmode
= curr_operand_mode
[ins
[0]];
848 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
849 push_to_sequence (*before
);
850 if (inmode
!= outmode
)
852 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
855 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
857 if (SCALAR_INT_MODE_P (inmode
))
858 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
860 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
861 LRA_SUBREG_P (new_out_reg
) = 1;
862 /* If the input reg is dying here, we can use the same hard
863 register for REG and IN_RTX. We do it only for original
864 pseudos as reload pseudos can die although original
865 pseudos still live where reload pseudos dies. */
866 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
867 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
868 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
873 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
875 if (SCALAR_INT_MODE_P (outmode
))
876 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
878 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
879 /* NEW_IN_REG is non-paradoxical subreg. We don't want
880 NEW_OUT_REG living above. We add clobber clause for
881 this. This is just a temporary clobber. We can remove
882 it at the end of LRA work. */
883 clobber
= emit_clobber (new_out_reg
);
884 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
885 LRA_SUBREG_P (new_in_reg
) = 1;
886 if (GET_CODE (in_rtx
) == SUBREG
)
888 rtx subreg_reg
= SUBREG_REG (in_rtx
);
890 /* If SUBREG_REG is dying here and sub-registers IN_RTX
891 and NEW_IN_REG are similar, we can use the same hard
892 register for REG and SUBREG_REG. */
893 if (REG_P (subreg_reg
)
894 && (int) REGNO (subreg_reg
) < lra_new_regno_start
895 && GET_MODE (subreg_reg
) == outmode
896 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
897 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
898 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
904 /* Pseudos have values -- see comments for lra_reg_info.
905 Different pseudos with the same value do not conflict even if
906 they live in the same place. When we create a pseudo we
907 assign value of original pseudo (if any) from which we
908 created the new pseudo. If we create the pseudo from the
909 input pseudo, the new pseudo will no conflict with the input
910 pseudo which is wrong when the input pseudo lives after the
911 insn and as the new pseudo value is changed by the insn
912 output. Therefore we create the new pseudo from the output.
914 We cannot reuse the current output register because we might
915 have a situation like "a <- a op b", where the constraints
916 force the second input operand ("b") to match the output
917 operand ("a"). "b" must then be copied into a new register
918 so that it doesn't clobber the current value of "a". */
920 new_in_reg
= new_out_reg
921 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
924 /* In operand can be got from transformations before processing insn
925 constraints. One example of such transformations is subreg
926 reloading (see function simplify_operand_subreg). The new
927 pseudos created by the transformations might have inaccurate
928 class (ALL_REGS) and we should make their classes more
930 narrow_reload_pseudo_class (in_rtx
, goal_class
);
931 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
932 *before
= get_insns ();
934 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
937 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
938 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
939 *curr_id
->operand_loc
[in
] = new_in_reg
;
941 lra_update_dups (curr_id
, ins
);
944 /* See a comment for the input operand above. */
945 narrow_reload_pseudo_class (out_rtx
, goal_class
);
946 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
949 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
951 *after
= get_insns ();
954 *curr_id
->operand_loc
[out
] = new_out_reg
;
955 lra_update_dup (curr_id
, out
);
958 /* Return register class which is union of all reg classes in insn
959 constraint alternative string starting with P. */
960 static enum reg_class
961 reg_class_from_constraints (const char *p
)
964 enum reg_class op_class
= NO_REGS
;
967 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
974 op_class
= (reg_class_subunion
975 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
981 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
985 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
987 #ifdef EXTRA_CONSTRAINT_STR
988 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
990 = (reg_class_subunion
991 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
998 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1001 while ((p
+= len
), c
);
1005 /* If OP is a register, return the class of the register as per
1006 get_reg_class, otherwise return NO_REGS. */
1007 static inline enum reg_class
1008 get_op_class (rtx op
)
1010 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1013 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1014 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1015 SUBREG for VAL to make them equal. */
1017 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1019 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1021 /* Usually size of mem_pseudo is greater than val size but in
1022 rare cases it can be less as it can be defined by target
1023 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1026 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1027 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1029 LRA_SUBREG_P (val
) = 1;
1033 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1034 LRA_SUBREG_P (mem_pseudo
) = 1;
1038 ? gen_move_insn (mem_pseudo
, val
)
1039 : gen_move_insn (val
, mem_pseudo
));
1042 /* Process a special case insn (register move), return true if we
1043 don't need to process it anymore. INSN should be a single set
1044 insn. Set up that RTL was changed through CHANGE_P and macro
1045 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1048 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1051 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
1052 enum reg_class dclass
, sclass
, secondary_class
;
1053 enum machine_mode sreg_mode
;
1054 secondary_reload_info sri
;
1056 lra_assert (curr_insn_set
!= NULL_RTX
);
1057 dreg
= dest
= SET_DEST (curr_insn_set
);
1058 sreg
= src
= SET_SRC (curr_insn_set
);
1059 if (GET_CODE (dest
) == SUBREG
)
1060 dreg
= SUBREG_REG (dest
);
1061 if (GET_CODE (src
) == SUBREG
)
1062 sreg
= SUBREG_REG (src
);
1063 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1065 sclass
= dclass
= NO_REGS
;
1067 dclass
= get_reg_class (REGNO (dreg
));
1068 if (dclass
== ALL_REGS
)
1069 /* ALL_REGS is used for new pseudos created by transformations
1070 like reload of SUBREG_REG (see function
1071 simplify_operand_subreg). We don't know their class yet. We
1072 should figure out the class from processing the insn
1073 constraints not in this fast path function. Even if ALL_REGS
1074 were a right class for the pseudo, secondary_... hooks usually
1075 are not define for ALL_REGS. */
1077 sreg_mode
= GET_MODE (sreg
);
1080 sclass
= get_reg_class (REGNO (sreg
));
1081 if (sclass
== ALL_REGS
)
1082 /* See comments above. */
1084 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1086 #ifdef SECONDARY_MEMORY_NEEDED
1087 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1088 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1089 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1090 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1098 if (! REG_P (dreg
) || ! REG_P (sreg
))
1100 sri
.prev_sri
= NULL
;
1101 sri
.icode
= CODE_FOR_nothing
;
1103 secondary_class
= NO_REGS
;
1104 /* Set up hard register for a reload pseudo for hook
1105 secondary_reload because some targets just ignore unassigned
1106 pseudos in the hook. */
1107 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1109 dregno
= REGNO (dreg
);
1110 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1114 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1116 sregno
= REGNO (sreg
);
1117 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1121 if (sclass
!= NO_REGS
)
1123 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1124 (reg_class_t
) sclass
,
1125 GET_MODE (src
), &sri
);
1126 if (sclass
== NO_REGS
1127 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1128 && dclass
!= NO_REGS
))
1130 enum reg_class old_sclass
= secondary_class
;
1131 secondary_reload_info old_sri
= sri
;
1133 sri
.prev_sri
= NULL
;
1134 sri
.icode
= CODE_FOR_nothing
;
1137 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1138 (reg_class_t
) dclass
,
1140 /* Check the target hook consistency. */
1142 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1143 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1144 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1147 reg_renumber
[sregno
] = -1;
1149 reg_renumber
[dregno
] = -1;
1150 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1154 if (secondary_class
!= NO_REGS
)
1155 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1159 if (old_sreg
!= sreg
)
1160 sreg
= copy_rtx (sreg
);
1161 if (sri
.icode
== CODE_FOR_nothing
)
1162 lra_emit_move (new_reg
, sreg
);
1165 enum reg_class scratch_class
;
1167 scratch_class
= (reg_class_from_constraints
1168 (insn_data
[sri
.icode
].operand
[2].constraint
));
1169 scratch_reg
= (lra_create_new_reg_with_unique_value
1170 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1171 scratch_class
, "scratch"));
1172 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1173 sreg
, scratch_reg
));
1175 before
= get_insns ();
1177 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1178 if (new_reg
!= NULL_RTX
)
1180 if (GET_CODE (src
) == SUBREG
)
1181 SUBREG_REG (src
) = new_reg
;
1183 SET_SRC (curr_insn_set
) = new_reg
;
1187 if (lra_dump_file
!= NULL
)
1189 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1190 dump_insn_slim (lra_dump_file
, curr_insn
);
1192 lra_set_insn_deleted (curr_insn
);
1198 /* The following data describe the result of process_alt_operands.
1199 The data are used in curr_insn_transform to generate reloads. */
1201 /* The chosen reg classes which should be used for the corresponding
1203 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1204 /* True if the operand should be the same as another operand and that
1205 other operand does not need a reload. */
1206 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1207 /* True if the operand does not need a reload. */
1208 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1209 /* True if the operand can be offsetable memory. */
1210 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1211 /* The number of an operand to which given operand can be matched to. */
1212 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1213 /* The number of elements in the following array. */
1214 static int goal_alt_dont_inherit_ops_num
;
1215 /* Numbers of operands whose reload pseudos should not be inherited. */
1216 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1217 /* True if the insn commutative operands should be swapped. */
1218 static bool goal_alt_swapped
;
1219 /* The chosen insn alternative. */
1220 static int goal_alt_number
;
1222 /* The following five variables are used to choose the best insn
1223 alternative. They reflect final characteristics of the best
1226 /* Number of necessary reloads and overall cost reflecting the
1227 previous value and other unpleasantness of the best alternative. */
1228 static int best_losers
, best_overall
;
1229 /* Overall number hard registers used for reloads. For example, on
1230 some targets we need 2 general registers to reload DFmode and only
1231 one floating point register. */
1232 static int best_reload_nregs
;
1233 /* Overall number reflecting distances of previous reloading the same
1234 value. The distances are counted from the current BB start. It is
1235 used to improve inheritance chances. */
1236 static int best_reload_sum
;
1238 /* True if the current insn should have no correspondingly input or
1240 static bool no_input_reloads_p
, no_output_reloads_p
;
1242 /* True if we swapped the commutative operands in the current
1244 static int curr_swapped
;
1246 /* Arrange for address element *LOC to be a register of class CL.
1247 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1248 automodified value; handle that case by adding the required output
1249 reloads to list AFTER. Return true if the RTL was changed. */
1251 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1254 enum reg_class rclass
, new_class
;
1257 enum machine_mode mode
;
1258 bool subreg_p
, before_p
= false;
1260 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1262 loc
= &SUBREG_REG (*loc
);
1264 mode
= GET_MODE (reg
);
1267 /* Always reload memory in an address even if the target supports
1269 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1274 regno
= REGNO (reg
);
1275 rclass
= get_reg_class (regno
);
1276 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1278 if (lra_dump_file
!= NULL
)
1280 fprintf (lra_dump_file
,
1281 "Changing pseudo %d in address of insn %u on equiv ",
1282 REGNO (reg
), INSN_UID (curr_insn
));
1283 dump_value_slim (lra_dump_file
, *loc
, 1);
1284 fprintf (lra_dump_file
, "\n");
1286 *loc
= copy_rtx (*loc
);
1288 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1291 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1292 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1295 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1297 lra_change_class (regno
, new_class
, " Change to", true);
1305 push_to_sequence (*before
);
1306 lra_emit_move (new_reg
, reg
);
1307 *before
= get_insns ();
1314 lra_emit_move (reg
, new_reg
);
1316 *after
= get_insns ();
1322 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1323 the insn to be inserted before curr insn. AFTER returns the
1324 the insn to be inserted after curr insn. ORIGREG and NEWREG
1325 are the original reg and new reg for reload. */
1327 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1331 push_to_sequence (*before
);
1332 lra_emit_move (newreg
, origreg
);
1333 *before
= get_insns ();
1339 lra_emit_move (origreg
, newreg
);
1341 *after
= get_insns ();
1346 /* Make reloads for subreg in operand NOP with internal subreg mode
1347 REG_MODE, add new reloads for further processing. Return true if
1348 any reload was generated. */
1350 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1354 enum machine_mode mode
;
1356 rtx operand
= *curr_id
->operand_loc
[nop
];
1357 enum reg_class regclass
;
1360 before
= after
= NULL_RTX
;
1362 if (GET_CODE (operand
) != SUBREG
)
1365 mode
= GET_MODE (operand
);
1366 reg
= SUBREG_REG (operand
);
1367 type
= curr_static_id
->operand
[nop
].type
;
1368 /* If we change address for paradoxical subreg of memory, the
1369 address might violate the necessary alignment or the access might
1370 be slow. So take this into consideration. We should not worry
1371 about access beyond allocated memory for paradoxical memory
1372 subregs as we don't substitute such equiv memory (see processing
1373 equivalences in function lra_constraints) and because for spilled
1374 pseudos we allocate stack memory enough for the biggest
1375 corresponding paradoxical subreg. */
1377 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1378 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1379 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1381 alter_subreg (curr_id
->operand_loc
[nop
], false);
1384 /* Put constant into memory when we have mixed modes. It generates
1385 a better code in most cases as it does not need a secondary
1386 reload memory. It also prevents LRA looping when LRA is using
1387 secondary reload memory again and again. */
1388 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1389 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1391 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1392 alter_subreg (curr_id
->operand_loc
[nop
], false);
1395 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1396 if there may be a problem accessing OPERAND in the outer
1399 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1400 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1401 /* Don't reload paradoxical subregs because we could be looping
1402 having repeatedly final regno out of hard regs range. */
1403 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1404 >= hard_regno_nregs
[hard_regno
][mode
])
1405 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1406 SUBREG_BYTE (operand
), mode
) < 0
1407 /* Don't reload subreg for matching reload. It is actually
1408 valid subreg in LRA. */
1409 && ! LRA_SUBREG_P (operand
))
1410 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1412 enum reg_class rclass
;
1415 /* There is a big probability that we will get the same class
1416 for the new pseudo and we will get the same insn which
1417 means infinite looping. So spill the new pseudo. */
1420 /* The class will be defined later in curr_insn_transform. */
1422 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1424 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1425 rclass
, TRUE
, "subreg reg", &new_reg
))
1427 bool insert_before
, insert_after
;
1428 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1430 insert_before
= (type
!= OP_OUT
1431 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1432 insert_after
= (type
!= OP_IN
);
1433 insert_move_for_subreg (insert_before
? &before
: NULL
,
1434 insert_after
? &after
: NULL
,
1437 SUBREG_REG (operand
) = new_reg
;
1438 lra_process_new_insns (curr_insn
, before
, after
,
1439 "Inserting subreg reload");
1442 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1443 IRA allocates hardreg to the inner pseudo reg according to its mode
1444 instead of the outermode, so the size of the hardreg may not be enough
1445 to contain the outermode operand, in that case we may need to insert
1446 reload for the reg. For the following two types of paradoxical subreg,
1447 we need to insert reload:
1448 1. If the op_type is OP_IN, and the hardreg could not be paired with
1449 other hardreg to contain the outermode operand
1450 (checked by in_hard_reg_set_p), we need to insert the reload.
1451 2. If the op_type is OP_OUT or OP_INOUT.
1453 Here is a paradoxical subreg example showing how the reload is generated:
1455 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1456 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1458 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1459 here, if reg107 is assigned to hardreg R15, because R15 is the last
1460 hardreg, compiler cannot find another hardreg to pair with R15 to
1461 contain TImode data. So we insert a TImode reload reg180 for it.
1462 After reload is inserted:
1464 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1465 (reg:DI 107 [ __comp ])) -1
1466 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1467 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1469 Two reload hard registers will be allocated to reg180 to save TImode data
1471 else if (REG_P (reg
)
1472 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1473 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1474 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1475 < hard_regno_nregs
[hard_regno
][mode
])
1476 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1478 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1481 /* The class will be defined later in curr_insn_transform. */
1482 enum reg_class rclass
1483 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1485 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1486 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1489 bool insert_before
, insert_after
;
1491 PUT_MODE (new_reg
, mode
);
1492 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1493 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1495 insert_before
= (type
!= OP_OUT
);
1496 insert_after
= (type
!= OP_IN
);
1497 insert_move_for_subreg (insert_before
? &before
: NULL
,
1498 insert_after
? &after
: NULL
,
1501 SUBREG_REG (operand
) = new_reg
;
1502 lra_process_new_insns (curr_insn
, before
, after
,
1503 "Inserting paradoxical subreg reload");
1509 /* Return TRUE if X refers for a hard register from SET. */
1511 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1513 int i
, j
, x_hard_regno
;
1514 enum machine_mode mode
;
1520 code
= GET_CODE (x
);
1521 mode
= GET_MODE (x
);
1525 code
= GET_CODE (x
);
1526 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1527 mode
= GET_MODE (x
);
1532 x_hard_regno
= get_hard_regno (x
);
1533 return (x_hard_regno
>= 0
1534 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1538 struct address_info ad
;
1540 decompose_mem_address (&ad
, x
);
1541 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1543 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1546 fmt
= GET_RTX_FORMAT (code
);
1547 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1551 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1554 else if (fmt
[i
] == 'E')
1556 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1557 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1564 /* Return true if OP is a spilled pseudo. */
1566 spilled_pseudo_p (rtx op
)
1569 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1572 /* Return true if X is a general constant. */
1574 general_constant_p (rtx x
)
1576 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1580 reg_in_class_p (rtx reg
, enum reg_class cl
)
1583 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1584 return in_class_p (reg
, cl
, NULL
);
1587 /* Major function to choose the current insn alternative and what
1588 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1589 negative we should consider only this alternative. Return false if
1590 we can not choose the alternative or find how to reload the
1593 process_alt_operands (int only_alternative
)
1596 int nop
, overall
, nalt
;
1597 int n_alternatives
= curr_static_id
->n_alternatives
;
1598 int n_operands
= curr_static_id
->n_operands
;
1599 /* LOSERS counts the operands that don't fit this alternative and
1600 would require loading. */
1602 /* REJECT is a count of how undesirable this alternative says it is
1603 if any reloading is required. If the alternative matches exactly
1604 then REJECT is ignored, but otherwise it gets this much counted
1605 against it in addition to the reloading needed. */
1607 /* The number of elements in the following array. */
1608 int early_clobbered_regs_num
;
1609 /* Numbers of operands which are early clobber registers. */
1610 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1611 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1612 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1613 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1614 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1615 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1616 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1617 /* The number of elements in the following array. */
1618 int curr_alt_dont_inherit_ops_num
;
1619 /* Numbers of operands whose reload pseudos should not be inherited. */
1620 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1622 /* The register when the operand is a subreg of register, otherwise the
1624 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1625 /* The register if the operand is a register or subreg of register,
1627 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1628 int hard_regno
[MAX_RECOG_OPERANDS
];
1629 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1630 int reload_nregs
, reload_sum
;
1634 /* Calculate some data common for all alternatives to speed up the
1636 for (nop
= 0; nop
< n_operands
; nop
++)
1640 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1641 /* The real hard regno of the operand after the allocation. */
1642 hard_regno
[nop
] = get_hard_regno (op
);
1644 operand_reg
[nop
] = reg
= op
;
1645 biggest_mode
[nop
] = GET_MODE (op
);
1646 if (GET_CODE (op
) == SUBREG
)
1648 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1649 if (GET_MODE_SIZE (biggest_mode
[nop
])
1650 < GET_MODE_SIZE (GET_MODE (reg
)))
1651 biggest_mode
[nop
] = GET_MODE (reg
);
1654 operand_reg
[nop
] = NULL_RTX
;
1655 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1656 || ((int) REGNO (reg
)
1657 == lra_get_elimination_hard_regno (REGNO (reg
))))
1658 no_subreg_reg_operand
[nop
] = reg
;
1660 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1661 /* Just use natural mode for elimination result. It should
1662 be enough for extra constraints hooks. */
1663 = regno_reg_rtx
[hard_regno
[nop
]];
1666 /* The constraints are made of several alternatives. Each operand's
1667 constraint looks like foo,bar,... with commas separating the
1668 alternatives. The first alternatives for all operands go
1669 together, the second alternatives go together, etc.
1671 First loop over alternatives. */
1672 alternative_mask enabled
= curr_id
->enabled_alternatives
;
1673 if (only_alternative
>= 0)
1674 enabled
&= ALTERNATIVE_BIT (only_alternative
);
1676 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1678 /* Loop over operands for one constraint alternative. */
1679 if (!TEST_BIT (enabled
, nalt
))
1682 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1683 for (nop
= 0; nop
< n_operands
; nop
++)
1685 int inc
= (curr_static_id
1686 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1687 if (lra_dump_file
!= NULL
&& inc
!= 0)
1688 fprintf (lra_dump_file
,
1689 " Staticly defined alt reject+=%d\n", inc
);
1692 early_clobbered_regs_num
= 0;
1694 for (nop
= 0; nop
< n_operands
; nop
++)
1698 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1699 bool win
, did_match
, offmemok
, early_clobber_p
;
1700 /* false => this operand can be reloaded somehow for this
1703 /* true => this operand can be reloaded if the alternative
1706 /* True if a constant forced into memory would be OK for
1709 enum reg_class this_alternative
, this_costly_alternative
;
1710 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1711 bool this_alternative_match_win
, this_alternative_win
;
1712 bool this_alternative_offmemok
;
1714 enum machine_mode mode
;
1716 opalt_num
= nalt
* n_operands
+ nop
;
1717 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1719 /* Fast track for no constraints at all. */
1720 curr_alt
[nop
] = NO_REGS
;
1721 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1722 curr_alt_win
[nop
] = true;
1723 curr_alt_match_win
[nop
] = false;
1724 curr_alt_offmemok
[nop
] = false;
1725 curr_alt_matches
[nop
] = -1;
1729 op
= no_subreg_reg_operand
[nop
];
1730 mode
= curr_operand_mode
[nop
];
1732 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1735 early_clobber_p
= false;
1736 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1738 this_costly_alternative
= this_alternative
= NO_REGS
;
1739 /* We update set of possible hard regs besides its class
1740 because reg class might be inaccurate. For example,
1741 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1742 is translated in HI_REGS because classes are merged by
1743 pairs and there is no accurate intermediate class. */
1744 CLEAR_HARD_REG_SET (this_alternative_set
);
1745 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1746 this_alternative_win
= false;
1747 this_alternative_match_win
= false;
1748 this_alternative_offmemok
= false;
1749 this_alternative_matches
= -1;
1751 /* An empty constraint should be excluded by the fast
1753 lra_assert (*p
!= 0 && *p
!= ',');
1755 /* Scan this alternative's specs for this operand; set WIN
1756 if the operand fits any letter in this alternative.
1757 Otherwise, clear BADOP if this operand could fit some
1758 letter after reloads, or set WINREG if this operand could
1759 fit after reloads provided the constraint allows some
1764 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1773 case '=': case '+': case '?': case '*': case '!':
1774 case ' ': case '\t':
1778 /* We only support one commutative marker, the first
1779 one. We already set commutative above. */
1783 early_clobber_p
= true;
1787 /* Ignore rest of this alternative. */
1791 case '0': case '1': case '2': case '3': case '4':
1792 case '5': case '6': case '7': case '8': case '9':
1797 m
= strtoul (p
, &end
, 10);
1800 lra_assert (nop
> m
);
1802 this_alternative_matches
= m
;
1803 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1804 /* We are supposed to match a previous operand.
1805 If we do, we win if that one did. If we do
1806 not, count both of the operands as losers.
1807 (This is too conservative, since most of the
1808 time only a single reload insn will be needed
1809 to make the two operands win. As a result,
1810 this alternative may be rejected when it is
1811 actually desirable.) */
1813 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1814 *curr_id
->operand_loc
[m
], m_hregno
))
1816 /* We should reject matching of an early
1817 clobber operand if the matching operand is
1818 not dying in the insn. */
1819 if (! curr_static_id
->operand
[m
].early_clobber
1820 || operand_reg
[nop
] == NULL_RTX
1821 || (find_regno_note (curr_insn
, REG_DEAD
,
1823 || REGNO (op
) == REGNO (operand_reg
[m
])))
1828 /* If we are matching a non-offsettable
1829 address where an offsettable address was
1830 expected, then we must reject this
1831 combination, because we can't reload
1833 if (curr_alt_offmemok
[m
]
1834 && MEM_P (*curr_id
->operand_loc
[m
])
1835 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1840 /* Operands don't match. Both operands must
1841 allow a reload register, otherwise we
1842 cannot make them match. */
1843 if (curr_alt
[m
] == NO_REGS
)
1845 /* Retroactively mark the operand we had to
1846 match as a loser, if it wasn't already and
1847 it wasn't matched to a register constraint
1848 (e.g it might be matched by memory). */
1850 && (operand_reg
[m
] == NULL_RTX
1851 || hard_regno
[m
] < 0))
1855 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1856 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1859 /* Prefer matching earlyclobber alternative as
1860 it results in less hard regs required for
1861 the insn than a non-matching earlyclobber
1863 if (curr_static_id
->operand
[m
].early_clobber
)
1865 if (lra_dump_file
!= NULL
)
1868 " %d Matching earlyclobber alt:"
1873 /* Otherwise we prefer no matching
1874 alternatives because it gives more freedom
1876 else if (operand_reg
[nop
] == NULL_RTX
1877 || (find_regno_note (curr_insn
, REG_DEAD
,
1878 REGNO (operand_reg
[nop
]))
1881 if (lra_dump_file
!= NULL
)
1884 " %d Matching alt: reject+=2\n",
1889 /* If we have to reload this operand and some
1890 previous operand also had to match the same
1891 thing as this operand, we don't know how to do
1893 if (!match_p
|| !curr_alt_win
[m
])
1895 for (i
= 0; i
< nop
; i
++)
1896 if (curr_alt_matches
[i
] == m
)
1904 /* This can be fixed with reloads if the operand
1905 we are supposed to match can be fixed with
1908 this_alternative
= curr_alt
[m
];
1909 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1910 winreg
= this_alternative
!= NO_REGS
;
1915 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1917 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1918 IOR_HARD_REG_SET (this_alternative_set
,
1919 reg_class_contents
[cl
]);
1922 this_costly_alternative
1923 = reg_class_subunion
[this_costly_alternative
][cl
];
1924 IOR_HARD_REG_SET (this_costly_alternative_set
,
1925 reg_class_contents
[cl
]);
1931 case TARGET_MEM_CONSTRAINT
:
1932 if (MEM_P (op
) || spilled_pseudo_p (op
))
1934 /* We can put constant or pseudo value into memory
1935 to satisfy the constraint. */
1936 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1943 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1944 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1950 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1951 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1955 /* Memory op whose address is not offsettable. */
1958 && ! offsettable_nonstrict_memref_p (op
))
1962 /* Memory operand whose address is offsettable. */
1965 && offsettable_nonstrict_memref_p (op
))
1966 || spilled_pseudo_p (op
))
1968 /* We can put constant or pseudo value into memory
1969 or make memory address offsetable to satisfy the
1971 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1979 if (GET_CODE (op
) == CONST_DOUBLE
1980 || (GET_CODE (op
) == CONST_VECTOR
1981 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1987 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1988 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1993 if (CONST_SCALAR_INT_P (op
))
1997 if (general_constant_p (op
))
2002 if (CONST_SCALAR_INT_P (op
))
2014 if (CONST_INT_P (op
)
2015 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2020 /* This constraint should be excluded by the fast
2027 || general_constant_p (op
)
2028 || spilled_pseudo_p (op
))
2030 /* Drop through into 'r' case. */
2034 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
2035 IOR_HARD_REG_SET (this_alternative_set
,
2036 reg_class_contents
[GENERAL_REGS
]);
2039 this_costly_alternative
2040 = (reg_class_subunion
2041 [this_costly_alternative
][GENERAL_REGS
]);
2042 IOR_HARD_REG_SET (this_costly_alternative_set
,
2043 reg_class_contents
[GENERAL_REGS
]);
2048 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
2050 #ifdef EXTRA_CONSTRAINT_STR
2051 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2054 && satisfies_memory_constraint_p (op
, p
))
2056 else if (spilled_pseudo_p (op
))
2059 /* If we didn't already win, we can reload
2060 constants via force_const_mem or put the
2061 pseudo value into memory, or make other
2062 memory by reloading the address like for
2064 if (CONST_POOL_OK_P (mode
, op
)
2065 || MEM_P (op
) || REG_P (op
))
2071 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2073 if (satisfies_address_constraint_p (op
, p
))
2076 /* If we didn't already win, we can reload
2077 the address into a base register. */
2078 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2081 = reg_class_subunion
[this_alternative
][cl
];
2082 IOR_HARD_REG_SET (this_alternative_set
,
2083 reg_class_contents
[cl
]);
2086 this_costly_alternative
2087 = (reg_class_subunion
2088 [this_costly_alternative
][cl
]);
2089 IOR_HARD_REG_SET (this_costly_alternative_set
,
2090 reg_class_contents
[cl
]);
2096 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2102 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
2103 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2104 IOR_HARD_REG_SET (this_alternative_set
,
2105 reg_class_contents
[cl
]);
2108 this_costly_alternative
2109 = reg_class_subunion
[this_costly_alternative
][cl
];
2110 IOR_HARD_REG_SET (this_costly_alternative_set
,
2111 reg_class_contents
[cl
]);
2114 if (mode
== BLKmode
)
2119 if (hard_regno
[nop
] >= 0
2120 && in_hard_reg_set_p (this_alternative_set
,
2121 mode
, hard_regno
[nop
]))
2123 else if (hard_regno
[nop
] < 0
2124 && in_class_p (op
, this_alternative
, NULL
))
2129 if (c
!= ' ' && c
!= '\t')
2130 costly_p
= c
== '*';
2132 while ((p
+= len
), c
);
2134 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2135 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2136 /* Record which operands fit this alternative. */
2139 this_alternative_win
= true;
2140 if (operand_reg
[nop
] != NULL_RTX
)
2142 if (hard_regno
[nop
] >= 0)
2144 if (in_hard_reg_set_p (this_costly_alternative_set
,
2145 mode
, hard_regno
[nop
]))
2147 if (lra_dump_file
!= NULL
)
2148 fprintf (lra_dump_file
,
2149 " %d Costly set: reject++\n",
2156 /* Prefer won reg to spilled pseudo under other
2157 equal conditions for possibe inheritance. */
2160 if (lra_dump_file
!= NULL
)
2163 " %d Non pseudo reload: reject++\n",
2167 if (in_class_p (operand_reg
[nop
],
2168 this_costly_alternative
, NULL
))
2170 if (lra_dump_file
!= NULL
)
2173 " %d Non pseudo costly reload:"
2179 /* We simulate the behaviour of old reload here.
2180 Although scratches need hard registers and it
2181 might result in spilling other pseudos, no reload
2182 insns are generated for the scratches. So it
2183 might cost something but probably less than old
2184 reload pass believes. */
2187 if (lra_dump_file
!= NULL
)
2188 fprintf (lra_dump_file
,
2189 " %d Scratch win: reject+=2\n",
2196 this_alternative_match_win
= true;
2199 int const_to_mem
= 0;
2202 /* Never do output reload of stack pointer. It makes
2203 impossible to do elimination when SP is changed in
2205 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2206 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2209 /* If this alternative asks for a specific reg class, see if there
2210 is at least one allocatable register in that class. */
2212 = (this_alternative
== NO_REGS
2213 || (hard_reg_set_subset_p
2214 (reg_class_contents
[this_alternative
],
2215 lra_no_alloc_regs
)));
2217 /* For asms, verify that the class for this alternative is possible
2218 for the mode that is specified. */
2219 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2222 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2223 if (HARD_REGNO_MODE_OK (i
, mode
)
2224 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2227 if (i
== FIRST_PSEUDO_REGISTER
)
2231 /* If this operand accepts a register, and if the
2232 register class has at least one allocatable register,
2233 then this operand can be reloaded. */
2234 if (winreg
&& !no_regs_p
)
2239 if (lra_dump_file
!= NULL
)
2240 fprintf (lra_dump_file
,
2241 " alt=%d: Bad operand -- refuse\n",
2246 /* If not assigned pseudo has a class which a subset of
2247 required reg class, it is a less costly alternative
2248 as the pseudo still can get a hard reg of necessary
2250 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2251 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2252 && ira_class_subset_p
[this_alternative
][cl
])
2254 if (lra_dump_file
!= NULL
)
2257 " %d Super set class reg: reject-=3\n", nop
);
2261 this_alternative_offmemok
= offmemok
;
2262 if (this_costly_alternative
!= NO_REGS
)
2264 if (lra_dump_file
!= NULL
)
2265 fprintf (lra_dump_file
,
2266 " %d Costly loser: reject++\n", nop
);
2269 /* If the operand is dying, has a matching constraint,
2270 and satisfies constraints of the matched operand
2271 which failed to satisfy the own constraints, most probably
2272 the reload for this operand will be gone. */
2273 if (this_alternative_matches
>= 0
2274 && !curr_alt_win
[this_alternative_matches
]
2276 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2277 && (hard_regno
[nop
] >= 0
2278 ? in_hard_reg_set_p (this_alternative_set
,
2279 mode
, hard_regno
[nop
])
2280 : in_class_p (op
, this_alternative
, NULL
)))
2282 if (lra_dump_file
!= NULL
)
2285 " %d Dying matched operand reload: reject++\n",
2291 /* Strict_low_part requires to reload the register
2292 not the sub-register. In this case we should
2293 check that a final reload hard reg can hold the
2295 if (curr_static_id
->operand
[nop
].strict_low
2297 && hard_regno
[nop
] < 0
2298 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2299 && ira_class_hard_regs_num
[this_alternative
] > 0
2300 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2301 [this_alternative
][0],
2303 (*curr_id
->operand_loc
[nop
])))
2305 if (lra_dump_file
!= NULL
)
2308 " alt=%d: Strict low subreg reload -- refuse\n",
2314 if (operand_reg
[nop
] != NULL_RTX
2315 /* Output operands and matched input operands are
2316 not inherited. The following conditions do not
2317 exactly describe the previous statement but they
2318 are pretty close. */
2319 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2320 && (this_alternative_matches
< 0
2321 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2323 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2327 /* The value of reload_sum has sense only if we
2328 process insns in their order. It happens only on
2329 the first constraints sub-pass when we do most of
2331 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2332 reload_sum
+= last_reload
- bb_reload_num
;
2334 /* If this is a constant that is reloaded into the
2335 desired class by copying it to memory first, count
2336 that as another reload. This is consistent with
2337 other code and is required to avoid choosing another
2338 alternative when the constant is moved into memory.
2339 Note that the test here is precisely the same as in
2340 the code below that calls force_const_mem. */
2341 if (CONST_POOL_OK_P (mode
, op
)
2342 && ((targetm
.preferred_reload_class
2343 (op
, this_alternative
) == NO_REGS
)
2344 || no_input_reloads_p
))
2351 /* Alternative loses if it requires a type of reload not
2352 permitted for this insn. We can always reload
2353 objects with a REG_UNUSED note. */
2354 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2355 && no_output_reloads_p
2356 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2357 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2358 && no_input_reloads_p
&& ! const_to_mem
)
2359 || (this_alternative_matches
>= 0
2360 && (no_input_reloads_p
2361 || (no_output_reloads_p
2362 && (curr_static_id
->operand
2363 [this_alternative_matches
].type
!= OP_IN
)
2364 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2365 no_subreg_reg_operand
2366 [this_alternative_matches
])))))
2368 if (lra_dump_file
!= NULL
)
2371 " alt=%d: No input/otput reload -- refuse\n",
2376 /* Check strong discouragement of reload of non-constant
2377 into class THIS_ALTERNATIVE. */
2378 if (! CONSTANT_P (op
) && ! no_regs_p
2379 && (targetm
.preferred_reload_class
2380 (op
, this_alternative
) == NO_REGS
2381 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2382 && (targetm
.preferred_output_reload_class
2383 (op
, this_alternative
) == NO_REGS
))))
2385 if (lra_dump_file
!= NULL
)
2386 fprintf (lra_dump_file
,
2387 " %d Non-prefered reload: reject+=%d\n",
2388 nop
, LRA_MAX_REJECT
);
2389 reject
+= LRA_MAX_REJECT
;
2392 if (! (MEM_P (op
) && offmemok
)
2393 && ! (const_to_mem
&& constmemok
))
2395 /* We prefer to reload pseudos over reloading other
2396 things, since such reloads may be able to be
2397 eliminated later. So bump REJECT in other cases.
2398 Don't do this in the case where we are forcing a
2399 constant into memory and it will then win since
2400 we don't want to have a different alternative
2402 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2404 if (lra_dump_file
!= NULL
)
2407 " %d Non-pseudo reload: reject+=2\n",
2414 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2416 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2418 if (lra_dump_file
!= NULL
)
2421 " %d Small class reload: reject+=%d\n",
2422 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2423 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2427 /* We are trying to spill pseudo into memory. It is
2428 usually more costly than moving to a hard register
2429 although it might takes the same number of
2431 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2433 if (lra_dump_file
!= NULL
)
2436 " %d Spill pseudo into memory: reject+=3\n",
2439 if (VECTOR_MODE_P (mode
))
2441 /* Spilling vectors into memory is usually more
2442 costly as they contain big values. */
2443 if (lra_dump_file
!= NULL
)
2446 " %d Spill vector pseudo: reject+=2\n",
2452 #ifdef SECONDARY_MEMORY_NEEDED
2453 /* If reload requires moving value through secondary
2454 memory, it will need one more insn at least. */
2455 if (this_alternative
!= NO_REGS
2456 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2457 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2458 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2460 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2461 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2465 /* Input reloads can be inherited more often than output
2466 reloads can be removed, so penalize output
2468 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2470 if (lra_dump_file
!= NULL
)
2473 " %d Non input pseudo reload: reject++\n",
2479 if (early_clobber_p
&& ! scratch_p
)
2481 if (lra_dump_file
!= NULL
)
2482 fprintf (lra_dump_file
,
2483 " %d Early clobber: reject++\n", nop
);
2486 /* ??? We check early clobbers after processing all operands
2487 (see loop below) and there we update the costs more.
2488 Should we update the cost (may be approximately) here
2489 because of early clobber register reloads or it is a rare
2490 or non-important thing to be worth to do it. */
2491 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2492 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2494 if (lra_dump_file
!= NULL
)
2495 fprintf (lra_dump_file
,
2496 " alt=%d,overall=%d,losers=%d -- refuse\n",
2497 nalt
, overall
, losers
);
2501 curr_alt
[nop
] = this_alternative
;
2502 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2503 curr_alt_win
[nop
] = this_alternative_win
;
2504 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2505 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2506 curr_alt_matches
[nop
] = this_alternative_matches
;
2508 if (this_alternative_matches
>= 0
2509 && !did_match
&& !this_alternative_win
)
2510 curr_alt_win
[this_alternative_matches
] = false;
2512 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2513 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2515 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2516 /* Prevent processing non-move insns. */
2517 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2518 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2519 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2520 && REG_P (no_subreg_reg_operand
[0])
2521 && REG_P (no_subreg_reg_operand
[1])
2522 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2523 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2524 || (! curr_alt_win
[0] && curr_alt_win
[1]
2525 && REG_P (no_subreg_reg_operand
[1])
2526 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2527 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2528 && REG_P (no_subreg_reg_operand
[0])
2529 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2530 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2531 no_subreg_reg_operand
[1])
2532 || (targetm
.preferred_reload_class
2533 (no_subreg_reg_operand
[1],
2534 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2535 /* If it is a result of recent elimination in move
2536 insn we can transform it into an add still by
2537 using this alternative. */
2538 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2540 /* We have a move insn and a new reload insn will be similar
2541 to the current insn. We should avoid such situation as it
2542 results in LRA cycling. */
2543 overall
+= LRA_MAX_REJECT
;
2546 curr_alt_dont_inherit_ops_num
= 0;
2547 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2549 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2550 HARD_REG_SET temp_set
;
2552 i
= early_clobbered_nops
[nop
];
2553 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2554 || hard_regno
[i
] < 0)
2556 lra_assert (operand_reg
[i
] != NULL_RTX
);
2557 clobbered_hard_regno
= hard_regno
[i
];
2558 CLEAR_HARD_REG_SET (temp_set
);
2559 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2560 first_conflict_j
= last_conflict_j
= -1;
2561 for (j
= 0; j
< n_operands
; j
++)
2563 /* We don't want process insides of match_operator and
2564 match_parallel because otherwise we would process
2565 their operands once again generating a wrong
2567 || curr_static_id
->operand
[j
].is_operator
)
2569 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2570 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2572 /* If we don't reload j-th operand, check conflicts. */
2573 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2574 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2576 if (first_conflict_j
< 0)
2577 first_conflict_j
= j
;
2578 last_conflict_j
= j
;
2580 if (last_conflict_j
< 0)
2582 /* If earlyclobber operand conflicts with another
2583 non-matching operand which is actually the same register
2584 as the earlyclobber operand, it is better to reload the
2585 another operand as an operand matching the earlyclobber
2586 operand can be also the same. */
2587 if (first_conflict_j
== last_conflict_j
2588 && operand_reg
[last_conflict_j
]
2589 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2590 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2592 curr_alt_win
[last_conflict_j
] = false;
2593 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2596 /* Early clobber was already reflected in REJECT. */
2597 lra_assert (reject
> 0);
2598 if (lra_dump_file
!= NULL
)
2601 " %d Conflict early clobber reload: reject--\n",
2604 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2608 /* We need to reload early clobbered register and the
2609 matched registers. */
2610 for (j
= 0; j
< n_operands
; j
++)
2611 if (curr_alt_matches
[j
] == i
)
2613 curr_alt_match_win
[j
] = false;
2615 overall
+= LRA_LOSER_COST_FACTOR
;
2617 if (! curr_alt_match_win
[i
])
2618 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2621 /* Remember pseudos used for match reloads are never
2623 lra_assert (curr_alt_matches
[i
] >= 0);
2624 curr_alt_win
[curr_alt_matches
[i
]] = false;
2626 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2628 /* Early clobber was already reflected in REJECT. */
2629 lra_assert (reject
> 0);
2630 if (lra_dump_file
!= NULL
)
2633 " %d Matched conflict early clobber reloads:"
2637 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2640 if (lra_dump_file
!= NULL
)
2641 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2642 nalt
, overall
, losers
, reload_nregs
);
2644 /* If this alternative can be made to work by reloading, and it
2645 needs less reloading than the others checked so far, record
2646 it as the chosen goal for reloading. */
2647 if ((best_losers
!= 0 && losers
== 0)
2648 || (((best_losers
== 0 && losers
== 0)
2649 || (best_losers
!= 0 && losers
!= 0))
2650 && (best_overall
> overall
2651 || (best_overall
== overall
2652 /* If the cost of the reloads is the same,
2653 prefer alternative which requires minimal
2654 number of reload regs. */
2655 && (reload_nregs
< best_reload_nregs
2656 || (reload_nregs
== best_reload_nregs
2657 && (best_reload_sum
< reload_sum
2658 || (best_reload_sum
== reload_sum
2659 && nalt
< goal_alt_number
))))))))
2661 for (nop
= 0; nop
< n_operands
; nop
++)
2663 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2664 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2665 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2666 goal_alt
[nop
] = curr_alt
[nop
];
2667 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2669 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2670 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2671 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2672 goal_alt_swapped
= curr_swapped
;
2673 best_overall
= overall
;
2674 best_losers
= losers
;
2675 best_reload_nregs
= reload_nregs
;
2676 best_reload_sum
= reload_sum
;
2677 goal_alt_number
= nalt
;
2680 /* Everything is satisfied. Do not process alternatives
2689 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2691 base_plus_disp_to_reg (struct address_info
*ad
)
2696 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2697 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2698 get_index_code (ad
));
2699 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2701 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2705 /* Make reload of index part of address AD. Return the new
2708 index_part_to_reg (struct address_info
*ad
)
2712 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2713 INDEX_REG_CLASS
, "index term");
2714 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2715 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2719 /* Return true if we can add a displacement to address AD, even if that
2720 makes the address invalid. The fix-up code requires any new address
2721 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2723 can_add_disp_p (struct address_info
*ad
)
2725 return (!ad
->autoinc_p
2726 && ad
->segment
== NULL
2727 && ad
->base
== ad
->base_term
2728 && ad
->disp
== ad
->disp_term
);
2731 /* Make equiv substitution in address AD. Return true if a substitution
2734 equiv_address_substitution (struct address_info
*ad
)
2736 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2737 HOST_WIDE_INT disp
, scale
;
2740 base_term
= strip_subreg (ad
->base_term
);
2741 if (base_term
== NULL
)
2742 base_reg
= new_base_reg
= NULL_RTX
;
2745 base_reg
= *base_term
;
2746 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2748 index_term
= strip_subreg (ad
->index_term
);
2749 if (index_term
== NULL
)
2750 index_reg
= new_index_reg
= NULL_RTX
;
2753 index_reg
= *index_term
;
2754 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2756 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2760 if (lra_dump_file
!= NULL
)
2762 fprintf (lra_dump_file
, "Changing address in insn %d ",
2763 INSN_UID (curr_insn
));
2764 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2766 if (base_reg
!= new_base_reg
)
2768 if (REG_P (new_base_reg
))
2770 *base_term
= new_base_reg
;
2773 else if (GET_CODE (new_base_reg
) == PLUS
2774 && REG_P (XEXP (new_base_reg
, 0))
2775 && CONST_INT_P (XEXP (new_base_reg
, 1))
2776 && can_add_disp_p (ad
))
2778 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2779 *base_term
= XEXP (new_base_reg
, 0);
2782 if (ad
->base_term2
!= NULL
)
2783 *ad
->base_term2
= *ad
->base_term
;
2785 if (index_reg
!= new_index_reg
)
2787 if (REG_P (new_index_reg
))
2789 *index_term
= new_index_reg
;
2792 else if (GET_CODE (new_index_reg
) == PLUS
2793 && REG_P (XEXP (new_index_reg
, 0))
2794 && CONST_INT_P (XEXP (new_index_reg
, 1))
2795 && can_add_disp_p (ad
)
2796 && (scale
= get_index_scale (ad
)))
2798 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2799 *index_term
= XEXP (new_index_reg
, 0);
2805 if (ad
->disp
!= NULL
)
2806 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2809 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2810 update_address (ad
);
2814 if (lra_dump_file
!= NULL
)
2817 fprintf (lra_dump_file
, " -- no change\n");
2820 fprintf (lra_dump_file
, " on equiv ");
2821 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2822 fprintf (lra_dump_file
, "\n");
2828 /* Major function to make reloads for an address in operand NOP.
2829 The supported cases are:
2831 1) an address that existed before LRA started, at which point it
2832 must have been valid. These addresses are subject to elimination
2833 and may have become invalid due to the elimination offset being out
2836 2) an address created by forcing a constant to memory
2837 (force_const_to_mem). The initial form of these addresses might
2838 not be valid, and it is this function's job to make them valid.
2840 3) a frame address formed from a register and a (possibly zero)
2841 constant offset. As above, these addresses might not be valid and
2842 this function must make them so.
2844 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2845 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2846 address. Return true for any RTL change.
2848 The function is a helper function which does not produce all
2849 transformations which can be necessary. It does just basic steps.
2850 To do all necessary transformations use function
2853 process_address_1 (int nop
, rtx
*before
, rtx
*after
)
2855 struct address_info ad
;
2857 rtx op
= *curr_id
->operand_loc
[nop
];
2858 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2861 if (constraint
[0] == 'p'
2862 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2863 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2864 else if (MEM_P (op
))
2865 decompose_mem_address (&ad
, op
);
2866 else if (GET_CODE (op
) == SUBREG
2867 && MEM_P (SUBREG_REG (op
)))
2868 decompose_mem_address (&ad
, SUBREG_REG (op
));
2871 change_p
= equiv_address_substitution (&ad
);
2872 if (ad
.base_term
!= NULL
2873 && (process_addr_reg
2874 (ad
.base_term
, before
,
2876 && !(REG_P (*ad
.base_term
)
2877 && find_regno_note (curr_insn
, REG_DEAD
,
2878 REGNO (*ad
.base_term
)) != NULL_RTX
)
2880 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2881 get_index_code (&ad
)))))
2884 if (ad
.base_term2
!= NULL
)
2885 *ad
.base_term2
= *ad
.base_term
;
2887 if (ad
.index_term
!= NULL
2888 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2891 #ifdef EXTRA_CONSTRAINT_STR
2892 /* Target hooks sometimes reject extra constraint addresses -- use
2893 EXTRA_CONSTRAINT_STR for the validation. */
2894 if (constraint
[0] != 'p'
2895 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2896 && satisfies_address_constraint_p (&ad
, constraint
))
2900 /* There are three cases where the shape of *AD.INNER may now be invalid:
2902 1) the original address was valid, but either elimination or
2903 equiv_address_substitution was applied and that made
2904 the address invalid.
2906 2) the address is an invalid symbolic address created by
2909 3) the address is a frame address with an invalid offset.
2911 All these cases involve a non-autoinc address, so there is no
2912 point revalidating other types. */
2913 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2916 /* Any index existed before LRA started, so we can assume that the
2917 presence and shape of the index is valid. */
2918 push_to_sequence (*before
);
2919 lra_assert (ad
.disp
== ad
.disp_term
);
2920 if (ad
.base
== NULL
)
2922 if (ad
.index
== NULL
)
2925 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2927 rtx addr
= *ad
.inner
;
2929 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2933 rtx last
= get_last_insn ();
2935 /* addr => lo_sum (new_base, addr), case (2) above. */
2936 insn
= emit_insn (gen_rtx_SET
2938 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2939 code
= recog_memoized (insn
);
2942 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2943 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2945 /* Try to put lo_sum into register. */
2946 insn
= emit_insn (gen_rtx_SET
2948 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2949 code
= recog_memoized (insn
);
2952 *ad
.inner
= new_reg
;
2953 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2963 delete_insns_since (last
);
2968 /* addr => new_base, case (2) above. */
2969 lra_emit_move (new_reg
, addr
);
2970 *ad
.inner
= new_reg
;
2975 /* index * scale + disp => new base + index * scale,
2977 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2978 GET_CODE (*ad
.index
));
2980 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2981 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2982 lra_emit_move (new_reg
, *ad
.disp
);
2983 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2984 new_reg
, *ad
.index
);
2987 else if (ad
.index
== NULL
)
2991 rtx set
, insns
, last_insn
;
2992 /* base + disp => new base, cases (1) and (3) above. */
2993 /* Another option would be to reload the displacement into an
2994 index register. However, postreload has code to optimize
2995 address reloads that have the same base and different
2996 displacements, so reloading into an index register would
2997 not necessarily be a win. */
2999 new_reg
= base_plus_disp_to_reg (&ad
);
3000 insns
= get_insns ();
3001 last_insn
= get_last_insn ();
3002 /* If we generated at least two insns, try last insn source as
3003 an address. If we succeed, we generate one less insn. */
3004 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3005 && GET_CODE (SET_SRC (set
)) == PLUS
3006 && REG_P (XEXP (SET_SRC (set
), 0))
3007 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3009 *ad
.inner
= SET_SRC (set
);
3010 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3012 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3013 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3014 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3015 get_index_code (&ad
));
3016 regno
= REGNO (*ad
.base_term
);
3017 if (regno
>= FIRST_PSEUDO_REGISTER
3018 && cl
!= lra_get_allocno_class (regno
))
3019 lra_change_class (regno
, cl
, " Change to", true);
3020 new_reg
= SET_SRC (set
);
3021 delete_insns_since (PREV_INSN (last_insn
));
3026 *ad
.inner
= new_reg
;
3028 else if (ad
.disp_term
!= NULL
)
3030 /* base + scale * index + disp => new base + scale * index,
3032 new_reg
= base_plus_disp_to_reg (&ad
);
3033 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3034 new_reg
, *ad
.index
);
3038 /* base + scale * index => base + new_reg,
3040 Index part of address may become invalid. For example, we
3041 changed pseudo on the equivalent memory and a subreg of the
3042 pseudo onto the memory of different mode for which the scale is
3044 new_reg
= index_part_to_reg (&ad
);
3045 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3046 *ad
.base_term
, new_reg
);
3048 *before
= get_insns ();
3053 /* Do address reloads until it is necessary. Use process_address_1 as
3054 a helper function. Return true for any RTL changes. */
3056 process_address (int nop
, rtx
*before
, rtx
*after
)
3060 while (process_address_1 (nop
, before
, after
))
3065 /* Emit insns to reload VALUE into a new register. VALUE is an
3066 auto-increment or auto-decrement RTX whose operand is a register or
3067 memory location; so reloading involves incrementing that location.
3068 IN is either identical to VALUE, or some cheaper place to reload
3069 value being incremented/decremented from.
3071 INC_AMOUNT is the number to increment or decrement by (always
3072 positive and ignored for POST_MODIFY/PRE_MODIFY).
3074 Return pseudo containing the result. */
3076 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3078 /* REG or MEM to be copied and incremented. */
3079 rtx incloc
= XEXP (value
, 0);
3080 /* Nonzero if increment after copying. */
3081 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3082 || GET_CODE (value
) == POST_MODIFY
);
3087 rtx real_in
= in
== value
? incloc
: in
;
3091 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3093 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3094 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3095 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3096 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3097 inc
= XEXP (XEXP (value
, 1), 1);
3101 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3102 inc_amount
= -inc_amount
;
3104 inc
= GEN_INT (inc_amount
);
3107 if (! post
&& REG_P (incloc
))
3110 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3113 if (real_in
!= result
)
3115 /* First copy the location to the result register. */
3116 lra_assert (REG_P (result
));
3117 emit_insn (gen_move_insn (result
, real_in
));
3120 /* We suppose that there are insns to add/sub with the constant
3121 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3122 old reload worked with this assumption. If the assumption
3123 becomes wrong, we should use approach in function
3124 base_plus_disp_to_reg. */
3127 /* See if we can directly increment INCLOC. */
3128 last
= get_last_insn ();
3129 add_insn
= emit_insn (plus_p
3130 ? gen_add2_insn (incloc
, inc
)
3131 : gen_sub2_insn (incloc
, inc
));
3133 code
= recog_memoized (add_insn
);
3136 if (! post
&& result
!= incloc
)
3137 emit_insn (gen_move_insn (result
, incloc
));
3140 delete_insns_since (last
);
3143 /* If couldn't do the increment directly, must increment in RESULT.
3144 The way we do this depends on whether this is pre- or
3145 post-increment. For pre-increment, copy INCLOC to the reload
3146 register, increment it there, then save back. */
3149 if (real_in
!= result
)
3150 emit_insn (gen_move_insn (result
, real_in
));
3152 emit_insn (gen_add2_insn (result
, inc
));
3154 emit_insn (gen_sub2_insn (result
, inc
));
3155 if (result
!= incloc
)
3156 emit_insn (gen_move_insn (incloc
, result
));
3162 Because this might be a jump insn or a compare, and because
3163 RESULT may not be available after the insn in an input
3164 reload, we must do the incrementing before the insn being
3167 We have already copied IN to RESULT. Increment the copy in
3168 RESULT, save that back, then decrement RESULT so it has
3169 the original value. */
3171 emit_insn (gen_add2_insn (result
, inc
));
3173 emit_insn (gen_sub2_insn (result
, inc
));
3174 emit_insn (gen_move_insn (incloc
, result
));
3175 /* Restore non-modified value for the result. We prefer this
3176 way because it does not require an additional hard
3180 if (CONST_INT_P (inc
))
3181 emit_insn (gen_add2_insn (result
,
3182 gen_int_mode (-INTVAL (inc
),
3183 GET_MODE (result
))));
3185 emit_insn (gen_sub2_insn (result
, inc
));
3188 emit_insn (gen_add2_insn (result
, inc
));
3193 /* Return true if the current move insn does not need processing as we
3194 already know that it satisfies its constraints. */
3196 simple_move_p (void)
3199 enum reg_class dclass
, sclass
;
3201 lra_assert (curr_insn_set
!= NULL_RTX
);
3202 dest
= SET_DEST (curr_insn_set
);
3203 src
= SET_SRC (curr_insn_set
);
3204 return ((dclass
= get_op_class (dest
)) != NO_REGS
3205 && (sclass
= get_op_class (src
)) != NO_REGS
3206 /* The backend guarantees that register moves of cost 2
3207 never need reloads. */
3208 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3211 /* Swap operands NOP and NOP + 1. */
3213 swap_operands (int nop
)
3215 enum machine_mode mode
= curr_operand_mode
[nop
];
3216 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3217 curr_operand_mode
[nop
+ 1] = mode
;
3218 rtx x
= *curr_id
->operand_loc
[nop
];
3219 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3220 *curr_id
->operand_loc
[nop
+ 1] = x
;
3221 /* Swap the duplicates too. */
3222 lra_update_dup (curr_id
, nop
);
3223 lra_update_dup (curr_id
, nop
+ 1);
3226 /* Main entry point of the constraint code: search the body of the
3227 current insn to choose the best alternative. It is mimicking insn
3228 alternative cost calculation model of former reload pass. That is
3229 because machine descriptions were written to use this model. This
3230 model can be changed in future. Make commutative operand exchange
3233 Return true if some RTL changes happened during function call. */
3235 curr_insn_transform (void)
3241 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3242 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3245 /* Flag that the insn has been changed through a transformation. */
3248 #ifdef SECONDARY_MEMORY_NEEDED
3251 int max_regno_before
;
3252 int reused_alternative_num
;
3254 curr_insn_set
= single_set (curr_insn
);
3255 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3258 no_input_reloads_p
= no_output_reloads_p
= false;
3259 goal_alt_number
= -1;
3260 change_p
= sec_mem_p
= false;
3261 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3262 reloads; neither are insns that SET cc0. Insns that use CC0 are
3263 not allowed to have any input reloads. */
3264 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3265 no_output_reloads_p
= true;
3268 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3269 no_input_reloads_p
= true;
3270 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3271 no_output_reloads_p
= true;
3274 n_operands
= curr_static_id
->n_operands
;
3275 n_alternatives
= curr_static_id
->n_alternatives
;
3277 /* Just return "no reloads" if insn has no operands with
3279 if (n_operands
== 0 || n_alternatives
== 0)
3282 max_regno_before
= max_reg_num ();
3284 for (i
= 0; i
< n_operands
; i
++)
3286 goal_alt_matched
[i
][0] = -1;
3287 goal_alt_matches
[i
] = -1;
3290 commutative
= curr_static_id
->commutative
;
3292 /* Now see what we need for pseudos that didn't get hard regs or got
3293 the wrong kind of hard reg. For this, we must consider all the
3294 operands together against the register constraints. */
3296 best_losers
= best_overall
= INT_MAX
;
3297 best_reload_sum
= 0;
3299 curr_swapped
= false;
3300 goal_alt_swapped
= false;
3302 /* Make equivalence substitution and memory subreg elimination
3303 before address processing because an address legitimacy can
3304 depend on memory mode. */
3305 for (i
= 0; i
< n_operands
; i
++)
3307 rtx op
= *curr_id
->operand_loc
[i
];
3308 rtx subst
, old
= op
;
3309 bool op_change_p
= false;
3311 if (GET_CODE (old
) == SUBREG
)
3312 old
= SUBREG_REG (old
);
3313 subst
= get_equiv_with_elimination (old
, curr_insn
);
3316 subst
= copy_rtx (subst
);
3317 lra_assert (REG_P (old
));
3318 if (GET_CODE (op
) == SUBREG
)
3319 SUBREG_REG (op
) = subst
;
3321 *curr_id
->operand_loc
[i
] = subst
;
3322 if (lra_dump_file
!= NULL
)
3324 fprintf (lra_dump_file
,
3325 "Changing pseudo %d in operand %i of insn %u on equiv ",
3326 REGNO (old
), i
, INSN_UID (curr_insn
));
3327 dump_value_slim (lra_dump_file
, subst
, 1);
3328 fprintf (lra_dump_file
, "\n");
3330 op_change_p
= change_p
= true;
3332 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3335 lra_update_dup (curr_id
, i
);
3339 /* Reload address registers and displacements. We do it before
3340 finding an alternative because of memory constraints. */
3341 before
= after
= NULL_RTX
;
3342 for (i
= 0; i
< n_operands
; i
++)
3343 if (! curr_static_id
->operand
[i
].is_operator
3344 && process_address (i
, &before
, &after
))
3347 lra_update_dup (curr_id
, i
);
3351 /* If we've changed the instruction then any alternative that
3352 we chose previously may no longer be valid. */
3353 lra_set_used_insn_alternative (curr_insn
, -1);
3355 if (curr_insn_set
!= NULL_RTX
3356 && check_and_process_move (&change_p
, &sec_mem_p
))
3361 reused_alternative_num
= curr_id
->used_insn_alternative
;
3362 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3363 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3364 reused_alternative_num
, INSN_UID (curr_insn
));
3366 if (process_alt_operands (reused_alternative_num
))
3369 /* If insn is commutative (it's safe to exchange a certain pair of
3370 operands) then we need to try each alternative twice, the second
3371 time matching those two operands as if we had exchanged them. To
3372 do this, really exchange them in operands.
3374 If we have just tried the alternatives the second time, return
3375 operands to normal and drop through. */
3377 if (reused_alternative_num
< 0 && commutative
>= 0)
3379 curr_swapped
= !curr_swapped
;
3382 swap_operands (commutative
);
3386 swap_operands (commutative
);
3389 if (! alt_p
&& ! sec_mem_p
)
3391 /* No alternative works with reloads?? */
3392 if (INSN_CODE (curr_insn
) >= 0)
3393 fatal_insn ("unable to generate reloads for:", curr_insn
);
3394 error_for_asm (curr_insn
,
3395 "inconsistent operand constraints in an %<asm%>");
3396 /* Avoid further trouble with this insn. */
3397 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3398 lra_invalidate_insn_data (curr_insn
);
3402 /* If the best alternative is with operands 1 and 2 swapped, swap
3403 them. Update the operand numbers of any reloads already
3406 if (goal_alt_swapped
)
3408 if (lra_dump_file
!= NULL
)
3409 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3410 INSN_UID (curr_insn
));
3412 /* Swap the duplicates too. */
3413 swap_operands (commutative
);
3417 #ifdef SECONDARY_MEMORY_NEEDED
3418 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3419 too conservatively. So we use the secondary memory only if there
3420 is no any alternative without reloads. */
3421 use_sec_mem_p
= false;
3423 use_sec_mem_p
= true;
3426 for (i
= 0; i
< n_operands
; i
++)
3427 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3429 use_sec_mem_p
= i
< n_operands
;
3434 rtx new_reg
, src
, dest
, rld
;
3435 enum machine_mode sec_mode
, rld_mode
;
3437 lra_assert (sec_mem_p
);
3438 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3439 && curr_static_id
->operand
[1].type
== OP_IN
);
3440 dest
= *curr_id
->operand_loc
[0];
3441 src
= *curr_id
->operand_loc
[1];
3442 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3444 rld_mode
= GET_MODE (rld
);
3445 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3446 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3448 sec_mode
= rld_mode
;
3450 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3451 NO_REGS
, "secondary");
3452 /* If the mode is changed, it should be wider. */
3453 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3454 if (sec_mode
!= rld_mode
)
3456 /* If the target says specifically to use another mode for
3457 secondary memory moves we can not reuse the original
3459 after
= emit_spill_move (false, new_reg
, dest
);
3460 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3461 "Inserting the sec. move");
3462 /* We may have non null BEFORE here (e.g. after address
3464 push_to_sequence (before
);
3465 before
= emit_spill_move (true, new_reg
, src
);
3467 before
= get_insns ();
3469 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3470 lra_set_insn_deleted (curr_insn
);
3472 else if (dest
== rld
)
3474 *curr_id
->operand_loc
[0] = new_reg
;
3475 after
= emit_spill_move (false, new_reg
, dest
);
3476 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3477 "Inserting the sec. move");
3481 *curr_id
->operand_loc
[1] = new_reg
;
3482 /* See comments above. */
3483 push_to_sequence (before
);
3484 before
= emit_spill_move (true, new_reg
, src
);
3486 before
= get_insns ();
3488 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3489 "Inserting the sec. move");
3491 lra_update_insn_regno_info (curr_insn
);
3496 lra_assert (goal_alt_number
>= 0);
3497 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3499 if (lra_dump_file
!= NULL
)
3503 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3504 goal_alt_number
, INSN_UID (curr_insn
));
3505 for (i
= 0; i
< n_operands
; i
++)
3507 p
= (curr_static_id
->operand_alternative
3508 [goal_alt_number
* n_operands
+ i
].constraint
);
3511 fprintf (lra_dump_file
, " (%d) ", i
);
3512 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3513 fputc (*p
, lra_dump_file
);
3515 if (INSN_CODE (curr_insn
) >= 0
3516 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3517 fprintf (lra_dump_file
, " {%s}", p
);
3518 if (curr_id
->sp_offset
!= 0)
3519 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3520 curr_id
->sp_offset
);
3521 fprintf (lra_dump_file
, "\n");
3524 /* Right now, for any pair of operands I and J that are required to
3525 match, with J < I, goal_alt_matches[I] is J. Add I to
3526 goal_alt_matched[J]. */
3528 for (i
= 0; i
< n_operands
; i
++)
3529 if ((j
= goal_alt_matches
[i
]) >= 0)
3531 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3533 /* We allow matching one output operand and several input
3536 || (curr_static_id
->operand
[j
].type
== OP_OUT
3537 && curr_static_id
->operand
[i
].type
== OP_IN
3538 && (curr_static_id
->operand
3539 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3540 goal_alt_matched
[j
][k
] = i
;
3541 goal_alt_matched
[j
][k
+ 1] = -1;
3544 for (i
= 0; i
< n_operands
; i
++)
3545 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3547 /* Any constants that aren't allowed and can't be reloaded into
3548 registers are here changed into memory references. */
3549 for (i
= 0; i
< n_operands
; i
++)
3550 if (goal_alt_win
[i
])
3553 enum reg_class new_class
;
3554 rtx reg
= *curr_id
->operand_loc
[i
];
3556 if (GET_CODE (reg
) == SUBREG
)
3557 reg
= SUBREG_REG (reg
);
3559 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3561 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3563 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3566 lra_change_class (regno
, new_class
, " Change to", true);
3572 const char *constraint
;
3574 rtx op
= *curr_id
->operand_loc
[i
];
3575 rtx subreg
= NULL_RTX
;
3576 enum machine_mode mode
= curr_operand_mode
[i
];
3578 if (GET_CODE (op
) == SUBREG
)
3581 op
= SUBREG_REG (op
);
3582 mode
= GET_MODE (op
);
3585 if (CONST_POOL_OK_P (mode
, op
)
3586 && ((targetm
.preferred_reload_class
3587 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3588 || no_input_reloads_p
))
3590 rtx tem
= force_const_mem (mode
, op
);
3593 if (subreg
!= NULL_RTX
)
3594 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3596 *curr_id
->operand_loc
[i
] = tem
;
3597 lra_update_dup (curr_id
, i
);
3598 process_address (i
, &before
, &after
);
3600 /* If the alternative accepts constant pool refs directly
3601 there will be no reload needed at all. */
3602 if (subreg
!= NULL_RTX
)
3604 /* Skip alternatives before the one requested. */
3605 constraint
= (curr_static_id
->operand_alternative
3606 [goal_alt_number
* n_operands
+ i
].constraint
);
3608 (c
= *constraint
) && c
!= ',' && c
!= '#';
3609 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3611 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3613 #ifdef EXTRA_CONSTRAINT_STR
3614 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3615 && satisfies_memory_constraint_p (tem
, constraint
))
3619 if (c
== '\0' || c
== ',' || c
== '#')
3622 goal_alt_win
[i
] = true;
3626 for (i
= 0; i
< n_operands
; i
++)
3629 bool optional_p
= false;
3631 rtx op
= *curr_id
->operand_loc
[i
];
3633 if (goal_alt_win
[i
])
3635 if (goal_alt
[i
] == NO_REGS
3637 /* When we assign NO_REGS it means that we will not
3638 assign a hard register to the scratch pseudo by
3639 assigment pass and the scratch pseudo will be
3640 spilled. Spilled scratch pseudos are transformed
3641 back to scratches at the LRA end. */
3642 && lra_former_scratch_operand_p (curr_insn
, i
))
3644 int regno
= REGNO (op
);
3645 lra_change_class (regno
, NO_REGS
, " Change to", true);
3646 if (lra_get_regno_hard_regno (regno
) >= 0)
3647 /* We don't have to mark all insn affected by the
3648 spilled pseudo as there is only one such insn, the
3650 reg_renumber
[regno
] = -1;
3652 /* We can do an optional reload. If the pseudo got a hard
3653 reg, we might improve the code through inheritance. If
3654 it does not get a hard register we coalesce memory/memory
3655 moves later. Ignore move insns to avoid cycling. */
3657 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3658 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3659 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3660 && regno
< new_regno_start
3661 && ! lra_former_scratch_p (regno
)
3662 && reg_renumber
[regno
] < 0
3663 && (curr_insn_set
== NULL_RTX
3664 || !((REG_P (SET_SRC (curr_insn_set
))
3665 || MEM_P (SET_SRC (curr_insn_set
))
3666 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3667 && (REG_P (SET_DEST (curr_insn_set
))
3668 || MEM_P (SET_DEST (curr_insn_set
))
3669 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3675 /* Operands that match previous ones have already been handled. */
3676 if (goal_alt_matches
[i
] >= 0)
3679 /* We should not have an operand with a non-offsettable address
3680 appearing where an offsettable address will do. It also may
3681 be a case when the address should be special in other words
3682 not a general one (e.g. it needs no index reg). */
3683 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3685 enum reg_class rclass
;
3686 rtx
*loc
= &XEXP (op
, 0);
3687 enum rtx_code code
= GET_CODE (*loc
);
3689 push_to_sequence (before
);
3690 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3692 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3693 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3694 /* This value does not matter for MODIFY. */
3695 GET_MODE_SIZE (GET_MODE (op
)));
3696 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3697 "offsetable address", &new_reg
))
3698 lra_emit_move (new_reg
, *loc
);
3699 before
= get_insns ();
3702 lra_update_dup (curr_id
, i
);
3704 else if (goal_alt_matched
[i
][0] == -1)
3706 enum machine_mode mode
;
3708 int hard_regno
, byte
;
3709 enum op_type type
= curr_static_id
->operand
[i
].type
;
3711 loc
= curr_id
->operand_loc
[i
];
3712 mode
= curr_operand_mode
[i
];
3713 if (GET_CODE (*loc
) == SUBREG
)
3715 reg
= SUBREG_REG (*loc
);
3716 byte
= SUBREG_BYTE (*loc
);
3718 /* Strict_low_part requires reload the register not
3719 the sub-register. */
3720 && (curr_static_id
->operand
[i
].strict_low
3721 || (GET_MODE_SIZE (mode
)
3722 <= GET_MODE_SIZE (GET_MODE (reg
))
3724 = get_try_hard_regno (REGNO (reg
))) >= 0
3725 && (simplify_subreg_regno
3727 GET_MODE (reg
), byte
, mode
) < 0)
3728 && (goal_alt
[i
] == NO_REGS
3729 || (simplify_subreg_regno
3730 (ira_class_hard_regs
[goal_alt
[i
]][0],
3731 GET_MODE (reg
), byte
, mode
) >= 0)))))
3733 loc
= &SUBREG_REG (*loc
);
3734 mode
= GET_MODE (*loc
);
3738 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3739 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3742 push_to_sequence (before
);
3743 lra_emit_move (new_reg
, old
);
3744 before
= get_insns ();
3749 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3752 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3754 after
= get_insns ();
3758 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3759 if (goal_alt_dont_inherit_ops
[j
] == i
)
3761 lra_set_regno_unique_value (REGNO (new_reg
));
3764 lra_update_dup (curr_id
, i
);
3766 else if (curr_static_id
->operand
[i
].type
== OP_IN
3767 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3770 /* generate reloads for input and matched outputs. */
3771 match_inputs
[0] = i
;
3772 match_inputs
[1] = -1;
3773 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3774 goal_alt
[i
], &before
, &after
);
3776 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3777 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3779 /* Generate reloads for output and matched inputs. */
3780 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3781 else if (curr_static_id
->operand
[i
].type
== OP_IN
3782 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3785 /* Generate reloads for matched inputs. */
3786 match_inputs
[0] = i
;
3787 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3788 match_inputs
[j
+ 1] = k
;
3789 match_inputs
[j
+ 1] = -1;
3790 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3793 /* We must generate code in any case when function
3794 process_alt_operands decides that it is possible. */
3798 lra_assert (REG_P (op
));
3800 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3801 if (GET_CODE (op
) == SUBREG
)
3802 op
= SUBREG_REG (op
);
3803 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3804 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3805 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3806 if (lra_dump_file
!= NULL
)
3807 fprintf (lra_dump_file
,
3808 " Making reload reg %d for reg %d optional\n",
3812 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3813 || max_regno_before
!= max_reg_num ())
3817 lra_update_operator_dups (curr_id
);
3818 /* Something changes -- process the insn. */
3819 lra_update_insn_regno_info (curr_insn
);
3821 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3825 /* Return true if X is in LIST. */
3827 in_list_p (rtx x
, rtx list
)
3829 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3830 if (XEXP (list
, 0) == x
)
3835 /* Return true if X contains an allocatable hard register (if
3836 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3838 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3844 code
= GET_CODE (x
);
3847 int regno
= REGNO (x
);
3848 HARD_REG_SET alloc_regs
;
3852 if (regno
>= FIRST_PSEUDO_REGISTER
)
3853 regno
= lra_get_regno_hard_regno (regno
);
3856 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3857 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3861 if (regno
< FIRST_PSEUDO_REGISTER
)
3865 return lra_get_regno_hard_regno (regno
) < 0;
3868 fmt
= GET_RTX_FORMAT (code
);
3869 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3873 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3876 else if (fmt
[i
] == 'E')
3878 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3879 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3886 /* Process all regs in location *LOC and change them on equivalent
3887 substitution. Return true if any change was done. */
3889 loc_equivalence_change_p (rtx
*loc
)
3891 rtx subst
, reg
, x
= *loc
;
3892 bool result
= false;
3893 enum rtx_code code
= GET_CODE (x
);
3899 reg
= SUBREG_REG (x
);
3900 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3901 && GET_MODE (subst
) == VOIDmode
)
3903 /* We cannot reload debug location. Simplify subreg here
3904 while we know the inner mode. */
3905 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3906 GET_MODE (reg
), SUBREG_BYTE (x
));
3910 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3916 /* Scan all the operand sub-expressions. */
3917 fmt
= GET_RTX_FORMAT (code
);
3918 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3921 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3922 else if (fmt
[i
] == 'E')
3923 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3925 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3930 /* Similar to loc_equivalence_change_p, but for use as
3931 simplify_replace_fn_rtx callback. DATA is insn for which the
3932 elimination is done. If it null we don't do the elimination. */
3934 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3939 rtx subst
= (data
== NULL
3940 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx
) data
));
3947 /* Maximum number of generated reload insns per an insn. It is for
3948 preventing this pass cycling in a bug case. */
3949 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3951 /* The current iteration number of this LRA pass. */
3952 int lra_constraint_iter
;
3954 /* The current iteration number of this LRA pass after the last spill
3956 int lra_constraint_iter_after_spill
;
3958 /* True if we substituted equiv which needs checking register
3959 allocation correctness because the equivalent value contains
3960 allocatable hard registers or when we restore multi-register
3962 bool lra_risky_transformations_p
;
3964 /* Return true if REGNO is referenced in more than one block. */
3966 multi_block_pseudo_p (int regno
)
3968 basic_block bb
= NULL
;
3972 if (regno
< FIRST_PSEUDO_REGISTER
)
3975 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3977 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3978 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3983 /* Return true if LIST contains a deleted insn. */
3985 contains_deleted_insn_p (rtx list
)
3987 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3988 if (NOTE_P (XEXP (list
, 0))
3989 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3994 /* Return true if X contains a pseudo dying in INSN. */
3996 dead_pseudo_p (rtx x
, rtx insn
)
4003 return (insn
!= NULL_RTX
4004 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4005 code
= GET_CODE (x
);
4006 fmt
= GET_RTX_FORMAT (code
);
4007 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4011 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4014 else if (fmt
[i
] == 'E')
4016 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4017 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4024 /* Return true if INSN contains a dying pseudo in INSN right hand
4027 insn_rhs_dead_pseudo_p (rtx insn
)
4029 rtx set
= single_set (insn
);
4031 gcc_assert (set
!= NULL
);
4032 return dead_pseudo_p (SET_SRC (set
), insn
);
4035 /* Return true if any init insn of REGNO contains a dying pseudo in
4036 insn right hand side. */
4038 init_insn_rhs_dead_pseudo_p (int regno
)
4040 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
4045 return insn_rhs_dead_pseudo_p (insns
);
4046 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
4047 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
4052 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4053 reverse only if we have one init insn with given REGNO as a
4056 reverse_equiv_p (int regno
)
4060 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
4062 if (! INSN_P (XEXP (insns
, 0))
4063 || XEXP (insns
, 1) != NULL_RTX
)
4065 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
4067 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4070 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4071 call this function only for non-reverse equivalence. */
4073 contains_reloaded_insn_p (int regno
)
4076 rtx list
= ira_reg_equiv
[regno
].init_insns
;
4078 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4079 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
4080 || ! REG_P (SET_DEST (set
))
4081 || (int) REGNO (SET_DEST (set
)) != regno
)
4086 /* Entry function of LRA constraint pass. Return true if the
4087 constraint pass did change the code. */
4089 lra_constraints (bool first_p
)
4092 int i
, hard_regno
, new_insns_num
;
4093 unsigned int min_len
, new_min_len
, uid
;
4094 rtx set
, x
, reg
, dest_reg
;
4095 basic_block last_bb
;
4096 bitmap_head equiv_insn_bitmap
;
4099 lra_constraint_iter
++;
4100 if (lra_dump_file
!= NULL
)
4101 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4102 lra_constraint_iter
);
4103 lra_constraint_iter_after_spill
++;
4104 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
4106 ("Maximum number of LRA constraint passes is achieved (%d)\n",
4107 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
4109 lra_risky_transformations_p
= false;
4110 new_insn_uid_start
= get_max_uid ();
4111 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4112 /* Mark used hard regs for target stack size calulations. */
4113 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4114 if (lra_reg_info
[i
].nrefs
!= 0
4115 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4119 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4120 for (j
= 0; j
< nregs
; j
++)
4121 df_set_regs_ever_live (hard_regno
+ j
, true);
4123 /* Do elimination before the equivalence processing as we can spill
4124 some pseudos during elimination. */
4125 lra_eliminate (false, first_p
);
4126 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4127 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4128 if (lra_reg_info
[i
].nrefs
!= 0)
4130 ira_reg_equiv
[i
].profitable_p
= true;
4131 reg
= regno_reg_rtx
[i
];
4132 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4134 bool pseudo_p
= contains_reg_p (x
, false, false);
4136 /* After RTL transformation, we can not guarantee that
4137 pseudo in the substitution was not reloaded which might
4138 make equivalence invalid. For example, in reverse
4145 the memory address register was reloaded before the 2nd
4147 if ((! first_p
&& pseudo_p
)
4148 /* We don't use DF for compilation speed sake. So it
4149 is problematic to update live info when we use an
4150 equivalence containing pseudos in more than one
4152 || (pseudo_p
&& multi_block_pseudo_p (i
))
4153 /* If an init insn was deleted for some reason, cancel
4154 the equiv. We could update the equiv insns after
4155 transformations including an equiv insn deletion
4156 but it is not worthy as such cases are extremely
4158 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4159 /* If it is not a reverse equivalence, we check that a
4160 pseudo in rhs of the init insn is not dying in the
4161 insn. Otherwise, the live info at the beginning of
4162 the corresponding BB might be wrong after we
4163 removed the insn. When the equiv can be a
4164 constant, the right hand side of the init insn can
4166 || (! reverse_equiv_p (i
)
4167 && (init_insn_rhs_dead_pseudo_p (i
)
4168 /* If we reloaded the pseudo in an equivalence
4169 init insn, we can not remove the equiv init
4170 insns and the init insns might write into
4171 const memory in this case. */
4172 || contains_reloaded_insn_p (i
)))
4173 /* Prevent access beyond equivalent memory for
4174 paradoxical subregs. */
4176 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4177 > GET_MODE_SIZE (GET_MODE (x
)))))
4178 ira_reg_equiv
[i
].defined_p
= false;
4179 if (contains_reg_p (x
, false, true))
4180 ira_reg_equiv
[i
].profitable_p
= false;
4181 if (get_equiv (reg
) != reg
)
4182 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4185 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4187 /* We should add all insns containing pseudos which should be
4188 substituted by their equivalences. */
4189 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4190 lra_push_insn_by_uid (uid
);
4191 min_len
= lra_insn_stack_length ();
4195 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4197 curr_insn
= lra_pop_insn ();
4199 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4200 if (curr_bb
!= last_bb
)
4203 bb_reload_num
= lra_curr_reload_num
;
4205 if (min_len
> new_min_len
)
4207 min_len
= new_min_len
;
4210 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4212 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4213 MAX_RELOAD_INSNS_NUMBER
);
4215 if (DEBUG_INSN_P (curr_insn
))
4217 /* We need to check equivalence in debug insn and change
4218 pseudo to the equivalent value if necessary. */
4219 curr_id
= lra_get_insn_recog_data (curr_insn
);
4220 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4222 rtx old
= *curr_id
->operand_loc
[0];
4223 *curr_id
->operand_loc
[0]
4224 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4225 loc_equivalence_callback
, curr_insn
);
4226 if (old
!= *curr_id
->operand_loc
[0])
4228 lra_update_insn_regno_info (curr_insn
);
4233 else if (INSN_P (curr_insn
))
4235 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4237 dest_reg
= SET_DEST (set
);
4238 /* The equivalence pseudo could be set up as SUBREG in a
4239 case when it is a call restore insn in a mode
4240 different from the pseudo mode. */
4241 if (GET_CODE (dest_reg
) == SUBREG
)
4242 dest_reg
= SUBREG_REG (dest_reg
);
4243 if ((REG_P (dest_reg
)
4244 && (x
= get_equiv (dest_reg
)) != dest_reg
4245 /* Remove insns which set up a pseudo whose value
4246 can not be changed. Such insns might be not in
4247 init_insns because we don't update equiv data
4248 during insn transformations.
4250 As an example, let suppose that a pseudo got
4251 hard register and on the 1st pass was not
4252 changed to equivalent constant. We generate an
4253 additional insn setting up the pseudo because of
4254 secondary memory movement. Then the pseudo is
4255 spilled and we use the equiv constant. In this
4256 case we should remove the additional insn and
4257 this insn is not init_insns list. */
4258 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4259 /* Check that this is actually an insn setting
4260 up the equivalence. */
4261 || in_list_p (curr_insn
,
4263 [REGNO (dest_reg
)].init_insns
)))
4264 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4265 && in_list_p (curr_insn
,
4267 [REGNO (SET_SRC (set
))].init_insns
)))
4269 /* This is equiv init insn of pseudo which did not get a
4270 hard register -- remove the insn. */
4271 if (lra_dump_file
!= NULL
)
4273 fprintf (lra_dump_file
,
4274 " Removing equiv init insn %i (freq=%d)\n",
4275 INSN_UID (curr_insn
),
4276 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4277 dump_insn_slim (lra_dump_file
, curr_insn
);
4279 if (contains_reg_p (x
, true, false))
4280 lra_risky_transformations_p
= true;
4281 lra_set_insn_deleted (curr_insn
);
4285 curr_id
= lra_get_insn_recog_data (curr_insn
);
4286 curr_static_id
= curr_id
->insn_static_data
;
4287 init_curr_insn_input_reloads ();
4288 init_curr_operand_mode ();
4289 if (curr_insn_transform ())
4291 /* Check non-transformed insns too for equiv change as USE
4292 or CLOBBER don't need reloads but can contain pseudos
4293 being changed on their equivalences. */
4294 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4295 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4297 lra_update_insn_regno_info (curr_insn
);
4302 bitmap_clear (&equiv_insn_bitmap
);
4303 /* If we used a new hard regno, changed_p should be true because the
4304 hard reg is assigned to a new pseudo. */
4305 #ifdef ENABLE_CHECKING
4308 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4309 if (lra_reg_info
[i
].nrefs
!= 0
4310 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4312 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4314 for (j
= 0; j
< nregs
; j
++)
4315 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4322 /* Initiate the LRA constraint pass. It is done once per
4325 lra_constraints_init (void)
4329 /* Finalize the LRA constraint pass. It is done once per
4332 lra_constraints_finish (void)
4338 /* This page contains code to do inheritance/split
4341 /* Number of reloads passed so far in current EBB. */
4342 static int reloads_num
;
4344 /* Number of calls passed so far in current EBB. */
4345 static int calls_num
;
4347 /* Current reload pseudo check for validity of elements in
4349 static int curr_usage_insns_check
;
4351 /* Info about last usage of registers in EBB to do inheritance/split
4352 transformation. Inheritance transformation is done from a spilled
4353 pseudo and split transformations from a hard register or a pseudo
4354 assigned to a hard register. */
4357 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4358 value INSNS is valid. The insns is chain of optional debug insns
4359 and a finishing non-debug insn using the corresponding reg. The
4360 value is also used to mark the registers which are set up in the
4361 current insn. The negated insn uid is used for this. */
4363 /* Value of global reloads_num at the last insn in INSNS. */
4365 /* Value of global reloads_nums at the last insn in INSNS. */
4367 /* It can be true only for splitting. And it means that the restore
4368 insn should be put after insn given by the following member. */
4370 /* Next insns in the current EBB which use the original reg and the
4371 original reg value is not changed between the current insn and
4372 the next insns. In order words, e.g. for inheritance, if we need
4373 to use the original reg value again in the next insns we can try
4374 to use the value in a hard register from a reload insn of the
4379 /* Map: regno -> corresponding pseudo usage insns. */
4380 static struct usage_insns
*usage_insns
;
4383 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4385 usage_insns
[regno
].check
= curr_usage_insns_check
;
4386 usage_insns
[regno
].insns
= insn
;
4387 usage_insns
[regno
].reloads_num
= reloads_num
;
4388 usage_insns
[regno
].calls_num
= calls_num
;
4389 usage_insns
[regno
].after_p
= after_p
;
4392 /* The function is used to form list REGNO usages which consists of
4393 optional debug insns finished by a non-debug insn using REGNO.
4394 RELOADS_NUM is current number of reload insns processed so far. */
4396 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4398 rtx next_usage_insns
;
4400 if (usage_insns
[regno
].check
== curr_usage_insns_check
4401 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4402 && DEBUG_INSN_P (insn
))
4404 /* Check that we did not add the debug insn yet. */
4405 if (next_usage_insns
!= insn
4406 && (GET_CODE (next_usage_insns
) != INSN_LIST
4407 || XEXP (next_usage_insns
, 0) != insn
))
4408 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4411 else if (NONDEBUG_INSN_P (insn
))
4412 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4414 usage_insns
[regno
].check
= 0;
4417 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4418 register NEW_REG. Return true if any change was made. */
4420 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4423 bool result
= false;
4431 code
= GET_CODE (x
);
4432 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4434 enum machine_mode mode
= GET_MODE (*loc
);
4435 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4437 if (mode
!= inner_mode
)
4439 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4440 || ! SCALAR_INT_MODE_P (inner_mode
))
4441 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4443 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4449 /* Scan all the operand sub-expressions. */
4450 fmt
= GET_RTX_FORMAT (code
);
4451 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4455 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4458 else if (fmt
[i
] == 'E')
4460 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4461 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4468 /* Return first non-debug insn in list USAGE_INSNS. */
4470 skip_usage_debug_insns (rtx usage_insns
)
4474 /* Skip debug insns. */
4475 for (insn
= usage_insns
;
4476 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4477 insn
= XEXP (insn
, 1))
4482 /* Return true if we need secondary memory moves for insn in
4483 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4486 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4487 rtx usage_insns ATTRIBUTE_UNUSED
)
4489 #ifndef SECONDARY_MEMORY_NEEDED
4492 rtx insn
, set
, dest
;
4495 if (inher_cl
== ALL_REGS
4496 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4498 lra_assert (INSN_P (insn
));
4499 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4501 dest
= SET_DEST (set
);
4504 lra_assert (inher_cl
!= NO_REGS
);
4505 cl
= get_reg_class (REGNO (dest
));
4506 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4507 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4511 /* Registers involved in inheritance/split in the current EBB
4512 (inheritance/split pseudos and original registers). */
4513 static bitmap_head check_only_regs
;
4515 /* Do inheritance transformations for insn INSN, which defines (if
4516 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4517 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4518 form as the "insns" field of usage_insns. Return true if we
4519 succeed in such transformation.
4521 The transformations look like:
4524 ... p <- i (new insn)
4526 <- ... p ... <- ... i ...
4528 ... i <- p (new insn)
4529 <- ... p ... <- ... i ...
4531 <- ... p ... <- ... i ...
4532 where p is a spilled original pseudo and i is a new inheritance pseudo.
4535 The inheritance pseudo has the smallest class of two classes CL and
4536 class of ORIGINAL REGNO. */
4538 inherit_reload_reg (bool def_p
, int original_regno
,
4539 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4541 if (optimize_function_for_size_p (cfun
))
4544 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4545 rtx original_reg
= regno_reg_rtx
[original_regno
];
4546 rtx new_reg
, new_insns
, usage_insn
;
4548 lra_assert (! usage_insns
[original_regno
].after_p
);
4549 if (lra_dump_file
!= NULL
)
4550 fprintf (lra_dump_file
,
4551 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4552 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4554 if (lra_dump_file
!= NULL
)
4556 fprintf (lra_dump_file
,
4557 " Rejecting inheritance for %d "
4558 "because of disjoint classes %s and %s\n",
4559 original_regno
, reg_class_names
[cl
],
4560 reg_class_names
[rclass
]);
4561 fprintf (lra_dump_file
,
4562 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4566 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4567 /* We don't use a subset of two classes because it can be
4568 NO_REGS. This transformation is still profitable in most
4569 cases even if the classes are not intersected as register
4570 move is probably cheaper than a memory load. */
4571 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4573 if (lra_dump_file
!= NULL
)
4574 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4575 reg_class_names
[cl
], reg_class_names
[rclass
]);
4579 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4581 /* Reject inheritance resulting in secondary memory moves.
4582 Otherwise, there is a danger in LRA cycling. Also such
4583 transformation will be unprofitable. */
4584 if (lra_dump_file
!= NULL
)
4586 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4587 rtx set
= single_set (insn
);
4589 lra_assert (set
!= NULL_RTX
);
4591 rtx dest
= SET_DEST (set
);
4593 lra_assert (REG_P (dest
));
4594 fprintf (lra_dump_file
,
4595 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4596 "as secondary mem is needed\n",
4597 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4598 original_regno
, reg_class_names
[rclass
]);
4599 fprintf (lra_dump_file
,
4600 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4604 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4605 rclass
, "inheritance");
4608 lra_emit_move (original_reg
, new_reg
);
4610 lra_emit_move (new_reg
, original_reg
);
4611 new_insns
= get_insns ();
4613 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4615 if (lra_dump_file
!= NULL
)
4617 fprintf (lra_dump_file
,
4618 " Rejecting inheritance %d->%d "
4619 "as it results in 2 or more insns:\n",
4620 original_regno
, REGNO (new_reg
));
4621 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4622 fprintf (lra_dump_file
,
4623 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4627 substitute_pseudo (&insn
, original_regno
, new_reg
);
4628 lra_update_insn_regno_info (insn
);
4630 /* We now have a new usage insn for original regno. */
4631 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4632 if (lra_dump_file
!= NULL
)
4633 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4634 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4635 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4636 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4637 bitmap_set_bit (&check_only_regs
, original_regno
);
4638 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4640 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4641 "Add original<-inheritance");
4643 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4644 "Add inheritance<-original");
4645 while (next_usage_insns
!= NULL_RTX
)
4647 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4649 usage_insn
= next_usage_insns
;
4650 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4651 next_usage_insns
= NULL
;
4655 usage_insn
= XEXP (next_usage_insns
, 0);
4656 lra_assert (DEBUG_INSN_P (usage_insn
));
4657 next_usage_insns
= XEXP (next_usage_insns
, 1);
4659 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4660 lra_update_insn_regno_info (usage_insn
);
4661 if (lra_dump_file
!= NULL
)
4663 fprintf (lra_dump_file
,
4664 " Inheritance reuse change %d->%d (bb%d):\n",
4665 original_regno
, REGNO (new_reg
),
4666 BLOCK_FOR_INSN (usage_insn
)->index
);
4667 dump_insn_slim (lra_dump_file
, usage_insn
);
4670 if (lra_dump_file
!= NULL
)
4671 fprintf (lra_dump_file
,
4672 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4676 /* Return true if we need a caller save/restore for pseudo REGNO which
4677 was assigned to a hard register. */
4679 need_for_call_save_p (int regno
)
4681 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4682 return (usage_insns
[regno
].calls_num
< calls_num
4683 && (overlaps_hard_reg_set_p
4684 ((flag_use_caller_save
&&
4685 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4686 ? lra_reg_info
[regno
].actual_call_used_reg_set
4687 : call_used_reg_set
,
4688 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4689 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4690 PSEUDO_REGNO_MODE (regno
))));
4693 /* Global registers occurring in the current EBB. */
4694 static bitmap_head ebb_global_regs
;
4696 /* Return true if we need a split for hard register REGNO or pseudo
4697 REGNO which was assigned to a hard register.
4698 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4699 used for reloads since the EBB end. It is an approximation of the
4700 used hard registers in the split range. The exact value would
4701 require expensive calculations. If we were aggressive with
4702 splitting because of the approximation, the split pseudo will save
4703 the same hard register assignment and will be removed in the undo
4704 pass. We still need the approximation because too aggressive
4705 splitting would result in too inaccurate cost calculation in the
4706 assignment pass because of too many generated moves which will be
4707 probably removed in the undo pass. */
4709 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4711 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4713 lra_assert (hard_regno
>= 0);
4714 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4715 /* Don't split eliminable hard registers, otherwise we can
4716 split hard registers like hard frame pointer, which
4717 lives on BB start/end according to DF-infrastructure,
4718 when there is a pseudo assigned to the register and
4719 living in the same BB. */
4720 && (regno
>= FIRST_PSEUDO_REGISTER
4721 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4722 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4723 /* Don't split call clobbered hard regs living through
4724 calls, otherwise we might have a check problem in the
4725 assign sub-pass as in the most cases (exception is a
4726 situation when lra_risky_transformations_p value is
4727 true) the assign pass assumes that all pseudos living
4728 through calls are assigned to call saved hard regs. */
4729 && (regno
>= FIRST_PSEUDO_REGISTER
4730 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4731 || usage_insns
[regno
].calls_num
== calls_num
)
4732 /* We need at least 2 reloads to make pseudo splitting
4733 profitable. We should provide hard regno splitting in
4734 any case to solve 1st insn scheduling problem when
4735 moving hard register definition up might result in
4736 impossibility to find hard register for reload pseudo of
4737 small register class. */
4738 && (usage_insns
[regno
].reloads_num
4739 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4740 && (regno
< FIRST_PSEUDO_REGISTER
4741 /* For short living pseudos, spilling + inheritance can
4742 be considered a substitution for splitting.
4743 Therefore we do not splitting for local pseudos. It
4744 decreases also aggressiveness of splitting. The
4745 minimal number of references is chosen taking into
4746 account that for 2 references splitting has no sense
4747 as we can just spill the pseudo. */
4748 || (regno
>= FIRST_PSEUDO_REGISTER
4749 && lra_reg_info
[regno
].nrefs
> 3
4750 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4751 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4754 /* Return class for the split pseudo created from original pseudo with
4755 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4756 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4757 results in no secondary memory movements. */
4758 static enum reg_class
4759 choose_split_class (enum reg_class allocno_class
,
4760 int hard_regno ATTRIBUTE_UNUSED
,
4761 enum machine_mode mode ATTRIBUTE_UNUSED
)
4763 #ifndef SECONDARY_MEMORY_NEEDED
4764 return allocno_class
;
4767 enum reg_class cl
, best_cl
= NO_REGS
;
4768 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4769 = REGNO_REG_CLASS (hard_regno
);
4771 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4772 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4773 return allocno_class
;
4775 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4777 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4778 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4779 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4780 && (best_cl
== NO_REGS
4781 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4787 /* Do split transformations for insn INSN, which defines or uses
4788 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4789 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4790 "insns" field of usage_insns.
4792 The transformations look like:
4795 ... s <- p (new insn -- save)
4797 ... p <- s (new insn -- restore)
4798 <- ... p ... <- ... p ...
4800 <- ... p ... <- ... p ...
4801 ... s <- p (new insn -- save)
4803 ... p <- s (new insn -- restore)
4804 <- ... p ... <- ... p ...
4806 where p is an original pseudo got a hard register or a hard
4807 register and s is a new split pseudo. The save is put before INSN
4808 if BEFORE_P is true. Return true if we succeed in such
4811 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4813 enum reg_class rclass
;
4815 int hard_regno
, nregs
;
4816 rtx new_reg
, save
, restore
, usage_insn
;
4820 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4822 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4823 hard_regno
= original_regno
;
4824 call_save_p
= false;
4829 hard_regno
= reg_renumber
[original_regno
];
4830 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4831 rclass
= lra_get_allocno_class (original_regno
);
4832 original_reg
= regno_reg_rtx
[original_regno
];
4833 call_save_p
= need_for_call_save_p (original_regno
);
4835 original_reg
= regno_reg_rtx
[original_regno
];
4836 lra_assert (hard_regno
>= 0);
4837 if (lra_dump_file
!= NULL
)
4838 fprintf (lra_dump_file
,
4839 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4842 enum machine_mode mode
= GET_MODE (original_reg
);
4844 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4845 hard_regno_nregs
[hard_regno
][mode
],
4847 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4851 rclass
= choose_split_class (rclass
, hard_regno
,
4852 GET_MODE (original_reg
));
4853 if (rclass
== NO_REGS
)
4855 if (lra_dump_file
!= NULL
)
4857 fprintf (lra_dump_file
,
4858 " Rejecting split of %d(%s): "
4859 "no good reg class for %d(%s)\n",
4861 reg_class_names
[lra_get_allocno_class (original_regno
)],
4863 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4866 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4870 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4872 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4874 save
= emit_spill_move (true, new_reg
, original_reg
);
4875 if (NEXT_INSN (save
) != NULL_RTX
)
4877 lra_assert (! call_save_p
);
4878 if (lra_dump_file
!= NULL
)
4882 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4883 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4884 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4885 fprintf (lra_dump_file
,
4886 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4890 restore
= emit_spill_move (false, new_reg
, original_reg
);
4891 if (NEXT_INSN (restore
) != NULL_RTX
)
4893 lra_assert (! call_save_p
);
4894 if (lra_dump_file
!= NULL
)
4896 fprintf (lra_dump_file
,
4897 " Rejecting split %d->%d "
4898 "resulting in > 2 %s restore insns:\n",
4899 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4900 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4901 fprintf (lra_dump_file
,
4902 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4906 after_p
= usage_insns
[original_regno
].after_p
;
4907 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4908 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4909 bitmap_set_bit (&check_only_regs
, original_regno
);
4910 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4913 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4915 usage_insn
= next_usage_insns
;
4918 usage_insn
= XEXP (next_usage_insns
, 0);
4919 lra_assert (DEBUG_INSN_P (usage_insn
));
4920 next_usage_insns
= XEXP (next_usage_insns
, 1);
4921 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4922 lra_update_insn_regno_info (usage_insn
);
4923 if (lra_dump_file
!= NULL
)
4925 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4926 original_regno
, REGNO (new_reg
));
4927 dump_insn_slim (lra_dump_file
, usage_insn
);
4930 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4931 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4932 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4933 after_p
? restore
: NULL_RTX
,
4935 ? "Add reg<-save" : "Add reg<-split");
4936 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4937 before_p
? NULL_RTX
: save
,
4939 ? "Add save<-reg" : "Add split<-reg");
4941 /* If we are trying to split multi-register. We should check
4942 conflicts on the next assignment sub-pass. IRA can allocate on
4943 sub-register levels, LRA do this on pseudos level right now and
4944 this discrepancy may create allocation conflicts after
4946 lra_risky_transformations_p
= true;
4947 if (lra_dump_file
!= NULL
)
4948 fprintf (lra_dump_file
,
4949 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4953 /* Recognize that we need a split transformation for insn INSN, which
4954 defines or uses REGNO in its insn biggest MODE (we use it only if
4955 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4956 hard registers which might be used for reloads since the EBB end.
4957 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4958 uid before starting INSN processing. Return true if we succeed in
4959 such transformation. */
4961 split_if_necessary (int regno
, enum machine_mode mode
,
4962 HARD_REG_SET potential_reload_hard_regs
,
4963 bool before_p
, rtx insn
, int max_uid
)
4967 rtx next_usage_insns
;
4969 if (regno
< FIRST_PSEUDO_REGISTER
)
4970 nregs
= hard_regno_nregs
[regno
][mode
];
4971 for (i
= 0; i
< nregs
; i
++)
4972 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4973 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4974 /* To avoid processing the register twice or more. */
4975 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4976 && INSN_UID (next_usage_insns
) < max_uid
)
4977 || (GET_CODE (next_usage_insns
) == INSN_LIST
4978 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4979 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4980 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4985 /* Check only registers living at the current program point in the
4987 static bitmap_head live_regs
;
4989 /* Update live info in EBB given by its HEAD and TAIL insns after
4990 inheritance/split transformation. The function removes dead moves
4993 update_ebb_live_info (rtx head
, rtx tail
)
5000 basic_block last_bb
, prev_bb
, curr_bb
;
5002 struct lra_insn_reg
*reg
;
5006 last_bb
= BLOCK_FOR_INSN (tail
);
5008 for (curr_insn
= tail
;
5009 curr_insn
!= PREV_INSN (head
);
5010 curr_insn
= prev_insn
)
5012 prev_insn
= PREV_INSN (curr_insn
);
5013 /* We need to process empty blocks too. They contain
5014 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5015 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5017 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5018 if (curr_bb
!= prev_bb
)
5020 if (prev_bb
!= NULL
)
5022 /* Update df_get_live_in (prev_bb): */
5023 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5024 if (bitmap_bit_p (&live_regs
, j
))
5025 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5027 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5029 if (curr_bb
!= last_bb
)
5031 /* Update df_get_live_out (curr_bb): */
5032 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5034 live_p
= bitmap_bit_p (&live_regs
, j
);
5036 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5037 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5043 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5045 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5049 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5051 if (! NONDEBUG_INSN_P (curr_insn
))
5053 curr_id
= lra_get_insn_recog_data (curr_insn
);
5054 curr_static_id
= curr_id
->insn_static_data
;
5056 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
5057 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5058 && bitmap_bit_p (&check_only_regs
, regno
)
5059 && ! bitmap_bit_p (&live_regs
, regno
))
5061 /* See which defined values die here. */
5062 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5063 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5064 bitmap_clear_bit (&live_regs
, reg
->regno
);
5065 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5066 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5067 bitmap_clear_bit (&live_regs
, reg
->regno
);
5068 /* Mark each used value as live. */
5069 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5070 if (reg
->type
!= OP_OUT
5071 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5072 bitmap_set_bit (&live_regs
, reg
->regno
);
5073 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5074 if (reg
->type
!= OP_OUT
5075 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5076 bitmap_set_bit (&live_regs
, reg
->regno
);
5077 if (curr_id
->arg_hard_regs
!= NULL
)
5078 /* Make argument hard registers live. */
5079 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5080 if (bitmap_bit_p (&check_only_regs
, regno
))
5081 bitmap_set_bit (&live_regs
, regno
);
5082 /* It is quite important to remove dead move insns because it
5083 means removing dead store. We don't need to process them for
5087 if (lra_dump_file
!= NULL
)
5089 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5090 dump_insn_slim (lra_dump_file
, curr_insn
);
5092 lra_set_insn_deleted (curr_insn
);
5097 /* The structure describes info to do an inheritance for the current
5098 insn. We need to collect such info first before doing the
5099 transformations because the transformations change the insn
5100 internal representation. */
5103 /* Original regno. */
5105 /* Subsequent insns which can inherit original reg value. */
5109 /* Array containing all info for doing inheritance from the current
5111 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5113 /* Number elements in the previous array. */
5114 static int to_inherit_num
;
5116 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5117 structure to_inherit. */
5119 add_to_inherit (int regno
, rtx insns
)
5123 for (i
= 0; i
< to_inherit_num
; i
++)
5124 if (to_inherit
[i
].regno
== regno
)
5126 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5127 to_inherit
[to_inherit_num
].regno
= regno
;
5128 to_inherit
[to_inherit_num
++].insns
= insns
;
5131 /* Return the last non-debug insn in basic block BB, or the block begin
5134 get_last_insertion_point (basic_block bb
)
5138 FOR_BB_INSNS_REVERSE (bb
, insn
)
5139 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5144 /* Set up RES by registers living on edges FROM except the edge (FROM,
5145 TO) or by registers set up in a jump insn in BB FROM. */
5147 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5150 struct lra_insn_reg
*reg
;
5154 lra_assert (to
!= NULL
);
5156 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5158 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5159 last
= get_last_insertion_point (from
);
5160 if (! JUMP_P (last
))
5162 curr_id
= lra_get_insn_recog_data (last
);
5163 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5164 if (reg
->type
!= OP_IN
)
5165 bitmap_set_bit (res
, reg
->regno
);
5168 /* Used as a temporary results of some bitmap calculations. */
5169 static bitmap_head temp_bitmap
;
5171 /* We split for reloads of small class of hard regs. The following
5172 defines how many hard regs the class should have to be qualified as
5173 small. The code is mostly oriented to x86/x86-64 architecture
5174 where some insns need to use only specific register or pair of
5175 registers and these register can live in RTL explicitly, e.g. for
5176 parameter passing. */
5177 static const int max_small_class_regs_num
= 2;
5179 /* Do inheritance/split transformations in EBB starting with HEAD and
5180 finishing on TAIL. We process EBB insns in the reverse order.
5181 Return true if we did any inheritance/split transformation in the
5184 We should avoid excessive splitting which results in worse code
5185 because of inaccurate cost calculations for spilling new split
5186 pseudos in such case. To achieve this we do splitting only if
5187 register pressure is high in given basic block and there are reload
5188 pseudos requiring hard registers. We could do more register
5189 pressure calculations at any given program point to avoid necessary
5190 splitting even more but it is to expensive and the current approach
5191 works well enough. */
5193 inherit_in_ebb (rtx head
, rtx tail
)
5195 int i
, src_regno
, dst_regno
, nregs
;
5196 bool change_p
, succ_p
, update_reloads_num_p
;
5197 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
5199 struct lra_insn_reg
*reg
;
5200 basic_block last_processed_bb
, curr_bb
= NULL
;
5201 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5205 bool head_p
, after_p
;
5208 curr_usage_insns_check
++;
5209 reloads_num
= calls_num
= 0;
5210 bitmap_clear (&check_only_regs
);
5211 last_processed_bb
= NULL
;
5212 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5213 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5214 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5215 /* We don't process new insns generated in the loop. */
5216 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5218 prev_insn
= PREV_INSN (curr_insn
);
5219 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5220 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5221 if (last_processed_bb
!= curr_bb
)
5223 /* We are at the end of BB. Add qualified living
5224 pseudos for potential splitting. */
5225 to_process
= df_get_live_out (curr_bb
);
5226 if (last_processed_bb
!= NULL
)
5228 /* We are somewhere in the middle of EBB. */
5229 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5231 to_process
= &temp_bitmap
;
5233 last_processed_bb
= curr_bb
;
5234 last_insn
= get_last_insertion_point (curr_bb
);
5235 after_p
= (! JUMP_P (last_insn
)
5236 && (! CALL_P (last_insn
)
5237 || (find_reg_note (last_insn
,
5238 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5239 && ! SIBLING_CALL_P (last_insn
))));
5240 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5241 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5243 if ((int) j
>= lra_constraint_new_regno_start
)
5245 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5247 if (j
< FIRST_PSEUDO_REGISTER
)
5248 SET_HARD_REG_BIT (live_hard_regs
, j
);
5250 add_to_hard_reg_set (&live_hard_regs
,
5251 PSEUDO_REGNO_MODE (j
),
5253 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5257 src_regno
= dst_regno
= -1;
5258 if (NONDEBUG_INSN_P (curr_insn
)
5259 && (set
= single_set (curr_insn
)) != NULL_RTX
5260 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5262 src_regno
= REGNO (SET_SRC (set
));
5263 dst_regno
= REGNO (SET_DEST (set
));
5265 update_reloads_num_p
= true;
5266 if (src_regno
< lra_constraint_new_regno_start
5267 && src_regno
>= FIRST_PSEUDO_REGISTER
5268 && reg_renumber
[src_regno
] < 0
5269 && dst_regno
>= lra_constraint_new_regno_start
5270 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5272 /* 'reload_pseudo <- original_pseudo'. */
5273 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5275 update_reloads_num_p
= false;
5277 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5278 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5279 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5280 curr_insn
, next_usage_insns
);
5284 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5285 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5286 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5287 reg_class_contents
[cl
]);
5289 else if (src_regno
>= lra_constraint_new_regno_start
5290 && dst_regno
< lra_constraint_new_regno_start
5291 && dst_regno
>= FIRST_PSEUDO_REGISTER
5292 && reg_renumber
[dst_regno
] < 0
5293 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5294 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5295 && (next_usage_insns
5296 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5298 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5300 update_reloads_num_p
= false;
5301 /* 'original_pseudo <- reload_pseudo'. */
5302 if (! JUMP_P (curr_insn
)
5303 && inherit_reload_reg (true, dst_regno
, cl
,
5304 curr_insn
, next_usage_insns
))
5307 usage_insns
[dst_regno
].check
= 0;
5308 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5309 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5310 reg_class_contents
[cl
]);
5312 else if (INSN_P (curr_insn
))
5315 int max_uid
= get_max_uid ();
5317 curr_id
= lra_get_insn_recog_data (curr_insn
);
5318 curr_static_id
= curr_id
->insn_static_data
;
5320 /* Process insn definitions. */
5321 for (iter
= 0; iter
< 2; iter
++)
5322 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5325 if (reg
->type
!= OP_IN
5326 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5328 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5329 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5330 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5331 && (next_usage_insns
5332 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5334 struct lra_insn_reg
*r
;
5336 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5337 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5339 /* Don't do inheritance if the pseudo is also
5340 used in the insn. */
5342 /* We can not do inheritance right now
5343 because the current insn reg info (chain
5344 regs) can change after that. */
5345 add_to_inherit (dst_regno
, next_usage_insns
);
5347 /* We can not process one reg twice here because of
5348 usage_insns invalidation. */
5349 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5350 || reg_renumber
[dst_regno
] >= 0)
5351 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5355 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5356 potential_reload_hard_regs
,
5357 false, curr_insn
, max_uid
))
5359 CLEAR_HARD_REG_SET (s
);
5360 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5361 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5363 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5364 reg_renumber
[dst_regno
]);
5365 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5367 /* We should invalidate potential inheritance or
5368 splitting for the current insn usages to the next
5369 usage insns (see code below) as the output pseudo
5371 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5372 && reg_renumber
[dst_regno
] < 0)
5373 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5374 && (dst_regno
< FIRST_PSEUDO_REGISTER
5375 || reg_renumber
[dst_regno
] >= 0)))
5377 /* Invalidate and mark definitions. */
5378 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5379 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5382 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5383 for (i
= 0; i
< nregs
; i
++)
5384 usage_insns
[dst_regno
+ i
].check
5385 = -(int) INSN_UID (curr_insn
);
5389 if (! JUMP_P (curr_insn
))
5390 for (i
= 0; i
< to_inherit_num
; i
++)
5391 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5392 ALL_REGS
, curr_insn
,
5393 to_inherit
[i
].insns
))
5395 if (CALL_P (curr_insn
))
5397 rtx cheap
, pat
, dest
, restore
;
5398 int regno
, hard_regno
;
5401 if ((cheap
= find_reg_note (curr_insn
,
5402 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5403 && ((cheap
= XEXP (cheap
, 0)), true)
5404 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5405 && (hard_regno
= reg_renumber
[regno
]) >= 0
5406 /* If there are pending saves/restores, the
5407 optimization is not worth. */
5408 && usage_insns
[regno
].calls_num
== calls_num
- 1
5409 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5411 /* Restore the pseudo from the call result as
5412 REG_RETURNED note says that the pseudo value is
5413 in the call result and the pseudo is an argument
5415 pat
= PATTERN (curr_insn
);
5416 if (GET_CODE (pat
) == PARALLEL
)
5417 pat
= XVECEXP (pat
, 0, 0);
5418 dest
= SET_DEST (pat
);
5420 emit_move_insn (cheap
, copy_rtx (dest
));
5421 restore
= get_insns ();
5423 lra_process_new_insns (curr_insn
, NULL
, restore
,
5424 "Inserting call parameter restore");
5425 /* We don't need to save/restore of the pseudo from
5427 usage_insns
[regno
].calls_num
= calls_num
;
5428 bitmap_set_bit (&check_only_regs
, regno
);
5432 /* Process insn usages. */
5433 for (iter
= 0; iter
< 2; iter
++)
5434 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5437 if ((reg
->type
!= OP_OUT
5438 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5439 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5441 if (src_regno
>= FIRST_PSEUDO_REGISTER
5442 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5444 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5445 && (next_usage_insns
5446 = usage_insns
[src_regno
].insns
) != NULL_RTX
5447 && NONDEBUG_INSN_P (curr_insn
))
5448 add_to_inherit (src_regno
, next_usage_insns
);
5449 else if (usage_insns
[src_regno
].check
5450 != -(int) INSN_UID (curr_insn
))
5451 /* Add usages but only if the reg is not set up
5452 in the same insn. */
5453 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5455 else if (src_regno
< FIRST_PSEUDO_REGISTER
5456 || reg_renumber
[src_regno
] >= 0)
5459 rtx use_insn
= curr_insn
;
5461 before_p
= (JUMP_P (curr_insn
)
5462 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5463 if (NONDEBUG_INSN_P (curr_insn
)
5464 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5465 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5466 potential_reload_hard_regs
,
5467 before_p
, curr_insn
, max_uid
))
5470 lra_risky_transformations_p
= true;
5473 usage_insns
[src_regno
].check
= 0;
5475 use_insn
= PREV_INSN (curr_insn
);
5477 if (NONDEBUG_INSN_P (curr_insn
))
5479 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5480 add_to_hard_reg_set (&live_hard_regs
,
5481 reg
->biggest_mode
, src_regno
);
5483 add_to_hard_reg_set (&live_hard_regs
,
5484 PSEUDO_REGNO_MODE (src_regno
),
5485 reg_renumber
[src_regno
]);
5487 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5490 /* Process call args. */
5491 if (curr_id
->arg_hard_regs
!= NULL
)
5492 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5493 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5495 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5496 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5498 for (i
= 0; i
< to_inherit_num
; i
++)
5500 src_regno
= to_inherit
[i
].regno
;
5501 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5502 curr_insn
, to_inherit
[i
].insns
))
5505 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5508 if (update_reloads_num_p
5509 && NONDEBUG_INSN_P (curr_insn
)
5510 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5513 if ((REG_P (SET_DEST (set
))
5514 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5515 && reg_renumber
[regno
] < 0
5516 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5517 || (REG_P (SET_SRC (set
))
5518 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5519 && reg_renumber
[regno
] < 0
5520 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5522 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5524 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5525 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5526 reg_class_contents
[cl
]);
5529 /* We reached the start of the current basic block. */
5530 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5531 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5533 /* We reached the beginning of the current block -- do
5534 rest of spliting in the current BB. */
5535 to_process
= df_get_live_in (curr_bb
);
5536 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5538 /* We are somewhere in the middle of EBB. */
5539 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5540 curr_bb
, &temp_bitmap
);
5541 to_process
= &temp_bitmap
;
5544 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5546 if ((int) j
>= lra_constraint_new_regno_start
)
5548 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5549 && usage_insns
[j
].check
== curr_usage_insns_check
5550 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5552 if (need_for_split_p (potential_reload_hard_regs
, j
))
5554 if (lra_dump_file
!= NULL
&& head_p
)
5556 fprintf (lra_dump_file
,
5557 " ----------------------------------\n");
5560 if (split_reg (false, j
, bb_note (curr_bb
),
5564 usage_insns
[j
].check
= 0;
5572 /* This value affects EBB forming. If probability of edge from EBB to
5573 a BB is not greater than the following value, we don't add the BB
5575 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5577 /* Current number of inheritance/split iteration. */
5578 int lra_inheritance_iter
;
5580 /* Entry function for inheritance/split pass. */
5582 lra_inheritance (void)
5585 basic_block bb
, start_bb
;
5588 lra_inheritance_iter
++;
5589 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5591 timevar_push (TV_LRA_INHERITANCE
);
5592 if (lra_dump_file
!= NULL
)
5593 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5594 lra_inheritance_iter
);
5595 curr_usage_insns_check
= 0;
5596 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5597 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5598 usage_insns
[i
].check
= 0;
5599 bitmap_initialize (&check_only_regs
, ®_obstack
);
5600 bitmap_initialize (&live_regs
, ®_obstack
);
5601 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5602 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5603 FOR_EACH_BB_FN (bb
, cfun
)
5606 if (lra_dump_file
!= NULL
)
5607 fprintf (lra_dump_file
, "EBB");
5608 /* Form a EBB starting with BB. */
5609 bitmap_clear (&ebb_global_regs
);
5610 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5613 if (lra_dump_file
!= NULL
)
5614 fprintf (lra_dump_file
, " %d", bb
->index
);
5615 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5616 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5618 e
= find_fallthru_edge (bb
->succs
);
5621 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5625 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5626 if (lra_dump_file
!= NULL
)
5627 fprintf (lra_dump_file
, "\n");
5628 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5629 /* Remember that the EBB head and tail can change in
5631 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5633 bitmap_clear (&ebb_global_regs
);
5634 bitmap_clear (&temp_bitmap
);
5635 bitmap_clear (&live_regs
);
5636 bitmap_clear (&check_only_regs
);
5639 timevar_pop (TV_LRA_INHERITANCE
);
5644 /* This page contains code to undo failed inheritance/split
5647 /* Current number of iteration undoing inheritance/split. */
5648 int lra_undo_inheritance_iter
;
5650 /* Fix BB live info LIVE after removing pseudos created on pass doing
5651 inheritance/split which are REMOVED_PSEUDOS. */
5653 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5658 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5659 if (bitmap_clear_bit (live
, regno
))
5660 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5663 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5668 if (GET_CODE (reg
) == SUBREG
)
5669 reg
= SUBREG_REG (reg
);
5675 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5676 return true if we did any change. The undo transformations for
5677 inheritance looks like
5681 p <- i, i <- p, and i <- i3
5682 where p is original pseudo from which inheritance pseudo i was
5683 created, i and i3 are removed inheritance pseudos, i2 is another
5684 not removed inheritance pseudo. All split pseudos or other
5685 occurrences of removed inheritance pseudos are changed on the
5686 corresponding original pseudos.
5688 The function also schedules insns changed and created during
5689 inheritance/split pass for processing by the subsequent constraint
5692 remove_inheritance_pseudos (bitmap remove_pseudos
)
5695 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5696 rtx set
, prev_set
, prev_insn
;
5697 bool change_p
, done_p
;
5699 change_p
= ! bitmap_empty_p (remove_pseudos
);
5700 /* We can not finish the function right away if CHANGE_P is true
5701 because we need to marks insns affected by previous
5702 inheritance/split pass for processing by the subsequent
5704 FOR_EACH_BB_FN (bb
, cfun
)
5706 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5707 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5708 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5710 if (! INSN_P (curr_insn
))
5713 sregno
= dregno
= -1;
5714 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5715 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5717 dregno
= get_regno (SET_DEST (set
));
5718 sregno
= get_regno (SET_SRC (set
));
5721 if (sregno
>= 0 && dregno
>= 0)
5723 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5724 && (lra_reg_info
[sregno
].restore_regno
== dregno
5725 || (bitmap_bit_p (remove_pseudos
, dregno
)
5726 && (lra_reg_info
[sregno
].restore_regno
5727 == lra_reg_info
[dregno
].restore_regno
))))
5728 || (bitmap_bit_p (remove_pseudos
, dregno
)
5729 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5730 /* One of the following cases:
5731 original <- removed inheritance pseudo
5732 removed inherit pseudo <- another removed inherit pseudo
5733 removed inherit pseudo <- original pseudo
5735 removed_split_pseudo <- original_reg
5736 original_reg <- removed_split_pseudo */
5738 if (lra_dump_file
!= NULL
)
5740 fprintf (lra_dump_file
, " Removing %s:\n",
5741 bitmap_bit_p (&lra_split_regs
, sregno
)
5742 || bitmap_bit_p (&lra_split_regs
, dregno
)
5743 ? "split" : "inheritance");
5744 dump_insn_slim (lra_dump_file
, curr_insn
);
5746 lra_set_insn_deleted (curr_insn
);
5749 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5750 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5752 /* Search the following pattern:
5753 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5754 original_pseudo <- inherit_or_split_pseudo1
5755 where the 2nd insn is the current insn and
5756 inherit_or_split_pseudo2 is not removed. If it is found,
5757 change the current insn onto:
5758 original_pseudo <- inherit_or_split_pseudo2. */
5759 for (prev_insn
= PREV_INSN (curr_insn
);
5760 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5761 prev_insn
= PREV_INSN (prev_insn
))
5763 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5764 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5765 /* There should be no subregs in insn we are
5766 searching because only the original reg might
5767 be in subreg when we changed the mode of
5768 load/store for splitting. */
5769 && REG_P (SET_DEST (prev_set
))
5770 && REG_P (SET_SRC (prev_set
))
5771 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5772 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5773 >= FIRST_PSEUDO_REGISTER
)
5774 /* As we consider chain of inheritance or
5775 splitting described in above comment we should
5776 check that sregno and prev_sregno were
5777 inheritance/split pseudos created from the
5778 same original regno. */
5779 && (lra_reg_info
[sregno
].restore_regno
5780 == lra_reg_info
[prev_sregno
].restore_regno
)
5781 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5783 lra_assert (GET_MODE (SET_SRC (prev_set
))
5784 == GET_MODE (regno_reg_rtx
[sregno
]));
5785 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5786 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5788 SET_SRC (set
) = SET_SRC (prev_set
);
5789 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5790 lra_set_used_insn_alternative_by_uid
5791 (INSN_UID (curr_insn
), -1);
5793 if (lra_dump_file
!= NULL
)
5795 fprintf (lra_dump_file
, " Change reload insn:\n");
5796 dump_insn_slim (lra_dump_file
, curr_insn
);
5803 struct lra_insn_reg
*reg
;
5804 bool restored_regs_p
= false;
5805 bool kept_regs_p
= false;
5807 curr_id
= lra_get_insn_recog_data (curr_insn
);
5808 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5811 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5812 if (restore_regno
>= 0)
5814 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5816 substitute_pseudo (&curr_insn
, regno
,
5817 regno_reg_rtx
[restore_regno
]);
5818 restored_regs_p
= true;
5824 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5826 /* The instruction has changed since the previous
5827 constraints pass. */
5828 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5829 lra_set_used_insn_alternative_by_uid
5830 (INSN_UID (curr_insn
), -1);
5832 else if (restored_regs_p
)
5833 /* The instruction has been restored to the form that
5834 it had during the previous constraints pass. */
5835 lra_update_insn_regno_info (curr_insn
);
5836 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5838 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5839 dump_insn_slim (lra_dump_file
, curr_insn
);
5847 /* If optional reload pseudos failed to get a hard register or was not
5848 inherited, it is better to remove optional reloads. We do this
5849 transformation after undoing inheritance to figure out necessity to
5850 remove optional reloads easier. Return true if we do any
5853 undo_optional_reloads (void)
5855 bool change_p
, keep_p
;
5856 unsigned int regno
, uid
;
5857 bitmap_iterator bi
, bi2
;
5858 rtx insn
, set
, src
, dest
;
5859 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5861 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5862 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5863 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5866 /* Keep optional reloads from previous subpasses. */
5867 if (lra_reg_info
[regno
].restore_regno
< 0
5868 /* If the original pseudo changed its allocation, just
5869 removing the optional pseudo is dangerous as the original
5870 pseudo will have longer live range. */
5871 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5873 else if (reg_renumber
[regno
] >= 0)
5874 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5876 insn
= lra_insn_recog_data
[uid
]->insn
;
5877 if ((set
= single_set (insn
)) == NULL_RTX
)
5879 src
= SET_SRC (set
);
5880 dest
= SET_DEST (set
);
5881 if (! REG_P (src
) || ! REG_P (dest
))
5883 if (REGNO (dest
) == regno
5884 /* Ignore insn for optional reloads itself. */
5885 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5886 /* Check only inheritance on last inheritance pass. */
5887 && (int) REGNO (src
) >= new_regno_start
5888 /* Check that the optional reload was inherited. */
5889 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5897 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5898 if (lra_dump_file
!= NULL
)
5899 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5902 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5903 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5904 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5906 if (lra_dump_file
!= NULL
)
5907 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5908 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5909 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5911 insn
= lra_insn_recog_data
[uid
]->insn
;
5912 if ((set
= single_set (insn
)) != NULL_RTX
)
5914 src
= SET_SRC (set
);
5915 dest
= SET_DEST (set
);
5916 if (REG_P (src
) && REG_P (dest
)
5917 && ((REGNO (src
) == regno
5918 && (lra_reg_info
[regno
].restore_regno
5919 == (int) REGNO (dest
)))
5920 || (REGNO (dest
) == regno
5921 && (lra_reg_info
[regno
].restore_regno
5922 == (int) REGNO (src
)))))
5924 if (lra_dump_file
!= NULL
)
5926 fprintf (lra_dump_file
, " Deleting move %u\n",
5928 dump_insn_slim (lra_dump_file
, insn
);
5930 lra_set_insn_deleted (insn
);
5933 /* We should not worry about generation memory-memory
5934 moves here as if the corresponding inheritance did
5935 not work (inheritance pseudo did not get a hard reg),
5936 we remove the inheritance pseudo and the optional
5939 substitute_pseudo (&insn
, regno
,
5940 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5941 lra_update_insn_regno_info (insn
);
5942 if (lra_dump_file
!= NULL
)
5944 fprintf (lra_dump_file
,
5945 " Restoring original insn:\n");
5946 dump_insn_slim (lra_dump_file
, insn
);
5950 /* Clear restore_regnos. */
5951 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5952 lra_reg_info
[regno
].restore_regno
= -1;
5953 bitmap_clear (&insn_bitmap
);
5954 bitmap_clear (&removed_optional_reload_pseudos
);
5958 /* Entry function for undoing inheritance/split transformation. Return true
5959 if we did any RTL change in this pass. */
5961 lra_undo_inheritance (void)
5964 int restore_regno
, hard_regno
;
5965 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5966 bitmap_head remove_pseudos
;
5970 lra_undo_inheritance_iter
++;
5971 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5973 if (lra_dump_file
!= NULL
)
5974 fprintf (lra_dump_file
,
5975 "\n********** Undoing inheritance #%d: **********\n\n",
5976 lra_undo_inheritance_iter
);
5977 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5978 n_inherit
= n_all_inherit
= 0;
5979 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5980 if (lra_reg_info
[regno
].restore_regno
>= 0)
5983 if (reg_renumber
[regno
] < 0
5984 /* If the original pseudo changed its allocation, just
5985 removing inheritance is dangerous as for changing
5986 allocation we used shorter live-ranges. */
5987 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5988 bitmap_set_bit (&remove_pseudos
, regno
);
5992 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5993 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5994 n_inherit
, n_all_inherit
,
5995 (double) n_inherit
/ n_all_inherit
* 100);
5996 n_split
= n_all_split
= 0;
5997 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5998 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
6001 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6002 ? reg_renumber
[restore_regno
] : restore_regno
);
6003 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6004 bitmap_set_bit (&remove_pseudos
, regno
);
6008 if (lra_dump_file
!= NULL
)
6009 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6010 regno
, restore_regno
);
6013 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6014 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6015 n_split
, n_all_split
,
6016 (double) n_split
/ n_all_split
* 100);
6017 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6018 bitmap_clear (&remove_pseudos
);
6019 /* Clear restore_regnos. */
6020 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6021 lra_reg_info
[regno
].restore_regno
= -1;
6022 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6023 lra_reg_info
[regno
].restore_regno
= -1;
6024 change_p
= undo_optional_reloads () || change_p
;