gcc/config/riscv/riscv-vector-builtins-types.def

   1 /* Intrinsic type iterators for RISC-V 'V' Extension for GNU compiler.
   2    Copyright (C) 2022-2024 Free Software Foundation, Inc.
   3    Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3, or (at your option)
  10 any later version.
  11
  12 GCC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING3. If not see
  19 <http://www.gnu.org/licenses/>. */
  20
  21 /* Use "DEF_RVV_I_OPS" macro include all signed integer which will be
  22    iterated and registered as intrinsic functions.  */
  23 #ifndef DEF_RVV_I_OPS
  24 #define DEF_RVV_I_OPS(TYPE, REQUIRE)
  25 #endif
  26
  27 /* Use "DEF_RVV_U_OPS" macro include all unsigned integer which will be
  28    iterated and registered as intrinsic functions.  */
  29 #ifndef DEF_RVV_U_OPS
  30 #define DEF_RVV_U_OPS(TYPE, REQUIRE)
  31 #endif
  32
  33 /* Use "DEF_RVV_F_OPS" macro include all floating-point which will be
  34    iterated and registered as intrinsic functions.  */
  35 #ifndef DEF_RVV_F_OPS
  36 #define DEF_RVV_F_OPS(TYPE, REQUIRE)
  37 #endif
  38
  39 /* Use "DEF_RVV_B_OPS" macro include all bool value which will be
  40    iterated and registered as intrinsic functions.  */
  41 #ifndef DEF_RVV_B_OPS
  42 #define DEF_RVV_B_OPS(TYPE, REQUIRE)
  43 #endif
  44
  45 /* Use "DEF_RVV_WEXTI_OPS" macro include Double-Widening signed integer which
  46    will be iterated and registered as intrinsic functions.  */
  47 #ifndef DEF_RVV_WEXTI_OPS
  48 #define DEF_RVV_WEXTI_OPS(TYPE, REQUIRE)
  49 #endif
  50
  51 /* Use "DEF_RVV_QEXTI_OPS" macro include Quad-Widening signed integer which will
  52    be iterated and registered as intrinsic functions.  */
  53 #ifndef DEF_RVV_QEXTI_OPS
  54 #define DEF_RVV_QEXTI_OPS(TYPE, REQUIRE)
  55 #endif
  56
  57 /* Use "DEF_RVV_OEXTI_OPS" macro include Oct-Widening signed integer which will
  58    be iterated and registered as intrinsic functions.  */
  59 #ifndef DEF_RVV_OEXTI_OPS
  60 #define DEF_RVV_OEXTI_OPS(TYPE, REQUIRE)
  61 #endif
  62
  63 /* Use "DEF_RVV_WEXTU_OPS" macro include Double-Widening unsigned integer which
  64    will be iterated and registered as intrinsic functions.  */
  65 #ifndef DEF_RVV_WEXTU_OPS
  66 #define DEF_RVV_WEXTU_OPS(TYPE, REQUIRE)
  67 #endif
  68
  69 /* Use "DEF_RVV_QEXTU_OPS" macro include Quad-Widening unsigned integer which
  70    will be iterated and registered as intrinsic functions.  */
  71 #ifndef DEF_RVV_QEXTU_OPS
  72 #define DEF_RVV_QEXTU_OPS(TYPE, REQUIRE)
  73 #endif
  74
  75 /* Use "DEF_RVV_OEXTU_OPS" macro include Oct-Widening unsigned integer which
  76    will be iterated and registered as intrinsic functions.  */
  77 #ifndef DEF_RVV_OEXTU_OPS
  78 #define DEF_RVV_OEXTU_OPS(TYPE, REQUIRE)
  79 #endif
  80
  81 /* Use "DEF_RVV_FULL_V_I_OPS" macro include all signed integer that require full
  82    'V' extension which will be iterated and registered as intrinsic functions.
  83  */
  84 #ifndef DEF_RVV_FULL_V_I_OPS
  85 #define DEF_RVV_FULL_V_I_OPS(TYPE, REQUIRE)
  86 #endif
  87
  88 /* Use "DEF_RVV_FULL_V_U_OPS" macro include all unsigned integer that require
  89    full 'V' extension which will be iterated and registered as intrinsic
  90    functions.  */
  91 #ifndef DEF_RVV_FULL_V_U_OPS
  92 #define DEF_RVV_FULL_V_U_OPS(TYPE, REQUIRE)
  93 #endif
  94
  95 /* Use "DEF_RVV_WEXTF_OPS" macro include Double-Widening float which
  96    will be iterated and registered as intrinsic functions.  */
  97 #ifndef DEF_RVV_WEXTF_OPS
  98 #define DEF_RVV_WEXTF_OPS(TYPE, REQUIRE)
  99 #endif
 100
 101 /* Use "DEF_RVV_CONVERT_I_OPS" macro include all integer that will be converted
 102    in the float with same nunits which will be iterated and registered as
 103    intrinsic functions.  */
 104 #ifndef DEF_RVV_CONVERT_I_OPS
 105 #define DEF_RVV_CONVERT_I_OPS(TYPE, REQUIRE)
 106 #endif
 107
 108 /* Use "DEF_RVV_CONVERT_U_OPS" macro include all unsigned integer that will be
 109    converted in the float with same nunits which will be iterated and registered
 110    as intrinsic functions.  */
 111 #ifndef DEF_RVV_CONVERT_U_OPS
 112 #define DEF_RVV_CONVERT_U_OPS(TYPE, REQUIRE)
 113 #endif
 114
 115 /* Use "DEF_RVV_WCONVERT_I_OPS" macro include all integer that will be widen
 116    converted in the float with same nunits which will be iterated and registered
 117    as intrinsic functions.  */
 118 #ifndef DEF_RVV_WCONVERT_I_OPS
 119 #define DEF_RVV_WCONVERT_I_OPS(TYPE, REQUIRE)
 120 #endif
 121
 122 /* Use "DEF_RVV_WCONVERT_U_OPS" macro include all unsigned integer that will be
 123    widen converted in the float with same nunits which will be iterated and
 124    registered as intrinsic functions.  */
 125 #ifndef DEF_RVV_WCONVERT_U_OPS
 126 #define DEF_RVV_WCONVERT_U_OPS(TYPE, REQUIRE)
 127 #endif
 128
 129 /* Use "DEF_RVV_WCONVERT_F_OPS" macro include all unsigned integer that will be
 130    widen converted in the float with same nunits which will be iterated and
 131    registered as intrinsic functions.  */
 132 #ifndef DEF_RVV_WCONVERT_F_OPS
 133 #define DEF_RVV_WCONVERT_F_OPS(TYPE, REQUIRE)
 134 #endif
 135
 136 /* Use "DEF_RVV_WI_OPS" macro include all signed integer can be widened which
 137    will be iterated and registered as intrinsic functions.  */
 138 #ifndef DEF_RVV_WI_OPS
 139 #define DEF_RVV_WI_OPS(TYPE, REQUIRE)
 140 #endif
 141
 142 /* Use "DEF_RVV_WU_OPS" macro include all unsigned integer can be widened which
 143    will be iterated and registered as intrinsic functions.  */
 144 #ifndef DEF_RVV_WU_OPS
 145 #define DEF_RVV_WU_OPS(TYPE, REQUIRE)
 146 #endif
 147
 148 /* Use "DEF_RVV_WF_OPS" macro include all floating-point can be widened which
 149    will be iterated and registered as intrinsic functions.  */
 150 #ifndef DEF_RVV_WF_OPS
 151 #define DEF_RVV_WF_OPS(TYPE, REQUIRE)
 152 #endif
 153
 154 /* Use "DEF_RVV_EI16_OPS" macro include all types for vrgatherei16 which will be
 155    iterated and registered as intrinsic functions.  */
 156 #ifndef DEF_RVV_EI16_OPS
 157 #define DEF_RVV_EI16_OPS(TYPE, REQUIRE)
 158 #endif
 159
 160 /* Use "DEF_RVV_EEW8_INTERPRET_OPS" macro include all types for EEW8 vinterpret
 161    which will be iterated and registered as intrinsic functions.  */
 162 #ifndef DEF_RVV_EEW8_INTERPRET_OPS
 163 #define DEF_RVV_EEW8_INTERPRET_OPS(TYPE, REQUIRE)
 164 #endif
 165
 166 /* Use "DEF_RVV_EEW16_INTERPRET_OPS" macro include all types for EEW16
 167    vinterpret which will be iterated and registered as intrinsic functions.  */
 168 #ifndef DEF_RVV_EEW16_INTERPRET_OPS
 169 #define DEF_RVV_EEW16_INTERPRET_OPS(TYPE, REQUIRE)
 170 #endif
 171
 172 /* Use "DEF_RVV_EEW32_INTERPRET_OPS" macro include all types for EEW32
 173    vinterpret which will be iterated and registered as intrinsic functions.  */
 174 #ifndef DEF_RVV_EEW32_INTERPRET_OPS
 175 #define DEF_RVV_EEW32_INTERPRET_OPS(TYPE, REQUIRE)
 176 #endif
 177
 178 /* Use "DEF_RVV_EEW64_INTERPRET_OPS" macro include all types for EEW64
 179    vinterpret which will be iterated and registered as intrinsic functions.  */
 180 #ifndef DEF_RVV_EEW64_INTERPRET_OPS
 181 #define DEF_RVV_EEW64_INTERPRET_OPS(TYPE, REQUIRE)
 182 #endif
 183
 184 /* Use "DEF_RVV_BOOL1_INTERPRET_OPS" macro include all types for BOOL1
 185    vinterpret which will be iterated and registered as intrinsic functions.  */
 186 #ifndef DEF_RVV_BOOL1_INTERPRET_OPS
 187 #define DEF_RVV_BOOL1_INTERPRET_OPS(TYPE, REQUIRE)
 188 #endif
 189
 190 /* Use "DEF_RVV_BOOL2_INTERPRET_OPS" macro include all types for BOOL2
 191    vinterpret which will be iterated and registered as intrinsic functions.  */
 192 #ifndef DEF_RVV_BOOL2_INTERPRET_OPS
 193 #define DEF_RVV_BOOL2_INTERPRET_OPS(TYPE, REQUIRE)
 194 #endif
 195
 196 /* Use "DEF_RVV_BOOL4_INTERPRET_OPS" macro include all types for BOOL4
 197    vinterpret which will be iterated and registered as intrinsic functions.  */
 198 #ifndef DEF_RVV_BOOL4_INTERPRET_OPS
 199 #define DEF_RVV_BOOL4_INTERPRET_OPS(TYPE, REQUIRE)
 200 #endif
 201
 202 /* Use "DEF_RVV_BOOL8_INTERPRET_OPS" macro include all types for BOOL8
 203    vinterpret which will be iterated and registered as intrinsic functions.  */
 204 #ifndef DEF_RVV_BOOL8_INTERPRET_OPS
 205 #define DEF_RVV_BOOL8_INTERPRET_OPS(TYPE, REQUIRE)
 206 #endif
 207
 208 /* Use "DEF_RVV_BOOL16_INTERPRET_OPS" macro include all types for BOOL16
 209    vinterpret which will be iterated and registered as intrinsic functions.  */
 210 #ifndef DEF_RVV_BOOL16_INTERPRET_OPS
 211 #define DEF_RVV_BOOL16_INTERPRET_OPS(TYPE, REQUIRE)
 212 #endif
 213
 214 /* Use "DEF_RVV_BOOL32_INTERPRET_OPS" macro include all types for BOOL32
 215    vinterpret which will be iterated and registered as intrinsic functions.  */
 216 #ifndef DEF_RVV_BOOL32_INTERPRET_OPS
 217 #define DEF_RVV_BOOL32_INTERPRET_OPS(TYPE, REQUIRE)
 218 #endif
 219
 220 /* Use "DEF_RVV_BOOL64_INTERPRET_OPS" macro include all types for BOOL64
 221    vinterpret which will be iterated and registered as intrinsic functions.  */
 222 #ifndef DEF_RVV_BOOL64_INTERPRET_OPS
 223 #define DEF_RVV_BOOL64_INTERPRET_OPS(TYPE, REQUIRE)
 224 #endif
 225
 226 /* Use "DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS" macro include all types for
 227    INT8M1 vinterpret which will be iterated and registered as intrinsic
 228    functions.  */
 229 #ifndef DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS
 230 #define DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
 231 #endif
 232
 233 /* Use "DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS" macro include all types for
 234    INT16M1 vinterpret which will be iterated and registered as intrinsic
 235    functions.  */
 236 #ifndef DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS
 237 #define DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
 238 #endif
 239
 240 /* Use "DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS" macro include all types for
 241    INT32M1 vinterpret which will be iterated and registered as intrinsic
 242    functions.  */
 243 #ifndef DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS
 244 #define DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
 245 #endif
 246
 247 /* Use "DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS" macro include all types for
 248    INT64M1 vinterpret which will be iterated and registered as intrinsic
 249    functions.  */
 250 #ifndef DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS
 251 #define DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
 252 #endif
 253
 254 /* Use "DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS" macro include all types for
 255    UINT8M1 vinterpret which will be iterated and registered as intrinsic
 256    functions.  */
 257 #ifndef DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS
 258 #define DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
 259 #endif
 260
 261 /* Use "DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS" macro include all types for
 262    UINT16M1 vinterpret which will be iterated and registered as intrinsic
 263    functions.  */
 264 #ifndef DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS
 265 #define DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
 266 #endif
 267
 268 /* Use "DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS" macro include all types for
 269    UINT32M1 vinterpret which will be iterated and registered as intrinsic
 270    functions.  */
 271 #ifndef DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS
 272 #define DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
 273 #endif
 274
 275 /* Use "DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS" macro include all types for
 276    UINT64M1 vinterpret which will be iterated and registered as intrinsic
 277    functions.  */
 278 #ifndef DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS
 279 #define DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
 280 #endif
 281
 282 /* Use "DEF_RVV_X2_VLMUL_EXT_OPS" macro include all types for X2 VLMUL EXT
 283    which will be iterated and registered as intrinsic functions.  */
 284 #ifndef DEF_RVV_X2_VLMUL_EXT_OPS
 285 #define DEF_RVV_X2_VLMUL_EXT_OPS(TYPE, REQUIRE)
 286 #endif
 287
 288 /* Use "DEF_RVV_X4_VLMUL_EXT_OPS" macro include all types for X4 VLMUL EXT
 289    which will be iterated and registered as intrinsic functions.  */
 290 #ifndef DEF_RVV_X4_VLMUL_EXT_OPS
 291 #define DEF_RVV_X4_VLMUL_EXT_OPS(TYPE, REQUIRE)
 292 #endif
 293
 294 /* Use "DEF_RVV_X8_VLMUL_EXT_OPS" macro include all types for X8 VLMUL EXT
 295    which will be iterated and registered as intrinsic functions.  */
 296 #ifndef DEF_RVV_X8_VLMUL_EXT_OPS
 297 #define DEF_RVV_X8_VLMUL_EXT_OPS(TYPE, REQUIRE)
 298 #endif
 299
 300 /* Use "DEF_RVV_X16_VLMUL_EXT_OPS" macro include all types for X16 VLMUL EXT
 301    which will be iterated and registered as intrinsic functions.  */
 302 #ifndef DEF_RVV_X16_VLMUL_EXT_OPS
 303 #define DEF_RVV_X16_VLMUL_EXT_OPS(TYPE, REQUIRE)
 304 #endif
 305
 306 /* Use "DEF_RVV_X32_VLMUL_EXT_OPS" macro include all types for X32 VLMUL EXT
 307    which will be iterated and registered as intrinsic functions.  */
 308 #ifndef DEF_RVV_X32_VLMUL_EXT_OPS
 309 #define DEF_RVV_X32_VLMUL_EXT_OPS(TYPE, REQUIRE)
 310 #endif
 311
 312 /* Use "DEF_RVV_X64_VLMUL_EXT_OPS" macro include all types for X64 VLMUL EXT
 313    which will be iterated and registered as intrinsic functions.  */
 314 #ifndef DEF_RVV_X64_VLMUL_EXT_OPS
 315 #define DEF_RVV_X64_VLMUL_EXT_OPS(TYPE, REQUIRE)
 316 #endif
 317
 318 /* Use "DEF_RVV_LMUL1_OPS" macro include all types for LMUL1
 319    which will be iterated and registered as intrinsic functions.  */
 320 #ifndef DEF_RVV_LMUL1_OPS
 321 #define DEF_RVV_LMUL1_OPS(TYPE, REQUIRE)
 322 #endif
 323
 324 /* Use "DEF_RVV_LMUL2_OPS" macro include all types for LMUL2
 325    which will be iterated and registered as intrinsic functions.  */
 326 #ifndef DEF_RVV_LMUL2_OPS
 327 #define DEF_RVV_LMUL2_OPS(TYPE, REQUIRE)
 328 #endif
 329
 330 /* Use "DEF_RVV_LMUL4_OPS" macro include all types for LMUL4
 331    which will be iterated and registered as intrinsic functions.  */
 332 #ifndef DEF_RVV_LMUL4_OPS
 333 #define DEF_RVV_LMUL4_OPS(TYPE, REQUIRE)
 334 #endif
 335
 336 /* Use "DEF_RVV_TUPLE_OPS" macro include all tuple types
 337    which will be iterated and registered as intrinsic functions.  */
 338 #ifndef DEF_RVV_TUPLE_OPS
 339 #define DEF_RVV_TUPLE_OPS(TYPE, REQUIRE)
 340 #endif
 341
 342 /* Use "DEF_RVV_CRYPTO_SEW32_OPS" macro include all SEW=32 types
 343    which will be iterated and registered as intrinsic functions.  */
 344 #ifndef DEF_RVV_CRYPTO_SEW32_OPS
 345 #define DEF_RVV_CRYPTO_SEW32_OPS(TYPE, REQUIRE)
 346 #endif
 347
 348 /* Use "DEF_RVV_CRYPTO_SEW64_OPS" macro include all SEW=64 types
 349    which will be iterated and registered as intrinsic functions.  */
 350 #ifndef DEF_RVV_CRYPTO_SEW64_OPS
 351 #define DEF_RVV_CRYPTO_SEW64_OPS(TYPE, REQUIRE)
 352 #endif
 353
 354 DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 355 DEF_RVV_I_OPS (vint8mf4_t, 0)
 356 DEF_RVV_I_OPS (vint8mf2_t, 0)
 357 DEF_RVV_I_OPS (vint8m1_t, 0)
 358 DEF_RVV_I_OPS (vint8m2_t, 0)
 359 DEF_RVV_I_OPS (vint8m4_t, 0)
 360 DEF_RVV_I_OPS (vint8m8_t, 0)
 361 DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 362 DEF_RVV_I_OPS (vint16mf2_t, 0)
 363 DEF_RVV_I_OPS (vint16m1_t, 0)
 364 DEF_RVV_I_OPS (vint16m2_t, 0)
 365 DEF_RVV_I_OPS (vint16m4_t, 0)
 366 DEF_RVV_I_OPS (vint16m8_t, 0)
 367 DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 368 DEF_RVV_I_OPS (vint32m1_t, 0)
 369 DEF_RVV_I_OPS (vint32m2_t, 0)
 370 DEF_RVV_I_OPS (vint32m4_t, 0)
 371 DEF_RVV_I_OPS (vint32m8_t, 0)
 372 DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 373 DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 374 DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 375 DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 376
 377 DEF_RVV_U_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 378 DEF_RVV_U_OPS (vuint8mf4_t, 0)
 379 DEF_RVV_U_OPS (vuint8mf2_t, 0)
 380 DEF_RVV_U_OPS (vuint8m1_t, 0)
 381 DEF_RVV_U_OPS (vuint8m2_t, 0)
 382 DEF_RVV_U_OPS (vuint8m4_t, 0)
 383 DEF_RVV_U_OPS (vuint8m8_t, 0)
 384 DEF_RVV_U_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 385 DEF_RVV_U_OPS (vuint16mf2_t, 0)
 386 DEF_RVV_U_OPS (vuint16m1_t, 0)
 387 DEF_RVV_U_OPS (vuint16m2_t, 0)
 388 DEF_RVV_U_OPS (vuint16m4_t, 0)
 389 DEF_RVV_U_OPS (vuint16m8_t, 0)
 390 DEF_RVV_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 391 DEF_RVV_U_OPS (vuint32m1_t, 0)
 392 DEF_RVV_U_OPS (vuint32m2_t, 0)
 393 DEF_RVV_U_OPS (vuint32m4_t, 0)
 394 DEF_RVV_U_OPS (vuint32m8_t, 0)
 395 DEF_RVV_U_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 396 DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 397 DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 398 DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 399
 400 DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
 401 DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
 402 DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
 403 DEF_RVV_F_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
 404 DEF_RVV_F_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
 405 DEF_RVV_F_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
 406
 407 DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
 408 DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
 409 DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
 410 DEF_RVV_F_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
 411 DEF_RVV_F_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
 412 DEF_RVV_F_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
 413 DEF_RVV_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
 414 DEF_RVV_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
 415 DEF_RVV_F_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
 416
 417 DEF_RVV_B_OPS (vbool64_t, RVV_REQUIRE_MIN_VLEN_64)
 418 DEF_RVV_B_OPS (vbool32_t, 0)
 419 DEF_RVV_B_OPS (vbool16_t, 0)
 420 DEF_RVV_B_OPS (vbool8_t, 0)
 421 DEF_RVV_B_OPS (vbool4_t, 0)
 422 DEF_RVV_B_OPS (vbool2_t, 0)
 423 DEF_RVV_B_OPS (vbool1_t, 0)
 424
 425 DEF_RVV_WEXTI_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 426 DEF_RVV_WEXTI_OPS (vint16mf2_t, 0)
 427 DEF_RVV_WEXTI_OPS (vint16m1_t, 0)
 428 DEF_RVV_WEXTI_OPS (vint16m2_t, 0)
 429 DEF_RVV_WEXTI_OPS (vint16m4_t, 0)
 430 DEF_RVV_WEXTI_OPS (vint16m8_t, 0)
 431 DEF_RVV_WEXTI_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 432 DEF_RVV_WEXTI_OPS (vint32m1_t, 0)
 433 DEF_RVV_WEXTI_OPS (vint32m2_t, 0)
 434 DEF_RVV_WEXTI_OPS (vint32m4_t, 0)
 435 DEF_RVV_WEXTI_OPS (vint32m8_t, 0)
 436 DEF_RVV_WEXTI_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 437 DEF_RVV_WEXTI_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 438 DEF_RVV_WEXTI_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 439 DEF_RVV_WEXTI_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 440
 441 DEF_RVV_QEXTI_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 442 DEF_RVV_QEXTI_OPS (vint32m1_t, 0)
 443 DEF_RVV_QEXTI_OPS (vint32m2_t, 0)
 444 DEF_RVV_QEXTI_OPS (vint32m4_t, 0)
 445 DEF_RVV_QEXTI_OPS (vint32m8_t, 0)
 446 DEF_RVV_QEXTI_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 447 DEF_RVV_QEXTI_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 448 DEF_RVV_QEXTI_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 449 DEF_RVV_QEXTI_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 450
 451 DEF_RVV_OEXTI_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 452 DEF_RVV_OEXTI_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 453 DEF_RVV_OEXTI_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 454 DEF_RVV_OEXTI_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 455
 456 DEF_RVV_WEXTU_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 457 DEF_RVV_WEXTU_OPS (vuint16mf2_t, 0)
 458 DEF_RVV_WEXTU_OPS (vuint16m1_t, 0)
 459 DEF_RVV_WEXTU_OPS (vuint16m2_t, 0)
 460 DEF_RVV_WEXTU_OPS (vuint16m4_t, 0)
 461 DEF_RVV_WEXTU_OPS (vuint16m8_t, 0)
 462 DEF_RVV_WEXTU_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 463 DEF_RVV_WEXTU_OPS (vuint32m1_t, 0)
 464 DEF_RVV_WEXTU_OPS (vuint32m2_t, 0)
 465 DEF_RVV_WEXTU_OPS (vuint32m4_t, 0)
 466 DEF_RVV_WEXTU_OPS (vuint32m8_t, 0)
 467 DEF_RVV_WEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 468 DEF_RVV_WEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 469 DEF_RVV_WEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 470 DEF_RVV_WEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 471
 472 DEF_RVV_QEXTU_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 473 DEF_RVV_QEXTU_OPS (vuint32m1_t, 0)
 474 DEF_RVV_QEXTU_OPS (vuint32m2_t, 0)
 475 DEF_RVV_QEXTU_OPS (vuint32m4_t, 0)
 476 DEF_RVV_QEXTU_OPS (vuint32m8_t, 0)
 477 DEF_RVV_QEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 478 DEF_RVV_QEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 479 DEF_RVV_QEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 480 DEF_RVV_QEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 481
 482 DEF_RVV_OEXTU_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 483 DEF_RVV_OEXTU_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 484 DEF_RVV_OEXTU_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 485 DEF_RVV_OEXTU_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 486
 487 DEF_RVV_FULL_V_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 488 DEF_RVV_FULL_V_I_OPS (vint8mf4_t, 0)
 489 DEF_RVV_FULL_V_I_OPS (vint8mf2_t, 0)
 490 DEF_RVV_FULL_V_I_OPS (vint8m1_t, 0)
 491 DEF_RVV_FULL_V_I_OPS (vint8m2_t, 0)
 492 DEF_RVV_FULL_V_I_OPS (vint8m4_t, 0)
 493 DEF_RVV_FULL_V_I_OPS (vint8m8_t, 0)
 494 DEF_RVV_FULL_V_I_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 495 DEF_RVV_FULL_V_I_OPS (vint16mf2_t, 0)
 496 DEF_RVV_FULL_V_I_OPS (vint16m1_t, 0)
 497 DEF_RVV_FULL_V_I_OPS (vint16m2_t, 0)
 498 DEF_RVV_FULL_V_I_OPS (vint16m4_t, 0)
 499 DEF_RVV_FULL_V_I_OPS (vint16m8_t, 0)
 500 DEF_RVV_FULL_V_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 501 DEF_RVV_FULL_V_I_OPS (vint32m1_t, 0)
 502 DEF_RVV_FULL_V_I_OPS (vint32m2_t, 0)
 503 DEF_RVV_FULL_V_I_OPS (vint32m4_t, 0)
 504 DEF_RVV_FULL_V_I_OPS (vint32m8_t, 0)
 505 DEF_RVV_FULL_V_I_OPS (vint64m1_t, RVV_REQUIRE_FULL_V)
 506 DEF_RVV_FULL_V_I_OPS (vint64m2_t, RVV_REQUIRE_FULL_V)
 507 DEF_RVV_FULL_V_I_OPS (vint64m4_t, RVV_REQUIRE_FULL_V)
 508 DEF_RVV_FULL_V_I_OPS (vint64m8_t, RVV_REQUIRE_FULL_V)
 509
 510 DEF_RVV_FULL_V_U_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 511 DEF_RVV_FULL_V_U_OPS (vuint8mf4_t, 0)
 512 DEF_RVV_FULL_V_U_OPS (vuint8mf2_t, 0)
 513 DEF_RVV_FULL_V_U_OPS (vuint8m1_t, 0)
 514 DEF_RVV_FULL_V_U_OPS (vuint8m2_t, 0)
 515 DEF_RVV_FULL_V_U_OPS (vuint8m4_t, 0)
 516 DEF_RVV_FULL_V_U_OPS (vuint8m8_t, 0)
 517 DEF_RVV_FULL_V_U_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 518 DEF_RVV_FULL_V_U_OPS (vuint16mf2_t, 0)
 519 DEF_RVV_FULL_V_U_OPS (vuint16m1_t, 0)
 520 DEF_RVV_FULL_V_U_OPS (vuint16m2_t, 0)
 521 DEF_RVV_FULL_V_U_OPS (vuint16m4_t, 0)
 522 DEF_RVV_FULL_V_U_OPS (vuint16m8_t, 0)
 523 DEF_RVV_FULL_V_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 524 DEF_RVV_FULL_V_U_OPS (vuint32m1_t, 0)
 525 DEF_RVV_FULL_V_U_OPS (vuint32m2_t, 0)
 526 DEF_RVV_FULL_V_U_OPS (vuint32m4_t, 0)
 527 DEF_RVV_FULL_V_U_OPS (vuint32m8_t, 0)
 528 DEF_RVV_FULL_V_U_OPS (vuint64m1_t, RVV_REQUIRE_FULL_V)
 529 DEF_RVV_FULL_V_U_OPS (vuint64m2_t, RVV_REQUIRE_FULL_V)
 530 DEF_RVV_FULL_V_U_OPS (vuint64m4_t, RVV_REQUIRE_FULL_V)
 531 DEF_RVV_FULL_V_U_OPS (vuint64m8_t, RVV_REQUIRE_FULL_V)
 532
 533 DEF_RVV_WEXTF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
 534 DEF_RVV_WEXTF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_16)
 535 DEF_RVV_WEXTF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_16)
 536 DEF_RVV_WEXTF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_16)
 537 DEF_RVV_WEXTF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_16)
 538
 539 DEF_RVV_WEXTF_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
 540 DEF_RVV_WEXTF_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
 541 DEF_RVV_WEXTF_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
 542 DEF_RVV_WEXTF_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
 543
 544 DEF_RVV_CONVERT_I_OPS (vint16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
 545 DEF_RVV_CONVERT_I_OPS (vint16mf2_t, RVV_REQUIRE_ELEN_FP_16)
 546 DEF_RVV_CONVERT_I_OPS (vint16m1_t, RVV_REQUIRE_ELEN_FP_16)
 547 DEF_RVV_CONVERT_I_OPS (vint16m2_t, RVV_REQUIRE_ELEN_FP_16)
 548 DEF_RVV_CONVERT_I_OPS (vint16m4_t, RVV_REQUIRE_ELEN_FP_16)
 549 DEF_RVV_CONVERT_I_OPS (vint16m8_t, RVV_REQUIRE_ELEN_FP_16)
 550
 551 DEF_RVV_CONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 552 DEF_RVV_CONVERT_I_OPS (vint32m1_t, 0)
 553 DEF_RVV_CONVERT_I_OPS (vint32m2_t, 0)
 554 DEF_RVV_CONVERT_I_OPS (vint32m4_t, 0)
 555 DEF_RVV_CONVERT_I_OPS (vint32m8_t, 0)
 556 DEF_RVV_CONVERT_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 557 DEF_RVV_CONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 558 DEF_RVV_CONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 559 DEF_RVV_CONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 560
 561 DEF_RVV_CONVERT_U_OPS (vuint16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
 562 DEF_RVV_CONVERT_U_OPS (vuint16mf2_t, RVV_REQUIRE_ELEN_FP_16)
 563 DEF_RVV_CONVERT_U_OPS (vuint16m1_t, RVV_REQUIRE_ELEN_FP_16)
 564 DEF_RVV_CONVERT_U_OPS (vuint16m2_t, RVV_REQUIRE_ELEN_FP_16)
 565 DEF_RVV_CONVERT_U_OPS (vuint16m4_t, RVV_REQUIRE_ELEN_FP_16)
 566 DEF_RVV_CONVERT_U_OPS (vuint16m8_t, RVV_REQUIRE_ELEN_FP_16)
 567
 568 DEF_RVV_CONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 569 DEF_RVV_CONVERT_U_OPS (vuint32m1_t, 0)
 570 DEF_RVV_CONVERT_U_OPS (vuint32m2_t, 0)
 571 DEF_RVV_CONVERT_U_OPS (vuint32m4_t, 0)
 572 DEF_RVV_CONVERT_U_OPS (vuint32m8_t, 0)
 573 DEF_RVV_CONVERT_U_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 574 DEF_RVV_CONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 575 DEF_RVV_CONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 576 DEF_RVV_CONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 577
 578 DEF_RVV_WCONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
 579 DEF_RVV_WCONVERT_I_OPS (vint32m1_t, RVV_REQUIRE_ELEN_FP_16)
 580 DEF_RVV_WCONVERT_I_OPS (vint32m2_t, RVV_REQUIRE_ELEN_FP_16)
 581 DEF_RVV_WCONVERT_I_OPS (vint32m4_t, RVV_REQUIRE_ELEN_FP_16)
 582 DEF_RVV_WCONVERT_I_OPS (vint32m8_t, RVV_REQUIRE_ELEN_FP_16)
 583
 584 DEF_RVV_WCONVERT_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
 585 DEF_RVV_WCONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
 586 DEF_RVV_WCONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
 587 DEF_RVV_WCONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
 588
 589 DEF_RVV_WCONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
 590 DEF_RVV_WCONVERT_U_OPS (vuint32m1_t, RVV_REQUIRE_ELEN_FP_16)
 591 DEF_RVV_WCONVERT_U_OPS (vuint32m2_t, RVV_REQUIRE_ELEN_FP_16)
 592 DEF_RVV_WCONVERT_U_OPS (vuint32m4_t, RVV_REQUIRE_ELEN_FP_16)
 593 DEF_RVV_WCONVERT_U_OPS (vuint32m8_t, RVV_REQUIRE_ELEN_FP_16)
 594
 595 DEF_RVV_WCONVERT_U_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
 596 DEF_RVV_WCONVERT_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
 597 DEF_RVV_WCONVERT_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
 598 DEF_RVV_WCONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64)
 599
 600 DEF_RVV_WCONVERT_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
 601 DEF_RVV_WCONVERT_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
 602 DEF_RVV_WCONVERT_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
 603 DEF_RVV_WCONVERT_F_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
 604 DEF_RVV_WCONVERT_F_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
 605
 606 DEF_RVV_WCONVERT_F_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
 607 DEF_RVV_WCONVERT_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
 608 DEF_RVV_WCONVERT_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
 609 DEF_RVV_WCONVERT_F_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
 610
 611 DEF_RVV_WI_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 612 DEF_RVV_WI_OPS (vint8mf4_t, 0)
 613 DEF_RVV_WI_OPS (vint8mf2_t, 0)
 614 DEF_RVV_WI_OPS (vint8m1_t, 0)
 615 DEF_RVV_WI_OPS (vint8m2_t, 0)
 616 DEF_RVV_WI_OPS (vint8m4_t, 0)
 617 DEF_RVV_WI_OPS (vint8m8_t, 0)
 618 DEF_RVV_WI_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 619 DEF_RVV_WI_OPS (vint16mf2_t, 0)
 620 DEF_RVV_WI_OPS (vint16m1_t, 0)
 621 DEF_RVV_WI_OPS (vint16m2_t, 0)
 622 DEF_RVV_WI_OPS (vint16m4_t, 0)
 623 DEF_RVV_WI_OPS (vint16m8_t, 0)
 624 DEF_RVV_WI_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 625 DEF_RVV_WI_OPS (vint32m1_t, 0)
 626 DEF_RVV_WI_OPS (vint32m2_t, 0)
 627 DEF_RVV_WI_OPS (vint32m4_t, 0)
 628 DEF_RVV_WI_OPS (vint32m8_t, 0)
 629
 630 DEF_RVV_WU_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 631 DEF_RVV_WU_OPS (vuint8mf4_t, 0)
 632 DEF_RVV_WU_OPS (vuint8mf2_t, 0)
 633 DEF_RVV_WU_OPS (vuint8m1_t, 0)
 634 DEF_RVV_WU_OPS (vuint8m2_t, 0)
 635 DEF_RVV_WU_OPS (vuint8m4_t, 0)
 636 DEF_RVV_WU_OPS (vuint8m8_t, 0)
 637 DEF_RVV_WU_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 638 DEF_RVV_WU_OPS (vuint16mf2_t, 0)
 639 DEF_RVV_WU_OPS (vuint16m1_t, 0)
 640 DEF_RVV_WU_OPS (vuint16m2_t, 0)
 641 DEF_RVV_WU_OPS (vuint16m4_t, 0)
 642 DEF_RVV_WU_OPS (vuint16m8_t, 0)
 643 DEF_RVV_WU_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 644 DEF_RVV_WU_OPS (vuint32m1_t, 0)
 645 DEF_RVV_WU_OPS (vuint32m2_t, 0)
 646 DEF_RVV_WU_OPS (vuint32m4_t, 0)
 647 DEF_RVV_WU_OPS (vuint32m8_t, 0)
 648
 649 DEF_RVV_WF_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
 650 DEF_RVV_WF_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
 651 DEF_RVV_WF_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
 652 DEF_RVV_WF_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
 653 DEF_RVV_WF_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
 654 DEF_RVV_WF_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
 655
 656 DEF_RVV_WF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
 657 DEF_RVV_WF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
 658 DEF_RVV_WF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
 659 DEF_RVV_WF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
 660 DEF_RVV_WF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
 661
 662 DEF_RVV_EI16_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 663 DEF_RVV_EI16_OPS (vint8mf4_t, 0)
 664 DEF_RVV_EI16_OPS (vint8mf2_t, 0)
 665 DEF_RVV_EI16_OPS (vint8m1_t, 0)
 666 DEF_RVV_EI16_OPS (vint8m2_t, 0)
 667 DEF_RVV_EI16_OPS (vint8m4_t, 0)
 668 DEF_RVV_EI16_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 669 DEF_RVV_EI16_OPS (vint16mf2_t, 0)
 670 DEF_RVV_EI16_OPS (vint16m1_t, 0)
 671 DEF_RVV_EI16_OPS (vint16m2_t, 0)
 672 DEF_RVV_EI16_OPS (vint16m4_t, 0)
 673 DEF_RVV_EI16_OPS (vint16m8_t, 0)
 674 DEF_RVV_EI16_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 675 DEF_RVV_EI16_OPS (vint32m1_t, 0)
 676 DEF_RVV_EI16_OPS (vint32m2_t, 0)
 677 DEF_RVV_EI16_OPS (vint32m4_t, 0)
 678 DEF_RVV_EI16_OPS (vint32m8_t, 0)
 679 DEF_RVV_EI16_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 680 DEF_RVV_EI16_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 681 DEF_RVV_EI16_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 682 DEF_RVV_EI16_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 683 DEF_RVV_EI16_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 684 DEF_RVV_EI16_OPS (vuint8mf4_t, 0)
 685 DEF_RVV_EI16_OPS (vuint8mf2_t, 0)
 686 DEF_RVV_EI16_OPS (vuint8m1_t, 0)
 687 DEF_RVV_EI16_OPS (vuint8m2_t, 0)
 688 DEF_RVV_EI16_OPS (vuint8m4_t, 0)
 689 DEF_RVV_EI16_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 690 DEF_RVV_EI16_OPS (vuint16mf2_t, 0)
 691 DEF_RVV_EI16_OPS (vuint16m1_t, 0)
 692 DEF_RVV_EI16_OPS (vuint16m2_t, 0)
 693 DEF_RVV_EI16_OPS (vuint16m4_t, 0)
 694 DEF_RVV_EI16_OPS (vuint16m8_t, 0)
 695 DEF_RVV_EI16_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 696 DEF_RVV_EI16_OPS (vuint32m1_t, 0)
 697 DEF_RVV_EI16_OPS (vuint32m2_t, 0)
 698 DEF_RVV_EI16_OPS (vuint32m4_t, 0)
 699 DEF_RVV_EI16_OPS (vuint32m8_t, 0)
 700 DEF_RVV_EI16_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 701 DEF_RVV_EI16_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 702 DEF_RVV_EI16_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 703 DEF_RVV_EI16_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 704
 705 DEF_RVV_EI16_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
 706 DEF_RVV_EI16_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
 707 DEF_RVV_EI16_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
 708 DEF_RVV_EI16_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
 709 DEF_RVV_EI16_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
 710 DEF_RVV_EI16_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
 711
 712 DEF_RVV_EI16_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
 713 DEF_RVV_EI16_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
 714 DEF_RVV_EI16_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
 715 DEF_RVV_EI16_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
 716 DEF_RVV_EI16_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
 717
 718 DEF_RVV_EI16_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
 719 DEF_RVV_EI16_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
 720 DEF_RVV_EI16_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
 721 DEF_RVV_EI16_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
 722
 723 DEF_RVV_EEW8_INTERPRET_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 724 DEF_RVV_EEW8_INTERPRET_OPS (vint16mf2_t, 0)
 725 DEF_RVV_EEW8_INTERPRET_OPS (vint16m1_t, 0)
 726 DEF_RVV_EEW8_INTERPRET_OPS (vint16m2_t, 0)
 727 DEF_RVV_EEW8_INTERPRET_OPS (vint16m4_t, 0)
 728 DEF_RVV_EEW8_INTERPRET_OPS (vint16m8_t, 0)
 729 DEF_RVV_EEW8_INTERPRET_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 730 DEF_RVV_EEW8_INTERPRET_OPS (vint32m1_t, 0)
 731 DEF_RVV_EEW8_INTERPRET_OPS (vint32m2_t, 0)
 732 DEF_RVV_EEW8_INTERPRET_OPS (vint32m4_t, 0)
 733 DEF_RVV_EEW8_INTERPRET_OPS (vint32m8_t, 0)
 734 DEF_RVV_EEW8_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 735 DEF_RVV_EEW8_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 736 DEF_RVV_EEW8_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 737 DEF_RVV_EEW8_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 738 DEF_RVV_EEW8_INTERPRET_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 739 DEF_RVV_EEW8_INTERPRET_OPS (vuint16mf2_t, 0)
 740 DEF_RVV_EEW8_INTERPRET_OPS (vuint16m1_t, 0)
 741 DEF_RVV_EEW8_INTERPRET_OPS (vuint16m2_t, 0)
 742 DEF_RVV_EEW8_INTERPRET_OPS (vuint16m4_t, 0)
 743 DEF_RVV_EEW8_INTERPRET_OPS (vuint16m8_t, 0)
 744 DEF_RVV_EEW8_INTERPRET_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 745 DEF_RVV_EEW8_INTERPRET_OPS (vuint32m1_t, 0)
 746 DEF_RVV_EEW8_INTERPRET_OPS (vuint32m2_t, 0)
 747 DEF_RVV_EEW8_INTERPRET_OPS (vuint32m4_t, 0)
 748 DEF_RVV_EEW8_INTERPRET_OPS (vuint32m8_t, 0)
 749 DEF_RVV_EEW8_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 750 DEF_RVV_EEW8_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 751 DEF_RVV_EEW8_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 752 DEF_RVV_EEW8_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 753
 754 DEF_RVV_EEW16_INTERPRET_OPS (vint8mf4_t, 0)
 755 DEF_RVV_EEW16_INTERPRET_OPS (vint8mf2_t, 0)
 756 DEF_RVV_EEW16_INTERPRET_OPS (vint8m1_t, 0)
 757 DEF_RVV_EEW16_INTERPRET_OPS (vint8m2_t, 0)
 758 DEF_RVV_EEW16_INTERPRET_OPS (vint8m4_t, 0)
 759 DEF_RVV_EEW16_INTERPRET_OPS (vint8m8_t, 0)
 760 DEF_RVV_EEW16_INTERPRET_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 761 DEF_RVV_EEW16_INTERPRET_OPS (vint32m1_t, 0)
 762 DEF_RVV_EEW16_INTERPRET_OPS (vint32m2_t, 0)
 763 DEF_RVV_EEW16_INTERPRET_OPS (vint32m4_t, 0)
 764 DEF_RVV_EEW16_INTERPRET_OPS (vint32m8_t, 0)
 765 DEF_RVV_EEW16_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 766 DEF_RVV_EEW16_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 767 DEF_RVV_EEW16_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 768 DEF_RVV_EEW16_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 769 DEF_RVV_EEW16_INTERPRET_OPS (vuint8mf4_t, 0)
 770 DEF_RVV_EEW16_INTERPRET_OPS (vuint8mf2_t, 0)
 771 DEF_RVV_EEW16_INTERPRET_OPS (vuint8m1_t, 0)
 772 DEF_RVV_EEW16_INTERPRET_OPS (vuint8m2_t, 0)
 773 DEF_RVV_EEW16_INTERPRET_OPS (vuint8m4_t, 0)
 774 DEF_RVV_EEW16_INTERPRET_OPS (vuint8m8_t, 0)
 775 DEF_RVV_EEW16_INTERPRET_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 776 DEF_RVV_EEW16_INTERPRET_OPS (vuint32m1_t, 0)
 777 DEF_RVV_EEW16_INTERPRET_OPS (vuint32m2_t, 0)
 778 DEF_RVV_EEW16_INTERPRET_OPS (vuint32m4_t, 0)
 779 DEF_RVV_EEW16_INTERPRET_OPS (vuint32m8_t, 0)
 780 DEF_RVV_EEW16_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 781 DEF_RVV_EEW16_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 782 DEF_RVV_EEW16_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 783 DEF_RVV_EEW16_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 784
 785 DEF_RVV_EEW32_INTERPRET_OPS (vint8mf2_t, 0)
 786 DEF_RVV_EEW32_INTERPRET_OPS (vint8m1_t, 0)
 787 DEF_RVV_EEW32_INTERPRET_OPS (vint8m2_t, 0)
 788 DEF_RVV_EEW32_INTERPRET_OPS (vint8m4_t, 0)
 789 DEF_RVV_EEW32_INTERPRET_OPS (vint8m8_t, 0)
 790 DEF_RVV_EEW32_INTERPRET_OPS (vint16mf2_t, 0)
 791 DEF_RVV_EEW32_INTERPRET_OPS (vint16m1_t, 0)
 792 DEF_RVV_EEW32_INTERPRET_OPS (vint16m2_t, 0)
 793 DEF_RVV_EEW32_INTERPRET_OPS (vint16m4_t, 0)
 794 DEF_RVV_EEW32_INTERPRET_OPS (vint16m8_t, 0)
 795 DEF_RVV_EEW32_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 796 DEF_RVV_EEW32_INTERPRET_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 797 DEF_RVV_EEW32_INTERPRET_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 798 DEF_RVV_EEW32_INTERPRET_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
 799 DEF_RVV_EEW32_INTERPRET_OPS (vuint8mf2_t, 0)
 800 DEF_RVV_EEW32_INTERPRET_OPS (vuint8m1_t, 0)
 801 DEF_RVV_EEW32_INTERPRET_OPS (vuint8m2_t, 0)
 802 DEF_RVV_EEW32_INTERPRET_OPS (vuint8m4_t, 0)
 803 DEF_RVV_EEW32_INTERPRET_OPS (vuint8m8_t, 0)
 804 DEF_RVV_EEW32_INTERPRET_OPS (vuint16mf2_t, 0)
 805 DEF_RVV_EEW32_INTERPRET_OPS (vuint16m1_t, 0)
 806 DEF_RVV_EEW32_INTERPRET_OPS (vuint16m2_t, 0)
 807 DEF_RVV_EEW32_INTERPRET_OPS (vuint16m4_t, 0)
 808 DEF_RVV_EEW32_INTERPRET_OPS (vuint16m8_t, 0)
 809 DEF_RVV_EEW32_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 810 DEF_RVV_EEW32_INTERPRET_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 811 DEF_RVV_EEW32_INTERPRET_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 812 DEF_RVV_EEW32_INTERPRET_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 813
 814 DEF_RVV_EEW64_INTERPRET_OPS (vint8m1_t, 0)
 815 DEF_RVV_EEW64_INTERPRET_OPS (vint8m2_t, 0)
 816 DEF_RVV_EEW64_INTERPRET_OPS (vint8m4_t, 0)
 817 DEF_RVV_EEW64_INTERPRET_OPS (vint8m8_t, 0)
 818 DEF_RVV_EEW64_INTERPRET_OPS (vint16m1_t, 0)
 819 DEF_RVV_EEW64_INTERPRET_OPS (vint16m2_t, 0)
 820 DEF_RVV_EEW64_INTERPRET_OPS (vint16m4_t, 0)
 821 DEF_RVV_EEW64_INTERPRET_OPS (vint16m8_t, 0)
 822 DEF_RVV_EEW64_INTERPRET_OPS (vint32m1_t, 0)
 823 DEF_RVV_EEW64_INTERPRET_OPS (vint32m2_t, 0)
 824 DEF_RVV_EEW64_INTERPRET_OPS (vint32m4_t, 0)
 825 DEF_RVV_EEW64_INTERPRET_OPS (vint32m8_t, 0)
 826 DEF_RVV_EEW64_INTERPRET_OPS (vuint8m1_t, 0)
 827 DEF_RVV_EEW64_INTERPRET_OPS (vuint8m2_t, 0)
 828 DEF_RVV_EEW64_INTERPRET_OPS (vuint8m4_t, 0)
 829 DEF_RVV_EEW64_INTERPRET_OPS (vuint8m8_t, 0)
 830 DEF_RVV_EEW64_INTERPRET_OPS (vuint16m1_t, 0)
 831 DEF_RVV_EEW64_INTERPRET_OPS (vuint16m2_t, 0)
 832 DEF_RVV_EEW64_INTERPRET_OPS (vuint16m4_t, 0)
 833 DEF_RVV_EEW64_INTERPRET_OPS (vuint16m8_t, 0)
 834 DEF_RVV_EEW64_INTERPRET_OPS (vuint32m1_t, 0)
 835 DEF_RVV_EEW64_INTERPRET_OPS (vuint32m2_t, 0)
 836 DEF_RVV_EEW64_INTERPRET_OPS (vuint32m4_t, 0)
 837 DEF_RVV_EEW64_INTERPRET_OPS (vuint32m8_t, 0)
 838
 839 DEF_RVV_BOOL1_INTERPRET_OPS (vint8m1_t, 0)
 840 DEF_RVV_BOOL1_INTERPRET_OPS (vint16m1_t, 0)
 841 DEF_RVV_BOOL1_INTERPRET_OPS (vint32m1_t, 0)
 842 DEF_RVV_BOOL1_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 843 DEF_RVV_BOOL1_INTERPRET_OPS (vuint8m1_t, 0)
 844 DEF_RVV_BOOL1_INTERPRET_OPS (vuint16m1_t, 0)
 845 DEF_RVV_BOOL1_INTERPRET_OPS (vuint32m1_t, 0)
 846 DEF_RVV_BOOL1_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 847
 848 DEF_RVV_BOOL2_INTERPRET_OPS (vint8m1_t, 0)
 849 DEF_RVV_BOOL2_INTERPRET_OPS (vint16m1_t, 0)
 850 DEF_RVV_BOOL2_INTERPRET_OPS (vint32m1_t, 0)
 851 DEF_RVV_BOOL2_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 852 DEF_RVV_BOOL2_INTERPRET_OPS (vuint8m1_t, 0)
 853 DEF_RVV_BOOL2_INTERPRET_OPS (vuint16m1_t, 0)
 854 DEF_RVV_BOOL2_INTERPRET_OPS (vuint32m1_t, 0)
 855 DEF_RVV_BOOL2_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 856
 857 DEF_RVV_BOOL4_INTERPRET_OPS (vint8m1_t, 0)
 858 DEF_RVV_BOOL4_INTERPRET_OPS (vint16m1_t, 0)
 859 DEF_RVV_BOOL4_INTERPRET_OPS (vint32m1_t, 0)
 860 DEF_RVV_BOOL4_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 861 DEF_RVV_BOOL4_INTERPRET_OPS (vuint8m1_t, 0)
 862 DEF_RVV_BOOL4_INTERPRET_OPS (vuint16m1_t, 0)
 863 DEF_RVV_BOOL4_INTERPRET_OPS (vuint32m1_t, 0)
 864 DEF_RVV_BOOL4_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 865
 866 DEF_RVV_BOOL8_INTERPRET_OPS (vint8m1_t, 0)
 867 DEF_RVV_BOOL8_INTERPRET_OPS (vint16m1_t, 0)
 868 DEF_RVV_BOOL8_INTERPRET_OPS (vint32m1_t, 0)
 869 DEF_RVV_BOOL8_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 870 DEF_RVV_BOOL8_INTERPRET_OPS (vuint8m1_t, 0)
 871 DEF_RVV_BOOL8_INTERPRET_OPS (vuint16m1_t, 0)
 872 DEF_RVV_BOOL8_INTERPRET_OPS (vuint32m1_t, 0)
 873 DEF_RVV_BOOL8_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 874
 875 DEF_RVV_BOOL16_INTERPRET_OPS (vint8m1_t, 0)
 876 DEF_RVV_BOOL16_INTERPRET_OPS (vint16m1_t, 0)
 877 DEF_RVV_BOOL16_INTERPRET_OPS (vint32m1_t, 0)
 878 DEF_RVV_BOOL16_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 879 DEF_RVV_BOOL16_INTERPRET_OPS (vuint8m1_t, 0)
 880 DEF_RVV_BOOL16_INTERPRET_OPS (vuint16m1_t, 0)
 881 DEF_RVV_BOOL16_INTERPRET_OPS (vuint32m1_t, 0)
 882 DEF_RVV_BOOL16_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 883
 884 DEF_RVV_BOOL32_INTERPRET_OPS (vint8m1_t, 0)
 885 DEF_RVV_BOOL32_INTERPRET_OPS (vint16m1_t, 0)
 886 DEF_RVV_BOOL32_INTERPRET_OPS (vint32m1_t, 0)
 887 DEF_RVV_BOOL32_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 888 DEF_RVV_BOOL32_INTERPRET_OPS (vuint8m1_t, 0)
 889 DEF_RVV_BOOL32_INTERPRET_OPS (vuint16m1_t, 0)
 890 DEF_RVV_BOOL32_INTERPRET_OPS (vuint32m1_t, 0)
 891 DEF_RVV_BOOL32_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 892
 893 DEF_RVV_BOOL64_INTERPRET_OPS (vint8m1_t, 0)
 894 DEF_RVV_BOOL64_INTERPRET_OPS (vint16m1_t, 0)
 895 DEF_RVV_BOOL64_INTERPRET_OPS (vint32m1_t, 0)
 896 DEF_RVV_BOOL64_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 897 DEF_RVV_BOOL64_INTERPRET_OPS (vuint8m1_t, 0)
 898 DEF_RVV_BOOL64_INTERPRET_OPS (vuint16m1_t, 0)
 899 DEF_RVV_BOOL64_INTERPRET_OPS (vuint32m1_t, 0)
 900 DEF_RVV_BOOL64_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 901
 902 DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool1_t, 0)
 903 DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool2_t, 0)
 904 DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool4_t, 0)
 905 DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool8_t, 0)
 906 DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool16_t, 0)
 907 DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool32_t, 0)
 908 DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
 909
 910 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool1_t, 0)
 911 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool2_t, 0)
 912 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool4_t, 0)
 913 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool8_t, 0)
 914 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool16_t, 0)
 915 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool32_t, 0)
 916 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
 917
 918 DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool1_t, 0)
 919 DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool2_t, 0)
 920 DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool4_t, 0)
 921 DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool8_t, 0)
 922 DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool16_t, 0)
 923 DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool32_t, 0)
 924 DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
 925
 926 DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool1_t, 0)
 927 DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool2_t, 0)
 928 DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool4_t, 0)
 929 DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool8_t, 0)
 930 DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool16_t, 0)
 931 DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool32_t, 0)
 932 DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
 933
 934 DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool1_t, 0)
 935 DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool2_t, 0)
 936 DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool4_t, 0)
 937 DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool8_t, 0)
 938 DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool16_t, 0)
 939 DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool32_t, 0)
 940 DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
 941
 942 DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool1_t, 0)
 943 DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool2_t, 0)
 944 DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool4_t, 0)
 945 DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool8_t, 0)
 946 DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool16_t, 0)
 947 DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool32_t, 0)
 948 DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
 949
 950 DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool1_t, 0)
 951 DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool2_t, 0)
 952 DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool4_t, 0)
 953 DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool8_t, 0)
 954 DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool16_t, 0)
 955 DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool32_t, 0)
 956 DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
 957
 958 DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool1_t, 0)
 959 DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool2_t, 0)
 960 DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool4_t, 0)
 961 DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool8_t, 0)
 962 DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool16_t, 0)
 963 DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool32_t, 0)
 964 DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
 965
 966 DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 967 DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf4_t, 0)
 968 DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf2_t, 0)
 969 DEF_RVV_X2_VLMUL_EXT_OPS (vint8m1_t, 0)
 970 DEF_RVV_X2_VLMUL_EXT_OPS (vint8m2_t, 0)
 971 DEF_RVV_X2_VLMUL_EXT_OPS (vint8m4_t, 0)
 972 DEF_RVV_X2_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 973 DEF_RVV_X2_VLMUL_EXT_OPS (vint16mf2_t, 0)
 974 DEF_RVV_X2_VLMUL_EXT_OPS (vint16m1_t, 0)
 975 DEF_RVV_X2_VLMUL_EXT_OPS (vint16m2_t, 0)
 976 DEF_RVV_X2_VLMUL_EXT_OPS (vint16m4_t, 0)
 977 DEF_RVV_X2_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 978 DEF_RVV_X2_VLMUL_EXT_OPS (vint32m1_t, 0)
 979 DEF_RVV_X2_VLMUL_EXT_OPS (vint32m2_t, 0)
 980 DEF_RVV_X2_VLMUL_EXT_OPS (vint32m4_t, 0)
 981 DEF_RVV_X2_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
 982 DEF_RVV_X2_VLMUL_EXT_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
 983 DEF_RVV_X2_VLMUL_EXT_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
 984 DEF_RVV_X2_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 985 DEF_RVV_X2_VLMUL_EXT_OPS (vuint8mf4_t, 0)
 986 DEF_RVV_X2_VLMUL_EXT_OPS (vuint8mf2_t, 0)
 987 DEF_RVV_X2_VLMUL_EXT_OPS (vuint8m1_t, 0)
 988 DEF_RVV_X2_VLMUL_EXT_OPS (vuint8m2_t, 0)
 989 DEF_RVV_X2_VLMUL_EXT_OPS (vuint8m4_t, 0)
 990 DEF_RVV_X2_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
 991 DEF_RVV_X2_VLMUL_EXT_OPS (vuint16mf2_t, 0)
 992 DEF_RVV_X2_VLMUL_EXT_OPS (vuint16m1_t, 0)
 993 DEF_RVV_X2_VLMUL_EXT_OPS (vuint16m2_t, 0)
 994 DEF_RVV_X2_VLMUL_EXT_OPS (vuint16m4_t, 0)
 995 DEF_RVV_X2_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
 996 DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m1_t, 0)
 997 DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m2_t, 0)
 998 DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m4_t, 0)
 999 DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
1000 DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
1001 DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
1002 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1003 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
1004 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
1005 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
1006 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
1007 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1008 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
1009 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
1010 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
1011 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
1012 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
1013 DEF_RVV_X2_VLMUL_EXT_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
1014
1015 DEF_RVV_X4_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1016 DEF_RVV_X4_VLMUL_EXT_OPS (vint8mf4_t, 0)
1017 DEF_RVV_X4_VLMUL_EXT_OPS (vint8mf2_t, 0)
1018 DEF_RVV_X4_VLMUL_EXT_OPS (vint8m1_t, 0)
1019 DEF_RVV_X4_VLMUL_EXT_OPS (vint8m2_t, 0)
1020 DEF_RVV_X4_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
1021 DEF_RVV_X4_VLMUL_EXT_OPS (vint16mf2_t, 0)
1022 DEF_RVV_X4_VLMUL_EXT_OPS (vint16m1_t, 0)
1023 DEF_RVV_X4_VLMUL_EXT_OPS (vint16m2_t, 0)
1024 DEF_RVV_X4_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
1025 DEF_RVV_X4_VLMUL_EXT_OPS (vint32m1_t, 0)
1026 DEF_RVV_X4_VLMUL_EXT_OPS (vint32m2_t, 0)
1027 DEF_RVV_X4_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
1028 DEF_RVV_X4_VLMUL_EXT_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
1029 DEF_RVV_X4_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1030 DEF_RVV_X4_VLMUL_EXT_OPS (vuint8mf4_t, 0)
1031 DEF_RVV_X4_VLMUL_EXT_OPS (vuint8mf2_t, 0)
1032 DEF_RVV_X4_VLMUL_EXT_OPS (vuint8m1_t, 0)
1033 DEF_RVV_X4_VLMUL_EXT_OPS (vuint8m2_t, 0)
1034 DEF_RVV_X4_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
1035 DEF_RVV_X4_VLMUL_EXT_OPS (vuint16mf2_t, 0)
1036 DEF_RVV_X4_VLMUL_EXT_OPS (vuint16m1_t, 0)
1037 DEF_RVV_X4_VLMUL_EXT_OPS (vuint16m2_t, 0)
1038 DEF_RVV_X4_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
1039 DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m1_t, 0)
1040 DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m2_t, 0)
1041 DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
1042 DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
1043 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1044 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
1045 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
1046 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
1047 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1048 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
1049 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
1050 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
1051 DEF_RVV_X4_VLMUL_EXT_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
1052
1053 DEF_RVV_X8_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1054 DEF_RVV_X8_VLMUL_EXT_OPS (vint8mf4_t, 0)
1055 DEF_RVV_X8_VLMUL_EXT_OPS (vint8mf2_t, 0)
1056 DEF_RVV_X8_VLMUL_EXT_OPS (vint8m1_t, 0)
1057 DEF_RVV_X8_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
1058 DEF_RVV_X8_VLMUL_EXT_OPS (vint16mf2_t, 0)
1059 DEF_RVV_X8_VLMUL_EXT_OPS (vint16m1_t, 0)
1060 DEF_RVV_X8_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
1061 DEF_RVV_X8_VLMUL_EXT_OPS (vint32m1_t, 0)
1062 DEF_RVV_X8_VLMUL_EXT_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
1063 DEF_RVV_X8_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1064 DEF_RVV_X8_VLMUL_EXT_OPS (vuint8mf4_t, 0)
1065 DEF_RVV_X8_VLMUL_EXT_OPS (vuint8mf2_t, 0)
1066 DEF_RVV_X8_VLMUL_EXT_OPS (vuint8m1_t, 0)
1067 DEF_RVV_X8_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
1068 DEF_RVV_X8_VLMUL_EXT_OPS (vuint16mf2_t, 0)
1069 DEF_RVV_X8_VLMUL_EXT_OPS (vuint16m1_t, 0)
1070 DEF_RVV_X8_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
1071 DEF_RVV_X8_VLMUL_EXT_OPS (vuint32m1_t, 0)
1072 DEF_RVV_X8_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
1073 DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1074 DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
1075 DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
1076 DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1077 DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
1078 DEF_RVV_X8_VLMUL_EXT_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
1079
1080 DEF_RVV_X16_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1081 DEF_RVV_X16_VLMUL_EXT_OPS (vint8mf4_t, 0)
1082 DEF_RVV_X16_VLMUL_EXT_OPS (vint8mf2_t, 0)
1083 DEF_RVV_X16_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
1084 DEF_RVV_X16_VLMUL_EXT_OPS (vint16mf2_t, 0)
1085 DEF_RVV_X16_VLMUL_EXT_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
1086 DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1087 DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf4_t, 0)
1088 DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf2_t, 0)
1089 DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
1090 DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf2_t, 0)
1091 DEF_RVV_X16_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
1092 DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1093 DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
1094 DEF_RVV_X16_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1095
1096 DEF_RVV_X32_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1097 DEF_RVV_X32_VLMUL_EXT_OPS (vint8mf4_t, 0)
1098 DEF_RVV_X32_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
1099 DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1100 DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf4_t, 0)
1101 DEF_RVV_X32_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
1102 DEF_RVV_X32_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1103
1104 DEF_RVV_X64_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1105 DEF_RVV_X64_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
1106
1107 DEF_RVV_LMUL1_OPS (vint8m1_t, 0)
1108 DEF_RVV_LMUL1_OPS (vint16m1_t, 0)
1109 DEF_RVV_LMUL1_OPS (vint32m1_t, 0)
1110 DEF_RVV_LMUL1_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
1111 DEF_RVV_LMUL1_OPS (vuint8m1_t, 0)
1112 DEF_RVV_LMUL1_OPS (vuint16m1_t, 0)
1113 DEF_RVV_LMUL1_OPS (vuint32m1_t, 0)
1114 DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
1115 DEF_RVV_LMUL1_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
1116 DEF_RVV_LMUL1_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
1117 DEF_RVV_LMUL1_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
1118
1119 DEF_RVV_LMUL2_OPS (vint8m2_t, 0)
1120 DEF_RVV_LMUL2_OPS (vint16m2_t, 0)
1121 DEF_RVV_LMUL2_OPS (vint32m2_t, 0)
1122 DEF_RVV_LMUL2_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
1123 DEF_RVV_LMUL2_OPS (vuint8m2_t, 0)
1124 DEF_RVV_LMUL2_OPS (vuint16m2_t, 0)
1125 DEF_RVV_LMUL2_OPS (vuint32m2_t, 0)
1126 DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
1127 DEF_RVV_LMUL2_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
1128 DEF_RVV_LMUL2_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
1129 DEF_RVV_LMUL2_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
1130
1131 DEF_RVV_LMUL4_OPS (vint8m4_t, 0)
1132 DEF_RVV_LMUL4_OPS (vint16m4_t, 0)
1133 DEF_RVV_LMUL4_OPS (vint32m4_t, 0)
1134 DEF_RVV_LMUL4_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
1135 DEF_RVV_LMUL4_OPS (vuint8m4_t, 0)
1136 DEF_RVV_LMUL4_OPS (vuint16m4_t, 0)
1137 DEF_RVV_LMUL4_OPS (vuint32m4_t, 0)
1138 DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
1139 DEF_RVV_LMUL4_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
1140 DEF_RVV_LMUL4_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
1141 DEF_RVV_LMUL4_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
1142
1143 DEF_RVV_TUPLE_OPS (vint8mf8x2_t, RVV_REQUIRE_MIN_VLEN_64)
1144 DEF_RVV_TUPLE_OPS (vuint8mf8x2_t, RVV_REQUIRE_MIN_VLEN_64)
1145 DEF_RVV_TUPLE_OPS (vint8mf8x3_t, RVV_REQUIRE_MIN_VLEN_64)
1146 DEF_RVV_TUPLE_OPS (vuint8mf8x3_t, RVV_REQUIRE_MIN_VLEN_64)
1147 DEF_RVV_TUPLE_OPS (vint8mf8x4_t, RVV_REQUIRE_MIN_VLEN_64)
1148 DEF_RVV_TUPLE_OPS (vuint8mf8x4_t, RVV_REQUIRE_MIN_VLEN_64)
1149 DEF_RVV_TUPLE_OPS (vint8mf8x5_t, RVV_REQUIRE_MIN_VLEN_64)
1150 DEF_RVV_TUPLE_OPS (vuint8mf8x5_t, RVV_REQUIRE_MIN_VLEN_64)
1151 DEF_RVV_TUPLE_OPS (vint8mf8x6_t, RVV_REQUIRE_MIN_VLEN_64)
1152 DEF_RVV_TUPLE_OPS (vuint8mf8x6_t, RVV_REQUIRE_MIN_VLEN_64)
1153 DEF_RVV_TUPLE_OPS (vint8mf8x7_t, RVV_REQUIRE_MIN_VLEN_64)
1154 DEF_RVV_TUPLE_OPS (vuint8mf8x7_t, RVV_REQUIRE_MIN_VLEN_64)
1155 DEF_RVV_TUPLE_OPS (vint8mf8x8_t, RVV_REQUIRE_MIN_VLEN_64)
1156 DEF_RVV_TUPLE_OPS (vuint8mf8x8_t, RVV_REQUIRE_MIN_VLEN_64)
1157 DEF_RVV_TUPLE_OPS (vint8mf4x2_t, 0)
1158 DEF_RVV_TUPLE_OPS (vuint8mf4x2_t, 0)
1159 DEF_RVV_TUPLE_OPS (vint8mf4x3_t, 0)
1160 DEF_RVV_TUPLE_OPS (vuint8mf4x3_t, 0)
1161 DEF_RVV_TUPLE_OPS (vint8mf4x4_t, 0)
1162 DEF_RVV_TUPLE_OPS (vuint8mf4x4_t, 0)
1163 DEF_RVV_TUPLE_OPS (vint8mf4x5_t, 0)
1164 DEF_RVV_TUPLE_OPS (vuint8mf4x5_t, 0)
1165 DEF_RVV_TUPLE_OPS (vint8mf4x6_t, 0)
1166 DEF_RVV_TUPLE_OPS (vuint8mf4x6_t, 0)
1167 DEF_RVV_TUPLE_OPS (vint8mf4x7_t, 0)
1168 DEF_RVV_TUPLE_OPS (vuint8mf4x7_t, 0)
1169 DEF_RVV_TUPLE_OPS (vint8mf4x8_t, 0)
1170 DEF_RVV_TUPLE_OPS (vuint8mf4x8_t, 0)
1171 DEF_RVV_TUPLE_OPS (vint8mf2x2_t, 0)
1172 DEF_RVV_TUPLE_OPS (vuint8mf2x2_t, 0)
1173 DEF_RVV_TUPLE_OPS (vint8mf2x3_t, 0)
1174 DEF_RVV_TUPLE_OPS (vuint8mf2x3_t, 0)
1175 DEF_RVV_TUPLE_OPS (vint8mf2x4_t, 0)
1176 DEF_RVV_TUPLE_OPS (vuint8mf2x4_t, 0)
1177 DEF_RVV_TUPLE_OPS (vint8mf2x5_t, 0)
1178 DEF_RVV_TUPLE_OPS (vuint8mf2x5_t, 0)
1179 DEF_RVV_TUPLE_OPS (vint8mf2x6_t, 0)
1180 DEF_RVV_TUPLE_OPS (vuint8mf2x6_t, 0)
1181 DEF_RVV_TUPLE_OPS (vint8mf2x7_t, 0)
1182 DEF_RVV_TUPLE_OPS (vuint8mf2x7_t, 0)
1183 DEF_RVV_TUPLE_OPS (vint8mf2x8_t, 0)
1184 DEF_RVV_TUPLE_OPS (vuint8mf2x8_t, 0)
1185 DEF_RVV_TUPLE_OPS (vint8m1x2_t, 0)
1186 DEF_RVV_TUPLE_OPS (vuint8m1x2_t, 0)
1187 DEF_RVV_TUPLE_OPS (vint8m1x3_t, 0)
1188 DEF_RVV_TUPLE_OPS (vuint8m1x3_t, 0)
1189 DEF_RVV_TUPLE_OPS (vint8m1x4_t, 0)
1190 DEF_RVV_TUPLE_OPS (vuint8m1x4_t, 0)
1191 DEF_RVV_TUPLE_OPS (vint8m1x5_t, 0)
1192 DEF_RVV_TUPLE_OPS (vuint8m1x5_t, 0)
1193 DEF_RVV_TUPLE_OPS (vint8m1x6_t, 0)
1194 DEF_RVV_TUPLE_OPS (vuint8m1x6_t, 0)
1195 DEF_RVV_TUPLE_OPS (vint8m1x7_t, 0)
1196 DEF_RVV_TUPLE_OPS (vuint8m1x7_t, 0)
1197 DEF_RVV_TUPLE_OPS (vint8m1x8_t, 0)
1198 DEF_RVV_TUPLE_OPS (vuint8m1x8_t, 0)
1199 DEF_RVV_TUPLE_OPS (vint8m2x2_t, 0)
1200 DEF_RVV_TUPLE_OPS (vuint8m2x2_t, 0)
1201 DEF_RVV_TUPLE_OPS (vint8m2x3_t, 0)
1202 DEF_RVV_TUPLE_OPS (vuint8m2x3_t, 0)
1203 DEF_RVV_TUPLE_OPS (vint8m2x4_t, 0)
1204 DEF_RVV_TUPLE_OPS (vuint8m2x4_t, 0)
1205 DEF_RVV_TUPLE_OPS (vint8m4x2_t, 0)
1206 DEF_RVV_TUPLE_OPS (vuint8m4x2_t, 0)
1207 DEF_RVV_TUPLE_OPS (vint16mf4x2_t, RVV_REQUIRE_MIN_VLEN_64)
1208 DEF_RVV_TUPLE_OPS (vuint16mf4x2_t, RVV_REQUIRE_MIN_VLEN_64)
1209 DEF_RVV_TUPLE_OPS (vint16mf4x3_t, RVV_REQUIRE_MIN_VLEN_64)
1210 DEF_RVV_TUPLE_OPS (vuint16mf4x3_t, RVV_REQUIRE_MIN_VLEN_64)
1211 DEF_RVV_TUPLE_OPS (vint16mf4x4_t, RVV_REQUIRE_MIN_VLEN_64)
1212 DEF_RVV_TUPLE_OPS (vuint16mf4x4_t, RVV_REQUIRE_MIN_VLEN_64)
1213 DEF_RVV_TUPLE_OPS (vint16mf4x5_t, RVV_REQUIRE_MIN_VLEN_64)
1214 DEF_RVV_TUPLE_OPS (vuint16mf4x5_t, RVV_REQUIRE_MIN_VLEN_64)
1215 DEF_RVV_TUPLE_OPS (vint16mf4x6_t, RVV_REQUIRE_MIN_VLEN_64)
1216 DEF_RVV_TUPLE_OPS (vuint16mf4x6_t, RVV_REQUIRE_MIN_VLEN_64)
1217 DEF_RVV_TUPLE_OPS (vint16mf4x7_t, RVV_REQUIRE_MIN_VLEN_64)
1218 DEF_RVV_TUPLE_OPS (vuint16mf4x7_t, RVV_REQUIRE_MIN_VLEN_64)
1219 DEF_RVV_TUPLE_OPS (vint16mf4x8_t, RVV_REQUIRE_MIN_VLEN_64)
1220 DEF_RVV_TUPLE_OPS (vuint16mf4x8_t, RVV_REQUIRE_MIN_VLEN_64)
1221 DEF_RVV_TUPLE_OPS (vint16mf2x2_t, 0)
1222 DEF_RVV_TUPLE_OPS (vuint16mf2x2_t, 0)
1223 DEF_RVV_TUPLE_OPS (vint16mf2x3_t, 0)
1224 DEF_RVV_TUPLE_OPS (vuint16mf2x3_t, 0)
1225 DEF_RVV_TUPLE_OPS (vint16mf2x4_t, 0)
1226 DEF_RVV_TUPLE_OPS (vuint16mf2x4_t, 0)
1227 DEF_RVV_TUPLE_OPS (vint16mf2x5_t, 0)
1228 DEF_RVV_TUPLE_OPS (vuint16mf2x5_t, 0)
1229 DEF_RVV_TUPLE_OPS (vint16mf2x6_t, 0)
1230 DEF_RVV_TUPLE_OPS (vuint16mf2x6_t, 0)
1231 DEF_RVV_TUPLE_OPS (vint16mf2x7_t, 0)
1232 DEF_RVV_TUPLE_OPS (vuint16mf2x7_t, 0)
1233 DEF_RVV_TUPLE_OPS (vint16mf2x8_t, 0)
1234 DEF_RVV_TUPLE_OPS (vuint16mf2x8_t, 0)
1235 DEF_RVV_TUPLE_OPS (vint16m1x2_t, 0)
1236 DEF_RVV_TUPLE_OPS (vuint16m1x2_t, 0)
1237 DEF_RVV_TUPLE_OPS (vint16m1x3_t, 0)
1238 DEF_RVV_TUPLE_OPS (vuint16m1x3_t, 0)
1239 DEF_RVV_TUPLE_OPS (vint16m1x4_t, 0)
1240 DEF_RVV_TUPLE_OPS (vuint16m1x4_t, 0)
1241 DEF_RVV_TUPLE_OPS (vint16m1x5_t, 0)
1242 DEF_RVV_TUPLE_OPS (vuint16m1x5_t, 0)
1243 DEF_RVV_TUPLE_OPS (vint16m1x6_t, 0)
1244 DEF_RVV_TUPLE_OPS (vuint16m1x6_t, 0)
1245 DEF_RVV_TUPLE_OPS (vint16m1x7_t, 0)
1246 DEF_RVV_TUPLE_OPS (vuint16m1x7_t, 0)
1247 DEF_RVV_TUPLE_OPS (vint16m1x8_t, 0)
1248 DEF_RVV_TUPLE_OPS (vuint16m1x8_t, 0)
1249 DEF_RVV_TUPLE_OPS (vint16m2x2_t, 0)
1250 DEF_RVV_TUPLE_OPS (vuint16m2x2_t, 0)
1251 DEF_RVV_TUPLE_OPS (vint16m2x3_t, 0)
1252 DEF_RVV_TUPLE_OPS (vuint16m2x3_t, 0)
1253 DEF_RVV_TUPLE_OPS (vint16m2x4_t, 0)
1254 DEF_RVV_TUPLE_OPS (vuint16m2x4_t, 0)
1255 DEF_RVV_TUPLE_OPS (vint16m4x2_t, 0)
1256 DEF_RVV_TUPLE_OPS (vuint16m4x2_t, 0)
1257 DEF_RVV_TUPLE_OPS (vint32mf2x2_t, RVV_REQUIRE_MIN_VLEN_64)
1258 DEF_RVV_TUPLE_OPS (vuint32mf2x2_t, RVV_REQUIRE_MIN_VLEN_64)
1259 DEF_RVV_TUPLE_OPS (vint32mf2x3_t, RVV_REQUIRE_MIN_VLEN_64)
1260 DEF_RVV_TUPLE_OPS (vuint32mf2x3_t, RVV_REQUIRE_MIN_VLEN_64)
1261 DEF_RVV_TUPLE_OPS (vint32mf2x4_t, RVV_REQUIRE_MIN_VLEN_64)
1262 DEF_RVV_TUPLE_OPS (vuint32mf2x4_t, RVV_REQUIRE_MIN_VLEN_64)
1263 DEF_RVV_TUPLE_OPS (vint32mf2x5_t, RVV_REQUIRE_MIN_VLEN_64)
1264 DEF_RVV_TUPLE_OPS (vuint32mf2x5_t, RVV_REQUIRE_MIN_VLEN_64)
1265 DEF_RVV_TUPLE_OPS (vint32mf2x6_t, RVV_REQUIRE_MIN_VLEN_64)
1266 DEF_RVV_TUPLE_OPS (vuint32mf2x6_t, RVV_REQUIRE_MIN_VLEN_64)
1267 DEF_RVV_TUPLE_OPS (vint32mf2x7_t, RVV_REQUIRE_MIN_VLEN_64)
1268 DEF_RVV_TUPLE_OPS (vuint32mf2x7_t, RVV_REQUIRE_MIN_VLEN_64)
1269 DEF_RVV_TUPLE_OPS (vint32mf2x8_t, RVV_REQUIRE_MIN_VLEN_64)
1270 DEF_RVV_TUPLE_OPS (vuint32mf2x8_t, RVV_REQUIRE_MIN_VLEN_64)
1271 DEF_RVV_TUPLE_OPS (vint32m1x2_t, 0)
1272 DEF_RVV_TUPLE_OPS (vuint32m1x2_t, 0)
1273 DEF_RVV_TUPLE_OPS (vint32m1x3_t, 0)
1274 DEF_RVV_TUPLE_OPS (vuint32m1x3_t, 0)
1275 DEF_RVV_TUPLE_OPS (vint32m1x4_t, 0)
1276 DEF_RVV_TUPLE_OPS (vuint32m1x4_t, 0)
1277 DEF_RVV_TUPLE_OPS (vint32m1x5_t, 0)
1278 DEF_RVV_TUPLE_OPS (vuint32m1x5_t, 0)
1279 DEF_RVV_TUPLE_OPS (vint32m1x6_t, 0)
1280 DEF_RVV_TUPLE_OPS (vuint32m1x6_t, 0)
1281 DEF_RVV_TUPLE_OPS (vint32m1x7_t, 0)
1282 DEF_RVV_TUPLE_OPS (vuint32m1x7_t, 0)
1283 DEF_RVV_TUPLE_OPS (vint32m1x8_t, 0)
1284 DEF_RVV_TUPLE_OPS (vuint32m1x8_t, 0)
1285 DEF_RVV_TUPLE_OPS (vint32m2x2_t, 0)
1286 DEF_RVV_TUPLE_OPS (vuint32m2x2_t, 0)
1287 DEF_RVV_TUPLE_OPS (vint32m2x3_t, 0)
1288 DEF_RVV_TUPLE_OPS (vuint32m2x3_t, 0)
1289 DEF_RVV_TUPLE_OPS (vint32m2x4_t, 0)
1290 DEF_RVV_TUPLE_OPS (vuint32m2x4_t, 0)
1291 DEF_RVV_TUPLE_OPS (vint32m4x2_t, 0)
1292 DEF_RVV_TUPLE_OPS (vuint32m4x2_t, 0)
1293 DEF_RVV_TUPLE_OPS (vint64m1x2_t, RVV_REQUIRE_ELEN_64)
1294 DEF_RVV_TUPLE_OPS (vuint64m1x2_t, RVV_REQUIRE_ELEN_64)
1295 DEF_RVV_TUPLE_OPS (vint64m1x3_t, RVV_REQUIRE_ELEN_64)
1296 DEF_RVV_TUPLE_OPS (vuint64m1x3_t, RVV_REQUIRE_ELEN_64)
1297 DEF_RVV_TUPLE_OPS (vint64m1x4_t, RVV_REQUIRE_ELEN_64)
1298 DEF_RVV_TUPLE_OPS (vuint64m1x4_t, RVV_REQUIRE_ELEN_64)
1299 DEF_RVV_TUPLE_OPS (vint64m1x5_t, RVV_REQUIRE_ELEN_64)
1300 DEF_RVV_TUPLE_OPS (vuint64m1x5_t, RVV_REQUIRE_ELEN_64)
1301 DEF_RVV_TUPLE_OPS (vint64m1x6_t, RVV_REQUIRE_ELEN_64)
1302 DEF_RVV_TUPLE_OPS (vuint64m1x6_t, RVV_REQUIRE_ELEN_64)
1303 DEF_RVV_TUPLE_OPS (vint64m1x7_t, RVV_REQUIRE_ELEN_64)
1304 DEF_RVV_TUPLE_OPS (vuint64m1x7_t, RVV_REQUIRE_ELEN_64)
1305 DEF_RVV_TUPLE_OPS (vint64m1x8_t, RVV_REQUIRE_ELEN_64)
1306 DEF_RVV_TUPLE_OPS (vuint64m1x8_t, RVV_REQUIRE_ELEN_64)
1307 DEF_RVV_TUPLE_OPS (vint64m2x2_t, RVV_REQUIRE_ELEN_64)
1308 DEF_RVV_TUPLE_OPS (vuint64m2x2_t, RVV_REQUIRE_ELEN_64)
1309 DEF_RVV_TUPLE_OPS (vint64m2x3_t, RVV_REQUIRE_ELEN_64)
1310 DEF_RVV_TUPLE_OPS (vuint64m2x3_t, RVV_REQUIRE_ELEN_64)
1311 DEF_RVV_TUPLE_OPS (vint64m2x4_t, RVV_REQUIRE_ELEN_64)
1312 DEF_RVV_TUPLE_OPS (vuint64m2x4_t, RVV_REQUIRE_ELEN_64)
1313 DEF_RVV_TUPLE_OPS (vint64m4x2_t, RVV_REQUIRE_ELEN_64)
1314 DEF_RVV_TUPLE_OPS (vuint64m4x2_t, RVV_REQUIRE_ELEN_64)
1315 DEF_RVV_TUPLE_OPS (vfloat16mf4x2_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1316 DEF_RVV_TUPLE_OPS (vfloat16mf4x3_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1317 DEF_RVV_TUPLE_OPS (vfloat16mf4x4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1318 DEF_RVV_TUPLE_OPS (vfloat16mf4x5_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1319 DEF_RVV_TUPLE_OPS (vfloat16mf4x6_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1320 DEF_RVV_TUPLE_OPS (vfloat16mf4x7_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1321 DEF_RVV_TUPLE_OPS (vfloat16mf4x8_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
1322 DEF_RVV_TUPLE_OPS (vfloat16mf2x2_t, RVV_REQUIRE_ELEN_FP_16)
1323 DEF_RVV_TUPLE_OPS (vfloat16mf2x3_t, RVV_REQUIRE_ELEN_FP_16)
1324 DEF_RVV_TUPLE_OPS (vfloat16mf2x4_t, RVV_REQUIRE_ELEN_FP_16)
1325 DEF_RVV_TUPLE_OPS (vfloat16mf2x5_t, RVV_REQUIRE_ELEN_FP_16)
1326 DEF_RVV_TUPLE_OPS (vfloat16mf2x6_t, RVV_REQUIRE_ELEN_FP_16)
1327 DEF_RVV_TUPLE_OPS (vfloat16mf2x7_t, RVV_REQUIRE_ELEN_FP_16)
1328 DEF_RVV_TUPLE_OPS (vfloat16mf2x8_t, RVV_REQUIRE_ELEN_FP_16)
1329 DEF_RVV_TUPLE_OPS (vfloat16m1x2_t, RVV_REQUIRE_ELEN_FP_16)
1330 DEF_RVV_TUPLE_OPS (vfloat16m1x3_t, RVV_REQUIRE_ELEN_FP_16)
1331 DEF_RVV_TUPLE_OPS (vfloat16m1x4_t, RVV_REQUIRE_ELEN_FP_16)
1332 DEF_RVV_TUPLE_OPS (vfloat16m1x5_t, RVV_REQUIRE_ELEN_FP_16)
1333 DEF_RVV_TUPLE_OPS (vfloat16m1x6_t, RVV_REQUIRE_ELEN_FP_16)
1334 DEF_RVV_TUPLE_OPS (vfloat16m1x7_t, RVV_REQUIRE_ELEN_FP_16)
1335 DEF_RVV_TUPLE_OPS (vfloat16m1x8_t, RVV_REQUIRE_ELEN_FP_16)
1336 DEF_RVV_TUPLE_OPS (vfloat16m2x2_t, RVV_REQUIRE_ELEN_FP_16)
1337 DEF_RVV_TUPLE_OPS (vfloat16m2x3_t, RVV_REQUIRE_ELEN_FP_16)
1338 DEF_RVV_TUPLE_OPS (vfloat16m2x4_t, RVV_REQUIRE_ELEN_FP_16)
1339 DEF_RVV_TUPLE_OPS (vfloat16m4x2_t, RVV_REQUIRE_ELEN_FP_16)
1340 DEF_RVV_TUPLE_OPS (vfloat32mf2x2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1341 DEF_RVV_TUPLE_OPS (vfloat32mf2x3_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1342 DEF_RVV_TUPLE_OPS (vfloat32mf2x4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1343 DEF_RVV_TUPLE_OPS (vfloat32mf2x5_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1344 DEF_RVV_TUPLE_OPS (vfloat32mf2x6_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1345 DEF_RVV_TUPLE_OPS (vfloat32mf2x7_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1346 DEF_RVV_TUPLE_OPS (vfloat32mf2x8_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
1347 DEF_RVV_TUPLE_OPS (vfloat32m1x2_t, RVV_REQUIRE_ELEN_FP_32)
1348 DEF_RVV_TUPLE_OPS (vfloat32m1x3_t, RVV_REQUIRE_ELEN_FP_32)
1349 DEF_RVV_TUPLE_OPS (vfloat32m1x4_t, RVV_REQUIRE_ELEN_FP_32)
1350 DEF_RVV_TUPLE_OPS (vfloat32m1x5_t, RVV_REQUIRE_ELEN_FP_32)
1351 DEF_RVV_TUPLE_OPS (vfloat32m1x6_t, RVV_REQUIRE_ELEN_FP_32)
1352 DEF_RVV_TUPLE_OPS (vfloat32m1x7_t, RVV_REQUIRE_ELEN_FP_32)
1353 DEF_RVV_TUPLE_OPS (vfloat32m1x8_t, RVV_REQUIRE_ELEN_FP_32)
1354 DEF_RVV_TUPLE_OPS (vfloat32m2x2_t, RVV_REQUIRE_ELEN_FP_32)
1355 DEF_RVV_TUPLE_OPS (vfloat32m2x3_t, RVV_REQUIRE_ELEN_FP_32)
1356 DEF_RVV_TUPLE_OPS (vfloat32m2x4_t, RVV_REQUIRE_ELEN_FP_32)
1357 DEF_RVV_TUPLE_OPS (vfloat32m4x2_t, RVV_REQUIRE_ELEN_FP_32)
1358 DEF_RVV_TUPLE_OPS (vfloat64m1x2_t, RVV_REQUIRE_ELEN_FP_64)
1359 DEF_RVV_TUPLE_OPS (vfloat64m1x3_t, RVV_REQUIRE_ELEN_FP_64)
1360 DEF_RVV_TUPLE_OPS (vfloat64m1x4_t, RVV_REQUIRE_ELEN_FP_64)
1361 DEF_RVV_TUPLE_OPS (vfloat64m1x5_t, RVV_REQUIRE_ELEN_FP_64)
1362 DEF_RVV_TUPLE_OPS (vfloat64m1x6_t, RVV_REQUIRE_ELEN_FP_64)
1363 DEF_RVV_TUPLE_OPS (vfloat64m1x7_t, RVV_REQUIRE_ELEN_FP_64)
1364 DEF_RVV_TUPLE_OPS (vfloat64m1x8_t, RVV_REQUIRE_ELEN_FP_64)
1365 DEF_RVV_TUPLE_OPS (vfloat64m2x2_t, RVV_REQUIRE_ELEN_FP_64)
1366 DEF_RVV_TUPLE_OPS (vfloat64m2x3_t, RVV_REQUIRE_ELEN_FP_64)
1367 DEF_RVV_TUPLE_OPS (vfloat64m2x4_t, RVV_REQUIRE_ELEN_FP_64)
1368 DEF_RVV_TUPLE_OPS (vfloat64m4x2_t, RVV_REQUIRE_ELEN_FP_64)
1369
1370 DEF_RVV_CRYPTO_SEW32_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
1371 DEF_RVV_CRYPTO_SEW32_OPS (vuint32m1_t, 0)
1372 DEF_RVV_CRYPTO_SEW32_OPS (vuint32m2_t, 0)
1373 DEF_RVV_CRYPTO_SEW32_OPS (vuint32m4_t, 0)
1374 DEF_RVV_CRYPTO_SEW32_OPS (vuint32m8_t, 0)
1375
1376 DEF_RVV_CRYPTO_SEW64_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
1377 DEF_RVV_CRYPTO_SEW64_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
1378 DEF_RVV_CRYPTO_SEW64_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
1379 DEF_RVV_CRYPTO_SEW64_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
1380
1381 #undef DEF_RVV_I_OPS
1382 #undef DEF_RVV_U_OPS
1383 #undef DEF_RVV_F_OPS
1384 #undef DEF_RVV_B_OPS
1385 #undef DEF_RVV_WEXTI_OPS
1386 #undef DEF_RVV_QEXTI_OPS
1387 #undef DEF_RVV_OEXTI_OPS
1388 #undef DEF_RVV_WEXTU_OPS
1389 #undef DEF_RVV_QEXTU_OPS
1390 #undef DEF_RVV_OEXTU_OPS
1391 #undef DEF_RVV_FULL_V_I_OPS
1392 #undef DEF_RVV_FULL_V_U_OPS
1393 #undef DEF_RVV_WEXTF_OPS
1394 #undef DEF_RVV_CONVERT_I_OPS
1395 #undef DEF_RVV_CONVERT_U_OPS
1396 #undef DEF_RVV_WCONVERT_I_OPS
1397 #undef DEF_RVV_WCONVERT_U_OPS
1398 #undef DEF_RVV_WCONVERT_F_OPS
1399 #undef DEF_RVV_WI_OPS
1400 #undef DEF_RVV_WU_OPS
1401 #undef DEF_RVV_WF_OPS
1402 #undef DEF_RVV_EI16_OPS
1403 #undef DEF_RVV_EEW8_INTERPRET_OPS
1404 #undef DEF_RVV_EEW16_INTERPRET_OPS
1405 #undef DEF_RVV_EEW32_INTERPRET_OPS
1406 #undef DEF_RVV_EEW64_INTERPRET_OPS
1407 #undef DEF_RVV_BOOL1_INTERPRET_OPS
1408 #undef DEF_RVV_BOOL2_INTERPRET_OPS
1409 #undef DEF_RVV_BOOL4_INTERPRET_OPS
1410 #undef DEF_RVV_BOOL8_INTERPRET_OPS
1411 #undef DEF_RVV_BOOL16_INTERPRET_OPS
1412 #undef DEF_RVV_BOOL32_INTERPRET_OPS
1413 #undef DEF_RVV_BOOL64_INTERPRET_OPS
1414 #undef DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS
1415 #undef DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS
1416 #undef DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS
1417 #undef DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS
1418 #undef DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS
1419 #undef DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS
1420 #undef DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS
1421 #undef DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS
1422 #undef DEF_RVV_X2_VLMUL_EXT_OPS
1423 #undef DEF_RVV_X4_VLMUL_EXT_OPS
1424 #undef DEF_RVV_X8_VLMUL_EXT_OPS
1425 #undef DEF_RVV_X16_VLMUL_EXT_OPS
1426 #undef DEF_RVV_X32_VLMUL_EXT_OPS
1427 #undef DEF_RVV_X64_VLMUL_EXT_OPS
1428 #undef DEF_RVV_LMUL1_OPS
1429 #undef DEF_RVV_LMUL2_OPS
1430 #undef DEF_RVV_LMUL4_OPS
1431 #undef DEF_RVV_TUPLE_OPS
1432 #undef DEF_RVV_CRYPTO_SEW32_OPS
1433 #undef DEF_RVV_CRYPTO_SEW64_OPS