1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "rtl-error.h"
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "hard-reg-set.h"
32 #include "addresses.h"
36 #include "basic-block.h"
39 #include "tree-pass.h"
41 #include "insn-codes.h"
43 #ifndef STACK_PUSH_CODE
44 #ifdef STACK_GROWS_DOWNWARD
45 #define STACK_PUSH_CODE PRE_DEC
47 #define STACK_PUSH_CODE PRE_INC
51 #ifndef STACK_POP_CODE
52 #ifdef STACK_GROWS_DOWNWARD
53 #define STACK_POP_CODE POST_INC
55 #define STACK_POP_CODE POST_DEC
59 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
60 static void validate_replace_src_1 (rtx
*, void *);
61 static rtx
split_insn (rtx
);
63 /* Nonzero means allow operands to be volatile.
64 This should be 0 if you are generating rtl, such as if you are calling
65 the functions in optabs.c and expmed.c (most of the time).
66 This should be 1 if all valid insns need to be recognized,
67 such as in reginfo.c and final.c and reload.c.
69 init_recog and init_recog_no_volatile are responsible for setting this. */
73 struct recog_data recog_data
;
75 /* Contains a vector of operand_alternative structures for every operand.
76 Set up by preprocess_constraints. */
77 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
79 /* On return from `constrain_operands', indicate which alternative
82 int which_alternative
;
84 /* Nonzero after end of reload pass.
85 Set to 1 or 0 by toplev.c.
86 Controls the significance of (SUBREG (MEM)). */
90 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
91 int epilogue_completed
;
93 /* Initialize data used by the function `recog'.
94 This must be called once in the compilation of a function
95 before any insn recognition may be done in the function. */
98 init_recog_no_volatile (void)
110 /* Return true if labels in asm operands BODY are LABEL_REFs. */
113 asm_labels_ok (rtx body
)
118 asmop
= extract_asm_operands (body
);
119 if (asmop
== NULL_RTX
)
122 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
123 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
129 /* Check that X is an insn-body for an `asm' with operands
130 and that the operands mentioned in it are legitimate. */
133 check_asm_operands (rtx x
)
137 const char **constraints
;
140 if (!asm_labels_ok (x
))
143 /* Post-reload, be more strict with things. */
144 if (reload_completed
)
146 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
147 extract_insn (make_insn_raw (x
));
148 constrain_operands (1);
149 return which_alternative
>= 0;
152 noperands
= asm_noperands (x
);
158 operands
= XALLOCAVEC (rtx
, noperands
);
159 constraints
= XALLOCAVEC (const char *, noperands
);
161 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
163 for (i
= 0; i
< noperands
; i
++)
165 const char *c
= constraints
[i
];
168 if (! asm_operand_ok (operands
[i
], c
, constraints
))
175 /* Static data for the next two routines. */
177 typedef struct change_t
186 static change_t
*changes
;
187 static int changes_allocated
;
189 static int num_changes
= 0;
191 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
192 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
193 the change is simply made.
195 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
196 will be called with the address and mode as parameters. If OBJECT is
197 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
200 IN_GROUP is nonzero if this is part of a group of changes that must be
201 performed as a group. In that case, the changes will be stored. The
202 function `apply_change_group' will validate and apply the changes.
204 If IN_GROUP is zero, this is a single change. Try to recognize the insn
205 or validate the memory reference with the change applied. If the result
206 is not valid for the machine, suppress the change and return zero.
207 Otherwise, perform the change and return 1. */
210 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
214 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
217 gcc_assert (in_group
!= 0 || num_changes
== 0);
221 /* Save the information describing this change. */
222 if (num_changes
>= changes_allocated
)
224 if (changes_allocated
== 0)
225 /* This value allows for repeated substitutions inside complex
226 indexed addresses, or changes in up to 5 insns. */
227 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
229 changes_allocated
*= 2;
231 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
234 changes
[num_changes
].object
= object
;
235 changes
[num_changes
].loc
= loc
;
236 changes
[num_changes
].old
= old
;
237 changes
[num_changes
].unshare
= unshare
;
239 if (object
&& !MEM_P (object
))
241 /* Set INSN_CODE to force rerecognition of insn. Save old code in
243 changes
[num_changes
].old_code
= INSN_CODE (object
);
244 INSN_CODE (object
) = -1;
249 /* If we are making a group of changes, return 1. Otherwise, validate the
250 change group we made. */
255 return apply_change_group ();
258 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
262 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
264 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
267 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
271 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
273 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
277 /* Keep X canonicalized if some changes have made it non-canonical; only
278 modifies the operands of X, not (for example) its code. Simplifications
279 are not the job of this routine.
281 Return true if anything was changed. */
283 canonicalize_change_group (rtx insn
, rtx x
)
285 if (COMMUTATIVE_P (x
)
286 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
288 /* Oops, the caller has made X no longer canonical.
289 Let's redo the changes in the correct order. */
290 rtx tem
= XEXP (x
, 0);
291 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
292 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
300 /* This subroutine of apply_change_group verifies whether the changes to INSN
301 were valid; i.e. whether INSN can still be recognized.
303 If IN_GROUP is true clobbers which have to be added in order to
304 match the instructions will be added to the current change group.
305 Otherwise the changes will take effect immediately. */
308 insn_invalid_p (rtx insn
, bool in_group
)
310 rtx pat
= PATTERN (insn
);
311 int num_clobbers
= 0;
312 /* If we are before reload and the pattern is a SET, see if we can add
314 int icode
= recog (pat
, insn
,
315 (GET_CODE (pat
) == SET
316 && ! reload_completed
&& ! reload_in_progress
)
317 ? &num_clobbers
: 0);
318 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
321 /* If this is an asm and the operand aren't legal, then fail. Likewise if
322 this is not an asm and the insn wasn't recognized. */
323 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
324 || (!is_asm
&& icode
< 0))
327 /* If we have to add CLOBBERs, fail if we have to add ones that reference
328 hard registers since our callers can't know if they are live or not.
329 Otherwise, add them. */
330 if (num_clobbers
> 0)
334 if (added_clobbers_hard_reg_p (icode
))
337 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
338 XVECEXP (newpat
, 0, 0) = pat
;
339 add_clobbers (newpat
, icode
);
341 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
343 PATTERN (insn
) = pat
= newpat
;
346 /* After reload, verify that all constraints are satisfied. */
347 if (reload_completed
)
351 if (! constrain_operands (1))
355 INSN_CODE (insn
) = icode
;
359 /* Return number of changes made and not validated yet. */
361 num_changes_pending (void)
366 /* Tentatively apply the changes numbered NUM and up.
367 Return 1 if all changes are valid, zero otherwise. */
370 verify_changes (int num
)
373 rtx last_validated
= NULL_RTX
;
375 /* The changes have been applied and all INSN_CODEs have been reset to force
378 The changes are valid if we aren't given an object, or if we are
379 given a MEM and it still is a valid address, or if this is in insn
380 and it is recognized. In the latter case, if reload has completed,
381 we also require that the operands meet the constraints for
384 for (i
= num
; i
< num_changes
; i
++)
386 rtx object
= changes
[i
].object
;
388 /* If there is no object to test or if it is the same as the one we
389 already tested, ignore it. */
390 if (object
== 0 || object
== last_validated
)
395 if (! memory_address_addr_space_p (GET_MODE (object
),
397 MEM_ADDR_SPACE (object
)))
400 else if (REG_P (changes
[i
].old
)
401 && asm_noperands (PATTERN (object
)) > 0
402 && REG_EXPR (changes
[i
].old
) != NULL_TREE
403 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
404 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
406 /* Don't allow changes of hard register operands to inline
407 assemblies if they have been defined as register asm ("x"). */
410 else if (DEBUG_INSN_P (object
))
412 else if (insn_invalid_p (object
, true))
414 rtx pat
= PATTERN (object
);
416 /* Perhaps we couldn't recognize the insn because there were
417 extra CLOBBERs at the end. If so, try to re-recognize
418 without the last CLOBBER (later iterations will cause each of
419 them to be eliminated, in turn). But don't do this if we
420 have an ASM_OPERAND. */
421 if (GET_CODE (pat
) == PARALLEL
422 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
423 && asm_noperands (PATTERN (object
)) < 0)
427 if (XVECLEN (pat
, 0) == 2)
428 newpat
= XVECEXP (pat
, 0, 0);
434 = gen_rtx_PARALLEL (VOIDmode
,
435 rtvec_alloc (XVECLEN (pat
, 0) - 1));
436 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
437 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
440 /* Add a new change to this group to replace the pattern
441 with this new pattern. Then consider this change
442 as having succeeded. The change we added will
443 cause the entire call to fail if things remain invalid.
445 Note that this can lose if a later change than the one
446 we are processing specified &XVECEXP (PATTERN (object), 0, X)
447 but this shouldn't occur. */
449 validate_change (object
, &PATTERN (object
), newpat
, 1);
452 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
453 || GET_CODE (pat
) == VAR_LOCATION
)
454 /* If this insn is a CLOBBER or USE, it is always valid, but is
460 last_validated
= object
;
463 return (i
== num_changes
);
466 /* A group of changes has previously been issued with validate_change
467 and verified with verify_changes. Call df_insn_rescan for each of
468 the insn changed and clear num_changes. */
471 confirm_change_group (void)
474 rtx last_object
= NULL
;
476 for (i
= 0; i
< num_changes
; i
++)
478 rtx object
= changes
[i
].object
;
480 if (changes
[i
].unshare
)
481 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
483 /* Avoid unnecessary rescanning when multiple changes to same instruction
487 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
488 df_insn_rescan (last_object
);
489 last_object
= object
;
493 if (last_object
&& INSN_P (last_object
))
494 df_insn_rescan (last_object
);
498 /* Apply a group of changes previously issued with `validate_change'.
499 If all changes are valid, call confirm_change_group and return 1,
500 otherwise, call cancel_changes and return 0. */
503 apply_change_group (void)
505 if (verify_changes (0))
507 confirm_change_group ();
518 /* Return the number of changes so far in the current group. */
521 num_validated_changes (void)
526 /* Retract the changes numbered NUM and up. */
529 cancel_changes (int num
)
533 /* Back out all the changes. Do this in the opposite order in which
535 for (i
= num_changes
- 1; i
>= num
; i
--)
537 *changes
[i
].loc
= changes
[i
].old
;
538 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
539 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
544 /* Reduce conditional compilation elsewhere. */
547 #define CODE_FOR_extv CODE_FOR_nothing
551 #define CODE_FOR_extzv CODE_FOR_nothing
554 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
558 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
559 enum machine_mode op0_mode
)
562 enum rtx_code code
= GET_CODE (x
);
565 if (SWAPPABLE_OPERANDS_P (x
)
566 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
568 validate_unshare_change (object
, loc
,
569 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
570 : swap_condition (code
),
571 GET_MODE (x
), XEXP (x
, 1),
580 /* If we have a PLUS whose second operand is now a CONST_INT, use
581 simplify_gen_binary to try to simplify it.
582 ??? We may want later to remove this, once simplification is
583 separated from this function. */
584 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
585 validate_change (object
, loc
,
587 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
590 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
591 validate_change (object
, loc
,
593 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
594 simplify_gen_unary (NEG
,
595 GET_MODE (x
), XEXP (x
, 1),
600 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
602 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
604 /* If any of the above failed, substitute in something that
605 we know won't be recognized. */
607 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
608 validate_change (object
, loc
, new_rtx
, 1);
612 /* All subregs possible to simplify should be simplified. */
613 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
616 /* Subregs of VOIDmode operands are incorrect. */
617 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
618 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
620 validate_change (object
, loc
, new_rtx
, 1);
624 /* If we are replacing a register with memory, try to change the memory
625 to be the mode required for memory in extract operations (this isn't
626 likely to be an insertion operation; if it was, nothing bad will
627 happen, we might just fail in some cases). */
629 if (MEM_P (XEXP (x
, 0))
630 && CONST_INT_P (XEXP (x
, 1))
631 && CONST_INT_P (XEXP (x
, 2))
632 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
633 MEM_ADDR_SPACE (XEXP (x
, 0)))
634 && !MEM_VOLATILE_P (XEXP (x
, 0)))
636 enum machine_mode wanted_mode
= VOIDmode
;
637 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
638 int pos
= INTVAL (XEXP (x
, 2));
640 if (GET_CODE (x
) == ZERO_EXTRACT
&& HAVE_extzv
)
642 wanted_mode
= insn_data
[CODE_FOR_extzv
].operand
[1].mode
;
643 if (wanted_mode
== VOIDmode
)
644 wanted_mode
= word_mode
;
646 else if (GET_CODE (x
) == SIGN_EXTRACT
&& HAVE_extv
)
648 wanted_mode
= insn_data
[CODE_FOR_extv
].operand
[1].mode
;
649 if (wanted_mode
== VOIDmode
)
650 wanted_mode
= word_mode
;
653 /* If we have a narrower mode, we can do something. */
654 if (wanted_mode
!= VOIDmode
655 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
657 int offset
= pos
/ BITS_PER_UNIT
;
660 /* If the bytes and bits are counted differently, we
661 must adjust the offset. */
662 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
664 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
667 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
668 == GET_MODE_BITSIZE (wanted_mode
));
669 pos
%= GET_MODE_BITSIZE (wanted_mode
);
671 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
673 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
674 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
685 /* Replace every occurrence of FROM in X with TO. Mark each change with
686 validate_change passing OBJECT. */
689 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
696 enum machine_mode op0_mode
= VOIDmode
;
697 int prev_changes
= num_changes
;
703 fmt
= GET_RTX_FORMAT (code
);
705 op0_mode
= GET_MODE (XEXP (x
, 0));
707 /* X matches FROM if it is the same rtx or they are both referring to the
708 same register in the same mode. Avoid calling rtx_equal_p unless the
709 operands look similar. */
712 || (REG_P (x
) && REG_P (from
)
713 && GET_MODE (x
) == GET_MODE (from
)
714 && REGNO (x
) == REGNO (from
))
715 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
716 && rtx_equal_p (x
, from
)))
718 validate_unshare_change (object
, loc
, to
, 1);
722 /* Call ourself recursively to perform the replacements.
723 We must not replace inside already replaced expression, otherwise we
724 get infinite recursion for replacements like (reg X)->(subreg (reg X))
725 done by regmove, so we must special case shared ASM_OPERANDS. */
727 if (GET_CODE (x
) == PARALLEL
)
729 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
731 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
732 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
734 /* Verify that operands are really shared. */
735 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
736 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
738 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
739 from
, to
, object
, simplify
);
742 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
747 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
750 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
751 else if (fmt
[i
] == 'E')
752 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
753 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
757 /* If we didn't substitute, there is nothing more to do. */
758 if (num_changes
== prev_changes
)
761 /* Allow substituted expression to have different mode. This is used by
762 regmove to change mode of pseudo register. */
763 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
764 op0_mode
= GET_MODE (XEXP (x
, 0));
766 /* Do changes needed to keep rtx consistent. Don't do any other
767 simplifications, as it is not our job. */
769 simplify_while_replacing (loc
, to
, object
, op0_mode
);
772 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
773 with TO. After all changes have been made, validate by seeing
774 if INSN is still valid. */
777 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
779 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
780 return apply_change_group ();
783 /* Try replacing every occurrence of FROM in INSN with TO. After all
784 changes have been made, validate by seeing if INSN is still valid. */
787 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
789 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
790 return apply_change_group ();
793 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
794 is a part of INSN. After all changes have been made, validate by seeing if
796 validate_replace_rtx (from, to, insn) is equivalent to
797 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
800 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
802 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
803 return apply_change_group ();
806 /* Same as above, but do not simplify rtx afterwards. */
808 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
811 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
812 return apply_change_group ();
816 /* Try replacing every occurrence of FROM in INSN with TO. This also
817 will replace in REG_EQUAL and REG_EQUIV notes. */
820 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
823 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
824 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
825 if (REG_NOTE_KIND (note
) == REG_EQUAL
826 || REG_NOTE_KIND (note
) == REG_EQUIV
)
827 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
830 /* Function called by note_uses to replace used subexpressions. */
831 struct validate_replace_src_data
833 rtx from
; /* Old RTX */
834 rtx to
; /* New RTX */
835 rtx insn
; /* Insn in which substitution is occurring. */
839 validate_replace_src_1 (rtx
*x
, void *data
)
841 struct validate_replace_src_data
*d
842 = (struct validate_replace_src_data
*) data
;
844 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
847 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
851 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
853 struct validate_replace_src_data d
;
858 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
861 /* Try simplify INSN.
862 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
863 pattern and return true if something was simplified. */
866 validate_simplify_insn (rtx insn
)
872 pat
= PATTERN (insn
);
874 if (GET_CODE (pat
) == SET
)
876 newpat
= simplify_rtx (SET_SRC (pat
));
877 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
878 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
879 newpat
= simplify_rtx (SET_DEST (pat
));
880 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
881 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
883 else if (GET_CODE (pat
) == PARALLEL
)
884 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
886 rtx s
= XVECEXP (pat
, 0, i
);
888 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
890 newpat
= simplify_rtx (SET_SRC (s
));
891 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
892 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
893 newpat
= simplify_rtx (SET_DEST (s
));
894 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
895 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
898 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
902 /* Return 1 if the insn using CC0 set by INSN does not contain
903 any ordered tests applied to the condition codes.
904 EQ and NE tests do not count. */
907 next_insn_tests_no_inequality (rtx insn
)
909 rtx next
= next_cc0_user (insn
);
911 /* If there is no next insn, we have to take the conservative choice. */
915 return (INSN_P (next
)
916 && ! inequality_comparisons_p (PATTERN (next
)));
920 /* Return 1 if OP is a valid general operand for machine mode MODE.
921 This is either a register reference, a memory reference,
922 or a constant. In the case of a memory reference, the address
923 is checked for general validity for the target machine.
925 Register and memory references must have mode MODE in order to be valid,
926 but some constants have no machine mode and are valid for any mode.
928 If MODE is VOIDmode, OP is checked for validity for whatever mode
931 The main use of this function is as a predicate in match_operand
932 expressions in the machine description. */
935 general_operand (rtx op
, enum machine_mode mode
)
937 enum rtx_code code
= GET_CODE (op
);
939 if (mode
== VOIDmode
)
940 mode
= GET_MODE (op
);
942 /* Don't accept CONST_INT or anything similar
943 if the caller wants something floating. */
944 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
945 && GET_MODE_CLASS (mode
) != MODE_INT
946 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
951 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
955 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
957 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
958 && targetm
.legitimate_constant_p (mode
== VOIDmode
962 /* Except for certain constants with VOIDmode, already checked for,
963 OP's mode must match MODE if MODE specifies a mode. */
965 if (GET_MODE (op
) != mode
)
970 rtx sub
= SUBREG_REG (op
);
972 #ifdef INSN_SCHEDULING
973 /* On machines that have insn scheduling, we want all memory
974 reference to be explicit, so outlaw paradoxical SUBREGs.
975 However, we must allow them after reload so that they can
976 get cleaned up by cleanup_subreg_operands. */
977 if (!reload_completed
&& MEM_P (sub
)
978 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
981 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
982 may result in incorrect reference. We should simplify all valid
983 subregs of MEM anyway. But allow this after reload because we
984 might be called from cleanup_subreg_operands.
986 ??? This is a kludge. */
987 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
991 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
992 create such rtl, and we must reject it. */
993 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
994 /* LRA can use subreg to store a floating point value in an
995 integer mode. Although the floating point and the
996 integer modes need the same number of hard registers, the
997 size of floating point mode can be less than the integer
1000 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1004 code
= GET_CODE (op
);
1008 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1009 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1013 rtx y
= XEXP (op
, 0);
1015 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1018 /* Use the mem's mode, since it will be reloaded thus. */
1019 if (memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1026 /* Return 1 if OP is a valid memory address for a memory reference
1029 The main use of this function is as a predicate in match_operand
1030 expressions in the machine description. */
1033 address_operand (rtx op
, enum machine_mode mode
)
1035 return memory_address_p (mode
, op
);
1038 /* Return 1 if OP is a register reference of mode MODE.
1039 If MODE is VOIDmode, accept a register in any mode.
1041 The main use of this function is as a predicate in match_operand
1042 expressions in the machine description. */
1045 register_operand (rtx op
, enum machine_mode mode
)
1047 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1050 if (GET_CODE (op
) == SUBREG
)
1052 rtx sub
= SUBREG_REG (op
);
1054 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1055 because it is guaranteed to be reloaded into one.
1056 Just make sure the MEM is valid in itself.
1057 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1058 but currently it does result from (SUBREG (REG)...) where the
1059 reg went on the stack.) */
1060 if (! reload_completed
&& MEM_P (sub
))
1061 return general_operand (op
, mode
);
1063 #ifdef CANNOT_CHANGE_MODE_CLASS
1065 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1066 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1067 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1068 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
)
1072 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1073 create such rtl, and we must reject it. */
1074 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1075 /* LRA can use subreg to store a floating point value in an
1076 integer mode. Although the floating point and the
1077 integer modes need the same number of hard registers, the
1078 size of floating point mode can be less than the integer
1080 && ! lra_in_progress
1081 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1088 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1089 || in_hard_reg_set_p (operand_reg_set
,
1090 GET_MODE (op
), REGNO (op
))));
1093 /* Return 1 for a register in Pmode; ignore the tested mode. */
1096 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1098 return register_operand (op
, Pmode
);
1101 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1102 or a hard register. */
1105 scratch_operand (rtx op
, enum machine_mode mode
)
1107 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1110 return (GET_CODE (op
) == SCRATCH
1112 && (lra_in_progress
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)));
1115 /* Return 1 if OP is a valid immediate operand for mode MODE.
1117 The main use of this function is as a predicate in match_operand
1118 expressions in the machine description. */
1121 immediate_operand (rtx op
, enum machine_mode mode
)
1123 /* Don't accept CONST_INT or anything similar
1124 if the caller wants something floating. */
1125 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1126 && GET_MODE_CLASS (mode
) != MODE_INT
1127 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1130 if (CONST_INT_P (op
)
1132 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1135 return (CONSTANT_P (op
)
1136 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1137 || GET_MODE (op
) == VOIDmode
)
1138 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1139 && targetm
.legitimate_constant_p (mode
== VOIDmode
1144 /* Returns 1 if OP is an operand that is a CONST_INT. */
1147 const_int_operand (rtx op
, enum machine_mode mode
)
1149 if (!CONST_INT_P (op
))
1152 if (mode
!= VOIDmode
1153 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1159 /* Returns 1 if OP is an operand that is a constant integer or constant
1160 floating-point number. */
1163 const_double_operand (rtx op
, enum machine_mode mode
)
1165 /* Don't accept CONST_INT or anything similar
1166 if the caller wants something floating. */
1167 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1168 && GET_MODE_CLASS (mode
) != MODE_INT
1169 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1172 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1173 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1174 || GET_MODE (op
) == VOIDmode
));
1177 /* Return 1 if OP is a general operand that is not an immediate operand. */
1180 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1182 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1185 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1188 nonmemory_operand (rtx op
, enum machine_mode mode
)
1190 if (CONSTANT_P (op
))
1191 return immediate_operand (op
, mode
);
1193 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1196 if (GET_CODE (op
) == SUBREG
)
1198 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1199 because it is guaranteed to be reloaded into one.
1200 Just make sure the MEM is valid in itself.
1201 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1202 but currently it does result from (SUBREG (REG)...) where the
1203 reg went on the stack.) */
1204 if (! reload_completed
&& MEM_P (SUBREG_REG (op
)))
1205 return general_operand (op
, mode
);
1206 op
= SUBREG_REG (op
);
1210 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1211 || in_hard_reg_set_p (operand_reg_set
,
1212 GET_MODE (op
), REGNO (op
))));
1215 /* Return 1 if OP is a valid operand that stands for pushing a
1216 value of mode MODE onto the stack.
1218 The main use of this function is as a predicate in match_operand
1219 expressions in the machine description. */
1222 push_operand (rtx op
, enum machine_mode mode
)
1224 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1226 #ifdef PUSH_ROUNDING
1227 rounded_size
= PUSH_ROUNDING (rounded_size
);
1233 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1238 if (rounded_size
== GET_MODE_SIZE (mode
))
1240 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1245 if (GET_CODE (op
) != PRE_MODIFY
1246 || GET_CODE (XEXP (op
, 1)) != PLUS
1247 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1248 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1249 #ifdef STACK_GROWS_DOWNWARD
1250 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1252 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1258 return XEXP (op
, 0) == stack_pointer_rtx
;
1261 /* Return 1 if OP is a valid operand that stands for popping a
1262 value of mode MODE off the stack.
1264 The main use of this function is as a predicate in match_operand
1265 expressions in the machine description. */
1268 pop_operand (rtx op
, enum machine_mode mode
)
1273 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1278 if (GET_CODE (op
) != STACK_POP_CODE
)
1281 return XEXP (op
, 0) == stack_pointer_rtx
;
1284 /* Return 1 if ADDR is a valid memory address
1285 for mode MODE in address space AS. */
1288 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1289 rtx addr
, addr_space_t as
)
1291 #ifdef GO_IF_LEGITIMATE_ADDRESS
1292 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1293 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1299 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1303 /* Return 1 if OP is a valid memory reference with mode MODE,
1304 including a valid address.
1306 The main use of this function is as a predicate in match_operand
1307 expressions in the machine description. */
1310 memory_operand (rtx op
, enum machine_mode mode
)
1314 if (! reload_completed
)
1315 /* Note that no SUBREG is a memory operand before end of reload pass,
1316 because (SUBREG (MEM...)) forces reloading into a register. */
1317 return MEM_P (op
) && general_operand (op
, mode
);
1319 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1323 if (GET_CODE (inner
) == SUBREG
)
1324 inner
= SUBREG_REG (inner
);
1326 return (MEM_P (inner
) && general_operand (op
, mode
));
1329 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1330 that is, a memory reference whose address is a general_operand. */
1333 indirect_operand (rtx op
, enum machine_mode mode
)
1335 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1336 if (! reload_completed
1337 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1339 int offset
= SUBREG_BYTE (op
);
1340 rtx inner
= SUBREG_REG (op
);
1342 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1345 /* The only way that we can have a general_operand as the resulting
1346 address is if OFFSET is zero and the address already is an operand
1347 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1350 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1351 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1352 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1353 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1354 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1358 && memory_operand (op
, mode
)
1359 && general_operand (XEXP (op
, 0), Pmode
));
1362 /* Return 1 if this is an ordered comparison operator (not including
1363 ORDERED and UNORDERED). */
1366 ordered_comparison_operator (rtx op
, enum machine_mode mode
)
1368 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1370 switch (GET_CODE (op
))
1388 /* Return 1 if this is a comparison operator. This allows the use of
1389 MATCH_OPERATOR to recognize all the branch insns. */
1392 comparison_operator (rtx op
, enum machine_mode mode
)
1394 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1395 && COMPARISON_P (op
));
1398 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1401 extract_asm_operands (rtx body
)
1404 switch (GET_CODE (body
))
1410 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1411 tmp
= SET_SRC (body
);
1412 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1417 tmp
= XVECEXP (body
, 0, 0);
1418 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1420 if (GET_CODE (tmp
) == SET
)
1422 tmp
= SET_SRC (tmp
);
1423 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1434 /* If BODY is an insn body that uses ASM_OPERANDS,
1435 return the number of operands (both input and output) in the insn.
1436 Otherwise return -1. */
1439 asm_noperands (const_rtx body
)
1441 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1447 if (GET_CODE (body
) == SET
)
1449 else if (GET_CODE (body
) == PARALLEL
)
1452 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1454 /* Multiple output operands, or 1 output plus some clobbers:
1456 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1457 /* Count backwards through CLOBBERs to determine number of SETs. */
1458 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1460 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1462 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1466 /* N_SETS is now number of output operands. */
1469 /* Verify that all the SETs we have
1470 came from a single original asm_operands insn
1471 (so that invalid combinations are blocked). */
1472 for (i
= 0; i
< n_sets
; i
++)
1474 rtx elt
= XVECEXP (body
, 0, i
);
1475 if (GET_CODE (elt
) != SET
)
1477 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1479 /* If these ASM_OPERANDS rtx's came from different original insns
1480 then they aren't allowed together. */
1481 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1482 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1488 /* 0 outputs, but some clobbers:
1489 body is [(asm_operands ...) (clobber (reg ...))...]. */
1490 /* Make sure all the other parallel things really are clobbers. */
1491 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1492 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1497 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1498 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1501 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1502 copy its operands (both input and output) into the vector OPERANDS,
1503 the locations of the operands within the insn into the vector OPERAND_LOCS,
1504 and the constraints for the operands into CONSTRAINTS.
1505 Write the modes of the operands into MODES.
1506 Return the assembler-template.
1508 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1509 we don't store that info. */
1512 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1513 const char **constraints
, enum machine_mode
*modes
,
1516 int nbase
= 0, n
, i
;
1519 switch (GET_CODE (body
))
1522 /* Zero output asm: BODY is (asm_operands ...). */
1527 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1528 asmop
= SET_SRC (body
);
1530 /* The output is in the SET.
1531 Its constraint is in the ASM_OPERANDS itself. */
1533 operands
[0] = SET_DEST (body
);
1535 operand_locs
[0] = &SET_DEST (body
);
1537 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1539 modes
[0] = GET_MODE (SET_DEST (body
));
1545 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1547 asmop
= XVECEXP (body
, 0, 0);
1548 if (GET_CODE (asmop
) == SET
)
1550 asmop
= SET_SRC (asmop
);
1552 /* At least one output, plus some CLOBBERs. The outputs are in
1553 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1554 for (i
= 0; i
< nparallel
; i
++)
1556 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1557 break; /* Past last SET */
1559 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1561 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1563 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1565 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1576 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1577 for (i
= 0; i
< n
; i
++)
1580 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1582 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1584 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1586 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1590 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1591 for (i
= 0; i
< n
; i
++)
1594 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1596 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1598 constraints
[nbase
+ i
] = "";
1600 modes
[nbase
+ i
] = Pmode
;
1604 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1606 return ASM_OPERANDS_TEMPLATE (asmop
);
1609 /* Check if an asm_operand matches its constraints.
1610 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1613 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1617 bool incdec_ok
= false;
1620 /* Use constrain_operands after reload. */
1621 gcc_assert (!reload_completed
);
1623 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1624 many alternatives as required to match the other operands. */
1625 if (*constraint
== '\0')
1630 char c
= *constraint
;
1647 case '0': case '1': case '2': case '3': case '4':
1648 case '5': case '6': case '7': case '8': case '9':
1649 /* If caller provided constraints pointer, look up
1650 the maching constraint. Otherwise, our caller should have
1651 given us the proper matching constraint, but we can't
1652 actually fail the check if they didn't. Indicate that
1653 results are inconclusive. */
1657 unsigned long match
;
1659 match
= strtoul (constraint
, &end
, 10);
1661 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1662 constraint
= (const char *) end
;
1668 while (ISDIGIT (*constraint
));
1675 if (address_operand (op
, VOIDmode
))
1679 case TARGET_MEM_CONSTRAINT
:
1680 case 'V': /* non-offsettable */
1681 if (memory_operand (op
, VOIDmode
))
1685 case 'o': /* offsettable */
1686 if (offsettable_nonstrict_memref_p (op
))
1691 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1692 excepting those that expand_call created. Further, on some
1693 machines which do not have generalized auto inc/dec, an inc/dec
1694 is not a memory_operand.
1696 Match any memory and hope things are resolved after reload. */
1700 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1701 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1711 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1712 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1721 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1722 || (GET_CODE (op
) == CONST_VECTOR
1723 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1728 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1729 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1733 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1734 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1739 if (CONST_SCALAR_INT_P (op
))
1744 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1749 if (CONST_SCALAR_INT_P (op
))
1754 if (CONST_INT_P (op
)
1755 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1759 if (CONST_INT_P (op
)
1760 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1764 if (CONST_INT_P (op
)
1765 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1769 if (CONST_INT_P (op
)
1770 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1774 if (CONST_INT_P (op
)
1775 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1779 if (CONST_INT_P (op
)
1780 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1784 if (CONST_INT_P (op
)
1785 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1789 if (CONST_INT_P (op
)
1790 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1799 if (general_operand (op
, VOIDmode
))
1804 /* For all other letters, we first check for a register class,
1805 otherwise it is an EXTRA_CONSTRAINT. */
1806 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1809 if (GET_MODE (op
) == BLKmode
)
1811 if (register_operand (op
, VOIDmode
))
1814 #ifdef EXTRA_CONSTRAINT_STR
1815 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
))
1816 /* Every memory operand can be reloaded to fit. */
1817 result
= result
|| memory_operand (op
, VOIDmode
);
1818 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
))
1819 /* Every address operand can be reloaded to fit. */
1820 result
= result
|| address_operand (op
, VOIDmode
);
1821 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1826 len
= CONSTRAINT_LEN (c
, constraint
);
1829 while (--len
&& *constraint
);
1835 /* For operands without < or > constraints reject side-effects. */
1836 if (!incdec_ok
&& result
&& MEM_P (op
))
1837 switch (GET_CODE (XEXP (op
, 0)))
1854 /* Given an rtx *P, if it is a sum containing an integer constant term,
1855 return the location (type rtx *) of the pointer to that constant term.
1856 Otherwise, return a null pointer. */
1859 find_constant_term_loc (rtx
*p
)
1862 enum rtx_code code
= GET_CODE (*p
);
1864 /* If *P IS such a constant term, P is its location. */
1866 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1870 /* Otherwise, if not a sum, it has no constant term. */
1872 if (GET_CODE (*p
) != PLUS
)
1875 /* If one of the summands is constant, return its location. */
1877 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1878 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1881 /* Otherwise, check each summand for containing a constant term. */
1883 if (XEXP (*p
, 0) != 0)
1885 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1890 if (XEXP (*p
, 1) != 0)
1892 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1900 /* Return 1 if OP is a memory reference
1901 whose address contains no side effects
1902 and remains valid after the addition
1903 of a positive integer less than the
1904 size of the object being referenced.
1906 We assume that the original address is valid and do not check it.
1908 This uses strict_memory_address_p as a subroutine, so
1909 don't use it before reload. */
1912 offsettable_memref_p (rtx op
)
1914 return ((MEM_P (op
))
1915 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1916 MEM_ADDR_SPACE (op
)));
1919 /* Similar, but don't require a strictly valid mem ref:
1920 consider pseudo-regs valid as index or base regs. */
1923 offsettable_nonstrict_memref_p (rtx op
)
1925 return ((MEM_P (op
))
1926 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1927 MEM_ADDR_SPACE (op
)));
1930 /* Return 1 if Y is a memory address which contains no side effects
1931 and would remain valid for address space AS after the addition of
1932 a positive integer less than the size of that mode.
1934 We assume that the original address is valid and do not check it.
1935 We do check that it is valid for narrower modes.
1937 If STRICTP is nonzero, we require a strictly valid address,
1938 for the sake of use in reload.c. */
1941 offsettable_address_addr_space_p (int strictp
, enum machine_mode mode
, rtx y
,
1944 enum rtx_code ycode
= GET_CODE (y
);
1948 int (*addressp
) (enum machine_mode
, rtx
, addr_space_t
) =
1949 (strictp
? strict_memory_address_addr_space_p
1950 : memory_address_addr_space_p
);
1951 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1953 if (CONSTANT_ADDRESS_P (y
))
1956 /* Adjusting an offsettable address involves changing to a narrower mode.
1957 Make sure that's OK. */
1959 if (mode_dependent_address_p (y
, as
))
1962 enum machine_mode address_mode
= GET_MODE (y
);
1963 if (address_mode
== VOIDmode
)
1964 address_mode
= targetm
.addr_space
.address_mode (as
);
1965 #ifdef POINTERS_EXTEND_UNSIGNED
1966 enum machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
1969 /* ??? How much offset does an offsettable BLKmode reference need?
1970 Clearly that depends on the situation in which it's being used.
1971 However, the current situation in which we test 0xffffffff is
1972 less than ideal. Caveat user. */
1974 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1976 /* If the expression contains a constant term,
1977 see if it remains valid when max possible offset is added. */
1979 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1984 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
1985 /* Use QImode because an odd displacement may be automatically invalid
1986 for any wider mode. But it should be valid for a single byte. */
1987 good
= (*addressp
) (QImode
, y
, as
);
1989 /* In any case, restore old contents of memory. */
1994 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
1997 /* The offset added here is chosen as the maximum offset that
1998 any instruction could need to add when operating on something
1999 of the specified mode. We assume that if Y and Y+c are
2000 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2001 go inside a LO_SUM here, so we do so as well. */
2002 if (GET_CODE (y
) == LO_SUM
2004 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
2005 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
2006 plus_constant (address_mode
, XEXP (y
, 1),
2008 #ifdef POINTERS_EXTEND_UNSIGNED
2009 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2010 else if (POINTERS_EXTEND_UNSIGNED
> 0
2011 && GET_CODE (y
) == ZERO_EXTEND
2012 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2013 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2014 plus_constant (pointer_mode
, XEXP (y
, 0),
2018 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2020 /* Use QImode because an odd displacement may be automatically invalid
2021 for any wider mode. But it should be valid for a single byte. */
2022 return (*addressp
) (QImode
, z
, as
);
2025 /* Return 1 if ADDR is an address-expression whose effect depends
2026 on the mode of the memory reference it is used in.
2028 ADDRSPACE is the address space associated with the address.
2030 Autoincrement addressing is a typical example of mode-dependence
2031 because the amount of the increment depends on the mode. */
2034 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2036 /* Auto-increment addressing with anything other than post_modify
2037 or pre_modify always introduces a mode dependency. Catch such
2038 cases now instead of deferring to the target. */
2039 if (GET_CODE (addr
) == PRE_INC
2040 || GET_CODE (addr
) == POST_INC
2041 || GET_CODE (addr
) == PRE_DEC
2042 || GET_CODE (addr
) == POST_DEC
)
2045 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2048 /* Like extract_insn, but save insn extracted and don't extract again, when
2049 called again for the same insn expecting that recog_data still contain the
2050 valid information. This is used primary by gen_attr infrastructure that
2051 often does extract insn again and again. */
2053 extract_insn_cached (rtx insn
)
2055 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2057 extract_insn (insn
);
2058 recog_data
.insn
= insn
;
2061 /* Do cached extract_insn, constrain_operands and complain about failures.
2062 Used by insn_attrtab. */
2064 extract_constrain_insn_cached (rtx insn
)
2066 extract_insn_cached (insn
);
2067 if (which_alternative
== -1
2068 && !constrain_operands (reload_completed
))
2069 fatal_insn_not_found (insn
);
2072 /* Do cached constrain_operands and complain about failures. */
2074 constrain_operands_cached (int strict
)
2076 if (which_alternative
== -1)
2077 return constrain_operands (strict
);
2082 /* Analyze INSN and fill in recog_data. */
2085 extract_insn (rtx insn
)
2090 rtx body
= PATTERN (insn
);
2092 recog_data
.n_operands
= 0;
2093 recog_data
.n_alternatives
= 0;
2094 recog_data
.n_dups
= 0;
2095 recog_data
.is_asm
= false;
2097 switch (GET_CODE (body
))
2108 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2113 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2114 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2115 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2121 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2124 /* This insn is an `asm' with operands. */
2126 /* expand_asm_operands makes sure there aren't too many operands. */
2127 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2129 /* Now get the operand values and constraints out of the insn. */
2130 decode_asm_operands (body
, recog_data
.operand
,
2131 recog_data
.operand_loc
,
2132 recog_data
.constraints
,
2133 recog_data
.operand_mode
, NULL
);
2134 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2137 const char *p
= recog_data
.constraints
[0];
2138 recog_data
.n_alternatives
= 1;
2140 recog_data
.n_alternatives
+= (*p
++ == ',');
2142 recog_data
.is_asm
= true;
2145 fatal_insn_not_found (insn
);
2149 /* Ordinary insn: recognize it, get the operands via insn_extract
2150 and get the constraints. */
2152 icode
= recog_memoized (insn
);
2154 fatal_insn_not_found (insn
);
2156 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2157 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2158 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2160 insn_extract (insn
);
2162 for (i
= 0; i
< noperands
; i
++)
2164 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2165 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2166 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2167 /* VOIDmode match_operands gets mode from their real operand. */
2168 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2169 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2172 for (i
= 0; i
< noperands
; i
++)
2173 recog_data
.operand_type
[i
]
2174 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2175 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2178 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2180 if (INSN_CODE (insn
) < 0)
2181 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2182 recog_data
.alternative_enabled_p
[i
] = true;
2185 recog_data
.insn
= insn
;
2186 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2188 which_alternative
= i
;
2189 recog_data
.alternative_enabled_p
[i
]
2190 = HAVE_ATTR_enabled
? get_attr_enabled (insn
) : 1;
2194 recog_data
.insn
= NULL
;
2195 which_alternative
= -1;
2198 /* After calling extract_insn, you can use this function to extract some
2199 information from the constraint strings into a more usable form.
2200 The collected data is stored in recog_op_alt. */
2202 preprocess_constraints (void)
2206 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2207 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2208 * sizeof (struct operand_alternative
)));
2210 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2213 struct operand_alternative
*op_alt
;
2214 const char *p
= recog_data
.constraints
[i
];
2216 op_alt
= recog_op_alt
[i
];
2218 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2220 op_alt
[j
].cl
= NO_REGS
;
2221 op_alt
[j
].constraint
= p
;
2222 op_alt
[j
].matches
= -1;
2223 op_alt
[j
].matched
= -1;
2225 if (!recog_data
.alternative_enabled_p
[j
])
2227 p
= skip_alternative (p
);
2231 if (*p
== '\0' || *p
== ',')
2233 op_alt
[j
].anything_ok
= 1;
2243 while (c
!= ',' && c
!= '\0');
2244 if (c
== ',' || c
== '\0')
2252 case '=': case '+': case '*': case '%':
2253 case 'E': case 'F': case 'G': case 'H':
2254 case 's': case 'i': case 'n':
2255 case 'I': case 'J': case 'K': case 'L':
2256 case 'M': case 'N': case 'O': case 'P':
2257 /* These don't say anything we care about. */
2261 op_alt
[j
].reject
+= 6;
2264 op_alt
[j
].reject
+= 600;
2267 op_alt
[j
].earlyclobber
= 1;
2270 case '0': case '1': case '2': case '3': case '4':
2271 case '5': case '6': case '7': case '8': case '9':
2274 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2275 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2280 case TARGET_MEM_CONSTRAINT
:
2281 op_alt
[j
].memory_ok
= 1;
2284 op_alt
[j
].decmem_ok
= 1;
2287 op_alt
[j
].incmem_ok
= 1;
2290 op_alt
[j
].nonoffmem_ok
= 1;
2293 op_alt
[j
].offmem_ok
= 1;
2296 op_alt
[j
].anything_ok
= 1;
2300 op_alt
[j
].is_address
= 1;
2301 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2302 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2309 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2313 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2315 op_alt
[j
].memory_ok
= 1;
2318 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2320 op_alt
[j
].is_address
= 1;
2322 = (reg_class_subunion
2323 [(int) op_alt
[j
].cl
]
2324 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2325 ADDRESS
, SCRATCH
)]);
2330 = (reg_class_subunion
2331 [(int) op_alt
[j
].cl
]
2332 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2335 p
+= CONSTRAINT_LEN (c
, p
);
2341 /* Check the operands of an insn against the insn's operand constraints
2342 and return 1 if they are valid.
2343 The information about the insn's operands, constraints, operand modes
2344 etc. is obtained from the global variables set up by extract_insn.
2346 WHICH_ALTERNATIVE is set to a number which indicates which
2347 alternative of constraints was matched: 0 for the first alternative,
2348 1 for the next, etc.
2350 In addition, when two operands are required to match
2351 and it happens that the output operand is (reg) while the
2352 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2353 make the output operand look like the input.
2354 This is because the output operand is the one the template will print.
2356 This is used in final, just before printing the assembler code and by
2357 the routines that determine an insn's attribute.
2359 If STRICT is a positive nonzero value, it means that we have been
2360 called after reload has been completed. In that case, we must
2361 do all checks strictly. If it is zero, it means that we have been called
2362 before reload has completed. In that case, we first try to see if we can
2363 find an alternative that matches strictly. If not, we try again, this
2364 time assuming that reload will fix up the insn. This provides a "best
2365 guess" for the alternative and is used to compute attributes of insns prior
2366 to reload. A negative value of STRICT is used for this internal call. */
2374 constrain_operands (int strict
)
2376 const char *constraints
[MAX_RECOG_OPERANDS
];
2377 int matching_operands
[MAX_RECOG_OPERANDS
];
2378 int earlyclobber
[MAX_RECOG_OPERANDS
];
2381 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2382 int funny_match_index
;
2384 which_alternative
= 0;
2385 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2388 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2390 constraints
[c
] = recog_data
.constraints
[c
];
2391 matching_operands
[c
] = -1;
2396 int seen_earlyclobber_at
= -1;
2399 funny_match_index
= 0;
2401 if (!recog_data
.alternative_enabled_p
[which_alternative
])
2405 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2406 constraints
[i
] = skip_alternative (constraints
[i
]);
2408 which_alternative
++;
2412 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2414 rtx op
= recog_data
.operand
[opno
];
2415 enum machine_mode mode
= GET_MODE (op
);
2416 const char *p
= constraints
[opno
];
2422 earlyclobber
[opno
] = 0;
2424 /* A unary operator may be accepted by the predicate, but it
2425 is irrelevant for matching constraints. */
2429 if (GET_CODE (op
) == SUBREG
)
2431 if (REG_P (SUBREG_REG (op
))
2432 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2433 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2434 GET_MODE (SUBREG_REG (op
)),
2437 op
= SUBREG_REG (op
);
2440 /* An empty constraint or empty alternative
2441 allows anything which matched the pattern. */
2442 if (*p
== 0 || *p
== ',')
2446 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2455 case '?': case '!': case '*': case '%':
2460 /* Ignore rest of this alternative as far as
2461 constraint checking is concerned. */
2464 while (*p
&& *p
!= ',');
2469 earlyclobber
[opno
] = 1;
2470 if (seen_earlyclobber_at
< 0)
2471 seen_earlyclobber_at
= opno
;
2474 case '0': case '1': case '2': case '3': case '4':
2475 case '5': case '6': case '7': case '8': case '9':
2477 /* This operand must be the same as a previous one.
2478 This kind of constraint is used for instructions such
2479 as add when they take only two operands.
2481 Note that the lower-numbered operand is passed first.
2483 If we are not testing strictly, assume that this
2484 constraint will be satisfied. */
2489 match
= strtoul (p
, &end
, 10);
2496 rtx op1
= recog_data
.operand
[match
];
2497 rtx op2
= recog_data
.operand
[opno
];
2499 /* A unary operator may be accepted by the predicate,
2500 but it is irrelevant for matching constraints. */
2502 op1
= XEXP (op1
, 0);
2504 op2
= XEXP (op2
, 0);
2506 val
= operands_match_p (op1
, op2
);
2509 matching_operands
[opno
] = match
;
2510 matching_operands
[match
] = opno
;
2515 /* If output is *x and input is *--x, arrange later
2516 to change the output to *--x as well, since the
2517 output op is the one that will be printed. */
2518 if (val
== 2 && strict
> 0)
2520 funny_match
[funny_match_index
].this_op
= opno
;
2521 funny_match
[funny_match_index
++].other
= match
;
2528 /* p is used for address_operands. When we are called by
2529 gen_reload, no one will have checked that the address is
2530 strictly valid, i.e., that all pseudos requiring hard regs
2531 have gotten them. */
2533 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2538 /* No need to check general_operand again;
2539 it was done in insn-recog.c. Well, except that reload
2540 doesn't check the validity of its replacements, but
2541 that should only matter when there's a bug. */
2543 /* Anything goes unless it is a REG and really has a hard reg
2544 but the hard reg is not in the class GENERAL_REGS. */
2548 || GENERAL_REGS
== ALL_REGS
2549 || (reload_in_progress
2550 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2551 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2554 else if (strict
< 0 || general_operand (op
, mode
))
2559 /* This is used for a MATCH_SCRATCH in the cases when
2560 we don't actually need anything. So anything goes
2565 case TARGET_MEM_CONSTRAINT
:
2566 /* Memory operands must be valid, to the extent
2567 required by STRICT. */
2571 && !strict_memory_address_addr_space_p
2572 (GET_MODE (op
), XEXP (op
, 0),
2573 MEM_ADDR_SPACE (op
)))
2576 && !memory_address_addr_space_p
2577 (GET_MODE (op
), XEXP (op
, 0),
2578 MEM_ADDR_SPACE (op
)))
2582 /* Before reload, accept what reload can turn into mem. */
2583 else if (strict
< 0 && CONSTANT_P (op
))
2585 /* During reload, accept a pseudo */
2586 else if (reload_in_progress
&& REG_P (op
)
2587 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2593 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2594 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2600 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2601 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2607 if (CONST_DOUBLE_AS_FLOAT_P (op
)
2608 || (GET_CODE (op
) == CONST_VECTOR
2609 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2615 if (CONST_DOUBLE_AS_FLOAT_P (op
)
2616 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2621 if (CONST_SCALAR_INT_P (op
))
2624 if (CONSTANT_P (op
))
2629 if (CONST_SCALAR_INT_P (op
))
2641 if (CONST_INT_P (op
)
2642 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2648 && ((strict
> 0 && ! offsettable_memref_p (op
))
2650 && !(CONSTANT_P (op
) || MEM_P (op
)))
2651 || (reload_in_progress
2653 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2658 if ((strict
> 0 && offsettable_memref_p (op
))
2659 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2660 /* Before reload, accept what reload can handle. */
2662 && (CONSTANT_P (op
) || MEM_P (op
)))
2663 /* During reload, accept a pseudo */
2664 || (reload_in_progress
&& REG_P (op
)
2665 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2674 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2680 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2681 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2683 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2686 #ifdef EXTRA_CONSTRAINT_STR
2687 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2690 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2691 /* Every memory operand can be reloaded to fit. */
2692 && ((strict
< 0 && MEM_P (op
))
2693 /* Before reload, accept what reload can turn
2695 || (strict
< 0 && CONSTANT_P (op
))
2696 /* During reload, accept a pseudo */
2697 || (reload_in_progress
&& REG_P (op
)
2698 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2700 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2701 /* Every address operand can be reloaded to fit. */
2704 /* Cater to architectures like IA-64 that define extra memory
2705 constraints without using define_memory_constraint. */
2706 else if (reload_in_progress
2708 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2709 && reg_renumber
[REGNO (op
)] < 0
2710 && reg_equiv_mem (REGNO (op
)) != 0
2711 && EXTRA_CONSTRAINT_STR
2712 (reg_equiv_mem (REGNO (op
)), c
, p
))
2718 while (p
+= len
, c
);
2720 constraints
[opno
] = p
;
2721 /* If this operand did not win somehow,
2722 this alternative loses. */
2726 /* This alternative won; the operands are ok.
2727 Change whichever operands this alternative says to change. */
2732 /* See if any earlyclobber operand conflicts with some other
2735 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2736 for (eopno
= seen_earlyclobber_at
;
2737 eopno
< recog_data
.n_operands
;
2739 /* Ignore earlyclobber operands now in memory,
2740 because we would often report failure when we have
2741 two memory operands, one of which was formerly a REG. */
2742 if (earlyclobber
[eopno
]
2743 && REG_P (recog_data
.operand
[eopno
]))
2744 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2745 if ((MEM_P (recog_data
.operand
[opno
])
2746 || recog_data
.operand_type
[opno
] != OP_OUT
)
2748 /* Ignore things like match_operator operands. */
2749 && *recog_data
.constraints
[opno
] != 0
2750 && ! (matching_operands
[opno
] == eopno
2751 && operands_match_p (recog_data
.operand
[opno
],
2752 recog_data
.operand
[eopno
]))
2753 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2754 recog_data
.operand
[eopno
]))
2759 while (--funny_match_index
>= 0)
2761 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2762 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2766 /* For operands without < or > constraints reject side-effects. */
2767 if (recog_data
.is_asm
)
2769 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2770 if (MEM_P (recog_data
.operand
[opno
]))
2771 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2779 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2780 && strchr (recog_data
.constraints
[opno
], '>')
2793 which_alternative
++;
2795 while (which_alternative
< recog_data
.n_alternatives
);
2797 which_alternative
= -1;
2798 /* If we are about to reject this, but we are not to test strictly,
2799 try a very loose test. Only return failure if it fails also. */
2801 return constrain_operands (-1);
2806 /* Return true iff OPERAND (assumed to be a REG rtx)
2807 is a hard reg in class CLASS when its regno is offset by OFFSET
2808 and changed to mode MODE.
2809 If REG occupies multiple hard regs, all of them must be in CLASS. */
2812 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2813 enum machine_mode mode
)
2815 unsigned int regno
= REGNO (operand
);
2820 /* Regno must not be a pseudo register. Offset may be negative. */
2821 return (HARD_REGISTER_NUM_P (regno
)
2822 && HARD_REGISTER_NUM_P (regno
+ offset
)
2823 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2827 /* Split single instruction. Helper function for split_all_insns and
2828 split_all_insns_noflow. Return last insn in the sequence if successful,
2829 or NULL if unsuccessful. */
2832 split_insn (rtx insn
)
2834 /* Split insns here to get max fine-grain parallelism. */
2835 rtx first
= PREV_INSN (insn
);
2836 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2837 rtx insn_set
, last_set
, note
;
2842 /* If the original instruction was a single set that was known to be
2843 equivalent to a constant, see if we can say the same about the last
2844 instruction in the split sequence. The two instructions must set
2845 the same destination. */
2846 insn_set
= single_set (insn
);
2849 last_set
= single_set (last
);
2850 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2852 note
= find_reg_equal_equiv_note (insn
);
2853 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2854 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2855 else if (CONSTANT_P (SET_SRC (insn_set
)))
2856 set_unique_reg_note (last
, REG_EQUAL
,
2857 copy_rtx (SET_SRC (insn_set
)));
2861 /* try_split returns the NOTE that INSN became. */
2862 SET_INSN_DELETED (insn
);
2864 /* ??? Coddle to md files that generate subregs in post-reload
2865 splitters instead of computing the proper hard register. */
2866 if (reload_completed
&& first
!= last
)
2868 first
= NEXT_INSN (first
);
2872 cleanup_subreg_operands (first
);
2875 first
= NEXT_INSN (first
);
2882 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2885 split_all_insns (void)
2891 blocks
= sbitmap_alloc (last_basic_block
);
2892 bitmap_clear (blocks
);
2895 FOR_EACH_BB_REVERSE (bb
)
2898 bool finish
= false;
2900 rtl_profile_for_bb (bb
);
2901 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2903 /* Can't use `next_real_insn' because that might go across
2904 CODE_LABELS and short-out basic blocks. */
2905 next
= NEXT_INSN (insn
);
2906 finish
= (insn
== BB_END (bb
));
2909 rtx set
= single_set (insn
);
2911 /* Don't split no-op move insns. These should silently
2912 disappear later in final. Splitting such insns would
2913 break the code that handles LIBCALL blocks. */
2914 if (set
&& set_noop_p (set
))
2916 /* Nops get in the way while scheduling, so delete them
2917 now if register allocation has already been done. It
2918 is too risky to try to do this before register
2919 allocation, and there are unlikely to be very many
2920 nops then anyways. */
2921 if (reload_completed
)
2922 delete_insn_and_edges (insn
);
2926 if (split_insn (insn
))
2928 bitmap_set_bit (blocks
, bb
->index
);
2936 default_rtl_profile ();
2938 find_many_sub_basic_blocks (blocks
);
2940 #ifdef ENABLE_CHECKING
2941 verify_flow_info ();
2944 sbitmap_free (blocks
);
2947 /* Same as split_all_insns, but do not expect CFG to be available.
2948 Used by machine dependent reorg passes. */
2951 split_all_insns_noflow (void)
2955 for (insn
= get_insns (); insn
; insn
= next
)
2957 next
= NEXT_INSN (insn
);
2960 /* Don't split no-op move insns. These should silently
2961 disappear later in final. Splitting such insns would
2962 break the code that handles LIBCALL blocks. */
2963 rtx set
= single_set (insn
);
2964 if (set
&& set_noop_p (set
))
2966 /* Nops get in the way while scheduling, so delete them
2967 now if register allocation has already been done. It
2968 is too risky to try to do this before register
2969 allocation, and there are unlikely to be very many
2972 ??? Should we use delete_insn when the CFG isn't valid? */
2973 if (reload_completed
)
2974 delete_insn_and_edges (insn
);
2983 #ifdef HAVE_peephole2
2984 struct peep2_insn_data
2990 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2991 static int peep2_current
;
2993 static bool peep2_do_rebuild_jump_labels
;
2994 static bool peep2_do_cleanup_cfg
;
2996 /* The number of instructions available to match a peep2. */
2997 int peep2_current_count
;
2999 /* A non-insn marker indicating the last insn of the block.
3000 The live_before regset for this element is correct, indicating
3001 DF_LIVE_OUT for the block. */
3002 #define PEEP2_EOB pc_rtx
3004 /* Wrap N to fit into the peep2_insn_data buffer. */
3007 peep2_buf_position (int n
)
3009 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3010 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3014 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3015 does not exist. Used by the recognizer to find the next insn to match
3016 in a multi-insn pattern. */
3019 peep2_next_insn (int n
)
3021 gcc_assert (n
<= peep2_current_count
);
3023 n
= peep2_buf_position (peep2_current
+ n
);
3025 return peep2_insn_data
[n
].insn
;
3028 /* Return true if REGNO is dead before the Nth non-note insn
3032 peep2_regno_dead_p (int ofs
, int regno
)
3034 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3036 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3038 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3040 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3043 /* Similarly for a REG. */
3046 peep2_reg_dead_p (int ofs
, rtx reg
)
3050 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3052 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3054 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3056 regno
= REGNO (reg
);
3057 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3059 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3064 /* Regno offset to be used in the register search. */
3065 static int search_ofs
;
3067 /* Try to find a hard register of mode MODE, matching the register class in
3068 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3069 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3070 in which case the only condition is that the register must be available
3071 before CURRENT_INSN.
3072 Registers that already have bits set in REG_SET will not be considered.
3074 If an appropriate register is available, it will be returned and the
3075 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3079 peep2_find_free_register (int from
, int to
, const char *class_str
,
3080 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
3087 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3088 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3090 from
= peep2_buf_position (peep2_current
+ from
);
3091 to
= peep2_buf_position (peep2_current
+ to
);
3093 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3094 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3098 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3100 /* Don't use registers set or clobbered by the insn. */
3101 for (def_rec
= DF_INSN_DEFS (peep2_insn_data
[from
].insn
);
3102 *def_rec
; def_rec
++)
3103 SET_HARD_REG_BIT (live
, DF_REF_REGNO (*def_rec
));
3105 from
= peep2_buf_position (from
+ 1);
3108 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
3109 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
3111 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3113 int raw_regno
, regno
, success
, j
;
3115 /* Distribute the free registers as much as possible. */
3116 raw_regno
= search_ofs
+ i
;
3117 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3118 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3119 #ifdef REG_ALLOC_ORDER
3120 regno
= reg_alloc_order
[raw_regno
];
3125 /* Can it support the mode we need? */
3126 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3130 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3132 /* Don't allocate fixed registers. */
3133 if (fixed_regs
[regno
+ j
])
3138 /* Don't allocate global registers. */
3139 if (global_regs
[regno
+ j
])
3144 /* Make sure the register is of the right class. */
3145 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3150 /* And that we don't create an extra save/restore. */
3151 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3157 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3163 /* And we don't clobber traceback for noreturn functions. */
3164 if ((regno
+ j
== FRAME_POINTER_REGNUM
3165 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3166 && (! reload_completed
|| frame_pointer_needed
))
3172 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3173 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3182 add_to_hard_reg_set (reg_set
, mode
, regno
);
3184 /* Start the next search with the next register. */
3185 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3187 search_ofs
= raw_regno
;
3189 return gen_rtx_REG (mode
, regno
);
3197 /* Forget all currently tracked instructions, only remember current
3201 peep2_reinit_state (regset live
)
3205 /* Indicate that all slots except the last holds invalid data. */
3206 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3207 peep2_insn_data
[i
].insn
= NULL_RTX
;
3208 peep2_current_count
= 0;
3210 /* Indicate that the last slot contains live_after data. */
3211 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3212 peep2_current
= MAX_INSNS_PER_PEEP2
;
3214 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3217 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3218 starting at INSN. Perform the replacement, removing the old insns and
3219 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3220 if the replacement is rejected. */
3223 peep2_attempt (basic_block bb
, rtx insn
, int match_len
, rtx attempt
)
3226 rtx last
, eh_note
, as_note
, before_try
, x
;
3227 rtx old_insn
, new_insn
;
3228 bool was_call
= false;
3230 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3231 match more than one insn, or to be split into more than one insn. */
3232 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3233 if (RTX_FRAME_RELATED_P (old_insn
))
3235 bool any_note
= false;
3241 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3242 may be in the stream for the purpose of register allocation. */
3243 if (active_insn_p (attempt
))
3246 new_insn
= next_active_insn (attempt
);
3247 if (next_active_insn (new_insn
))
3250 /* We have a 1-1 replacement. Copy over any frame-related info. */
3251 RTX_FRAME_RELATED_P (new_insn
) = 1;
3253 /* Allow the backend to fill in a note during the split. */
3254 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3255 switch (REG_NOTE_KIND (note
))
3257 case REG_FRAME_RELATED_EXPR
:
3258 case REG_CFA_DEF_CFA
:
3259 case REG_CFA_ADJUST_CFA
:
3260 case REG_CFA_OFFSET
:
3261 case REG_CFA_REGISTER
:
3262 case REG_CFA_EXPRESSION
:
3263 case REG_CFA_RESTORE
:
3264 case REG_CFA_SET_VDRAP
:
3271 /* If the backend didn't supply a note, copy one over. */
3273 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3274 switch (REG_NOTE_KIND (note
))
3276 case REG_FRAME_RELATED_EXPR
:
3277 case REG_CFA_DEF_CFA
:
3278 case REG_CFA_ADJUST_CFA
:
3279 case REG_CFA_OFFSET
:
3280 case REG_CFA_REGISTER
:
3281 case REG_CFA_EXPRESSION
:
3282 case REG_CFA_RESTORE
:
3283 case REG_CFA_SET_VDRAP
:
3284 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3291 /* If there still isn't a note, make sure the unwind info sees the
3292 same expression as before the split. */
3295 rtx old_set
, new_set
;
3297 /* The old insn had better have been simple, or annotated. */
3298 old_set
= single_set (old_insn
);
3299 gcc_assert (old_set
!= NULL
);
3301 new_set
= single_set (new_insn
);
3302 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3303 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3306 /* Copy prologue/epilogue status. This is required in order to keep
3307 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3308 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3311 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3312 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3313 cfg-related call notes. */
3314 for (i
= 0; i
<= match_len
; ++i
)
3319 j
= peep2_buf_position (peep2_current
+ i
);
3320 old_insn
= peep2_insn_data
[j
].insn
;
3321 if (!CALL_P (old_insn
))
3326 while (new_insn
!= NULL_RTX
)
3328 if (CALL_P (new_insn
))
3330 new_insn
= NEXT_INSN (new_insn
);
3333 gcc_assert (new_insn
!= NULL_RTX
);
3335 CALL_INSN_FUNCTION_USAGE (new_insn
)
3336 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3338 for (note
= REG_NOTES (old_insn
);
3340 note
= XEXP (note
, 1))
3341 switch (REG_NOTE_KIND (note
))
3346 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3350 /* Discard all other reg notes. */
3354 /* Croak if there is another call in the sequence. */
3355 while (++i
<= match_len
)
3357 j
= peep2_buf_position (peep2_current
+ i
);
3358 old_insn
= peep2_insn_data
[j
].insn
;
3359 gcc_assert (!CALL_P (old_insn
));
3364 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3365 move those notes over to the new sequence. */
3367 for (i
= match_len
; i
>= 0; --i
)
3369 int j
= peep2_buf_position (peep2_current
+ i
);
3370 old_insn
= peep2_insn_data
[j
].insn
;
3372 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3377 i
= peep2_buf_position (peep2_current
+ match_len
);
3378 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3380 /* Replace the old sequence with the new. */
3381 last
= emit_insn_after_setloc (attempt
,
3382 peep2_insn_data
[i
].insn
,
3383 INSN_LOCATION (peep2_insn_data
[i
].insn
));
3384 before_try
= PREV_INSN (insn
);
3385 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3387 /* Re-insert the EH_REGION notes. */
3388 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3393 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3394 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3398 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3401 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3402 if (x
!= BB_END (bb
)
3403 && (can_throw_internal (x
)
3404 || can_nonlocal_goto (x
)))
3409 nfte
= split_block (bb
, x
);
3410 flags
= (eh_edge
->flags
3411 & (EDGE_EH
| EDGE_ABNORMAL
));
3413 flags
|= EDGE_ABNORMAL_CALL
;
3414 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3417 nehe
->probability
= eh_edge
->probability
;
3419 = REG_BR_PROB_BASE
- nehe
->probability
;
3421 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3426 /* Converting possibly trapping insn to non-trapping is
3427 possible. Zap dummy outgoing edges. */
3428 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3431 /* Re-insert the ARGS_SIZE notes. */
3433 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3435 /* If we generated a jump instruction, it won't have
3436 JUMP_LABEL set. Recompute after we're done. */
3437 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3440 peep2_do_rebuild_jump_labels
= true;
3447 /* After performing a replacement in basic block BB, fix up the life
3448 information in our buffer. LAST is the last of the insns that we
3449 emitted as a replacement. PREV is the insn before the start of
3450 the replacement. MATCH_LEN is the number of instructions that were
3451 matched, and which now need to be replaced in the buffer. */
3454 peep2_update_life (basic_block bb
, int match_len
, rtx last
, rtx prev
)
3456 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3460 INIT_REG_SET (&live
);
3461 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3463 gcc_assert (peep2_current_count
>= match_len
+ 1);
3464 peep2_current_count
-= match_len
+ 1;
3472 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3474 peep2_current_count
++;
3476 i
= MAX_INSNS_PER_PEEP2
;
3477 peep2_insn_data
[i
].insn
= x
;
3478 df_simulate_one_insn_backwards (bb
, x
, &live
);
3479 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3485 CLEAR_REG_SET (&live
);
3490 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3491 Return true if we added it, false otherwise. The caller will try to match
3492 peepholes against the buffer if we return false; otherwise it will try to
3493 add more instructions to the buffer. */
3496 peep2_fill_buffer (basic_block bb
, rtx insn
, regset live
)
3500 /* Once we have filled the maximum number of insns the buffer can hold,
3501 allow the caller to match the insns against peepholes. We wait until
3502 the buffer is full in case the target has similar peepholes of different
3503 length; we always want to match the longest if possible. */
3504 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3507 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3508 any other pattern, lest it change the semantics of the frame info. */
3509 if (RTX_FRAME_RELATED_P (insn
))
3511 /* Let the buffer drain first. */
3512 if (peep2_current_count
> 0)
3514 /* Now the insn will be the only thing in the buffer. */
3517 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3518 peep2_insn_data
[pos
].insn
= insn
;
3519 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3520 peep2_current_count
++;
3522 df_simulate_one_insn_forwards (bb
, insn
, live
);
3526 /* Perform the peephole2 optimization pass. */
3529 peephole2_optimize (void)
3536 peep2_do_cleanup_cfg
= false;
3537 peep2_do_rebuild_jump_labels
= false;
3539 df_set_flags (DF_LR_RUN_DCE
);
3540 df_note_add_problem ();
3543 /* Initialize the regsets we're going to use. */
3544 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3545 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3547 live
= BITMAP_ALLOC (®_obstack
);
3549 FOR_EACH_BB_REVERSE (bb
)
3551 bool past_end
= false;
3554 rtl_profile_for_bb (bb
);
3556 /* Start up propagation. */
3557 bitmap_copy (live
, DF_LR_IN (bb
));
3558 df_simulate_initialize_forwards (bb
, live
);
3559 peep2_reinit_state (live
);
3561 insn
= BB_HEAD (bb
);
3567 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3570 insn
= NEXT_INSN (insn
);
3571 if (insn
== NEXT_INSN (BB_END (bb
)))
3575 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3578 /* If we did not fill an empty buffer, it signals the end of the
3580 if (peep2_current_count
== 0)
3583 /* The buffer filled to the current maximum, so try to match. */
3585 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3586 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3587 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3589 /* Match the peephole. */
3590 head
= peep2_insn_data
[peep2_current
].insn
;
3591 attempt
= peephole2_insns (PATTERN (head
), head
, &match_len
);
3592 if (attempt
!= NULL
)
3594 rtx last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3597 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3602 /* No match: advance the buffer by one insn. */
3603 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3604 peep2_current_count
--;
3608 default_rtl_profile ();
3609 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3610 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3612 if (peep2_do_rebuild_jump_labels
)
3613 rebuild_jump_labels (get_insns ());
3615 #endif /* HAVE_peephole2 */
3617 /* Common predicates for use with define_bypass. */
3619 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3620 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3621 must be either a single_set or a PARALLEL with SETs inside. */
3624 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3626 rtx out_set
, in_set
;
3627 rtx out_pat
, in_pat
;
3628 rtx out_exp
, in_exp
;
3631 in_set
= single_set (in_insn
);
3634 if (!MEM_P (SET_DEST (in_set
)))
3637 out_set
= single_set (out_insn
);
3640 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3645 out_pat
= PATTERN (out_insn
);
3647 if (GET_CODE (out_pat
) != PARALLEL
)
3650 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3652 out_exp
= XVECEXP (out_pat
, 0, i
);
3654 if (GET_CODE (out_exp
) == CLOBBER
)
3657 gcc_assert (GET_CODE (out_exp
) == SET
);
3659 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3666 in_pat
= PATTERN (in_insn
);
3667 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3669 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3671 in_exp
= XVECEXP (in_pat
, 0, i
);
3673 if (GET_CODE (in_exp
) == CLOBBER
)
3676 gcc_assert (GET_CODE (in_exp
) == SET
);
3678 if (!MEM_P (SET_DEST (in_exp
)))
3681 out_set
= single_set (out_insn
);
3684 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3689 out_pat
= PATTERN (out_insn
);
3690 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3692 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3694 out_exp
= XVECEXP (out_pat
, 0, j
);
3696 if (GET_CODE (out_exp
) == CLOBBER
)
3699 gcc_assert (GET_CODE (out_exp
) == SET
);
3701 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3711 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3712 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3713 or multiple set; IN_INSN should be single_set for truth, but for convenience
3714 of insn categorization may be any JUMP or CALL insn. */
3717 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3719 rtx out_set
, in_set
;
3721 in_set
= single_set (in_insn
);
3724 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3728 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3730 in_set
= SET_SRC (in_set
);
3732 out_set
= single_set (out_insn
);
3735 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3736 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3744 out_pat
= PATTERN (out_insn
);
3745 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3747 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3749 rtx exp
= XVECEXP (out_pat
, 0, i
);
3751 if (GET_CODE (exp
) == CLOBBER
)
3754 gcc_assert (GET_CODE (exp
) == SET
);
3756 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3757 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3766 gate_handle_peephole2 (void)
3768 return (optimize
> 0 && flag_peephole2
);
3772 rest_of_handle_peephole2 (void)
3774 #ifdef HAVE_peephole2
3775 peephole2_optimize ();
3780 struct rtl_opt_pass pass_peephole2
=
3784 "peephole2", /* name */
3785 OPTGROUP_NONE
, /* optinfo_flags */
3786 gate_handle_peephole2
, /* gate */
3787 rest_of_handle_peephole2
, /* execute */
3790 0, /* static_pass_number */
3791 TV_PEEPHOLE2
, /* tv_id */
3792 0, /* properties_required */
3793 0, /* properties_provided */
3794 0, /* properties_destroyed */
3795 0, /* todo_flags_start */
3796 TODO_df_finish
| TODO_verify_rtl_sharing
|
3797 0 /* todo_flags_finish */
3802 rest_of_handle_split_all_insns (void)
3808 struct rtl_opt_pass pass_split_all_insns
=
3812 "split1", /* name */
3813 OPTGROUP_NONE
, /* optinfo_flags */
3815 rest_of_handle_split_all_insns
, /* execute */
3818 0, /* static_pass_number */
3819 TV_NONE
, /* tv_id */
3820 0, /* properties_required */
3821 0, /* properties_provided */
3822 0, /* properties_destroyed */
3823 0, /* todo_flags_start */
3824 0 /* todo_flags_finish */
3829 rest_of_handle_split_after_reload (void)
3831 /* If optimizing, then go ahead and split insns now. */
3839 struct rtl_opt_pass pass_split_after_reload
=
3843 "split2", /* name */
3844 OPTGROUP_NONE
, /* optinfo_flags */
3846 rest_of_handle_split_after_reload
, /* execute */
3849 0, /* static_pass_number */
3850 TV_NONE
, /* tv_id */
3851 0, /* properties_required */
3852 0, /* properties_provided */
3853 0, /* properties_destroyed */
3854 0, /* todo_flags_start */
3855 0 /* todo_flags_finish */
3860 gate_handle_split_before_regstack (void)
3862 #if HAVE_ATTR_length && defined (STACK_REGS)
3863 /* If flow2 creates new instructions which need splitting
3864 and scheduling after reload is not done, they might not be
3865 split until final which doesn't allow splitting
3866 if HAVE_ATTR_length. */
3867 # ifdef INSN_SCHEDULING
3868 return (optimize
&& !flag_schedule_insns_after_reload
);
3878 rest_of_handle_split_before_regstack (void)
3884 struct rtl_opt_pass pass_split_before_regstack
=
3888 "split3", /* name */
3889 OPTGROUP_NONE
, /* optinfo_flags */
3890 gate_handle_split_before_regstack
, /* gate */
3891 rest_of_handle_split_before_regstack
, /* execute */
3894 0, /* static_pass_number */
3895 TV_NONE
, /* tv_id */
3896 0, /* properties_required */
3897 0, /* properties_provided */
3898 0, /* properties_destroyed */
3899 0, /* todo_flags_start */
3900 0 /* todo_flags_finish */
3905 gate_handle_split_before_sched2 (void)
3907 #ifdef INSN_SCHEDULING
3908 return optimize
> 0 && flag_schedule_insns_after_reload
;
3915 rest_of_handle_split_before_sched2 (void)
3917 #ifdef INSN_SCHEDULING
3923 struct rtl_opt_pass pass_split_before_sched2
=
3927 "split4", /* name */
3928 OPTGROUP_NONE
, /* optinfo_flags */
3929 gate_handle_split_before_sched2
, /* gate */
3930 rest_of_handle_split_before_sched2
, /* execute */
3933 0, /* static_pass_number */
3934 TV_NONE
, /* tv_id */
3935 0, /* properties_required */
3936 0, /* properties_provided */
3937 0, /* properties_destroyed */
3938 0, /* todo_flags_start */
3939 TODO_verify_flow
/* todo_flags_finish */
3943 /* The placement of the splitting that we do for shorten_branches
3944 depends on whether regstack is used by the target or not. */
3946 gate_do_final_split (void)
3948 #if HAVE_ATTR_length && !defined (STACK_REGS)
3955 struct rtl_opt_pass pass_split_for_shorten_branches
=
3959 "split5", /* name */
3960 OPTGROUP_NONE
, /* optinfo_flags */
3961 gate_do_final_split
, /* gate */
3962 split_all_insns_noflow
, /* execute */
3965 0, /* static_pass_number */
3966 TV_NONE
, /* tv_id */
3967 0, /* properties_required */
3968 0, /* properties_provided */
3969 0, /* properties_destroyed */
3970 0, /* todo_flags_start */
3971 TODO_verify_rtl_sharing
/* todo_flags_finish */