libjava/sysdep/pa/locks.h

   1 // locks.h - Thread synchronization primitives. PA-RISC implementation.
   2
   3 /* Copyright (C) 2002, 2005  Free Software Foundation
   4
   5    This file is part of libgcj.
   6
   7 This software is copyrighted work licensed under the terms of the
   8 Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
   9 details.  */
  10
  11 #ifndef __SYSDEP_LOCKS_H__
  12 #define __SYSDEP_LOCKS_H__
  13
  14 // Integer type big enough for object address.
  15 typedef size_t obj_addr_t;
  16
  17 template<int _Inst>
  18   struct _pa_jv_cas_lock
  19   {
  20     static volatile int _S_pa_jv_cas_lock;
  21   };
  22
  23 template<int _Inst>
  24 volatile int
  25 _pa_jv_cas_lock<_Inst>::_S_pa_jv_cas_lock __attribute__ ((aligned (16))) = 1;
  26
  27 // Because of the lack of weak support when using the hpux som
  28 // linker, we explicitly instantiate the atomicity lock.
  29 template volatile int _pa_jv_cas_lock<0>::_S_pa_jv_cas_lock;
  30
  31 // Atomically replace *addr by new_val if it was initially equal to old_val.
  32 // Return true if the comparison is successful.
  33 // Assumed to have acquire semantics, i.e. later memory operations
  34 // cannot execute before the compare_and_swap finishes.
  35 // The following implementation is atomic but it can deadlock
  36 // (e.g., if a thread dies holding the lock).
  37 inline static bool
  38 __attribute__ ((__unused__))
  39 compare_and_swap(volatile obj_addr_t *addr,
  40                  obj_addr_t old_val,
  41                  obj_addr_t new_val)
  42 {
  43   bool result;
  44   int tmp;
  45   volatile int& lock = _pa_jv_cas_lock<0>::_S_pa_jv_cas_lock;
  46
  47   __asm__ __volatile__ ("ldcw 0(%1),%0\n\t"
  48                         "cmpib,<>,n 0,%0,.+20\n\t"
  49                         "ldw 0(%1),%0\n\t"
  50                         "cmpib,= 0,%0,.-4\n\t"
  51                         "nop\n\t"
  52                         "b,n .-20"
  53                         : "=&r" (tmp)
  54                         : "r" (&lock)
  55                         : "memory");
  56
  57   if (*addr != old_val)
  58     result = false;
  59   else
  60     {
  61       *addr = new_val;
  62       result = true;
  63     }
  64
  65   /* Reset lock with PA 2.0 "ordered" store.  */
  66   __asm__ __volatile__ ("stw,ma %1,0(%0)"
  67                         : : "r" (&lock), "r" (tmp) : "memory");
  68
  69   return result;
  70 }
  71
  72 // Set *addr to new_val with release semantics, i.e. making sure
  73 // that prior loads and stores complete before this
  74 // assignment.
  75 inline static void
  76 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
  77 {
  78   __asm__ __volatile__(" " : : : "memory");
  79   *(addr) = new_val;
  80 }
  81
  82 // Compare_and_swap with release semantics instead of acquire semantics.
  83 // On many architecture, the operation makes both guarantees, so the
  84 // implementation can be the same.
  85 inline static bool
  86 compare_and_swap_release(volatile obj_addr_t *addr,
  87                                                      obj_addr_t old,
  88                                                      obj_addr_t new_val)
  89 {
  90   return compare_and_swap(addr, old, new_val);
  91 }
  92
  93 // Ensure that subsequent instructions do not execute on stale
  94 // data that was loaded from memory before the barrier.
  95 inline static void
  96 read_barrier()
  97 {
  98   __asm__ __volatile__(" " : : : "memory");
  99 }
 100
 101 // Ensure that prior stores to memory are completed with respect to other
 102 // processors.
 103 inline static void
 104 write_barrier()
 105 {
 106   __asm__ __volatile__(" " : : : "memory");
 107 }
 108
 109 #endif
 110