1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
2 /* { dg-options "-O2 -ftree-vectorize --save-temps" } */
5 #define TYPE unsigned char
14 void __attribute__ ((noinline
, noclone
))
15 NAME(f2
) (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
)
17 for (int i
= 0; i
< N
; ++i
)
24 void __attribute__ ((noinline
, noclone
))
25 NAME(f3
) (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
,
28 for (int i
= 0; i
< N
; ++i
)
36 void __attribute__ ((noinline
, noclone
))
37 NAME(f4
) (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
,
38 TYPE
*__restrict d
, TYPE
*__restrict e
)
40 for (int i
= 0; i
< N
; ++i
)
49 void __attribute__ ((noinline
, noclone
))
50 NAME(g2
) (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
)
52 for (int i
= 0; i
< N
; ++i
)
59 void __attribute__ ((noinline
, noclone
))
60 NAME(g3
) (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
,
63 for (int i
= 0; i
< N
; ++i
)
71 void __attribute__ ((noinline
, noclone
))
72 NAME(g4
) (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
,
73 TYPE
*__restrict d
, TYPE
*__restrict e
)
75 for (int i
= 0; i
< N
; ++i
)
84 /* { dg-final { scan-assembler {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */
85 /* { dg-final { scan-assembler {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */
86 /* { dg-final { scan-assembler {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */
87 /* { dg-final { scan-assembler {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */
88 /* { dg-final { scan-assembler {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */
89 /* { dg-final { scan-assembler {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */