1 /* { dg-do compile } */
2 /* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=scalable" } */
6 #define VEC_PERM(TYPE) \
7 TYPE __attribute__ ((noinline, noclone)) \
8 vec_slp_##TYPE (TYPE *restrict a, int n) \
10 for (int i = 0; i < n; ++i) \
38 /* 1 for each 8-bit type, 4 for each 32-bit type and 8 for double. */
39 /* { dg-final { scan-assembler-times {\tld1rd\tz[0-9]+\.d, } 22 } } */
40 /* 1 for each 16-bit type. */
41 /* { dg-final { scan-assembler-times {\tld1rqb\tz[0-9]\.b, } 3 } } */
42 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #99\n} 2 } } */
43 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #11\n} 2 } } */
44 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #17\n} 2 } } */
45 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #80\n} 2 } } */
46 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #63\n} 2 } } */
47 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #37\n} 2 } } */
48 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #24\n} 2 } } */
49 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #81\n} 2 } } */
50 /* The 32-bit types need:
52 ZIP1 ZIP1 (2 ZIP2s optimized away)
55 and the 64-bit types need:
57 ZIP1 ZIP1 ZIP1 ZIP1 (4 ZIP2s optimized away)
59 ZIP1 ZIP2 ZIP1 ZIP2. */
60 /* { dg-final { scan-assembler-times {\tzip1\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 33 } } */
61 /* { dg-final { scan-assembler-times {\tzip2\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 15 } } */
63 /* The loop should be fully-masked. The 32-bit types need two loads
64 and stores each and the 64-bit types need four. */
65 /* { dg-final { scan-assembler-times {\tld1b\t} 2 } } */
66 /* { dg-final { scan-assembler-times {\tst1b\t} 2 } } */
67 /* { dg-final { scan-assembler-times {\tld1h\t} 3 } } */
68 /* { dg-final { scan-assembler-times {\tst1h\t} 3 } } */
69 /* { dg-final { scan-assembler-times {\tld1w\t} 6 } } */
70 /* { dg-final { scan-assembler-times {\tst1w\t} 6 } } */
71 /* { dg-final { scan-assembler-times {\tld1d\t} 12 } } */
72 /* { dg-final { scan-assembler-times {\tst1d\t} 12 } } */
73 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.b} 4 } } */
74 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.h} 6 } } */
75 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s} 12 } } */
76 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d} 24 } } */
77 /* { dg-final { scan-assembler-not {\tldr} } } */
78 /* { dg-final { scan-assembler-not {\tstr} } } */
80 /* { dg-final { scan-assembler-not {\tuqdec[bh]\t} } } */
81 /* We use UQDECW instead of UQDECD ..., MUL #2. */
82 /* { dg-final { scan-assembler-times {\tuqdecw\t} 6 } } */
83 /* { dg-final { scan-assembler-times {\tuqdecd\t} 6 } } */