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(CONST_OK_FOR_LETTER_P): Only allow constants valid when inverted for 'K'.
[official-gcc.git] / gcc / config / arm / arm.h
blob3163cd9e2015f88f7839e0f9f10159ad6a67a508
1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
23 /* Sometimes the directive `riscos' is checked. This does not imply that this
24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
27 extern void output_func_prologue ();
28 extern void output_func_epilogue ();
29 extern char *output_add_immediate ();
30 extern char *output_call ();
31 extern char *output_call_mem ();
32 extern char *output_move_double ();
33 extern char *output_mov_double_fpu_from_arm ();
34 extern char *output_mov_double_arm_from_fpu ();
35 extern char *output_mov_long_double_fpu_from_arm ();
36 extern char *output_mov_long_double_arm_from_fpu ();
37 extern char *output_mov_long_double_arm_from_arm ();
38 extern char *output_mov_immediate ();
39 extern char *output_multi_immediate ();
40 extern char *output_return_instruction ();
41 extern char *output_load_symbol ();
42 extern char *fp_immediate_constant ();
43 extern struct rtx_def *gen_compare_reg ();
44 extern struct rtx_def *arm_gen_store_multiple ();
45 extern struct rtx_def *arm_gen_load_multiple ();
46
47 extern char *arm_condition_codes[];
48
49 /* This is needed by the tail-calling peepholes */
50 extern int frame_pointer_needed;
51
52 \f
53 #ifndef CPP_PREDEFINES
54 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
55 #endif
56
57 #ifndef CPP_SPEC
58 #define CPP_SPEC "%{m6:-D__arm6__}"
59 #endif
60 \f
61 /* Run-time Target Specification. */
62 #ifndef TARGET_VERSION
63 #define TARGET_VERSION \
64 fputs (" (ARM/generic)", stderr);
65 #endif
66
67 /* Run-time compilation parameters selecting different hardware subsets.
68 On the ARM, misuse it in a different way. */
69 extern int target_flags;
70
71 /* Nonzero if the function prologue (and epilogue) should obey
72 the ARM Procedure Call Standard. */
73 #define TARGET_APCS (target_flags & 1)
74
75 /* Nonzero if the function prologue should output the function name to enable
76 the post mortem debugger to print a backtrace (very useful on RISCOS,
77 unused on RISCiX). Specifying this flag also enables -mapcs.
78 XXX Must still be implemented in the prologue. */
79 #define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
80
81 /* Nonzero if floating point instructions are emulated by the FPE, in which
82 case instruction scheduling becomes very uninteresting. */
83 #define TARGET_FPE (target_flags & 4)
84
85 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
86 of condition flags when returning from a branch & link (ie. a function) */
87 #define TARGET_6 (target_flags & 8)
88
89 /* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
90 are passed to the preprocessor and the assembler post-processor. They
91 aren't needed in the main pass of the compiler, but if we don't define
92 them in target switches cc1 complains about them. For the sake of
93 argument lets allocate bit 31 of target flags for such options. */
94
95 #ifndef ARM_EXTRA_TARGET_SWITCHES
96 #define ARM_EXTRA_TARGET_SWITCHES
97 #endif
98
99 #define TARGET_SWITCHES \
100 { \
101 {"apcs", 1}, \
102 {"poke-function-name", 2}, \
103 {"fpe", 4}, \
104 {"6", 8}, \
105 {"2", -8}, \
106 {"3", -8}, \
107 ARM_EXTRA_TARGET_SWITCHES \
108 {"", TARGET_DEFAULT } \
109 }
110
111 /* Which processor we are running on. Currently this is only used to
112 get the condition code clobbering attribute right when we are running on
113 an arm 6 */
114
115 enum processor_type
116 {
117 PROCESSOR_ARM2,
118 PROCESSOR_ARM3,
119 PROCESSOR_ARM6
120 };
121
122 /* Recast the cpu class to be the cpu attribute. */
123
124 /* Recast the cpu class to be the cpu attribute. */
125 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
126
127 extern enum processor_type arm_cpu;
128
129 #define TARGET_DEFAULT 0
130
131 #define TARGET_MEM_FUNCTIONS 1
132
133 /* OVERRIDE_OPTIONS takes care of the following:
134 - if -mpoke-function-name, then -mapcs.
135 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
136 - if floating point is done by emulation, forget about instruction
137 scheduling. Note that this only saves compilation time; it doesn't
138 matter for the final code. */
139 #ifndef TARGET_WHEN_DEBUGGING
140 #define TARGET_WHEN_DEBUGGING 1
141 #endif
142
143 #define OVERRIDE_OPTIONS \
144 { \
145 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
146 warning ("-g without a frame pointer may not give sensible debugging");\
147 if (TARGET_POKE_FUNCTION_NAME) \
148 target_flags |= 1; \
149 if (TARGET_FPE) \
150 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
151 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
152 }
153 \f
154 /* Target machine storage Layout. */
155
156
157 /* Define this macro if it is advisable to hold scalars in registers
158 in a wider mode than that declared by the program. In such cases,
159 the value is constrained to be within the bounds of the declared
160 type, but kept valid in the wider mode. The signedness of the
161 extension may differ from that of the type. */
162
163 /* It is far faster to zero extend chars than to sign extend them */
164
165 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
166 if (GET_MODE_CLASS (MODE) == MODE_INT \
167 && GET_MODE_SIZE (MODE) < 4) \
168 { \
169 if (MODE == QImode) \
170 UNSIGNEDP = 1; \
171 (MODE) = SImode; \
172 }
173
174 /* Define for XFmode extended real floating point support.
175 This will automatically cause REAL_ARITHMETIC to be defined. */
176 /* For the ARM:
177 I think I have added all the code to make this work. Unfortunately,
178 early releases of the floating point emulation code on RISCiX used a
179 different format for extended precision numbers. On my RISCiX box there
180 is a bug somewhere which causes the machine to lock up when running enquire
181 with long doubles. There is the additional aspect that Norcroft C
182 treats long doubles as doubles and we ought to remain compatible.
183 Perhaps someone with an FPA coprocessor and not running RISCiX would like
184 to try this someday. */
185 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
186
187 /* Disable XFmode patterns in md file */
188 #define ENABLE_XF_PATTERNS 0
189
190 /* Define if you don't want extended real, but do want to use the
191 software floating point emulator for REAL_ARITHMETIC and
192 decimal <-> binary conversion. */
193 /* See comment above */
194 #define REAL_ARITHMETIC
195
196 /* Define this if most significant bit is lowest numbered
197 in instructions that operate on numbered bit-fields. */
198 #define BITS_BIG_ENDIAN 0
199
200 /* Define this if most significant byte of a word is the lowest numbered. */
201 #define BYTES_BIG_ENDIAN 0
202
203 /* Define this if most significant word of a multiword number is the lowest
204 numbered. */
205 #define WORDS_BIG_ENDIAN 0
206
207 /* Define this if most significant word of doubles is the lowest numbered */
208 #define FLOAT_WORDS_BIG_ENDIAN 1
209
210 /* Number of bits in an addressable storage unit */
211 #define BITS_PER_UNIT 8
212
213 #define BITS_PER_WORD 32
214
215 #define UNITS_PER_WORD 4
216
217 #define POINTER_SIZE 32
218
219 #define PARM_BOUNDARY 32
220
221 #define STACK_BOUNDARY 32
222
223 #define FUNCTION_BOUNDARY 32
224
225 #define EMPTY_FIELD_BOUNDARY 32
226
227 #define BIGGEST_ALIGNMENT 32
228
229 /* Make strings word-aligned so strcpy from constants will be faster. */
230 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
231 (TREE_CODE (EXP) == STRING_CST \
232 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
233
234 /* Every structures size must be a multiple of 32 bits. */
235 #define STRUCTURE_SIZE_BOUNDARY 32
236
237 /* Non-zero if move instructions will actually fail to work
238 when given unaligned data. */
239 #define STRICT_ALIGNMENT 1
240
241 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
242
243 /* Define number of bits in most basic integer type.
244 (If undefined, default is BITS_PER_WORD). */
245 /* #define INT_TYPE_SIZE */
246 \f
247 /* Standard register usage. */
248
249 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
250 (S - saved over call).
251
252 r0 * argument word/integer result
253 r1-r3 argument word
254
255 r4-r8 S register variable
256 r9 S (rfp) register variable (real frame pointer)
257
258 r10 F S (sl) stack limit (not currently used)
259 r11 F S (fp) argument pointer
260 r12 (ip) temp workspace
261 r13 F S (sp) lower end of current stack frame
262 r14 (lr) link address/workspace
263 r15 F (pc) program counter
264
265 f0 floating point result
266 f1-f3 floating point scratch
267
268 f4-f7 S floating point variable
269
270 cc This is NOT a real register, but is used internally
271 to represent things that use or set the condition
272 codes.
273 sfp This isn't either. It is used during rtl generation
274 since the offset between the frame pointer and the
275 auto's isn't known until after register allocation.
276 afp Nor this, we only need this because of non-local
277 goto. Without it fp appears to be used and the
278 elimination code won't get rid of sfp. It tracks
279 fp exactly at all times.
280
281 *: See CONDITIONAL_REGISTER_USAGE */
282
283 /* The stack backtrace structure is as follows:
284 fp points to here: | save code pointer | [fp]
285 | return link value | [fp, #-4]
286 | return sp value | [fp, #-8]
287 | return fp value | [fp, #-12]
288 [| saved r10 value |]
289 [| saved r9 value |]
290 [| saved r8 value |]
291 [| saved r7 value |]
292 [| saved r6 value |]
293 [| saved r5 value |]
294 [| saved r4 value |]
295 [| saved r3 value |]
296 [| saved r2 value |]
297 [| saved r1 value |]
298 [| saved r0 value |]
299 [| saved f7 value |] three words
300 [| saved f6 value |] three words
301 [| saved f5 value |] three words
302 [| saved f4 value |] three words
303 r0-r3 are not normally saved in a C function. */
304
305 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
306 #define FIRST_PSEUDO_REGISTER 27
307
308 /* 1 for registers that have pervasive standard uses
309 and are not available for the register allocator. */
310 #define FIXED_REGISTERS \
311 { \
312 0,0,0,0,0,0,0,0, \
313 0,0,1,1,0,1,0,1, \
314 0,0,0,0,0,0,0,0, \
315 1,1,1 \
316 }
317
318 /* 1 for registers not available across function calls.
319 These must include the FIXED_REGISTERS and also any
320 registers that can be used without being saved.
321 The latter must include the registers where values are returned
322 and the register where structure-value addresses are passed.
323 Aside from that, you can include as many other registers as you like.
324 The CC is not preserved over function calls on the ARM 6, so it is
325 easier to assume this for all. SFP is preserved, since FP is. */
326 #define CALL_USED_REGISTERS \
327 { \
328 1,1,1,1,0,0,0,0, \
329 0,0,1,1,1,1,1,1, \
330 1,1,1,1,0,0,0,0, \
331 1,1,1 \
332 }
333
334 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
335 trampled. This effectively reduces the number of available registers by 1.
336 XXX It is a hack, I know.
337 XXX Is this still needed? */
338 #define CONDITIONAL_REGISTER_USAGE \
339 { \
340 if (obey_regdecls) \
341 fixed_regs[0] = 1; \
342 }
343
344 /* Return number of consecutive hard regs needed starting at reg REGNO
345 to hold something of mode MODE.
346 This is ordinarily the length in words of a value of mode MODE
347 but can be less for certain modes in special long registers.
348
349 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
350 mode. */
351 #define HARD_REGNO_NREGS(REGNO, MODE) \
352 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
353 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
354 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
355
356 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
357 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
358 regs holding FP. */
359 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
360 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
361 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
362 || REGNO == ARG_POINTER_REGNUM \
363 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
364
365 /* Value is 1 if it is a good idea to tie two pseudo registers
366 when one has mode MODE1 and one has mode MODE2.
367 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
368 for any hard reg, then this must be 0 for correct output. */
369 #define MODES_TIEABLE_P(MODE1, MODE2) \
370 (((MODE1) == SFmode || (MODE1) == DFmode) \
371 == ((MODE2) == SFmode || (MODE2) == DFmode))
372
373 /* Specify the registers used for certain standard purposes.
374 The values of these macros are register numbers. */
375
376 /* Define this if the program counter is overloaded on a register. */
377 #define PC_REGNUM 15
378
379 /* Register to use for pushing function arguments. */
380 #define STACK_POINTER_REGNUM 13
381
382 /* Base register for access to local variables of the function. */
383 #define FRAME_POINTER_REGNUM 25
384
385 /* Define this to be where the real frame pointer is if it is not possible to
386 work out the offset between the frame pointer and the automatic variables
387 until after register allocation has taken place. FRAME_POINTER_REGNUM
388 should point to a special register that we will make sure is eliminated. */
389 #define HARD_FRAME_POINTER_REGNUM 11
390
391 /* Value should be nonzero if functions must have frame pointers.
392 Zero means the frame pointer need not be set up (and parms may be accessed
393 via the stack pointer) in functions that seem suitable.
394 If we have to have a frame pointer we might as well make use of it.
395 APCS says that the frame pointer does not need to be pushed in leaf
396 functions. */
397 #define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ())
398
399 /* Base register for access to arguments of the function. */
400 #define ARG_POINTER_REGNUM 26
401
402 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
403 as an invisible last argument (possible since varargs don't exist in
404 Pascal), so the following is not true. */
405 #define STATIC_CHAIN_REGNUM 8
406
407 /* Register in which address to store a structure value
408 is passed to a function. */
409 #define STRUCT_VALUE_REGNUM 0
410
411 /* Internal, so that we don't need to refer to a raw number */
412 #define CC_REGNUM 24
413
414 /* The order in which register should be allocated. It is good to use ip
415 since no saving is required (though calls clobber it) and it never contains
416 function parameters. It is quite good to use lr since other calls may
417 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
418 least likely to contain a function parameter; in addition results are
419 returned in r0.
420 */
421 #define REG_ALLOC_ORDER \
422 { \
423 3, 2, 1, 0, 12, 14, 4, 5, \
424 6, 7, 8, 10, 9, 11, 13, 15, \
425 16, 17, 18, 19, 20, 21, 22, 23, \
426 24, 25 \
427 }
428 \f
429 /* Register and constant classes. */
430
431 /* Register classes: all ARM regs or all FPU regs---simple! */
432 enum reg_class
433 {
434 NO_REGS,
435 FPU_REGS,
436 GENERAL_REGS,
437 ALL_REGS,
438 LIM_REG_CLASSES
439 };
440
441 #define N_REG_CLASSES (int) LIM_REG_CLASSES
442
443 /* Give names of register classes as strings for dump file. */
444 #define REG_CLASS_NAMES \
445 { \
446 "NO_REGS", \
447 "FPU_REGS", \
448 "GENERAL_REGS", \
449 "ALL_REGS", \
450 }
451
452 /* Define which registers fit in which classes.
453 This is an initializer for a vector of HARD_REG_SET
454 of length N_REG_CLASSES. */
455 #define REG_CLASS_CONTENTS \
456 { \
457 0x0000000, /* NO_REGS */ \
458 0x0FF0000, /* FPU_REGS */ \
459 0x200FFFF, /* GENERAL_REGS */ \
460 0x2FFFFFF /* ALL_REGS */ \
461 }
462
463 /* The same information, inverted:
464 Return the class number of the smallest class containing
465 reg number REGNO. This could be a conditional expression
466 or could index an array. */
467 #define REGNO_REG_CLASS(REGNO) \
468 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
469 || REGNO == ARG_POINTER_REGNUM) \
470 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
471 ? NO_REGS : FPU_REGS)
472
473 /* The class value for index registers, and the one for base regs. */
474 #define INDEX_REG_CLASS GENERAL_REGS
475 #define BASE_REG_CLASS GENERAL_REGS
476
477 /* Get reg_class from a letter such as appears in the machine description.
478 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
479 #define REG_CLASS_FROM_LETTER(C) \
480 ((C)=='f' ? FPU_REGS : NO_REGS)
481
482 /* The letters I, J, K, L and M in a register constraint string
483 can be used to stand for particular ranges of immediate operands.
484 This macro defines what the ranges are.
485 C is the letter, and VALUE is a constant value.
486 Return 1 if VALUE is in the range specified by C.
487 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
488 J: valid indexing constants.
489 K: ~value ok in rhs argument of data operand.
490 L: -value ok in rhs argument of data operand. */
491 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
492 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
493 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
494 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
495 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : 0)
496
497 /* For the ARM, `Q' means that this is a memory operand that is just
498 an offset from a register.
499 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
500 address. This means that the symbol is in the text segment and can be
501 accessed without using a load. */
502
503 #define EXTRA_CONSTRAINT(OP, C) \
504 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
505 : (C) == 'R' ? (GET_CODE (OP) == MEM \
506 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
507 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
508 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
509
510 /* Constant letter 'G' for the FPU immediate constants.
511 'H' means the same constant negated. */
512 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
513 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
514 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
515
516 /* Given an rtx X being reloaded into a reg required to be
517 in class CLASS, return the class of reg to actually use.
518 In general this is just CLASS; but on some machines
519 in some cases it is preferable to use a more restrictive class. */
520 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
521
522 /* Return the register class of a scratch register needed to copy IN into
523 or out of a register in CLASS in MODE. If it can be done directly,
524 NO_REGS is returned. */
525 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
526 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
527 && true_regnum (X) == -1) ? GENERAL_REGS \
528 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
529
530 /* Return the maximum number of consecutive registers
531 needed to represent mode MODE in a register of class CLASS.
532 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
533 #define CLASS_MAX_NREGS(CLASS, MODE) \
534 ((CLASS) == FPU_REGS ? 1 \
535 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
536
537 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
538 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
539 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
540 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
541 ? 20 : 2)
542 \f
543 /* Stack layout; function entry, exit and calling. */
544
545 /* Define this if pushing a word on the stack
546 makes the stack pointer a smaller address. */
547 #define STACK_GROWS_DOWNWARD 1
548
549 /* Define this if the nominal address of the stack frame
550 is at the high-address end of the local variables;
551 that is, each additional local variable allocated
552 goes at a more negative offset in the frame. */
553 #define FRAME_GROWS_DOWNWARD 1
554
555 /* Offset within stack frame to start allocating local variables at.
556 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
557 first local allocated. Otherwise, it is the offset to the BEGINNING
558 of the first local allocated. */
559 #define STARTING_FRAME_OFFSET 0
560
561 /* If we generate an insn to push BYTES bytes,
562 this says how many the stack pointer really advances by. */
563 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
564
565 /* Offset of first parameter from the argument pointer register value. */
566 #define FIRST_PARM_OFFSET(FNDECL) 4
567
568 /* Value is the number of byte of arguments automatically
569 popped when returning from a subroutine call.
570 FUNTYPE is the data type of the function (as a tree),
571 or for a library call it is an identifier node for the subroutine name.
572 SIZE is the number of bytes of arguments passed on the stack.
573
574 On the ARM, the caller does not pop any of its arguments that were passed
575 on the stack. */
576 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
577
578 /* Define how to find the value returned by a function.
579 VALTYPE is the data type of the value (as a tree).
580 If the precise function being called is known, FUNC is its FUNCTION_DECL;
581 otherwise, FUNC is 0. */
582 #define FUNCTION_VALUE(VALTYPE, FUNC) \
583 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
584 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
585 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
586
587 /* Define how to find the value returned by a library function
588 assuming the value has mode MODE. */
589 #define LIBCALL_VALUE(MODE) \
590 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
591 ? gen_rtx (REG, MODE, 16) \
592 : gen_rtx (REG, MODE, 0))
593
594 /* 1 if N is a possible register number for a function value.
595 On the ARM, only r0 and f0 can return results. */
596 #define FUNCTION_VALUE_REGNO_P(REGNO) \
597 ((REGNO) == 0 || (REGNO) == 16)
598
599 /* Define where to put the arguments to a function.
600 Value is zero to push the argument on the stack,
601 or a hard register in which to store the argument.
602
603 MODE is the argument's machine mode.
604 TYPE is the data type of the argument (as a tree).
605 This is null for libcalls where that information may
606 not be available.
607 CUM is a variable of type CUMULATIVE_ARGS which gives info about
608 the preceding args and about the function being called.
609 NAMED is nonzero if this argument is a named parameter
610 (otherwise it is an extra parameter matching an ellipsis).
611
612 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
613 other arguments are passed on the stack. If (NAMED == 0) (which happens
614 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
615 passed in the stack (function_prologue will indeed make it pass in the
616 stack if necessary). */
617 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
618 ((NAMED) \
619 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
620 : 0)
621
622 /* For an arg passed partly in registers and partly in memory,
623 this is the number of registers used.
624 For args passed entirely in registers or entirely in memory, zero. */
625 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
626 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
627 ? GET_MODE_SIZE (MODE) \
628 : int_size_in_bytes (TYPE)) \
629 ? 4 - (CUM) / 4 : 0)
630
631 /* A C type for declaring a variable that is used as the first argument of
632 `FUNCTION_ARG' and other related values. For some target machines, the
633 type `int' suffices and can hold the number of bytes of argument so far.
634
635 On the ARM, this is the number of bytes of arguments scanned so far. */
636 #define CUMULATIVE_ARGS int
637
638 /* Initialize a variable CUM of type CUMULATIVE_ARGS
639 for a call to a function whose data type is FNTYPE.
640 For a library call, FNTYPE is 0.
641 On the ARM, the offset starts at 0. */
642 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
643 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
644
645 /* Update the data in CUM to advance over an argument
646 of mode MODE and data type TYPE.
647 (TYPE is null for libcalls where that information may not be available.) */
648 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
649 (CUM) += ((MODE) != BLKmode \
650 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
651 : (int_size_in_bytes (TYPE) + 3) & ~3) \
652
653 /* 1 if N is a possible register number for function argument passing.
654 On the ARM, r0-r3 are used to pass args. */
655 #define FUNCTION_ARG_REGNO_P(REGNO) \
656 ((REGNO) >= 0 && (REGNO) <= 3)
657
658 /* Perform any actions needed for a function that is receiving a variable
659 number of arguments. CUM is as above. MODE and TYPE are the mode and type
660 of the current parameter. PRETEND_SIZE is a variable that should be set to
661 the amount of stack that must be pushed by the prolog to pretend that our
662 caller pushed it.
663
664 Normally, this macro will push all remaining incoming registers on the
665 stack and set PRETEND_SIZE to the length of the registers pushed.
666
667 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
668 named arg and all anonymous args onto the stack.
669 XXX I know the prologue shouldn't be pushing registers, but it is faster
670 that way. */
671 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
672 { \
673 extern int current_function_anonymous_args; \
674 current_function_anonymous_args = 1; \
675 if ((CUM) < 16) \
676 (PRETEND_SIZE) = 16 - (CUM); \
677 }
678
679 /* Generate assembly output for the start of a function. */
680 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
681 output_func_prologue ((STREAM), (SIZE))
682
683 /* Call the function profiler with a given profile label. The Acorn compiler
684 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
685 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
686 to mind about this! */
687 #define FUNCTION_PROFILER(STREAM,LABELNO) \
688 { \
689 fprintf(STREAM, "\tmov\tip, lr\n"); \
690 fprintf(STREAM, "\tbl\tmcount\n"); \
691 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
692 arm_increase_location (12); \
693 }
694
695 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
696 the stack pointer does not matter. The value is tested only in
697 functions that have frame pointers.
698 No definition is equivalent to always zero.
699
700 On the ARM, the function epilogue recovers the stack pointer from the
701 frame. */
702 #define EXIT_IGNORE_STACK 1
703
704 /* Generate the assembly code for function exit. */
705 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
706 output_func_epilogue ((STREAM), (SIZE))
707
708 /* Determine if the epilogue should be output as RTL.
709 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
710 #define USE_RETURN_INSN use_return_insn ()
711
712 /* Definitions for register eliminations.
713
714 This is an array of structures. Each structure initializes one pair
715 of eliminable registers. The "from" register number is given first,
716 followed by "to". Eliminations of the same "from" register are listed
717 in order of preference.
718
719 We have two registers that can be eliminated on the ARM. First, the
720 arg pointer register can often be eliminated in favor of the stack
721 pointer register. Secondly, the pseudo frame pointer register can always
722 be eliminated; it is replaced with either the stack or the real frame
723 pointer. */
724
725 #define ELIMINABLE_REGS \
726 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
727 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
728 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
729 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
730
731 /* Given FROM and TO register numbers, say whether this elimination is allowed.
732 Frame pointer elimination is automatically handled.
733
734 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
735 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
736 pointer, we must eliminate FRAME_POINTER_REGNUM into
737 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
738 #define CAN_ELIMINATE(FROM, TO) \
739 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
740
741 /* Define the offset between two registers, one to be eliminated, and the other
742 its replacement, at the start of a routine. */
743 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
744 { \
745 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
746 (OFFSET) = 0; \
747 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
748 (OFFSET) = (get_frame_size () + 3 & ~3); \
749 else \
750 { \
751 int regno; \
752 int offset = 12; \
753 int saved_hard_reg = 0; \
754 \
755 for (regno = 0; regno <= 10; regno++) \
756 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
757 saved_hard_reg = 1, offset += 4; \
758 for (regno = 16; regno <=23; regno++) \
759 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
760 offset += 12; \
761 if ((FROM) == FRAME_POINTER_REGNUM) \
762 (OFFSET) = -offset; \
763 else \
764 { \
765 if (! regs_ever_live[HARD_FRAME_POINTER_REGNUM]) \
766 offset -= 16; \
767 if (regs_ever_live[14] || saved_hard_reg) \
768 offset += 4; \
769 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
770 } \
771 } \
772 }
773
774 /* Output assembler code for a block containing the constant parts
775 of a trampoline, leaving space for the variable parts.
776
777 On the ARM, (if r8 is the static chain regnum, and remembering that
778 referencing pc adds an offset of 8) the trampoline looks like:
779 ldr r8, [pc, #0]
780 ldr pc, [pc]
781 .word static chain value
782 .word function's address */
783 #define TRAMPOLINE_TEMPLATE(FILE) \
784 { \
785 fprintf ((FILE), "\tldr\tr8, [pc, #0]\n"); \
786 fprintf ((FILE), "\tldr\tpc, [pc, #0]\n"); \
787 fprintf ((FILE), "\t.word\t0\n"); \
788 fprintf ((FILE), "\t.word\t0\n"); \
789 }
790
791 /* Length in units of the trampoline for entering a nested function. */
792 #define TRAMPOLINE_SIZE 16
793
794 /* Alignment required for a trampoline in units. */
795 #define TRAMPOLINE_ALIGN 4
796
797 /* Emit RTL insns to initialize the variable parts of a trampoline.
798 FNADDR is an RTX for the address of the function's pure code.
799 CXT is an RTX for the static chain value for the function. */
800 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
801 { \
802 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
803 (CXT)); \
804 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
805 (FNADDR)); \
806 }
807
808 /* Call the function profiler with a given profile label. The Acorn compiler
809 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
810 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
811 to mind about this! */
812 #define FUNCTION_PROFILER(STREAM,LABELNO) \
813 { \
814 fprintf(STREAM, "\tmov\tip, lr\n"); \
815 fprintf(STREAM, "\tbl\tmcount\n"); \
816 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
817 arm_increase_location (12); \
818 }
819 \f
820 /* Addressing modes, and classification of registers for them. */
821
822 #define HAVE_POST_INCREMENT 1
823 #define HAVE_PRE_INCREMENT 1
824 #define HAVE_POST_DECREMENT 1
825 #define HAVE_PRE_DECREMENT 1
826
827 /* Macros to check register numbers against specific register classes. */
828
829 /* These assume that REGNO is a hard or pseudo reg number.
830 They give nonzero only if REGNO is a hard reg of the suitable class
831 or a pseudo reg currently allocated to a suitable hard reg.
832 Since they use reg_renumber, they are safe only once reg_renumber
833 has been allocated, which happens in local-alloc.c.
834
835 On the ARM, don't allow the pc to be used. */
836 #define REGNO_OK_FOR_BASE_P(REGNO) \
837 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
838 || (REGNO) == ARG_POINTER_REGNUM \
839 || (unsigned) reg_renumber[(REGNO)] < 15 \
840 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
841 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
842 #define REGNO_OK_FOR_INDEX_P(REGNO) \
843 REGNO_OK_FOR_BASE_P(REGNO)
844
845 /* Maximum number of registers that can appear in a valid memory address.
846 Shifts in addresses can't be by a register. */
847
848 #define MAX_REGS_PER_ADDRESS 2
849
850 /* Recognize any constant value that is a valid address. */
851 /* XXX We can address any constant, eventually... */
852 #if 0
853 #define CONSTANT_ADDRESS_P(X) \
854 ( GET_CODE(X) == LABEL_REF \
855 || GET_CODE(X) == SYMBOL_REF \
856 || GET_CODE(X) == CONST_INT \
857 || GET_CODE(X) == CONST )
858 #endif
859
860 #define CONSTANT_ADDRESS_P(X) \
861 (GET_CODE (X) == SYMBOL_REF \
862 && (CONSTANT_POOL_ADDRESS_P (X) \
863 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
864
865 /* Nonzero if the constant value X is a legitimate general operand.
866 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
867
868 On the ARM, allow any integer (invalid ones are removed later by insn
869 patterns), nice doubles and symbol_refs which refer to the function's
870 constant pool XXX. */
871 #define LEGITIMATE_CONSTANT_P(X) \
872 (GET_CODE (X) == CONST_INT \
873 || (GET_CODE (X) == CONST_DOUBLE \
874 && (const_double_rtx_ok_for_fpu (X) \
875 || neg_const_double_rtx_ok_for_fpu (X))) \
876 || CONSTANT_ADDRESS_P (X))
877
878 /* Symbols in the text segment can be accessed without indirecting via the
879 constant pool; it may take an extra binary operation, but this is still
880 faster than indirecting via memory. Don't do this when not optimizing,
881 since we won't be calculating al of the offsets necessary to do this
882 simplification. */
883
884 #define ENCODE_SECTION_INFO(decl) \
885 { \
886 if (optimize > 0 && TREE_CONSTANT (decl) \
887 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
888 { \
889 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
890 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
891 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
892 } \
893 }
894
895 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
896 and check its validity for a certain class.
897 We have two alternate definitions for each of them.
898 The usual definition accepts all pseudo regs; the other rejects
899 them unless they have been allocated suitable hard regs.
900 The symbol REG_OK_STRICT causes the latter definition to be used. */
901 #ifndef REG_OK_STRICT
902
903 /* Nonzero if X is a hard reg that can be used as a base reg
904 or if it is a pseudo reg. */
905 #define REG_OK_FOR_BASE_P(X) \
906 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
907 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
908
909 /* Nonzero if X is a hard reg that can be used as an index
910 or if it is a pseudo reg. */
911 #define REG_OK_FOR_INDEX_P(X) \
912 REG_OK_FOR_BASE_P(X)
913
914 #define REG_OK_FOR_PRE_POST_P(X) \
915 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
916 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
917
918 #else
919
920 /* Nonzero if X is a hard reg that can be used as a base reg. */
921 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
922
923 /* Nonzero if X is a hard reg that can be used as an index. */
924 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
925
926 #define REG_OK_FOR_PRE_POST_P(X) \
927 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
928 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
929 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
930 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
931
932 #endif
933 \f
934 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
935 that is a valid memory address for an instruction.
936 The MODE argument is the machine mode for the MEM expression
937 that wants to use this address.
938
939 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
940 #define BASE_REGISTER_RTX_P(X) \
941 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
942
943 #define INDEX_REGISTER_RTX_P(X) \
944 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
945
946 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
947 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
948 only be small constants. */
949 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
950 do \
951 { \
952 HOST_WIDE_INT range; \
953 enum rtx_code code = GET_CODE (INDEX); \
954 \
955 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
956 { \
957 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
958 && INTVAL (INDEX) > -1024 \
959 && (INTVAL (INDEX) & 3) == 0) \
960 goto LABEL; \
961 } \
962 else \
963 { \
964 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
965 goto LABEL; \
966 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
967 { \
968 rtx xiop0 = XEXP (INDEX, 0); \
969 rtx xiop1 = XEXP (INDEX, 1); \
970 if (INDEX_REGISTER_RTX_P (xiop0) \
971 && power_of_two_operand (xiop1, SImode)) \
972 goto LABEL; \
973 if (INDEX_REGISTER_RTX_P (xiop1) \
974 && power_of_two_operand (xiop0, SImode)) \
975 goto LABEL; \
976 } \
977 if (GET_MODE_SIZE (MODE) <= 4 \
978 && (code == LSHIFTRT || code == ASHIFTRT \
979 || code == ASHIFT || code == ROTATERT)) \
980 { \
981 rtx op = XEXP (INDEX, 1); \
982 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
983 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
984 && INTVAL (op) <= 31) \
985 goto LABEL; \
986 } \
987 range = (MODE) == HImode ? 4095 : 4096; \
988 if (code == CONST_INT && INTVAL (INDEX) < range \
989 && INTVAL (INDEX) > -range) \
990 goto LABEL; \
991 } \
992 } while (0)
993
994 /* Jump to LABEL if X is a valid address RTX. This must also take
995 REG_OK_STRICT into account when deciding about valid registers, but it uses
996 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
997 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
998 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
999 refs must be forced though a static cell to ensure addressability. */
1000 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1001 { \
1002 if (BASE_REGISTER_RTX_P (X)) \
1003 goto LABEL; \
1004 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1005 && GET_CODE (XEXP (X, 0)) == REG \
1006 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1007 goto LABEL; \
1008 else if ((MODE) == TImode) \
1009 ; \
1010 else if (GET_CODE (X) == PLUS) \
1011 { \
1012 rtx xop0 = XEXP(X,0); \
1013 rtx xop1 = XEXP(X,1); \
1014 \
1015 if (BASE_REGISTER_RTX_P (xop0)) \
1016 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1017 else if (BASE_REGISTER_RTX_P (xop1)) \
1018 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1019 } \
1020 else if (GET_CODE (X) == MINUS) \
1021 { \
1022 rtx xop0 = XEXP (X,0); \
1023 rtx xop1 = XEXP (X,1); \
1024 \
1025 if (BASE_REGISTER_RTX_P (xop0)) \
1026 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1027 } \
1028 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1029 && GET_CODE (X) == SYMBOL_REF \
1030 && CONSTANT_POOL_ADDRESS_P (X)) \
1031 goto LABEL; \
1032 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1033 && GET_CODE (XEXP (X, 0)) == REG \
1034 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1035 goto LABEL; \
1036 }
1037 \f
1038 /* Try machine-dependent ways of modifying an illegitimate address
1039 to be legitimate. If we find one, return the new, valid address.
1040 This macro is used in only one place: `memory_address' in explow.c.
1041
1042 OLDX is the address as it was before break_out_memory_refs was called.
1043 In some cases it is useful to look at this to decide what needs to be done.
1044
1045 MODE and WIN are passed so that this macro can use
1046 GO_IF_LEGITIMATE_ADDRESS.
1047
1048 It is always safe for this macro to do nothing. It exists to recognize
1049 opportunities to optimize the output.
1050
1051 On the ARM, try to convert [REG, #BIGCONST]
1052 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1053 where VALIDCONST == 0 in case of TImode. */
1054 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1055 { \
1056 if (GET_CODE (X) == PLUS) \
1057 { \
1058 rtx xop0 = XEXP (X, 0); \
1059 rtx xop1 = XEXP (X, 1); \
1060 \
1061 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1062 { \
1063 int n = INTVAL (xop1); \
1064 int low_n = ((MODE) == TImode ? 0 \
1065 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1066 rtx base_reg = gen_reg_rtx (SImode); \
1067 rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1068 gen_rtx (CONST_INT, \
1069 VOIDmode, n - low_n)), \
1070 0); \
1071 emit_move_insn (base_reg, val); \
1072 (X) = (low_n == 0 ? base_reg \
1073 : gen_rtx (PLUS, SImode, base_reg, \
1074 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1075 } \
1076 else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \
1077 { \
1078 int n = INTVAL (xop0); \
1079 int low_n = ((MODE) == TImode ? 0 \
1080 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1081 rtx base_reg = gen_reg_rtx (SImode); \
1082 rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \
1083 gen_rtx (CONST_INT, \
1084 VOIDmode, n - low_n)), \
1085 0); \
1086 emit_move_insn (base_reg, val); \
1087 (X) = (low_n == 0 ? base_reg \
1088 : gen_rtx (PLUS, SImode, base_reg, \
1089 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1090 } \
1091 } \
1092 if (memory_address_p (MODE, X)) \
1093 goto win; \
1094 }
1095
1096 /* Go to LABEL if ADDR (a legitimate address expression)
1097 has an effect that depends on the machine mode it is used for. */
1098 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1099 { \
1100 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1101 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1102 goto LABEL; \
1103 }
1104 \f
1105 /* Specify the machine mode that this machine uses
1106 for the index in the tablejump instruction. */
1107 #define CASE_VECTOR_MODE SImode
1108
1109 /* Define this if the tablejump instruction expects the table
1110 to contain offsets from the address of the table.
1111 Do not define this if the table should contain absolute addresses. */
1112 /* #define CASE_VECTOR_PC_RELATIVE */
1113
1114 /* Specify the tree operation to be used to convert reals to integers. */
1115 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1116
1117 /* This is the kind of divide that is easiest to do in the general case. */
1118 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1119
1120 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1121 unsigned is probably best, but may break some code. */
1122 #ifndef DEFAULT_SIGNED_CHAR
1123 #define DEFAULT_SIGNED_CHAR 1
1124 #endif
1125
1126 /* Don't cse the address of the function being compiled. */
1127 #define NO_RECURSIVE_FUNCTION_CSE 1
1128
1129 /* Max number of bytes we can move from memory to memory
1130 in one reasonably fast instruction. */
1131 #define MOVE_MAX 4
1132
1133 /* Define if operations between registers always perform the operation
1134 on the full register even if a narrower mode is specified. */
1135 #define WORD_REGISTER_OPERATIONS
1136
1137 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1138 will either zero-extend or sign-extend. The value of this macro should
1139 be the code that says which one of the two operations is implicitly
1140 done, NIL if none. */
1141 #define LOAD_EXTEND_OP(MODE) \
1142 ((MODE) == QImode ? ZERO_EXTEND : NIL)
1143
1144 /* Define this if zero-extension is slow (more than one real instruction).
1145 On the ARM, it is more than one instruction only if not fetching from
1146 memory. */
1147 /* #define SLOW_ZERO_EXTEND */
1148
1149 /* Nonzero if access to memory by bytes is slow and undesirable. */
1150 #define SLOW_BYTE_ACCESS 0
1151
1152 /* Immediate shift counts are truncated by the output routines (or was it
1153 the assembler?). Shift counts in a register are truncated by ARM. Note
1154 that the native compiler puts too large (> 32) immediate shift counts
1155 into a register and shifts by the register, letting the ARM decide what
1156 to do instead of doing that itself. */
1157 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1158 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1159 On the arm, Y in a register is used modulo 256 for the shift. Only for
1160 rotates is modulo 32 used. */
1161 /* #define SHIFT_COUNT_TRUNCATED 1 */
1162
1163 /* XX This is not true, is it? */
1164 /* All integers have the same format so truncation is easy. */
1165 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1166
1167 /* Calling from registers is a massive pain. */
1168 #define NO_FUNCTION_CSE 1
1169
1170 /* Chars and shorts should be passed as ints. */
1171 #define PROMOTE_PROTOTYPES 1
1172
1173 /* The machine modes of pointers and functions */
1174 #define Pmode SImode
1175 #define FUNCTION_MODE Pmode
1176
1177 /* The structure type of the machine dependent info field of insns
1178 No uses for this yet. */
1179 /* #define INSN_MACHINE_INFO struct machine_info */
1180
1181 /* The relative costs of various types of constants. Note that cse.c defines
1182 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1183 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1184 case CONST_INT: \
1185 if (const_ok_for_arm (INTVAL (RTX))) \
1186 return (OUTER_CODE) == SET ? 2 : -1; \
1187 else if (OUTER_CODE == AND \
1188 && const_ok_for_arm (~INTVAL (RTX))) \
1189 return -1; \
1190 else if ((OUTER_CODE == COMPARE \
1191 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1192 && const_ok_for_arm (-INTVAL (RTX))) \
1193 return -1; \
1194 else \
1195 return 5; \
1196 case CONST: \
1197 case LABEL_REF: \
1198 case SYMBOL_REF: \
1199 return 6; \
1200 case CONST_DOUBLE: \
1201 if (const_double_rtx_ok_for_fpu (RTX)) \
1202 return (OUTER_CODE) == SET ? 2 : -1; \
1203 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1204 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1205 return -1; \
1206 return(7);
1207
1208 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1209 case MEM: \
1210 { \
1211 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1;\
1212 return (COSTS_N_INSNS (10*num_words)); \
1213 } \
1214 case MULT: \
1215 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1216 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
1217 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1218 return COSTS_N_INSNS (9); \
1219 case ASHIFT: \
1220 case LSHIFTRT: \
1221 case ASHIFTRT: \
1222 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1223 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1224 break; \
1225 case MINUS: \
1226 { \
1227 enum rtx_code code = GET_CODE (XEXP (X, 1)); \
1228 if (code == MULT) \
1229 { \
1230 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \
1231 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1232 return COSTS_N_INSNS (1); \
1233 break; \
1234 } \
1235 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
1236 return COSTS_N_INSNS (1); \
1237 } /* fall through */ \
1238 case PLUS: \
1239 case IOR: \
1240 case XOR: \
1241 case AND: \
1242 { \
1243 enum rtx_code code = GET_CODE (XEXP (X, 0)); \
1244 if (code == MULT) \
1245 { \
1246 if (GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1247 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1248 return COSTS_N_INSNS (1); \
1249 if (GET_CODE (X) == PLUS) \
1250 return COSTS_N_INSNS (12); \
1251 break; \
1252 } \
1253 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
1254 return COSTS_N_INSNS (1); \
1255 break; \
1256 } \
1257 case NOT: \
1258 return rtx_cost (XEXP (X, 0), GET_CODE (XEXP (X, 0))); \
1259 case IF_THEN_ELSE: \
1260 { \
1261 if (GET_CODE (XEXP(X,1)) == PC || GET_CODE (XEXP(X,2)) == PC) \
1262 return COSTS_N_INSNS (4); \
1263 return COSTS_N_INSNS (1); \
1264 } \
1265 case SIGN_EXTEND: \
1266 return COSTS_N_INSNS (2); \
1267 case ZERO_EXTEND: \
1268 if (GET_MODE (XEXP (X, 0)) == QImode) \
1269 { \
1270 if (GET_CODE (XEXP (X, 0)) == MEM) \
1271 return COSTS_N_INSNS (10); \
1272 return COSTS_N_INSNS (1); \
1273 } \
1274 break; \
1275 case COMPARE: \
1276 if (GET_CODE (XEXP (X, 1)) == REG) \
1277 return 4; \
1278 case SMIN: \
1279 case SMAX: \
1280 case UMIN: \
1281 case UMAX: \
1282 return COSTS_N_INSNS (3); \
1283 case ABS: \
1284 if (GET_MODE (X) == SImode) \
1285 return COSTS_N_INSNS (2); \
1286 return COSTS_N_INSNS (1);
1287
1288 /* Moves to and from memory are quite expensive */
1289 #define MEMORY_MOVE_COST(MODE) 10
1290
1291 /* All address computations that can be done are free */
1292 #define ADDRESS_COST(x) 2
1293
1294 /* Try to generate sequences that don't involve branches, we can then use
1295 conditional instructions */
1296 #define BRANCH_COST 4
1297 \f
1298 /* Condition code information. */
1299 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1300 return the mode to be used for the comparison.
1301 CCFPEmode should be used with floating inequalites,
1302 CCFPmode should be used with floating equalities.
1303 CC_NOOVmode should be used with SImode integer equalites
1304 CCmode should be used otherwise. */
1305
1306 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1307
1308 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1309
1310 #define SELECT_CC_MODE(OP,X,Y) \
1311 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1312 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1313 : ((GET_MODE (X) == SImode) \
1314 && ((OP) == EQ || (OP) == NE) \
1315 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1316 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1317 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1318 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
1319 || GET_CODE (X) == LSHIFTRT \
1320 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1321 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1322 ? CC_NOOVmode \
1323 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1324
1325 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1326
1327 #define STORE_FLAG_VALUE 1
1328
1329 /* Define the information needed to generate branch insns. This is
1330 stored from the compare operation. Note that we can't use "rtx" here
1331 since it hasn't been defined! */
1332
1333 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1334 extern int arm_compare_fp;
1335
1336 /* Define the codes that are matched by predicates in arm.c */
1337 #define PREDICATE_CODES \
1338 {"s_register_operand", {SUBREG, REG}}, \
1339 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1340 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1341 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1342 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1343 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1344 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1345 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1346 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \
1347 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1348 {"load_multiple_operation", {PARALLEL}}, \
1349 {"store_multiple_operation", {PARALLEL}}, \
1350 {"equality_operator", {EQ, NE}}, \
1351 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1352 {"const_shift_operand", {CONST_INT}}, \
1353 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1354 {"cc_register", {REG}},
1355
1356 \f
1357 /* Assembler output control */
1358
1359 #ifndef ARM_OS_NAME
1360 #define ARM_OS_NAME "(generic)"
1361 #endif
1362
1363 /* The text to go at the start of the assembler file */
1364 #define ASM_FILE_START(STREAM) \
1365 { \
1366 extern char *version_string; \
1367 \
1368 fprintf (STREAM,"@ Generated by gcc %s for ARM/%s\n", version_string, \
1369 ARM_OS_NAME); \
1370 fprintf (STREAM,"rfp\t.req\tr9\n"); \
1371 fprintf (STREAM,"fp\t.req\tr11\n"); \
1372 fprintf (STREAM,"ip\t.req\tr12\n"); \
1373 fprintf (STREAM,"sp\t.req\tr13\n"); \
1374 fprintf (STREAM,"lr\t.req\tr14\n"); \
1375 fprintf (STREAM,"pc\t.req\tr15\n"); \
1376 }
1377
1378 #define ASM_APP_ON ""
1379 #define ASM_APP_OFF ""
1380
1381 /* Switch to the text or data segment. */
1382 #define TEXT_SECTION_ASM_OP ".text"
1383 #define DATA_SECTION_ASM_OP ".data"
1384
1385 /* The assembler's names for the registers. RFP need not always be used as
1386 the Real framepointer; it can also be used as a normal general register.
1387 Note that the name `fp' is horribly misleading since `fp' is in fact only
1388 the argument-and-return-context pointer. */
1389 #define REGISTER_NAMES \
1390 { \
1391 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1392 "r8","rfp", "sl", "fp", "ip", "sp", "lr", "pc", \
1393 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1394 "cc", "sfp", "afp" \
1395 }
1396
1397 /* Arm Assembler barfs on dollars */
1398 #define DOLLARS_IN_IDENTIFIERS 0
1399
1400 #define NO_DOLLAR_IN_LABEL
1401
1402 /* DBX register number for a given compiler register number */
1403 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1404
1405 /* Generate DBX debugging information. riscix.h will undefine this because
1406 the native assembler does not support stabs. */
1407 #define DBX_DEBUGGING_INFO 1
1408
1409 /* Acorn dbx moans about continuation chars, so don't use any. */
1410 #define DBX_CONTIN_LENGTH 0
1411
1412 /* Output a source filename for the debugger. RISCiX dbx insists that the
1413 ``desc'' field is set to compiler version number >= 315 (sic). */
1414 #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1415 do { \
1416 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1417 &ltext_label_name[1]); \
1418 text_section (); \
1419 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1420 } while (0)
1421
1422 /* Output a label definition. */
1423 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1424 arm_asm_output_label ((STREAM), (NAME))
1425
1426 /* Output a function label definition. */
1427 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1428 ASM_OUTPUT_LABEL(STREAM, NAME)
1429
1430 /* Output a globalising directive for a label. */
1431 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1432 (fprintf (STREAM, "\t.global\t"), \
1433 assemble_name (STREAM, NAME), \
1434 fputc ('\n',STREAM)) \
1435
1436 /* Output a reference to a label. */
1437 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1438 fprintf (STREAM, "_%s", NAME)
1439
1440 /* Make an internal label into a string. */
1441 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1442 sprintf (STRING, "*%s%d", PREFIX, NUM)
1443
1444 /* Output an internal label definition. */
1445 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1446 do \
1447 { \
1448 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1449 extern int arm_target_label, arm_ccfsm_state; \
1450 extern rtx arm_target_insn; \
1451 \
1452 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1453 && !strcmp (PREFIX, "L")) \
1454 { \
1455 arm_ccfsm_state = 0; \
1456 arm_target_insn = NULL; \
1457 } \
1458 strcpy (s, "*"); \
1459 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1460 arm_asm_output_label (STREAM, s); \
1461 } while (0)
1462
1463 /* Nothing special is done about jump tables */
1464 /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1465 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1466
1467 /* Construct a private name. */
1468 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1469 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1470 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1471
1472 /* Output a push or a pop instruction (only used when profiling). */
1473 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1474 fprintf(STREAM,"\tstmfd\tsp!,{%s}\n", reg_names[REGNO])
1475
1476 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1477 fprintf(STREAM,"\tldmfd\tsp!,{%s}\n", reg_names[REGNO])
1478
1479 /* Output a relative address. Not needed since jump tables are absolute
1480 but we must define it anyway. */
1481 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1482 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1483
1484 /* Output an element of a dispatch table. */
1485 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1486 fprintf (STREAM, "\t.word\tL%d\n", VALUE)
1487
1488 /* Output various types of constants. For real numbers we output hex, with
1489 a comment containing the "human" value, this allows us to pass NaN's which
1490 the riscix assembler doesn't understand (it also makes cross-assembling
1491 less likely to fail). */
1492
1493 #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
1494 do { char dstr[30]; \
1495 long l[3]; \
1496 arm_increase_location (12); \
1497 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1498 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1499 if (sizeof (int) == sizeof (long)) \
1500 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t@ long double %s\n", \
1501 l[2], l[1], l[0], dstr); \
1502 else \
1503 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t@ long double %s\n",\
1504 l[0], l[1], l[2], dstr); \
1505 } while (0)
1506
1507
1508 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1509 do { char dstr[30]; \
1510 long l[2]; \
1511 arm_increase_location (8); \
1512 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1513 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1514 if (sizeof (int) == sizeof (long)) \
1515 fprintf (STREAM, "\t.long 0x%x, 0x%x\t@ double %s\n", l[0], l[1],\
1516 dstr); \
1517 else \
1518 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t@ double %s\n", l[0], \
1519 l[1], dstr); \
1520 } while (0)
1521
1522 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1523 do { char dstr[30]; \
1524 long l; \
1525 arm_increase_location (4); \
1526 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1527 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1528 if (sizeof (int) == sizeof (long)) \
1529 fprintf (STREAM, "\t.word 0x%x\t@ float %s\n", l, dstr); \
1530 else \
1531 fprintf (STREAM, "\t.word 0x%lx\t@ float %s\n", l, dstr); \
1532 } while (0);
1533
1534 #define ASM_OUTPUT_INT(STREAM, EXP) \
1535 (fprintf (STREAM, "\t.word\t"), \
1536 output_addr_const (STREAM, (EXP)), \
1537 arm_increase_location (4), \
1538 fputc ('\n', STREAM))
1539
1540 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1541 (fprintf (STREAM, "\t.short\t"), \
1542 output_addr_const (STREAM, (EXP)), \
1543 arm_increase_location (2), \
1544 fputc ('\n', STREAM))
1545
1546 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1547 (fprintf (STREAM, "\t.byte\t"), \
1548 output_addr_const (STREAM, (EXP)), \
1549 arm_increase_location (1), \
1550 fputc ('\n', STREAM))
1551
1552 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1553 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1554 arm_increase_location (1))
1555
1556 #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
1557 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
1558
1559 /* Output a gap. In fact we fill it with nulls. */
1560 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1561 (arm_increase_location (NBYTES), \
1562 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1563
1564 /* Align output to a power of two. Horrible /bin/as. */
1565 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1566 do \
1567 { \
1568 register int amount = 1 << (POWER); \
1569 extern int arm_text_location; \
1570 \
1571 if (amount == 2) \
1572 fprintf (STREAM, "\t.even\n"); \
1573 else \
1574 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1575 \
1576 if (in_text_section ()) \
1577 arm_text_location = ((arm_text_location + amount - 1) \
1578 & ~(amount - 1)); \
1579 } while (0)
1580
1581 /* Output a common block */
1582 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1583 (fprintf (STREAM, "\t.comm\t"), \
1584 assemble_name ((STREAM), (NAME)), \
1585 fprintf(STREAM, ", %d\t@%d\n", ROUNDED, SIZE))
1586
1587 /* Output a local common block. /bin/as can't do this, so hack a `.space' into
1588 the bss segment. Note that this is *bad* practice. */
1589 #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1590 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1591
1592 /* Output a source line for the debugger. */
1593 /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1594
1595 /* Output a #ident directive. */
1596 #define ASM_OUTPUT_IDENT(STREAM,STRING) \
1597 fprintf (STREAM,"- - - ident %s\n",STRING)
1598
1599 /* The assembler's parentheses characters. */
1600 #define ASM_OPEN_PAREN "("
1601 #define ASM_CLOSE_PAREN ")"
1602
1603 /* Target characters. */
1604 #define TARGET_BELL 007
1605 #define TARGET_BS 010
1606 #define TARGET_TAB 011
1607 #define TARGET_NEWLINE 012
1608 #define TARGET_VT 013
1609 #define TARGET_FF 014
1610 #define TARGET_CR 015
1611 \f
1612 /* Only perform branch elimination (by making instructions conditional) if
1613 we're optimising. Otherwise it's of no use anyway. */
1614 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1615 if (optimize) \
1616 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1617
1618 #ifndef ARM_COMMENT_CHAR
1619 #define ARM_COMMENT_CHAR '@'
1620 #endif
1621
1622 /* Default is for register names not to have a prefix. */
1623 #ifndef ARM_REG_PREFIX
1624 #define ARM_REG_PREFIX ""
1625 #endif
1626
1627 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1628 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1629 /* Output an operand of an instruction. */
1630 #define PRINT_OPERAND(STREAM, X, CODE) \
1631 arm_print_operand (STREAM, X, CODE)
1632
1633 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1634 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1635 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1636 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1637 ? ((~ (HOST_WIDE_INT) 0) \
1638 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1639 : 0))))
1640
1641 /* Output the address of an operand. */
1642 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1643 { \
1644 int is_minus = GET_CODE (X) == MINUS; \
1645 \
1646 if (GET_CODE (X) == REG) \
1647 fprintf (STREAM, "[%s, #0]", reg_names[REGNO (X)]); \
1648 else if (GET_CODE (X) == PLUS || is_minus) \
1649 { \
1650 rtx base = XEXP (X, 0); \
1651 rtx index = XEXP (X, 1); \
1652 char *base_reg_name; \
1653 HOST_WIDE_INT offset = 0; \
1654 if (GET_CODE (base) != REG) \
1655 { \
1656 /* Ensure that BASE is a register (one of them must be). */ \
1657 rtx temp = base; \
1658 base = index; \
1659 index = temp; \
1660 } \
1661 base_reg_name = reg_names[REGNO (base)]; \
1662 switch (GET_CODE (index)) \
1663 { \
1664 case CONST_INT: \
1665 offset = INTVAL (index); \
1666 if (is_minus) \
1667 offset = -offset; \
1668 fprintf (STREAM, "[%s, #%d]", base_reg_name, offset); \
1669 break; \
1670 \
1671 case REG: \
1672 fprintf (STREAM, "[%s, %s%s]", base_reg_name, \
1673 is_minus ? "-" : "", reg_names[REGNO (index)] ); \
1674 break; \
1675 \
1676 case MULT: \
1677 case ASHIFTRT: \
1678 case LSHIFTRT: \
1679 case ASHIFT: \
1680 case ROTATERT: \
1681 { \
1682 fprintf (STREAM, "[%s, %s%s, ", base_reg_name, \
1683 is_minus ? "-" : "", \
1684 reg_names[REGNO (XEXP (index, 0))]); \
1685 arm_print_operand (STREAM, index, 'S'); \
1686 fputs ("]", STREAM); \
1687 break; \
1688 } \
1689 \
1690 default: \
1691 abort(); \
1692 } \
1693 } \
1694 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1695 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1696 { \
1697 extern int output_memory_reference_mode; \
1698 \
1699 if (GET_CODE (XEXP (X, 0)) != REG) \
1700 abort (); \
1701 \
1702 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1703 fprintf (STREAM, "[%s, #%s%d]!", reg_names[REGNO (XEXP (X, 0))],\
1704 GET_CODE (X) == PRE_DEC ? "-" : "", \
1705 GET_MODE_SIZE (output_memory_reference_mode)); \
1706 else \
1707 fprintf (STREAM, "[%s], #%s%d", reg_names[REGNO (XEXP (X, 0))], \
1708 GET_CODE (X) == POST_DEC ? "-" : "", \
1709 GET_MODE_SIZE (output_memory_reference_mode)); \
1710 } \
1711 else output_addr_const(STREAM, X); \
1712 }
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