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Minor formatting changes.
[official-gcc.git] / gcc / config / arm / arm.h
blob8e7b857930cd9f1c580cb71553ed47372d8587e5
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #ifndef __ARM_H__
26 #define __ARM_H__
27
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 /* Configure didn't specify. */
52 #define TARGET_CPU_generic 0x8000
53
54 enum arm_cond_code
55 {
56 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
57 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
58 };
59
60 extern enum arm_cond_code arm_current_cc;
61 extern char * arm_condition_codes[];
62
63 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
64
65 extern int arm_target_label;
66 extern int arm_ccfsm_state;
67 extern struct rtx_def * arm_target_insn;
68 extern int lr_save_eliminated;
69 /* This is needed by the tail-calling peepholes */
70 extern int frame_pointer_needed;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
75
76 \f
77 /* Just in case configure has failed to define anything. */
78 #ifndef TARGET_CPU_DEFAULT
79 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
80 #endif
81
82 /* If the configuration file doesn't specify the cpu, the subtarget may
83 override it. If it doesn't, then default to an ARM6. */
84 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
85 #undef TARGET_CPU_DEFAULT
86 #ifdef SUBTARGET_CPU_DEFAULT
87 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
88 #else
89 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
90 #endif
91 #endif
92
93 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
94 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
95 #else
96 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
97 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
98 #else
99 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
100 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
101 #else
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
104 #else
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
107 #else
108 Unrecognized value in TARGET_CPU_DEFAULT.
109 #endif
110 #endif
111 #endif
112 #endif
113 #endif
114
115 #ifndef CPP_PREDEFINES
116 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
117 #endif
118
119 #define CPP_SPEC "\
120 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
121 %(cpp_endian) %(subtarget_cpp_spec)"
122
123 /* Set the architecture define -- if -march= is set, then it overrides
124 the -mcpu= setting. */
125 #define CPP_CPU_ARCH_SPEC "\
126 %{march=arm2:-D__ARM_ARCH_2__} \
127 %{march=arm250:-D__ARM_ARCH_2__} \
128 %{march=arm3:-D__ARM_ARCH_2__} \
129 %{march=arm6:-D__ARM_ARCH_3__} \
130 %{march=arm600:-D__ARM_ARCH_3__} \
131 %{march=arm610:-D__ARM_ARCH_3__} \
132 %{march=arm7:-D__ARM_ARCH_3__} \
133 %{march=arm700:-D__ARM_ARCH_3__} \
134 %{march=arm710:-D__ARM_ARCH_3__} \
135 %{march=arm720:-D__ARM_ARCH_3__} \
136 %{march=arm7100:-D__ARM_ARCH_3__} \
137 %{march=arm7500:-D__ARM_ARCH_3__} \
138 %{march=arm7500fe:-D__ARM_ARCH_3__} \
139 %{march=arm7m:-D__ARM_ARCH_3M__} \
140 %{march=arm7dm:-D__ARM_ARCH_3M__} \
141 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
142 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
143 %{march=arm8:-D__ARM_ARCH_4__} \
144 %{march=arm810:-D__ARM_ARCH_4__} \
145 %{march=arm9:-D__ARM_ARCH_4T__} \
146 %{march=arm920:-D__ARM_ARCH_4__} \
147 %{march=arm920t:-D__ARM_ARCH_4T__} \
148 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
149 %{march=strongarm:-D__ARM_ARCH_4__} \
150 %{march=strongarm110:-D__ARM_ARCH_4__} \
151 %{march=strongarm1100:-D__ARM_ARCH_4__} \
152 %{march=armv2:-D__ARM_ARCH_2__} \
153 %{march=armv2a:-D__ARM_ARCH_2__} \
154 %{march=armv3:-D__ARM_ARCH_3__} \
155 %{march=armv3m:-D__ARM_ARCH_3M__} \
156 %{march=armv4:-D__ARM_ARCH_4__} \
157 %{march=armv4t:-D__ARM_ARCH_4T__} \
158 %{march=armv5:-D__ARM_ARCH_5__} \
159 %{!march=*: \
160 %{mcpu=arm2:-D__ARM_ARCH_2__} \
161 %{mcpu=arm250:-D__ARM_ARCH_2__} \
162 %{mcpu=arm3:-D__ARM_ARCH_2__} \
163 %{mcpu=arm6:-D__ARM_ARCH_3__} \
164 %{mcpu=arm600:-D__ARM_ARCH_3__} \
165 %{mcpu=arm610:-D__ARM_ARCH_3__} \
166 %{mcpu=arm7:-D__ARM_ARCH_3__} \
167 %{mcpu=arm700:-D__ARM_ARCH_3__} \
168 %{mcpu=arm710:-D__ARM_ARCH_3__} \
169 %{mcpu=arm720:-D__ARM_ARCH_3__} \
170 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
171 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
172 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
173 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
174 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
175 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
176 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
177 %{mcpu=arm8:-D__ARM_ARCH_4__} \
178 %{mcpu=arm810:-D__ARM_ARCH_4__} \
179 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
180 %{mcpu=arm920:-D__ARM_ARCH_4__} \
181 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
182 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
183 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
184 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
185 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
186 %{!mcpu*:%(cpp_cpu_arch_default)}} \
187 "
188
189 /* Define __APCS_26__ if the PC also contains the PSR */
190 #define CPP_APCS_PC_SPEC "\
191 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
192 -D__APCS_32__} \
193 %{mapcs-26:-D__APCS_26__} \
194 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
195 "
196
197 #ifndef CPP_APCS_PC_DEFAULT_SPEC
198 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
199 #endif
200
201 #define CPP_FLOAT_SPEC "\
202 %{msoft-float:\
203 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
204 -D__SOFTFP__} \
205 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
206 "
207
208 /* Default is hard float, which doesn't define anything */
209 #define CPP_FLOAT_DEFAULT_SPEC ""
210
211 #define CPP_ENDIAN_SPEC "\
212 %{mbig-endian: \
213 %{mlittle-endian: \
214 %e-mbig-endian and -mlittle-endian may not be used together} \
215 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
216 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
217 "
218
219 /* Default is little endian, which doesn't define anything. */
220 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__"
221
222 #define CC1_SPEC ""
223
224 /* This macro defines names of additional specifications to put in the specs
225 that can be used in various specifications like CC1_SPEC. Its definition
226 is an initializer with a subgrouping for each command option.
227
228 Each subgrouping contains a string constant, that defines the
229 specification name, and a string constant that used by the GNU CC driver
230 program.
231
232 Do not define this macro if it does not need to do anything. */
233 #define EXTRA_SPECS \
234 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
235 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
236 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
237 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
238 { "cpp_float", CPP_FLOAT_SPEC }, \
239 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
240 { "cpp_endian", CPP_ENDIAN_SPEC }, \
241 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
242 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
243 SUBTARGET_EXTRA_SPECS
244
245 #ifndef SUBTARGET_EXTRA_SPECS
246 #define SUBTARGET_EXTRA_SPECS
247 #endif
248
249 #ifndef SUBTARGET_CPP_SPEC
250 #define SUBTARGET_CPP_SPEC ""
251 #endif
252
253 #ifndef SUBTARGET_EXTRA_ASM_SPEC
254 #define SUBTARGET_EXTRA_ASM_SPEC
255 #endif
256
257 #ifndef ASM_SPEC
258 #define ASM_SPEC "\
259 %{mbig-endian:-EB} \
260 %{mcpu=*:-m%*} \
261 %{march=*:-m%*} \
262 %{mapcs-*:-mapcs-%*} \
263 %{matpcs:-matpcs} \
264 %{mapcs-float:-mfloat} \
265 %{msoft-float:-mno-fpu} \
266 %{mthumb-interwork:-mthumb-interwork} \
267 " SUBTARGET_EXTRA_ASM_SPEC
268 #endif
269 \f
270 /* Run-time Target Specification. */
271 #ifndef TARGET_VERSION
272 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
273 #endif
274
275 /* Nonzero if the function prologue (and epilogue) should obey
276 the ARM Procedure Call Standard. */
277 #define ARM_FLAG_APCS_FRAME (1 << 0)
278
279 /* Nonzero if the function prologue should output the function name to enable
280 the post mortem debugger to print a backtrace (very useful on RISCOS,
281 unused on RISCiX). Specifying this flag also enables
282 -fno-omit-frame-pointer.
283 XXX Must still be implemented in the prologue. */
284 #define ARM_FLAG_POKE (1 << 1)
285
286 /* Nonzero if floating point instructions are emulated by the FPE, in which
287 case instruction scheduling becomes very uninteresting. */
288 #define ARM_FLAG_FPE (1 << 2)
289
290 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
291 that assume restoration of the condition flags when returning from a
292 branch and link (ie a function). */
293 #define ARM_FLAG_APCS_32 (1 << 3)
294
295 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
296
297 /* Nonzero if stack checking should be performed on entry to each function
298 which allocates temporary variables on the stack. */
299 #define ARM_FLAG_APCS_STACK (1 << 4)
300
301 /* Nonzero if floating point parameters should be passed to functions in
302 floating point registers. */
303 #define ARM_FLAG_APCS_FLOAT (1 << 5)
304
305 /* Nonzero if re-entrant, position independent code should be generated.
306 This is equivalent to -fpic. */
307 #define ARM_FLAG_APCS_REENT (1 << 6)
308
309 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
310 be loaded using either LDRH or LDRB instructions. */
311 #define ARM_FLAG_MMU_TRAPS (1 << 7)
312
313 /* Nonzero if all floating point instructions are missing (and there is no
314 emulator either). Generate function calls for all ops in this case. */
315 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
316
317 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
318 #define ARM_FLAG_BIG_END (1 << 9)
319
320 /* Nonzero if we should compile for Thumb interworking. */
321 #define ARM_FLAG_INTERWORK (1 << 10)
322
323 /* Nonzero if we should have little-endian words even when compiling for
324 big-endian (for backwards compatibility with older versions of GCC). */
325 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
326
327 /* Nonzero if we need to protect the prolog from scheduling */
328 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
329
330 /* Nonzero if a call to abort should be generated if a noreturn
331 function tries to return. */
332 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
333
334 /* Nonzero if function prologues should not load the PIC register. */
335 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
336
337 /* Nonzero if all call instructions should be indirect. */
338 #define ARM_FLAG_LONG_CALLS (1 << 15)
339
340 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
341 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
342 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
343 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
344 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
345 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
346 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
347 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
348 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
349 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
350 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
351 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
352 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
353 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
354 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
355 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
356 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
357
358 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
359 Bit 31 is reserved. See riscix.h. */
360 #ifndef SUBTARGET_SWITCHES
361 #define SUBTARGET_SWITCHES
362 #endif
363
364 #define TARGET_SWITCHES \
365 { \
366 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
367 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
368 "Generate APCS conformant stack frames" }, \
369 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
370 {"poke-function-name", ARM_FLAG_POKE, \
371 "Store function names in object code" }, \
372 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
373 {"fpe", ARM_FLAG_FPE, "" }, \
374 {"apcs-32", ARM_FLAG_APCS_32, \
375 "Use the 32bit version of the APCS" }, \
376 {"apcs-26", -ARM_FLAG_APCS_32, \
377 "Use the 26bit version of the APCS" }, \
378 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
379 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
380 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
381 "Pass FP arguments in FP registers" }, \
382 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
383 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
384 "Generate re-entrant, PIC code" }, \
385 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
386 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
387 "The MMU will trap on unaligned accesses" }, \
388 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
389 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
390 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
391 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
392 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
393 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
394 "Use library calls to perform FP operations" }, \
395 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
396 "Use hardware floating point instructions" }, \
397 {"big-endian", ARM_FLAG_BIG_END, \
398 "Assume target CPU is configured as big endian" }, \
399 {"little-endian", -ARM_FLAG_BIG_END, \
400 "Assume target CPU is configured as little endian" }, \
401 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
402 "Assume big endian bytes, little endian words" }, \
403 {"thumb-interwork", ARM_FLAG_INTERWORK, \
404 "Support calls between THUMB and ARM instructions sets" }, \
405 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
406 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
407 "Generate a call to abort if a noreturn function returns"},\
408 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
409 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
410 "Do not move instructions into a function's prologue" }, \
411 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
412 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
413 "Do not load the PIC register in function prologues" }, \
414 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
415 {"long-calls", ARM_FLAG_LONG_CALLS, \
416 "Generate call insns as indirect calls, if necessary"}, \
417 {"no-long-calls", -ARM_FLAG_LONG_CALLS, ""}, \
418 SUBTARGET_SWITCHES \
419 {"", TARGET_DEFAULT, "" } \
420 }
421
422 #define TARGET_OPTIONS \
423 { \
424 {"cpu=", & arm_select[0].string, \
425 "Specify the name of the target CPU" }, \
426 {"arch=", & arm_select[1].string, \
427 "Specify the name of the target architecture" }, \
428 {"tune=", & arm_select[2].string, "" }, \
429 {"fpe=", & target_fp_name, "" }, \
430 {"fp=", & target_fp_name, \
431 "Specify the version of the floating point emulator" }, \
432 { "structure-size-boundary=", & structure_size_string, \
433 "Specify the minimum bit alignment of structures" }, \
434 { "pic-register=", & arm_pic_register_string, \
435 "Specify the register to be used for PIC addressing" } \
436 }
437
438 struct arm_cpu_select
439 {
440 const char * string;
441 const char * name;
442 const struct processors * processors;
443 };
444
445 /* This is a magic array. If the user specifies a command line switch
446 which matches one of the entries in TARGET_OPTIONS then the corresponding
447 string pointer will be set to the value specified by the user. */
448 extern struct arm_cpu_select arm_select[];
449
450 enum prog_mode_type
451 {
452 prog_mode26,
453 prog_mode32
454 };
455
456 /* Recast the program mode class to be the prog_mode attribute */
457 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
458
459 extern enum prog_mode_type arm_prgmode;
460
461 /* What sort of floating point unit do we have? Hardware or software.
462 If software, is it issue 2 or issue 3? */
463 enum floating_point_type
464 {
465 FP_HARD,
466 FP_SOFT2,
467 FP_SOFT3
468 };
469
470 /* Recast the floating point class to be the floating point attribute. */
471 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
472
473 /* What type of floating point to tune for */
474 extern enum floating_point_type arm_fpu;
475
476 /* What type of floating point instructions are available */
477 extern enum floating_point_type arm_fpu_arch;
478
479 /* Default floating point architecture. Override in sub-target if
480 necessary. */
481 #define FP_DEFAULT FP_SOFT2
482
483 /* Nonzero if the processor has a fast multiply insn, and one that does
484 a 64-bit multiply of two 32-bit values. */
485 extern int arm_fast_multiply;
486
487 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
488 extern int arm_arch4;
489
490 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
491 extern int arm_arch5;
492
493 /* Nonzero if this chip can benefit from load scheduling. */
494 extern int arm_ld_sched;
495
496 /* Nonzero if this chip is a StrongARM. */
497 extern int arm_is_strong;
498
499 /* Nonzero if this chip is a an ARM6 or an ARM7. */
500 extern int arm_is_6_or_7;
501
502 #ifndef TARGET_DEFAULT
503 #define TARGET_DEFAULT 0
504 #endif
505
506 /* The frame pointer register used in gcc has nothing to do with debugging;
507 that is controlled by the APCS-FRAME option. */
508 /* Not fully implemented yet. */
509 /* #define CAN_DEBUG_WITHOUT_FP 1 */
510
511 #define TARGET_MEM_FUNCTIONS 1
512
513 #define OVERRIDE_OPTIONS arm_override_options ()
514
515 /* Nonzero if PIC code requires explicit qualifiers to generate
516 PLT and GOT relocs rather than the assembler doing so implicitly.
517 Subtargets can override these if required. */
518 #ifndef NEED_GOT_RELOC
519 #define NEED_GOT_RELOC 0
520 #endif
521 #ifndef NEED_PLT_RELOC
522 #define NEED_PLT_RELOC 0
523 #endif
524
525 /* Nonzero if we need to refer to the GOT with a PC-relative
526 offset. In other words, generate
527
528 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
529
530 rather than
531
532 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
533
534 The default is true, which matches NetBSD. Subtargets can
535 override this if required. */
536 #ifndef GOT_PCREL
537 #define GOT_PCREL 1
538 #endif
539 \f
540 /* Target machine storage Layout. */
541
542
543 /* Define this macro if it is advisable to hold scalars in registers
544 in a wider mode than that declared by the program. In such cases,
545 the value is constrained to be within the bounds of the declared
546 type, but kept valid in the wider mode. The signedness of the
547 extension may differ from that of the type. */
548
549 /* It is far faster to zero extend chars than to sign extend them */
550
551 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
552 if (GET_MODE_CLASS (MODE) == MODE_INT \
553 && GET_MODE_SIZE (MODE) < 4) \
554 { \
555 if (MODE == QImode) \
556 UNSIGNEDP = 1; \
557 else if (MODE == HImode) \
558 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
559 (MODE) = SImode; \
560 }
561
562 /* Define this macro if the promotion described by `PROMOTE_MODE'
563 should also be done for outgoing function arguments. */
564 /* This is required to ensure that push insns always push a word. */
565 #define PROMOTE_FUNCTION_ARGS
566
567 /* Define for XFmode extended real floating point support.
568 This will automatically cause REAL_ARITHMETIC to be defined. */
569 /* For the ARM:
570 I think I have added all the code to make this work. Unfortunately,
571 early releases of the floating point emulation code on RISCiX used a
572 different format for extended precision numbers. On my RISCiX box there
573 is a bug somewhere which causes the machine to lock up when running enquire
574 with long doubles. There is the additional aspect that Norcroft C
575 treats long doubles as doubles and we ought to remain compatible.
576 Perhaps someone with an FPA coprocessor and not running RISCiX would like
577 to try this someday. */
578 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
579
580 /* Disable XFmode patterns in md file */
581 #define ENABLE_XF_PATTERNS 0
582
583 /* Define if you don't want extended real, but do want to use the
584 software floating point emulator for REAL_ARITHMETIC and
585 decimal <-> binary conversion. */
586 /* See comment above */
587 #define REAL_ARITHMETIC
588
589 /* Define this if most significant bit is lowest numbered
590 in instructions that operate on numbered bit-fields. */
591 #define BITS_BIG_ENDIAN 0
592
593 /* Define this if most significant byte of a word is the lowest numbered.
594 Most ARM processors are run in little endian mode, so that is the default.
595 If you want to have it run-time selectable, change the definition in a
596 cover file to be TARGET_BIG_ENDIAN. */
597 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
598
599 /* Define this if most significant word of a multiword number is the lowest
600 numbered.
601 This is always false, even when in big-endian mode. */
602 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
603
604 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
605 on processor pre-defineds when compiling libgcc2.c. */
606 #if defined(__ARMEB__) && !defined(__ARMWEL__)
607 #define LIBGCC2_WORDS_BIG_ENDIAN 1
608 #else
609 #define LIBGCC2_WORDS_BIG_ENDIAN 0
610 #endif
611
612 /* Define this if most significant word of doubles is the lowest numbered.
613 This is always true, even when in little-endian mode. */
614 #define FLOAT_WORDS_BIG_ENDIAN 1
615
616 /* Number of bits in an addressable storage unit */
617 #define BITS_PER_UNIT 8
618
619 #define BITS_PER_WORD 32
620
621 #define UNITS_PER_WORD 4
622
623 #define POINTER_SIZE 32
624
625 #define PARM_BOUNDARY 32
626
627 #define STACK_BOUNDARY 32
628
629 #define FUNCTION_BOUNDARY 32
630
631 #define EMPTY_FIELD_BOUNDARY 32
632
633 #define BIGGEST_ALIGNMENT 32
634
635 /* Make strings word-aligned so strcpy from constants will be faster. */
636 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
637 (TREE_CODE (EXP) == STRING_CST \
638 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
639
640 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
641 value set in previous versions of this toolchain was 8, which produces more
642 compact structures. The command line option -mstructure_size_boundary=<n>
643 can be used to change this value. For compatability with the ARM SDK
644 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
645 0020D) page 2-20 says "Structures are aligned on word boundaries". */
646 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
647 extern int arm_structure_size_boundary;
648
649 /* This is the value used to initialise arm_structure_size_boundary. If a
650 particular arm target wants to change the default value it should change
651 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
652 for an example of this. */
653 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
654 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
655 #endif
656
657 /* Used when parsing command line option -mstructure_size_boundary. */
658 extern const char * structure_size_string;
659
660 /* Non-zero if move instructions will actually fail to work
661 when given unaligned data. */
662 #define STRICT_ALIGNMENT 1
663
664 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
665
666 \f
667 /* Standard register usage. */
668
669 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
670 (S - saved over call).
671
672 r0 * argument word/integer result
673 r1-r3 argument word
674
675 r4-r8 S register variable
676 r9 S (rfp) register variable (real frame pointer)
677
678 r10 F S (sl) stack limit (used by -mapcs-stack-check)
679 r11 F S (fp) argument pointer
680 r12 (ip) temp workspace
681 r13 F S (sp) lower end of current stack frame
682 r14 (lr) link address/workspace
683 r15 F (pc) program counter
684
685 f0 floating point result
686 f1-f3 floating point scratch
687
688 f4-f7 S floating point variable
689
690 cc This is NOT a real register, but is used internally
691 to represent things that use or set the condition
692 codes.
693 sfp This isn't either. It is used during rtl generation
694 since the offset between the frame pointer and the
695 auto's isn't known until after register allocation.
696 afp Nor this, we only need this because of non-local
697 goto. Without it fp appears to be used and the
698 elimination code won't get rid of sfp. It tracks
699 fp exactly at all times.
700
701 *: See CONDITIONAL_REGISTER_USAGE */
702
703 /* The stack backtrace structure is as follows:
704 fp points to here: | save code pointer | [fp]
705 | return link value | [fp, #-4]
706 | return sp value | [fp, #-8]
707 | return fp value | [fp, #-12]
708 [| saved r10 value |]
709 [| saved r9 value |]
710 [| saved r8 value |]
711 [| saved r7 value |]
712 [| saved r6 value |]
713 [| saved r5 value |]
714 [| saved r4 value |]
715 [| saved r3 value |]
716 [| saved r2 value |]
717 [| saved r1 value |]
718 [| saved r0 value |]
719 [| saved f7 value |] three words
720 [| saved f6 value |] three words
721 [| saved f5 value |] three words
722 [| saved f4 value |] three words
723 r0-r3 are not normally saved in a C function. */
724
725 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
726 #define FIRST_PSEUDO_REGISTER 27
727
728 /* 1 for registers that have pervasive standard uses
729 and are not available for the register allocator. */
730 #define FIXED_REGISTERS \
731 { \
732 0,0,0,0,0,0,0,0, \
733 0,0,0,1,0,1,0,1, \
734 0,0,0,0,0,0,0,0, \
735 1,1,1 \
736 }
737
738 /* 1 for registers not available across function calls.
739 These must include the FIXED_REGISTERS and also any
740 registers that can be used without being saved.
741 The latter must include the registers where values are returned
742 and the register where structure-value addresses are passed.
743 Aside from that, you can include as many other registers as you like.
744 The CC is not preserved over function calls on the ARM 6, so it is
745 easier to assume this for all. SFP is preserved, since FP is. */
746 #define CALL_USED_REGISTERS \
747 { \
748 1,1,1,1,0,0,0,0, \
749 0,0,0,1,1,1,1,1, \
750 1,1,1,1,0,0,0,0, \
751 1,1,1 \
752 }
753
754 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
755 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
756 #endif
757
758 #define CONDITIONAL_REGISTER_USAGE \
759 { \
760 if (TARGET_SOFT_FLOAT) \
761 { \
762 int regno; \
763 for (regno = 16; regno < 24; ++regno) \
764 fixed_regs[regno] = call_used_regs[regno] = 1; \
765 } \
766 if (flag_pic) \
767 { \
768 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
769 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
770 } \
771 else if (TARGET_APCS_STACK) \
772 { \
773 fixed_regs[10] = 1; \
774 call_used_regs[10] = 1; \
775 } \
776 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
777 }
778
779 /* These are a couple of extensions to the formats accecpted
780 by asm_fprintf:
781 %@ prints out ASM_COMMENT_START
782 %r prints out REGISTER_PREFIX reg_names[arg] */
783 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
784 case '@': \
785 fputs (ASM_COMMENT_START, FILE); \
786 break; \
787 \
788 case 'r': \
789 fputs (REGISTER_PREFIX, FILE); \
790 fputs (reg_names [va_arg (ARGS, int)], FILE); \
791 break;
792
793 /* Convert fron bytes to ints. */
794 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
795
796 /* The number of (integer) registers required to hold a quantity of type MODE. */
797 #define NUM_REGS(MODE) \
798 NUM_INTS (GET_MODE_SIZE (MODE))
799
800 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
801 #define NUM_REGS2(MODE, TYPE) \
802 NUM_INTS ((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
803
804 /* The number of (integer) argument register available. */
805 #define NUM_ARG_REGS 4
806
807 /* Return the regiser number of the N'th (integer) argument. */
808 #define ARG_REGISTER(N) (N - 1)
809
810 /* The number of the last argument register. */
811 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
812
813 /* Return number of consecutive hard regs needed starting at reg REGNO
814 to hold something of mode MODE.
815 This is ordinarily the length in words of a value of mode MODE
816 but can be less for certain modes in special long registers.
817
818 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
819 mode. */
820 #define HARD_REGNO_NREGS(REGNO, MODE) \
821 (( REGNO >= 16 \
822 && REGNO != FRAME_POINTER_REGNUM \
823 && REGNO != ARG_POINTER_REGNUM) \
824 ? 1 : NUM_REGS (MODE))
825
826 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
827 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
828 regs holding FP. */
829 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
830 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
831 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
832 || REGNO == ARG_POINTER_REGNUM \
833 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
834
835 /* Value is 1 if it is a good idea to tie two pseudo registers
836 when one has mode MODE1 and one has mode MODE2.
837 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
838 for any hard reg, then this must be 0 for correct output. */
839 #define MODES_TIEABLE_P(MODE1, MODE2) \
840 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
841
842 /* Specify the registers used for certain standard purposes.
843 The values of these macros are register numbers. */
844
845 /* Define this if the program counter is overloaded on a register. */
846 #define PC_REGNUM 15
847
848 /* Register to use for pushing function arguments. */
849 #define STACK_POINTER_REGNUM 13
850 #define SP_REGNUM STACK_POINTER_REGNUM
851
852 /* Base register for access to local variables of the function. */
853 #define FRAME_POINTER_REGNUM 25
854
855 /* Define this to be where the real frame pointer is if it is not possible to
856 work out the offset between the frame pointer and the automatic variables
857 until after register allocation has taken place. FRAME_POINTER_REGNUM
858 should point to a special register that we will make sure is eliminated. */
859 #define HARD_FRAME_POINTER_REGNUM 11
860 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
861
862 /* Register which holds return address from a subroutine call. */
863 #define LR_REGNUM 14
864
865 /* Scratch register - used in all kinds of places, eg trampolines. */
866 #define IP_REGNUM 12
867
868 /* Value should be nonzero if functions must have frame pointers.
869 Zero means the frame pointer need not be set up (and parms may be accessed
870 via the stack pointer) in functions that seem suitable.
871 If we have to have a frame pointer we might as well make use of it.
872 APCS says that the frame pointer does not need to be pushed in leaf
873 functions, or simple tail call functions. */
874 #define FRAME_POINTER_REQUIRED \
875 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
876
877 /* Base register for access to arguments of the function. */
878 #define ARG_POINTER_REGNUM 26
879
880 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
881 as an invisible last argument (possible since varargs don't exist in
882 Pascal), so the following is not true. */
883 #define STATIC_CHAIN_REGNUM 8
884
885 /* Register in which address to store a structure value
886 is passed to a function. */
887 #define STRUCT_VALUE_REGNUM 0
888
889 /* Internal, so that we don't need to refer to a raw number */
890 #define CC_REGNUM 24
891
892 /* The order in which register should be allocated. It is good to use ip
893 since no saving is required (though calls clobber it) and it never contains
894 function parameters. It is quite good to use lr since other calls may
895 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
896 least likely to contain a function parameter; in addition results are
897 returned in r0.
898 */
899 #define REG_ALLOC_ORDER \
900 { \
901 3, 2, 1, 0, 12, 14, 4, 5, \
902 6, 7, 8, 10, 9, 11, 13, 15, \
903 16, 17, 18, 19, 20, 21, 22, 23, \
904 24, 25, 26 \
905 }
906 \f
907 /* Register and constant classes. */
908
909 /* Register classes: all ARM regs or all FPU regs---simple! */
910 enum reg_class
911 {
912 NO_REGS,
913 FPU_REGS,
914 GENERAL_REGS,
915 ALL_REGS,
916 LIM_REG_CLASSES
917 };
918
919 #define N_REG_CLASSES (int) LIM_REG_CLASSES
920
921 /* Give names of register classes as strings for dump file. */
922 #define REG_CLASS_NAMES \
923 { \
924 "NO_REGS", \
925 "FPU_REGS", \
926 "GENERAL_REGS", \
927 "ALL_REGS", \
928 }
929
930 /* Define which registers fit in which classes.
931 This is an initializer for a vector of HARD_REG_SET
932 of length N_REG_CLASSES. */
933 #define REG_CLASS_CONTENTS \
934 { \
935 { 0x0000000 }, /* NO_REGS */ \
936 { 0x0FF0000 }, /* FPU_REGS */ \
937 { 0x200FFFF }, /* GENERAL_REGS */ \
938 { 0x2FFFFFF } /* ALL_REGS */ \
939 }
940
941 /* The same information, inverted:
942 Return the class number of the smallest class containing
943 reg number REGNO. This could be a conditional expression
944 or could index an array. */
945 #define REGNO_REG_CLASS(REGNO) \
946 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
947 || REGNO == ARG_POINTER_REGNUM) \
948 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
949 ? NO_REGS : FPU_REGS)
950
951 /* The class value for index registers, and the one for base regs. */
952 #define INDEX_REG_CLASS GENERAL_REGS
953 #define BASE_REG_CLASS GENERAL_REGS
954
955 /* Get reg_class from a letter such as appears in the machine description.
956 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
957 #define REG_CLASS_FROM_LETTER(C) \
958 ((C)=='f' ? FPU_REGS : NO_REGS)
959
960 /* The letters I, J, K, L and M in a register constraint string
961 can be used to stand for particular ranges of immediate operands.
962 This macro defines what the ranges are.
963 C is the letter, and VALUE is a constant value.
964 Return 1 if VALUE is in the range specified by C.
965 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
966 J: valid indexing constants.
967 K: ~value ok in rhs argument of data operand.
968 L: -value ok in rhs argument of data operand.
969 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
970 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
971 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
972 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
973 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
974 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
975 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
976 || (((VALUE) & ((VALUE) - 1)) == 0)) \
977 : 0)
978
979 /* For the ARM, `Q' means that this is a memory operand that is just
980 an offset from a register.
981 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
982 address. This means that the symbol is in the text segment and can be
983 accessed without using a load. */
984
985 #define EXTRA_CONSTRAINT(OP, C) \
986 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
987 : (C) == 'R' ? (GET_CODE (OP) == MEM \
988 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
989 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
990 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
991 : 0)
992
993 /* Constant letter 'G' for the FPU immediate constants.
994 'H' means the same constant negated. */
995 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
996 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
997 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
998
999 /* Given an rtx X being reloaded into a reg required to be
1000 in class CLASS, return the class of reg to actually use.
1001 In general this is just CLASS; but on some machines
1002 in some cases it is preferable to use a more restrictive class. */
1003 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
1004
1005 /* Return the register class of a scratch register needed to copy IN into
1006 or out of a register in CLASS in MODE. If it can be done directly,
1007 NO_REGS is returned. */
1008 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1009 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1010 ? GENERAL_REGS : NO_REGS)
1011
1012 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1013 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1014 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1015 && (GET_CODE (X) == MEM \
1016 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1017 && true_regnum (X) == -1))) \
1018 ? GENERAL_REGS : NO_REGS)
1019
1020 /* Try a machine-dependent way of reloading an illegitimate address
1021 operand. If we find one, push the reload and jump to WIN. This
1022 macro is used in only one place: `find_reloads_address' in reload.c.
1023
1024 For the ARM, we wish to handle large displacements off a base
1025 register by splitting the addend across a MOV and the mem insn.
1026 This can cut the number of reloads needed. */
1027 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1028 do \
1029 { \
1030 if (GET_CODE (X) == PLUS \
1031 && GET_CODE (XEXP (X, 0)) == REG \
1032 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1033 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1034 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1035 { \
1036 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1037 HOST_WIDE_INT low, high; \
1038 \
1039 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1040 low = ((val & 0xf) ^ 0x8) - 0x8; \
1041 else if (MODE == SImode \
1042 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1043 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1044 /* Need to be careful, -4096 is not a valid offset */ \
1045 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1046 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1047 /* Need to be careful, -256 is not a valid offset */ \
1048 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1049 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1050 && TARGET_HARD_FLOAT) \
1051 /* Need to be careful, -1024 is not a valid offset */ \
1052 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1053 else \
1054 break; \
1055 \
1056 high = ((((val - low) & 0xffffffffUL) ^ 0x80000000UL) - 0x80000000UL);\
1057 /* Check for overflow or zero */ \
1058 if (low == 0 || high == 0 || (high + low != val)) \
1059 break; \
1060 \
1061 /* Reload the high part into a base reg; leave the low part \
1062 in the mem. */ \
1063 X = gen_rtx_PLUS (GET_MODE (X), \
1064 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1065 GEN_INT (high)), \
1066 GEN_INT (low)); \
1067 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1068 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1069 OPNUM, TYPE); \
1070 goto WIN; \
1071 } \
1072 } \
1073 while (0)
1074
1075 /* Return the maximum number of consecutive registers
1076 needed to represent mode MODE in a register of class CLASS.
1077 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1078 #define CLASS_MAX_NREGS(CLASS, MODE) \
1079 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1080
1081 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1082 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1083 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
1084 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
1085 ? 20 : 2)
1086 \f
1087 /* Stack layout; function entry, exit and calling. */
1088
1089 /* Define this if pushing a word on the stack
1090 makes the stack pointer a smaller address. */
1091 #define STACK_GROWS_DOWNWARD 1
1092
1093 /* Define this if the nominal address of the stack frame
1094 is at the high-address end of the local variables;
1095 that is, each additional local variable allocated
1096 goes at a more negative offset in the frame. */
1097 #define FRAME_GROWS_DOWNWARD 1
1098
1099 /* Offset within stack frame to start allocating local variables at.
1100 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1101 first local allocated. Otherwise, it is the offset to the BEGINNING
1102 of the first local allocated. */
1103 #define STARTING_FRAME_OFFSET 0
1104
1105 /* If we generate an insn to push BYTES bytes,
1106 this says how many the stack pointer really advances by. */
1107 /* The push insns do not do this rounding implicitly. So don't define this. */
1108 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1109
1110 /* Define this if the maximum size of all the outgoing args is to be
1111 accumulated and pushed during the prologue. The amount can be
1112 found in the variable current_function_outgoing_args_size. */
1113 #define ACCUMULATE_OUTGOING_ARGS 1
1114
1115 /* Offset of first parameter from the argument pointer register value. */
1116 #define FIRST_PARM_OFFSET(FNDECL) 4
1117
1118 /* Value is the number of byte of arguments automatically
1119 popped when returning from a subroutine call.
1120 FUNDECL is the declaration node of the function (as a tree),
1121 FUNTYPE is the data type of the function (as a tree),
1122 or for a library call it is an identifier node for the subroutine name.
1123 SIZE is the number of bytes of arguments passed on the stack.
1124
1125 On the ARM, the caller does not pop any of its arguments that were passed
1126 on the stack. */
1127 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1128
1129 /* Define how to find the value returned by a library function
1130 assuming the value has mode MODE. */
1131 #define LIBCALL_VALUE(MODE) \
1132 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1133 ? gen_rtx_REG (MODE, 16) \
1134 : gen_rtx_REG (MODE, 0))
1135
1136 /* Define how to find the value returned by a function.
1137 VALTYPE is the data type of the value (as a tree).
1138 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1139 otherwise, FUNC is 0. */
1140 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1141 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1142
1143 /* 1 if N is a possible register number for a function value.
1144 On the ARM, only r0 and f0 can return results. */
1145 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1146 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT))
1147
1148 /* How large values are returned */
1149 /* A C expression which can inhibit the returning of certain function values
1150 in registers, based on the type of value. */
1151 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1152
1153 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1154 values must be in memory. On the ARM, they need only do so if larger
1155 than a word, or if they contain elements offset from zero in the struct. */
1156 #define DEFAULT_PCC_STRUCT_RETURN 0
1157
1158 /* A C type for declaring a variable that is used as the first argument of
1159 `FUNCTION_ARG' and other related values. For some target machines, the
1160 type `int' suffices and can hold the number of bytes of argument so far. */
1161 typedef struct
1162 {
1163 /* This is the number of argument registers scanned so far. */
1164 int nregs;
1165 /* instructions on how to process this call. */
1166 int call_cookie;
1167 }
1168 CUMULATIVE_ARGS;
1169
1170 /* Flags for the call_cookie field of CUMULATIVE_ARGS. */
1171 #define CALL_NORMAL 0 /* No special processing. */
1172 #define CALL_LONG 1 /* Always call indirect. */
1173 #define CALL_SHORT 2 /* Never call indirect. */
1174
1175 /* Define where to put the arguments to a function.
1176 Value is zero to push the argument on the stack,
1177 or a hard register in which to store the argument.
1178
1179 MODE is the argument's machine mode.
1180 TYPE is the data type of the argument (as a tree).
1181 This is null for libcalls where that information may
1182 not be available.
1183 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1184 the preceding args and about the function being called.
1185 NAMED is nonzero if this argument is a named parameter
1186 (otherwise it is an extra parameter matching an ellipsis).
1187
1188 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1189 other arguments are passed on the stack. If (NAMED == 0) (which happens
1190 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1191 passed in the stack (function_prologue will indeed make it pass in the
1192 stack if necessary). */
1193 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1194 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1195
1196 /* For an arg passed partly in registers and partly in memory,
1197 this is the number of registers used.
1198 For args passed entirely in registers or entirely in memory, zero. */
1199 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1200 ( NUM_ARG_REGS > (CUM).nregs \
1201 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1202 ? NUM_ARG_REGS - (CUM).nregs : 0)
1203
1204 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1205 for a call to a function whose data type is FNTYPE.
1206 For a library call, FNTYPE is 0.
1207 On the ARM, the offset starts at 0. */
1208 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1209 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1210
1211 /* Update the data in CUM to advance over an argument
1212 of mode MODE and data type TYPE.
1213 (TYPE is null for libcalls where that information may not be available.) */
1214 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1215 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1216
1217 /* 1 if N is a possible register number for function argument passing.
1218 On the ARM, r0-r3 are used to pass args. */
1219 #define FUNCTION_ARG_REGNO_P(REGNO) \
1220 ((REGNO) >= 0 && (REGNO) <= 3)
1221
1222 /* Perform any actions needed for a function that is receiving a variable
1223 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1224 of the current parameter. PRETEND_SIZE is a variable that should be set to
1225 the amount of stack that must be pushed by the prolog to pretend that our
1226 caller pushed it.
1227
1228 Normally, this macro will push all remaining incoming registers on the
1229 stack and set PRETEND_SIZE to the length of the registers pushed.
1230
1231 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1232 named arg and all anonymous args onto the stack.
1233 XXX I know the prologue shouldn't be pushing registers, but it is faster
1234 that way. */
1235 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1236 { \
1237 extern int current_function_anonymous_args; \
1238 current_function_anonymous_args = 1; \
1239 if ((CUM).nregs < NUM_ARG_REGS) \
1240 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1241 }
1242
1243 /* Generate assembly output for the start of a function. */
1244 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1245 output_func_prologue ((STREAM), (SIZE))
1246
1247 /* If your target environment doesn't prefix user functions with an
1248 underscore, you may wish to re-define this to prevent any conflicts.
1249 e.g. AOF may prefix mcount with an underscore. */
1250 #ifndef ARM_MCOUNT_NAME
1251 #define ARM_MCOUNT_NAME "*mcount"
1252 #endif
1253
1254 /* Call the function profiler with a given profile label. The Acorn
1255 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1256 On the ARM the full profile code will look like:
1257 .data
1258 LP1
1259 .word 0
1260 .text
1261 mov ip, lr
1262 bl mcount
1263 .word LP1
1264
1265 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1266 will output the .text section.
1267
1268 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1269 ``prof'' doesn't seem to mind about this! */
1270 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1271 { \
1272 char temp[20]; \
1273 rtx sym; \
1274 \
1275 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1276 IP_REGNUM, LR_REGNUM); \
1277 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1278 fputc ('\n', STREAM); \
1279 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1280 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1281 ASM_OUTPUT_INT (STREAM, sym); \
1282 }
1283
1284 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1285 the stack pointer does not matter. The value is tested only in
1286 functions that have frame pointers.
1287 No definition is equivalent to always zero.
1288
1289 On the ARM, the function epilogue recovers the stack pointer from the
1290 frame. */
1291 #define EXIT_IGNORE_STACK 1
1292
1293 /* Generate the assembly code for function exit. */
1294 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1295 output_func_epilogue (SIZE)
1296
1297 /* Determine if the epilogue should be output as RTL.
1298 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1299 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1300
1301 /* Definitions for register eliminations.
1302
1303 This is an array of structures. Each structure initializes one pair
1304 of eliminable registers. The "from" register number is given first,
1305 followed by "to". Eliminations of the same "from" register are listed
1306 in order of preference.
1307
1308 We have two registers that can be eliminated on the ARM. First, the
1309 arg pointer register can often be eliminated in favor of the stack
1310 pointer register. Secondly, the pseudo frame pointer register can always
1311 be eliminated; it is replaced with either the stack or the real frame
1312 pointer. */
1313
1314 #define ELIMINABLE_REGS \
1315 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1316 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
1317 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1318 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
1319
1320 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1321 Frame pointer elimination is automatically handled.
1322
1323 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1324 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1325 pointer, we must eliminate FRAME_POINTER_REGNUM into
1326 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1327 #define CAN_ELIMINATE(FROM, TO) \
1328 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1329
1330 /* Define the offset between two registers, one to be eliminated, and the other
1331 its replacement, at the start of a routine. */
1332 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1333 { \
1334 int volatile_func = arm_volatile_func (); \
1335 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1336 (OFFSET) = 0; \
1337 else if ((FROM) == FRAME_POINTER_REGNUM \
1338 && (TO) == STACK_POINTER_REGNUM) \
1339 (OFFSET) = current_function_outgoing_args_size \
1340 + ((get_frame_size () + 3) & ~3); \
1341 else \
1342 { \
1343 int regno; \
1344 int offset = 12; \
1345 int saved_hard_reg = 0; \
1346 \
1347 if (! volatile_func) \
1348 { \
1349 for (regno = 0; regno <= 10; regno++) \
1350 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1351 saved_hard_reg = 1, offset += 4; \
1352 /* PIC register is a fixed reg, so call_used_regs set. */ \
1353 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1354 saved_hard_reg = 1, offset += 4; \
1355 for (regno = 16; regno <=23; regno++) \
1356 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1357 offset += 12; \
1358 } \
1359 if ((FROM) == FRAME_POINTER_REGNUM) \
1360 (OFFSET) = -offset; \
1361 else \
1362 { \
1363 if (! frame_pointer_needed) \
1364 offset -= 16; \
1365 if (! volatile_func \
1366 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1367 offset += 4; \
1368 offset += current_function_outgoing_args_size; \
1369 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \
1370 } \
1371 } \
1372 }
1373
1374 /* Output assembler code for a block containing the constant parts
1375 of a trampoline, leaving space for the variable parts.
1376
1377 On the ARM, (if r8 is the static chain regnum, and remembering that
1378 referencing pc adds an offset of 8) the trampoline looks like:
1379 ldr r8, [pc, #0]
1380 ldr pc, [pc]
1381 .word static chain value
1382 .word function's address
1383 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1384 #define TRAMPOLINE_TEMPLATE(FILE) \
1385 { \
1386 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1387 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \
1388 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1389 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1390 REGISTER_PREFIX, reg_names[PC_REGNUM], \
1391 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1392 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1393 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1394 }
1395
1396 /* Length in units of the trampoline for entering a nested function. */
1397 #define TRAMPOLINE_SIZE 16
1398
1399 /* Alignment required for a trampoline in units. */
1400 #define TRAMPOLINE_ALIGN 4
1401
1402 /* Emit RTL insns to initialize the variable parts of a trampoline.
1403 FNADDR is an RTX for the address of the function's pure code.
1404 CXT is an RTX for the static chain value for the function. */
1405 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1406 { \
1407 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1408 (CXT)); \
1409 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1410 (FNADDR)); \
1411 }
1412
1413 \f
1414 /* Addressing modes, and classification of registers for them. */
1415
1416 #define HAVE_POST_INCREMENT 1
1417 #define HAVE_PRE_INCREMENT 1
1418 #define HAVE_POST_DECREMENT 1
1419 #define HAVE_PRE_DECREMENT 1
1420
1421 /* Macros to check register numbers against specific register classes. */
1422
1423 /* These assume that REGNO is a hard or pseudo reg number.
1424 They give nonzero only if REGNO is a hard reg of the suitable class
1425 or a pseudo reg currently allocated to a suitable hard reg.
1426 Since they use reg_renumber, they are safe only once reg_renumber
1427 has been allocated, which happens in local-alloc.c.
1428
1429 On the ARM, don't allow the pc to be used. */
1430 #define REGNO_OK_FOR_BASE_P(REGNO) \
1431 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1432 || (REGNO) == ARG_POINTER_REGNUM \
1433 || (unsigned) reg_renumber[(REGNO)] < 15 \
1434 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1435 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1436 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1437 REGNO_OK_FOR_BASE_P(REGNO)
1438
1439 /* Maximum number of registers that can appear in a valid memory address.
1440 Shifts in addresses can't be by a register. */
1441
1442 #define MAX_REGS_PER_ADDRESS 2
1443
1444 /* Recognize any constant value that is a valid address. */
1445 /* XXX We can address any constant, eventually... */
1446
1447 #ifdef AOF_ASSEMBLER
1448
1449 #define CONSTANT_ADDRESS_P(X) \
1450 (GET_CODE (X) == SYMBOL_REF \
1451 && CONSTANT_POOL_ADDRESS_P (X))
1452
1453 #else
1454
1455 #define CONSTANT_ADDRESS_P(X) \
1456 (GET_CODE (X) == SYMBOL_REF \
1457 && (CONSTANT_POOL_ADDRESS_P (X) \
1458 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1459
1460 #endif /* AOF_ASSEMBLER */
1461
1462 /* Nonzero if the constant value X is a legitimate general operand.
1463 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1464
1465 On the ARM, allow any integer (invalid ones are removed later by insn
1466 patterns), nice doubles and symbol_refs which refer to the function's
1467 constant pool XXX.
1468
1469 When generating pic allow anything. */
1470 #define LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1471 \f
1472 /* Special characters prefixed to function names
1473 in order to encode attribute like information.
1474 Note, '@' and '*' have already been taken. */
1475 #define SHORT_CALL_FLAG_CHAR '^'
1476 #define LONG_CALL_FLAG_CHAR '#'
1477
1478 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1479 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1480
1481 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1482 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1483
1484 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1485 #define SUBTARGET_NAME_ENCODING_LENGTHS
1486 #endif
1487
1488 /* This is a C fragement for the inside of a switch statement.
1489 Each case label should return the number of characters to
1490 be stripped from the start of a function's name, if that
1491 name starts with the indicated character. */
1492 #define ARM_NAME_ENCODING_LENGTHS \
1493 case SHORT_CALL_FLAG_CHAR: return 1; \
1494 case LONG_CALL_FLAG_CHAR: return 1; \
1495 case '*': return 1; \
1496 SUBTARGET_NAME_ENCODING_LENGTHS
1497
1498 /* This has to be handled by a function because more than part of the
1499 ARM backend uses funciton name prefixes to encode attributes. */
1500 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1501 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1502
1503 /* This is how to output a reference to a user-level label named NAME.
1504 `assemble_name' uses this. */
1505 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1506 fprintf (FILE, "%s%s", USER_LABEL_PREFIX, arm_strip_name_encoding (NAME))
1507
1508 /* If we are referencing a function that is weak then encode a long call
1509 flag in the function name, otherwise if the function is static or
1510 or known to be defined in this file then encode a short call flag.
1511 This macro is used inside the ENCODE_SECTION macro. */
1512 #define ARM_ENCODE_CALL_TYPE(decl) \
1513 if (TREE_CODE (decl) == FUNCTION_DECL) \
1514 { \
1515 if (DECL_WEAK (decl)) \
1516 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1517 else if (! TREE_PUBLIC (decl)) \
1518 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1519 } \
1520
1521 /* Symbols in the text segment can be accessed without indirecting via the
1522 constant pool; it may take an extra binary operation, but this is still
1523 faster than indirecting via memory. Don't do this when not optimizing,
1524 since we won't be calculating al of the offsets necessary to do this
1525 simplification. */
1526 /* This doesn't work with AOF syntax, since the string table may be in
1527 a different AREA. */
1528 #ifndef AOF_ASSEMBLER
1529 #define ENCODE_SECTION_INFO(decl) \
1530 { \
1531 if (optimize > 0 && TREE_CONSTANT (decl) \
1532 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1533 { \
1534 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1535 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1536 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1537 } \
1538 ARM_ENCODE_CALL_TYPE (decl) \
1539 }
1540 #else
1541 #define ENCODE_SECTION_INFO(decl) \
1542 { \
1543 ARM_ENCODE_CALL_TYPE (decl) \
1544 }
1545 #endif
1546
1547 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1548 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1549
1550 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1551 and check its validity for a certain class.
1552 We have two alternate definitions for each of them.
1553 The usual definition accepts all pseudo regs; the other rejects
1554 them unless they have been allocated suitable hard regs.
1555 The symbol REG_OK_STRICT causes the latter definition to be used. */
1556 #ifndef REG_OK_STRICT
1557
1558 /* Nonzero if X is a hard reg that can be used as a base reg
1559 or if it is a pseudo reg. */
1560 #define REG_OK_FOR_BASE_P(X) \
1561 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1562 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1563
1564 /* Nonzero if X is a hard reg that can be used as an index
1565 or if it is a pseudo reg. */
1566 #define REG_OK_FOR_INDEX_P(X) \
1567 REG_OK_FOR_BASE_P(X)
1568
1569 #define REG_OK_FOR_PRE_POST_P(X) \
1570 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1571 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1572
1573 #else
1574
1575 /* Nonzero if X is a hard reg that can be used as a base reg. */
1576 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1577
1578 /* Nonzero if X is a hard reg that can be used as an index. */
1579 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1580
1581 #define REG_OK_FOR_PRE_POST_P(X) \
1582 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1583 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1584 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1585 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1586
1587 #endif
1588 \f
1589 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1590 that is a valid memory address for an instruction.
1591 The MODE argument is the machine mode for the MEM expression
1592 that wants to use this address.
1593
1594 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1595 #define BASE_REGISTER_RTX_P(X) \
1596 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1597
1598 #define INDEX_REGISTER_RTX_P(X) \
1599 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1600
1601 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1602 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1603 only be small constants. */
1604 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1605 do \
1606 { \
1607 HOST_WIDE_INT range; \
1608 enum rtx_code code = GET_CODE (INDEX); \
1609 \
1610 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1611 { \
1612 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1613 && INTVAL (INDEX) > -1024 \
1614 && (INTVAL (INDEX) & 3) == 0) \
1615 goto LABEL; \
1616 } \
1617 else \
1618 { \
1619 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1620 goto LABEL; \
1621 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1622 && (! arm_arch4 || (MODE) != HImode)) \
1623 { \
1624 rtx xiop0 = XEXP (INDEX, 0); \
1625 rtx xiop1 = XEXP (INDEX, 1); \
1626 if (INDEX_REGISTER_RTX_P (xiop0) \
1627 && power_of_two_operand (xiop1, SImode)) \
1628 goto LABEL; \
1629 if (INDEX_REGISTER_RTX_P (xiop1) \
1630 && power_of_two_operand (xiop0, SImode)) \
1631 goto LABEL; \
1632 } \
1633 if (GET_MODE_SIZE (MODE) <= 4 \
1634 && (code == LSHIFTRT || code == ASHIFTRT \
1635 || code == ASHIFT || code == ROTATERT) \
1636 && (! arm_arch4 || (MODE) != HImode)) \
1637 { \
1638 rtx op = XEXP (INDEX, 1); \
1639 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1640 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1641 && INTVAL (op) <= 31) \
1642 goto LABEL; \
1643 } \
1644 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1645 range = ((MODE) == HImode || (MODE) == QImode) \
1646 ? (arm_arch4 ? 256 : 4095) : 4096; \
1647 if (code == CONST_INT && INTVAL (INDEX) < range \
1648 && INTVAL (INDEX) > -range) \
1649 goto LABEL; \
1650 } \
1651 } \
1652 while (0)
1653
1654 /* Jump to LABEL if X is a valid address RTX. This must also take
1655 REG_OK_STRICT into account when deciding about valid registers, but it uses
1656 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1657 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1658 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1659 refs must be forced though a static cell to ensure addressability. */
1660 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1661 { \
1662 if (BASE_REGISTER_RTX_P (X)) \
1663 goto LABEL; \
1664 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1665 && GET_CODE (XEXP (X, 0)) == REG \
1666 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1667 goto LABEL; \
1668 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1669 && (GET_CODE (X) == LABEL_REF \
1670 || (GET_CODE (X) == CONST \
1671 && GET_CODE (XEXP ((X), 0)) == PLUS \
1672 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1673 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1674 goto LABEL; \
1675 else if ((MODE) == TImode) \
1676 ; \
1677 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1678 { \
1679 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1680 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1681 { \
1682 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1683 if (val == 4 || val == -4 || val == -8) \
1684 goto LABEL; \
1685 } \
1686 } \
1687 else if (GET_CODE (X) == PLUS) \
1688 { \
1689 rtx xop0 = XEXP(X,0); \
1690 rtx xop1 = XEXP(X,1); \
1691 \
1692 if (BASE_REGISTER_RTX_P (xop0)) \
1693 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1694 else if (BASE_REGISTER_RTX_P (xop1)) \
1695 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1696 } \
1697 /* Reload currently can't handle MINUS, so disable this for now */ \
1698 /* else if (GET_CODE (X) == MINUS) \
1699 { \
1700 rtx xop0 = XEXP (X,0); \
1701 rtx xop1 = XEXP (X,1); \
1702 \
1703 if (BASE_REGISTER_RTX_P (xop0)) \
1704 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1705 } */ \
1706 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1707 && GET_CODE (X) == SYMBOL_REF \
1708 && CONSTANT_POOL_ADDRESS_P (X) \
1709 && ! (flag_pic \
1710 && symbol_mentioned_p (get_pool_constant (X)))) \
1711 goto LABEL; \
1712 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1713 && (GET_MODE_SIZE (MODE) <= 4) \
1714 && GET_CODE (XEXP (X, 0)) == REG \
1715 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1716 goto LABEL; \
1717 }
1718 \f
1719 /* Try machine-dependent ways of modifying an illegitimate address
1720 to be legitimate. If we find one, return the new, valid address.
1721 This macro is used in only one place: `memory_address' in explow.c.
1722
1723 OLDX is the address as it was before break_out_memory_refs was called.
1724 In some cases it is useful to look at this to decide what needs to be done.
1725
1726 MODE and WIN are passed so that this macro can use
1727 GO_IF_LEGITIMATE_ADDRESS.
1728
1729 It is always safe for this macro to do nothing. It exists to recognize
1730 opportunities to optimize the output.
1731
1732 On the ARM, try to convert [REG, #BIGCONST]
1733 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1734 where VALIDCONST == 0 in case of TImode. */
1735 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1736 { \
1737 if (GET_CODE (X) == PLUS) \
1738 { \
1739 rtx xop0 = XEXP (X, 0); \
1740 rtx xop1 = XEXP (X, 1); \
1741 \
1742 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1743 xop0 = force_reg (SImode, xop0); \
1744 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1745 xop1 = force_reg (SImode, xop1); \
1746 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1747 { \
1748 HOST_WIDE_INT n, low_n; \
1749 rtx base_reg, val; \
1750 n = INTVAL (xop1); \
1751 \
1752 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1753 { \
1754 low_n = n & 0x0f; \
1755 n &= ~0x0f; \
1756 if (low_n > 4) \
1757 { \
1758 n += 16; \
1759 low_n -= 16; \
1760 } \
1761 } \
1762 else \
1763 { \
1764 low_n = ((MODE) == TImode ? 0 \
1765 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1766 n -= low_n; \
1767 } \
1768 base_reg = gen_reg_rtx (SImode); \
1769 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1770 GEN_INT (n)), NULL_RTX); \
1771 emit_move_insn (base_reg, val); \
1772 (X) = (low_n == 0 ? base_reg \
1773 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1774 } \
1775 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1776 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1777 } \
1778 else if (GET_CODE (X) == MINUS) \
1779 { \
1780 rtx xop0 = XEXP (X, 0); \
1781 rtx xop1 = XEXP (X, 1); \
1782 \
1783 if (CONSTANT_P (xop0)) \
1784 xop0 = force_reg (SImode, xop0); \
1785 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1786 xop1 = force_reg (SImode, xop1); \
1787 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1788 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1789 } \
1790 if (flag_pic) \
1791 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1792 if (memory_address_p (MODE, X)) \
1793 goto WIN; \
1794 }
1795
1796 /* Go to LABEL if ADDR (a legitimate address expression)
1797 has an effect that depends on the machine mode it is used for. */
1798 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1799 { \
1800 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1801 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1802 goto LABEL; \
1803 }
1804 \f
1805 /* Specify the machine mode that this machine uses
1806 for the index in the tablejump instruction. */
1807 #define CASE_VECTOR_MODE SImode
1808
1809 /* Define as C expression which evaluates to nonzero if the tablejump
1810 instruction expects the table to contain offsets from the address of the
1811 table.
1812 Do not define this if the table should contain absolute addresses. */
1813 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1814
1815 /* Specify the tree operation to be used to convert reals to integers. */
1816 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1817
1818 /* This is the kind of divide that is easiest to do in the general case. */
1819 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1820
1821 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1822 unsigned is probably best, but may break some code. */
1823 #ifndef DEFAULT_SIGNED_CHAR
1824 #define DEFAULT_SIGNED_CHAR 0
1825 #endif
1826
1827 /* Don't cse the address of the function being compiled. */
1828 #define NO_RECURSIVE_FUNCTION_CSE 1
1829
1830 /* Max number of bytes we can move from memory to memory
1831 in one reasonably fast instruction. */
1832 #define MOVE_MAX 4
1833
1834 /* Define if operations between registers always perform the operation
1835 on the full register even if a narrower mode is specified. */
1836 #define WORD_REGISTER_OPERATIONS
1837
1838 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1839 will either zero-extend or sign-extend. The value of this macro should
1840 be the code that says which one of the two operations is implicitly
1841 done, NIL if none. */
1842 #define LOAD_EXTEND_OP(MODE) \
1843 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1844 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1845
1846 /* Define this if zero-extension is slow (more than one real instruction).
1847 On the ARM, it is more than one instruction only if not fetching from
1848 memory. */
1849 /* #define SLOW_ZERO_EXTEND */
1850
1851 /* Nonzero if access to memory by bytes is slow and undesirable. */
1852 #define SLOW_BYTE_ACCESS 0
1853
1854 /* Immediate shift counts are truncated by the output routines (or was it
1855 the assembler?). Shift counts in a register are truncated by ARM. Note
1856 that the native compiler puts too large (> 32) immediate shift counts
1857 into a register and shifts by the register, letting the ARM decide what
1858 to do instead of doing that itself. */
1859 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1860 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1861 On the arm, Y in a register is used modulo 256 for the shift. Only for
1862 rotates is modulo 32 used. */
1863 /* #define SHIFT_COUNT_TRUNCATED 1 */
1864
1865 /* All integers have the same format so truncation is easy. */
1866 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1867
1868 /* Calling from registers is a massive pain. */
1869 #define NO_FUNCTION_CSE 1
1870
1871 /* Chars and shorts should be passed as ints. */
1872 #define PROMOTE_PROTOTYPES 1
1873
1874 /* The machine modes of pointers and functions */
1875 #define Pmode SImode
1876 #define FUNCTION_MODE Pmode
1877
1878 /* The structure type of the machine dependent info field of insns
1879 No uses for this yet. */
1880 /* #define INSN_MACHINE_INFO struct machine_info */
1881
1882 /* The relative costs of various types of constants. Note that cse.c defines
1883 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1884 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1885 case CONST_INT: \
1886 if (const_ok_for_arm (INTVAL (RTX))) \
1887 return (OUTER_CODE) == SET ? 2 : -1; \
1888 else if (OUTER_CODE == AND \
1889 && const_ok_for_arm (~INTVAL (RTX))) \
1890 return -1; \
1891 else if ((OUTER_CODE == COMPARE \
1892 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1893 && const_ok_for_arm (-INTVAL (RTX))) \
1894 return -1; \
1895 else \
1896 return 5; \
1897 case CONST: \
1898 case LABEL_REF: \
1899 case SYMBOL_REF: \
1900 return 6; \
1901 case CONST_DOUBLE: \
1902 if (const_double_rtx_ok_for_fpu (RTX)) \
1903 return (OUTER_CODE) == SET ? 2 : -1; \
1904 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1905 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1906 return -1; \
1907 return(7);
1908
1909 #define ARM_FRAME_RTX(X) \
1910 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1911 || (X) == arg_pointer_rtx)
1912
1913 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
1914 return arm_rtx_costs (X, CODE);
1915
1916 /* Moves to and from memory are quite expensive */
1917 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1918
1919 /* All address computations that can be done are free, but rtx cost returns
1920 the same for practically all of them. So we weight the different types
1921 of address here in the order (most pref first):
1922 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1923 #define ADDRESS_COST(X) \
1924 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1925 || GET_CODE (X) == SYMBOL_REF) \
1926 ? 0 \
1927 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1928 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1929 ? 10 \
1930 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1931 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1932 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1933 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1934 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1935 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1936 ? 1 : 0)) \
1937 : 4)))))
1938
1939 /* Try to generate sequences that don't involve branches, we can then use
1940 conditional instructions */
1941 #define BRANCH_COST 4
1942
1943 /* A C statement to update the variable COST based on the relationship
1944 between INSN that is dependent on DEP through dependence LINK. */
1945 #define ADJUST_COST(INSN, LINK, DEP, COST) \
1946 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
1947 \f
1948 /* Position Independent Code. */
1949 /* We decide which register to use based on the compilation options and
1950 the assembler in use; this is more general than the APCS restriction of
1951 using sb (r9) all the time. */
1952 extern int arm_pic_register;
1953
1954 /* Used when parsing command line option -mpic-register=. */
1955 extern const char * arm_pic_register_string;
1956
1957 /* The register number of the register used to address a table of static
1958 data addresses in memory. */
1959 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1960
1961 #define FINALIZE_PIC arm_finalize_pic ()
1962
1963 /* We can't directly access anything that contains a symbol,
1964 nor can we indirect via the constant pool. */
1965 #define LEGITIMATE_PIC_OPERAND_P(X) \
1966 ( ! symbol_mentioned_p (X) \
1967 && ! label_mentioned_p (X) \
1968 && (! CONSTANT_POOL_ADDRESS_P (X) \
1969 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
1970 && ! label_mentioned_p (get_pool_constant (X)))))
1971
1972 /* We need to know when we are making a constant pool; this determines
1973 whether data needs to be in the GOT or can be referenced via a GOT
1974 offset. */
1975 extern int making_const_table;
1976 \f
1977 /* If defined, a C expression whose value is nonzero if IDENTIFIER
1978 with arguments ARGS is a valid machine specific attribute for TYPE.
1979 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
1980 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
1981 (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
1982
1983 /* If defined, a C expression whose value is zero if the attributes on
1984 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
1985 two if they are nearly compatible (which causes a warning to be
1986 generated). */
1987 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
1988 (arm_comp_type_attributes (TYPE1, TYPE2))
1989
1990 /* If defined, a C statement that assigns default attributes to newly
1991 defined TYPE. */
1992 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
1993 arm_set_default_type_attributes (TYPE)
1994
1995 /* Handle pragmas for compatibility with Intel's compilers. */
1996 #define HANDLE_PRAGMA(GET, UNGET, NAME) arm_process_pragma (GET, UNGET, NAME)
1997 \f
1998 /* Condition code information. */
1999 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2000 return the mode to be used for the comparison.
2001 CCFPEmode should be used with floating inequalities,
2002 CCFPmode should be used with floating equalities.
2003 CC_NOOVmode should be used with SImode integer equalities.
2004 CC_Zmode should be used if only the Z flag is set correctly
2005 CCmode should be used otherwise. */
2006
2007 #define EXTRA_CC_MODES \
2008 CC(CC_NOOVmode, "CC_NOOV") \
2009 CC(CC_Zmode, "CC_Z") \
2010 CC(CC_SWPmode, "CC_SWP") \
2011 CC(CCFPmode, "CCFP") \
2012 CC(CCFPEmode, "CCFPE") \
2013 CC(CC_DNEmode, "CC_DNE") \
2014 CC(CC_DEQmode, "CC_DEQ") \
2015 CC(CC_DLEmode, "CC_DLE") \
2016 CC(CC_DLTmode, "CC_DLT") \
2017 CC(CC_DGEmode, "CC_DGE") \
2018 CC(CC_DGTmode, "CC_DGT") \
2019 CC(CC_DLEUmode, "CC_DLEU") \
2020 CC(CC_DLTUmode, "CC_DLTU") \
2021 CC(CC_DGEUmode, "CC_DGEU") \
2022 CC(CC_DGTUmode, "CC_DGTU") \
2023 CC(CC_Cmode, "CC_C")
2024
2025 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
2026
2027 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2028
2029 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2030 do \
2031 { \
2032 if (GET_CODE (OP1) == CONST_INT \
2033 && ! (const_ok_for_arm (INTVAL (OP1)) \
2034 || (const_ok_for_arm (- INTVAL (OP1))))) \
2035 { \
2036 rtx const_op = OP1; \
2037 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2038 OP1 = const_op; \
2039 } \
2040 } \
2041 while (0)
2042
2043 #define STORE_FLAG_VALUE 1
2044
2045 /* Define the information needed to generate branch insns. This is
2046 stored from the compare operation. Note that we can't use "rtx" here
2047 since it hasn't been defined! */
2048
2049 extern struct rtx_def * arm_compare_op0;
2050 extern struct rtx_def * arm_compare_op1;
2051
2052 /* Define the codes that are matched by predicates in arm.c */
2053 #define PREDICATE_CODES \
2054 {"s_register_operand", {SUBREG, REG}}, \
2055 {"f_register_operand", {SUBREG, REG}}, \
2056 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2057 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2058 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2059 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2060 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2061 {"offsettable_memory_operand", {MEM}}, \
2062 {"bad_signed_byte_operand", {MEM}}, \
2063 {"alignable_memory_operand", {MEM}}, \
2064 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2065 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2066 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2067 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2068 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2069 {"load_multiple_operation", {PARALLEL}}, \
2070 {"store_multiple_operation", {PARALLEL}}, \
2071 {"equality_operator", {EQ, NE}}, \
2072 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2073 {"const_shift_operand", {CONST_INT}}, \
2074 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2075 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2076 {"multi_register_push", {PARALLEL}}, \
2077 {"cc_register", {REG}}, \
2078 {"logical_binary_operator", {AND, IOR, XOR}}, \
2079 {"dominant_cc_register", {REG}},
2080
2081 \f
2082
2083 /* Gcc puts the pool in the wrong place for ARM, since we can only
2084 load addresses a limited distance around the pc. We do some
2085 special munging to move the constant pool values to the correct
2086 point in the code. */
2087 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
2088
2089 /* Output an internal label definition. */
2090 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2091 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2092 do \
2093 { \
2094 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2095 \
2096 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2097 && !strcmp (PREFIX, "L")) \
2098 { \
2099 arm_ccfsm_state = 0; \
2100 arm_target_insn = NULL; \
2101 } \
2102 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2103 ASM_OUTPUT_LABEL (STREAM, s); \
2104 } \
2105 while (0)
2106 #endif
2107
2108 /* Output a push or a pop instruction (only used when profiling). */
2109 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2110 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2111
2112 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2113 asm_fprintf (STREAM,"\tldmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2114
2115 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2116 do \
2117 { \
2118 if (TARGET_POKE_FUNCTION_NAME) \
2119 arm_poke_function_name (STREAM, (char *) NAME); \
2120 } \
2121 while (0)
2122
2123 /* Target characters. */
2124 #define TARGET_BELL 007
2125 #define TARGET_BS 010
2126 #define TARGET_TAB 011
2127 #define TARGET_NEWLINE 012
2128 #define TARGET_VT 013
2129 #define TARGET_FF 014
2130 #define TARGET_CR 015
2131 \f
2132 /* Only perform branch elimination (by making instructions conditional) if
2133 we're optimising. Otherwise it's of no use anyway. */
2134 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2135 if (optimize) \
2136 arm_final_prescan_insn (INSN)
2137
2138 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2139 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
2140
2141 /* Output an operand of an instruction. */
2142 #define PRINT_OPERAND(STREAM, X, CODE) \
2143 arm_print_operand (STREAM, X, CODE)
2144
2145 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2146 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2147 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffffUL) | \
2148 (((x) & (unsigned HOST_WIDE_INT) 0x80000000UL) \
2149 ? ((~ (HOST_WIDE_INT) 0) \
2150 & ~ (unsigned HOST_WIDE_INT) 0xffffffffUL) \
2151 : 0))))
2152
2153 /* Output the address of an operand. */
2154 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
2155 { \
2156 int is_minus = GET_CODE (X) == MINUS; \
2157 \
2158 if (GET_CODE (X) == REG) \
2159 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2160 else if (GET_CODE (X) == PLUS || is_minus) \
2161 { \
2162 rtx base = XEXP (X, 0); \
2163 rtx index = XEXP (X, 1); \
2164 int base_reg; \
2165 HOST_WIDE_INT offset = 0; \
2166 if (GET_CODE (base) != REG) \
2167 { \
2168 /* Ensure that BASE is a register (one of them must be). */ \
2169 rtx temp = base; \
2170 base = index; \
2171 index = temp; \
2172 } \
2173 base_reg = REGNO (base); \
2174 switch (GET_CODE (index)) \
2175 { \
2176 case CONST_INT: \
2177 offset = INTVAL (index); \
2178 if (is_minus) \
2179 offset = -offset; \
2180 asm_fprintf (STREAM, "[%r, #%d]", base_reg, offset); \
2181 break; \
2182 \
2183 case REG: \
2184 asm_fprintf (STREAM, "[%r, %s%r]", base_reg, \
2185 is_minus ? "-" : "", REGNO (index)); \
2186 break; \
2187 \
2188 case MULT: \
2189 case ASHIFTRT: \
2190 case LSHIFTRT: \
2191 case ASHIFT: \
2192 case ROTATERT: \
2193 { \
2194 asm_fprintf (STREAM, "[%r, %s%r", base_reg, \
2195 is_minus ? "-" : "", REGNO (XEXP (index, 0))); \
2196 arm_print_operand (STREAM, index, 'S'); \
2197 fputs ("]", STREAM); \
2198 break; \
2199 } \
2200 \
2201 default: \
2202 abort(); \
2203 } \
2204 } \
2205 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2206 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2207 { \
2208 extern int output_memory_reference_mode; \
2209 \
2210 if (GET_CODE (XEXP (X, 0)) != REG) \
2211 abort (); \
2212 \
2213 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2214 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2215 REGNO (XEXP (X, 0)), \
2216 GET_CODE (X) == PRE_DEC ? "-" : "", \
2217 GET_MODE_SIZE (output_memory_reference_mode)); \
2218 else \
2219 asm_fprintf (STREAM, "[%r], #%s%d", \
2220 REGNO (XEXP (X, 0)), \
2221 GET_CODE (X) == POST_DEC ? "-" : "", \
2222 GET_MODE_SIZE (output_memory_reference_mode)); \
2223 } \
2224 else output_addr_const (STREAM, X); \
2225 }
2226
2227 /* Handles PIC addr specially */
2228 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2229 { \
2230 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2231 { \
2232 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2233 fputs (" - (", STREAM); \
2234 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2235 fputs (")", STREAM); \
2236 } \
2237 else output_addr_const (STREAM, X); \
2238 \
2239 /* Mark symbols as position independent. We only do this in the \
2240 .text segment, not in the .data segment. */ \
2241 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2242 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2243 { \
2244 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2245 fprintf (STREAM, "(GOTOFF)"); \
2246 else if (GET_CODE (X) == LABEL_REF) \
2247 fprintf (STREAM, "(GOTOFF)"); \
2248 else \
2249 fprintf (STREAM, "(GOT)"); \
2250 } \
2251 }
2252
2253 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2254 Used for C++ multiple inheritance. */
2255 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2256 do \
2257 { \
2258 int mi_delta = (DELTA); \
2259 const char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2260 int shift = 0; \
2261 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2262 ? 1 : 0); \
2263 if (mi_delta < 0) \
2264 mi_delta = - mi_delta; \
2265 while (mi_delta != 0) \
2266 { \
2267 if ((mi_delta & (3 << shift)) == 0) \
2268 shift += 2; \
2269 else \
2270 { \
2271 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2272 mi_op, this_regno, this_regno, \
2273 mi_delta & (0xff << shift)); \
2274 mi_delta &= ~(0xff << shift); \
2275 shift += 8; \
2276 } \
2277 } \
2278 fputs ("\tb\t", FILE); \
2279 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2280 if (NEED_PLT_RELOC) \
2281 fputs ("(PLT)", FILE); \
2282 fputc ('\n', FILE); \
2283 } \
2284 while (0)
2285
2286 /* A C expression whose value is RTL representing the value of the return
2287 address for the frame COUNT steps up from the current frame. */
2288
2289 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2290 ((COUNT == 0) \
2291 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2292 : NULL_RTX)
2293
2294 /* Pick up the return address upon entry to a procedure. Used for
2295 dwarf2 unwind information. This also enables the table driven
2296 mechanism. */
2297
2298 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2299 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2300
2301 /* Used to mask out junk bits from the return address, such as
2302 processor state, interrupt status, condition codes and the like. */
2303 #define MASK_RETURN_ADDR \
2304 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2305 in 26 bit mode, the condition codes must be masked out of the \
2306 return address. This does not apply to ARM6 and later processors \
2307 when running in 32 bit mode. */ \
2308 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2309
2310 #endif /* __ARM_H__ */
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