| blob | c8a16e0850d8eb4f36351fcb566348e1b5ef8dd6 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
70 /* Not really meaningful values, but at least something. */
71 #ifndef SIMULTANEOUS_PREFETCHES
72 #define SIMULTANEOUS_PREFETCHES 3
73 #endif
74 #ifndef PREFETCH_BLOCK
75 #define PREFETCH_BLOCK 32
76 #endif
77 #ifndef HAVE_prefetch
78 #define HAVE_prefetch 0
79 #define CODE_FOR_prefetch 0
80 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
81 #endif
83 /* Give up the prefetch optimizations once we exceed a given threshold.
84 It is unlikely that we would be able to optimize something in a loop
85 with so many detected prefetches. */
86 #define MAX_PREFETCHES 100
87 /* The number of prefetch blocks that are beneficial to fetch at once before
88 a loop with a known (and low) iteration count. */
89 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
90 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
91 since it is likely that the data are already in the cache. */
92 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
94 /* Parameterize some prefetch heuristics so they can be turned on and off
95 easily for performance testing on new architectures. These can be
96 defined in target-dependent files. */
98 /* Prefetch is worthwhile only when loads/stores are dense. */
99 #ifndef PREFETCH_ONLY_DENSE_MEM
100 #define PREFETCH_ONLY_DENSE_MEM 1
101 #endif
103 /* Define what we mean by "dense" loads and stores; This value divided by 256
104 is the minimum percentage of memory references that worth prefetching. */
105 #ifndef PREFETCH_DENSE_MEM
106 #define PREFETCH_DENSE_MEM 220
107 #endif
109 /* Do not prefetch for a loop whose iteration count is known to be low. */
110 #ifndef PREFETCH_NO_LOW_LOOPCNT
111 #define PREFETCH_NO_LOW_LOOPCNT 1
112 #endif
114 /* Define what we mean by a "low" iteration count. */
115 #ifndef PREFETCH_LOW_LOOPCNT
116 #define PREFETCH_LOW_LOOPCNT 32
117 #endif
119 /* Do not prefetch for a loop that contains a function call; such a loop is
120 probably not an internal loop. */
121 #ifndef PREFETCH_NO_CALL
122 #define PREFETCH_NO_CALL 1
123 #endif
125 /* Do not prefetch accesses with an extreme stride. */
126 #ifndef PREFETCH_NO_EXTREME_STRIDE
127 #define PREFETCH_NO_EXTREME_STRIDE 1
128 #endif
130 /* Define what we mean by an "extreme" stride. */
131 #ifndef PREFETCH_EXTREME_STRIDE
132 #define PREFETCH_EXTREME_STRIDE 4096
133 #endif
135 /* Define a limit to how far apart indices can be and still be merged
136 into a single prefetch. */
137 #ifndef PREFETCH_EXTREME_DIFFERENCE
138 #define PREFETCH_EXTREME_DIFFERENCE 4096
139 #endif
141 /* Issue prefetch instructions before the loop to fetch data to be used
142 in the first few loop iterations. */
143 #ifndef PREFETCH_BEFORE_LOOP
144 #define PREFETCH_BEFORE_LOOP 1
145 #endif
147 /* Do not handle reversed order prefetches (negative stride). */
148 #ifndef PREFETCH_NO_REVERSE_ORDER
149 #define PREFETCH_NO_REVERSE_ORDER 1
150 #endif
152 /* Prefetch even if the GIV is in conditional code. */
153 #ifndef PREFETCH_CONDITIONAL
154 #define PREFETCH_CONDITIONAL 1
155 #endif
157 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
158 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
160 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
161 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
162 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
164 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
165 ((REGNO) < FIRST_PSEUDO_REGISTER \
166 ? (int) hard_regno_nregs[(REGNO)][GET_MODE (SET_DEST)] : 1)
169 /* Vector mapping INSN_UIDs to luids.
170 The luids are like uids but increase monotonically always.
171 We use them to see whether a jump comes from outside a given loop. */
175 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
176 number the insn is contained in. */
180 /* 1 + largest uid of any insn. */
184 /* Number of loops detected in current function. Used as index to the
185 next few tables. */
189 /* Bound on pseudo register number before loop optimization.
190 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
193 /* The value to pass to the next call of reg_scan_update. */
195 \f
196 /* During the analysis of a loop, a chain of `struct movable's
197 is made to record all the movable insns found.
198 Then the entire chain can be scanned to decide which to move. */
200 struct movable
201 {
206 of any registers used within the LIBCALL. */
208 that must be moved with this one. */
211 may be adjusted when matching movables
212 that load the same value are found. */
214 including other movables that force this
215 or match this one. */
217 a low part that we should avoid changing when
218 clearing the rest of the reg. */
222 /* If PARTIAL is 1, GLOBAL means something different:
223 that the reg is live outside the range from where it is set
224 to the following label. */
228 In particular, moving it does not make it
229 invariant. */
231 load SRC, rather than copying INSN. */
233 first insn of a consecutive sets group. */
236 the original insn with a copy from that
237 pseudo, rather than deleting it. */
241 };
246 /* Forward declarations. */
261 #if 0
263 #endif
306 rtx *);
367 {
368 rtx match;
369 rtx replacement;
370 rtx insn;
373 /* Nonzero iff INSN is between START and END, inclusive. */
374 #define INSN_IN_RANGE_P(INSN, START, END) \
375 (INSN_UID (INSN) < max_uid_for_loop \
376 && INSN_LUID (INSN) >= INSN_LUID (START) \
377 && INSN_LUID (INSN) <= INSN_LUID (END))
379 /* Indirect_jump_in_function is computed once per function. */
387 \f
388 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
389 copy the value of the strength reduced giv to its original register. */
392 /* Cost of using a register, to normalize the benefits of a giv. */
395 void
397 {
403 }
404 \f
405 /* Compute the mapping from uids to luids.
406 LUIDs are numbers assigned to insns, like uids,
407 except that luids increase monotonically through the code.
408 Start at insn START and stop just before END. Assign LUIDs
409 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
410 static int
412 {
414 rtx insn;
417 {
420 /* Don't assign luids to line-number NOTEs, so that the distance in
421 luids between two insns is not affected by -g. */
425 else
426 /* Give a line number note the same luid as preceding insn. */
428 }
430 }
431 \f
432 /* Entry point of this file. Perform loop optimization
433 on the current function. F is the first insn of the function
434 and DUMPFILE is a stream for output of a trace of actions taken
435 (or 0 if none should be output). */
437 void
439 {
440 rtx insn;
455 /* Count the number of loops. */
459 {
462 max_loop_num++;
463 }
465 /* Don't waste time if no loops. */
471 /* Get size to use for tables indexed by uids.
472 Leave some space for labels allocated by find_and_verify_loops. */
478 /* Allocate storage for array of loops. */
481 /* Find and process each loop.
482 First, find them, and record them in order of their beginnings. */
485 /* Allocate and initialize auxiliary loop information. */
490 /* Now find all register lifetimes. This must be done after
491 find_and_verify_loops, because it might reorder the insns in the
492 function. */
495 /* This must occur after reg_scan so that registers created by gcse
496 will have entries in the register tables.
498 We could have added a call to reg_scan after gcse_main in toplev.c,
499 but moving this call to init_alias_analysis is more efficient. */
502 /* See if we went too far. Note that get_max_uid already returns
503 one more that the maximum uid of all insn. */
506 /* Now reset it to the actual size we need. See above. */
509 /* find_and_verify_loops has already called compute_luids, but it
510 might have rearranged code afterwards, so we need to recompute
511 the luids now. */
514 /* Don't leave gaps in uid_luid for insns that have been
515 deleted. It is possible that the first or last insn
516 using some register has been deleted by cross-jumping.
517 Make sure that uid_luid for that former insn's uid
518 points to the general area where that insn used to be. */
520 {
524 }
529 /* Determine if the function has indirect jump. On some systems
530 this prevents low overhead loop instructions from being used. */
533 /* Now scan the loops, last ones first, since this means inner ones are done
534 before outer ones. */
536 {
540 {
543 }
544 }
548 /* Clean up. */
556 }
557 \f
558 /* Returns the next insn, in execution order, after INSN. START and
559 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
560 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
561 insn-stream; it is used with loops that are entered near the
562 bottom. */
564 static rtx
566 {
570 {
572 /* Go to the top of the loop, and continue there. */
574 else
575 /* We're done. */
577 }
580 /* We're done. */
584 }
586 /* Find any register references hidden inside X and add them to
587 the dependency list DEPS. This is used to look inside CLOBBER (MEM
588 when checking whether a PARALLEL can be pulled out of a loop. */
590 static rtx
592 {
596 else
597 {
601 {
607 }
608 }
610 }
612 /* Optimize one loop described by LOOP. */
614 /* ??? Could also move memory writes out of loops if the destination address
615 is invariant, the source is invariant, the memory write is not volatile,
616 and if we can prove that no read inside the loop can read this address
617 before the write occurs. If there is a read of this address after the
618 write, then we can also mark the memory read as invariant. */
620 static void
622 {
628 rtx p;
629 /* 1 if we are scanning insns that could be executed zero times. */
631 /* 1 if we are scanning insns that might never be executed
632 due to a subroutine call which might exit before they are reached. */
634 /* Number of insns in the loop. */
638 /* The SET from an insn, if it is the only SET in the insn. */
640 /* Chain describing insns movable in current loop. */
642 /* Ratio of extra register life span we can justify
643 for saving an instruction. More if loop doesn't call subroutines
644 since in that case saving an insn makes more difference
645 and more registers are available. */
647 /* Nonzero if we are scanning instructions in a sub-loop. */
656 /* Determine whether this loop starts with a jump down to a test at
657 the end. This will occur for a small number of loops with a test
658 that is too complex to duplicate in front of the loop.
660 We search for the first insn or label in the loop, skipping NOTEs.
661 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
662 (because we might have a loop executed only once that contains a
663 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
664 (in case we have a degenerate loop).
666 Note that if we mistakenly think that a loop is entered at the top
667 when, in fact, it is entered at the exit test, the only effect will be
668 slightly poorer optimization. Making the opposite error can generate
669 incorrect code. Since very few loops now start with a jump to the
670 exit test, the code here to detect that case is very conservative. */
673 p != loop_end
679 ;
683 /* If loop end is the end of the current function, then emit a
684 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
685 note insn. This is the position we use when sinking insns out of
686 the loop. */
689 else
692 /* Set up variables describing this loop. */
696 /* If loop has a jump before the first label,
697 the true entry is the target of that jump.
698 Start scan from there.
699 But record in LOOP->TOP the place where the end-test jumps
700 back to so we can scan that after the end of the loop. */
702 /* Loop entry must be unconditional jump (and not a RETURN) */
705 /* Check to see whether the jump actually
706 jumps out of the loop (meaning it's no loop).
707 This case can happen for things like
708 do {..} while (0). If this label was generated previously
709 by loop, we can't tell anything about it and have to reject
710 the loop. */
712 {
715 }
717 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
718 as required by loop_reg_used_before_p. So skip such loops. (This
719 test may never be true, but it's best to play it safe.)
721 Also, skip loops where we do not start scanning at a label. This
722 test also rejects loops starting with a JUMP_INSN that failed the
723 test above. */
727 {
732 }
734 /* Allocate extra space for REGs that might be created by load_mems.
735 We allocate a little extra slop as well, in the hopes that we
736 won't have to reallocate the regs array. */
741 {
747 }
749 /* Scan through the loop finding insns that are safe to move.
750 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
751 this reg will be considered invariant for subsequent insns.
752 We consider whether subsequent insns use the reg
753 in deciding whether it is worth actually moving.
755 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
756 and therefore it is possible that the insns we are scanning
757 would never be executed. At such times, we must make sure
758 that it is safe to execute the insn once instead of zero times.
759 When MAYBE_NEVER is 0, all insns will be executed at least once
760 so that is not a problem. */
765 {
767 in_libcall--;
769 {
772 in_libcall++;
776 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
778 #endif
780 {
788 /* Figure out what to use as a source of this insn. If a
789 REG_EQUIV note is given or if a REG_EQUAL note with a
790 constant operand is specified, use it as the source and
791 mark that we should move this insn by calling
792 emit_move_insn rather that duplicating the insn.
794 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
795 note is present. */
799 else
800 {
805 {
807 /* A libcall block can use regs that don't appear in
808 the equivalent expression. To move the libcall,
809 we must move those regs too. */
811 }
812 }
814 /* For parallels, add any possible uses to the dependencies, as
815 we can't move the insn without resolving them first.
816 MEMs inside CLOBBERs may also reference registers; these
817 count as implicit uses. */
819 {
821 {
824 dependencies
826 dependencies);
831 }
832 }
835 than the one where it is set (meaning that
836 something after this point in the loop might
837 depend on its value before the set). */
839 /* And the set is not guaranteed to be executed once
840 the loop starts, or the value before the set is
841 needed before the set occurs...
843 ??? Note we have quadratic behavior here, mitigated
844 by the fact that the previous test will often fail for
845 large loops. Rather than re-scanning the entire loop
846 each time for register usage, we should build tables
847 of the register usage and use them here instead. */
848 && (maybe_never
850 /* It is unsafe to move the set. However, it may be OK to
851 move the source into a new pseudo, and substitute a
852 reg-to-reg copy for the original insn.
854 This code used to consider it OK to move a set of a variable
855 which was not created by the user and not used in an exit
856 test.
857 That behavior is incorrect and was removed. */
860 /* Don't try to optimize a MODE_CC set with a constant
861 source. It probably will be combined with a conditional
862 jump. */
865 ;
866 /* Don't try to optimize a register that was made
867 by loop-optimization for an inner loop.
868 We don't know its life-span, so we can't compute
869 the benefit. */
871 ;
872 /* Don't move the source and add a reg-to-reg copy:
873 - with -Os (this certainly increases size),
874 - if the mode doesn't support copy operations (obviously),
875 - if the source is already a reg (the motion will gain nothing),
876 - if the source is a legitimate constant (likewise). */
878 && (optimize_size
883 ;
886 || (tem2
889 || (tem1
890 = consec_sets_invariant_p
893 p)))
894 /* If the insn can cause a trap (such as divide by zero),
895 can't move it unless it's guaranteed to be executed
896 once loop is entered. Even a function call might
897 prevent the trap insn from being reached
898 (since it might exit!) */
901 {
905 /* A potential lossage is where we have a case where two insns
906 can be combined as long as they are both in the loop, but
907 we move one of them outside the loop. For large loops,
908 this can lose. The most common case of this is the address
909 of a function being called.
911 Therefore, if this register is marked as being used
912 exactly once if we are in a loop with calls
913 (a "large loop"), see if we can replace the usage of
914 this register with the source of this SET. If we can,
915 delete this insn.
917 Don't do this if P has a REG_RETVAL note or if we have
918 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
930 && (! SMALL_REGISTER_CLASSES
935 /* This test is not redundant; SET_SRC (set) might be
936 a call-clobbered register and the life of REGNO
937 might span a call. */
944 {
945 /* Replace any usage in a REG_EQUAL note. Must copy
946 the new source, so that we don't get rtx sharing
947 between the SET_SOURCE and REG_NOTES of insn p. */
949 = (replace_rtx
955 i++)
958 }
967 m->consec
978 /* Set M->cond if either loop_invariant_p
979 or consec_sets_invariant_p returned 2
980 (only conditionally invariant). */
990 /* Add M to the end of the chain MOVABLES. */
994 {
995 /* It is possible for the first instruction to have a
996 REG_EQUAL note but a non-invariant SET_SRC, so we must
997 remember the status of the first instruction in case
998 the last instruction doesn't have a REG_EQUAL note. */
1001 /* Skip this insn, not checking REG_LIBCALL notes. */
1003 /* Skip the consecutive insns, if there are any. */
1005 /* Back up to the last insn of the consecutive group. */
1008 /* We must now reset m->move_insn, m->is_equiv, and
1009 possibly m->set_src to correspond to the effects of
1010 all the insns. */
1014 else
1015 {
1019 else
1022 }
1023 m->is_equiv
1025 }
1026 }
1027 /* If this register is always set within a STRICT_LOW_PART
1028 or set to zero, then its high bytes are constant.
1029 So clear them outside the loop and within the loop
1030 just load the low bytes.
1031 We must check that the machine has an instruction to do so.
1032 Also, if the value loaded into the register
1033 depends on the same register, this cannot be done. */
1043 {
1046 {
1061 /* If the insn may not be executed on some cycles,
1062 we can't clear the whole reg; clear just high part.
1063 Not even if the reg is used only within this loop.
1064 Consider this:
1065 while (1)
1066 while (s != t) {
1067 if (foo ()) x = *s;
1068 use (x);
1069 }
1070 Clearing x before the inner loop could clobber a value
1071 being saved from the last time around the outer loop.
1072 However, if the reg is not used outside this loop
1073 and all uses of the register are in the same
1074 basic block as the store, there is no problem.
1076 If this insn was made by loop, we don't know its
1077 INSN_LUID and hence must make a conservative
1078 assumption. */
1081 || (labels_in_range_p
1085 else
1094 i++)
1096 /* Add M to the end of the chain MOVABLES. */
1098 }
1099 }
1100 }
1101 }
1102 /* Past a call insn, we get to insns which might not be executed
1103 because the call might exit. This matters for insns that trap.
1104 Constant and pure call insns always return, so they don't count. */
1107 /* Past a label or a jump, we get to insns for which we
1108 can't count on whether or how many times they will be
1109 executed during each iteration. Therefore, we can
1110 only move out sets of trivial variables
1111 (those not used after the loop). */
1112 /* Similar code appears twice in strength_reduce. */
1114 /* If we enter the loop in the middle, and scan around to the
1115 beginning, don't set maybe_never for that. This must be an
1116 unconditional jump, otherwise the code at the top of the
1117 loop might never be executed. Unconditional jumps are
1118 followed by a barrier then the loop_end. */
1124 {
1125 /* At the virtual top of a converted loop, insns are again known to
1126 be executed: logically, the loop begins here even though the exit
1127 code has been duplicated. */
1131 loop_depth++;
1133 loop_depth--;
1134 }
1135 }
1137 /* If one movable subsumes another, ignore that other. */
1141 /* For each movable insn, see if the reg that it loads
1142 leads when it dies right into another conditionally movable insn.
1143 If so, record that the second insn "forces" the first one,
1144 since the second can be moved only if the first is. */
1148 /* See if there are multiple movable insns that load the same value.
1149 If there are, make all but the first point at the first one
1150 through the `match' field, and add the priorities of them
1151 all together as the priority of the first. */
1155 /* Now consider each movable insn to decide whether it is worth moving.
1156 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1158 For machines with few registers this increases code size, so do not
1159 move moveables when optimizing for code size on such machines.
1160 (The 18 below is the value for i386.) */
1164 {
1167 /* Recalculate regs->array if move_movables has created new
1168 registers. */
1170 {
1176 ;
1181 }
1182 }
1184 /* Now candidates that still are negative are those not moved.
1185 Change regs->array[I].set_in_loop to indicate that those are not actually
1186 invariant. */
1191 /* Now that we've moved some things out of the loop, we might be able to
1192 hoist even more memory references. */
1195 /* Recalculate regs->array if load_mems has created new registers. */
1203 ;
1210 {
1212 /* Ensure our label doesn't go away. */
1223 }
1226 /* The movable information is required for strength reduction. */
1232 }
1233 \f
1234 /* Add elements to *OUTPUT to record all the pseudo-regs
1235 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1237 static void
1239 {
1247 {
1265 }
1269 {
1273 {
1282 }
1283 }
1284 }
1285 \f
1286 /* Check what regs are referred to in the libcall block ending with INSN,
1287 aside from those mentioned in the equivalent value.
1288 If there are none, return 0.
1289 If there are one or more, return an EXPR_LIST containing all of them. */
1291 static rtx
1293 {
1298 /* First, find all the regs used in the libcall block
1299 that are not mentioned as inputs to the result. */
1302 {
1306 }
1309 }
1310 \f
1311 /* Return 1 if all uses of REG
1312 are between INSN and the end of the basic block. */
1314 static int
1316 {
1318 rtx p;
1323 /* Search this basic block for the already recorded last use of the reg. */
1325 {
1327 {
1333 /* Ordinary insn: if this is the last use, we win. */
1339 /* Jump insn: if this is the last use, we win. */
1342 /* Otherwise, it's the end of the basic block, so we lose. */
1347 /* It's the end of the basic block, so we lose. */
1352 }
1353 }
1355 /* The "last use" that was recorded can't be found after the first
1356 use. This can happen when the last use was deleted while
1357 processing an inner loop, this inner loop was then completely
1358 unrolled, and the outer loop is always exited after the inner loop,
1359 so that everything after the first use becomes a single basic block. */
1361 }
1362 \f
1363 /* Compute the benefit of eliminating the insns in the block whose
1364 last insn is LAST. This may be a group of insns used to compute a
1365 value directly or can contain a library call. */
1367 static int
1369 {
1370 rtx insn;
1375 {
1378 routine. */
1382 benefit++;
1383 }
1386 }
1387 \f
1388 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1390 static rtx
1392 {
1394 {
1395 rtx temp;
1397 /* If first insn of libcall sequence, skip to end. */
1398 /* Do this at start of loop, since INSN is guaranteed to
1399 be an insn here. */
1404 do
1407 }
1410 }
1412 /* Ignore any movable whose insn falls within a libcall
1413 which is part of another movable.
1414 We make use of the fact that the movable for the libcall value
1415 was made later and so appears later on the chain. */
1417 static void
1419 {
1423 {
1424 /* Is this a movable for the value of a libcall? */
1427 {
1428 rtx insn;
1429 /* Check for earlier movables inside that range,
1430 and mark them invalid. We cannot use LUIDs here because
1431 insns created by loop.c for prior loops don't have LUIDs.
1432 Rather than reject all such insns from movables, we just
1433 explicitly check each insn in the libcall (since invariant
1434 libcalls aren't that common). */
1439 }
1440 }
1441 }
1443 /* For each movable insn, see if the reg that it loads
1444 leads when it dies right into another conditionally movable insn.
1445 If so, record that the second insn "forces" the first one,
1446 since the second can be moved only if the first is. */
1448 static void
1450 {
1454 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1456 {
1459 /* ??? Could this be a bug? What if CSE caused the
1460 register of M1 to be used after this insn?
1461 Since CSE does not update regno_last_uid,
1462 this insn M->insn might not be where it dies.
1463 But very likely this doesn't matter; what matters is
1464 that M's reg is computed from M1's reg. */
1469 /* If m->consec, m->set_src isn't valid. */
1473 /* Increase the priority of the moving the first insn
1474 since it permits the second to be moved as well.
1475 Likewise for insns already forced by the first insn. */
1477 {
1482 {
1485 }
1486 }
1487 }
1488 }
1489 \f
1490 /* Find invariant expressions that are equal and can be combined into
1491 one register. */
1493 static void
1495 {
1500 /* Regs that are set more than once are not allowed to match
1501 or be matched. I'm no longer sure why not. */
1502 /* Only pseudo registers are allowed to match or be matched,
1503 since move_movables does not validate the change. */
1504 /* Perhaps testing m->consec_sets would be more appropriate here? */
1511 {
1518 /* We want later insns to match the first one. Don't make the first
1519 one match any later ones. So start this loop at m->next. */
1525 /* A reg used outside the loop mustn't be eliminated. */
1527 /* A reg used for zero-extending mustn't be eliminated. */
1530 ||
1531 (
1532 /* Can combine regs with different modes loaded from the
1533 same constant only if the modes are the same or
1534 if both are integer modes with M wider or the same
1535 width as M1. The check for integer is redundant, but
1536 safe, since the only case of differing destination
1537 modes with equal sources is when both sources are
1538 VOIDmode, i.e., CONST_INT. */
1544 /* See if the source of M1 says it matches M. */
1551 {
1557 }
1558 }
1560 /* Now combine the regs used for zero-extension.
1561 This can be done for those not marked `global'
1562 provided their lives don't overlap. */
1566 {
1569 /* Combine all the registers for extension from mode MODE.
1570 Don't combine any that are used outside this loop. */
1574 {
1581 {
1582 /* First one: don't check for overlap, just record it. */
1585 }
1587 /* Make sure they extend to the same mode.
1588 (Almost always true.) */
1592 /* We already have one: check for overlap with those
1593 already combined together. */
1600 /* No overlap: we can combine this with the others. */
1606 overlap:
1607 ;
1608 }
1609 }
1611 /* Clean up. */
1613 }
1615 /* Returns the number of movable instructions in LOOP that were not
1616 moved outside the loop. */
1618 static int
1620 {
1629 }
1631 \f
1632 /* Return 1 if regs X and Y will become the same if moved. */
1634 static int
1636 {
1653 }
1655 /* Return 1 if X and Y are identical-looking rtx's.
1656 This is the Lisp function EQUAL for rtx arguments.
1658 If two registers are matching movables or a movable register and an
1659 equivalent constant, consider them equal. */
1661 static int
1664 {
1678 /* If we have a register and a constant, they may sometimes be
1679 equal. */
1682 {
1687 }
1690 {
1695 }
1697 /* Otherwise, rtx's of different codes cannot be equal. */
1701 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1702 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1707 /* These three types of rtx's can be compared nonrecursively. */
1716 /* Compare the elements. If any pair of corresponding elements
1717 fail to match, return 0 for the whole things. */
1721 {
1723 {
1735 /* Two vectors must have the same length. */
1739 /* And the corresponding elements must match. */
1758 /* These are just backpointers, so they don't matter. */
1764 /* It is believed that rtx's at this level will never
1765 contain anything but integers and other rtx's,
1766 except for within LABEL_REFs and SYMBOL_REFs. */
1769 }
1770 }
1772 }
1773 \f
1774 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1775 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1776 references is incremented once for each added note. */
1778 static void
1780 {
1784 rtx insn;
1787 {
1788 /* This code used to ignore labels that referred to dispatch tables to
1789 avoid flow generating (slightly) worse code.
1791 We no longer ignore such label references (see LABEL_REF handling in
1792 mark_jump_label for additional information). */
1795 {
1800 }
1801 }
1805 {
1811 }
1812 }
1813 \f
1814 /* Scan MOVABLES, and move the insns that deserve to be moved.
1815 If two matching movables are combined, replace one reg with the
1816 other throughout. */
1818 static void
1821 {
1826 rtx p;
1829 /* Map of pseudo-register replacements to handle combining
1830 when we move several insns that load the same value
1831 into different pseudo-registers. */
1836 {
1837 /* Describe this movable insn. */
1840 {
1861 }
1863 /* Ignore the insn if it's already done (it matched something else).
1864 Otherwise, see if it is now safe to move. */
1876 {
1878 rtx p;
1881 /* We have an insn that is safe to move.
1882 Compute its desirability. */
1893 /* An insn MUST be moved if we already moved something else
1894 which is safe only if this one is moved too: that is,
1895 if already_moved[REGNO] is nonzero. */
1897 /* An insn is desirable to move if the new lifetime of the
1898 register is no more than THRESHOLD times the old lifetime.
1899 If it's not desirable, it means the loop is so big
1900 that moving won't speed things up much,
1901 and it is liable to make register usage worse. */
1903 /* It is also desirable to move if it can be moved at no
1904 extra cost because something else was already moved. */
1907 || flag_move_all_movables
1912 {
1921 /* Now move the insns that set the reg. */
1924 {
1927 /* Find the end of this chain of matching regs.
1928 Thus, we load each reg in the chain from that one reg.
1929 And that reg is loaded with 0 directly,
1930 since it has ->match == 0. */
1936 /* Mark the moved, invariant reg as being allowed to
1937 share a hard reg with the other matching invariant. */
1941 regs_may_share
1944 regs_may_share));
1952 }
1953 /* If we are to re-generate the item being moved with a
1954 new move insn, first delete what we have and then emit
1955 the move insn before the loop. */
1957 {
1961 {
1962 /* If this is the first insn of a library call sequence,
1963 something is very wrong. */
1968 /* If this is the last insn of a libcall sequence, then
1969 delete every insn in the sequence except the last.
1970 The last insn is handled in the normal manner. */
1973 {
1977 }
1982 /* simplify_giv_expr expects that it can walk the insns
1983 at m->insn forwards and see this old sequence we are
1984 tossing here. delete_insn does preserve the next
1985 pointers, but when we skip over a NOTE we must fix
1986 it up. Otherwise that code walks into the non-deleted
1987 insn stream. */
1992 {
1993 /* Replace the original insn with a move from
1994 our newly created temp. */
2000 }
2001 }
2020 /* The more regs we move, the less we like moving them. */
2022 }
2023 else
2024 {
2026 {
2029 /* If first insn of libcall sequence, skip to end. */
2030 /* Do this at start of loop, since p is guaranteed to
2031 be an insn here. */
2036 /* If last insn of libcall sequence, move all
2037 insns except the last before the loop. The last
2038 insn is handled in the normal manner. */
2041 {
2049 {
2050 rtx body;
2051 rtx n;
2052 rtx next;
2059 /* Find the next insn after TEMP,
2060 not counting USE or NOTE insns. */
2068 /* If that is the call, this may be the insn
2069 that loads the function address.
2071 Extract the function address from the insn
2072 that loads it into a register.
2073 If this insn was cse'd, we get incorrect code.
2075 So emit a new move insn that copies the
2076 function address into the register that the
2077 call insn will use. flow.c will delete any
2078 redundant stores that we have created. */
2083 NULL_RTX)))
2084 {
2090 }
2091 /* We have the call insn.
2092 If it uses the register we suspect it might,
2093 load it with the correct address directly. */
2098 gen_move_insn
2102 {
2104 /* Because the USAGE information potentially
2105 contains objects other than hard registers
2106 we need to copy it. */
2110 }
2111 else
2120 }
2123 }
2125 {
2126 /* P sets REG to zero; but we should clear only
2127 the bits that are not covered by the mode
2128 m->savemode. */
2130 rtx sequence;
2131 rtx tem;
2134 tem = expand_simple_binop
2147 }
2149 {
2151 /* Because the USAGE information potentially
2152 contains objects other than hard registers
2153 we need to copy it. */
2157 }
2159 {
2160 rtx seq;
2161 /* The SET_SRC might not be invariant, so we must
2162 use the REG_EQUAL note. */
2175 }
2177 {
2185 }
2186 else
2190 {
2194 /* If there is a REG_EQUAL note present whose value
2195 is not loop invariant, then delete it, since it
2196 may cause problems with later optimization passes.
2197 It is possible for cse to create such notes
2198 like this as a result of record_jump_cond. */
2203 }
2212 /* If library call, now fix the REG_NOTES that contain
2213 insn pointers, namely REG_LIBCALL on FIRST
2214 and REG_RETVAL on I1. */
2216 {
2220 }
2226 /* simplify_giv_expr expects that it can walk the insns
2227 at m->insn forwards and see this old sequence we are
2228 tossing here. delete_insn does preserve the next
2229 pointers, but when we skip over a NOTE we must fix
2230 it up. Otherwise that code walks into the non-deleted
2231 insn stream. */
2236 {
2237 rtx seq;
2238 /* Replace the original insn with a move from
2239 our newly created temp. */
2245 }
2246 }
2248 /* The more regs we move, the less we like moving them. */
2250 }
2255 {
2256 /* Any other movable that loads the same register
2257 MUST be moved. */
2260 /* This reg has been moved out of one loop. */
2263 /* The reg set here is now invariant. */
2265 {
2269 }
2271 /* Change the length-of-life info for the register
2272 to say it lives at least the full length of this loop.
2273 This will help guide optimizations in outer loops. */
2276 /* This is the old insn before all the moved insns.
2277 We can't use the moved insn because it is out of range
2278 in uid_luid. Only the old insns have luids. */
2282 }
2284 /* Combine with this moved insn any other matching movables. */
2289 {
2290 rtx temp;
2292 /* Schedule the reg loaded by M1
2293 for replacement so that shares the reg of M.
2294 If the modes differ (only possible in restricted
2295 circumstances, make a SUBREG.
2297 Note this assumes that the target dependent files
2298 treat REG and SUBREG equally, including within
2299 GO_IF_LEGITIMATE_ADDRESS and in all the
2300 predicates since we never verify that replacing the
2301 original register with a SUBREG results in a
2302 recognizable insn. */
2305 else
2310 /* Get rid of the matching insn
2311 and prevent further processing of it. */
2314 /* If library call, delete all insns. */
2316 NULL_RTX)))
2318 else
2321 /* Any other movable that loads the same register
2322 MUST be moved. */
2325 /* The reg merged here is now invariant,
2326 if the reg it matches is invariant. */
2328 {
2332 i++)
2334 }
2335 }
2336 }
2339 }
2345 }
2350 /* Go through all the instructions in the loop, making
2351 all the register substitutions scheduled in REG_MAP. */
2354 {
2358 }
2360 /* Clean up. */
2363 }
2366 static void
2368 {
2371 else
2374 }
2377 static void
2379 {
2384 {
2387 }
2388 }
2389 \f
2390 #if 0
2391 /* Scan X and replace the address of any MEM in it with ADDR.
2392 REG is the address that MEM should have before the replacement. */
2394 static void
2396 {
2405 {
2417 /* Short cut for very common case. */
2422 /* Short cut for very common case. */
2427 /* If this MEM uses a reg other than the one we expected,
2428 something is wrong. */
2436 }
2440 {
2444 {
2448 }
2449 }
2450 }
2451 #endif
2452 \f
2453 /* Return the number of memory refs to addresses that vary
2454 in the rtx X. */
2456 static int
2458 {
2469 {
2486 }
2491 {
2495 {
2499 }
2500 }
2502 }
2503 \f
2504 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2505 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2506 `unknown_address_altered', `unknown_constant_address_altered', and
2507 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2508 list `store_mems' in LOOP. */
2510 static void
2512 {
2514 rtx insn;
2518 /* The label after END. Jumping here is just like falling off the
2519 end of the loop. We use next_nonnote_insn instead of next_label
2520 as a hedge against the (pathological) case where some actual insn
2521 might end up between the two. */
2540 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2545 {
2547 {
2550 }
2551 }
2555 {
2557 {
2560 {
2562 /* Count number of loops contained in this one. */
2564 }
2571 {
2574 }
2581 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2582 attached FUNCTION_USAGE expression list, not accounted for by the
2583 code above. We should note these to avoid missing dependencies in
2584 later references. */
2585 {
2586 rtx fusage_entry;
2590 {
2596 {
2601 }
2602 }
2603 }
2608 {
2612 {
2617 {
2620 }
2621 else
2622 {
2625 }
2627 do
2628 {
2630 {
2632 {
2633 /* Something tricky. */
2636 }
2639 {
2640 /* A jump outside the current loop. */
2643 }
2644 }
2648 }
2650 }
2651 else
2652 {
2653 /* A return, or something tricky. */
2655 }
2656 }
2657 /* Fall through. */
2678 }
2679 }
2681 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2683 anywhere. */
2685 /* We don't want loads for MEMs moved to a location before the
2686 one at which their stack memory becomes allocated. (Note
2687 that this is not a problem for malloc, etc., since those
2688 require actual function calls. */
2689 && ! current_function_calls_alloca
2690 /* There are ways to leave the loop other than falling off the
2691 end. */
2697 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2698 that loop_invariant_p and load_mems can use true_dependence
2699 to determine what is really clobbered. */
2701 {
2704 loop_info->store_mems
2706 }
2708 {
2712 loop_info->store_mems
2714 }
2715 }
2716 \f
2717 /* Invalidate all loops containing LABEL. */
2719 static void
2721 {
2725 }
2727 /* Scan the function looking for loops. Record the start and end of each loop.
2728 Also mark as invalid loops any loops that contain a setjmp or are branched
2729 to from outside the loop. */
2731 static void
2733 {
2734 rtx insn;
2735 rtx label;
2745 /* If there are jumps to undefined labels,
2746 treat them as jumps out of any/all loops.
2747 This also avoids writing past end of tables when there are no loops. */
2750 /* Find boundaries of loops, mark which loops are contained within
2751 loops, and invalidate loops that have setjmp. */
2756 {
2759 {
2763 num_loops++;
2787 }
2791 {
2792 /* In this case, we must invalidate our current loop and any
2793 enclosing loop. */
2795 {
2801 }
2802 }
2804 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2805 enclosing loop, but this doesn't matter. */
2807 }
2809 /* Any loop containing a label used in an initializer must be invalidated,
2810 because it can be jumped into from anywhere. */
2814 /* Any loop containing a label used for an exception handler must be
2815 invalidated, because it can be jumped into from anywhere. */
2818 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2819 loop that it is not contained within, that loop is marked invalid.
2820 If any INSN or CALL_INSN uses a label's address, then the loop containing
2821 that label is marked invalid, because it could be jumped into from
2822 anywhere.
2824 Also look for blocks of code ending in an unconditional branch that
2825 exits the loop. If such a block is surrounded by a conditional
2826 branch around the block, move the block elsewhere (see below) and
2827 invert the jump to point to the code block. This may eliminate a
2828 label in our loop and will simplify processing by both us and a
2829 possible second cse pass. */
2833 {
2837 {
2841 }
2848 /* See if this is an unconditional branch outside the loop. */
2856 {
2857 rtx p;
2863 /* Go backwards until we reach the start of the loop, a label,
2864 or a JUMP_INSN. */
2871 ;
2873 /* Check for the case where we have a jump to an inner nested
2874 loop, and do not perform the optimization in that case. */
2877 {
2880 {
2885 }
2886 }
2888 /* Make sure that the target of P is within the current loop. */
2894 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2895 we have a block of code to try to move.
2897 We look backward and then forward from the target of INSN
2898 to find a BARRIER at the same loop depth as the target.
2899 If we find such a BARRIER, we make a new label for the start
2900 of the block, invert the jump in P and point it to that label,
2901 and move the block of code to the spot we found. */
2906 /* Just ignore jumps to labels that were never emitted.
2907 These always indicate compilation errors. */
2911 /* If it's not safe to move the sequence, then we
2912 mustn't try. */
2915 {
2916 rtx target
2920 rtx tmp;
2922 /* Search for possible garbage past the conditional jumps
2923 and look for the last barrier. */
2931 /* Don't move things inside a tablejump. */
2944 /* Don't move things inside a tablejump. */
2955 {
2959 /* Ensure our label doesn't go away. */
2962 /* Verify that uid_loop is large enough and that
2963 we can invert P. */
2965 {
2968 /* If no suitable BARRIER was found, create a suitable
2969 one before TARGET. Since TARGET is a fall through
2970 path, we'll need to insert a jump around our block
2971 and add a BARRIER before TARGET.
2973 This creates an extra unconditional jump outside
2974 the loop. However, the benefits of removing rarely
2975 executed instructions from inside the loop usually
2976 outweighs the cost of the extra unconditional jump
2977 outside the loop. */
2979 {
2980 rtx temp;
2987 }
2989 /* Include the BARRIER after INSN and copy the
2990 block after LOC. */
2995 /* All those insns are now in TARGET_LOOP. */
3001 /* The label jumped to by INSN is no longer a loop
3002 exit. Unless INSN does not have a label (e.g.,
3003 it is a RETURN insn), search loop->exit_labels
3004 to find its label_ref, and remove it. Also turn
3005 off LABEL_OUTSIDE_LOOP_P bit. */
3007 {
3009 r;
3012 {
3016 else
3019 }
3025 /* If we didn't find it, then something is
3026 wrong. */
3029 }
3031 /* P is now a jump outside the loop, so it must be put
3032 in loop->exit_labels, and marked as such.
3033 The easiest way to do this is to just call
3034 mark_loop_jump again for P. */
3037 /* If INSN now jumps to the insn after it,
3038 delete INSN. */
3043 }
3045 /* Continue the loop after where the conditional
3046 branch used to jump, since the only branch insn
3047 in the block (if it still remains) is an inter-loop
3048 branch and hence needs no processing. */
3054 /* This loop will be continued with NEXT_INSN (insn). */
3056 }
3057 }
3058 }
3059 }
3060 }
3062 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3063 loops it is contained in, mark the target loop invalid.
3065 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3067 static void
3069 {
3075 {
3087 /* There could be a label reference in here. */
3099 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3111 /* Link together all labels that branch outside the loop. This
3112 is used by final_[bg]iv_value and the loop unrolling code. Also
3113 mark this LABEL_REF so we know that this branch should predict
3114 false. */
3116 /* A check to make sure the label is not in an inner nested loop,
3117 since this does not count as a loop exit. */
3119 {
3124 }
3125 else
3129 {
3138 }
3140 /* If this is inside a loop, but not in the current loop or one enclosed
3141 by it, it invalidates at least one loop. */
3146 /* We must invalidate every nested loop containing the target of this
3147 label, except those that also contain the jump insn. */
3150 {
3151 /* Stop when we reach a loop that also contains the jump insn. */
3156 /* If we get here, we know we need to invalidate a loop. */
3163 }
3167 /* If this is not setting pc, ignore. */
3189 /* Strictly speaking this is not a jump into the loop, only a possible
3190 jump out of the loop. However, we have no way to link the destination
3191 of this jump onto the list of exit labels. To be safe we mark this
3192 loop and any containing loops as invalid. */
3194 {
3196 {
3202 }
3203 }
3205 }
3206 }
3207 \f
3208 /* Return nonzero if there is a label in the range from
3209 insn INSN to and including the insn whose luid is END
3210 INSN must have an assigned luid (i.e., it must not have
3211 been previously created by loop.c). */
3213 static int
3215 {
3217 {
3221 }
3224 }
3226 /* Record that a memory reference X is being set. */
3228 static void
3231 {
3237 /* Count number of memory writes.
3238 This affects heuristics in strength_reduce. */
3241 /* BLKmode MEM means all memory is clobbered. */
3243 {
3246 else
3250 }
3254 }
3256 /* X is a value modified by an INSN that references a biv inside a loop
3257 exit test (ie, X is somehow related to the value of the biv). If X
3258 is a pseudo that is used more than once, then the biv is (effectively)
3259 used more than once. DATA is a pointer to a loop_regs structure. */
3261 static void
3263 {
3278 /* If we do not have usage information, or if we know the register
3279 is used more than once, note that fact for check_dbra_loop. */
3284 }
3285 \f
3286 /* Return nonzero if the rtx X is invariant over the current loop.
3288 The value is 2 if we refer to something only conditionally invariant.
3290 A memory ref is invariant if it is not volatile and does not conflict
3291 with anything stored in `loop_info->store_mems'. */
3293 int
3295 {
3302 rtx mem_list_entry;
3308 {
3316 /* A LABEL_REF is normally invariant, however, if we are unrolling
3317 loops, and this label is inside the loop, then it isn't invariant.
3318 This is because each unrolled copy of the loop body will have
3319 a copy of this label. If this was invariant, then an insn loading
3320 the address of this label into a register might get moved outside
3321 the loop, and then each loop body would end up using the same label.
3323 We don't know the loop bounds here though, so just fail for all
3324 labels. */
3327 else
3336 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3337 since the reg might be set by initialization within the loop. */
3348 /* Out-of-range regs can occur when we are called from unrolling.
3349 These registers created by the unroller are set in the loop,
3350 hence are never invariant.
3351 Other out-of-range regs can be generated by load_mems; those that
3352 are written to in the loop are not invariant, while those that are
3353 not written to are invariant. It would be easy for load_mems
3354 to set n_times_set correctly for these registers, however, there
3355 is no easy way to distinguish them from registers created by the
3356 unroller. */
3367 /* Volatile memory references must be rejected. Do this before
3368 checking for read-only items, so that volatile read-only items
3369 will be rejected also. */
3373 /* See if there is any dependence between a store and this load. */
3376 {
3382 }
3384 /* It's not invalidated by a store in memory
3385 but we must still verify the address is invariant. */
3389 /* Don't mess with insns declared volatile. */
3396 }
3400 {
3402 {
3408 }
3410 {
3413 {
3419 }
3421 }
3422 }
3425 }
3426 \f
3427 /* Return nonzero if all the insns in the loop that set REG
3428 are INSN and the immediately following insns,
3429 and if each of those insns sets REG in an invariant way
3430 (not counting uses of REG in them).
3432 The value is 2 if some of these insns are only conditionally invariant.
3434 We assume that INSN itself is the first set of REG
3435 and that its source is invariant. */
3437 static int
3439 rtx insn)
3440 {
3444 rtx temp;
3445 /* Number of sets we have to insist on finding after INSN. */
3451 /* If N_SETS hit the limit, we can't rely on its value. */
3458 {
3460 rtx set;
3465 /* If library call, skip to end of it. */
3474 {
3479 {
3480 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3481 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3482 notes are OK. */
3488 }
3489 }
3491 count--;
3493 {
3496 }
3497 }
3500 /* If loop_invariant_p ever returned 2, we return 2. */
3502 }
3503 \f
3504 /* Look at all uses (not sets) of registers in X. For each, if it is
3505 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3506 a different insn, set USAGE[REGNO] to const0_rtx. */
3508 static void
3510 {
3522 {
3523 /* Don't count SET_DEST if it is a REG; otherwise count things
3524 in SET_DEST because if a register is partially modified, it won't
3525 show up as a potential movable so we don't care how USAGE is set
3526 for it. */
3530 }
3531 else
3533 {
3539 }
3540 }
3541 \f
3542 /* Count and record any set in X which is contained in INSN. Update
3543 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3544 in X. */
3546 static void
3548 {
3550 /* Don't move a reg that has an explicit clobber.
3551 It's not worth the pain to try to do it correctly. */
3555 {
3563 {
3567 {
3568 /* If this is the first setting of this reg
3569 in current basic block, and it was set before,
3570 it must be set in two basic blocks, so it cannot
3571 be moved out of the loop. */
3575 /* If this is not first setting in current basic block,
3576 see if reg was used in between previous one and this.
3577 If so, neither one can be moved. */
3584 }
3585 }
3586 }
3587 }
3588 \f
3589 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3590 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3591 contained in insn INSN is used by any insn that precedes INSN in
3592 cyclic order starting from the loop entry point.
3594 We don't want to use INSN_LUID here because if we restrict INSN to those
3595 that have a valid INSN_LUID, it means we cannot move an invariant out
3596 from an inner loop past two loops. */
3598 static int
3600 {
3602 rtx p;
3604 /* Scan forward checking for register usage. If we hit INSN, we
3605 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3607 {
3613 }
3616 }
3617 \f
3619 /* Information we collect about arrays that we might want to prefetch. */
3620 struct prefetch_info
3621 {
3625 index. */
3626 HOST_WIDE_INT index;
3628 iteration. */
3630 prefetch area in one iteration. */
3632 This is set only for loops with known
3633 iteration counts and is 0xffffffff
3634 otherwise. */
3638 };
3640 /* Data used by check_store function. */
3641 struct check_store_data
3642 {
3643 rtx mem_address;
3645 };
3651 /* Set mem_write when mem_address is found. Used as callback to
3652 note_stores. */
3653 static void
3655 {
3660 }
3661 \f
3662 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3663 important to get some addresses combined. Later more sophisticated
3664 transformations can be added when necessary.
3666 ??? Same trick with swapping operand is done at several other places.
3667 It can be nice to develop some common way to handle this. */
3669 static int
3671 {
3683 {
3688 }
3690 /* Compare the elements. If any pair of corresponding elements fails to
3691 match, return 0 for the whole thing. */
3695 {
3697 {
3709 /* Two vectors must have the same length. */
3713 /* And the corresponding elements must match. */
3731 /* These are just backpointers, so they don't matter. */
3737 /* It is believed that rtx's at this level will never
3738 contain anything but integers and other rtx's,
3739 except for within LABEL_REFs and SYMBOL_REFs. */
3742 }
3743 }
3745 }
3746 \f
3747 /* Remove constant addition value from the expression X (when present)
3748 and return it. */
3750 static HOST_WIDE_INT
3752 {
3756 /* Avoid clobbering a shared CONST expression. */
3758 {
3762 {
3765 }
3767 }
3770 {
3773 }
3775 /* For plus expression recurse on ourself. */
3777 {
3781 /* In case our parameter was constant, remove extra zero from the
3782 expression. */
3787 }
3790 }
3792 /* Attempt to identify accesses to arrays that are most likely to cause cache
3793 misses, and emit prefetch instructions a few prefetch blocks forward.
3795 To detect the arrays we use the GIV information that was collected by the
3796 strength reduction pass.
3798 The prefetch instructions are generated after the GIV information is done
3799 and before the strength reduction process. The new GIVs are injected into
3800 the strength reduction tables, so the prefetch addresses are optimized as
3801 well.
3803 GIVs are split into base address, stride, and constant addition values.
3804 GIVs with the same address, stride and close addition values are combined
3805 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3806 for write instructions can be used for the block we write to, on machines
3807 that support write prefetches.
3809 Several heuristics are used to determine when to prefetch. They are
3810 controlled by defined symbols that can be overridden for each target. */
3812 static void
3814 {
3830 /* Consider only loops w/o calls. When a call is done, the loop is probably
3831 slow enough to read the memory. */
3833 {
3838 }
3840 /* Don't prefetch in loops known to have few iterations. */
3844 {
3849 }
3851 /* Search all induction variables and pick those interesting for the prefetch
3852 machinery. */
3854 {
3860 /* Expect all BIVs to be executed in each iteration. This makes our
3861 analysis more conservative. */
3863 {
3864 /* Discard non-constant additions that we can't handle well yet, and
3865 BIVs that are executed multiple times; such BIVs ought to be
3866 handled in the nested loop. We accept not_every_iteration BIVs,
3867 since these only result in larger strides and make our
3868 heuristics more conservative. */
3870 {
3872 {
3878 }
3880 }
3883 {
3885 {
3891 }
3893 }
3897 }
3903 {
3904 rtx address;
3905 rtx temp;
3914 /* See whether an induction variable is interesting to us and if
3915 not, report the reason. */
3919 /* We are interested only in constant stride memory references
3920 in order to be able to compute density easily. */
3924 else
3925 {
3928 {
3931 }
3933 /* On some targets, reversed order prefetches are not
3934 worthwhile. */
3938 /* Prefetch of accesses with an extreme stride might not be
3939 worthwhile, either. */
3944 /* Ignore GIVs with varying add values; we can't predict the
3945 value for the next iteration. */
3949 /* Ignore GIVs in the nested loops; they ought to have been
3950 handled already. */
3953 }
3956 {
3962 }
3964 /* Determine the pointer to the basic array we are examining. It is
3965 the sum of the BIV's initial value and the GIV's add_val. */
3975 /* When the GIV is not always executed, we might be better off by
3976 not dirtying the cache pages. */
3979 else
3980 {
3985 }
3987 /* Attempt to find another prefetch to the same array and see if we
3988 can merge this one. */
3992 {
3993 /* In case both access same array (same location
3994 just with small difference in constant indexes), merge
3995 the prefetches. Just do the later and the earlier will
3996 get prefetched from previous iteration.
3997 The artificial threshold should not be too small,
3998 but also not bigger than small portion of memory usually
3999 traversed by single loop. */
4002 {
4011 }
4015 {
4020 }
4021 }
4023 /* Merging failed. */
4025 {
4033 num_prefetches++;
4035 {
4040 }
4041 }
4042 }
4043 }
4046 {
4049 /* Attempt to calculate the total number of bytes fetched by all
4050 iterations of the loop. Avoid overflow. */
4055 else
4060 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4065 {
4070 }
4071 else
4072 {
4078 }
4079 else
4082 /* Find how many prefetch instructions we'll use within the loop. */
4084 {
4090 }
4091 }
4093 /* Determine how many iterations ahead to prefetch within the loop, based
4094 on how many prefetches we currently expect to do within the loop. */
4096 {
4098 {
4104 }
4105 }
4106 /* We'll also use AHEAD to determine how many prefetch instructions to
4107 emit before a loop, so don't leave it zero. */
4112 {
4113 /* Update if we've decided not to prefetch anything within the loop. */
4117 /* Find how many prefetch instructions we'll use before the loop. */
4119 {
4127 }
4130 {
4150 }
4151 }
4154 {
4155 /* Record that this loop uses prefetch instructions. */
4159 {
4164 }
4165 }
4168 {
4172 {
4174 rtx insn;
4178 rtx seq;
4180 /* We can save some effort by offsetting the address on
4181 architectures with offsettable memory references. */
4184 else
4185 {
4191 }
4194 /* Make sure the address operand is valid for prefetch. */
4204 /* Check all insns emitted and record the new GIV
4205 information. */
4208 {
4213 }
4214 }
4217 {
4218 /* Emit insns before the loop to fetch the first cache lines or,
4219 if we're not prefetching within the loop, everything we expect
4220 to need. */
4222 {
4230 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4231 non-constant INIT_VAL to have the same mode as REG, which
4232 in this case we know to be Pmode. */
4234 {
4235 rtx seq;
4242 }
4248 loop_start);
4249 }
4250 }
4251 }
4254 }
4255 \f
4256 /* Communication with routines called via `note_stores'. */
4260 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4264 /* ??? Unfinished optimizations, and possible future optimizations,
4265 for the strength reduction code. */
4267 /* ??? The interaction of biv elimination, and recognition of 'constant'
4268 bivs, may cause problems. */
4270 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4271 performance problems.
4273 Perhaps don't eliminate things that can be combined with an addressing
4274 mode. Find all givs that have the same biv, mult_val, and add_val;
4275 then for each giv, check to see if its only use dies in a following
4276 memory address. If so, generate a new memory address and check to see
4277 if it is valid. If it is valid, then store the modified memory address,
4278 otherwise, mark the giv as not done so that it will get its own iv. */
4280 /* ??? Could try to optimize branches when it is known that a biv is always
4281 positive. */
4283 /* ??? When replace a biv in a compare insn, we should replace with closest
4284 giv so that an optimized branch can still be recognized by the combiner,
4285 e.g. the VAX acb insn. */
4287 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4288 was rerun in loop_optimize whenever a register was added or moved.
4289 Also, some of the optimizations could be a little less conservative. */
4290 \f
4291 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4292 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4293 callback.
4295 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4296 least once for every loop iteration except for the last one.
4298 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4299 loop iteration.
4300 */
4301 void
4303 {
4308 rtx p;
4310 /* If loop_scan_start points to the loop exit test, we have to be wary of
4311 subversive use of gotos inside expression statements. */
4315 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4319 {
4322 /* Past CODE_LABEL, we get to insns that may be executed multiple
4323 times. The only way we can be sure that they can't is if every
4324 jump insn between here and the end of the loop either
4325 returns, exits the loop, is a jump to a location that is still
4326 behind the label, or is a jump to the loop start. */
4329 {
4335 {
4340 {
4343 else
4347 }
4355 {
4358 }
4359 }
4360 }
4362 /* Past a jump, we get to insns for which we can't count
4363 on whether they will be executed during each iteration. */
4364 /* This code appears twice in strength_reduce. There is also similar
4365 code in scan_loop. */
4367 /* If we enter the loop in the middle, and scan around to the
4368 beginning, don't set not_every_iteration for that.
4369 This can be any kind of jump, since we want to know if insns
4370 will be executed if the loop is executed. */
4375 {
4378 /* If this is a jump outside the loop, then it also doesn't
4379 matter. Check to see if the target of this branch is on the
4380 loop->exits_labels list. */
4388 }
4391 {
4392 /* At the virtual top of a converted loop, insns are again known to
4393 be executed each iteration: logically, the loop begins here
4394 even though the exit code has been duplicated.
4396 Insns are also again known to be executed each iteration at
4397 the LOOP_CONT note. */
4403 loop_depth++;
4405 loop_depth--;
4406 }
4408 /* Note if we pass a loop latch. If we do, then we can not clear
4409 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4410 a loop since a jump before the last CODE_LABEL may have started
4411 a new loop iteration.
4413 Note that LOOP_TOP is only set for rotated loops and we need
4414 this check for all loops, so compare against the CODE_LABEL
4415 which immediately follows LOOP_START. */
4420 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4421 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4422 or not an insn is known to be executed each iteration of the
4423 loop, whether or not any iterations are known to occur.
4425 Therefore, if we have just passed a label and have no more labels
4426 between here and the test insn of the loop, and we have not passed
4427 a jump to the top of the loop, then we know these insns will be
4428 executed each iteration. */
4431 && !past_loop_latch
4436 }
4437 }
4438 \f
4439 static void
4441 {
4444 /* Temporary list pointers for traversing ivs->list. */
4451 /* Scan ivs->list to remove all regs that proved not to be bivs.
4452 Make a sanity check against regs->n_times_set. */
4454 {
4456 /* Above happens if register modified by subreg, etc. */
4457 /* Make sure it is not recognized as a basic induction var: */
4459 /* If never incremented, it is invariant that we decided not to
4460 move. So leave it alone. */
4462 {
4473 }
4474 else
4475 {
4480 }
4481 }
4482 }
4485 /* Determine how BIVS are initialized by looking through pre-header
4486 extended basic block. */
4487 static void
4489 {
4491 /* Temporary list pointers for traversing ivs->list. */
4494 rtx p;
4496 /* Find initial value for each biv by searching backwards from loop_start,
4497 halting at first label. Also record any test condition. */
4501 {
4502 rtx test;
4512 /* Record any test of a biv that branches around the loop if no store
4513 between it and the start of loop. We only care about tests with
4514 constants and registers and only certain of those. */
4524 {
4525 /* If an NE test, we have an initial value! */
4527 {
4531 }
4532 else
4534 }
4535 }
4536 }
4539 /* Look at the each biv and see if we can say anything better about its
4540 initial value from any initializing insns set up above. (This is done
4541 in two passes to avoid missing SETs in a PARALLEL.) */
4542 static void
4544 {
4546 /* Temporary list pointers for traversing ivs->list. */
4551 {
4552 rtx src;
4553 rtx note;
4558 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4559 is a constant, use the value of that. */
4565 else
4578 {
4582 {
4585 }
4586 }
4587 /* If we can't make it a giv,
4588 let biv keep initial value of "itself". */
4591 }
4592 }
4595 /* Search the loop for general induction variables. */
4597 static void
4599 {
4601 }
4604 /* For each giv for which we still don't know whether or not it is
4605 replaceable, check to see if it is replaceable because its final value
4606 can be calculated. */
4608 static void
4610 {
4615 {
4621 }
4622 }
4625 /* Return nonzero if it is possible to eliminate the biv BL provided
4626 all givs are reduced. This is possible if either the reg is not
4627 used outside the loop, or we can compute what its final value will
4628 be. */
4630 static int
4633 {
4634 /* For architectures with a decrement_and_branch_until_zero insn,
4635 don't do this if we put a REG_NONNEG note on the endtest for this
4636 biv. */
4638 #ifdef HAVE_decrement_and_branch_until_zero
4640 {
4645 }
4646 #endif
4648 /* Check that biv is used outside loop or if it has a final value.
4649 Compare against bl->init_insn rather than loop->start. We aren't
4650 concerned with any uses of the biv between init_insn and
4651 loop->start since these won't be affected by the value of the biv
4652 elsewhere in the function, so long as init_insn doesn't use the
4653 biv itself. */
4664 {
4672 }
4674 }
4677 /* Reduce each giv of BL that we have decided to reduce. */
4679 static void
4681 {
4685 {
4688 {
4691 /* If the code for derived givs immediately below has already
4692 allocated a new_reg, we must keep it. */
4696 #ifdef AUTO_INC_DEC
4697 /* If the target has auto-increment addressing modes, and
4698 this is an address giv, then try to put the increment
4699 immediately after its use, so that flow can create an
4700 auto-increment addressing mode. */
4701 /* Don't do this for loops entered at the bottom, to avoid
4702 this invalid transformation:
4703 jmp L; -> jmp L;
4704 TOP: TOP:
4705 use giv use giv
4706 L: inc giv
4707 inc biv L:
4708 test biv test giv
4709 cbr TOP cbr TOP
4710 */
4713 /* We don't handle reversed biv's because bl->biv->insn
4714 does not have a valid INSN_LUID. */
4719 {
4720 /* If other giv's have been combined with this one, then
4721 this will work only if all uses of the other giv's occur
4722 before this giv's insn. This is difficult to check.
4724 We simplify this by looking for the common case where
4725 there is one DEST_REG giv, and this giv's insn is the
4726 last use of the dest_reg of that DEST_REG giv. If the
4727 increment occurs after the address giv, then we can
4728 perform the optimization. (Otherwise, the increment
4729 would have to go before other_giv, and we would not be
4730 able to combine it with the address giv to get an
4731 auto-inc address.) */
4733 {
4738 {
4741 else
4743 }
4750 }
4751 /* Check for case where increment is before the address
4752 giv. Do this test in "loop order". */
4761 else
4764 #ifdef HAVE_cc0
4765 {
4766 rtx prev;
4768 /* We can't put an insn immediately after one setting
4769 cc0, or immediately before one using cc0. */
4776 }
4777 #endif
4781 }
4782 #endif
4784 /* For each place where the biv is incremented, add an insn
4785 to increment the new, reduced reg for the giv. */
4787 {
4788 rtx insert_before;
4790 /* Skip if location is the same as a previous one. */
4797 else
4805 /* A multiply is acceptable here
4806 since this is presumed to be seldom executed. */
4810 }
4812 /* Add code at loop start to initialize giv's reduced reg. */
4817 }
4818 }
4819 }
4822 /* Check for givs whose first use is their definition and whose
4823 last use is the definition of another giv. If so, it is likely
4824 dead and should not be used to derive another giv nor to
4825 eliminate a biv. */
4827 static void
4829 {
4833 {
4840 {
4846 }
4847 }
4848 }
4851 static void
4853 {
4857 {
4864 /* Update expression if this was combined, in case other giv was
4865 replaced. */
4870 /* See if this register is known to be a pointer to something. If
4871 so, see if we can find the alignment. First see if there is a
4872 destination register that is a pointer. If so, this shares the
4873 alignment too. Next see if we can deduce anything from the
4874 computational information. If not, and this is a DEST_ADDR
4875 giv, at least we know that it's a pointer, though we don't know
4876 the alignment. */
4884 {
4893 }
4897 {
4905 }
4910 /* Store reduced reg as the address in the memref where we found
4911 this giv. */
4914 {
4916 }
4917 else
4918 {
4920 rtx note;
4922 /* Not replaceable; emit an insn to set the original giv reg from
4923 the reduced giv, same as above. */
4928 /* The original insn may have a REG_EQUAL note. This note is
4929 now incorrect and may result in invalid substitutions later.
4930 The original insn is dead, but may be part of a libcall
4931 sequence, which doesn't seem worth the bother of handling. */
4935 }
4937 /* When a loop is reversed, givs which depend on the reversed
4938 biv, and which are live outside the loop, must be set to their
4939 correct final value. This insn is only needed if the giv is
4940 not replaceable. The correct final value is the same as the
4941 value that the giv starts the reversed loop with. */
4952 {
4957 }
4958 }
4959 }
4962 static int
4965 rtx test_reg)
4966 {
4975 /* Reduce benefit if not replaceable, since we will insert a
4976 move-insn to replace the insn that calculates this giv. Don't do
4977 this unless the giv is a user variable, since it will often be
4978 marked non-replaceable because of the duplication of the exit
4979 code outside the loop. In such a case, the copies we insert are
4980 dead and will be deleted. So they don't have a cost. Similar
4981 situations exist. */
4982 /* ??? The new final_[bg]iv_value code does a much better job of
4983 finding replaceable giv's, and hence this code may no longer be
4984 necessary. */
4989 /* Decrease the benefit to count the add-insns that we will insert
4990 to increment the reduced reg for the giv. ??? This can
4991 overestimate the run-time cost of the additional insns, e.g. if
4992 there are multiple basic blocks that increment the biv, but only
4993 one of these blocks is executed during each iteration. There is
4994 no good way to detect cases like this with the current structure
4995 of the loop optimizer. This code is more accurate for
4996 determining code size than run-time benefits. */
4999 /* Decide whether to strength-reduce this giv or to leave the code
5000 unchanged (recompute it from the biv each time it is used). This
5001 decision can be made independently for each giv. */
5003 #ifdef AUTO_INC_DEC
5004 /* Attempt to guess whether autoincrement will handle some of the
5005 new add insns; if so, increase BENEFIT (undo the subtraction of
5006 add_cost that was done above). */
5008 /* Increasing the benefit is risky, since this is only a guess.
5009 Avoid increasing register pressure in cases where there would
5010 be no other benefit from reducing this giv. */
5013 {
5028 }
5029 #endif
5032 }
5035 /* Free IV structures for LOOP. */
5037 static void
5039 {
5046 {
5052 {
5055 }
5057 {
5060 }
5064 }
5065 }
5068 /* Perform strength reduction and induction variable elimination.
5070 Pseudo registers created during this function will be beyond the
5071 last valid index in several tables including
5072 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5073 problem here, because the added registers cannot be givs outside of
5074 their loop, and hence will never be reconsidered. But scan_loop
5075 must check regnos to make sure they are in bounds. */
5077 static void
5079 {
5083 rtx p;
5084 /* Temporary list pointer for traversing ivs->list. */
5086 /* Ratio of extra register life span we can justify
5087 for saving an instruction. More if loop doesn't call subroutines
5088 since in that case saving an insn makes more difference
5089 and more registers are available. */
5090 /* ??? could set this to last value of threshold in move_movables */
5092 /* Map of pseudo-register replacements. */
5104 /* Find all BIVs in loop. */
5107 /* Exit if there are no bivs. */
5109 {
5110 /* Can still unroll the loop anyways, but indicate that there is no
5111 strength reduction info available. */
5117 }
5119 /* Determine how BIVS are initialized by looking through pre-header
5120 extended basic block. */
5123 /* Look at the each biv and see if we can say anything better about its
5124 initial value from any initializing insns set up above. */
5127 /* Search the loop for general induction variables. */
5130 /* Try to calculate and save the number of loop iterations. This is
5131 set to zero if the actual number can not be calculated. This must
5132 be called after all giv's have been identified, since otherwise it may
5133 fail if the iteration variable is a giv. */
5136 #ifdef HAVE_prefetch
5139 #endif
5141 /* Now for each giv for which we still don't know whether or not it is
5142 replaceable, check to see if it is replaceable because its final value
5143 can be calculated. This must be done after loop_iterations is called,
5144 so that final_giv_value will work correctly. */
5147 /* Try to prove that the loop counter variable (if any) is always
5148 nonnegative; if so, record that fact with a REG_NONNEG note
5149 so that "decrement and branch until zero" insn can be used. */
5152 /* Create reg_map to hold substitutions for replaceable giv regs.
5153 Some givs might have been made from biv increments, so look at
5154 ivs->reg_iv_type for a suitable size. */
5158 /* Examine each iv class for feasibility of strength reduction/induction
5159 variable elimination. */
5162 {
5166 /* Test whether it will be possible to eliminate this biv
5167 provided all givs are reduced. */
5170 /* This will be true at the end, if all givs which depend on this
5171 biv have been strength reduced.
5172 We can't (currently) eliminate the biv unless this is so. */
5175 /* Check each extension dependent giv in this class to see if its
5176 root biv is safe from wrapping in the interior mode. */
5179 /* Combine all giv's for this iv_class. */
5183 {
5191 /* If an insn is not to be strength reduced, then set its ignore
5192 flag, and clear bl->all_reduced. */
5194 /* A giv that depends on a reversed biv must be reduced if it is
5195 used after the loop exit, otherwise, it would have the wrong
5196 value after the loop exit. To make it simple, just reduce all
5197 of such giv's whether or not we know they are used after the loop
5198 exit. */
5203 {
5211 }
5212 else
5213 {
5214 /* Check that we can increment the reduced giv without a
5215 multiply insn. If not, reject it. */
5220 {
5228 }
5229 }
5230 }
5232 /* Check for givs whose first use is their definition and whose
5233 last use is the definition of another giv. If so, it is likely
5234 dead and should not be used to derive another giv nor to
5235 eliminate a biv. */
5238 /* Reduce each giv that we decided to reduce. */
5241 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5242 as not reduced.
5244 For each giv register that can be reduced now: if replaceable,
5245 substitute reduced reg wherever the old giv occurs;
5246 else add new move insn "giv_reg = reduced_reg". */
5249 /* All the givs based on the biv bl have been reduced if they
5250 merit it. */
5252 /* For each giv not marked as maybe dead that has been combined with a
5253 second giv, clear any "maybe dead" mark on that second giv.
5254 v->new_reg will either be or refer to the register of the giv it
5255 combined with.
5257 Doing this clearing avoids problems in biv elimination where
5258 a giv's new_reg is a complex value that can't be put in the
5259 insn but the giv combined with (with a reg as new_reg) is
5260 marked maybe_dead. Since the register will be used in either
5261 case, we'd prefer it be used from the simpler giv. */
5267 /* Try to eliminate the biv, if it is a candidate.
5268 This won't work if ! bl->all_reduced,
5269 since the givs we planned to use might not have been reduced.
5271 We have to be careful that we didn't initially think we could
5272 eliminate this biv because of a giv that we now think may be
5273 dead and shouldn't be used as a biv replacement.
5275 Also, there is the possibility that we may have a giv that looks
5276 like it can be used to eliminate a biv, but the resulting insn
5277 isn't valid. This can happen, for example, on the 88k, where a
5278 JUMP_INSN can compare a register only with zero. Attempts to
5279 replace it with a compare with a constant will fail.
5281 Note that in cases where this call fails, we may have replaced some
5282 of the occurrences of the biv with a giv, but no harm was done in
5283 doing so in the rare cases where it can occur. */
5287 {
5288 /* ?? If we created a new test to bypass the loop entirely,
5289 or otherwise drop straight in, based on this test, then
5290 we might want to rewrite it also. This way some later
5291 pass has more hope of removing the initialization of this
5292 biv entirely. */
5294 /* If final_value != 0, then the biv may be used after loop end
5295 and we must emit an insn to set it just in case.
5297 Reversed bivs already have an insn after the loop setting their
5298 value, so we don't need another one. We can't calculate the
5299 proper final value for such a biv here anyways. */
5308 }
5309 /* See above note wrt final_value. But since we couldn't eliminate
5310 the biv, we must set the value after the loop instead of before. */
5314 }
5316 /* Go through all the instructions in the loop, making all the
5317 register substitutions scheduled in REG_MAP. */
5321 {
5325 }
5328 {
5329 /* When we completely unroll a loop we will likely not need the increment
5330 of the loop BIV and we will not need the conditional branch at the
5331 end of the loop. */
5334 #ifdef HAVE_cc0
5335 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5336 need the comparison before the conditional branch at the end of the
5337 loop. */
5339 #endif
5341 /* We'll need one copy for each loop iteration. */
5344 /* A little slop to account for the ability to remove initialization
5345 code, better CSE, and other secondary benefits of completely
5346 unrolling some loops. */
5349 /* Clamp the value. */
5352 }
5354 /* Unroll loops from within strength reduction so that we can use the
5355 induction variable information that strength_reduce has already
5356 collected. Always unroll loops that would be as small or smaller
5357 unrolled than when rolled. */
5370 }
5371 \f
5372 /*Record all basic induction variables calculated in the insn. */
5373 static rtx
5376 {
5378 rtx set;
5379 rtx dest_reg;
5380 rtx inc_val;
5381 rtx mult_val;
5387 {
5392 {
5397 {
5398 /* It is a possible basic induction variable.
5399 Create and initialize an induction structure for it. */
5406 }
5409 }
5410 }
5412 }
5413 \f
5414 /* Record all givs calculated in the insn.
5415 A register is a giv if: it is only set once, it is a function of a
5416 biv and a constant (or invariant), and it is not a biv. */
5417 static rtx
5420 {
5423 rtx set;
5424 /* Look for a general induction variable in a register. */
5429 {
5430 rtx src_reg;
5431 rtx dest_reg;
5432 rtx add_val;
5433 rtx mult_val;
5434 rtx ext_val;
5437 rtx last_consec_insn;
5446 /* Equivalent expression is a giv. */
5451 /* Don't try to handle any regs made by loop optimization.
5452 We have nothing on them in regno_first_uid, etc. */
5454 /* Don't recognize a BASIC_INDUCT_VAR here. */
5456 /* This must be the only place where the register is set. */
5458 /* or all sets must be consecutive and make a giv. */
5463 {
5466 /* If this is a library call, increase benefit. */
5470 /* Skip the consecutive insns, if there are any. */
5478 }
5479 }
5481 /* Look for givs which are memory addresses. */
5484 maybe_multiple);
5486 /* Update the status of whether giv can derive other givs. This can
5487 change when we pass a label or an insn that updates a biv. */
5491 }
5492 \f
5493 /* Return 1 if X is a valid source for an initial value (or as value being
5494 compared against in an initial test).
5496 X must be either a register or constant and must not be clobbered between
5497 the current insn and the start of the loop.
5499 INSN is the insn containing X. */
5501 static int
5503 {
5507 /* Only consider pseudos we know about initialized in insns whose luids
5508 we know. */
5513 /* Don't use call-clobbered registers across a call which clobbers it. On
5514 some machines, don't use any hard registers at all. */
5516 && (SMALL_REGISTER_CLASSES
5520 /* Don't use registers that have been clobbered before the start of the
5521 loop. */
5526 }
5527 \f
5528 /* Scan X for memory refs and check each memory address
5529 as a possible giv. INSN is the insn whose pattern X comes from.
5530 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5531 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5532 more than once in each loop iteration. */
5534 static void
5537 {
5547 {
5563 {
5564 rtx src_reg;
5565 rtx add_val;
5566 rtx mult_val;
5567 rtx ext_val;
5570 /* This code used to disable creating GIVs with mult_val == 1 and
5571 add_val == 0. However, this leads to lost optimizations when
5572 it comes time to combine a set of related DEST_ADDR GIVs, since
5573 this one would not be seen. */
5578 {
5579 /* Found one; record it. */
5587 }
5588 }
5593 }
5595 /* Recursively scan the subexpressions for other mem refs. */
5601 maybe_multiple);
5605 maybe_multiple);
5606 }
5607 \f
5608 /* Fill in the data about one biv update.
5609 V is the `struct induction' in which we record the biv. (It is
5610 allocated by the caller, with alloca.)
5611 INSN is the insn that sets it.
5612 DEST_REG is the biv's reg.
5614 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5615 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5616 being set to INC_VAL.
5618 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5619 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5620 can be executed more than once per iteration. If MAYBE_MULTIPLE
5621 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5622 executed exactly once per iteration. */
5624 static void
5628 {
5645 /* Add this to the reg's iv_class, creating a class
5646 if this is the first incrementation of the reg. */
5650 {
5651 /* Create and initialize new iv_class. */
5661 /* Set initial value to the reg itself. */
5664 /* We haven't seen the initializing insn yet. */
5674 /* Add this class to ivs->list. */
5678 /* Put it in the array of biv register classes. */
5680 }
5681 else
5682 {
5683 /* Check if location is the same as a previous one. */
5687 {
5690 }
5691 }
5693 /* Update IV_CLASS entry for this biv. */
5702 }
5703 \f
5704 /* Fill in the data about one giv.
5705 V is the `struct induction' in which we record the giv. (It is
5706 allocated by the caller, with alloca.)
5707 INSN is the insn that sets it.
5708 BENEFIT estimates the savings from deleting this insn.
5709 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5710 into a register or is used as a memory address.
5712 SRC_REG is the biv reg which the giv is computed from.
5713 DEST_REG is the giv's reg (if the giv is stored in a reg).
5714 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5715 LOCATION points to the place where this giv's value appears in INSN. */
5717 static void
5722 {
5727 rtx temp;
5729 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5730 undo the MULT canonicalization that we performed earlier. */
5760 /* The v->always_computable field is used in update_giv_derive, to
5761 determine whether a giv can be used to derive another giv. For a
5762 DEST_REG giv, INSN computes a new value for the giv, so its value
5763 isn't computable if INSN insn't executed every iteration.
5764 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5765 it does not compute a new value. Hence the value is always computable
5766 regardless of whether INSN is executed each iteration. */
5770 else
5776 {
5779 }
5781 {
5786 /* If the lifetime is zero, it means that this register is
5787 really a dead store. So mark this as a giv that can be
5788 ignored. This will not prevent the biv from being eliminated. */
5794 }
5796 /* Add the giv to the class of givs computed from one biv. */
5800 {
5803 /* Don't count DEST_ADDR. This is supposed to count the number of
5804 insns that calculate givs. */
5808 }
5809 else
5810 /* Fatal error, biv missing for this giv? */
5814 {
5817 }
5818 else
5819 {
5820 /* The giv can be replaced outright by the reduced register only if all
5821 of the following conditions are true:
5822 - the insn that sets the giv is always executed on any iteration
5823 on which the giv is used at all
5824 (there are two ways to deduce this:
5825 either the insn is executed on every iteration,
5826 or all uses follow that insn in the same basic block),
5827 - the giv is not used outside the loop
5828 - no assignments to the biv occur during the giv's lifetime. */
5831 /* Previous line always fails if INSN was moved by loop opt. */
5834 && (! not_every_iteration
5836 {
5837 /* Now check that there are no assignments to the biv within the
5838 giv's lifetime. This requires two separate checks. */
5840 /* Check each biv update, and fail if any are between the first
5841 and last use of the giv.
5843 If this loop contains an inner loop that was unrolled, then
5844 the insn modifying the biv may have been emitted by the loop
5845 unrolling code, and hence does not have a valid luid. Just
5846 mark the biv as not replaceable in this case. It is not very
5847 useful as a biv, because it is used in two different loops.
5848 It is very unlikely that we would be able to optimize the giv
5849 using this biv anyways. */
5854 {
5860 {
5864 }
5865 }
5867 /* If there are any backwards branches that go from after the
5868 biv update to before it, then this giv is not replaceable. */
5872 {
5876 }
5877 }
5878 else
5879 {
5880 /* May still be replaceable, we don't have enough info here to
5881 decide. */
5884 }
5885 }
5887 /* Record whether the add_val contains a const_int, for later use by
5888 combine_givs. */
5889 {
5894 ;
5898 {
5900 {
5905 else
5907 }
5910 }
5911 }
5915 }
5917 /* All this does is determine whether a giv can be made replaceable because
5918 its final value can be calculated. This code can not be part of record_giv
5919 above, because final_giv_value requires that the number of loop iterations
5920 be known, and that can not be accurately calculated until after all givs
5921 have been identified. */
5923 static void
5925 {
5928 /* DEST_ADDR givs will never reach here, because they are always marked
5929 replaceable above in record_giv. */
5931 /* The giv can be replaced outright by the reduced register only if all
5932 of the following conditions are true:
5933 - the insn that sets the giv is always executed on any iteration
5934 on which the giv is used at all
5935 (there are two ways to deduce this:
5936 either the insn is executed on every iteration,
5937 or all uses follow that insn in the same basic block),
5938 - its final value can be calculated (this condition is different
5939 than the one above in record_giv)
5940 - it's not used before the it's set
5941 - no assignments to the biv occur during the giv's lifetime. */
5943 #if 0
5944 /* This is only called now when replaceable is known to be false. */
5945 /* Clear replaceable, so that it won't confuse final_giv_value. */
5947 #endif
5952 {
5955 rtx last_giv_use;
5960 /* When trying to determine whether or not a biv increment occurs
5961 during the lifetime of the giv, we can ignore uses of the variable
5962 outside the loop because final_value is true. Hence we can not
5963 use regno_last_uid and regno_first_uid as above in record_giv. */
5965 /* Search the loop to determine whether any assignments to the
5966 biv occur during the giv's lifetime. Start with the insn
5967 that sets the giv, and search around the loop until we come
5968 back to that insn again.
5970 Also fail if there is a jump within the giv's lifetime that jumps
5971 to somewhere outside the lifetime but still within the loop. This
5972 catches spaghetti code where the execution order is not linear, and
5973 hence the above test fails. Here we assume that the giv lifetime
5974 does not extend from one iteration of the loop to the next, so as
5975 to make the test easier. Since the lifetime isn't known yet,
5976 this requires two loops. See also record_giv above. */
5981 {
5984 {
5987 }
5992 {
5993 /* It is possible for the BIV increment to use the GIV if we
5994 have a cycle. Thus we must be sure to check each insn for
5995 both BIV and GIV uses, and we must check for BIV uses
5996 first. */
6003 {
6005 {
6009 }
6011 }
6012 }
6013 }
6015 /* Now that the lifetime of the giv is known, check for branches
6016 from within the lifetime to outside the lifetime if it is still
6017 replaceable. */
6020 {
6023 {
6036 {
6045 }
6046 }
6047 }
6049 /* If it is replaceable, then save the final value. */
6052 }
6057 }
6058 \f
6059 /* Update the status of whether a giv can derive other givs.
6061 We need to do something special if there is or may be an update to the biv
6062 between the time the giv is defined and the time it is used to derive
6063 another giv.
6065 In addition, a giv that is only conditionally set is not allowed to
6066 derive another giv once a label has been passed.
6068 The cases we look at are when a label or an update to a biv is passed. */
6070 static void
6072 {
6076 rtx tem;
6079 /* Search all IV classes, then all bivs, and finally all givs.
6081 There are three cases we are concerned with. First we have the situation
6082 of a giv that is only updated conditionally. In that case, it may not
6083 derive any givs after a label is passed.
6085 The second case is when a biv update occurs, or may occur, after the
6086 definition of a giv. For certain biv updates (see below) that are
6087 known to occur between the giv definition and use, we can adjust the
6088 giv definition. For others, or when the biv update is conditional,
6089 we must prevent the giv from deriving any other givs. There are two
6090 sub-cases within this case.
6092 If this is a label, we are concerned with any biv update that is done
6093 conditionally, since it may be done after the giv is defined followed by
6094 a branch here (actually, we need to pass both a jump and a label, but
6095 this extra tracking doesn't seem worth it).
6097 If this is a jump, we are concerned about any biv update that may be
6098 executed multiple times. We are actually only concerned about
6099 backward jumps, but it is probably not worth performing the test
6100 on the jump again here.
6102 If this is a biv update, we must adjust the giv status to show that a
6103 subsequent biv update was performed. If this adjustment cannot be done,
6104 the giv cannot derive further givs. */
6110 {
6111 /* Skip if location is the same as a previous one. */
6116 {
6117 /* If cant_derive is already true, there is no point in
6118 checking all of these conditions again. */
6122 /* If this giv is conditionally set and we have passed a label,
6123 it cannot derive anything. */
6127 /* Skip givs that have mult_val == 0, since
6128 they are really invariants. Also skip those that are
6129 replaceable, since we know their lifetime doesn't contain
6130 any biv update. */
6134 /* The only way we can allow this giv to derive another
6135 is if this is a biv increment and we can form the product
6136 of biv->add_val and giv->mult_val. In this case, we will
6137 be able to compute a compensation. */
6139 {
6140 rtx ext_val_dummy;
6151 tem = simplify_giv_expr
6158 else
6160 }
6164 }
6165 }
6166 }
6167 \f
6168 /* Check whether an insn is an increment legitimate for a basic induction var.
6169 X is the source of insn P, or a part of it.
6170 MODE is the mode in which X should be interpreted.
6172 DEST_REG is the putative biv, also the destination of the insn.
6173 We accept patterns of these forms:
6174 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6175 REG = INVARIANT + REG
6177 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6178 store the additive term into *INC_VAL, and store the place where
6179 we found the additive term into *LOCATION.
6181 If X is an assignment of an invariant into DEST_REG, we set
6182 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6184 We also want to detect a BIV when it corresponds to a variable
6185 whose mode was promoted. In that case, an increment
6186 of the variable may be a PLUS that adds a SUBREG of that variable to
6187 an invariant and then sign- or zero-extends the result of the PLUS
6188 into the variable.
6190 Most GIVs in such cases will be in the promoted mode, since that is the
6191 probably the natural computation mode (and almost certainly the mode
6192 used for addresses) on the machine. So we view the pseudo-reg containing
6193 the variable as the BIV, as if it were simply incremented.
6195 Note that treating the entire pseudo as a BIV will result in making
6196 simple increments to any GIVs based on it. However, if the variable
6197 overflows in its declared mode but not its promoted mode, the result will
6198 be incorrect. This is acceptable if the variable is signed, since
6199 overflows in such cases are undefined, but not if it is unsigned, since
6200 those overflows are defined. So we only check for SIGN_EXTEND and
6201 not ZERO_EXTEND.
6203 If we cannot find a biv, we return 0. */
6205 static int
6209 {
6217 {
6223 {
6225 }
6230 {
6232 }
6233 else
6240 /* convert_modes can emit new instructions, e.g. when arg is a loop
6241 invariant MEM and dest_reg has a different mode.
6242 These instructions would be emitted after the end of the function
6243 and then *inc_val would be an uninitialized pseudo.
6244 Detect this and bail in this case.
6245 Other alternatives to solve this can be introducing a convert_modes
6246 variant which is allowed to fail but not allowed to emit new
6247 instructions, emit these instructions before loop start and let
6248 it be garbage collected if *inc_val is never used or saving the
6249 *inc_val initialization sequence generated here and when *inc_val
6250 is going to be actually used, emit it at some suitable place. */
6254 {
6257 }
6265 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6266 handle addition of promoted variables.
6267 ??? The comment at the start of this function is wrong: promoted
6268 variable increments don't look like it says they do. */
6274 /* If this register is assigned in a previous insn, look at its
6275 source, but don't go outside the loop or past a label. */
6277 /* If this sets a register to itself, we would repeat any previous
6278 biv increment if we applied this strategy blindly. */
6284 {
6285 rtx dest;
6286 do
6287 {
6289 }
6318 }
6319 /* Fall through. */
6321 /* Can accept constant setting of biv only when inside inner most loop.
6322 Otherwise, a biv of an inner loop may be incorrectly recognized
6323 as a biv of the outer loop,
6324 causing code to be moved INTO the inner loop. */
6331 /* convert_modes aborts if we try to convert to or from CCmode, so just
6332 exclude that case. It is very unlikely that a condition code value
6333 would be a useful iterator anyways. convert_modes aborts if we try to
6334 convert a float mode to non-float or vice versa too. */
6338 {
6339 /* Possible bug here? Perhaps we don't know the mode of X. */
6343 {
6346 }
6351 }
6352 else
6356 /* Ignore this BIV if signed arithmetic overflow is defined. */
6363 /* Similar, since this can be a sign extension. */
6368 ;
6382 location);
6387 }
6388 }
6389 \f
6390 /* A general induction variable (giv) is any quantity that is a linear
6391 function of a basic induction variable,
6392 i.e. giv = biv * mult_val + add_val.
6393 The coefficients can be any loop invariant quantity.
6394 A giv need not be computed directly from the biv;
6395 it can be computed by way of other givs. */
6397 /* Determine whether X computes a giv.
6398 If it does, return a nonzero value
6399 which is the benefit from eliminating the computation of X;
6400 set *SRC_REG to the register of the biv that it is computed from;
6401 set *ADD_VAL and *MULT_VAL to the coefficients,
6402 such that the value of X is biv * mult + add; */
6404 static int
6409 {
6413 /* If this is an invariant, forget it, it isn't a giv. */
6424 {
6427 /* Since this is now an invariant and wasn't before, it must be a giv
6428 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6429 with. */
6436 /* This is equivalent to a BIV. */
6443 /* Either (plus (biv) (invar)) or
6444 (plus (mult (biv) (invar_1)) (invar_2)). */
6446 {
6449 }
6450 else
6451 {
6454 }
6459 /* ADD_VAL is zero. */
6467 }
6469 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6470 unless they are CONST_INT). */
6478 else
6481 /* Always return true if this is a giv so it will be detected as such,
6482 even if the benefit is zero or negative. This allows elimination
6483 of bivs that might otherwise not be eliminated. */
6485 }
6486 \f
6487 /* Given an expression, X, try to form it as a linear function of a biv.
6488 We will canonicalize it to be of the form
6489 (plus (mult (BIV) (invar_1))
6490 (invar_2))
6491 with possible degeneracies.
6493 The invariant expressions must each be of a form that can be used as a
6494 machine operand. We surround then with a USE rtx (a hack, but localized
6495 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6496 routine; it is the caller's responsibility to strip them.
6498 If no such canonicalization is possible (i.e., two biv's are used or an
6499 expression that is neither invariant nor a biv or giv), this routine
6500 returns 0.
6502 For a nonzero return, the result will have a code of CONST_INT, USE,
6503 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6505 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6510 static rtx
6512 {
6517 rtx tem;
6519 /* If this is not an integer mode, or if we cannot do arithmetic in this
6520 mode, this can't be a giv. */
6527 {
6534 /* Put constant last, CONST_INT last if both constant. */
6542 /* Handle addition of zero, then addition of an invariant. */
6547 {
6550 /* Adding two invariants must result in an invariant, so enclose
6551 addition operation inside a USE and return it. */
6561 else
6570 /* biv + invar or mult + invar. Return sum. */
6574 /* (a + invar_1) + invar_2. Associate. */
6575 return
6581 arg1)),
6586 }
6588 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6589 MULT to reduce cases. */
6595 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6596 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6597 Recurse to associate the second PLUS. */
6602 return
6610 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6626 /* Handle "a - b" as "a + b * (-1)". */
6632 constm1_rtx)),
6641 /* Put constant last, CONST_INT last if both constant. */
6646 /* If second argument is not now constant, not giv. */
6650 /* Handle multiply by 0 or 1. */
6658 {
6660 /* biv * invar. Done. */
6664 /* Product of two constants. */
6668 /* invar * invar is a giv, but attempt to simplify it somehow. */
6674 {
6675 /* (invar_0 * invar_1) * invar_2. Associate. */
6682 arg1)),
6684 }
6685 /* Propagate the MULT expressions to the innermost nodes. */
6687 {
6688 /* (invar_0 + invar_1) * invar_2. Distribute. */
6694 arg1),
6698 arg1)),
6700 }
6704 /* (a * invar_1) * invar_2. Associate. */
6710 arg1)),
6714 /* (a + invar_1) * invar_2. Distribute. */
6719 arg1),
6722 arg1)),
6727 }
6730 /* Shift by constant is multiply by power of two. */
6734 return
6743 /* "-a" is "a * (-1)" */
6749 /* "~a" is "-a - 1". Silly, but easy. */
6753 const1_rtx),
6757 /* Already in proper form for invariant. */
6763 /* Conditionally recognize extensions of simple IVs. After we've
6764 computed loop traversal counts and verified the range of the
6765 source IV, we'll reevaluate this as a GIV. */
6767 {
6770 {
6773 }
6774 }
6778 /* If this is a new register, we can't deal with it. */
6782 /* Check for biv or giv. */
6784 {
6788 {
6791 /* Form expression from giv and add benefit. Ensure this giv
6792 can derive another and subtract any needed adjustment if so. */
6794 /* Increasing the benefit here is risky. The only case in which it
6795 is arguably correct is if this is the only use of V. In other
6796 cases, this will artificially inflate the benefit of the current
6797 giv, and lead to suboptimal code. Thus, it is disabled, since
6798 potentially not reducing an only marginally beneficial giv is
6799 less harmful than reducing many givs that are not really
6800 beneficial. */
6801 {
6805 }
6818 {
6821 }
6822 else
6823 {
6826 }
6828 }
6831 do_default:
6832 /* If it isn't an induction variable, and it is invariant, we
6833 may be able to simplify things further by looking through
6834 the bits we just moved outside the loop. */
6836 {
6842 {
6843 /* Ok, we found a match. Substitute and simplify. */
6845 /* If we match another movable, we must use that, as
6846 this one is going away. */
6851 /* If consec is nonzero, this is a member of a group of
6852 instructions that were moved together. We handle this
6853 case only to the point of seeking to the last insn and
6854 looking for a REG_EQUAL. Fail if we don't find one. */
6856 {
6859 do
6860 {
6862 }
6868 }
6869 else
6870 {
6874 }
6877 {
6878 /* What we are most interested in is pointer
6879 arithmetic on invariants -- only take
6880 patterns we may be able to do something with. */
6886 {
6888 benefit);
6891 }
6896 {
6901 }
6902 }
6904 }
6905 }
6907 }
6909 /* Fall through to general case. */
6911 /* If invariant, return as USE (unless CONST_INT).
6912 Otherwise, not giv. */
6917 {
6926 }
6927 else
6929 }
6930 }
6932 /* This routine folds invariants such that there is only ever one
6933 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6935 static rtx
6937 {
6943 {
6946 }
6949 {
6952 }
6953 else
6954 {
6957 }
6958 }
6960 static rtx
6962 {
6964 {
6968 else
6971 }
6974 else
6977 }
6978 \f
6979 /* Help detect a giv that is calculated by several consecutive insns;
6980 for example,
6981 giv = biv * M
6982 giv = giv + A
6983 The caller has already identified the first insn P as having a giv as dest;
6984 we check that all other insns that set the same register follow
6985 immediately after P, that they alter nothing else,
6986 and that the result of the last is still a giv.
6988 The value is 0 if the reg set in P is not really a giv.
6989 Otherwise, the value is the amount gained by eliminating
6990 all the consecutive insns that compute the value.
6992 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6993 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6995 The coefficients of the ultimate giv value are stored in
6996 *MULT_VAL and *ADD_VAL. */
6998 static int
7002 {
7008 rtx temp;
7009 rtx set;
7011 /* Indicate that this is a giv so that we can update the value produced in
7012 each insn of the multi-insn sequence.
7014 This induction structure will be used only by the call to
7015 general_induction_var below, so we can allocate it on our stack.
7016 If this is a giv, our caller will replace the induct var entry with
7017 a new induction structure. */
7038 {
7042 /* If libcall, skip to end of call sequence. */
7053 /* Giv created by equivalent expression. */
7059 {
7063 count--;
7067 }
7069 {
7070 /* Allow insns that set something other than this giv to a
7071 constant. Such insns are needed on machines which cannot
7072 include long constants and should not disqualify a giv. */
7081 }
7082 }
7087 }
7088 \f
7089 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7090 represented by G1. If no such expression can be found, or it is clear that
7091 it cannot possibly be a valid address, 0 is returned.
7093 To perform the computation, we note that
7094 G1 = x * v + a and
7095 G2 = y * v + b
7096 where `v' is the biv.
7098 So G2 = (y/b) * G1 + (b - a*y/x).
7100 Note that MULT = y/x.
7102 Update: A and B are now allowed to be additive expressions such that
7103 B contains all variables in A. That is, computing B-A will not require
7104 subtracting variables. */
7106 static rtx
7108 {
7109 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7114 /* If MULT is not 1, we cannot handle A with non-constants, since we
7115 would then be required to subtract multiples of the registers in A.
7116 This is theoretically possible, and may even apply to some Fortran
7117 constructs, but it is a lot of work and we do not attempt it here. */
7122 /* In general these structures are sorted top to bottom (down the PLUS
7123 chain), but not left to right across the PLUS. If B is a higher
7124 order giv than A, we can strip one level and recurse. If A is higher
7125 order, we'll eventually bail out, but won't know that until the end.
7126 If they are the same, we'll strip one level around this loop. */
7129 {
7141 /* We matched: remove one reg completely. */
7144 /* An alternate match. */
7147 /* An alternate match. */
7149 else
7150 {
7151 /* Indicates an extra register in B. Strip one level from B and
7152 recurse, hoping B was the higher order expression. */
7157 }
7158 }
7160 /* Here we are at the last level of A, go through the cases hoping to
7161 get rid of everything but a constant. */
7164 {
7177 }
7179 {
7181 }
7183 {
7188 }
7190 {
7195 else
7197 }
7202 }
7204 rtx
7206 {
7209 /* The value that G1 will be multiplied by must be a constant integer. Also,
7210 the only chance we have of getting a valid address is if b*c/a (see above
7211 for notation) is also an integer. */
7214 {
7222 }
7225 else
7226 {
7227 /* ??? Find out if the one is a multiple of the other? */
7229 }
7233 {
7234 /* Failed. If we've got a multiplication factor between G1 and G2,
7235 scale G1's addend and try again. */
7237 {
7241 {
7242 HOST_WIDE_INT m;
7246 }
7247 else
7248 {
7250 mult);
7251 }
7254 }
7255 }
7259 /* Form simplified final result. */
7264 else
7269 else
7270 {
7273 {
7277 }
7280 }
7281 }
7282 \f
7283 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7284 represented by G1. This indicates that G2 should be combined with G1 and
7285 that G2 can use (either directly or via an address expression) a register
7286 used to represent G1. */
7288 static rtx
7290 {
7293 /* With the introduction of ext dependent givs, we must care for modes.
7294 G2 must not use a wider mode than G1. */
7304 /* If these givs are identical, they can be combined. We use the results
7305 of express_from because the addends are not in a canonical form, so
7306 rtx_equal_p is a weaker test. */
7307 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7308 combination to be the other way round. */
7311 {
7313 }
7315 /* If G2 can be expressed as a function of G1 and that function is valid
7316 as an address and no more expensive than using a register for G2,
7317 the expression of G2 in terms of G1 can be used. */
7324 }
7325 \f
7326 /* Check each extension dependent giv in this class to see if its
7327 root biv is safe from wrapping in the interior mode, which would
7328 make the giv illegal. */
7330 static void
7332 {
7336 HOST_WIDE_INT start_val;
7342 /* Make sure the iteration data is available. We must have
7343 constants in order to be certain of no overflow. */
7349 /* Make sure the host can represent the arithmetic. */
7351 {
7353 HOST_WIDE_INT s_end_val;
7365 /* Check for host arithmetic overflow. */
7367 {
7369 HOST_WIDE_INT s_max;
7376 /* Check zero extension of biv ok. */
7378 /* Check for host arithmetic overflow. */
7379 && (neg_incr
7382 /* Check for target arithmetic overflow. */
7383 && (neg_incr
7386 {
7388 }
7390 /* Check sign extension of biv ok. */
7391 /* ??? While it is true that overflow with signed and pointer
7392 arithmetic is undefined, I fear too many programmers don't
7393 keep this fact in mind -- myself included on occasion.
7394 So leave alone with the signed overflow optimizations. */
7396 /* Check for host arithmetic overflow. */
7397 && (neg_incr
7400 /* Check for target arithmetic overflow. */
7401 && (neg_incr
7404 {
7406 }
7407 }
7408 }
7410 /* If we know the BIV is compared at run-time against an
7411 invariant value, and the increment is +/- 1, we may also
7412 be able to prove that the BIV cannot overflow. */
7418 {
7419 /* If the increment is +1, and the exit test is a <,
7420 the BIV cannot overflow. (For <=, we have the
7421 problematic case that the comparison value might
7422 be the maximum value of the range.) */
7424 {
7429 }
7431 /* Likewise for increment -1 and exit test >. */
7433 {
7438 }
7439 }
7441 /* Invalidate givs that fail the tests. */
7444 {
7449 {
7458 /* We don't know whether this value is being used as either
7459 signed or unsigned, so to safely truncate we must satisfy
7460 both. The initial check here verifies the BIV itself;
7461 once that is successful we may check its range wrt the
7462 derived GIV. This works only if we were able to determine
7463 constant start and end values above. */
7465 {
7469 /* We know from the above that both endpoints are nonnegative,
7470 and that there is no wrapping. Verify that both endpoints
7471 are within the (signed) range of the outer mode. */
7474 }
7479 }
7482 {
7484 {
7488 }
7489 }
7490 else
7491 {
7493 {
7498 else
7499 {
7504 else
7506 }
7511 }
7514 }
7515 }
7516 }
7518 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7520 rtx
7522 {
7528 /* Recall that check_ext_dependent_givs verified that the known bounds
7529 of a biv did not overflow or wrap with respect to the extension for
7530 the giv. Therefore, constants need no additional adjustment. */
7534 /* Otherwise, we must adjust the value to compensate for the
7535 differing modes of the biv and the giv. */
7537 }
7538 \f
7539 struct combine_givs_stats
7540 {
7543 };
7545 static int
7547 {
7554 /* Stabilize the sort. */
7558 }
7560 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7561 any other. If so, point SAME to the giv combined with and set NEW_REG to
7562 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7563 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7565 static void
7567 {
7568 /* Additional benefit to add for being combined multiple times. */
7576 /* Count givs, because bl->giv_count is incorrect here. */
7580 giv_count++;
7592 {
7594 rtx single_use;
7599 /* If a DEST_REG GIV is used only once, do not allow it to combine
7600 with anything, for in doing so we will gain nothing that cannot
7601 be had by simply letting the GIV with which we would have combined
7602 to be reduced on its own. The losage shows up in particular with
7603 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7604 be seen elsewhere as well. */
7611 /* Add an additional weight for zero addends. */
7616 {
7617 rtx this_combine;
7622 {
7625 }
7626 }
7628 }
7630 /* Iterate, combining until we can't. */
7631 restart:
7635 {
7638 {
7644 }
7646 }
7649 {
7655 /* If it has already been combined, skip. */
7660 {
7663 /* If it has already been combined, skip. */
7665 {
7670 /* For destination, we now may replace by mem expression instead
7671 of register. This changes the costs considerably, so add the
7672 compensation. */
7682 /* ??? The new final_[bg]iv_value code does a much better job
7683 of finding replaceable giv's, and hence this code may no
7684 longer be necessary. */
7688 /* To help optimize the next set of combinations, remove
7689 this giv from the benefits of other potential mates. */
7691 {
7695 }
7702 }
7703 }
7705 /* To help optimize the next set of combinations, remove
7706 this giv from the benefits of other potential mates. */
7708 {
7710 {
7714 }
7718 /* We've finished with this giv, and everything it touched.
7719 Restart the combination so that proper weights for the
7720 rest of the givs are properly taken into account. */
7721 /* ??? Ideally we would compact the arrays at this point, so
7722 as to not cover old ground. But sanely compacting
7723 can_combine is tricky. */
7725 }
7726 }
7728 /* Clean up. */
7731 }
7732 \f
7733 /* Generate sequence for REG = B * M + A. B is the initial value of
7734 the basic induction variable, M a multiplicative constant, A an
7735 additive constant and REG the destination register. */
7737 static rtx
7739 {
7740 rtx seq;
7741 rtx result;
7744 /* Use unsigned arithmetic. */
7752 }
7755 /* Update registers created in insn sequence SEQ. */
7757 static void
7759 {
7760 rtx insn;
7762 /* Update register info for alias analysis. */
7766 {
7773 }
7774 }
7777 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7778 is the initial value of the basic induction variable, M a
7779 multiplicative constant, A an additive constant and REG the
7780 destination register. */
7782 void
7785 {
7786 rtx seq;
7789 {
7792 }
7794 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7797 /* Increase the lifetime of any invariants moved further in code. */
7802 /* It is possible that the expansion created lots of new registers.
7803 Iterate over the sequence we just created and record them all. We
7804 must do this before inserting the sequence. */
7808 }
7811 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7812 initial value of the basic induction variable, M a multiplicative
7813 constant, A an additive constant and REG the destination
7814 register. */
7816 void
7818 {
7819 rtx seq;
7821 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7824 /* Increase the lifetime of any invariants moved further in code.
7825 ???? Is this really necessary? */
7830 /* It is possible that the expansion created lots of new registers.
7831 Iterate over the sequence we just created and record them all. We
7832 must do this before inserting the sequence. */
7836 }
7839 /* Emit insns after loop to set REG = B * M + A. B is the initial
7840 value of the basic induction variable, M a multiplicative constant,
7841 A an additive constant and REG the destination register. */
7843 void
7845 {
7846 rtx seq;
7848 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7851 /* It is possible that the expansion created lots of new registers.
7852 Iterate over the sequence we just created and record them all. We
7853 must do this before inserting the sequence. */
7857 }
7861 /* Similar to gen_add_mult, but compute cost rather than generating
7862 sequence. */
7864 static int
7866 {
7876 {
7881 }
7884 }
7885 \f
7886 /* Test whether A * B can be computed without
7887 an actual multiply insn. Value is 1 if so.
7889 ??? This function stinks because it generates a ton of wasted RTL
7890 ??? and as a result fragments GC memory to no end. There are other
7891 ??? places in the compiler which are invoked a lot and do the same
7892 ??? thing, generate wasted RTL just to see if something is possible. */
7894 static int
7896 {
7897 rtx tmp;
7900 /* If only one is constant, make it B. */
7904 /* If first constant, both constant, so don't need multiply. */
7908 /* If second not constant, neither is constant, so would need multiply. */
7912 /* One operand is constant, so might not need multiply insn. Generate the
7913 code for the multiply and see if a call or multiply, or long sequence
7914 of insns is generated. */
7923 {
7926 {
7936 {
7939 }
7942 }
7943 }
7953 }
7954 \f
7955 /* Check to see if loop can be terminated by a "decrement and branch until
7956 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7957 Also try reversing an increment loop to a decrement loop
7958 to see if the optimization can be performed.
7959 Value is nonzero if optimization was performed. */
7961 /* This is useful even if the architecture doesn't have such an insn,
7962 because it might change a loops which increments from 0 to n to a loop
7963 which decrements from n to 0. A loop that decrements to zero is usually
7964 faster than one that increments from zero. */
7966 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7967 such as approx_final_value, biv_total_increment, loop_iterations, and
7968 final_[bg]iv_value. */
7970 static int
7972 {
7977 rtx reg;
7979 rtx jump_label;
7980 rtx final_value;
7981 rtx start_value;
7982 rtx new_add_val;
7983 rtx comparison;
7984 rtx before_comparison;
7985 rtx p;
7986 rtx jump;
7987 rtx first_compare;
7992 /* If last insn is a conditional branch, and the insn before tests a
7993 register value, try to optimize it. Otherwise, we can't do anything. */
8002 /* Try to compute whether the compare/branch at the loop end is one or
8003 two instructions. */
8009 else
8012 {
8013 /* If more than one condition is present to control the loop, then
8014 do not proceed, as this function does not know how to rewrite
8015 loop tests with more than one condition.
8017 Look backwards from the first insn in the last comparison
8018 sequence and see if we've got another comparison sequence. */
8020 rtx jump1;
8024 }
8026 /* Check all of the bivs to see if the compare uses one of them.
8027 Skip biv's set more than once because we can't guarantee that
8028 it will be zero on the last iteration. Also skip if the biv is
8029 used between its update and the test insn. */
8032 {
8037 first_compare))
8039 }
8041 /* Try swapping the comparison to identify a suitable biv. */
8048 first_compare))
8049 {
8051 VOIDmode,
8055 }
8060 /* Look for the case where the basic induction variable is always
8061 nonnegative, and equals zero on the last iteration.
8062 In this case, add a reg_note REG_NONNEG, which allows the
8063 m68k DBRA instruction to be used. */
8069 {
8070 /* Initial value must be greater than 0,
8071 init_val % -dec_value == 0 to ensure that it equals zero on
8072 the last iteration */
8078 {
8079 /* Register always nonnegative, add REG_NOTE to branch. */
8087 }
8089 /* If the decrement is 1 and the value was tested as >= 0 before
8090 the loop, then we can safely optimize. */
8092 {
8106 {
8114 }
8115 }
8116 }
8119 {
8120 /* Try to change inc to dec, so can apply above optimization. */
8121 /* Can do this if:
8122 all registers modified are induction variables or invariant,
8123 all memory references have non-overlapping addresses
8124 (obviously true if only one write)
8125 allow 2 insns for the compare/jump at the end of the loop. */
8126 /* Also, we must avoid any instructions which use both the reversed
8127 biv and another biv. Such instructions will fail if the loop is
8128 reversed. We meet this condition by requiring that either
8129 no_use_except_counting is true, or else that there is only
8130 one biv. */
8132 /* 1 if the iteration var is used only to count iterations. */
8134 /* 1 if the loop has no memory store, or it has a single memory store
8135 which is reversible. */
8141 {
8145 /* If there are no givs for this biv, and the only exit is the
8146 fall through at the end of the loop, then
8147 see if perhaps there are no uses except to count. */
8151 {
8156 /* An insn that sets the biv is okay. */
8157 ;
8159 /* An insn that doesn't mention the biv is okay. */
8160 ;
8163 {
8164 /* If either of these insns uses the biv and sets a pseudo
8165 that has more than one usage, then the biv has uses
8166 other than counting since it's used to derive a value
8167 that is used more than one time. */
8169 regs);
8171 {
8174 }
8175 }
8176 else
8177 {
8180 }
8181 }
8183 /* A biv has uses besides counting if it is used to set
8184 another biv. */
8188 {
8191 }
8192 }
8195 /* No need to worry about MEMs. */
8196 ;
8198 {
8203 /* If the loop has a single store, and the destination address is
8204 invariant, then we can't reverse the loop, because this address
8205 might then have the wrong value at loop exit.
8206 This would work if the source was invariant also, however, in that
8207 case, the insn should have been moved out of the loop. */
8210 {
8213 /* If we could prove that each of the memory locations
8214 written to was different, then we could reverse the
8215 store -- but we don't presently have any way of
8216 knowing that. */
8219 /* If the store depends on a register that is set after the
8220 store, it depends on the initial value, and is thus not
8221 reversible. */
8223 {
8230 }
8231 }
8232 }
8233 else
8236 /* This code only acts for innermost loops. Also it simplifies
8237 the memory address check by only reversing loops with
8238 zero or one memory access.
8239 Two memory accesses could involve parts of the same array,
8240 and that can't be reversed.
8241 If the biv is used only for counting, than we don't need to worry
8242 about all these things. */
8248 && reversible_mem_store
8253 {
8254 rtx tem;
8256 /* Loop can be reversed. */
8260 /* Now check other conditions:
8262 The increment must be a constant, as must the initial value,
8263 and the comparison code must be LT.
8265 This test can probably be improved since +/- 1 in the constant
8266 can be obtained by changing LT to LE and vice versa; this is
8267 confusing. */
8270 /* for constants, LE gets turned into LT */
8275 {
8287 comparison_const_width
8289 else
8290 comparison_const_width
8294 comparison_sign_mask
8297 /* If the comparison value is not a loop invariant, then we
8298 can not reverse this loop.
8300 ??? If the insns which initialize the comparison value as
8301 a whole compute an invariant result, then we could move
8302 them out of the loop and proceed with loop reversal. */
8310 /* Normalize the initial value if it is an integer and
8311 has no other use except as a counter. This will allow
8312 a few more loops to be reversed. */
8316 {
8318 /* The code below requires comparison_val to be a multiple
8319 of add_val in order to do the loop reversal, so
8320 round up comparison_val to a multiple of add_val.
8321 Since comparison_value is constant, we know that the
8322 current comparison code is LT. */
8324 comparison_val
8326 /* We postpone overflow checks for COMPARISON_VAL here;
8327 even if there is an overflow, we might still be able to
8328 reverse the loop, if converting the loop exit test to
8329 NE is possible. */
8331 }
8333 /* First check if we can do a vanilla loop reversal. */
8335 /* If we have a decrement_and_branch_on_count,
8336 prefer the NE test, since this will allow that
8337 instruction to be generated. Note that we must
8338 use a vanilla loop reversal if the biv is used to
8339 calculate a giv or has a non-counting use. */
8340 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8341 && defined (HAVE_decrement_and_branch_on_count)
8345 #endif
8347 /* Now do postponed overflow checks on COMPARISON_VAL. */
8350 {
8351 /* Register will always be nonnegative, with value
8352 0 on last iteration */
8356 }
8360 {
8363 }
8364 else
8370 /* If the initial value is not zero, or if the comparison
8371 value is not an exact multiple of the increment, then we
8372 can not reverse this loop. */
8375 {
8378 }
8379 else
8380 {
8383 }
8387 /* Reset these in case we normalized the initial value
8388 and comparison value above. */
8391 {
8393 final_value
8395 }
8398 /* Save some info needed to produce the new insns. */
8404 /* Set start_value; if this is not a CONST_INT, we need
8405 to generate a SUB.
8406 Initialize biv to start_value before loop start.
8407 The old initializing insn will be deleted as a
8408 dead store by flow.c. */
8411 {
8412 start_value
8415 }
8417 {
8424 start_value
8430 }
8432 {
8434 initial_value);
8438 start_value
8441 }
8442 else
8443 /* We could handle the other cases too, but it'll be
8444 better to have a testcase first. */
8447 /* We may not have a single insn which can increment a reg, so
8448 create a sequence to hold all the insns from expand_inc. */
8457 /* Update biv info to reflect its new status. */
8462 /* Update loop info. */
8471 /* Inc LABEL_NUSES so that delete_insn will
8472 not delete the label. */
8475 /* If we have a separate comparison insn that does more
8476 than just set cc0, the result of the comparison might
8477 be used outside the loop. */
8479 #ifdef HAVE_CC0
8481 #endif
8482 );
8484 /* Emit an insn after the end of the loop to set the biv's
8485 proper exit value if it is used anywhere outside the loop. */
8495 /* Delete compare/branch at end of loop. */
8500 /* Add new compare/branch insn at end of loop. */
8512 ;
8518 {
8520 {
8521 /* Increment of LABEL_NUSES done above. */
8522 /* Register is now always nonnegative,
8523 so add REG_NONNEG note to the branch. */
8526 }
8528 }
8530 /* No insn may reference both the reversed and another biv or it
8531 will fail (see comment near the top of the loop reversal
8532 code).
8533 Earlier on, we have verified that the biv has no use except
8534 counting, or it is the only biv in this function.
8535 However, the code that computes no_use_except_counting does
8536 not verify reg notes. It's possible to have an insn that
8537 references another biv, and has a REG_EQUAL note with an
8538 expression based on the reversed biv. To avoid this case,
8539 remove all REG_EQUAL notes based on the reversed biv
8540 here. */
8543 {
8546 /* If this is a set of a GIV based on the reversed biv, any
8547 REG_EQUAL notes should still be correct. */
8554 {
8559 else
8561 }
8562 }
8564 /* Mark that this biv has been reversed. Each giv which depends
8565 on this biv, and which is also live past the end of the loop
8566 will have to be fixed up. */
8571 {
8575 else
8577 }
8580 }
8581 }
8582 }
8585 }
8586 \f
8587 /* Verify whether the biv BL appears to be eliminable,
8588 based on the insns in the loop that refer to it.
8590 If ELIMINATE_P is nonzero, actually do the elimination.
8592 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8593 determine whether invariant insns should be placed inside or at the
8594 start of the loop. */
8596 static int
8599 {
8602 rtx p;
8604 /* Scan all insns in the loop, stopping if we find one that uses the
8605 biv in a way that we cannot eliminate. */
8608 {
8612 rtx note;
8614 /* If this is a libcall that sets a giv, skip ahead to its end. */
8616 {
8620 {
8625 {
8632 }
8633 }
8634 }
8636 /* Closely examine the insn if the biv is mentioned. */
8641 {
8647 }
8649 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8654 }
8657 {
8662 }
8665 }
8666 \f
8667 /* INSN and REFERENCE are instructions in the same insn chain.
8668 Return nonzero if INSN is first. */
8670 int
8672 {
8676 {
8677 /* Start with test for not first so that INSN == REFERENCE yields not
8678 first. */
8684 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8685 previous insn, hence the <= comparison below does not work if
8686 P is a note. */
8697 }
8698 }
8700 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8701 the offset that we have to take into account due to auto-increment /
8702 div derivation is zero. */
8703 static int
8706 {
8707 /* If the giv V had the auto-inc address optimization applied
8708 to it, and INSN occurs between the giv insn and the biv
8709 insn, then we'd have to adjust the value used here.
8710 This is rare, so we don't bother to make this possible. */
8719 }
8721 /* If BL appears in X (part of the pattern of INSN), see if we can
8722 eliminate its use. If so, return 1. If not, return 0.
8724 If BIV does not appear in X, return 1.
8726 If ELIMINATE_P is nonzero, actually do the elimination.
8727 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8728 Depending on how many items have been moved out of the loop, it
8729 will either be before INSN (when WHERE_INSN is nonzero) or at the
8730 start of the loop (when WHERE_INSN is zero). */
8732 static int
8736 {
8742 #ifdef HAVE_cc0
8744 #endif
8750 {
8752 /* If we haven't already been able to do something with this BIV,
8753 we can't eliminate it. */
8759 /* If this sets the BIV, it is not a problem. */
8763 /* If this is an insn that defines a giv, it is also ok because
8764 it will go away when the giv is reduced. */
8769 #ifdef HAVE_cc0
8771 {
8772 /* Can replace with any giv that was reduced and
8773 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8774 Require a constant for MULT_VAL, so we know it's nonzero.
8775 ??? We disable this optimization to avoid potential
8776 overflows. */
8784 {
8791 /* If the giv has the opposite direction of change,
8792 then reverse the comparison. */
8796 else
8799 /* We can probably test that giv's reduced reg. */
8802 }
8804 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8805 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8806 Require a constant for MULT_VAL, so we know it's nonzero.
8807 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8808 overflow problem. */
8820 {
8827 /* If the giv has the opposite direction of change,
8828 then reverse the comparison. */
8832 else
8836 /* Replace biv with the giv's reduced register. */
8841 /* Insn doesn't support that constant or invariant. Copy it
8842 into a register (it will be a loop invariant.) */
8849 /* Substitute the new register for its invariant value in
8850 the compare expression. */
8854 }
8855 }
8856 #endif
8863 /* See if either argument is the biv. */
8868 else
8872 {
8873 /* First try to replace with any giv that has constant positive
8874 mult_val and constant add_val. We might be able to support
8875 negative mult_val, but it seems complex to do it in general. */
8887 {
8891 /* Don't eliminate if the linear combination that makes up
8892 the giv overflows when it is applied to ARG. */
8894 {
8895 rtx add_val;
8899 else
8905 }
8910 /* Replace biv with the giv's reduced reg. */
8913 /* If all constants are actually constant integers and
8914 the derived constant can be directly placed in the COMPARE,
8915 do so. */
8918 {
8921 }
8922 else
8923 {
8924 /* Otherwise, load it into a register. */
8929 }
8935 }
8937 /* Look for giv with positive constant mult_val and nonconst add_val.
8938 Insert insns to calculate new compare value.
8939 ??? Turn this off due to possible overflow. */
8947 {
8948 rtx tem;
8958 /* Replace biv with giv's reduced register. */
8962 /* Compute value to compare against. */
8966 /* Use it in this insn. */
8970 }
8971 }
8973 {
8975 {
8976 /* Look for giv with constant positive mult_val and nonconst
8977 add_val. Insert insns to compute new compare value.
8978 ??? Turn this off due to possible overflow. */
8985 {
8986 rtx tem;
8996 /* Replace biv with giv's reduced register. */
9000 /* Compute value to compare against. */
9007 }
9008 }
9010 /* This code has problems. Basically, you can't know when
9011 seeing if we will eliminate BL, whether a particular giv
9012 of ARG will be reduced. If it isn't going to be reduced,
9013 we can't eliminate BL. We can try forcing it to be reduced,
9014 but that can generate poor code.
9016 The problem is that the benefit of reducing TV, below should
9017 be increased if BL can actually be eliminated, but this means
9018 we might have to do a topological sort of the order in which
9019 we try to process biv. It doesn't seem worthwhile to do
9020 this sort of thing now. */
9022 #if 0
9023 /* Otherwise the reg compared with had better be a biv. */
9028 /* Look for a pair of givs, one for each biv,
9029 with identical coefficients. */
9031 {
9043 {
9050 /* Replace biv with its giv's reduced reg. */
9052 /* Replace other operand with the other giv's
9053 reduced reg. */
9056 }
9057 }
9058 #endif
9059 }
9061 /* If we get here, the biv can't be eliminated. */
9065 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9066 biv is used in it, since it will be replaced. */
9074 }
9076 /* See if any subexpression fails elimination. */
9079 {
9081 {
9094 }
9095 }
9098 }
9099 \f
9100 /* Return nonzero if the last use of REG
9101 is in an insn following INSN in the same basic block. */
9103 static int
9105 {
9106 rtx n;
9110 {
9113 }
9115 }
9116 \f
9117 /* Called via `note_stores' to record the initial value of a biv. Here we
9118 just record the location of the set and process it later. */
9120 static void
9122 {
9133 /* If this is the first set found, record it. */
9135 {
9138 }
9139 }
9140 \f
9141 /* If any of the registers in X are "old" and currently have a last use earlier
9142 than INSN, update them to have a last use of INSN. Their actual last use
9143 will be the previous insn but it will not have a valid uid_luid so we can't
9144 use it. X must be a source expression only. */
9146 static void
9148 {
9149 /* Check for the case where INSN does not have a valid luid. In this case,
9150 there is no need to modify the regno_last_uid, as this can only happen
9151 when code is inserted after the loop_end to set a pseudo's final value,
9152 and hence this insn will never be the last use of x.
9153 ???? This comment is not correct. See for example loop_givs_reduce.
9154 This may insert an insn before another new insn. */
9158 {
9160 }
9161 else
9162 {
9166 {
9172 }
9173 }
9174 }
9175 \f
9176 /* Given an insn INSN and condition COND, return the condition in a
9177 canonical form to simplify testing by callers. Specifically:
9179 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9180 (2) Both operands will be machine operands; (cc0) will have been replaced.
9181 (3) If an operand is a constant, it will be the second operand.
9182 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9183 for GE, GEU, and LEU.
9185 If the condition cannot be understood, or is an inequality floating-point
9186 comparison which needs to be reversed, 0 will be returned.
9188 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9190 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9191 insn used in locating the condition was found. If a replacement test
9192 of the condition is desired, it should be placed in front of that
9193 insn and we will be sure that the inputs are still valid.
9195 If WANT_REG is nonzero, we wish the condition to be relative to that
9196 register, if possible. Therefore, do not canonicalize the condition
9197 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9198 to be a compare to a CC mode register.
9200 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
9201 and at INSN. */
9203 rtx
9206 {
9209 rtx set;
9210 rtx tem;
9228 /* If we are comparing a register with zero, see if the register is set
9229 in the previous insn to a COMPARE or a comparison operation. Perform
9230 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9231 in cse.c */
9237 {
9238 /* Set nonzero when we find something of interest. */
9241 #ifdef HAVE_cc0
9242 /* If comparison with cc0, import actual comparison from compare
9243 insn. */
9245 {
9256 }
9257 #endif
9259 /* If this is a COMPARE, pick up the two things being compared. */
9261 {
9265 }
9269 /* Go back to the previous insn. Stop if it is not an INSN. We also
9270 stop if it isn't a single set or if it has a REG_INC note because
9271 we don't want to bother dealing with it. */
9285 /* If this is setting OP0, get what it sets it to if it looks
9286 relevant. */
9288 {
9290 #ifdef FLOAT_STORE_FLAG_VALUE
9291 REAL_VALUE_TYPE fsfv;
9292 #endif
9294 /* ??? We may not combine comparisons done in a CCmode with
9295 comparisons not done in a CCmode. This is to aid targets
9296 like Alpha that have an IEEE compliant EQ instruction, and
9297 a non-IEEE compliant BEQ instruction. The use of CCmode is
9298 actually artificial, simply to prevent the combination, but
9299 should not affect other platforms.
9301 However, we must allow VOIDmode comparisons to match either
9302 CCmode or non-CCmode comparison, because some ports have
9303 modeless comparisons inside branch patterns.
9305 ??? This mode check should perhaps look more like the mode check
9306 in simplify_comparison in combine. */
9314 && (STORE_FLAG_VALUE
9317 #ifdef FLOAT_STORE_FLAG_VALUE
9322 #endif
9323 ))
9334 && (STORE_FLAG_VALUE
9337 #ifdef FLOAT_STORE_FLAG_VALUE
9342 #endif
9343 ))
9349 {
9352 }
9353 else
9355 }
9358 /* If this sets OP0, but not directly, we have to give up. */
9362 {
9363 /* If the caller is expecting the condition to be valid at INSN,
9364 make sure X doesn't change before INSN. */
9371 {
9376 }
9381 }
9382 }
9384 /* If constant is first, put it last. */
9388 /* If OP0 is the result of a comparison, we weren't able to find what
9389 was really being compared, so fail. */
9394 /* Canonicalize any ordered comparison with integers involving equality
9395 if we can do computations in the relevant mode and we do not
9396 overflow. */
9402 {
9405 unsigned HOST_WIDE_INT max_val
9409 {
9415 /* When cross-compiling, const_val might be sign-extended from
9416 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9436 }
9437 }
9439 /* Never return CC0; return zero instead. */
9444 }
9446 /* Given a jump insn JUMP, return the condition that will cause it to branch
9447 to its JUMP_LABEL. If the condition cannot be understood, or is an
9448 inequality floating-point comparison which needs to be reversed, 0 will
9449 be returned.
9451 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9452 insn used in locating the condition was found. If a replacement test
9453 of the condition is desired, it should be placed in front of that
9454 insn and we will be sure that the inputs are still valid. If EARLIEST
9455 is null, the returned condition will be valid at INSN.
9457 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9458 compare CC mode register.
9460 VALID_AT_INSN_P is the same as for canonicalize_condition. */
9462 rtx
9464 {
9465 rtx cond;
9467 rtx set;
9469 /* If this is not a standard conditional jump, we can't parse it. */
9477 /* If this branches to JUMP_LABEL when the condition is false, reverse
9478 the condition. */
9479 reverse
9485 }
9487 /* Similar to above routine, except that we also put an invariant last
9488 unless both operands are invariants. */
9490 rtx
9492 {
9502 }
9504 /* Scan the function and determine whether it has indirect (computed) jumps.
9506 This is taken mostly from flow.c; similar code exists elsewhere
9507 in the compiler. It may be useful to put this into rtlanal.c. */
9508 static int
9510 {
9511 rtx insn;
9518 }
9520 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9521 documentation for LOOP_MEMS for the definition of `appropriate'.
9522 This function is called from prescan_loop via for_each_rtx. */
9524 static int
9526 {
9535 {
9540 /* We're not interested in MEMs that are only clobbered. */
9544 /* We're not interested in the MEM associated with a
9545 CONST_DOUBLE, so there's no need to traverse into this. */
9549 /* We're not interested in any MEMs that only appear in notes. */
9553 /* This is not a MEM. */
9555 }
9557 /* See if we've already seen this MEM. */
9560 {
9564 /* The modes of the two memory accesses are different. If
9565 this happens, something tricky is going on, and we just
9566 don't optimize accesses to this MEM. */
9570 }
9572 /* Resize the array, if necessary. */
9574 {
9577 else
9582 }
9584 /* Actually insert the MEM. */
9586 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9587 because we can't put it in a register. We still store it in the
9588 table, though, so that if we see the same address later, but in a
9589 non-BLK mode, we'll not think we can optimize it at that point. */
9595 }
9598 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9600 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9601 register that is modified by an insn between FROM and TO. If the
9602 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9603 more, stop incrementing it, to avoid overflow.
9605 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9606 register I is used, if it is only used once. Otherwise, it is set
9607 to 0 (for no uses) or const0_rtx for more than one use. This
9608 parameter may be zero, in which case this processing is not done.
9610 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9611 optimize register I. */
9613 static void
9615 {
9618 /* last_set[n] is nonzero iff reg n has been set in the current
9619 basic block. In that case, it is the insn that last set reg n. */
9621 rtx insn;
9627 /* Grow the regs array if not allocated or too small. */
9629 {
9634 /* Zero the new elements. */
9637 }
9639 /* Clear previously scanned fields but do not clear n_times_set. */
9641 {
9645 }
9649 /* Scan the loop, recording register usage. */
9652 {
9654 {
9655 /* Record registers that have exactly one use. */
9658 /* Include uses in REG_EQUAL notes. */
9666 {
9670 last_set);
9671 }
9672 }
9677 /* Invalidate all registers used for function argument passing.
9678 We check rtx_varies_p for the same reason as below, to allow
9679 optimizing PIC calculations. */
9681 {
9682 rtx link;
9684 link;
9686 {
9693 }
9694 }
9695 }
9697 /* Invalidate all hard registers clobbered by calls. With one exception:
9698 a call-clobbered PIC register is still function-invariant for our
9699 purposes, since we can hoist any PIC calculations out of the loop.
9700 Thus the call to rtx_varies_p. */
9705 {
9708 }
9710 #ifdef AVOID_CCMODE_COPIES
9711 /* Don't try to move insns which set CC registers if we should not
9712 create CCmode register copies. */
9716 #endif
9718 /* Set regs->array[I].n_times_set for the new registers. */
9723 }
9725 /* Returns the number of real INSNs in the LOOP. */
9727 static int
9729 {
9731 rtx insn;
9739 }
9741 /* Move MEMs into registers for the duration of the loop. */
9743 static void
9745 {
9752 rtx end_label;
9753 /* Nonzero if the next instruction may never be executed. */
9760 /* We cannot use next_label here because it skips over normal insns. */
9765 /* Check to see if it's possible that some instructions in the loop are
9766 never executed. Also check if there is a goto out of the loop other
9767 than right after the end of the loop. */
9771 {
9775 /* If we enter the loop in the middle, and scan
9776 around to the beginning, don't set maybe_never
9777 for that. This must be an unconditional jump,
9778 otherwise the code at the top of the loop might
9779 never be executed. Unconditional jumps are
9780 followed a by barrier then loop end. */
9785 {
9786 /* If this is a jump outside of the loop but not right
9787 after the end of the loop, we would have to emit new fixup
9788 sequences for each such label. */
9790 JUMP_INSN is executed, we must be conservative. */
9799 /* Something complicated. */
9801 else
9802 /* If there are any more instructions in the loop, they
9803 might not be reached. */
9805 }
9808 }
9810 /* Find start of the extended basic block that enters the loop. */
9814 ;
9819 /* Build table of mems that get set to constant values before the
9820 loop. */
9824 /* Actually move the MEMs. */
9826 {
9827 regset_head load_copies;
9828 regset_head store_copies;
9830 rtx reg;
9832 rtx mem_list_entry;
9836 /* There's no telling whether or not MEM is modified. */
9839 /* Go through the MEMs written to in the loop to see if this
9840 one is aliased by one of them. */
9843 {
9848 {
9849 /* MEM is indeed aliased by this store. */
9852 }
9854 }
9860 /* If this MEM is written to, we must be sure that there
9861 are no reads from another MEM that aliases this one. */
9863 {
9867 {
9871 VOIDmode,
9873 rtx_varies_p))
9874 {
9875 /* It's not safe to hoist loop_info->mems[i] out of
9876 the loop because writes to it might not be
9877 seen by reads from loop_info->mems[j]. */
9880 }
9881 }
9882 }
9885 /* We can't access the MEM outside the loop; it might
9886 cause a trap that wouldn't have happened otherwise. */
9890 /* We thought we were going to lift this MEM out of the
9891 loop, but later discovered that we could not. */
9897 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9898 order to keep scan_loop from moving stores to this MEM
9899 out of the loop just because this REG is neither a
9900 user-variable nor used in the loop test. */
9905 /* Now, replace all references to the MEM with the
9906 corresponding pseudos. */
9911 {
9913 {
9914 rtx set;
9918 /* See if this copies the mem into a register that isn't
9919 modified afterwards. We'll try to do copy propagation
9920 a little further on. */
9922 /* @@@ This test is _way_ too conservative. */
9923 && ! maybe_never
9931 /* See if this copies the mem from a register that isn't
9932 modified afterwards. We'll try to remove the
9933 redundant copy later on by doing a little register
9934 renaming and copy propagation. This will help
9935 to untangle things for the BIV detection code. */
9937 && ! maybe_never
9945 /* If this is a call which uses / clobbers this memory
9946 location, we must not change the interface here. */
9950 {
9954 }
9955 else
9956 /* Replace the memory reference with the shadow register. */
9959 }
9964 }
9969 /* We couldn't replace all occurrences of the MEM. */
9971 else
9972 {
9973 /* Load the memory immediately before LOOP->START, which is
9974 the NOTE_LOOP_BEG. */
9976 rtx set;
9982 {
9986 {
9990 /* Extending hard register lifetimes causes crash
9991 on SRC targets. Doing so on non-SRC is
9992 probably also not good idea, since we most
9993 probably have pseudoregister equivalence as
9994 well. */
9997 }
9998 /* Use the constant equivalence if that is cheap enough. */
10004 {
10007 }
10009 /* If best_equiv is nonzero, we know that MEM is set to a
10010 constant or register before the loop. We will use this
10011 knowledge to initialize the shadow register with that
10012 constant or reg rather than by loading from MEM. */
10015 }
10020 {
10023 {
10026 }
10027 }
10033 {
10035 {
10038 }
10040 /* Store the memory immediately after END, which is
10041 the NOTE_LOOP_END. */
10044 }
10047 {
10052 }
10054 /* Attempt a bit of copy propagation. This helps untangle the
10055 data flow, and enables {basic,general}_induction_var to find
10056 more bivs/givs. */
10057 EXECUTE_IF_SET_IN_REG_SET
10059 {
10061 });
10064 EXECUTE_IF_SET_IN_REG_SET
10066 {
10068 });
10070 }
10071 }
10073 /* Now, we need to replace all references to the previous exit
10074 label with the new one. */
10081 }
10083 /* For communication between note_reg_stored and its caller. */
10084 struct note_reg_stored_arg
10085 {
10087 rtx reg;
10088 };
10090 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10091 is equal to ARG. */
10092 static void
10094 {
10098 }
10100 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10101 There must be exactly one insn that sets this pseudo; it will be
10102 deleted if all replacements succeed and we can prove that the register
10103 is not used after the loop. */
10105 static void
10107 {
10108 /* This is the reg that we are copying from. */
10111 rtx insn;
10112 /* These help keep track of whether we replaced all uses of the reg. */
10119 {
10120 rtx set;
10122 /* Only substitute within one extended basic block from the initializing
10123 insn. */
10130 /* Is this the initializing insn? */
10135 {
10142 }
10144 /* Only substitute after seeing the initializing insn. */
10146 {
10153 /* Stop replacing when REPLACEMENT is modified. */
10158 {
10161 /* It is possible that we've turned previously valid REG_EQUAL to
10162 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10163 REPLACEMENT is modified, we get different meaning. */
10167 }
10168 }
10169 }
10173 {
10177 {
10178 rtx first;
10179 rtx retval_note;
10181 /* Assume we're just deleting INIT_INSN. */
10183 /* Look for REG_RETVAL note. If we're deleting the end of
10184 the libcall sequence, the whole sequence can go. */
10186 /* If we found a REG_RETVAL note, find the first instruction
10187 in the sequence. */
10191 /* Delete the instructions. */
10193 }
10196 }
10197 }
10199 /* Replace all the instructions from FIRST up to and including LAST
10200 with NOTE_INSN_DELETED notes. */
10202 static void
10204 {
10206 {
10212 /* If this was the LAST instructions we're supposed to delete,
10213 we're done. */
10218 }
10219 }
10221 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10222 loop LOOP if the order of the sets of these registers can be
10223 swapped. There must be exactly one insn within the loop that sets
10224 this pseudo followed immediately by a move insn that sets
10225 REPLACEMENT with REGNO. */
10226 static void
10229 {
10230 rtx insn;
10239 {
10240 /* Search for the insn that copies REGNO to NEW_REGNO? */
10248 }
10251 {
10252 rtx prev_insn;
10253 rtx prev_set;
10255 /* Some DEF-USE info would come in handy here to make this
10256 function more general. For now, just check the previous insn
10257 which is the most likely candidate for setting REGNO. */
10265 {
10266 /* We have:
10267 (set (reg regno) (expr))
10268 (set (reg new_regno) (reg regno))
10270 so try converting this to:
10271 (set (reg new_regno) (expr))
10272 (set (reg regno) (reg new_regno))
10274 The former construct is often generated when a global
10275 variable used for an induction variable is shadowed by a
10276 register (NEW_REGNO). The latter construct improves the
10277 chances of GIV replacement and BIV elimination. */
10287 {
10294 /* Update first use of REGNO. */
10298 /* Now perform copy propagation to hopefully
10299 remove all uses of REGNO within the loop. */
10301 }
10302 }
10303 }
10304 }
10306 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10308 static int
10310 {
10312 {
10316 }
10318 }
10320 /* Returns the first MEM found in NOTE by depth-first search. */
10322 static rtx
10324 {
10328 }
10330 /* Replace MEM with its associated pseudo register. This function is
10331 called from load_mems via for_each_rtx. DATA is actually a pointer
10332 to a structure describing the instruction currently being scanned
10333 and the MEM we are currently replacing. */
10335 static int
10337 {
10345 {
10350 /* We're not interested in the MEM associated with a
10351 CONST_DOUBLE, so there's no need to traverse into one. */
10355 /* This is not a MEM. */
10357 }
10360 /* This is not the MEM we are currently replacing. */
10363 /* Actually replace the MEM. */
10367 }
10369 static void
10371 {
10372 loop_replace_args args;
10380 /* If we hoist a mem write out of the loop, then REG_EQUAL
10381 notes referring to the mem are no longer valid. */
10383 {
10388 {
10392 {
10393 /* Remove the note. */
10396 }
10397 }
10398 }
10399 }
10401 /* Replace one register with another. Called through for_each_rtx; PX points
10402 to the rtx being scanned. DATA is actually a pointer to
10403 a structure of arguments. */
10405 static int
10407 {
10418 }
10420 static void
10422 {
10423 loop_replace_args args;
10430 }
10431 \f
10432 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10433 (ignored in the interim). */
10435 static rtx
10438 rtx pattern)
10439 {
10441 }
10444 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10445 in basic block WHERE_BB (ignored in the interim) within the loop
10446 otherwise hoist PATTERN into the loop pre-header. */
10448 rtx
10450 basic_block where_bb ATTRIBUTE_UNUSED,
10452 {
10456 }
10459 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10460 WHERE_BB (ignored in the interim) within the loop. */
10462 static rtx
10464 basic_block where_bb ATTRIBUTE_UNUSED,
10466 {
10468 }
10471 /* Hoist insn for PATTERN into the loop pre-header. */
10473 rtx
10475 {
10477 }
10480 /* Hoist call insn for PATTERN into the loop pre-header. */
10482 static rtx
10484 {
10486 }
10489 /* Sink insn for PATTERN after the loop end. */
10491 rtx
10493 {
10495 }
10497 /* bl->final_value can be either general_operand or PLUS of general_operand
10498 and constant. Emit sequence of instructions to load it into REG. */
10499 static rtx
10501 {
10502 rtx seq;
10510 }
10512 /* If the loop has multiple exits, emit insn for PATTERN before the
10513 loop to ensure that it will always be executed no matter how the
10514 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10515 since this is slightly more efficient. */
10517 static rtx
10519 {
10522 else
10524 }
10525 \f
10526 static void
10528 {
10536 iv_num++;
10541 {
10544 }
10545 }
10548 static void
10551 {
10553 rtx incr;
10564 {
10567 }
10569 {
10572 }
10576 {
10580 }
10583 {
10587 }
10589 /* List the increments. */
10591 {
10595 }
10597 /* List the givs. */
10599 {
10604 else
10607 }
10608 }
10611 static void
10613 {
10624 {
10628 }
10631 }
10634 static void
10636 {
10643 else
10659 {
10661 {
10673 }
10674 }
10685 {
10689 }
10692 }
10695 void
10697 {
10699 }
10702 void
10704 {
10706 }
10709 void
10711 {
10713 }
10716 void
10718 {
10720 }
10723 #define LOOP_BLOCK_NUM_1(INSN) \
10724 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10726 /* The notes do not have an assigned block, so look at the next insn. */
10727 #define LOOP_BLOCK_NUM(INSN) \
10728 ((INSN) ? (NOTE_P (INSN) \
10729 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10730 : LOOP_BLOCK_NUM_1 (INSN)) \
10731 : -1)
10733 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10735 static void
10738 {
10739 rtx label;
10744 /* Print diagnostics to compare our concept of a loop with
10745 what the loop notes say. */
10760 {
10780 {
10783 {
10786 }
10787 }
10790 /* This can happen when a marked loop appears as two nested loops,
10791 say from while (a || b) {}. The inner loop won't match
10792 the loop markers but the outer one will. */
10795 }
10796 }
10798 /* Call this function from the debugger to dump LOOP. */
10800 void
10802 {
10804 }
10806 /* Call this function from the debugger to dump LOOPS. */
10808 void
10810 {
10812 }