RISC-V: Add patterns to convert AND mask to two shifts.
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / shift-shift-3.c
blobc974e75b38a9b701cfb404e9b633786b3f51474f
1 /* { dg-do compile } */
2 /* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
4 /* Test for lshrsi3_zero_extend_3+2 pattern that uses
5 high_mask_shift_operand. */
6 unsigned long
7 sub1 (unsigned long i)
9 return (i >> 32) << 32;
12 unsigned long
13 sub2 (unsigned long i)
15 return (i >> 63) << 63;
17 /* { dg-final { scan-assembler-times "slli" 2 } } */
18 /* { dg-final { scan-assembler-times "srli" 2 } } */