| blob | 88272567c5661fc32c3b64e0fa5aba50db155c4e |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
92 #ifndef CHECK_STACK_LIMIT
93 #define CHECK_STACK_LIMIT (-1)
94 #endif
96 /* Return index of given mode in mult and division cost tables. */
97 #define MODE_INDEX(mode) \
98 ((mode) == QImode ? 0 \
99 : (mode) == HImode ? 1 \
100 : (mode) == SImode ? 2 \
101 : (mode) == DImode ? 3 \
102 : 4)
104 /* Processor costs (relative to an add) */
105 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
106 #define COSTS_N_BYTES(N) ((N) * 2)
108 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
117 const
140 in QImode, HImode and SImode.
141 Relative to reg-reg move (2). */
145 in SFmode, DFmode and XFmode */
147 in SFmode, DFmode and XFmode */
150 in SImode and DImode */
152 in SImode and DImode */
155 in SImode, DImode and TImode */
157 in SImode, DImode and TImode */
170 ix86_size_memcpy,
171 ix86_size_memset,
183 };
185 /* Processor costs (relative to an add) */
188 DUMMY_STRINGOP_ALGS};
191 DUMMY_STRINGOP_ALGS};
193 static const
216 in QImode, HImode and SImode.
217 Relative to reg-reg move (2). */
221 in SFmode, DFmode and XFmode */
223 in SFmode, DFmode and XFmode */
226 in SImode and DImode */
228 in SImode and DImode */
231 in SImode, DImode and TImode */
233 in SImode, DImode and TImode */
246 i386_memcpy,
247 i386_memset,
259 };
263 DUMMY_STRINGOP_ALGS};
266 DUMMY_STRINGOP_ALGS};
268 static const
291 in QImode, HImode and SImode.
292 Relative to reg-reg move (2). */
296 in SFmode, DFmode and XFmode */
298 in SFmode, DFmode and XFmode */
301 in SImode and DImode */
303 in SImode and DImode */
306 in SImode, DImode and TImode */
308 in SImode, DImode and TImode */
311 shared for code and data, so 4kB is
312 not really precise. */
323 i486_memcpy,
324 i486_memset,
336 };
340 DUMMY_STRINGOP_ALGS};
343 DUMMY_STRINGOP_ALGS};
345 static const
368 in QImode, HImode and SImode.
369 Relative to reg-reg move (2). */
373 in SFmode, DFmode and XFmode */
375 in SFmode, DFmode and XFmode */
378 in SImode and DImode */
380 in SImode and DImode */
383 in SImode, DImode and TImode */
385 in SImode, DImode and TImode */
398 pentium_memcpy,
399 pentium_memset,
411 };
413 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
414 (we ensure the alignment). For small blocks inline loop is still a
415 noticeable win, for bigger blocks either rep movsl or rep movsb is
416 way to go. Rep movsb has apparently more expensive startup time in CPU,
417 but after 4K the difference is down in the noise. */
422 DUMMY_STRINGOP_ALGS};
427 DUMMY_STRINGOP_ALGS};
428 static const
451 in QImode, HImode and SImode.
452 Relative to reg-reg move (2). */
456 in SFmode, DFmode and XFmode */
458 in SFmode, DFmode and XFmode */
461 in SImode and DImode */
463 in SImode and DImode */
466 in SImode, DImode and TImode */
468 in SImode, DImode and TImode */
481 pentiumpro_memcpy,
482 pentiumpro_memset,
494 };
498 DUMMY_STRINGOP_ALGS};
501 DUMMY_STRINGOP_ALGS};
502 static const
525 in QImode, HImode and SImode.
526 Relative to reg-reg move (2). */
530 in SFmode, DFmode and XFmode */
532 in SFmode, DFmode and XFmode */
536 in SImode and DImode */
538 in SImode and DImode */
541 in SImode, DImode and TImode */
543 in SImode, DImode and TImode */
556 geode_memcpy,
557 geode_memset,
569 };
573 DUMMY_STRINGOP_ALGS};
576 DUMMY_STRINGOP_ALGS};
577 static const
600 in QImode, HImode and SImode.
601 Relative to reg-reg move (2). */
605 in SFmode, DFmode and XFmode */
607 in SFmode, DFmode and XFmode */
610 in SImode and DImode */
612 in SImode and DImode */
615 in SImode, DImode and TImode */
617 in SImode, DImode and TImode */
621 have integrated l2 cache, but
622 optimizing for k6 is not important
623 enough to worry about that. */
633 k6_memcpy,
634 k6_memset,
646 };
648 /* For some reason, Athlon deals better with REP prefix (relative to loops)
649 compared to K8. Alignment becomes important after 8 bytes for memcpy and
650 128 bytes for memset. */
653 DUMMY_STRINGOP_ALGS};
656 DUMMY_STRINGOP_ALGS};
657 static const
680 in QImode, HImode and SImode.
681 Relative to reg-reg move (2). */
685 in SFmode, DFmode and XFmode */
687 in SFmode, DFmode and XFmode */
690 in SImode and DImode */
692 in SImode and DImode */
695 in SImode, DImode and TImode */
697 in SImode, DImode and TImode */
710 athlon_memcpy,
711 athlon_memset,
723 };
725 /* K8 has optimized REP instruction for medium sized blocks, but for very
726 small blocks it is better to use loop. For large blocks, libcall can
727 do nontemporary accesses and beat inline considerably. */
738 static const
761 in QImode, HImode and SImode.
762 Relative to reg-reg move (2). */
766 in SFmode, DFmode and XFmode */
768 in SFmode, DFmode and XFmode */
771 in SImode and DImode */
773 in SImode and DImode */
776 in SImode, DImode and TImode */
778 in SImode, DImode and TImode */
783 /* New AMD processors never drop prefetches; if they cannot be performed
784 immediately, they are queued. We set number of simultaneous prefetches
785 to a large constant to reflect this (it probably is not a good idea not
786 to limit number of prefetches at all, as their execution also takes some
787 time). */
797 k8_memcpy,
798 k8_memset,
810 };
812 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
813 very small blocks it is better to use loop. For large blocks, libcall can
814 do nontemporary accesses and beat inline considerably. */
847 in QImode, HImode and SImode.
848 Relative to reg-reg move (2). */
852 in SFmode, DFmode and XFmode */
854 in SFmode, DFmode and XFmode */
857 in SImode and DImode */
859 in SImode and DImode */
862 in SImode, DImode and TImode */
864 in SImode, DImode and TImode */
866 /* On K8:
867 MOVD reg64, xmmreg Double FSTORE 4
868 MOVD reg32, xmmreg Double FSTORE 4
869 On AMDFAM10:
870 MOVD reg64, xmmreg Double FADD 3
871 1/1 1/1
872 MOVD reg32, xmmreg Double FADD 3
873 1/1 1/1 */
877 /* New AMD processors never drop prefetches; if they cannot be performed
878 immediately, they are queued. We set number of simultaneous prefetches
879 to a large constant to reflect this (it probably is not a good idea not
880 to limit number of prefetches at all, as their execution also takes some
881 time). */
891 amdfam10_memcpy,
892 amdfam10_memset,
904 };
906 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
907 very small blocks it is better to use loop. For large blocks, libcall
908 can do nontemporary accesses and beat inline considerably. */
942 in QImode, HImode and SImode.
943 Relative to reg-reg move (2). */
947 in SFmode, DFmode and XFmode */
949 in SFmode, DFmode and XFmode */
952 in SImode and DImode */
954 in SImode and DImode */
957 in SImode, DImode and TImode */
959 in SImode, DImode and TImode */
961 /* On K8:
962 MOVD reg64, xmmreg Double FSTORE 4
963 MOVD reg32, xmmreg Double FSTORE 4
964 On AMDFAM10:
965 MOVD reg64, xmmreg Double FADD 3
966 1/1 1/1
967 MOVD reg32, xmmreg Double FADD 3
968 1/1 1/1 */
972 /* New AMD processors never drop prefetches; if they cannot be performed
973 immediately, they are queued. We set number of simultaneous prefetches
974 to a large constant to reflect this (it probably is not a good idea not
975 to limit number of prefetches at all, as their execution also takes some
976 time). */
986 bdver1_memcpy,
987 bdver1_memset,
999 };
1001 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1002 very small blocks it is better to use loop. For large blocks, libcall
1003 can do nontemporary accesses and beat inline considerably. */
1038 in QImode, HImode and SImode.
1039 Relative to reg-reg move (2). */
1043 in SFmode, DFmode and XFmode */
1045 in SFmode, DFmode and XFmode */
1048 in SImode and DImode */
1050 in SImode and DImode */
1053 in SImode, DImode and TImode */
1055 in SImode, DImode and TImode */
1057 /* On K8:
1058 MOVD reg64, xmmreg Double FSTORE 4
1059 MOVD reg32, xmmreg Double FSTORE 4
1060 On AMDFAM10:
1061 MOVD reg64, xmmreg Double FADD 3
1062 1/1 1/1
1063 MOVD reg32, xmmreg Double FADD 3
1064 1/1 1/1 */
1068 /* New AMD processors never drop prefetches; if they cannot be performed
1069 immediately, they are queued. We set number of simultaneous prefetches
1070 to a large constant to reflect this (it probably is not a good idea not
1071 to limit number of prefetches at all, as their execution also takes some
1072 time). */
1082 bdver2_memcpy,
1083 bdver2_memset,
1095 };
1098 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1099 very small blocks it is better to use loop. For large blocks, libcall
1100 can do nontemporary accesses and beat inline considerably. */
1133 in QImode, HImode and SImode.
1134 Relative to reg-reg move (2). */
1138 in SFmode, DFmode and XFmode */
1140 in SFmode, DFmode and XFmode */
1143 in SImode and DImode */
1145 in SImode and DImode */
1148 in SImode, DImode and TImode */
1150 in SImode, DImode and TImode */
1155 /* New AMD processors never drop prefetches; if they cannot be performed
1156 immediately, they are queued. We set number of simultaneous prefetches
1157 to a large constant to reflect this (it probably is not a good idea not
1158 to limit number of prefetches at all, as their execution also takes some
1159 time). */
1169 bdver3_memcpy,
1170 bdver3_memset,
1182 };
1184 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1185 very small blocks it is better to use loop. For large blocks, libcall
1186 can do nontemporary accesses and beat inline considerably. */
1219 in QImode, HImode and SImode.
1220 Relative to reg-reg move (2). */
1224 in SFmode, DFmode and XFmode */
1226 in SFmode, DFmode and XFmode */
1229 in SImode and DImode */
1231 in SImode and DImode */
1234 in SImode, DImode and TImode */
1236 in SImode, DImode and TImode */
1241 /* New AMD processors never drop prefetches; if they cannot be performed
1242 immediately, they are queued. We set number of simultaneous prefetches
1243 to a large constant to reflect this (it probably is not a good idea not
1244 to limit number of prefetches at all, as their execution also takes some
1245 time). */
1255 bdver4_memcpy,
1256 bdver4_memset,
1268 };
1270 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1271 very small blocks it is better to use loop. For large blocks, libcall can
1272 do nontemporary accesses and beat inline considerably. */
1305 in QImode, HImode and SImode.
1306 Relative to reg-reg move (2). */
1310 in SFmode, DFmode and XFmode */
1312 in SFmode, DFmode and XFmode */
1315 in SImode and DImode */
1317 in SImode and DImode */
1320 in SImode, DImode and TImode */
1322 in SImode, DImode and TImode */
1324 /* On K8:
1325 MOVD reg64, xmmreg Double FSTORE 4
1326 MOVD reg32, xmmreg Double FSTORE 4
1327 On AMDFAM10:
1328 MOVD reg64, xmmreg Double FADD 3
1329 1/1 1/1
1330 MOVD reg32, xmmreg Double FADD 3
1331 1/1 1/1 */
1344 btver1_memcpy,
1345 btver1_memset,
1357 };
1391 in QImode, HImode and SImode.
1392 Relative to reg-reg move (2). */
1396 in SFmode, DFmode and XFmode */
1398 in SFmode, DFmode and XFmode */
1401 in SImode and DImode */
1403 in SImode and DImode */
1406 in SImode, DImode and TImode */
1408 in SImode, DImode and TImode */
1410 /* On K8:
1411 MOVD reg64, xmmreg Double FSTORE 4
1412 MOVD reg32, xmmreg Double FSTORE 4
1413 On AMDFAM10:
1414 MOVD reg64, xmmreg Double FADD 3
1415 1/1 1/1
1416 MOVD reg32, xmmreg Double FADD 3
1417 1/1 1/1 */
1429 btver2_memcpy,
1430 btver2_memset,
1442 };
1446 DUMMY_STRINGOP_ALGS};
1450 DUMMY_STRINGOP_ALGS};
1452 static const
1475 in QImode, HImode and SImode.
1476 Relative to reg-reg move (2). */
1480 in SFmode, DFmode and XFmode */
1482 in SFmode, DFmode and XFmode */
1485 in SImode and DImode */
1487 in SImode and DImode */
1490 in SImode, DImode and TImode */
1492 in SImode, DImode and TImode */
1505 pentium4_memcpy,
1506 pentium4_memset,
1518 };
1531 static const
1554 in QImode, HImode and SImode.
1555 Relative to reg-reg move (2). */
1559 in SFmode, DFmode and XFmode */
1561 in SFmode, DFmode and XFmode */
1564 in SImode and DImode */
1566 in SImode and DImode */
1569 in SImode, DImode and TImode */
1571 in SImode, DImode and TImode */
1584 nocona_memcpy,
1585 nocona_memset,
1597 };
1608 static const
1631 in QImode, HImode and SImode.
1632 Relative to reg-reg move (2). */
1636 in SFmode, DFmode and XFmode */
1638 in SFmode, DFmode and XFmode */
1641 in SImode and DImode */
1643 in SImode and DImode */
1646 in SImode, DImode and TImode */
1648 in SImode, DImode and TImode */
1661 atom_memcpy,
1662 atom_memset,
1674 };
1685 static const
1708 in QImode, HImode and SImode.
1709 Relative to reg-reg move (2). */
1713 in SFmode, DFmode and XFmode */
1715 in SFmode, DFmode and XFmode */
1718 in SImode and DImode */
1720 in SImode and DImode */
1723 in SImode, DImode and TImode */
1725 in SImode, DImode and TImode */
1738 slm_memcpy,
1739 slm_memset,
1751 };
1762 static const
1785 in QImode, HImode and SImode.
1786 Relative to reg-reg move (2). */
1790 in SFmode, DFmode and XFmode */
1792 in SFmode, DFmode and XFmode */
1795 in SImode and DImode */
1797 in SImode and DImode */
1800 in SImode, DImode and TImode */
1802 in SImode, DImode and TImode */
1815 intel_memcpy,
1816 intel_memset,
1828 };
1830 /* Generic should produce code tuned for Core-i7 (and newer chips)
1831 and btver1 (and newer chips). */
1843 static const
1846 /* On all chips taken into consideration lea is 2 cycles and more. With
1847 this cost however our current implementation of synth_mult results in
1848 use of unnecessary temporary registers causing regression on several
1849 SPECfp benchmarks. */
1870 in QImode, HImode and SImode.
1871 Relative to reg-reg move (2). */
1875 in SFmode, DFmode and XFmode */
1877 in SFmode, DFmode and XFmode */
1880 in SImode and DImode */
1882 in SImode and DImode */
1885 in SImode, DImode and TImode */
1887 in SImode, DImode and TImode */
1893 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1894 value is increased to perhaps more appropriate value of 5. */
1902 generic_memcpy,
1903 generic_memset,
1915 };
1917 /* core_cost should produce code tuned for Core familly of CPUs. */
1930 static const
1933 /* On all chips taken into consideration lea is 2 cycles and more. With
1934 this cost however our current implementation of synth_mult results in
1935 use of unnecessary temporary registers causing regression on several
1936 SPECfp benchmarks. */
1957 in QImode, HImode and SImode.
1958 Relative to reg-reg move (2). */
1962 in SFmode, DFmode and XFmode */
1964 in SFmode, DFmode and XFmode */
1967 in SImode and DImode */
1969 in SImode and DImode */
1972 in SImode, DImode and TImode */
1974 in SImode, DImode and TImode */
1980 /* FIXME perhaps more appropriate value is 5. */
1988 core_memcpy,
1989 core_memset,
2001 };
2004 /* Set by -mtune. */
2007 /* Set by -mtune or -Os. */
2010 /* Processor feature/optimization bitmasks. */
2011 #define m_386 (1<<PROCESSOR_I386)
2012 #define m_486 (1<<PROCESSOR_I486)
2013 #define m_PENT (1<<PROCESSOR_PENTIUM)
2014 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2015 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2016 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2017 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2018 #define m_CORE2 (1<<PROCESSOR_CORE2)
2019 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2020 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2021 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2022 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2023 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2024 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2025 #define m_INTEL (1<<PROCESSOR_INTEL)
2027 #define m_GEODE (1<<PROCESSOR_GEODE)
2028 #define m_K6 (1<<PROCESSOR_K6)
2029 #define m_K6_GEODE (m_K6 | m_GEODE)
2030 #define m_K8 (1<<PROCESSOR_K8)
2031 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2032 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2033 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2034 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2035 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2036 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2037 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2038 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2039 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2040 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2041 #define m_BTVER (m_BTVER1 | m_BTVER2)
2042 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2044 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2047 #undef DEF_TUNE
2048 #define DEF_TUNE(tune, name, selector) name,
2050 #undef DEF_TUNE
2051 };
2053 /* Feature tests against the various tunings. */
2056 /* Feature tests against the various tunings used to create ix86_tune_features
2057 based on the processor mask. */
2059 #undef DEF_TUNE
2060 #define DEF_TUNE(tune, name, selector) selector,
2062 #undef DEF_TUNE
2063 };
2065 /* Feature tests against the various architecture variations. */
2068 /* Feature tests against the various architecture variations, used to create
2069 ix86_arch_features based on the processor mask. */
2071 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2074 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2077 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2080 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2083 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2085 };
2087 /* In case the average insn count for single function invocation is
2088 lower than this constant, emit fast (but longer) prologue and
2089 epilogue code. */
2090 #define FAST_PROLOGUE_INSN_COUNT 20
2092 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2097 /* Array of the smallest class containing reg number REGNO, indexed by
2098 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2101 {
2102 /* ax, dx, cx, bx */
2104 /* si, di, bp, sp */
2106 /* FP registers */
2109 /* arg pointer */
2110 NON_Q_REGS,
2111 /* flags, fpsr, fpcr, frame */
2113 /* SSE registers */
2116 /* MMX registers */
2119 /* REX registers */
2122 /* SSE REX registers */
2125 /* AVX-512 SSE registers */
2130 /* Mask registers. */
2133 };
2135 /* The "default" register map used in 32bit mode. */
2138 {
2149 };
2151 /* The "default" register map used in 64bit mode. */
2154 {
2165 };
2167 /* Define the register numbers to be used in Dwarf debugging information.
2168 The SVR4 reference port C compiler uses the following register numbers
2169 in its Dwarf output code:
2170 0 for %eax (gcc regno = 0)
2171 1 for %ecx (gcc regno = 2)
2172 2 for %edx (gcc regno = 1)
2173 3 for %ebx (gcc regno = 3)
2174 4 for %esp (gcc regno = 7)
2175 5 for %ebp (gcc regno = 6)
2176 6 for %esi (gcc regno = 4)
2177 7 for %edi (gcc regno = 5)
2178 The following three DWARF register numbers are never generated by
2179 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2180 believes these numbers have these meanings.
2181 8 for %eip (no gcc equivalent)
2182 9 for %eflags (gcc regno = 17)
2183 10 for %trapno (no gcc equivalent)
2184 It is not at all clear how we should number the FP stack registers
2185 for the x86 architecture. If the version of SDB on x86/svr4 were
2186 a bit less brain dead with respect to floating-point then we would
2187 have a precedent to follow with respect to DWARF register numbers
2188 for x86 FP registers, but the SDB on x86/svr4 is so completely
2189 broken with respect to FP registers that it is hardly worth thinking
2190 of it as something to strive for compatibility with.
2191 The version of x86/svr4 SDB I have at the moment does (partially)
2192 seem to believe that DWARF register number 11 is associated with
2193 the x86 register %st(0), but that's about all. Higher DWARF
2194 register numbers don't seem to be associated with anything in
2195 particular, and even for DWARF regno 11, SDB only seems to under-
2196 stand that it should say that a variable lives in %st(0) (when
2197 asked via an `=' command) if we said it was in DWARF regno 11,
2198 but SDB still prints garbage when asked for the value of the
2199 variable in question (via a `/' command).
2200 (Also note that the labels SDB prints for various FP stack regs
2201 when doing an `x' command are all wrong.)
2202 Note that these problems generally don't affect the native SVR4
2203 C compiler because it doesn't allow the use of -O with -g and
2204 because when it is *not* optimizing, it allocates a memory
2205 location for each floating-point variable, and the memory
2206 location is what gets described in the DWARF AT_location
2207 attribute for the variable in question.
2208 Regardless of the severe mental illness of the x86/svr4 SDB, we
2209 do something sensible here and we use the following DWARF
2210 register numbers. Note that these are all stack-top-relative
2211 numbers.
2212 11 for %st(0) (gcc regno = 8)
2213 12 for %st(1) (gcc regno = 9)
2214 13 for %st(2) (gcc regno = 10)
2215 14 for %st(3) (gcc regno = 11)
2216 15 for %st(4) (gcc regno = 12)
2217 16 for %st(5) (gcc regno = 13)
2218 17 for %st(6) (gcc regno = 14)
2219 18 for %st(7) (gcc regno = 15)
2220 */
2222 {
2233 };
2235 /* Define parameter passing and return registers. */
2238 {
2240 };
2243 {
2245 };
2248 {
2250 };
2252 /* Additional registers that are clobbered by SYSV calls. */
2255 {
2260 };
2262 /* Define the structure for the machine field in struct function. */
2267 rtx rtl;
2269 };
2271 /* Structure describing stack frame layout.
2272 Stack grows downward:
2274 [arguments]
2275 <- ARG_POINTER
2276 saved pc
2278 saved static chain if ix86_static_chain_on_stack
2280 saved frame pointer if frame_pointer_needed
2281 <- HARD_FRAME_POINTER
2282 [saved regs]
2283 <- regs_save_offset
2284 [padding0]
2286 [saved SSE regs]
2287 <- sse_regs_save_offset
2288 [padding1] |
2289 | <- FRAME_POINTER
2290 [va_arg registers] |
2291 |
2292 [frame] |
2293 |
2294 [padding2] | = to_allocate
2295 <- STACK_POINTER
2296 */
2297 struct ix86_frame
2298 {
2305 /* The offsets relative to ARG_POINTER. */
2306 HOST_WIDE_INT frame_pointer_offset;
2307 HOST_WIDE_INT hard_frame_pointer_offset;
2308 HOST_WIDE_INT stack_pointer_offset;
2309 HOST_WIDE_INT hfp_save_offset;
2310 HOST_WIDE_INT reg_save_offset;
2311 HOST_WIDE_INT sse_reg_save_offset;
2313 /* When save_regs_using_mov is set, emit prologue using
2314 move instead of push instructions. */
2316 };
2318 /* Which cpu are we scheduling for. */
2321 /* Which cpu are we optimizing for. */
2324 /* Which instruction set architecture to use. */
2327 /* True if processor has SSE prefetch instruction. */
2330 /* -mstackrealign option */
2347 /* Preferred alignment for stack boundary in bits. */
2350 /* Alignment for incoming stack boundary in bits specified at
2351 command line. */
2354 /* Default alignment for incoming stack boundary in bits. */
2357 /* Alignment for incoming stack boundary in bits. */
2360 /* Calling abi specific va_list type nodes. */
2364 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2368 /* Fence to use after loop using movnt. */
2369 tree x86_mfence;
2371 /* Register class used for passing given 64bit part of the argument.
2372 These represent classes as documented by the PS ABI, with the exception
2373 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2374 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2376 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2377 whenever possible (upper half does contain padding). */
2378 enum x86_64_reg_class
2379 {
2380 X86_64_NO_CLASS,
2381 X86_64_INTEGER_CLASS,
2382 X86_64_INTEGERSI_CLASS,
2383 X86_64_SSE_CLASS,
2384 X86_64_SSESF_CLASS,
2385 X86_64_SSEDF_CLASS,
2386 X86_64_SSEUP_CLASS,
2387 X86_64_X87_CLASS,
2388 X86_64_X87UP_CLASS,
2389 X86_64_COMPLEX_X87_CLASS,
2390 X86_64_MEMORY_CLASS
2391 };
2393 #define MAX_CLASSES 8
2395 /* Table of constants used by fldpi, fldln2, etc.... */
2399 \f
2404 const_tree);
2416 enum ix86_function_specific_strings
2417 {
2418 IX86_FUNCTION_SPECIFIC_ARCH,
2419 IX86_FUNCTION_SPECIFIC_TUNE,
2420 IX86_FUNCTION_SPECIFIC_MAX
2421 };
2442 \f
2443 #ifndef SUBTARGET32_DEFAULT_CPU
2445 #endif
2447 /* Whether -mtune= or -march= were specified */
2451 /* Vectorization library interface and handlers. */
2457 /* Processor target table, indexed by processor number */
2458 struct ptt
2459 {
2467 };
2469 /* This table must be in sync with enum processor_type in i386.h. */
2471 {
2497 };
2498 \f
2499 static unsigned int
2501 {
2504 /* vzeroupper instructions are inserted immediately after reload to
2505 account for possible spills from 256bit registers. The pass
2506 reuses mode switching infrastructure by re-running mode insertion
2507 pass, so disable entities that have already been processed. */
2513 /* Call optimize_mode_switching. */
2516 }
2521 {
2532 };
2535 {
2539 {}
2541 /* opt_pass methods: */
2543 {
2545 }
2548 {
2550 }
2556 rtl_opt_pass *
2558 {
2560 }
2562 /* Return true if a red-zone is in use. */
2566 {
2568 }
2569 \f
2570 /* Return a string that documents the current -m options. The caller is
2571 responsible for freeing the string. */
2577 {
2578 struct ix86_target_opts
2579 {
2582 };
2584 /* This table is ordered so that options like -msse4.2 that imply
2585 preceding options while match those first. */
2587 {
2632 };
2634 /* Flag options. */
2636 {
2665 };
2682 /* Add -march= option. */
2684 {
2687 }
2689 /* Add -mtune= option. */
2691 {
2694 }
2696 /* Add -m32/-m64/-mx32. */
2698 {
2701 else
2703 isa &= ~ (OPTION_MASK_ISA_64BIT
2704 | OPTION_MASK_ABI_64
2706 }
2707 else
2711 /* Pick out the options in isa options. */
2713 {
2715 {
2718 }
2719 }
2722 {
2725 isa);
2726 }
2728 /* Add flag options. */
2730 {
2732 {
2735 }
2736 }
2739 {
2742 }
2744 /* Add -fpmath= option. */
2746 {
2749 {
2764 }
2765 }
2767 /* Any options? */
2773 /* Size the string. */
2777 {
2782 }
2784 /* Build the string. */
2789 {
2796 {
2798 line_len++;
2801 {
2805 }
2806 }
2810 {
2814 }
2815 }
2821 }
2823 /* Return true, if profiling code should be emitted before
2824 prologue. Otherwise it returns false.
2825 Note: For x86 with "hotfix" it is sorried. */
2826 static bool
2828 {
2830 }
2832 /* Function that is callable from the debugger to print the current
2833 options. */
2834 void ATTRIBUTE_UNUSED
2836 {
2842 {
2845 }
2846 else
2850 }
2853 #define DEF_ENUM
2854 #define DEF_ALG(alg, name) #name,
2856 #undef DEF_ENUM
2857 #undef DEF_ALG
2858 };
2860 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2861 The string is of the following form (or comma separated list of it):
2863 strategy_alg:max_size:[align|noalign]
2865 where the full size range for the strategy is either [0, max_size] or
2866 [min_size, max_size], in which min_size is the max_size + 1 of the
2867 preceding range. The last size range must have max_size == -1.
2869 Examples:
2871 1.
2872 -mmemcpy-strategy=libcall:-1:noalign
2874 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2877 2.
2878 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2880 This is to tell the compiler to use the following strategy for memset
2881 1) when the expected size is between [1, 16], use rep_8byte strategy;
2882 2) when the size is between [17, 2048], use vector_loop;
2883 3) when the size is > 2048, use libcall. */
2885 struct stringop_size_range
2886 {
2888 stringop_alg alg;
2890 };
2892 static void
2894 {
2902 else
2907 do
2908 {
2918 {
2922 }
2925 {
2929 }
2936 {
2938 alg_name,
2941 }
2949 else
2950 {
2954 }
2955 n++;
2957 }
2961 {
2966 }
2969 {
2973 }
2975 /* Now override the default algs array. */
2977 {
2983 }
2984 }
2986 \f
2987 /* parse -mtune-ctrl= option. When DUMP is true,
2988 print the features that are explicitly set. */
2990 static void
2992 {
3000 do
3001 {
3008 {
3009 curr_feature_string++;
3011 }
3013 {
3015 {
3021 }
3022 }
3027 }
3030 }
3032 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3033 processor type. */
3035 static void
3037 {
3042 {
3045 else
3047 }
3050 {
3055 }
3058 }
3061 /* Override various settings based on options. If MAIN_ARGS_P, the
3062 options are from the command line, otherwise they are from
3063 attributes. */
3065 static void
3069 {
3077 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3078 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3079 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3080 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3081 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3082 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3083 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3084 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3085 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3086 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3087 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3088 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3089 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3090 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3091 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3092 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3093 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3094 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3095 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3096 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3097 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3098 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3099 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3100 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3101 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3102 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3103 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3104 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3105 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3106 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3107 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3108 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3109 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3110 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3111 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3112 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3113 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3114 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3115 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3116 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3117 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3118 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3119 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3120 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3121 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3122 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3123 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3124 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3125 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3127 #define PTA_CORE2 \
3128 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3129 | PTA_CX16 | PTA_FXSR)
3130 #define PTA_NEHALEM \
3131 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3132 #define PTA_WESTMERE \
3133 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3134 #define PTA_SANDYBRIDGE \
3135 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3136 #define PTA_IVYBRIDGE \
3137 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3138 #define PTA_HASWELL \
3139 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3140 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3141 #define PTA_BROADWELL \
3142 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3143 #define PTA_BONNELL \
3144 (PTA_CORE2 | PTA_MOVBE)
3145 #define PTA_SILVERMONT \
3146 (PTA_WESTMERE | PTA_MOVBE)
3148 /* if this reaches 64, need to widen struct pta flags below */
3150 static struct pta
3151 {
3156 }
3158 {
3192 PTA_SANDYBRIDGE},
3194 PTA_SANDYBRIDGE},
3196 PTA_IVYBRIDGE},
3198 PTA_IVYBRIDGE},
3288 PTA_64BIT
3290 };
3292 /* -mrecip options. */
3293 static struct
3294 {
3297 }
3299 {
3306 };
3310 /* Set up prefix/suffix so the error messages refer to either the command
3311 line argument, or the attribute(target). */
3313 {
3317 }
3318 else
3319 {
3323 }
3325 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3326 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3329 #ifdef TARGET_BI_ARCH
3330 else
3331 {
3332 #if TARGET_BI_ARCH == 1
3333 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3334 is on and OPTION_MASK_ABI_X32 is off. We turn off
3335 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3336 -mx32. */
3339 #else
3340 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3341 on and OPTION_MASK_ABI_64 is off. We turn off
3342 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3343 -m64. */
3346 #endif
3347 }
3348 #endif
3351 {
3352 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3353 OPTION_MASK_ABI_64 for TARGET_X32. */
3356 }
3359 | OPTION_MASK_ABI_X32
3362 {
3363 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3364 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3367 }
3369 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3370 SUBTARGET_OVERRIDE_OPTIONS;
3371 #endif
3373 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3374 SUBSUBTARGET_OVERRIDE_OPTIONS;
3375 #endif
3377 /* -fPIC is the default for x86_64. */
3381 /* Need to check -mtune=generic first. */
3383 {
3384 /* As special support for cross compilers we read -mtune=native
3385 as -mtune=generic. With native compilers we won't see the
3386 -mtune=native, as it was changed by the driver. */
3388 {
3390 }
3395 }
3396 else
3397 {
3401 {
3402 opts->x_ix86_tune_string
3405 }
3407 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3408 or defaulted. We need to use a sensible tune option. */
3410 {
3412 }
3413 }
3417 {
3418 /* rep; movq isn't available in 32-bit code. */
3421 }
3424 opts->x_ix86_arch_string
3427 else
3431 {
3439 }
3440 else
3447 /* For targets using ms ABI enable ms-extensions, if not
3448 explicit turned off. For non-ms ABI we turn off this
3449 option. */
3454 {
3456 {
3500 {
3503 }
3511 }
3512 }
3513 else
3514 {
3515 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3516 use of rip-relative addressing. This eliminates fixups that
3517 would otherwise be needed if this object is to be placed in a
3518 DLL, and is essentially just as efficient as direct addressing. */
3524 else
3526 }
3528 {
3531 }
3539 {
3542 /* Default cpu tuning to the architecture. */
3696 }
3714 {
3718 {
3720 {
3722 {
3730 }
3731 else
3734 }
3735 }
3736 /* Intel CPUs have always interpreted SSE prefetch instructions as
3737 NOPs; so, we can enable SSE prefetch instructions even when
3738 -mtune (rather than -march) points us to a processor that has them.
3739 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3740 higher processors. */
3745 }
3753 #ifndef USE_IX86_FRAME_POINTER
3754 #define USE_IX86_FRAME_POINTER 0
3755 #endif
3757 #ifndef USE_X86_64_FRAME_POINTER
3758 #define USE_X86_64_FRAME_POINTER 0
3759 #endif
3761 /* Set the default values for switches whose default depends on TARGET_64BIT
3762 in case they weren't overwritten by command line options. */
3764 {
3772 opts->x_flag_unwind_tables
3776 }
3777 else
3778 {
3780 opts->x_flag_omit_frame_pointer
3786 }
3791 else
3794 /* Arrange to set up i386_stack_locals for all functions. */
3797 /* Validate -mregparm= value. */
3799 {
3803 {
3807 }
3808 }
3812 /* Default align_* from the processor table. */
3814 {
3817 }
3819 {
3822 }
3824 {
3826 }
3828 /* Provide default for -mbranch-cost= value. */
3833 {
3834 opts->x_target_flags
3837 /* Enable by default the SSE and MMX builtins. Do allow the user to
3838 explicitly disable any of these. In particular, disabling SSE and
3839 MMX for kernel code is extremely useful. */
3841 opts->x_ix86_isa_flags
3848 }
3849 else
3850 {
3851 opts->x_target_flags
3855 opts->x_ix86_isa_flags
3858 /* i386 ABI does not specify red zone. It still makes sense to use it
3859 when programmer takes care to stack from being destroyed. */
3862 }
3864 /* Keep nonleaf frame pointers. */
3870 /* If we're doing fast math, we don't care about comparison order
3871 wrt NaNs. This lets us use a shorter comparison sequence. */
3875 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3876 since the insns won't need emulation. */
3880 /* Likewise, if the target doesn't have a 387, or we've specified
3881 software floating point, don't use 387 inline intrinsics. */
3885 /* Turn on MMX builtins for -msse. */
3887 opts->x_ix86_isa_flags
3890 /* Enable SSE prefetch. */
3895 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3898 opts->x_ix86_isa_flags
3901 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3904 opts->x_ix86_isa_flags
3907 /* Enable lzcnt instruction for -mabm. */
3909 opts->x_ix86_isa_flags
3912 /* Validate -mpreferred-stack-boundary= value or default it to
3913 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3916 {
3923 {
3927 else
3930 }
3931 else
3932 ix86_preferred_stack_boundary
3934 }
3936 /* Set the default value for -mstackrealign. */
3942 /* Validate -mincoming-stack-boundary= value or default it to
3943 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3946 {
3953 else
3954 {
3955 ix86_user_incoming_stack_boundary
3957 ix86_incoming_stack_boundary
3959 }
3960 }
3962 /* Accept -msseregparm only if at least SSE support is enabled. */
3968 {
3970 {
3972 {
3975 }
3978 {
3981 }
3982 }
3983 }
3984 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3985 fpmath=387. The second is however default at many targets since the
3986 extra 80bit precision of temporaries is considered to be part of ABI.
3987 Overwrite the default at least for -ffast-math.
3988 TODO: -mfpmath=both seems to produce same performing code with bit
3989 smaller binaries. It is however not clear if register allocation is
3990 ready for this setting.
3991 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3992 codegen. We may switch to 387 with -ffast-math for size optimized
3993 functions. */
3997 else
4000 /* If the i387 is disabled, then do not return values in it. */
4004 /* Use external vectorized library in vectorizing intrinsics. */
4007 {
4018 }
4025 /* If stack probes are required, the space used for large function
4026 arguments on the stack must also be probed, so enable
4027 -maccumulate-outgoing-args so this happens in the prologue. */
4030 {
4035 }
4037 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4038 {
4044 }
4046 /* When scheduling description is not available, disable scheduler pass
4047 so it won't slow down the compilation and make x87 code slower. */
4068 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4070 && HAVE_prefetch
4075 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4076 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4081 {
4084 {
4086 ix86_gen_tls_local_dynamic_base_64
4088 }
4089 else
4090 {
4092 ix86_gen_tls_local_dynamic_base_64
4094 }
4095 }
4096 else
4100 {
4110 }
4111 else
4112 {
4122 }
4124 #ifdef USE_IX86_CLD
4125 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4128 #endif
4131 {
4136 }
4138 {
4142 }
4144 {
4145 #if defined(PROFILE_BEFORE_PROLOGUE)
4147 #else
4149 #endif
4150 }
4152 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4153 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4154 AVX unaligned load/store. */
4156 {
4166 /* Enable 128-bit AVX instruction generation
4167 for the auto-vectorizer. */
4171 }
4174 {
4181 {
4184 {
4186 q++;
4187 }
4188 else
4193 else
4194 {
4197 {
4200 }
4203 {
4207 }
4208 }
4213 else
4215 }
4216 }
4223 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4224 for 64-bit Bionic. */
4229 ? MASK_LONG_DOUBLE_128
4232 /* Only one of them can be active. */
4236 /* Save the initial options in case the user does function specific
4237 options. */
4239 target_option_default_node = target_option_current_node
4242 /* Handle stack protector */
4244 opts->x_ix86_stack_protector_guard
4247 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4249 {
4253 }
4256 {
4260 }
4261 }
4263 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4265 static void
4267 {
4269 static struct register_pass_info insert_vzeroupper_info
4272 };
4277 /* This needs to be done at start up. It's convenient to do it here. */
4279 }
4281 /* Update register usage after having seen the compiler flags. */
4283 static void
4285 {
4289 /* The PIC register, if it exists, is fixed. */
4294 /* For 32-bit targets, squash the REX registers. */
4296 {
4303 }
4305 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4313 {
4314 /* Set/reset conditionally defined registers from
4315 CALL_USED_REGISTERS initializer. */
4319 /* Calculate registers of CLOBBERED_REGS register set
4320 as call used registers from GENERAL_REGS register set. */
4324 }
4326 /* If MMX is disabled, squash the registers. */
4332 /* If SSE is disabled, squash the registers. */
4338 /* If the FPU is disabled, squash the registers. */
4344 /* If AVX512F is disabled, squash the registers. */
4346 {
4352 }
4353 }
4355 \f
4356 /* Save the current options */
4358 static void
4361 {
4396 /* The fields are char but the variables are not; make sure the
4397 values fit in the fields. */
4402 }
4404 /* Restore the current options */
4406 static void
4409 {
4415 /* We don't change -fPIC. */
4452 /* Recreate the arch feature tests if the arch changed */
4454 {
4459 }
4461 /* Recreate the tune optimization tests */
4464 }
4466 /* Print the current options */
4468 static void
4471 {
4489 {
4492 }
4493 }
4495 \f
4496 /* Inner function to process the attribute((target(...))), take an argument and
4497 set the current options from the argument. If we have a list, recursively go
4498 over the list. */
4500 static bool
4505 {
4509 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4510 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4511 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4512 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4513 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4515 enum ix86_opt_type
4516 {
4517 ix86_opt_unknown,
4518 ix86_opt_yes,
4519 ix86_opt_no,
4520 ix86_opt_str,
4521 ix86_opt_enum,
4522 ix86_opt_isa
4523 };
4525 static const struct
4526 {
4533 /* isa options */
4579 /* enum options */
4582 /* string options */
4586 /* flag options */
4588 OPT_mcld,
4589 MASK_CLD),
4592 OPT_mfancy_math_387,
4593 MASK_NO_FANCY_MATH_387),
4596 OPT_mieee_fp,
4597 MASK_IEEE_FP),
4600 OPT_minline_all_stringops,
4601 MASK_INLINE_ALL_STRINGOPS),
4604 OPT_minline_stringops_dynamically,
4605 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4608 OPT_mno_align_stringops,
4609 MASK_NO_ALIGN_STRINGOPS),
4612 OPT_mrecip,
4613 MASK_RECIP),
4615 };
4617 /* If this is a list, recurse to get the options. */
4619 {
4626 enum_opts_set))
4630 }
4633 {
4636 }
4638 /* Handle multiple arguments separated by commas. */
4642 {
4656 {
4660 }
4661 else
4662 {
4665 }
4667 /* Recognize no-xxx. */
4669 {
4673 }
4674 else
4677 /* Find the option. */
4681 {
4689 {
4694 }
4695 }
4697 /* Process the option. */
4699 {
4702 }
4705 {
4711 }
4714 {
4720 else
4722 }
4725 {
4727 {
4730 }
4731 else
4733 }
4736 {
4744 global_dc);
4745 else
4746 {
4749 }
4750 }
4752 else
4754 }
4757 }
4759 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4761 tree
4765 {
4780 /* Process each of the options on the chain. */
4785 /* If the changed options are different from the default, rerun
4786 ix86_option_override_internal, and then save the options away.
4787 The string options are are attribute options, and will be undone
4788 when we copy the save structure. */
4794 {
4795 /* If we are using the default tune= or arch=, undo the string assigned,
4796 and use the default. */
4807 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4812 {
4815 }
4817 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4820 /* Add any builtin functions with the new isa if any. */
4823 /* Save the current options unless we are validating options for
4824 #pragma. */
4831 /* Free up memory allocated to hold the strings */
4834 }
4837 }
4839 /* Hook to validate attribute((target("string"))). */
4841 static bool
4844 tree args,
4846 {
4851 /* attribute((target("default"))) does nothing, beyond
4852 affecting multi-versioning. */
4861 /* Get the optimization options of the current function. */
4867 /* Init func_options. */
4875 /* Initialize func_options to the default before its target options can
4876 be set. */
4889 {
4894 }
4897 }
4899 \f
4900 /* Hook to determine if one function can safely inline another. */
4902 static bool
4904 {
4909 /* If callee has no option attributes, then it is ok to inline. */
4913 /* If caller has no option attributes, but callee does then it is not ok to
4914 inline. */
4918 else
4919 {
4923 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4924 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4925 function. */
4930 /* See if we have the same non-isa options. */
4934 /* See if arch, tune, etc. are the same. */
4947 else
4949 }
4952 }
4954 \f
4955 /* Remember the last target of ix86_set_current_function. */
4958 /* Invalidate ix86_previous_fndecl cache. */
4959 void
4961 {
4963 }
4965 /* Establish appropriate back-end context for processing the function
4966 FNDECL. The argument might be NULL to indicate processing at top
4967 level, outside of any function scope. */
4968 static void
4970 {
4971 /* Only change the context if the function changes. This hook is called
4972 several times in the course of compiling a function, and we don't want to
4973 slow things down too much or call target_reinit when it isn't safe. */
4975 {
4976 tree old_tree = (ix86_previous_fndecl
4980 tree new_tree = (fndecl
4986 ;
4989 {
4994 else
4997 }
5000 {
5008 else
5011 }
5012 }
5013 }
5015 \f
5016 /* Return true if this goes in large data/bss. */
5018 static bool
5020 {
5024 /* Functions are never large data. */
5029 {
5035 }
5036 else
5037 {
5040 /* If this is an incomplete type with size 0, then we can't put it
5041 in data because it might be too big when completed. */
5044 }
5047 }
5049 /* Switch to the appropriate section for output of DECL.
5050 DECL is either a `VAR_DECL' node or a constant of some sort.
5051 RELOC indicates whether forming the initial value of DECL requires
5052 link-time relocations. */
5057 {
5060 {
5064 {
5098 /* We don't split these for medium model. Place them into
5099 default sections and hope for best. */
5101 }
5103 {
5104 /* We might get called with string constants, but get_named_section
5105 doesn't like them as they are not DECLs. Also, we need to set
5106 flags in that case. */
5110 }
5111 }
5113 }
5115 /* Select a set of attributes for section NAME based on the properties
5116 of DECL and whether or not RELOC indicates that DECL's initializer
5117 might contain runtime relocations. */
5119 static unsigned int ATTRIBUTE_UNUSED
5121 {
5135 }
5137 /* Build up a unique section name, expressed as a
5138 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5139 RELOC indicates whether the initial value of EXP requires
5140 link-time relocations. */
5142 static void ATTRIBUTE_UNUSED
5144 {
5147 {
5149 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5153 {
5177 /* We don't split these for medium model. Place them into
5178 default sections and hope for best. */
5180 }
5182 {
5189 /* If we're using one_only, then there needs to be a .gnu.linkonce
5190 prefix to the section name. */
5197 }
5198 }
5200 }
5202 #ifdef COMMON_ASM_OP
5203 /* This says how to output assembler code to declare an
5204 uninitialized external linkage data object.
5206 For medium model x86-64 we need to use .largecomm opcode for
5207 large objects. */
5208 void
5212 {
5216 else
5221 }
5222 #endif
5224 /* Utility function for targets to use in implementing
5225 ASM_OUTPUT_ALIGNED_BSS. */
5227 void
5231 {
5235 else
5238 #ifdef ASM_DECLARE_OBJECT_NAME
5241 #else
5242 /* Standard thing is just output label for the object. */
5246 }
5247 \f
5248 /* Decide whether we must probe the stack before any space allocation
5249 on this target. It's essentially TARGET_STACK_PROBE except when
5250 -fstack-check causes the stack to be already probed differently. */
5252 bool
5254 {
5255 /* Do not probe the stack twice if static stack checking is enabled. */
5260 }
5261 \f
5262 /* Decide whether we can make a sibling call to a function. DECL is the
5263 declaration of the function being targeted by the call and EXP is the
5264 CALL_EXPR representing the call. */
5266 static bool
5268 {
5272 /* If we are generating position-independent code, we cannot sibcall
5273 optimize any indirect call, or a direct call to a global function,
5274 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5276 && !TARGET_64BIT
5277 && flag_pic
5281 /* If we need to align the outgoing stack, then sibcalling would
5282 unalign the stack, which may break the called function. */
5288 {
5291 }
5292 else
5293 {
5294 /* We're looking at the CALL_EXPR, we need the type of the function. */
5299 }
5301 /* Check that the return value locations are the same. Like
5302 if we are returning floats on the 80387 register stack, we cannot
5303 make a sibcall from a function that doesn't return a float to a
5304 function that does or, conversely, from a function that does return
5305 a float to a function that doesn't; the necessary stack adjustment
5306 would not be executed. This is also the place we notice
5307 differences in the return value ABI. Note that it is ok for one
5308 of the functions to have void return type as long as the return
5309 value of the other is passed in a register. */
5314 {
5317 }
5319 ;
5324 {
5325 /* The SYSV ABI has more call-clobbered registers;
5326 disallow sibcalls from MS to SYSV. */
5330 }
5331 else
5332 {
5333 /* If this call is indirect, we'll need to be able to use a
5334 call-clobbered register for the address of the target function.
5335 Make sure that all such registers are not used for passing
5336 parameters. Note that DLLIMPORT functions are indirect. */
5339 {
5341 {
5342 /* ??? Need to count the actual number of registers to be used,
5343 not the possible number of registers. Fix later. */
5345 }
5346 }
5347 }
5349 /* Otherwise okay. That also includes certain types of indirect calls. */
5351 }
5353 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5354 and "sseregparm" calling convention attributes;
5355 arguments as in struct attribute_spec.handler. */
5357 static tree
5359 tree args,
5362 {
5367 {
5369 name);
5372 }
5374 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5376 {
5377 tree cst;
5380 {
5382 }
5385 {
5387 }
5391 {
5394 name);
5396 }
5398 {
5402 }
5405 }
5408 {
5409 /* Do not warn when emulating the MS ABI. */
5414 name);
5417 }
5419 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5421 {
5423 {
5425 }
5427 {
5429 }
5431 {
5433 }
5435 {
5437 }
5438 }
5440 /* Can combine stdcall with fastcall (redundant), regparm and
5441 sseregparm. */
5443 {
5445 {
5447 }
5449 {
5451 }
5453 {
5455 }
5456 }
5458 /* Can combine cdecl with regparm and sseregparm. */
5460 {
5462 {
5464 }
5466 {
5468 }
5470 {
5472 }
5473 }
5475 {
5478 name);
5480 {
5482 }
5484 {
5486 }
5488 {
5490 }
5491 }
5493 /* Can combine sseregparm with all attributes. */
5496 }
5498 /* The transactional memory builtins are implicitly regparm or fastcall
5499 depending on the ABI. Override the generic do-nothing attribute that
5500 these builtins were declared with, and replace it with one of the two
5501 attributes that we expect elsewhere. */
5503 static tree
5505 tree args ATTRIBUTE_UNUSED,
5507 {
5508 tree alt;
5510 /* In no case do we want to add the placeholder attribute. */
5513 /* The 64-bit ABI is unchanged for transactional memory. */
5517 /* ??? Is there a better way to validate 32-bit windows? We have
5518 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5521 else
5522 {
5525 }
5529 }
5531 /* This function determines from TYPE the calling-convention. */
5533 unsigned int
5535 {
5538 tree attrs;
5545 {
5555 /* Regparam isn't allowed for thiscall and fastcall. */
5557 {
5562 }
5566 }
5573 || is_stdarg
5579 }
5581 /* Return 0 if the attributes for two types are incompatible, 1 if they
5582 are compatible, and 2 if they are nearly compatible (which causes a
5583 warning to be generated). */
5585 static int
5587 {
5603 }
5604 \f
5605 /* Return the regparm value for a function with the indicated TYPE and DECL.
5606 DECL may be NULL when calling function indirectly
5607 or considering a libcall. */
5609 static int
5611 {
5612 tree attr;
5623 {
5626 {
5629 }
5630 }
5636 /* Use register calling convention for local functions when possible. */
5639 /* Caller and callee must agree on the calling convention, so
5640 checking here just optimize means that with
5641 __attribute__((optimize (...))) caller could use regparm convention
5642 and callee not, or vice versa. Instead look at whether the callee
5643 is optimized or not. */
5646 {
5647 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5650 {
5653 /* Make sure no regparm register is taken by a
5654 fixed register variable. */
5659 /* We don't want to use regparm(3) for nested functions as
5660 these use a static chain pointer in the third argument. */
5664 /* In 32-bit mode save a register for the split stack. */
5668 /* Each fixed register usage increases register pressure,
5669 so less registers should be used for argument passing.
5670 This functionality can be overriden by an explicit
5671 regparm value. */
5674 globals++;
5676 local_regparm
5681 }
5682 }
5685 }
5687 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5688 DFmode (2) arguments in SSE registers for a function with the
5689 indicated TYPE and DECL. DECL may be NULL when calling function
5690 indirectly or considering a libcall. Otherwise return 0. */
5692 static int
5694 {
5697 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5698 by the sseregparm attribute. */
5701 {
5703 {
5705 {
5709 else
5712 }
5714 }
5717 }
5719 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5720 (and DFmode for SSE2) arguments in SSE registers. */
5723 {
5724 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5728 }
5731 }
5733 /* Return true if EAX is live at the start of the function. Used by
5734 ix86_expand_prologue to determine if we need special help before
5735 calling allocate_stack_worker. */
5737 static bool
5739 {
5740 /* Cheat. Don't bother working forward from ix86_function_regparm
5741 to the function type to whether an actual argument is located in
5742 eax. Instead just look at cfg info, which is still close enough
5743 to correct at this point. This gives false positives for broken
5744 functions that might use uninitialized data that happens to be
5745 allocated in eax, but who cares? */
5747 }
5749 static bool
5751 {
5752 tree attr;
5755 {
5761 /* For 32-bit MS-ABI the default is to keep aggregate
5762 return pointer. */
5765 }
5767 }
5769 /* Value is the number of bytes of arguments automatically
5770 popped when returning from a subroutine call.
5771 FUNDECL is the declaration node of the function (as a tree),
5772 FUNTYPE is the data type of the function (as a tree),
5773 or for a library call it is an identifier node for the subroutine name.
5774 SIZE is the number of bytes of arguments passed on the stack.
5776 On the 80386, the RTD insn may be used to pop them if the number
5777 of args is fixed, but if the number is variable then the caller
5778 must pop them all. RTD can't be used for library calls now
5779 because the library is compiled with the Unix compiler.
5780 Use of RTD is a selectable option, since it is incompatible with
5781 standard Unix calling sequences. If the option is not selected,
5782 the caller must always pop the args.
5784 The attribute stdcall is equivalent to RTD on a per module basis. */
5786 static int
5788 {
5791 /* None of the 64-bit ABIs pop arguments. */
5802 /* Lose any fake structure return argument if it is passed on the stack. */
5805 {
5809 }
5812 }
5814 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5816 static bool
5818 {
5819 /* Check operand constraints in case hard registers were propagated
5820 into insn pattern. This check prevents combine pass from
5821 generating insn patterns with invalid hard register operands.
5822 These invalid insns can eventually confuse reload to error out
5823 with a spill failure. See also PRs 46829 and 46843. */
5825 {
5832 {
5840 /* For pre-AVX disallow unaligned loads/stores where the
5841 instructions don't support it. */
5845 {
5849 }
5851 /* A unary operator may be accepted by the predicate, but it
5852 is irrelevant for matching constraints. */
5857 {
5865 }
5872 /* Operand has no constraints, anything is OK. */
5876 {
5879 && operands_match_p
5883 {
5886 }
5887 }
5891 }
5892 }
5895 }
5896 \f
5897 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5899 static unsigned HOST_WIDE_INT
5901 {
5905 }
5906 \f
5907 /* Argument support functions. */
5909 /* Return true when register may be used to pass function parameters. */
5910 bool
5912 {
5917 {
5921 else
5927 }
5933 /* TODO: The function should depend on current function ABI but
5934 builtins.c would need updating then. Therefore we use the
5935 default ABI. */
5937 /* RAX is used as hidden argument to va_arg functions. */
5943 else
5950 }
5952 /* Return if we do not know how to pass TYPE solely in registers. */
5954 static bool
5956 {
5960 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5961 The layout_type routine is crafty and tries to trick us into passing
5962 currently unsupported vector types on the stack by using TImode. */
5965 }
5967 /* It returns the size, in bytes, of the area reserved for arguments passed
5968 in registers for the function represented by fndecl dependent to the used
5969 abi format. */
5970 int
5972 {
5976 else
5981 }
5983 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5984 call abi used. */
5985 enum calling_abi
5987 {
5989 {
5992 {
5995 }
5999 }
6001 }
6003 /* We add this as a workaround in order to use libc_has_function
6004 hook in i386.md. */
6005 bool
6007 {
6009 }
6011 static bool
6013 {
6015 {
6019 else
6021 }
6023 }
6025 static enum calling_abi
6027 {
6031 }
6033 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6034 call abi used. */
6035 enum calling_abi
6037 {
6041 }
6043 /* Write the extra assembler code needed to declare a function properly. */
6045 void
6047 tree decl)
6048 {
6052 {
6058 }
6060 #ifdef SUBTARGET_ASM_UNWIND_INIT
6062 #endif
6066 /* Output magic byte marker, if hot-patch attribute is set. */
6068 {
6070 {
6071 /* leaq [%rsp + 0], %rsp */
6074 }
6075 else
6076 {
6077 /* movl.s %edi, %edi
6078 push %ebp
6079 movl.s %esp, %ebp */
6082 }
6083 }
6084 }
6086 /* regclass.c */
6089 /* Implementation of call abi switching target hook. Specific to FNDECL
6090 the specific call register sets are set. See also
6091 ix86_conditional_register_usage for more details. */
6092 void
6094 {
6097 else
6099 }
6101 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6102 expensive re-initialization of init_regs each time we switch function context
6103 since this is needed only during RTL expansion. */
6104 static void
6106 {
6110 }
6112 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6113 for a call to a function whose data type is FNTYPE.
6114 For a library call, FNTYPE is 0. */
6116 void
6120 tree fndecl,
6122 {
6128 {
6131 }
6132 else
6133 {
6136 }
6140 /* Set up the number of registers to use for passing arguments. */
6143 {
6145 ? X86_64_REGPARM_MAX
6147 }
6149 {
6152 {
6154 ? X86_64_SSE_REGPARM_MAX
6156 }
6157 }
6165 /* Because type might mismatch in between caller and callee, we need to
6166 use actual type of function for local calls.
6167 FIXME: cgraph_analyze can be told to actually record if function uses
6168 va_start so for local functions maybe_vaarg can be made aggressive
6169 helping K&R code.
6170 FIXME: once typesytem is fixed, we won't need this code anymore. */
6178 {
6179 /* If there are variable arguments, then we won't pass anything
6180 in registers in 32-bit mode. */
6182 {
6191 }
6193 /* Use ecx and edx registers if function has fastcall attribute,
6194 else look for regparm information. */
6196 {
6199 {
6202 }
6204 {
6207 }
6208 else
6210 }
6212 /* Set up the number of SSE registers used for passing SFmode
6213 and DFmode arguments. Warn for mismatching ABI. */
6215 }
6216 }
6218 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6219 But in the case of vector types, it is some vector mode.
6221 When we have only some of our vector isa extensions enabled, then there
6222 are some modes for which vector_mode_supported_p is false. For these
6223 modes, the generic vector support in gcc will choose some non-vector mode
6224 in order to implement the type. By computing the natural mode, we'll
6225 select the proper ABI location for the operand and not depend on whatever
6226 the middle-end decides to do with these vector types.
6228 The midde-end can't deal with the vector types > 16 bytes. In this
6229 case, we return the original mode and warn ABI change if CUM isn't
6230 NULL.
6232 If INT_RETURN is true, warn ABI change if the vector mode isn't
6233 available for function return value. */
6235 static enum machine_mode
6238 {
6242 {
6245 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6247 {
6252 else
6255 /* Get the mode which has this inner mode and number of units. */
6259 {
6261 {
6266 {
6270 }
6272 {
6276 }
6279 }
6281 {
6286 {
6290 }
6292 {
6296 }
6299 }
6302 {
6307 {
6311 }
6313 {
6317 }
6318 }
6320 {
6325 {
6329 }
6331 {
6335 }
6336 }
6338 }
6341 }
6342 }
6345 }
6347 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6348 this may not agree with the mode that the type system has chosen for the
6349 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6350 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6352 static rtx
6355 {
6356 rtx tmp;
6360 else
6361 {
6365 }
6368 }
6370 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6371 of this code is to classify each 8bytes of incoming argument by the register
6372 class and assign registers accordingly. */
6374 /* Return the union class of CLASS1 and CLASS2.
6375 See the x86-64 PS ABI for details. */
6377 static enum x86_64_reg_class
6379 {
6380 /* Rule #1: If both classes are equal, this is the resulting class. */
6384 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6385 the other class. */
6391 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6395 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6403 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6404 MEMORY is used. */
6413 /* Rule #6: Otherwise class SSE is used. */
6415 }
6417 /* Classify the argument of type TYPE and mode MODE.
6418 CLASSES will be filled by the register class used to pass each word
6419 of the operand. The number of words is returned. In case the parameter
6420 should be passed in memory, 0 is returned. As a special case for zero
6421 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6423 BIT_OFFSET is used internally for handling records and specifies offset
6424 of the offset in bits modulo 512 to avoid overflow cases.
6426 See the x86-64 PS ABI for details.
6427 */
6429 static int
6432 {
6433 HOST_WIDE_INT bytes =
6435 int words
6438 /* Variable sized entities are always passed/returned in memory. */
6447 {
6449 tree field;
6452 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6459 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6460 signalize memory class, so handle it as special case. */
6462 {
6465 }
6467 /* Classify each field of record and merge classes. */
6469 {
6471 /* And now merge the fields of structure. */
6473 {
6475 {
6481 /* Bitfields are always classified as integer. Handle them
6482 early, since later code would consider them to be
6483 misaligned integers. */
6485 {
6494 }
6495 else
6496 {
6501 /* Flexible array member is ignored. */
6508 {
6512 {
6515 "the ABI of passing struct with"
6516 " a flexible array member has"
6518 }
6520 }
6522 subclasses,
6532 }
6533 }
6534 }
6538 /* Arrays are handled as small records. */
6539 {
6546 /* The partial classes are now full classes. */
6557 }
6560 /* Unions are similar to RECORD_TYPE but offset is always 0.
6561 */
6563 {
6565 {
6573 bit_offset);
6578 }
6579 }
6584 }
6587 {
6588 /* When size > 16 bytes, if the first one isn't
6589 X86_64_SSE_CLASS or any other ones aren't
6590 X86_64_SSEUP_CLASS, everything should be passed in
6591 memory. */
6598 }
6600 /* Final merger cleanup. */
6602 {
6603 /* If one class is MEMORY, everything should be passed in
6604 memory. */
6608 /* The X86_64_SSEUP_CLASS should be always preceded by
6609 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6613 {
6614 /* The first one should never be X86_64_SSEUP_CLASS. */
6617 }
6619 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6620 everything should be passed in memory. */
6623 {
6626 /* The first one should never be X86_64_X87UP_CLASS. */
6629 {
6632 "the ABI of passing union with long double"
6634 }
6636 }
6637 }
6639 }
6641 /* Compute alignment needed. We align all types to natural boundaries with
6642 exception of XFmode that is aligned to 64bits. */
6644 {
6653 /* Misaligned fields are always returned in memory. */
6656 }
6658 /* for V1xx modes, just use the base mode */
6663 /* Classification of atomic types. */
6665 {
6681 {
6684 /* Analyze last 128 bits only. */
6688 {
6691 }
6693 {
6696 }
6698 {
6702 }
6704 {
6707 }
6708 else
6710 }
6717 /* OImode shouldn't be used directly. */
6724 else
6742 else
6743 {
6747 {
6750 "the ABI of passing structure with complex float"
6752 }
6755 }
6764 /* This modes is larger than 16 bytes. */
6822 else
6826 }
6827 }
6829 /* Examine the argument and return set number of register required in each
6830 class. Return true iff parameter should be passed in memory. */
6832 static bool
6835 {
6846 {
6867 }
6870 }
6872 /* Construct container for the argument used by GCC interface. See
6873 FUNCTION_ARG for the detailed description. */
6875 static rtx
6879 {
6880 /* The following variables hold the static issued_error state. */
6894 rtx ret;
6905 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6906 some less clueful developer tries to use floating-point anyway. */
6908 {
6910 {
6912 {
6915 }
6916 }
6918 {
6921 }
6923 }
6925 /* Likewise, error if the ABI requires us to return values in the
6926 x87 registers and the user specified -mno-80387. */
6932 {
6934 {
6937 }
6939 }
6941 /* First construct simple cases. Avoid SCmode, since we want to use
6942 single register to pass this type. */
6945 {
6960 /* Zero sized array, struct or class. */
6964 }
7003 /* Otherwise figure out the entries of the PARALLEL. */
7005 {
7009 {
7014 /* Merge TImodes on aligned occasions here too. */
7016 tmpmode
7020 else
7022 /* We've requested 24 bytes we
7023 don't have mode for. Use DImode. */
7030 intreg++;
7038 sse_regno++;
7046 sse_regno++;
7051 {
7057 {
7059 i++;
7060 }
7061 else
7086 }
7092 sse_regno++;
7096 }
7097 }
7099 /* Empty aligned struct, union or class. */
7107 }
7109 /* Update the data in CUM to advance over an argument of mode MODE
7110 and data type TYPE. (TYPE is null for libcalls where that information
7111 may not be available.) */
7113 static void
7116 HOST_WIDE_INT words)
7117 {
7119 {
7126 /* FALLTHRU */
7137 {
7140 }
7144 /* OImode shouldn't be used directly. */
7153 /* FALLTHRU */
7175 {
7180 {
7183 }
7184 }
7194 {
7199 {
7202 }
7203 }
7205 }
7206 }
7208 static void
7211 {
7214 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7221 {
7226 }
7227 else
7228 {
7232 }
7233 }
7235 static void
7237 HOST_WIDE_INT words)
7238 {
7239 /* Otherwise, this should be passed indirect. */
7244 {
7247 }
7248 }
7250 /* Update the data in CUM to advance over an argument of mode MODE and
7251 data type TYPE. (TYPE is null for libcalls where that information
7252 may not be available.) */
7254 static void
7257 {
7263 else
7274 else
7276 }
7278 /* Define where to put the arguments to a function.
7279 Value is zero to push the argument on the stack,
7280 or a hard register in which to store the argument.
7282 MODE is the argument's machine mode.
7283 TYPE is the data type of the argument (as a tree).
7284 This is null for libcalls where that information may
7285 not be available.
7286 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7287 the preceding args and about the function being called.
7288 NAMED is nonzero if this argument is a named parameter
7289 (otherwise it is an extra parameter matching an ellipsis). */
7291 static rtx
7295 {
7296 /* Avoid the AL settings for the Unix64 ABI. */
7301 {
7308 /* FALLTHRU */
7314 {
7317 /* Fastcall allocates the first two DWORD (SImode) or
7318 smaller arguments to ECX and EDX if it isn't an
7319 aggregate type . */
7321 {
7327 /* ECX not EAX is the first allocated register. */
7330 }
7332 }
7341 /* FALLTHRU */
7343 /* In 32bit, we pass TImode in xmm registers. */
7351 {
7355 }
7360 /* OImode and XImode shouldn't be used directly. */
7376 {
7380 }
7390 {
7394 }
7396 }
7399 }
7401 static rtx
7404 {
7405 /* Handle a hidden AL argument containing number of registers
7406 for varargs x86-64 functions. */
7410 ? X86_64_SSE_REGPARM_MAX
7415 {
7431 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7435 }
7441 }
7443 static rtx
7446 HOST_WIDE_INT bytes)
7447 {
7450 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7451 We use value of -2 to specify that current function call is MSABI. */
7455 /* If we've run out of registers, it goes on the stack. */
7461 /* Only floating point modes are passed in anything but integer regs. */
7463 {
7466 else
7467 {
7470 /* Unnamed floating parameters are passed in both the
7471 SSE and integer registers. */
7477 }
7478 }
7479 /* Handle aggregated types passed in register. */
7481 {
7486 }
7489 }
7491 /* Return where to put the arguments to a function.
7492 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7494 MODE is the argument's machine mode. TYPE is the data type of the
7495 argument. It is null for libcalls where that information may not be
7496 available. CUM gives information about the preceding args and about
7497 the function being called. NAMED is nonzero if this argument is a
7498 named parameter (otherwise it is an extra parameter matching an
7499 ellipsis). */
7501 static rtx
7504 {
7508 rtx arg;
7512 else
7516 /* To simplify the code below, represent vector types with a vector mode
7517 even if MMX/SSE are not active. */
7525 else
7529 }
7531 /* A C expression that indicates when an argument must be passed by
7532 reference. If nonzero for an argument, a copy of that argument is
7533 made in memory and a pointer to the argument is passed instead of
7534 the argument itself. The pointer is passed in whatever way is
7535 appropriate for passing a pointer to that type. */
7537 static bool
7540 {
7543 /* See Windows x64 Software Convention. */
7545 {
7548 {
7549 /* Arrays are passed by reference. */
7554 {
7555 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7556 are passed by reference. */
7558 }
7559 }
7561 /* __m128 is passed by reference. */
7567 }
7568 }
7573 }
7575 /* Return true when TYPE should be 128bit aligned for 32bit argument
7576 passing ABI. XXX: This function is obsolete and is only used for
7577 checking psABI compatibility with previous versions of GCC. */
7579 static bool
7581 {
7593 {
7594 /* Walk the aggregates recursively. */
7596 {
7600 {
7601 tree field;
7603 /* Walk all the structure fields. */
7605 {
7609 }
7611 }
7614 /* Just for use if some languages passes arrays by value. */
7621 }
7622 }
7624 }
7626 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7627 XXX: This function is obsolete and is only used for checking psABI
7628 compatibility with previous versions of GCC. */
7630 static unsigned int
7633 {
7634 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7635 natural boundaries. */
7637 {
7638 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7639 make an exception for SSE modes since these require 128bit
7640 alignment.
7642 The handling here differs from field_alignment. ICC aligns MMX
7643 arguments to 4 byte boundaries, while structure fields are aligned
7644 to 8 byte boundaries. */
7646 {
7649 }
7650 else
7651 {
7654 }
7655 }
7659 }
7661 /* Return true when TYPE should be 128bit aligned for 32bit argument
7662 passing ABI. */
7664 static bool
7666 {
7676 {
7677 /* Walk the aggregates recursively. */
7679 {
7683 {
7684 tree field;
7686 /* Walk all the structure fields. */
7688 field;
7690 {
7694 }
7696 }
7699 /* Just for use if some languages passes arrays by value. */
7706 }
7707 }
7708 else
7712 }
7714 /* Gives the alignment boundary, in bits, of an argument with the
7715 specified mode and type. */
7717 static unsigned int
7719 {
7722 {
7723 /* Since the main variant type is used for call, we convert it to
7724 the main variant type. */
7727 }
7728 else
7732 else
7733 {
7738 {
7739 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7741 {
7744 }
7750 }
7753 && !warned
7755 saved_align))
7756 {
7759 "The ABI for passing parameters with %d-byte"
7762 }
7763 }
7766 }
7768 /* Return true if N is a possible register number of function value. */
7770 static bool
7772 {
7774 {
7782 /* Complex values are returned in %st(0)/%st(1) pair. */
7785 /* TODO: The function should depend on current function ABI but
7786 builtins.c would need updating then. Therefore we use the
7787 default ABI. */
7792 /* Complex values are returned in %xmm0/%xmm1 pair. */
7801 }
7804 }
7806 /* Define how to find the value returned by a function.
7807 VALTYPE is the data type of the value (as a tree).
7808 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7809 otherwise, FUNC is 0. */
7811 static rtx
7814 {
7817 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7818 we normally prevent this case when mmx is not available. However
7819 some ABIs may require the result to be returned like DImode. */
7823 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7824 we prevent this case when sse is not available. However some ABIs
7825 may require the result to be returned like integer TImode. */
7830 /* 32-byte vector modes in %ymm0. */
7834 /* 64-byte vector modes in %zmm0. */
7838 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7841 else
7842 /* Most things go in %eax. */
7845 /* Override FP return register with %xmm0 for local functions when
7846 SSE math is enabled or for functions with sseregparm attribute. */
7848 {
7853 }
7855 /* OImode shouldn't be used directly. */
7859 }
7861 static rtx
7863 const_tree valtype)
7864 {
7865 rtx ret;
7867 /* Handle libcalls, which don't provide a type node. */
7869 {
7873 {
7892 }
7895 }
7897 {
7898 /* Pointers are always returned in word_mode. */
7900 }
7906 /* For zero sized structures, construct_container returns NULL, but we
7907 need to keep rest of compiler happy by returning meaningful value. */
7912 }
7914 static rtx
7916 const_tree valtype)
7917 {
7921 {
7923 {
7942 }
7943 }
7945 }
7947 static rtx
7950 {
7962 else
7964 }
7966 static rtx
7969 {
7975 }
7977 /* Pointer function arguments and return values are promoted to
7978 word_mode. */
7980 static enum machine_mode
7984 {
7986 {
7989 }
7991 for_return);
7992 }
7994 /* Return true if a structure, union or array with MODE containing FIELD
7995 should be accessed using BLKmode. */
7997 static bool
7999 {
8000 /* Union with XFmode must be in BLKmode. */
8004 }
8006 rtx
8008 {
8010 }
8012 /* Return true iff type is returned in memory. */
8014 static bool
8016 {
8017 #ifdef SUBTARGET_RETURN_IN_MEMORY
8019 #else
8021 HOST_WIDE_INT size;
8024 {
8026 {
8029 /* __m128 is returned in xmm0. */
8038 /* Otherwise, the size must be exactly in [1248]. */
8040 }
8041 else
8042 {
8047 }
8048 }
8049 else
8050 {
8060 {
8061 /* User-created vectors small enough to fit in EAX. */
8065 /* Unless ABI prescibes otherwise,
8066 MMX/3dNow values are returned in MM0 if available. */
8071 /* SSE values are returned in XMM0 if available. */
8075 /* AVX values are returned in YMM0 if available. */
8079 /* AVX512F values are returned in ZMM0 if available. */
8082 }
8090 /* OImode shouldn't be used directly. */
8094 }
8095 #endif
8096 }
8098 \f
8099 /* Create the va_list data type. */
8101 /* Returns the calling convention specific va_list date type.
8102 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8104 static tree
8106 {
8109 /* For i386 we use plain pointer to argument area. */
8119 unsigned_type_node);
8122 unsigned_type_node);
8125 ptr_type_node);
8128 ptr_type_node);
8147 /* The correct type is an array type of one element. */
8149 }
8151 /* Setup the builtin va_list data type and for 64-bit the additional
8152 calling convention specific va_list data types. */
8154 static tree
8156 {
8159 /* Initialize abi specific va_list builtin types. */
8161 {
8162 tree t;
8164 {
8169 }
8170 else
8171 {
8176 }
8178 {
8183 }
8184 else
8185 {
8190 }
8191 }
8194 }
8196 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8198 static void
8200 {
8202 alias_set_type set;
8205 /* GPR size of varargs save area. */
8208 else
8211 /* FPR size of varargs save area. We don't need it if we don't pass
8212 anything in SSE registers. */
8215 else
8229 {
8237 }
8240 {
8244 /* Now emit code to save SSE registers. The AX parameter contains number
8245 of SSE parameter registers used to call this function, though all we
8246 actually check here is the zero/non-zero status. */
8251 label));
8253 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8254 we used movdqa (i.e. TImode) instead? Perhaps even better would
8255 be if we could determine the real mode of the data, via a hook
8256 into pass_stdarg. Ignore all that for now. */
8266 {
8275 }
8278 }
8279 }
8281 static void
8283 {
8287 /* Reset to zero, as there might be a sysv vaarg used
8288 before. */
8293 {
8304 }
8305 }
8307 static void
8311 {
8313 CUMULATIVE_ARGS next_cum;
8314 tree fntype;
8316 /* This argument doesn't appear to be used anymore. Which is good,
8317 because the old code here didn't suppress rtl generation. */
8325 /* For varargs, we do not want to skip the dummy va_dcl argument.
8326 For stdargs, we do want to skip the last named argument. */
8334 else
8336 }
8338 /* Checks if TYPE is of kind va_list char *. */
8340 static bool
8342 {
8343 tree canonic;
8345 /* For 32-bit it is always true. */
8351 }
8353 /* Implement va_start. */
8355 static void
8357 {
8361 tree type;
8362 rtx ovf_rtx;
8366 {
8369 /* When we are splitting the stack, we can't refer to the stack
8370 arguments using internal_arg_pointer, because they may be on
8371 the old stack. The split stack prologue will arrange to
8372 leave a pointer to the old stack arguments in a scratch
8373 register, which we here copy to a pseudo-register. The split
8374 stack prologue can't set the pseudo-register directly because
8375 it (the prologue) runs before any registers have been saved. */
8379 {
8393 }
8394 }
8396 /* Only 64bit target needs something special. */
8398 {
8401 else
8402 {
8411 }
8413 }
8422 /* The following should be folded into the MEM_REF offset. */
8432 /* Count number of gp and fp argument registers used. */
8438 {
8444 }
8447 {
8453 }
8455 /* Find the overflow area. */
8459 else
8469 {
8470 /* Find the register save area.
8471 Prologue of the function save it right above stack frame. */
8479 }
8480 }
8482 /* Implement va_arg. */
8484 static tree
8487 {
8494 rtx container;
8496 tree ptrtype;
8500 /* Only 64bit target needs something special. */
8524 {
8537 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8539 {
8542 }
8550 }
8552 /* Pull the value out of the saved registers. */
8557 {
8571 /* In case we are passing structure, verify that it is consecutive block
8572 on the register save area. If not we need to do moves. */
8574 {
8575 /* Verify that all registers are strictly consecutive */
8577 {
8581 {
8586 }
8587 }
8588 else
8589 {
8593 {
8598 }
8599 }
8600 }
8602 {
8605 }
8606 else
8607 {
8610 }
8612 /* First ensure that we fit completely in registers. */
8614 {
8621 }
8623 {
8631 }
8633 /* Compute index to start of area used for integer regs. */
8635 {
8636 /* int_addr = gpr + sav; */
8639 }
8641 {
8642 /* sse_addr = fpr + sav; */
8645 }
8647 {
8651 /* addr = &temp; */
8656 {
8660 tree piece_type;
8661 tree addr_type;
8662 tree daddr_type;
8671 {
8676 }
8680 else
8687 {
8690 }
8691 else
8692 {
8695 }
8702 {
8707 }
8708 else
8709 {
8710 tree copy
8715 }
8717 }
8718 }
8721 {
8725 }
8728 {
8732 }
8737 }
8739 /* ... otherwise out of the overflow area. */
8741 /* When we align parameter on stack for caller, if the parameter
8742 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8743 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8744 here with caller. */
8749 /* Care for on-stack alignment if needed. */
8752 else
8753 {
8758 }
8775 }
8776 \f
8777 /* Return true if OPNUM's MEM should be matched
8778 in movabs* patterns. */
8780 bool
8782 {
8794 }
8795 \f
8796 /* Initialize the table of extra 80387 mathematical constants. */
8798 static void
8800 {
8802 {
8808 };
8812 {
8814 /* Ensure each constant is rounded to XFmode precision. */
8817 }
8820 }
8822 /* Return non-zero if the constant is something that
8823 can be loaded with a special instruction. */
8825 int
8827 {
8830 REAL_VALUE_TYPE r;
8842 /* For XFmode constants, try to find a special 80387 instruction when
8843 optimizing for size or on those CPUs that benefit from them. */
8846 {
8855 }
8857 /* Load of the constant -0.0 or -1.0 will be split as
8858 fldz;fchs or fld1;fchs sequence. */
8865 }
8867 /* Return the opcode of the special instruction to be used to load
8868 the constant X. */
8872 {
8874 {
8894 }
8895 }
8897 /* Return the CONST_DOUBLE representing the 80387 constant that is
8898 loaded by the specified special instruction. The argument IDX
8899 matches the return value from standard_80387_constant_p. */
8901 rtx
8903 {
8910 {
8921 }
8924 XFmode);
8925 }
8927 /* Return 1 if X is all 0s and 2 if x is all 1s
8928 in supported SSE/AVX vector mode. */
8930 int
8932 {
8939 {
8960 }
8963 }
8965 /* Return the opcode of the special instruction to be used to load
8966 the constant X. */
8970 {
8972 {
8975 {
8997 }
9006 else
9011 }
9013 }
9015 /* Returns true if OP contains a symbol reference */
9017 bool
9019 {
9028 {
9030 {
9036 }
9040 }
9043 }
9045 /* Return true if it is appropriate to emit `ret' instructions in the
9046 body of a function. Do this only if the epilogue is simple, needing a
9047 couple of insns. Prior to reloading, we can't tell how many registers
9048 must be saved, so return false then. Return false if there is no frame
9049 marker to de-allocate. */
9051 bool
9053 {
9059 /* Don't allow more than 32k pop, since that's all we can do
9060 with one instruction. */
9067 }
9068 \f
9069 /* Value should be nonzero if functions must have frame pointers.
9070 Zero means the frame pointer need not be set up (and parms may
9071 be accessed via the stack pointer) in functions that seem suitable. */
9073 static bool
9075 {
9076 /* If we accessed previous frames, then the generated code expects
9077 to be able to access the saved ebp value in our frame. */
9081 /* Several x86 os'es need a frame pointer for other reasons,
9082 usually pertaining to setjmp. */
9086 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9090 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9091 allocation is 4GB. */
9095 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9096 turns off the frame pointer by default. Turn it back on now if
9097 we've not got a leaf function. */
9107 }
9109 /* Record that the current function accesses previous call frames. */
9111 void
9113 {
9115 }
9116 \f
9117 #ifndef USE_HIDDEN_LINKONCE
9118 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9119 # define USE_HIDDEN_LINKONCE 1
9120 # else
9121 # define USE_HIDDEN_LINKONCE 0
9122 # endif
9123 #endif
9127 /* Fills in the label name that should be used for a pc thunk for
9128 the given register. */
9130 static void
9132 {
9137 else
9139 }
9142 /* This function generates code for -fpic that loads %ebx with
9143 the return address of the caller and then returns. */
9145 static void
9147 {
9152 {
9154 tree decl;
9170 #if TARGET_MACHO
9172 {
9181 }
9182 else
9183 #endif
9185 {
9196 }
9197 else
9198 {
9201 }
9207 /* Make sure unwind info is emitted for the thunk if needed. */
9210 /* Pad stack IP move with 4 instructions (two NOPs count
9211 as one instruction). */
9213 {
9218 }
9229 }
9233 }
9235 /* Emit code for the SET_GOT patterns. */
9239 {
9245 {
9246 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9251 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9252 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9253 an unadorned address. */
9258 }
9263 {
9265 /* We don't need a pic base, we're not producing pic. */
9272 }
9273 else
9274 {
9283 #if TARGET_MACHO
9284 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9285 This is what will be referenced by the Mach-O PIC subsystem. */
9289 /* When we are restoring the pic base at the site of a nonlocal label,
9290 and we decided to emit the pic base above, we will still output a
9291 local label used for calculating the correction offset (even though
9292 the offset will be 0 in that case). */
9296 #endif
9297 }
9303 }
9305 /* Generate an "push" pattern for input ARG. */
9307 static rtx
9309 {
9322 stack_pointer_rtx)),
9323 arg);
9324 }
9326 /* Generate an "pop" pattern for input ARG. */
9328 static rtx
9330 {
9335 arg,
9338 stack_pointer_rtx)));
9339 }
9341 /* Return >= 0 if there is an unused call-clobbered register available
9342 for the entire function. */
9344 static unsigned int
9346 {
9350 {
9352 /* Can't use the same register for both PIC and DRAP. */
9355 else
9360 }
9363 }
9365 /* Return TRUE if we need to save REGNO. */
9367 static bool
9369 {
9380 {
9383 {
9389 }
9390 }
9401 }
9403 /* Return number of saved general prupose registers. */
9405 static int
9407 {
9413 nregs ++;
9415 }
9417 /* Return number of saved SSE registrers. */
9419 static int
9421 {
9429 nregs ++;
9431 }
9433 /* Given FROM and TO register numbers, say whether this elimination is
9434 allowed. If stack alignment is needed, we can only replace argument
9435 pointer with hard frame pointer, or replace frame pointer with stack
9436 pointer. Otherwise, frame pointer elimination is automatically
9437 handled and all other eliminations are valid. */
9439 static bool
9441 {
9447 else
9449 }
9451 /* Return the offset between two registers, one to be eliminated, and the other
9452 its replacement, at the start of a routine. */
9454 HOST_WIDE_INT
9456 {
9465 else
9466 {
9474 }
9475 }
9477 /* In a dynamically-aligned function, we can't know the offset from
9478 stack pointer to frame pointer, so we must ensure that setjmp
9479 eliminates fp against the hard fp (%ebp) rather than trying to
9480 index from %esp up to the top of the frame across a gap that is
9481 of unknown (at compile-time) size. */
9482 static rtx
9484 {
9486 }
9488 /* When using -fsplit-stack, the allocation routines set a field in
9489 the TCB to the bottom of the stack plus this much space, measured
9490 in bytes. */
9492 #define SPLIT_STACK_AVAILABLE 256
9494 /* Fill structure ix86_frame about frame of currently computed function. */
9496 static void
9498 {
9500 HOST_WIDE_INT offset;
9503 HOST_WIDE_INT to_allocate;
9508 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9509 function prologues and leaf. */
9513 {
9516 }
9517 /* preferred_stack_boundary is never updated for call
9518 expanded from tls descriptor. Update it here. We don't update it in
9519 expand stage because according to the comments before
9520 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9521 away. */
9524 {
9528 }
9537 /* For SEH we have to limit the amount of code movement into the prologue.
9538 At present we do this via a BLOCKAGE, at which point there's very little
9539 scheduling that can be done, which means that there's very little point
9540 in doing anything except PUSHs. */
9544 /* During reload iteration the amount of registers saved can change.
9545 Recompute the value as needed. Do not recompute when amount of registers
9546 didn't change as reload does multiple calls to the function and does not
9547 expect the decision to change within single iteration. */
9550 {
9556 /* The fast prologue uses move instead of push to save registers. This
9557 is significantly longer, but also executes faster as modern hardware
9558 can execute the moves in parallel, but can't do that for push/pop.
9560 Be careful about choosing what prologue to emit: When function takes
9561 many instructions to execute we may use slow version as well as in
9562 case function is known to be outside hot spot (this is known with
9563 feedback only). Weight the size of function by number of registers
9564 to save as it is cheap to use one or two push instructions but very
9565 slow to use many of them. */
9569 || (flag_branch_probabilities
9572 else
9575 }
9577 frame->save_regs_using_mov
9579 /* If static stack checking is enabled and done with probes,
9580 the registers need to be saved before allocating the frame. */
9583 /* Skip return address. */
9586 /* Skip pushed static chain. */
9590 /* Skip saved base pointer. */
9595 /* The traditional frame pointer location is at the top of the frame. */
9598 /* Register save area */
9602 /* On SEH target, registers are pushed just before the frame pointer
9603 location. */
9607 /* Align and set SSE register save area. */
9609 {
9610 /* The only ABI that has saved SSE registers (Win64) also has a
9611 16-byte aligned default stack, and thus we don't need to be
9612 within the re-aligned local stack frame to save them. */
9616 }
9619 /* The re-aligned stack starts here. Values before this point are not
9620 directly comparable with values below this point. In order to make
9621 sure that no value happens to be the same before and after, force
9622 the alignment computation below to add a non-zero value. */
9626 /* Va-arg area */
9630 /* Align start of frame for local function. */
9639 /* Frame pointer points here. */
9644 /* Add outgoing arguments area. Can be skipped if we eliminated
9645 all the function calls as dead code.
9646 Skipping is however impossible when function calls alloca. Alloca
9647 expander assumes that last crtl->outgoing_args_size
9648 of stack frame are unused. */
9652 {
9655 }
9656 else
9659 /* Align stack boundary. Only needed if we're calling another function
9660 or using alloca. */
9665 /* We've reached end of stack frame. */
9668 /* Size prologue needs to allocate. */
9679 {
9685 }
9686 else
9690 /* The SEH frame pointer location is near the bottom of the frame.
9691 This is enforced by the fact that the difference between the
9692 stack pointer and the frame pointer is limited to 240 bytes in
9693 the unwind data structure. */
9695 {
9696 HOST_WIDE_INT diff;
9698 /* If we can leave the frame pointer where it is, do so. Also, returns
9699 the establisher frame for __builtin_frame_address (0). */
9704 {
9705 /* Ideally we'd determine what portion of the local stack frame
9706 (within the constraint of the lowest 240) is most heavily used.
9707 But without that complication, simply bias the frame pointer
9708 by 128 bytes so as to maximize the amount of the local stack
9709 frame that is addressable with 8-bit offsets. */
9711 }
9712 }
9713 }
9715 /* This is semi-inlined memory_address_length, but simplified
9716 since we know that we're always dealing with reg+offset, and
9717 to avoid having to create and discard all that rtl. */
9721 {
9725 {
9726 /* EBP and R13 cannot be encoded without an offset. */
9728 }
9732 /* ESP and R12 must be encoded with a SIB byte. */
9734 len++;
9737 }
9739 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9740 The valid base registers are taken from CFUN->MACHINE->FS. */
9742 static rtx
9744 {
9750 {
9751 /* Choose the base register most likely to allow the most scheduling
9752 opportunities. Generally FP is valid throughout the function,
9753 while DRAP must be reloaded within the epilogue. But choose either
9754 over the SP due to increased encoding size. */
9757 {
9760 }
9762 {
9765 }
9767 {
9770 }
9771 }
9772 else
9773 {
9774 HOST_WIDE_INT toffset;
9777 /* Choose the base register with the smallest address encoding.
9778 With a tie, choose FP > DRAP > SP. */
9780 {
9784 }
9786 {
9790 {
9794 }
9795 }
9797 {
9801 {
9805 }
9806 }
9807 }
9811 }
9813 /* Emit code to save registers in the prologue. */
9815 static void
9817 {
9819 rtx insn;
9823 {
9826 }
9827 }
9829 /* Emit a single register save at CFA - CFA_OFFSET. */
9831 static void
9833 HOST_WIDE_INT cfa_offset)
9834 {
9842 /* For SSE saves, we need to indicate the 128-bit alignment. */
9853 /* When saving registers into a re-aligned local stack frame, avoid
9854 any tricky guessing by dwarf2out. */
9856 {
9860 {
9861 /* A bit of a hack. We force the DRAP register to be saved in
9862 the re-aligned stack frame, which provides us with a copy
9863 of the CFA that will last past the prologue. Install it. */
9869 }
9870 else
9871 {
9872 /* The frame pointer is a stable reference within the
9873 aligned frame. Use it. */
9880 }
9881 }
9883 /* The memory may not be relative to the current CFA register,
9884 which means that we may need to generate a new pattern for
9885 use by the unwind info. */
9887 {
9892 }
9893 }
9895 /* Emit code to save registers using MOV insns.
9896 First register is stored at CFA - CFA_OFFSET. */
9897 static void
9899 {
9904 {
9907 }
9908 }
9910 /* Emit code to save SSE registers using MOV insns.
9911 First register is stored at CFA - CFA_OFFSET. */
9912 static void
9914 {
9919 {
9922 }
9923 }
9927 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9928 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9929 Don't add the note if the previously saved value will be left untouched
9930 within stack red-zone till return, as unwinders can find the same value
9931 in the register and on the stack. */
9933 static void
9935 {
9941 {
9944 }
9945 else
9946 queued_cfa_restores
9948 }
9950 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9952 static void
9954 {
9955 rtx last;
9959 ;
9964 }
9966 /* Expand prologue or epilogue stack adjustment.
9967 The pattern exist to put a dependency on all ebp-based memory accesses.
9968 STYLE should be negative if instructions should be marked as frame related,
9969 zero if %r11 register is live and cannot be freely used and positive
9970 otherwise. */
9972 static void
9975 {
9977 rtx insn;
9984 else
9985 {
9986 rtx tmp;
9987 /* r11 is used by indirect sibcall return as well, set before the
9988 epilogue and used after the epilogue. */
9991 else
9992 {
9996 }
10002 }
10009 {
10010 rtx r;
10020 }
10022 {
10025 {
10029 }
10030 }
10033 {
10038 {
10041 }
10043 {
10046 }
10047 else
10048 {
10049 /* Else there are two possibilities: SP itself, which we set
10050 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10051 taken care of this by hand along the eh_return path. */
10054 }
10058 }
10059 }
10061 /* Find an available register to be used as dynamic realign argument
10062 pointer regsiter. Such a register will be written in prologue and
10063 used in begin of body, so it must not be
10064 1. parameter passing register.
10065 2. GOT pointer.
10066 We reuse static-chain register if it is available. Otherwise, we
10067 use DI for i386 and R13 for x86-64. We chose R13 since it has
10068 shorter encoding.
10070 Return: the regno of chosen register. */
10072 static unsigned int
10074 {
10078 {
10079 /* Use R13 for nested function or function need static chain.
10080 Since function with tail call may use any caller-saved
10081 registers in epilogue, DRAP must not use caller-saved
10082 register in such case. */
10087 }
10088 else
10089 {
10090 /* Use DI for nested function or function need static chain.
10091 Since function with tail call may use any caller-saved
10092 registers in epilogue, DRAP must not use caller-saved
10093 register in such case. */
10097 /* Reuse static chain register if it isn't used for parameter
10098 passing. */
10100 {
10104 }
10106 }
10107 }
10109 /* Return minimum incoming stack alignment. */
10111 static unsigned int
10113 {
10116 /* Prefer the one specified at command line. */
10119 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10120 if -mstackrealign is used, it isn't used for sibcall check and
10121 estimated stack alignment is 128bit. */
10123 && !TARGET_64BIT
10124 && ix86_force_align_arg_pointer
10127 else
10130 /* Incoming stack alignment can be changed on individual functions
10131 via force_align_arg_pointer attribute. We use the smallest
10132 incoming stack boundary. */
10138 /* The incoming stack frame has to be aligned at least at
10139 parm_stack_boundary. */
10143 /* Stack at entrance of main is aligned by runtime. We use the
10144 smallest incoming stack boundary. */
10152 }
10154 /* Update incoming stack boundary and estimated stack alignment. */
10156 static void
10158 {
10159 ix86_incoming_stack_boundary
10162 /* x86_64 vararg needs 16byte stack alignment for register save
10163 area. */
10168 }
10170 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10171 needed or an rtx for DRAP otherwise. */
10173 static rtx
10175 {
10180 {
10181 /* Assign DRAP to vDRAP and returns vDRAP */
10183 rtx drap_vreg;
10184 rtx arg_ptr;
10197 {
10200 }
10202 }
10203 else
10205 }
10207 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10209 static rtx
10211 {
10213 }
10216 rtx reg;
10218 };
10220 /* Return a short-lived scratch register for use on function entry.
10221 In 32-bit mode, it is valid only after the registers are saved
10222 in the prologue. This register must be released by means of
10223 release_scratch_register_on_entry once it is dead. */
10225 static void
10227 {
10233 {
10234 /* We always use R11 in 64-bit mode. */
10236 }
10237 else
10238 {
10240 bool fastcall_p
10242 bool thiscall_p
10246 int drap_regno
10249 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10250 for the static chain register. */
10254 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10255 for the static chain register. */
10260 /* ecx is the static chain register. */
10262 && !static_chain_p
10267 /* esi is the static chain register. */
10273 else
10274 {
10277 }
10278 }
10282 {
10285 }
10286 }
10288 /* Release a scratch register obtained from the preceding function. */
10290 static void
10292 {
10294 {
10298 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10304 }
10305 }
10307 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10309 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10311 static void
10313 {
10314 /* We skip the probe for the first interval + a small dope of 4 words and
10315 probe that many bytes past the specified size to maintain a protection
10316 area at the botton of the stack. */
10320 /* See if we have a constant small number of probes to generate. If so,
10321 that's the easy case. The run-time loop is made up of 11 insns in the
10322 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10323 for n # of intervals. */
10325 {
10329 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10330 values of N from 1 until it exceeds SIZE. If only one probe is
10331 needed, this will not generate any code. Then adjust and probe
10332 to PROBE_INTERVAL + SIZE. */
10334 {
10336 {
10339 }
10340 else
10347 }
10351 else
10359 /* Adjust back to account for the additional first interval. */
10363 }
10365 /* Otherwise, do the same as above, but in a loop. Note that we must be
10366 extra careful with variables wrapping around because we might be at
10367 the very top (or the very bottom) of the address space and we have
10368 to be able to handle this case properly; in particular, we use an
10369 equality test for the loop condition. */
10370 else
10371 {
10372 HOST_WIDE_INT rounded_size;
10378 /* Step 1: round SIZE to the previous multiple of the interval. */
10383 /* Step 2: compute initial and final value of the loop counter. */
10385 /* SP = SP_0 + PROBE_INTERVAL. */
10390 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10394 stack_pointer_rtx)));
10397 /* Step 3: the loop
10399 while (SP != LAST_ADDR)
10400 {
10401 SP = SP + PROBE_INTERVAL
10402 probe at SP
10403 }
10405 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10406 values of N from 1 until it is equal to ROUNDED_SIZE. */
10411 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10412 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10415 {
10420 }
10422 /* Adjust back to account for the additional first interval. */
10428 }
10432 /* Even if the stack pointer isn't the CFA register, we need to correctly
10433 describe the adjustments made to it, in particular differentiate the
10434 frame-related ones from the frame-unrelated ones. */
10436 {
10449 }
10451 /* Make sure nothing is scheduled before we are done. */
10453 }
10455 /* Adjust the stack pointer up to REG while probing it. */
10459 {
10469 /* Jump to END_LAB if SP == LAST_ADDR. */
10477 /* SP = SP + PROBE_INTERVAL. */
10481 /* Probe at SP. */
10492 }
10494 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10495 inclusive. These are offsets from the current stack pointer. */
10497 static void
10499 {
10500 /* See if we have a constant small number of probes to generate. If so,
10501 that's the easy case. The run-time loop is made up of 7 insns in the
10502 generic case while the compile-time loop is made up of n insns for n #
10503 of intervals. */
10505 {
10506 HOST_WIDE_INT i;
10508 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10509 it exceeds SIZE. If only one probe is needed, this will not
10510 generate any code. Then probe at FIRST + SIZE. */
10517 }
10519 /* Otherwise, do the same as above, but in a loop. Note that we must be
10520 extra careful with variables wrapping around because we might be at
10521 the very top (or the very bottom) of the address space and we have
10522 to be able to handle this case properly; in particular, we use an
10523 equality test for the loop condition. */
10524 else
10525 {
10532 /* Step 1: round SIZE to the previous multiple of the interval. */
10537 /* Step 2: compute initial and final value of the loop counter. */
10539 /* TEST_OFFSET = FIRST. */
10542 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10546 /* Step 3: the loop
10548 while (TEST_ADDR != LAST_ADDR)
10549 {
10550 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10551 probe at TEST_ADDR
10552 }
10554 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10555 until it is equal to ROUNDED_SIZE. */
10560 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10561 that SIZE is equal to ROUNDED_SIZE. */
10566 stack_pointer_rtx,
10571 }
10573 /* Make sure nothing is scheduled before we are done. */
10575 }
10577 /* Probe a range of stack addresses from REG to END, inclusive. These are
10578 offsets from the current stack pointer. */
10582 {
10592 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10600 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10604 /* Probe at TEST_ADDR. */
10617 }
10619 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10620 to be generated in correct form. */
10621 static void
10623 {
10624 /* Check if stack realign is really needed after reload, and
10625 stores result in cfun */
10626 unsigned int incoming_stack_boundary
10635 {
10636 /* After stack_realign_needed is finalized, we can't no longer
10637 change it. */
10640 }
10642 /* If the only reason for frame_pointer_needed is that we conservatively
10643 assumed stack realignment might be needed, but in the end nothing that
10644 needed the stack alignment had been spilled, clear frame_pointer_needed
10645 and say we don't need stack realignment. */
10647 && frame_pointer_needed
10649 && flag_omit_frame_pointer
10651 && !ix86_current_function_calls_tls_descriptor
10660 {
10662 basic_block bb;
10669 HARD_FRAME_POINTER_REGNUM);
10671 {
10672 rtx insn;
10676 set_up_by_prologue))
10677 {
10681 }
10682 }
10684 /* If drap has been set, but it actually isn't live at the start
10685 of the function, there is no reason to set it up. */
10687 {
10690 {
10693 }
10694 }
10695 else
10710 }
10714 }
10716 /* Expand the prologue into a bunch of separate insns. */
10718 void
10720 {
10725 HOST_WIDE_INT allocate;
10731 /* DRAP should not coexist with stack_realign_fp */
10736 /* Initialize CFA state for before the prologue. */
10740 /* Track SP offset to the CFA. We continue tracking this after we've
10741 swapped the CFA register away from SP. In the case of re-alignment
10742 this is fudged; we're interested to offsets within the local frame. */
10749 {
10750 /* We should have already generated an error for any use of
10751 ms_hook on a nested function. */
10754 /* Check if profiling is active and we shall use profiling before
10755 prologue variant. If so sorry. */
10760 /* In ix86_asm_output_function_label we emitted:
10761 8b ff movl.s %edi,%edi
10762 55 push %ebp
10763 8b ec movl.s %esp,%ebp
10765 This matches the hookable function prologue in Win32 API
10766 functions in Microsoft Windows XP Service Pack 2 and newer.
10767 Wine uses this to enable Windows apps to hook the Win32 API
10768 functions provided by Wine.
10770 What that means is that we've already set up the frame pointer. */
10774 {
10777 /* We've decided to use the frame pointer already set up.
10778 Describe this to the unwinder by pretending that both
10779 push and mov insns happen right here.
10781 Putting the unwind info here at the end of the ms_hook
10782 is done so that we can make absolutely certain we get
10783 the required byte sequence at the start of the function,
10784 rather than relying on an assembler that can produce
10785 the exact encoding required.
10787 However it does mean (in the unpatched case) that we have
10788 a 1 insn window where the asynchronous unwind info is
10789 incorrect. However, if we placed the unwind info at
10790 its correct location we would have incorrect unwind info
10791 in the patched case. Which is probably all moot since
10792 I don't expect Wine generates dwarf2 unwind info for the
10793 system libraries that use this feature. */
10799 stack_pointer_rtx);
10807 /* Note that gen_push incremented m->fs.cfa_offset, even
10808 though we didn't emit the push insn here. */
10812 }
10813 else
10814 {
10815 /* The frame pointer is not needed so pop %ebp again.
10816 This leaves us with a pristine state. */
10818 }
10819 }
10821 /* The first insn of a function that accepts its static chain on the
10822 stack is to push the register that would be filled in by a direct
10823 call. This insn will be skipped by the trampoline. */
10825 {
10829 /* We don't want to interpret this push insn as a register save,
10830 only as a stack adjustment. The real copy of the register as
10831 a save will be done later, if needed. */
10836 }
10838 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10839 of DRAP is needed and stack realignment is really needed after reload */
10841 {
10844 /* Only need to push parameter pointer reg if it is caller saved. */
10846 {
10847 /* Push arg pointer reg */
10850 }
10852 /* Grab the argument pointer. */
10859 /* Align the stack. */
10861 stack_pointer_rtx,
10865 /* Replicate the return address on the stack so that return
10866 address can be reached via (argp - 1) slot. This is needed
10867 to implement macro RETURN_ADDR_RTX and intrinsic function
10868 expand_builtin_return_addr etc. */
10874 /* For the purposes of frame and register save area addressing,
10875 we've started over with a new frame. */
10878 }
10884 {
10885 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10886 slower on all targets. Also sdb doesn't like it. */
10890 /* Push registers now, before setting the frame pointer
10891 on SEH target. */
10893 && TARGET_SEH
10895 {
10899 }
10902 {
10910 }
10911 }
10914 {
10915 /* If saving registers via PUSH, do so now. */
10917 {
10921 }
10923 /* When using red zone we may start register saving before allocating
10924 the stack frame saving one cycle of the prologue. However, avoid
10925 doing this if we have to probe the stack; at least on x86_64 the
10926 stack probe can turn into a call that clobbers a red zone location. */
10928 && (! TARGET_STACK_PROBE
10930 {
10933 }
10934 }
10937 {
10941 /* The computation of the size of the re-aligned stack frame means
10942 that we must allocate the size of the register save area before
10943 performing the actual alignment. Otherwise we cannot guarantee
10944 that there's enough storage above the realignment point. */
10951 /* Align the stack. */
10953 stack_pointer_rtx,
10956 /* For the purposes of register save area addressing, the stack
10957 pointer is no longer valid. As for the value of sp_offset,
10958 see ix86_compute_frame_layout, which we need to match in order
10959 to pass verification of stack_pointer_offset at the end. */
10962 }
10967 {
10968 /* We start to count from ARG_POINTER. */
10971 /* If it was realigned, take into account the fake frame. */
10973 {
10980 /* This over-estimates by 1 minimal-stack-alignment-unit but
10981 mitigates that by counting in the new return address slot. */
10982 current_function_dynamic_stack_size
10984 }
10987 }
10989 /* On SEH target with very large frame size, allocate an area to save
10990 SSE registers (as the very large allocation won't be described). */
10994 {
10995 HOST_WIDE_INT sse_size =
11000 /* No need to do stack checking as the area will be immediately
11001 written. */
11008 }
11010 /* The stack has already been decremented by the instruction calling us
11011 so probe if the size is non-negative to preserve the protection area. */
11013 {
11014 /* We expect the registers to be saved when probes are used. */
11018 {
11021 {
11024 }
11025 }
11026 else
11027 {
11034 {
11036 {
11039 }
11040 else
11042 }
11043 else
11044 {
11046 {
11050 }
11051 else
11053 }
11054 }
11055 }
11058 ;
11061 {
11065 }
11066 else
11067 {
11079 {
11082 /* Note that SEH directives need to continue tracking the stack
11083 pointer even after the frame pointer has been set up. */
11085 {
11089 }
11090 }
11093 {
11098 {
11102 }
11103 }
11108 /* Use the fact that AX still contains ALLOCATE. */
11110 ? gen_pro_epilogue_adjust_stack_di_sub
11117 {
11125 }
11128 /* Use stack_pointer_rtx for relative addressing so that code
11129 works for realigned stack, too. */
11131 {
11138 }
11140 {
11145 }
11146 }
11149 /* If we havn't already set up the frame pointer, do so now. */
11151 {
11163 }
11171 /* We don't use pic-register for pe-coff target. */
11173 && !TARGET_PECOFF
11176 {
11183 }
11186 {
11188 {
11190 {
11200 label));
11204 }
11205 else
11207 }
11208 else
11209 {
11213 }
11214 }
11216 /* In the pic_reg_used case, make sure that the got load isn't deleted
11217 when mcount needs it. Blockage to avoid call movement across mcount
11218 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11219 note. */
11224 {
11225 /* vDRAP is setup but after reload it turns out stack realign
11226 isn't necessary, here we will emit prologue to setup DRAP
11227 without stack realign adjustment */
11230 }
11232 /* Prevent instructions from being scheduled into register save push
11233 sequence when access to the redzone area is done through frame pointer.
11234 The offset between the frame pointer and the stack pointer is calculated
11235 relative to the value of the stack pointer at the end of the function
11236 prologue, and moving instructions that access redzone area via frame
11237 pointer inside push sequence violates this assumption. */
11241 /* Emit cld instruction if stringops are used in the function. */
11245 /* SEH requires that the prologue end within 256 bytes of the start of
11246 the function. Prevent instruction schedules that would extend that.
11247 Further, prevent alloca modifications to the stack pointer from being
11248 combined with prologue modifications. */
11251 }
11253 /* Emit code to restore REG using a POP insn. */
11255 static void
11257 {
11266 {
11267 /* Previously we'd represented the CFA as an expression
11268 like *(%ebp - 8). We've just popped that value from
11269 the stack, which means we need to reset the CFA to
11270 the drap register. This will remain until we restore
11271 the stack pointer. */
11275 /* This means that the DRAP register is valid for addressing too. */
11278 }
11281 {
11288 }
11290 /* When the frame pointer is the CFA, and we pop it, we are
11291 swapping back to the stack pointer as the CFA. This happens
11292 for stack frames that don't allocate other data, so we assume
11293 the stack pointer is now pointing at the return address, i.e.
11294 the function entry state, which makes the offset be 1 word. */
11296 {
11299 {
11307 }
11308 }
11309 }
11311 /* Emit code to restore saved registers using POP insns. */
11313 static void
11315 {
11321 }
11323 /* Emit code and notes for the LEAVE instruction. */
11325 static void
11327 {
11339 {
11347 }
11350 }
11352 /* Emit code to restore saved registers using MOV insns.
11353 First register is restored from CFA - CFA_OFFSET. */
11354 static void
11357 {
11363 {
11372 {
11373 /* Previously we'd represented the CFA as an expression
11374 like *(%ebp - 8). We've just popped that value from
11375 the stack, which means we need to reset the CFA to
11376 the drap register. This will remain until we restore
11377 the stack pointer. */
11381 /* This means that the DRAP register is valid for addressing. */
11383 }
11384 else
11388 }
11389 }
11391 /* Emit code to restore saved registers using MOV insns.
11392 First register is restored from CFA - CFA_OFFSET. */
11393 static void
11396 {
11401 {
11403 rtx mem;
11413 }
11414 }
11416 /* Restore function stack, frame, and registers. */
11418 void
11420 {
11436 /* The FP must be valid if the frame pointer is present. */
11441 /* We must have *some* valid pointer to the stack frame. */
11444 /* The DRAP is never valid at this point. */
11447 /* See the comment about red zone and frame
11448 pointer usage in ix86_expand_prologue. */
11455 /* Determine the CFA offset of the end of the red-zone. */
11458 {
11459 /* The red-zone begins below the return address. */
11462 /* When the register save area is in the aligned portion of
11463 the stack, determine the maximum runtime displacement that
11464 matches up with the aligned frame. */
11468 }
11470 /* Special care must be taken for the normal return case of a function
11471 using eh_return: the eax and edx registers are marked as saved, but
11472 not restored along this path. Adjust the save location to match. */
11476 /* EH_RETURN requires the use of moves to function properly. */
11479 /* SEH requires the use of pops to identify the epilogue. */
11482 /* If we're only restoring one register and sp is not valid then
11483 using a move instruction to restore the register since it's
11484 less work than reloading sp and popping the register. */
11497 && TARGET_USE_LEAVE
11501 else
11505 {
11506 /* Ensure that the entire register save area is addressable via
11507 the stack pointer, if we will restore via sp. */
11512 {
11516 style,
11518 }
11519 }
11521 /* If there are any SSE registers to restore, then we have to do it
11522 via moves, since there's obviously no pop for SSE regs. */
11528 {
11529 rtx t;
11534 /* eh_return epilogues need %ecx added to the stack pointer. */
11536 {
11539 /* Stack align doesn't work with eh_return. */
11541 /* Neither does regparm nested functions. */
11545 {
11553 /* Note that we use SA as a temporary CFA, as the return
11554 address is at the proper place relative to it. We
11555 pretend this happens at the FP restore insn because
11556 prior to this insn the FP would be stored at the wrong
11557 offset relative to SA, and after this insn we have no
11558 other reasonable register to use for the CFA. We don't
11559 bother resetting the CFA to the SP for the duration of
11560 the return insn. */
11573 }
11574 else
11575 {
11583 {
11587 UNITS_PER_WORD));
11589 }
11590 }
11593 }
11594 }
11595 else
11596 {
11597 /* SEH requires that the function end with (1) a stack adjustment
11598 if necessary, (2) a sequence of pops, and (3) a return or
11599 jump instruction. Prevent insns from the function body from
11600 being scheduled into this sequence. */
11602 {
11603 /* Prevent a catch region from being adjacent to the standard
11604 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11605 several other flags that would be interesting to test are
11606 not yet set up. */
11609 else
11611 }
11613 /* First step is to deallocate the stack frame so that we can
11614 pop the registers. Also do it on SEH target for very large
11615 frame as the emitted instructions aren't allowed by the ABI in
11616 epilogues. */
11618 || (TARGET_SEH
11621 {
11626 }
11628 {
11632 style,
11634 }
11637 }
11639 /* If we used a stack pointer and haven't already got rid of it,
11640 then do so now. */
11642 {
11643 /* If the stack pointer is valid and pointing at the frame
11644 pointer store address, then we only need a pop. */
11647 /* Leave results in shorter dependency chains on CPUs that are
11648 able to grok it fast. */
11653 else
11654 {
11656 hard_frame_pointer_rtx,
11659 }
11660 }
11663 {
11665 rtx insn;
11691 }
11693 /* At this point the stack pointer must be valid, and we must have
11694 restored all of the registers. We may not have deallocated the
11695 entire stack frame. We've delayed this until now because it may
11696 be possible to merge the local stack deallocation with the
11697 deallocation forced by ix86_static_chain_on_stack. */
11702 {
11706 }
11707 else
11710 /* Sibcall epilogues don't want a return instruction. */
11712 {
11715 }
11718 {
11721 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11722 address, do explicit add, and jump indirectly to the caller. */
11725 {
11727 rtx insn;
11729 /* There is no "pascal" calling convention in any 64bit ABI. */
11746 }
11747 else
11749 }
11750 else
11753 /* Restore the state back to the state from the prologue,
11754 so that it's correct for the next epilogue. */
11756 }
11758 /* Reset from the function's potential modifications. */
11760 static void
11762 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11763 {
11766 #if TARGET_MACHO
11767 /* Mach-O doesn't support labels at the end of objects, so if
11768 it looks like we might want one, insert a NOP. */
11769 {
11775 {
11776 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11777 notes only, instead set their CODE_LABEL_NUMBER to -1,
11778 otherwise there would be code generation differences
11779 in between -g and -g0. */
11783 }
11793 }
11794 #endif
11796 }
11798 /* Return a scratch register to use in the split stack prologue. The
11799 split stack prologue is used for -fsplit-stack. It is the first
11800 instructions in the function, even before the regular prologue.
11801 The scratch register can be any caller-saved register which is not
11802 used for parameters or for the static chain. */
11804 static unsigned int
11806 {
11809 else
11810 {
11823 {
11825 {
11829 }
11831 }
11833 {
11837 }
11839 {
11842 else
11843 {
11845 {
11849 }
11851 }
11852 }
11853 else
11854 {
11855 /* FIXME: We could make this work by pushing a register
11856 around the addition and comparison. */
11859 }
11860 }
11861 }
11863 /* A SYMBOL_REF for the function which allocates new stackspace for
11864 -fsplit-stack. */
11868 /* A SYMBOL_REF for the more stack function when using the large
11869 model. */
11873 /* Handle -fsplit-stack. These are the first instructions in the
11874 function, even before the regular prologue. */
11876 void
11878 {
11880 HOST_WIDE_INT allocate;
11885 rtx fn;
11893 /* This is the label we will branch to if we have enough stack
11894 space. We expect the basic block reordering pass to reverse this
11895 branch if optimizing, so that we branch in the unlikely case. */
11898 /* We need to compare the stack pointer minus the frame size with
11899 the stack boundary in the TCB. The stack boundary always gives
11900 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11901 can compare directly. Otherwise we need to do an addition. */
11904 UNSPEC_STACK_CHECK);
11909 else
11910 {
11912 rtx offset;
11914 /* We need a scratch register to hold the stack pointer minus
11915 the required frame size. Since this is the very start of the
11916 function, the scratch register can be any caller-saved
11917 register which is not used for parameters. */
11924 {
11925 /* We don't use ix86_gen_add3 in this case because it will
11926 want to split to lea, but when not optimizing the insn
11927 will not be split after this point. */
11930 offset)));
11931 }
11932 else
11933 {
11936 stack_pointer_rtx));
11937 }
11939 }
11945 /* Mark the jump as very likely to be taken. */
11953 /* Get more stack space. We pass in the desired stack space and the
11954 size of the arguments to copy to the new stack. In 32-bit mode
11955 we push the parameters; __morestack will return on a new stack
11956 anyhow. In 64-bit mode we pass the parameters in r10 and
11957 r11. */
11962 {
11968 /* If this function uses a static chain, it will be in %r10.
11969 Preserve it across the call to __morestack. */
11971 {
11972 rtx rax;
11977 }
11981 {
11982 HOST_WIDE_INT argval;
11985 /* When using the large model we need to load the address
11986 into a register, and we've run out of registers. So we
11987 switch to a different calling convention, and we call a
11988 different function: __morestack_large. We pass the
11989 argument size in the upper 32 bits of r10 and pass the
11990 frame size in the lower 32 bits. */
11995 split_stack_fn_large =
11999 {
12009 UNSPEC_GOT);
12015 }
12016 else
12023 }
12024 else
12025 {
12029 }
12032 }
12033 else
12034 {
12037 }
12043 /* In order to make call/return prediction work right, we now need
12044 to execute a return instruction. See
12045 libgcc/config/i386/morestack.S for the details on how this works.
12047 For flow purposes gcc must not see this as a return
12048 instruction--we need control flow to continue at the subsequent
12049 label. Therefore, we use an unspec. */
12053 /* If we are in 64-bit mode and this function uses a static chain,
12054 we saved %r10 in %rax before calling _morestack. */
12059 /* If this function calls va_start, we need to store a pointer to
12060 the arguments on the old stack, because they may not have been
12061 all copied to the new stack. At this point the old stack can be
12062 found at the frame pointer value used by __morestack, because
12063 __morestack has set that up before calling back to us. Here we
12064 store that pointer in a scratch register, and in
12065 ix86_expand_prologue we store the scratch register in a stack
12066 slot. */
12068 {
12070 rtx frame_reg;
12077 /* 64-bit:
12078 fp -> old fp value
12079 return address within this function
12080 return address of caller of this function
12081 stack arguments
12082 So we add three words to get to the stack arguments.
12084 32-bit:
12085 fp -> old fp value
12086 return address within this function
12087 first argument to __morestack
12088 second argument to __morestack
12089 return address of caller of this function
12090 stack arguments
12091 So we add five words to get to the stack arguments.
12092 */
12103 }
12108 /* If this function calls va_start, we now have to set the scratch
12109 register for the case where we do not call __morestack. In this
12110 case we need to set it based on the stack pointer. */
12112 {
12119 }
12120 }
12122 /* We may have to tell the dataflow pass that the split stack prologue
12123 is initializing a scratch register. */
12125 static void
12127 {
12129 {
12132 }
12133 }
12134 \f
12135 /* Extract the parts of an RTL expression that is a valid memory address
12136 for an instruction. Return 0 if the structure of the address is
12137 grossly off. Return -1 if the address contains ASHIFT, so it is not
12138 strictly valid, but still used for computing length of lea instruction. */
12140 int
12142 {
12147 rtx tmp;
12151 /* Allow zero-extended SImode addresses,
12152 they will be emitted with addr32 prefix. */
12154 {
12157 {
12161 }
12164 {
12171 }
12172 }
12174 /* Allow SImode subregs of DImode addresses,
12175 they will be emitted with addr32 prefix. */
12177 {
12180 {
12184 }
12185 }
12190 {
12193 else
12195 }
12197 {
12202 do
12203 {
12208 }
12215 {
12218 {
12243 /* FALLTHRU */
12247 && TARGET_TLS_DIRECT_SEG_REFS
12250 else
12257 /* FALLTHRU */
12264 else
12279 }
12280 }
12281 }
12283 {
12286 }
12288 {
12289 /* We're called for lea too, which implements ashift on occasion. */
12299 }
12300 else
12304 {
12306 ;
12309 ;
12310 else
12312 }
12314 /* Extract the integral value of scale. */
12316 {
12320 }
12325 /* Avoid useless 0 displacement. */
12329 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12334 {
12335 rtx tmp;
12338 }
12340 /* Special case: %ebp cannot be encoded as a base without a displacement.
12341 Similarly %r13. */
12343 && base_reg
12352 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12353 Avoid this by transforming to [%esi+0].
12354 Reload calls address legitimization without cfun defined, so we need
12355 to test cfun for being non-NULL. */
12361 /* Special case: encode reg+reg instead of reg*2. */
12365 /* Special case: scaling cannot be encoded without base or displacement. */
12376 }
12377 \f
12378 /* Return cost of the memory address x.
12379 For i386, it is better to use a complex address than let gcc copy
12380 the address into a reg and make a new pseudo. But not if the address
12381 requires to two regs - that would mean more pseudos with longer
12382 lifetimes. */
12383 static int
12385 addr_space_t as ATTRIBUTE_UNUSED,
12387 {
12399 /* Attempt to minimize number of registers in the address. */
12405 cost++;
12412 cost++;
12414 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12415 since it's predecode logic can't detect the length of instructions
12416 and it degenerates to vector decoded. Increase cost of such
12417 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12418 to split such addresses or even refuse such addresses at all.
12420 Following addressing modes are affected:
12421 [base+scale*index]
12422 [scale*index+disp]
12423 [base+index]
12425 The first and last case may be avoidable by explicitly coding the zero in
12426 memory address, but I don't have AMD-K6 machine handy to check this
12427 theory. */
12436 }
12437 \f
12438 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12439 this is used for to form addresses to local data when -fPIC is in
12440 use. */
12442 static bool
12444 {
12447 }
12449 /* Determine if a given RTX is a valid constant. We already know this
12450 satisfies CONSTANT_P. */
12452 static bool
12454 {
12456 {
12461 {
12465 }
12470 /* Only some unspecs are valid as "constants". */
12473 {
12489 }
12491 /* We must have drilled down to a symbol. */
12496 /* FALLTHRU */
12499 /* TLS symbols are never valid. */
12503 /* DLLIMPORT symbols are never valid. */
12508 #if TARGET_MACHO
12509 /* mdynamic-no-pic */
12512 #endif
12528 }
12530 /* Otherwise we handle everything else in the move patterns. */
12532 }
12534 /* Determine if it's legal to put X into the constant pool. This
12535 is not possible for the address of thread-local symbols, which
12536 is checked above. */
12538 static bool
12540 {
12541 /* We can always put integral constants and vectors in memory. */
12543 {
12551 }
12553 }
12555 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12556 otherwise zero. */
12558 static bool
12560 {
12566 }
12569 /* Nonzero if the constant value X is a legitimate general operand
12570 when generating PIC code. It is given that flag_pic is on and
12571 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12573 bool
12575 {
12576 rtx inner;
12579 {
12586 /* Only some unspecs are valid as "constants". */
12589 {
12602 }
12603 /* FALLTHRU */
12611 }
12612 }
12614 /* Determine if a given CONST RTX is a valid memory displacement
12615 in PIC mode. */
12617 bool
12619 {
12622 /* In 64bit mode we can allow direct addresses of symbols and labels
12623 when they are not dynamic symbols. */
12625 {
12629 {
12653 /* FALLTHRU */
12656 /* TLS references should always be enclosed in UNSPEC.
12657 The dllimported symbol needs always to be resolved. */
12663 {
12671 /* Function-symbols need to be resolved only for
12672 large-model.
12673 For the small-model we don't need to resolve anything
12674 here. */
12679 /* Non-external symbols don't need to be resolved for
12680 large, and medium-model. */
12685 }
12694 }
12695 }
12701 {
12702 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12703 of GOT tables. We should not need these anyway. */
12715 }
12719 {
12724 }
12733 {
12737 /* We need to check for both symbols and labels because VxWorks loads
12738 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12739 details. */
12743 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12744 While ABI specify also 32bit relocation but we don't produce it in
12745 small PIC model at all. */
12767 }
12770 }
12772 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12773 replace the input X, or the original X if no replacement is called for.
12774 The output parameter *WIN is 1 if the calling macro should goto WIN,
12775 0 if it should not. */
12777 bool
12782 {
12783 /* Reload can generate:
12785 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12786 (reg:DI 97))
12787 (reg:DI 2 cx))
12789 This RTX is rejected from ix86_legitimate_address_p due to
12790 non-strictness of base register 97. Following this rejection,
12791 reload pushes all three components into separate registers,
12792 creating invalid memory address RTX.
12794 Following code reloads only the invalid part of the
12795 memory address RTX. */
12801 {
12807 {
12812 }
12816 {
12821 }
12825 }
12828 }
12830 /* Determine if op is suitable RTX for an address register.
12831 Return naked register if a register or a register subreg is
12832 found, otherwise return NULL_RTX. */
12834 static rtx
12836 {
12839 /* Only SImode or DImode registers can form the address. */
12846 {
12854 /* Don't allow SUBREGs that span more than a word. It can
12855 lead to spill failures when the register is one word out
12856 of a two word structure. */
12860 /* Allow only SUBREGs of non-eliminable hard registers. */
12863 }
12865 /* Op is not a register. */
12867 }
12869 /* Recognizes RTL expressions that are valid memory addresses for an
12870 instruction. The MODE argument is the machine mode for the MEM
12871 expression that wants to use this address.
12873 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12874 convert common non-canonical forms to canonical form so that they will
12875 be recognized. */
12877 static bool
12880 {
12883 HOST_WIDE_INT scale;
12887 /* Decomposition failed. */
12896 /* Validate base register. */
12898 {
12906 /* Base is not valid. */
12908 }
12910 /* Validate index register. */
12912 {
12920 /* Index is not valid. */
12922 }
12924 /* Index and base should have the same mode. */
12929 /* Address override works only on the (%reg) part of %fs:(%reg). */
12935 /* Validate scale factor. */
12937 {
12939 /* Scale without index. */
12943 /* Scale is not a valid multiplier. */
12945 }
12947 /* Validate displacement. */
12949 {
12954 {
12955 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12956 used. While ABI specify also 32bit relocations, we don't produce
12957 them at all and use IP relative instead. */
12964 /* 64bit address unspec. */
12984 /* Invalid address unspec. */
12986 }
12989 && (flag_pic
12990 || (TARGET_MACHO
12991 #if TARGET_MACHO
12992 && MACHOPIC_INDIRECT
12994 #endif
12995 )))
12996 {
12998 is_legitimate_pic:
13000 {
13001 /* foo@dtpoff(%rX) is ok. */
13008 /* Non-constant pic memory reference. */
13010 }
13013 /* Displacement is an invalid pic construct. */
13015 #if TARGET_MACHO
13018 /* displacment must be referenced via non_lazy_pointer */
13020 #endif
13022 /* This code used to verify that a symbolic pic displacement
13023 includes the pic_offset_table_rtx register.
13025 While this is good idea, unfortunately these constructs may
13026 be created by "adds using lea" optimization for incorrect
13027 code like:
13029 int a;
13030 int foo(int i)
13031 {
13032 return *(&a+i);
13033 }
13035 This code is nonsensical, but results in addressing
13036 GOT table with pic_offset_table_rtx base. We can't
13037 just refuse it easily, since it gets matched by
13038 "addsi3" pattern, that later gets split to lea in the
13039 case output register differs from input. While this
13040 can be handled by separate addsi pattern for this case
13041 that never results in lea, this seems to be easier and
13042 correct fix for crash to disable this test. */
13043 }
13050 /* Displacement is not constant. */
13054 /* Displacement is out of range. */
13056 /* In x32 mode, constant addresses are sign extended to 64bit, so
13057 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13062 }
13064 /* Everything looks valid. */
13066 }
13068 /* Determine if a given RTX is a valid constant address. */
13070 bool
13072 {
13074 }
13075 \f
13076 /* Return a unique alias set for the GOT. */
13078 static alias_set_type
13080 {
13085 }
13087 /* Return a legitimate reference for ORIG (an address) using the
13088 register REG. If REG is 0, a new pseudo is generated.
13090 There are two types of references that must be handled:
13092 1. Global data references must load the address from the GOT, via
13093 the PIC reg. An insn is emitted to do this load, and the reg is
13094 returned.
13096 2. Static data references, constant pool addresses, and code labels
13097 compute the address as an offset from the GOT, whose base is in
13098 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13099 differentiate them from global data objects. The returned
13100 address is the PIC reg + an unspec constant.
13102 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13103 reg also appears in the address. */
13105 static rtx
13107 {
13111 #if TARGET_MACHO
13113 {
13116 /* Use the generic Mach-O PIC machinery. */
13118 }
13119 #endif
13122 {
13126 }
13132 {
13133 rtx tmpreg;
13134 /* This symbol may be referenced via a displacement from the PIC
13135 base address (@GOTOFF). */
13142 {
13144 UNSPEC_GOTOFF);
13146 }
13147 else
13152 else
13157 {
13161 }
13162 else
13164 }
13166 {
13167 /* This symbol may be referenced via a displacement from the PIC
13168 base address (@GOTOFF). */
13175 {
13177 UNSPEC_GOTOFF);
13179 }
13180 else
13186 {
13189 }
13190 }
13192 /* We can't use @GOTOFF for text labels on VxWorks;
13193 see gotoff_operand. */
13195 {
13200 /* For x64 PE-COFF there is no GOT table. So we use address
13201 directly. */
13203 {
13211 }
13213 {
13221 /* Use directly gen_movsi, otherwise the address is loaded
13222 into register for CSE. We don't want to CSE this addresses,
13223 instead we CSE addresses from the GOT table, so skip this. */
13226 }
13227 else
13228 {
13229 /* This symbol must be referenced via a load from the
13230 Global Offset Table (@GOT). */
13246 }
13247 }
13248 else
13249 {
13252 {
13254 {
13257 }
13258 else
13260 }
13262 {
13265 /* We must match stuff we generate before. Assume the only
13266 unspecs that can get here are ours. Not that we could do
13267 anything with them anyway.... */
13273 }
13275 {
13278 /* Check first to see if this is a constant offset from a @GOTOFF
13279 symbol reference. */
13282 {
13284 {
13288 UNSPEC_GOTOFF);
13294 {
13297 }
13298 }
13299 else
13300 {
13303 {
13307 }
13308 }
13309 }
13310 else
13311 {
13314 new_rtx
13318 {
13321 {
13324 new_rtx
13326 }
13327 else
13329 }
13330 else
13331 {
13334 {
13337 }
13339 }
13340 }
13341 }
13342 }
13344 }
13345 \f
13346 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13348 static rtx
13350 {
13354 {
13359 }
13365 }
13367 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13371 static rtx
13373 {
13375 {
13381 }
13384 {
13386 UNSPEC_PLTOFF);
13389 }
13392 }
13394 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13398 rtx
13400 {
13402 {
13403 ix86_tls_module_base_symbol
13408 }
13411 }
13413 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13414 false if we expect this to be used for a memory address and true if
13415 we expect to load the address into a register. */
13417 static rtx
13419 {
13425 /* Fall back to global dynamic model if tool chain cannot support local
13426 dynamic. */
13433 {
13438 {
13441 else
13442 {
13445 }
13446 }
13449 {
13452 else
13462 }
13463 else
13464 {
13468 {
13470 rtx insns;
13473 emit_call_insn
13483 }
13484 else
13486 }
13493 {
13496 else
13497 {
13500 }
13501 }
13504 {
13509 else
13515 }
13516 else
13517 {
13521 {
13526 emit_call_insn
13531 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13532 share the LD_BASE result with other LD model accesses. */
13534 UNSPEC_TLS_LD_BASE);
13538 }
13539 else
13541 }
13549 {
13556 }
13561 {
13563 {
13564 /* The Sun linker took the AMD64 TLS spec literally
13565 and can only handle %rax as destination of the
13566 initial executable code sequence. */
13571 }
13573 /* Generate DImode references to avoid %fs:(%reg32)
13574 problems and linker IE->LE relaxation bug. */
13578 }
13580 {
13585 }
13587 {
13591 }
13592 else
13593 {
13596 }
13606 {
13611 }
13612 else
13613 {
13617 }
13627 {
13631 }
13632 else
13633 {
13637 }
13642 }
13645 }
13647 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13648 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13649 unique refptr-DECL symbol corresponding to symbol DECL. */
13652 htab_t dllimport_map;
13654 static tree
13656 {
13663 tree to;
13664 rtx rtl;
13691 else
13704 {
13706 #ifdef SUB_TARGET_RECORD_STUB
13708 #endif
13709 }
13718 }
13720 /* Expand SYMBOL into its corresponding far-addresse symbol.
13721 WANT_REG is true if we require the result be a register. */
13723 static rtx
13725 {
13726 tree imp_decl;
13727 rtx x;
13736 }
13738 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13739 true if we require the result be a register. */
13741 static rtx
13743 {
13744 tree imp_decl;
13745 rtx x;
13754 }
13756 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13757 is true if we require the result be a register. */
13759 static rtx
13761 {
13766 {
13773 {
13776 }
13777 }
13793 {
13796 }
13798 }
13800 /* Try machine-dependent ways of modifying an illegitimate address
13801 to be legitimate. If we find one, return the new, valid address.
13802 This macro is used in only one place: `memory_address' in explow.c.
13804 OLDX is the address as it was before break_out_memory_refs was called.
13805 In some cases it is useful to look at this to decide what needs to be done.
13807 It is always safe for this macro to do nothing. It exists to recognize
13808 opportunities to optimize the output.
13810 For the 80386, we handle X+REG by loading X into a register R and
13811 using R+REG. R will go in a general reg and indexing will be used.
13812 However, if REG is a broken-out memory address or multiplication,
13813 nothing needs to be done because REG can certainly go in a general reg.
13815 When -fpic is used, special handling is needed for symbolic references.
13816 See comments by legitimize_pic_address in i386.c for details. */
13818 static rtx
13821 {
13832 {
13836 }
13839 {
13843 }
13848 #if TARGET_MACHO
13851 #endif
13853 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13857 {
13862 }
13865 {
13866 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13871 {
13877 }
13882 {
13888 }
13890 /* Put multiply first if it isn't already. */
13892 {
13897 }
13899 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13900 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13901 created by virtual register instantiation, register elimination, and
13902 similar optimizations. */
13904 {
13910 }
13912 /* Canonicalize
13913 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13914 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13919 {
13920 rtx constant;
13924 {
13927 }
13929 {
13932 }
13933 else
13937 {
13944 }
13945 }
13951 {
13954 }
13957 {
13960 }
13968 {
13971 }
13977 {
13981 {
13984 }
13988 }
13991 {
13995 {
13998 }
14002 }
14003 }
14006 }
14007 \f
14008 /* Print an integer constant expression in assembler syntax. Addition
14009 and subtraction are the only arithmetic that may appear in these
14010 expressions. FILE is the stdio stream to write to, X is the rtx, and
14011 CODE is the operand print code from the output string. */
14013 static void
14015 {
14019 {
14028 else
14029 {
14032 /* Mark the decl as referenced so that cgraph will
14033 output the function. */
14037 #if TARGET_MACHO
14041 #endif
14043 }
14051 /* FALLTHRU */
14062 /* This used to output parentheses around the expression,
14063 but that does not work on the 386 (either ATT or BSD assembler). */
14069 {
14070 /* We can use %d if the number is <32 bits and positive. */
14075 else
14077 }
14078 else
14079 /* We can't handle floating point constants;
14080 TARGET_PRINT_OPERAND must handle them. */
14085 /* Some assemblers need integer constants to appear first. */
14087 {
14091 }
14092 else
14093 {
14098 }
14113 {
14117 }
14122 {
14141 /* FIXME: This might be @TPOFF in Sun ld too. */
14150 else
14160 else
14166 #if TARGET_MACHO
14171 #endif
14175 }
14180 }
14181 }
14183 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14184 We need to emit DTP-relative relocations. */
14186 static void ATTRIBUTE_UNUSED
14188 {
14193 {
14201 }
14202 }
14204 /* Return true if X is a representation of the PIC register. This copes
14205 with calls from ix86_find_base_term, where the register might have
14206 been replaced by a cselib value. */
14208 static bool
14210 {
14214 else
14216 }
14218 /* Helper function for ix86_delegitimize_address.
14219 Attempt to delegitimize TLS local-exec accesses. */
14221 static rtx
14223 {
14248 {
14253 }
14259 }
14261 /* In the name of slightly smaller debug output, and to cater to
14262 general assembler lossage, recognize PIC+GOTOFF and turn it back
14263 into a direct symbol reference.
14265 On Darwin, this is necessary to avoid a crash, because Darwin
14266 has a different PIC label for each routine but the DWARF debugging
14267 information is not associated with any particular routine, so it's
14268 necessary to remove references to the PIC label from RTL stored by
14269 the DWARF output code. */
14271 static rtx
14273 {
14275 /* addend is NULL or some rtx if x is something+GOTOFF where
14276 something doesn't include the PIC register. */
14278 /* reg_addend is NULL or a multiple of some register. */
14280 /* const_addend is NULL or a const_int. */
14282 /* This is the result, or NULL. */
14291 {
14298 {
14304 }
14311 {
14314 {
14319 }
14321 }
14326 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14327 and -mcmodel=medium -fpic. */
14328 }
14335 /* %ebx + GOT/GOTOFF */
14336 ;
14338 {
14339 /* %ebx + %reg * scale + GOT/GOTOFF */
14345 else
14346 {
14349 }
14350 }
14351 else
14357 {
14360 }
14381 {
14382 /* If the rest of original X doesn't involve the PIC register, add
14383 addend and subtract pic_offset_table_rtx. This can happen e.g.
14384 for code like:
14385 leal (%ebx, %ecx, 4), %ecx
14386 ...
14387 movl foo@GOTOFF(%ecx), %edx
14388 in which case we return (%ecx - %ebx) + foo. */
14391 pic_offset_table_rtx),
14392 result);
14393 else
14395 }
14397 {
14401 }
14403 }
14405 /* If X is a machine specific address (i.e. a symbol or label being
14406 referenced as a displacement from the GOT implemented using an
14407 UNSPEC), then return the base term. Otherwise return X. */
14409 rtx
14411 {
14412 rtx term;
14415 {
14429 }
14432 }
14433 \f
14434 static void
14437 {
14441 {
14444 }
14449 {
14452 {
14471 }
14475 {
14494 }
14501 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14502 Those same assemblers have the same but opposite lossage on cmov. */
14505 else
14510 {
14523 }
14530 else
14535 {
14548 }
14555 else
14565 else
14576 }
14578 }
14580 /* Print the name of register X to FILE based on its machine mode and number.
14581 If CODE is 'w', pretend the mode is HImode.
14582 If CODE is 'b', pretend the mode is QImode.
14583 If CODE is 'k', pretend the mode is SImode.
14584 If CODE is 'q', pretend the mode is DImode.
14585 If CODE is 'x', pretend the mode is V4SFmode.
14586 If CODE is 't', pretend the mode is V8SFmode.
14587 If CODE is 'g', pretend the mode is V16SFmode.
14588 If CODE is 'h', pretend the reg is the 'high' byte register.
14589 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14590 If CODE is 'd', duplicate the operand for AVX instruction.
14591 */
14593 void
14595 {
14604 {
14608 }
14635 else
14638 /* Irritatingly, AMD extended registers use different naming convention
14639 from the normal registers: "r%d[bwd]" */
14641 {
14646 {
14660 /* no suffix */
14665 }
14667 }
14671 {
14674 {
14677 }
14678 /* FALLTHRU */
14684 /* FALLTHRU */
14687 normal:
14702 {
14707 }
14710 {
14715 }
14719 }
14723 {
14726 else
14728 }
14729 }
14731 /* Locate some local-dynamic symbol still in use by this function
14732 so that we can print its name in some tls_local_dynamic_base
14733 pattern. */
14735 static int
14737 {
14742 {
14745 }
14748 }
14752 {
14753 rtx insn;
14764 }
14766 /* Meaning of CODE:
14767 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14768 C -- print opcode suffix for set/cmov insn.
14769 c -- like C, but print reversed condition
14770 F,f -- likewise, but for floating-point.
14771 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14772 otherwise nothing
14773 R -- print embeded rounding and sae.
14774 r -- print only sae.
14775 z -- print the opcode suffix for the size of the current operand.
14776 Z -- likewise, with special suffixes for x87 instructions.
14777 * -- print a star (in certain assembler syntax)
14778 A -- print an absolute memory reference.
14779 E -- print address with DImode register names if TARGET_64BIT.
14780 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14781 s -- print a shift double count, followed by the assemblers argument
14782 delimiter.
14783 b -- print the QImode name of the register for the indicated operand.
14784 %b0 would print %al if operands[0] is reg 0.
14785 w -- likewise, print the HImode name of the register.
14786 k -- likewise, print the SImode name of the register.
14787 q -- likewise, print the DImode name of the register.
14788 x -- likewise, print the V4SFmode name of the register.
14789 t -- likewise, print the V8SFmode name of the register.
14790 g -- likewise, print the V16SFmode name of the register.
14791 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14792 y -- print "st(0)" instead of "st" as a register.
14793 d -- print duplicated register operand for AVX instruction.
14794 D -- print condition for SSE cmp instruction.
14795 P -- if PIC, print an @PLT suffix.
14796 p -- print raw symbol name.
14797 X -- don't print any sort of PIC '@' suffix for a symbol.
14798 & -- print some in-use local-dynamic symbol name.
14799 H -- print a memory address offset by 8; used for sse high-parts
14800 Y -- print condition for XOP pcom* instruction.
14801 + -- print a branch hint as 'cs' or 'ds' prefix
14802 ; -- print a semicolon (after prefixes due to bug in older gas).
14803 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14804 @ -- print a segment register of thread base pointer load
14805 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14806 */
14808 void
14810 {
14812 {
14814 {
14817 {
14823 /* Intel syntax. For absolute addresses, registers should not
14824 be surrounded by braces. */
14826 {
14831 }
14836 }
14842 /* Wrap address in an UNSPEC to declare special handling. */
14880 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14885 {
14899 output_operand_lossage
14902 }
14905 #endif
14910 {
14911 /* Opcodes don't get size suffixes if using Intel opcodes. */
14916 {
14934 output_operand_lossage
14937 }
14938 }
14941 warning
14943 /* FALLTHRU */
14946 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14951 {
14953 {
14955 #ifdef HAVE_AS_IX86_FILDS
14957 #endif
14965 #ifdef HAVE_AS_IX86_FILDQ
14967 #else
14969 #endif
14974 }
14975 }
14977 {
14978 /* 387 opcodes don't get size suffixes
14979 if the operands are registers. */
14984 {
15000 }
15001 }
15002 else
15003 {
15004 output_operand_lossage
15007 }
15009 output_operand_lossage
15030 {
15033 }
15038 {
15089 }
15093 /* Little bit of braindamage here. The SSE compare instructions
15094 does use completely different names for the comparisons that the
15095 fp conditional moves. */
15097 {
15100 {
15103 }
15109 {
15112 }
15118 {
15121 }
15130 {
15133 }
15139 {
15142 }
15148 {
15151 }
15162 }
15167 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15170 #endif
15175 {
15179 }
15183 file);
15188 {
15192 }
15193 /* It doesn't actually matter what mode we use here, as we're
15194 only going to use this for printing. */
15196 /* Output 'qword ptr' for intel assembler dialect. */
15205 #ifdef HAVE_AS_IX86_HLE
15207 #else
15209 #endif
15211 #ifdef HAVE_AS_IX86_HLE
15213 #else
15215 #endif
15216 /* We do not want to print value of the operand. */
15245 {
15260 }
15273 {
15278 else
15281 }
15284 {
15285 rtx x;
15294 {
15299 {
15301 bool cputaken
15304 /* Emit hints only in the case default branch prediction
15305 heuristics would fail. */
15307 {
15308 /* We use 3e (DS) prefix for taken branches and
15309 2e (CS) prefix for not taken branches. */
15312 else
15314 }
15315 }
15316 }
15318 }
15321 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15323 #endif
15330 /* The kernel uses a different segment register for performance
15331 reasons; a system call would not have to trash the userspace
15332 segment register, which would be expensive. */
15335 else
15350 }
15351 }
15357 {
15358 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15361 {
15364 {
15373 else
15380 }
15382 /* Check for explicit size override (codes 'b', 'w', 'k',
15383 'q' and 'x') */
15397 }
15400 /* Avoid (%rip) for call operands. */
15406 else
15408 }
15411 {
15412 REAL_VALUE_TYPE r;
15420 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15424 else
15426 }
15429 {
15430 REAL_VALUE_TYPE r;
15439 }
15441 /* These float cases don't actually occur as immediate operands. */
15443 {
15448 }
15450 else
15451 {
15452 /* We have patterns that allow zero sets of memory, for instance.
15453 In 64-bit mode, we should probably support all 8-byte vectors,
15454 since we can in fact encode that into an immediate. */
15456 {
15459 }
15462 {
15464 {
15467 }
15470 {
15473 else
15475 }
15476 }
15481 else
15483 }
15484 }
15486 static bool
15488 {
15491 }
15492 \f
15493 /* Print a memory operand whose address is ADDR. */
15495 static void
15497 {
15506 {
15513 }
15515 {
15519 }
15520 else
15531 {
15542 }
15544 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15546 {
15558 }
15560 {
15561 /* Displacement only requires special attention. */
15564 {
15568 }
15571 else
15573 }
15574 else
15575 {
15576 /* Print SImode register names to force addr32 prefix. */
15578 {
15579 #ifdef ENABLE_CHECKING
15582 {
15593 }
15594 #endif
15597 }
15599 && TARGET_X32
15600 && disp
15603 {
15604 /* X32 runs in 64-bit mode, where displacement, DISP, in
15605 address DISP(%r64), is encoded as 32-bit immediate sign-
15606 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15607 address is %r64 + 0xffffffffbffffd00. When %r64 <
15608 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15609 which is invalid for x32. The correct address is %r64
15610 - 0x40000300 == 0xf7ffdd64. To properly encode
15611 -0x40000300(%r64) for x32, we zero-extend negative
15612 displacement by forcing addr32 prefix which truncates
15613 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15614 zero-extend all negative displacements, including -1(%rsp).
15615 However, for small negative displacements, sign-extension
15616 won't cause overflow. We only zero-extend negative
15617 displacements if they < -16*1024*1024, which is also used
15618 to check legitimate address displacements for PIC. */
15620 }
15623 {
15625 {
15630 else
15632 }
15638 {
15643 }
15645 }
15646 else
15647 {
15651 {
15652 /* Pull out the offset of a symbol; print any symbol itself. */
15656 {
15660 }
15668 else
15670 }
15674 {
15677 {
15681 }
15682 }
15685 else
15689 {
15694 }
15696 }
15697 }
15698 }
15700 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15702 static bool
15704 {
15705 rtx op;
15712 {
15715 /* FIXME: This might be @TPOFF in Sun ld. */
15726 else
15738 else
15745 #if TARGET_MACHO
15751 #endif
15754 {
15759 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15761 #else
15763 #endif
15766 }
15771 }
15774 }
15775 \f
15776 /* Split one or more double-mode RTL references into pairs of half-mode
15777 references. The RTL can be REG, offsettable MEM, integer constant, or
15778 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15779 split and "num" is its length. lo_half and hi_half are output arrays
15780 that parallel "operands". */
15782 void
15785 {
15790 {
15799 }
15804 {
15807 /* simplify_subreg refuse to split volatile memory addresses,
15808 but we still have to handle it. */
15810 {
15813 }
15814 else
15815 {
15822 }
15823 }
15824 }
15825 \f
15826 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15827 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15828 is the expression of the binary operation. The output may either be
15829 emitted here, or returned to the caller, like all output_* functions.
15831 There is no guarantee that the operands are the same mode, as they
15832 might be within FLOAT or FLOAT_EXTEND expressions. */
15834 #ifndef SYSV386_COMPAT
15835 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15836 wants to fix the assemblers because that causes incompatibility
15837 with gcc. No-one wants to fix gcc because that causes
15838 incompatibility with assemblers... You can use the option of
15839 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15840 #define SYSV386_COMPAT 1
15841 #endif
15845 {
15851 #ifdef ENABLE_CHECKING
15852 /* Even if we do not want to check the inputs, this documents input
15853 constraints. Which helps in understanding the following code. */
15863 else
15865 #endif
15868 {
15873 else
15882 else
15891 else
15900 else
15907 }
15910 {
15912 {
15916 else
15918 }
15919 else
15920 {
15924 else
15926 }
15928 }
15932 {
15936 {
15940 }
15942 /* know operands[0] == operands[1]. */
15945 {
15948 }
15951 {
15953 /* How is it that we are storing to a dead operand[2]?
15954 Well, presumably operands[1] is dead too. We can't
15955 store the result to st(0) as st(0) gets popped on this
15956 instruction. Instead store to operands[2] (which I
15957 think has to be st(1)). st(1) will be popped later.
15958 gcc <= 2.8.1 didn't have this check and generated
15959 assembly code that the Unixware assembler rejected. */
15961 else
15964 }
15968 else
15975 {
15978 }
15981 {
15984 }
15987 {
15988 #if SYSV386_COMPAT
15989 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15990 derived assemblers, confusingly reverse the direction of
15991 the operation for fsub{r} and fdiv{r} when the
15992 destination register is not st(0). The Intel assembler
15993 doesn't have this brain damage. Read !SYSV386_COMPAT to
15994 figure out what the hardware really does. */
15997 else
15999 #else
16001 /* As above for fmul/fadd, we can't store to st(0). */
16003 else
16005 #endif
16007 }
16010 {
16011 #if SYSV386_COMPAT
16014 else
16016 #else
16019 else
16021 #endif
16023 }
16026 {
16029 else
16032 }
16034 {
16035 #if SYSV386_COMPAT
16037 #else
16039 #endif
16040 }
16041 else
16042 {
16043 #if SYSV386_COMPAT
16045 #else
16047 #endif
16048 }
16053 }
16057 }
16059 /* Check if a 256bit AVX register is referenced inside of EXP. */
16061 static int
16063 {
16074 }
16076 /* Return needed mode for entity in optimize_mode_switching pass. */
16078 static int
16080 {
16082 {
16083 rtx link;
16085 /* Needed mode is set to AVX_U128_CLEAN if there are
16086 no 256bit modes used in function arguments. */
16088 link;
16090 {
16092 {
16097 }
16098 }
16101 }
16103 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16104 changes state only when a 256bit register is written to, but we need
16105 to prevent the compiler from moving optimal insertion point above
16106 eventual read from 256bit register. */
16111 }
16113 /* Return mode that i387 must be switched into
16114 prior to the execution of insn. */
16116 static int
16118 {
16121 /* The mode UNINITIALIZED is used to store control word after a
16122 function call or ASM pattern. The mode ANY specify that function
16123 has no requirements on the control word and make no changes in the
16124 bits we are interested in. */
16138 {
16161 }
16164 }
16166 /* Return mode that entity must be switched into
16167 prior to the execution of insn. */
16169 static int
16171 {
16173 {
16183 }
16185 }
16187 /* Check if a 256bit AVX register is referenced in stores. */
16189 static void
16191 {
16193 {
16196 }
16197 }
16199 /* Calculate mode of upper 128bit AVX registers after the insn. */
16201 static int
16203 {
16210 /* We know that state is clean after CALL insn if there are no
16211 256bit registers used in the function return register. */
16213 {
16218 }
16220 /* Otherwise, return current mode. Remember that if insn
16221 references AVX 256bit registers, the mode was already changed
16222 to DIRTY from MODE_NEEDED. */
16224 }
16226 /* Return the mode that an insn results in. */
16228 int
16230 {
16232 {
16242 }
16243 }
16245 static int
16247 {
16248 tree arg;
16250 /* Entry mode is set to AVX_U128_DIRTY if there are
16251 256bit modes used in function arguments. */
16254 {
16259 }
16262 }
16264 /* Return a mode that ENTITY is assumed to be
16265 switched to at function entry. */
16267 static int
16269 {
16271 {
16281 }
16282 }
16284 static int
16286 {
16289 /* Exit mode is set to AVX_U128_DIRTY if there are
16290 256bit modes used in the function return register. */
16295 }
16297 /* Return a mode that ENTITY is assumed to be
16298 switched to at function exit. */
16300 static int
16302 {
16304 {
16314 }
16315 }
16317 static int
16319 {
16321 }
16323 /* Output code to initialize control word copies used by trunc?f?i and
16324 rounding patterns. CURRENT_MODE is set to current control word,
16325 while NEW_MODE is set to new control word. */
16327 static void
16329 {
16331 rtx new_mode;
16342 {
16344 {
16346 /* round toward zero (truncate) */
16352 /* round down toward -oo */
16359 /* round up toward +oo */
16366 /* mask precision exception for nearbyint() */
16373 }
16374 }
16375 else
16376 {
16378 {
16380 /* round toward zero (truncate) */
16386 /* round down toward -oo */
16392 /* round up toward +oo */
16398 /* mask precision exception for nearbyint() */
16405 }
16406 }
16412 }
16414 /* Emit vzeroupper. */
16416 void
16418 {
16421 /* Cancel automatic vzeroupper insertion if there are
16422 live call-saved SSE registers at the insertion point. */
16434 }
16436 /* Generate one or more insns to set ENTITY to MODE. */
16438 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16439 is the set of hard registers live at the point where the insn(s)
16440 are to be inserted. */
16442 static void
16444 {
16446 {
16461 }
16462 }
16464 /* Output code for INSN to convert a float to a signed int. OPERANDS
16465 are the insn operands. The output may be [HSD]Imode and the input
16466 operand may be [SDX]Fmode. */
16470 {
16475 /* Jump through a hoop or two for DImode, since the hardware has no
16476 non-popping instruction. We used to do this a different way, but
16477 that was somewhat fragile and broke with post-reload splitters. */
16487 else
16488 {
16493 else
16497 }
16500 }
16502 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16503 have the values zero or one, indicates the ffreep insn's operand
16504 from the OPERANDS array. */
16508 {
16510 #ifdef HAVE_AS_IX86_FFREEP
16512 #else
16513 {
16523 }
16524 #endif
16527 }
16530 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16531 should be used. UNORDERED_P is true when fucom should be used. */
16535 {
16541 {
16544 }
16545 else
16546 {
16549 }
16552 {
16556 else
16558 else
16561 else
16563 }
16570 {
16572 {
16575 }
16576 else
16578 }
16581 && stack_top_dies
16584 {
16585 /* If both the top of the 387 stack dies, and the other operand
16586 is also a stack register that dies, then this must be a
16587 `fcompp' float compare */
16590 {
16591 /* There is no double popping fcomi variant. Fortunately,
16592 eflags is immune from the fstp's cc clobbering. */
16595 else
16598 }
16599 else
16600 {
16603 else
16605 }
16606 }
16607 else
16608 {
16609 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16612 {
16620 NULL,
16621 NULL,
16628 NULL,
16629 NULL,
16630 NULL,
16631 NULL
16632 };
16647 }
16648 }
16650 void
16652 {
16655 #ifdef ASM_QUAD
16658 #else
16660 #endif
16663 }
16665 void
16667 {
16670 #ifdef ASM_QUAD
16673 #else
16675 #endif
16676 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16682 #if TARGET_MACHO
16684 {
16688 }
16689 #endif
16690 else
16693 }
16694 \f
16695 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16696 for the target. */
16698 void
16700 {
16701 rtx tmp;
16703 /* We play register width games, which are only valid after reload. */
16706 /* Avoid HImode and its attendant prefix byte. */
16712 {
16715 }
16718 }
16720 /* X is an unchanging MEM. If it is a constant pool reference, return
16721 the constant pool rtx, else NULL. */
16723 rtx
16725 {
16732 }
16734 void
16736 {
16744 {
16745 rtx tmp;
16749 {
16755 }
16758 }
16762 {
16765 rtx tmp;
16770 else
16774 {
16781 }
16782 }
16786 {
16788 {
16789 #if TARGET_MACHO
16790 /* dynamic-no-pic */
16792 {
16793 rtx temp = ((reload_in_progress
16801 }
16803 {
16807 }
16810 else
16811 {
16819 }
16820 /* dynamic-no-pic */
16821 #endif
16822 }
16823 else
16824 {
16828 {
16834 }
16835 }
16836 }
16837 else
16838 {
16849 /* Force large constants in 64bit compilation into register
16850 to get them CSEed. */
16862 {
16863 /* If we are loading a floating point constant to a register,
16864 force the value to memory now, since we'll get better code
16865 out the back end. */
16869 {
16874 }
16875 }
16876 }
16879 }
16881 void
16883 {
16890 /* Force constants other than zero into memory. We do not know how
16891 the instructions used to build constants modify the upper 64 bits
16892 of the register, once we have that information we may be able
16893 to handle some of them more efficiently. */
16902 /* We need to check memory alignment for SSE mode since attribute
16903 can make operands unaligned. */
16908 {
16911 /* ix86_expand_vector_move_misalign() does not like constants ... */
16917 /* ... nor both arguments in memory. */
16925 }
16927 /* Make operand1 a register if it isn't already. */
16931 {
16934 }
16937 }
16939 /* Split 32-byte AVX unaligned load and store if needed. */
16941 static void
16943 {
16944 rtx m;
16951 {
16972 }
16975 {
16977 {
16984 }
16985 /* Normal *mov<mode>_internal pattern will handle
16986 unaligned loads just fine if misaligned_operand
16987 is true, and without the UNSPEC it can be combined
16988 with arithmetic instructions. */
16991 else
16993 }
16995 {
16997 {
17002 }
17003 else
17005 }
17006 else
17008 }
17010 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17011 straight to ix86_expand_vector_move. */
17012 /* Code generation for scalar reg-reg moves of single and double precision data:
17013 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17014 movaps reg, reg
17015 else
17016 movss reg, reg
17017 if (x86_sse_partial_reg_dependency == true)
17018 movapd reg, reg
17019 else
17020 movsd reg, reg
17022 Code generation for scalar loads of double precision data:
17023 if (x86_sse_split_regs == true)
17024 movlpd mem, reg (gas syntax)
17025 else
17026 movsd mem, reg
17028 Code generation for unaligned packed loads of single precision data
17029 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17030 if (x86_sse_unaligned_move_optimal)
17031 movups mem, reg
17033 if (x86_sse_partial_reg_dependency == true)
17034 {
17035 xorps reg, reg
17036 movlps mem, reg
17037 movhps mem+8, reg
17038 }
17039 else
17040 {
17041 movlps mem, reg
17042 movhps mem+8, reg
17043 }
17045 Code generation for unaligned packed loads of double precision data
17046 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17047 if (x86_sse_unaligned_move_optimal)
17048 movupd mem, reg
17050 if (x86_sse_split_regs == true)
17051 {
17052 movlpd mem, reg
17053 movhpd mem+8, reg
17054 }
17055 else
17056 {
17057 movsd mem, reg
17058 movhpd mem+8, reg
17059 }
17060 */
17062 void
17064 {
17073 {
17075 {
17079 {
17081 {
17084 }
17085 else
17087 }
17089 /* FALLTHRU */
17093 {
17108 }
17114 else
17122 }
17125 }
17129 {
17131 {
17135 {
17137 {
17140 }
17141 else
17143 }
17145 /* FALLTHRU */
17155 }
17158 }
17161 {
17162 /* Normal *mov<mode>_internal pattern will handle
17163 unaligned loads just fine if misaligned_operand
17164 is true, and without the UNSPEC it can be combined
17165 with arithmetic instructions. */
17171 /* ??? If we have typed data, then it would appear that using
17172 movdqu is the only way to get unaligned data loaded with
17173 integer type. */
17175 {
17177 {
17180 }
17182 /* We will eventually emit movups based on insn attributes. */
17186 }
17188 {
17189 rtx zero;
17192 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17193 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17195 {
17196 /* We will eventually emit movups based on insn attributes. */
17199 }
17201 /* When SSE registers are split into halves, we can avoid
17202 writing to the top half twice. */
17204 {
17207 }
17208 else
17209 {
17210 /* ??? Not sure about the best option for the Intel chips.
17211 The following would seem to satisfy; the register is
17212 entirely cleared, breaking the dependency chain. We
17213 then store to the upper half, with a dependency depth
17214 of one. A rumor has it that Intel recommends two movsd
17215 followed by an unpacklpd, but this is unconfirmed. And
17216 given that the dependency depth of the unpacklpd would
17217 still be one, I'm not sure why this would be better. */
17219 }
17225 }
17226 else
17227 {
17228 rtx t;
17231 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17232 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17234 {
17236 {
17239 }
17246 }
17250 else
17255 else
17264 }
17265 }
17267 {
17269 {
17272 /* We will eventually emit movups based on insn attributes. */
17274 }
17276 {
17278 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17279 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17281 /* We will eventually emit movups based on insn attributes. */
17283 else
17284 {
17289 }
17290 }
17291 else
17292 {
17297 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17298 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17300 {
17303 }
17304 else
17305 {
17310 }
17311 }
17312 }
17313 else
17315 }
17317 /* Helper function of ix86_fixup_binary_operands to canonicalize
17318 operand order. Returns true if the operands should be swapped. */
17320 static bool
17322 rtx operands[])
17323 {
17328 /* If the operation is not commutative, we can't do anything. */
17332 /* Highest priority is that src1 should match dst. */
17338 /* Next highest priority is that immediate constants come second. */
17344 /* Lowest priority is that memory references should come second. */
17351 }
17354 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17355 destination to use for the operation. If different from the true
17356 destination in operands[0], a copy operation will be required. */
17358 rtx
17360 rtx operands[])
17361 {
17366 /* Canonicalize operand order. */
17368 {
17369 rtx temp;
17371 /* It is invalid to swap operands of different modes. */
17377 }
17379 /* Both source operands cannot be in memory. */
17381 {
17382 /* Optimization: Only read from memory once. */
17384 {
17387 }
17390 else
17392 }
17394 /* If the destination is memory, and we do not have matching source
17395 operands, do things in registers. */
17399 /* Source 1 cannot be a constant. */
17403 /* Source 1 cannot be a non-matching memory. */
17407 /* Improve address combine. */
17416 }
17418 /* Similarly, but assume that the destination has already been
17419 set up properly. */
17421 void
17424 {
17427 }
17429 /* Attempt to expand a binary operator. Make the expansion closer to the
17430 actual machine, then just general_operand, which will allow 3 separate
17431 memory references (one output, two input) in a single insn. */
17433 void
17435 rtx operands[])
17436 {
17443 /* Emit the instruction. */
17447 {
17448 /* Reload doesn't know about the flags register, and doesn't know that
17449 it doesn't want to clobber it. We can only do this with PLUS. */
17452 }
17456 {
17457 /* This is going to be an LEA; avoid splitting it later. */
17459 }
17460 else
17461 {
17464 }
17466 /* Fix up the destination if needed. */
17469 }
17471 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17472 the given OPERANDS. */
17474 void
17476 rtx operands[])
17477 {
17480 {
17483 }
17485 {
17488 }
17489 /* Optimize (__m128i) d | (__m128i) e and similar code
17490 when d and e are float vectors into float vector logical
17491 insn. In C/C++ without using intrinsics there is no other way
17492 to express vector logical operation on float vectors than
17493 to cast them temporarily to integer vectors. */
17495 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17504 {
17505 rtx dst;
17507 {
17514 {
17517 }
17518 else
17519 {
17524 }
17535 }
17536 }
17545 }
17547 /* Return TRUE or FALSE depending on whether the binary operator meets the
17548 appropriate constraints. */
17550 bool
17553 {
17558 /* Both source operands cannot be in memory. */
17562 /* Canonicalize operand order for commutative operators. */
17564 {
17568 }
17570 /* If the destination is memory, we must have a matching source operand. */
17574 /* Source 1 cannot be a constant. */
17578 /* Source 1 cannot be a non-matching memory. */
17580 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17588 }
17590 /* Attempt to expand a unary operator. Make the expansion closer to the
17591 actual machine, then just general_operand, which will allow 2 separate
17592 memory references (one output, one input) in a single insn. */
17594 void
17596 rtx operands[])
17597 {
17604 /* If the destination is memory, and we do not have matching source
17605 operands, do things in registers. */
17608 {
17611 else
17613 }
17615 /* When source operand is memory, destination must match. */
17619 /* Emit the instruction. */
17623 {
17624 /* Reload doesn't know about the flags register, and doesn't know that
17625 it doesn't want to clobber it. */
17628 }
17629 else
17630 {
17633 }
17635 /* Fix up the destination if needed. */
17638 }
17640 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17641 divisor are within the range [0-255]. */
17643 void
17646 {
17655 {
17668 }
17675 /* Use 8bit unsigned divimod if dividend and divisor are within
17676 the range [0-255]. */
17685 pc_rtx);
17690 /* Generate original signed/unsigned divimod. */
17695 /* Branch to the end. */
17699 /* Generate 8bit unsigned divide. */
17701 /* Don't use operands[0] for result of 8bit divide since not all
17702 registers support QImode ZERO_EXTRACT. */
17709 {
17712 }
17713 else
17714 {
17717 }
17719 /* Extract remainder from AH. */
17723 else
17724 {
17725 /* Need a new scratch register since the old one has result
17726 of 8bit divide. */
17730 }
17733 /* Zero extend quotient from AL. */
17739 }
17741 /* Whether it is OK to emit CFI directives when emitting asm code. */
17743 bool
17745 {
17747 }
17749 #define LEA_MAX_STALL (3)
17750 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17752 /* Increase given DISTANCE in half-cycles according to
17753 dependencies between PREV and NEXT instructions.
17754 Add 1 half-cycle if there is no dependency and
17755 go to next cycle if there is some dependecy. */
17757 static unsigned int
17759 {
17776 }
17778 /* Function checks if instruction INSN defines register number
17779 REGNO1 or REGNO2. */
17781 static bool
17783 rtx insn)
17784 {
17792 {
17794 }
17797 }
17799 /* Function checks if instruction INSN uses register number
17800 REGNO as a part of address expression. */
17802 static bool
17804 {
17812 }
17814 /* Search backward for non-agu definition of register number REGNO1
17815 or register number REGNO2 in basic block starting from instruction
17816 START up to head of basic block or instruction INSN.
17818 Function puts true value into *FOUND var if definition was found
17819 and false otherwise.
17821 Distance in half-cycles between START and found instruction or head
17822 of BB is added to DISTANCE and returned. */
17824 static int
17828 {
17838 {
17840 {
17843 {
17846 {
17849 }
17850 }
17853 }
17858 }
17861 }
17863 /* Search backward for non-agu definition of register number REGNO1
17864 or register number REGNO2 in INSN's basic block until
17865 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17866 2. Reach neighbour BBs boundary, or
17867 3. Reach agu definition.
17868 Returns the distance between the non-agu definition point and INSN.
17869 If no definition point, returns -1. */
17871 static int
17873 rtx insn)
17874 {
17885 {
17886 edge e;
17887 edge_iterator ei;
17892 {
17895 }
17901 else
17902 {
17907 {
17908 int bb_dist
17914 {
17921 }
17922 }
17925 }
17926 }
17928 /* get_attr_type may modify recog data. We want to make sure
17929 that recog data is valid for instruction INSN, on which
17930 distance_non_agu_define is called. INSN is unchanged here. */
17937 }
17939 /* Return the distance in half-cycles between INSN and the next
17940 insn that uses register number REGNO in memory address added
17941 to DISTANCE. Return -1 if REGNO0 is set.
17943 Put true value into *FOUND if register usage was found and
17944 false otherwise.
17945 Put true value into *REDEFINED if register redefinition was
17946 found and false otherwise. */
17948 static int
17952 {
17961 {
17964 /* If insn and start belong to the same bb, set prev to insn,
17965 so the call to increase_distance will increase the distance
17966 between insns by 1. */
17968 }
17973 {
17975 {
17978 {
17979 /* Return DISTANCE if OP0 is used in memory
17980 address in NEXT. */
17983 }
17986 {
17987 /* Return -1 if OP0 is set in NEXT. */
17990 }
17993 }
17999 }
18002 }
18004 /* Return the distance between INSN and the next insn that uses
18005 register number REGNO0 in memory address. Return -1 if no such
18006 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18008 static int
18010 {
18022 {
18023 edge e;
18024 edge_iterator ei;
18029 {
18032 }
18038 else
18039 {
18045 {
18046 int bb_dist
18051 {
18058 }
18059 }
18062 }
18063 }
18069 }
18071 /* Define this macro to tune LEA priority vs ADD, it take effect when
18072 there is a dilemma of choicing LEA or ADD
18073 Negative value: ADD is more preferred than LEA
18074 Zero: Netrual
18075 Positive value: LEA is more preferred than ADD*/
18076 #define IX86_LEA_PRIORITY 0
18078 /* Return true if usage of lea INSN has performance advantage
18079 over a sequence of instructions. Instructions sequence has
18080 SPLIT_COST cycles higher latency than lea latency. */
18082 static bool
18085 {
18088 /* For Silvermont if using a 2-source or 3-source LEA for
18089 non-destructive destination purposes, or due to wanting
18090 ability to use SCALE, the use of LEA is justified. */
18092 {
18100 }
18106 {
18107 /* If there is no non AGU operand definition, no AGU
18108 operand usage and split cost is 0 then both lea
18109 and non lea variants have same priority. Currently
18110 we prefer lea for 64 bit code and non lea on 32 bit
18111 code. */
18114 else
18116 }
18118 /* With longer definitions distance lea is more preferable.
18119 Here we change it to take into account splitting cost and
18120 lea priority. */
18123 /* If there is no use in memory addess then we just check
18124 that split cost exceeds AGU stall. */
18128 /* If this insn has both backward non-agu dependence and forward
18129 agu dependence, the one with short distance takes effect. */
18131 }
18133 /* Return true if it is legal to clobber flags by INSN and
18134 false otherwise. */
18136 static bool
18138 {
18141 bitmap live;
18144 {
18146 {
18153 }
18159 }
18163 }
18165 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18166 move and add to avoid AGU stalls. */
18168 bool
18170 {
18173 /* Check if we need to optimize. */
18177 /* Check it is correct to split here. */
18185 /* We need to split only adds with non destructive
18186 destination operand. */
18189 else
18191 }
18193 /* Return true if we should emit lea instruction instead of mov
18194 instruction. */
18196 bool
18198 {
18201 /* Check if we need to optimize. */
18205 /* Use lea for reg to reg moves only. */
18213 }
18215 /* Return true if we need to split lea into a sequence of
18216 instructions to avoid AGU stalls. */
18218 bool
18220 {
18226 /* Check we need to optimize. */
18230 /* The "at least two components" test below might not catch simple
18231 move or zero extension insns if parts.base is non-NULL and parts.disp
18232 is const0_rtx as the only components in the address, e.g. if the
18233 register is %rbp or %r13. As this test is much cheaper and moves or
18234 zero extensions are the common case, do this check first. */
18240 /* Check if it is OK to split here. */
18247 /* There should be at least two components in the address. */
18252 /* We should not split into add if non legitimate pic
18253 operand is used as displacement. */
18268 /* Compute how many cycles we will add to execution time
18269 if split lea into a sequence of instructions. */
18271 {
18272 /* Have to use mov instruction if non desctructive
18273 destination form is used. */
18277 /* Have to add index to base if both exist. */
18281 /* Have to use shift and adds if scale is 2 or greater. */
18283 {
18288 else
18290 }
18292 /* Have to use add instruction with immediate if
18293 disp is non zero. */
18297 /* Subtract the price of lea. */
18299 }
18303 }
18305 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18306 matches destination. RTX includes clobber of FLAGS_REG. */
18308 static void
18311 {
18318 }
18320 /* Return true if regno1 def is nearest to the insn. */
18322 static bool
18324 {
18331 {
18333 {
18336 }
18342 }
18344 /* None of the regs is defined in the bb. */
18346 }
18348 /* Split lea instructions into a sequence of instructions
18349 which are executed on ALU to avoid AGU stalls.
18350 It is assumed that it is allowed to clobber flags register
18351 at lea position. */
18353 void
18355 {
18371 {
18374 }
18377 {
18380 }
18386 {
18387 /* Case r1 = r1 + ... */
18389 {
18390 /* If we have a case r1 = r1 + C * r2 then we
18391 should use multiplication which is very
18392 expensive. Assume cost model is wrong if we
18393 have such case here. */
18398 }
18399 else
18400 {
18401 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18405 /* Use shift for scaling. */
18414 }
18415 }
18417 {
18420 }
18421 else
18422 {
18424 {
18427 }
18429 {
18432 }
18433 else
18434 {
18439 else
18440 {
18441 rtx tmp1;
18443 /* Find better operand for SET instruction, depending
18444 on which definition is farther from the insn. */
18447 else
18457 }
18460 }
18464 }
18465 }
18467 /* Return true if it is ok to optimize an ADD operation to LEA
18468 operation to avoid flag register consumation. For most processors,
18469 ADD is faster than LEA. For the processors like BONNELL, if the
18470 destination register of LEA holds an actual address which will be
18471 used soon, LEA is better and otherwise ADD is better. */
18473 bool
18475 {
18480 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18488 }
18490 /* Return true if destination reg of SET_BODY is shift count of
18491 USE_BODY. */
18493 static bool
18495 {
18496 rtx set_dest;
18497 rtx shift_rtx;
18500 /* Retrieve destination of SET_BODY. */
18502 {
18511 use_body))
18516 }
18518 /* Retrieve shift count of USE_BODY. */
18520 {
18532 }
18540 {
18543 /* Return true if shift count is dest of SET_BODY. */
18545 {
18546 /* Add check since it can be invoked before register
18547 allocation in pre-reload schedule. */
18553 }
18554 }
18557 }
18559 /* Return true if destination reg of SET_INSN is shift count of
18560 USE_INSN. */
18562 bool
18564 {
18567 }
18569 /* Return TRUE or FALSE depending on whether the unary operator meets the
18570 appropriate constraints. */
18572 bool
18576 {
18577 /* If one of operands is memory, source and destination must match. */
18583 }
18585 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18586 are ok, keeping in mind the possible movddup alternative. */
18588 bool
18590 {
18596 }
18598 /* Post-reload splitter for converting an SF or DFmode value in an
18599 SSE register into an unsigned SImode. */
18601 void
18603 {
18614 /* Load up the value into the low element. We must ensure that the other
18615 elements are valid floats -- zero is the easiest such value. */
18617 {
18620 else
18622 }
18623 else
18624 {
18629 else
18631 }
18651 else
18656 }
18658 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18659 Expects the 64-bit DImode to be supplied in a pair of integral
18660 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18661 -mfpmath=sse, !optimize_size only. */
18663 void
18665 {
18669 rtx x;
18675 {
18678 }
18679 else
18680 {
18684 }
18692 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18695 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18696 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18697 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18698 (0x1.0p84 + double(fp_value_hi_xmm)).
18699 Note these exponents differ by 32. */
18703 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18704 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18713 /* Add the upper and lower DFmode values together. */
18716 else
18717 {
18721 }
18724 }
18726 /* Not used, but eases macroization of patterns. */
18727 void
18729 rtx input ATTRIBUTE_UNUSED)
18730 {
18732 }
18734 /* Convert an unsigned SImode value into a DFmode. Only currently used
18735 for SSE, but applicable anywhere. */
18737 void
18739 {
18740 REAL_VALUE_TYPE TWO31r;
18755 }
18757 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18758 32-bit mode; otherwise we have a direct convert instruction. */
18760 void
18762 {
18763 REAL_VALUE_TYPE TWO32r;
18781 }
18783 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18784 For x86_32, -mfpmath=sse, !optimize_size only. */
18785 void
18787 {
18788 REAL_VALUE_TYPE ONE16r;
18807 }
18809 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18810 a vector of unsigned ints VAL to vector of floats TARGET. */
18812 void
18814 {
18816 REAL_VALUE_TYPE TWO16r;
18823 else
18828 OPTAB_DIRECT);
18839 OPTAB_DIRECT);
18841 OPTAB_DIRECT);
18844 }
18846 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18847 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18848 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18849 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18851 rtx
18853 {
18854 REAL_VALUE_TYPE TWO31r;
18869 {
18875 }
18884 OPTAB_DIRECT);
18885 else
18886 {
18892 OPTAB_DIRECT);
18893 }
18896 }
18898 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18899 then replicate the value for all elements of the vector
18900 register. */
18902 rtx
18904 {
18906 rtvec v;
18910 {
18943 }
18944 }
18946 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18947 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18948 for an SSE register. If VECT is true, then replicate the mask for
18949 all elements of the vector register. If INVERT is true, then create
18950 a mask excluding the sign bit. */
18952 rtx
18954 {
18958 rtx v;
18959 rtx mask;
18961 /* Find the sign bit, sign extended to 2*HWI. */
18963 {
18987 else
18995 {
18998 }
18999 else
19000 {
19001 rtvec vec;
19007 {
19010 }
19011 else
19021 }
19026 }
19031 /* Force this value into the low part of a fp vector constant. */
19040 }
19042 /* Generate code for floating point ABS or NEG. */
19044 void
19046 rtx operands[])
19047 {
19058 {
19064 }
19066 /* NEG and ABS performed with SSE use bitwise mask operations.
19067 Create the appropriate mask now. */
19070 else
19080 {
19082 rtvec par;
19087 else
19088 {
19091 }
19093 }
19094 else
19096 }
19098 /* Expand a copysign operation. Special case operand 0 being a constant. */
19100 void
19102 {
19116 else
19120 {
19127 {
19130 else
19131 {
19135 }
19136 }
19146 else
19150 }
19151 else
19152 {
19162 else
19166 }
19167 }
19169 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19170 be a constant, and so has already been expanded into a vector constant. */
19172 void
19174 {
19190 {
19193 }
19194 }
19196 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19197 so we have to do two masks. */
19199 void
19201 {
19216 {
19217 /* Shouldn't happen often (it's useless, obviously), but when it does
19218 we'd generate incorrect code if we continue below. */
19221 }
19224 {
19235 }
19236 else
19237 {
19239 {
19241 }
19243 {
19247 }
19251 {
19254 }
19256 {
19261 }
19263 }
19267 }
19269 /* Return TRUE or FALSE depending on whether the first SET in INSN
19270 has source and destination with matching CC modes, and that the
19271 CC mode is at least as constrained as REQ_MODE. */
19273 bool
19275 {
19276 rtx set;
19287 {
19297 /* FALLTHRU */
19301 /* FALLTHRU */
19305 /* FALLTHRU */
19319 }
19322 }
19324 /* Generate insn patterns to do an integer compare of OPERANDS. */
19326 static rtx
19328 {
19335 /* This is very simple, but making the interface the same as in the
19336 FP case makes the rest of the code easier. */
19340 /* Return the test that should be put into the flags user, i.e.
19341 the bcc, scc, or cmov instruction. */
19343 }
19345 /* Figure out whether to use ordered or unordered fp comparisons.
19346 Return the appropriate mode to use. */
19348 enum machine_mode
19350 {
19351 /* ??? In order to make all comparisons reversible, we do all comparisons
19352 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19353 all forms trapping and nontrapping comparisons, we can make inequality
19354 comparisons trapping again, since it results in better code when using
19355 FCOM based compares. */
19357 }
19359 enum machine_mode
19361 {
19365 {
19368 }
19371 {
19372 /* Only zero flag is needed. */
19376 /* Codes needing carry flag. */
19379 /* Detect overflow checks. They need just the carry flag. */
19383 else
19388 /* Codes possibly doable only with sign flag when
19389 comparing against zero. */
19394 else
19395 /* For other cases Carry flag is not required. */
19397 /* Codes doable only with sign flag when comparing
19398 against zero, but we miss jump instruction for it
19399 so we need to use relational tests against overflow
19400 that thus needs to be zero. */
19405 else
19407 /* strcmp pattern do (use flags) and combine may ask us for proper
19408 mode. */
19413 }
19414 }
19416 /* Return the fixed registers used for condition codes. */
19418 static bool
19420 {
19424 }
19426 /* If two condition code modes are compatible, return a condition code
19427 mode which is compatible with both. Otherwise, return
19428 VOIDmode. */
19430 static enum machine_mode
19432 {
19449 {
19463 {
19477 }
19481 /* These are only compatible with themselves, which we already
19482 checked above. */
19484 }
19485 }
19488 /* Return a comparison we can do and that it is equivalent to
19489 swap_condition (code) apart possibly from orderedness.
19490 But, never change orderedness if TARGET_IEEE_FP, returning
19491 UNKNOWN in that case if necessary. */
19493 static enum rtx_code
19495 {
19497 {
19508 }
19509 }
19511 /* Return cost of comparison CODE using the best strategy for performance.
19512 All following functions do use number of instructions as a cost metrics.
19513 In future this should be tweaked to compute bytes for optimize_size and
19514 take into account performance of various instructions on various CPUs. */
19516 static int
19518 {
19521 /* The cost of code using bit-twiddling on %ah. */
19523 {
19546 }
19549 {
19556 }
19557 }
19559 /* Return strategy to use for floating-point. We assume that fcomi is always
19560 preferrable where available, since that is also true when looking at size
19561 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19563 enum ix86_fpcmp_strategy
19565 {
19566 /* Do fcomi/sahf based test when profitable. */
19575 }
19577 /* Swap, force into registers, or otherwise massage the two operands
19578 to a fp comparison. The operands are updated in place; the new
19579 comparison code is returned. */
19581 static enum rtx_code
19583 {
19589 /* All of the unordered compare instructions only work on registers.
19590 The same is true of the fcomi compare instructions. The XFmode
19591 compare instructions require registers except when comparing
19592 against zero or when converting operand 1 from fixed point to
19593 floating point. */
19602 {
19605 }
19606 else
19607 {
19608 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19609 things around if they appear profitable, otherwise force op0
19610 into a register. */
19616 {
19619 {
19620 rtx tmp;
19623 }
19624 }
19630 {
19635 {
19638 }
19639 else
19641 }
19642 }
19644 /* Try to rearrange the comparison to make it cheaper. */
19648 {
19649 rtx tmp;
19654 }
19659 }
19661 /* Convert comparison codes we use to represent FP comparison to integer
19662 code that will result in proper branch. Return UNKNOWN if no such code
19663 is available. */
19665 enum rtx_code
19667 {
19669 {
19692 }
19693 }
19695 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19697 static rtx
19699 {
19706 /* Do fcomi/sahf based test when profitable. */
19708 {
19713 tmp);
19721 tmp);
19730 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19737 /* In the unordered case, we have to check C2 for NaN's, which
19738 doesn't happen to work out to anything nice combination-wise.
19739 So do some bit twiddling on the value we've got in AH to come
19740 up with an appropriate set of condition codes. */
19744 {
19748 {
19751 }
19752 else
19753 {
19759 }
19764 {
19769 }
19770 else
19771 {
19774 }
19779 {
19782 }
19783 else
19784 {
19788 }
19793 {
19799 }
19800 else
19801 {
19804 }
19809 {
19814 }
19815 else
19816 {
19819 }
19824 {
19829 }
19830 else
19831 {
19834 }
19848 }
19853 }
19855 /* Return the test that should be put into the flags user, i.e.
19856 the bcc, scc, or cmov instruction. */
19859 const0_rtx);
19860 }
19862 static rtx
19864 {
19865 rtx ret;
19871 {
19874 }
19875 else
19879 }
19881 void
19883 {
19885 rtx tmp;
19888 {
19895 simple:
19899 pc_rtx);
19907 /* Expand DImode branch into multiple compare+branch. */
19908 {
19914 {
19917 }
19924 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19925 avoid two branches. This costs one extra insn, so disable when
19926 optimizing for size. */
19931 {
19949 }
19951 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19952 op1 is a constant and the low word is zero, then we can just
19953 examine the high word. Similarly for low word -1 and
19954 less-or-equal-than or greater-than. */
19958 {
19961 {
19964 }
19968 {
19971 }
19975 }
19977 /* Otherwise, we need two or three jumps. */
19986 {
20000 }
20002 /*
20003 * a < b =>
20004 * if (hi(a) < hi(b)) goto true;
20005 * if (hi(a) > hi(b)) goto false;
20006 * if (lo(a) < lo(b)) goto true;
20007 * false:
20008 */
20020 }
20025 }
20026 }
20028 /* Split branch based on floating point condition. */
20029 void
20032 {
20033 rtx condition;
20034 rtx i;
20037 {
20042 }
20045 tmp);
20053 }
20055 void
20057 {
20058 rtx ret;
20065 }
20067 /* Expand comparison setting or clearing carry flag. Return true when
20068 successful and set pop for the operation. */
20069 static bool
20071 {
20075 /* Do not handle double-mode compares that go through special path. */
20080 {
20085 /* Shortcut: following common codes never translate
20086 into carry flag compares. */
20091 /* These comparisons require zero flag; swap operands so they won't. */
20094 {
20099 }
20101 /* Try to expand the comparison and verify that we end up with
20102 carry flag based comparison. This fails to be true only when
20103 we decide to expand comparison using arithmetic that is not
20104 too common scenario. */
20113 else
20122 }
20128 {
20133 /* Convert a==0 into (unsigned)a<1. */
20142 /* Convert a>b into b<a or a>=b-1. */
20146 {
20148 /* Bail out on overflow. We still can swap operands but that
20149 would force loading of the constant into register. */
20154 }
20155 else
20156 {
20161 }
20164 /* Convert a>=0 into (unsigned)a<0x80000000. */
20182 }
20183 /* Swapping operands may cause constant to appear as first operand. */
20185 {
20189 }
20193 }
20195 bool
20197 {
20221 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20222 HImode insns, we'd be swallowed in word prefix ops. */
20228 {
20232 HOST_WIDE_INT diff;
20235 /* Sign bit compares are better done using shifts than we do by using
20236 sbb. */
20239 {
20240 /* Detect overlap between destination and compare sources. */
20244 {
20245 rtx flags;
20254 {
20256 compare_code
20258 }
20260 /* To simplify rest of code, restrict to the GEU case. */
20262 {
20268 }
20269 else
20270 {
20273 reverse_condition_maybe_unordered
20275 else
20278 }
20287 else
20290 }
20291 else
20292 {
20295 else
20296 {
20301 }
20303 }
20306 {
20307 /*
20308 * cmpl op0,op1
20309 * sbbl dest,dest
20310 * [addl dest, ct]
20311 *
20312 * Size 5 - 8.
20313 */
20318 }
20320 {
20321 /*
20322 * cmpl op0,op1
20323 * sbbl dest,dest
20324 * orl $ct, dest
20325 *
20326 * Size 8.
20327 */
20331 }
20333 {
20334 /*
20335 * cmpl op0,op1
20336 * sbbl dest,dest
20337 * notl dest
20338 * [addl dest, cf]
20339 *
20340 * Size 8 - 11.
20341 */
20347 }
20348 else
20349 {
20350 /*
20351 * cmpl op0,op1
20352 * sbbl dest,dest
20353 * [notl dest]
20354 * andl cf - ct, dest
20355 * [addl dest, ct]
20356 *
20357 * Size 8 - 11.
20358 */
20361 {
20365 }
20375 }
20381 }
20384 {
20387 HOST_WIDE_INT tmp;
20392 {
20395 /* We may be reversing unordered compare to normal compare, that
20396 is not valid in general (we may convert non-trapping condition
20397 to trapping one), however on i386 we currently emit all
20398 comparisons unordered. */
20401 }
20402 else
20403 {
20406 }
20407 }
20412 {
20417 {
20422 }
20423 }
20425 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20429 {
20430 /* If lea code below could be used, only optimize
20431 if it results in a 2 insn sequence. */
20437 {
20438 /*
20439 * notl op1 (if necessary)
20440 * sarl $31, op1
20441 * orl cf, op1
20442 */
20444 {
20448 }
20459 }
20460 }
20468 {
20469 /*
20470 * xorl dest,dest
20471 * cmpl op1,op2
20472 * setcc dest
20473 * lea cf(dest*(ct-cf)),dest
20474 *
20475 * Size 14.
20476 *
20477 * This also catches the degenerate setcc-only case.
20478 */
20480 rtx tmp;
20486 /* On x86_64 the lea instruction operates on Pmode, so we need
20487 to get arithmetics done in proper mode to match. */
20490 else
20491 {
20492 rtx out1;
20495 nops++;
20497 {
20499 nops++;
20500 }
20501 }
20503 {
20505 nops++;
20506 }
20508 {
20511 else
20513 }
20518 }
20520 /*
20521 * General case: Jumpful:
20522 * xorl dest,dest cmpl op1, op2
20523 * cmpl op1, op2 movl ct, dest
20524 * setcc dest jcc 1f
20525 * decl dest movl cf, dest
20526 * andl (cf-ct),dest 1:
20527 * addl ct,dest
20528 *
20529 * Size 20. Size 14.
20530 *
20531 * This is reasonably steep, but branch mispredict costs are
20532 * high on modern cpus, so consider failing only if optimizing
20533 * for space.
20534 */
20539 {
20541 {
20548 {
20551 /* We may be reversing unordered compare to normal compare,
20552 that is not valid in general (we may convert non-trapping
20553 condition to trapping one), however on i386 we currently
20554 emit all comparisons unordered. */
20556 }
20557 else
20558 {
20562 }
20563 }
20566 {
20567 /* notl op1 (if needed)
20568 sarl $31, op1
20569 andl (cf-ct), op1
20570 addl ct, op1
20572 For x < 0 (resp. x <= -1) there will be no notl,
20573 so if possible swap the constants to get rid of the
20574 complement.
20575 True/false will be -1/0 while code below (store flag
20576 followed by decrement) is 0/-1, so the constants need
20577 to be exchanged once more. */
20580 {
20583 }
20584 else
20585 {
20589 }
20592 }
20593 else
20594 {
20598 constm1_rtx,
20600 }
20612 }
20613 }
20616 {
20617 /* Try a few things more with specific constants and a variable. */
20619 optab op;
20625 /* If one of the two operands is an interesting constant, load a
20626 constant with the above and mask it in with a logical operation. */
20629 {
20635 else
20637 }
20639 {
20645 else
20647 }
20648 else
20655 /* Recurse to get the constant loaded. */
20659 /* Mask in the interesting variable. */
20661 OPTAB_WIDEN);
20666 }
20668 /*
20669 * For comparison with above,
20670 *
20671 * movl cf,dest
20672 * movl ct,tmp
20673 * cmpl op1,op2
20674 * cmovcc tmp,dest
20675 *
20676 * Size 15.
20677 */
20699 }
20701 /* Swap, force into registers, or otherwise massage the two operands
20702 to an sse comparison with a mask result. Thus we differ a bit from
20703 ix86_prepare_fp_compare_args which expects to produce a flags result.
20705 The DEST operand exists to help determine whether to commute commutative
20706 operators. The POP0/POP1 operands are updated in place. The new
20707 comparison code is returned, or UNKNOWN if not implementable. */
20709 static enum rtx_code
20712 {
20713 rtx tmp;
20716 {
20719 /* AVX supports all the needed comparisons. */
20722 /* We have no LTGT as an operator. We could implement it with
20723 NE & ORDERED, but this requires an extra temporary. It's
20724 not clear that it's worth it. */
20731 /* These are supported directly. */
20738 /* AVX has 3 operand comparisons, no need to swap anything. */
20741 /* For commutative operators, try to canonicalize the destination
20742 operand to be first in the comparison - this helps reload to
20743 avoid extra moves. */
20746 /* FALLTHRU */
20752 /* These are not supported directly before AVX, and furthermore
20753 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20754 comparison operands to transform into something that is
20755 supported. */
20764 }
20767 }
20769 /* Detect conditional moves that exactly match min/max operational
20770 semantics. Note that this is IEEE safe, as long as we don't
20771 interchange the operands.
20773 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20774 and TRUE if the operation is successful and instructions are emitted. */
20776 static bool
20779 {
20782 rtx tmp;
20785 ;
20787 {
20791 }
20792 else
20799 else
20804 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20805 but MODE may be a vector mode and thus not appropriate. */
20807 {
20809 rtvec v;
20814 }
20815 else
20816 {
20819 }
20823 }
20825 /* Expand an sse vector comparison. Return the register with the result. */
20827 static rtx
20830 {
20834 /* In general case result of comparison can differ from operands' type. */
20837 /* In AVX512F the result of comparison is an integer mask. */
20839 rtx x;
20842 {
20847 }
20848 else
20861 /* Compare patterns for int modes are unspec in AVX512F only. */
20863 {
20867 {
20876 }
20879 {
20882 }
20883 }
20887 {
20890 }
20891 else
20895 }
20897 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20898 operations. This is used for both scalar and vector conditional moves. */
20900 static void
20902 {
20906 /* In AVX512F the result of comparison is an integer mask. */
20914 {
20916 }
20919 {
20923 }
20926 {
20931 }
20934 {
20938 }
20941 {
20949 op_true,
20950 op_false)));
20951 }
20952 else
20953 {
20963 {
20977 {
20984 }
20999 {
21006 }
21024 }
21027 {
21031 }
21032 else
21033 {
21039 else
21051 }
21052 }
21053 }
21055 /* Expand a floating-point conditional move. Return true if successful. */
21057 bool
21059 {
21067 {
21070 /* Since we've no cmove for sse registers, don't force bad register
21071 allocation just to gain access to it. Deny movcc when the
21072 comparison mode doesn't match the move mode. */
21091 }
21098 /* The floating point conditional move instructions don't directly
21099 support conditions resulting from a signed integer comparison. */
21103 {
21108 }
21115 }
21117 /* Expand a floating-point vector conditional move; a vcond operation
21118 rather than a movcc operation. */
21120 bool
21122 {
21124 rtx cmp;
21129 {
21130 rtx temp;
21132 {
21149 }
21151 OPTAB_DIRECT);
21154 }
21164 }
21166 /* Expand a signed/unsigned integral vector conditional move. */
21168 bool
21170 {
21180 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21181 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21190 {
21194 {
21200 }
21203 {
21209 }
21210 }
21219 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21223 ;
21224 else
21225 {
21226 /* Canonicalize the comparison to EQ, GT, GTU. */
21228 {
21245 /* FALLTHRU */
21255 }
21257 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21259 {
21261 {
21263 /* SSE4.1 supports EQ. */
21270 /* SSE4.2 supports GT/GTU. */
21277 }
21278 }
21280 /* Unsigned parallel compare is not supported by the hardware.
21281 Play some tricks to turn this into a signed comparison
21282 against 0. */
21284 {
21288 {
21295 {
21300 {
21309 }
21310 /* Subtract (-(INT MAX) - 1) from both operands to make
21311 them signed. */
21322 }
21329 /* Perform a parallel unsigned saturating subtraction. */
21342 }
21343 }
21344 }
21346 /* Allow the comparison to be done in one mode, but the movcc to
21347 happen in another mode. */
21349 {
21352 }
21353 else
21354 {
21360 }
21365 }
21367 static bool
21369 {
21372 {
21376 op1));
21381 op1));
21393 }
21394 }
21396 /* Expand a variable vector permutation. */
21398 void
21400 {
21411 /* Number of elements in the vector. */
21420 {
21422 {
21423 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21424 an constant shuffle operand. With a tiny bit of effort we can
21425 use VPERMD instead. A re-interpretation stall for V4DFmode is
21426 unfortunate but there's no avoiding it.
21427 Similarly for V16HImode we don't have instructions for variable
21428 shuffling, while for V32QImode we can use after preparing suitable
21429 masks vpshufb; vpshufb; vpermq; vpor. */
21432 {
21436 }
21437 else
21438 {
21442 }
21445 /* Replicate the low bits of the V4DImode mask into V8SImode:
21446 mask = { A B C D }
21447 t1 = { A A B B C C D D }. */
21455 else
21458 /* Multiply the shuffle indicies by two. */
21460 OPTAB_DIRECT);
21462 /* Add one to the odd shuffle indicies:
21463 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21465 {
21468 }
21472 OPTAB_DIRECT);
21474 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21479 }
21482 {
21484 /* The VPERMD and VPERMPS instructions already properly ignore
21485 the high bits of the shuffle elements. No need for us to
21486 perform an AND ourselves. */
21488 {
21493 }
21494 else
21495 {
21501 }
21508 else
21509 {
21515 }
21519 /* By combining the two 128-bit input vectors into one 256-bit
21520 input vector, we can use VPERMD and VPERMPS for the full
21521 two-operand shuffle. */
21553 /* From mask create two adjusted masks, which contain the same
21554 bits as mask in the low 7 bits of each vector element.
21555 The first mask will have the most significant bit clear
21556 if it requests element from the same 128-bit lane
21557 and MSB set if it requests element from the other 128-bit lane.
21558 The second mask will have the opposite values of the MSB,
21559 and additionally will have its 128-bit lanes swapped.
21560 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21561 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21562 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21563 stands for other 12 bytes. */
21564 /* The bit whether element is from the same lane or the other
21565 lane is bit 4, so shift it up by 3 to the MSB position. */
21569 /* Clear MSB bits from the mask just in case it had them set. */
21571 /* After this t1 will have MSB set for elements from other lane. */
21573 /* Clear bits other than MSB. */
21575 /* Or in the lower bits from mask into t3. */
21577 /* And invert MSB bits in t1, so MSB is set for elements from the same
21578 lane. */
21580 /* Swap 128-bit lanes in t3. */
21585 /* And or in the lower bits from mask into t1. */
21588 {
21589 /* Each of these shuffles will put 0s in places where
21590 element from the other 128-bit lane is needed, otherwise
21591 will shuffle in the requested value. */
21595 /* For t3 the 128-bit lanes are swapped again. */
21600 /* And oring both together leads to the result. */
21607 }
21610 /* Similarly to the above one_operand_shuffle code,
21611 just for repeated twice for each operand. merge_two:
21612 code will merge the two results together. */
21636 }
21637 }
21640 {
21641 /* The XOP VPPERM insn supports three inputs. By ignoring the
21642 one_operand_shuffle special case, we avoid creating another
21643 set of constant vectors in memory. */
21646 /* mask = mask & {2*w-1, ...} */
21648 }
21649 else
21650 {
21651 /* mask = mask & {w-1, ...} */
21653 }
21661 /* For non-QImode operations, convert the word permutation control
21662 into a byte permutation control. */
21664 {
21669 /* Convert mask to vector of chars. */
21672 /* Replicate each of the input bytes into byte positions:
21673 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21674 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21675 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21682 else
21685 /* Convert it into the byte positions by doing
21686 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21692 }
21694 /* The actual shuffle operations all operate on V16QImode. */
21699 {
21706 }
21708 {
21715 }
21716 else
21717 {
21721 /* Shuffle the two input vectors independently. */
21727 merge_two:
21728 /* Then merge them together. The key is whether any given control
21729 element contained a bit set that indicates the second word. */
21733 {
21734 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21735 more shuffle to convert the V2DI input mask into a V4SI
21736 input mask. At which point the masking that expand_int_vcond
21737 will work as desired. */
21745 }
21767 }
21768 }
21770 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21771 true if we should do zero extension, else sign extension. HIGH_P is
21772 true if we want the N/2 high elements, else the low elements. */
21774 void
21776 {
21778 rtx tmp;
21781 {
21787 {
21791 else
21794 extract
21800 else
21803 extract
21809 else
21812 extract
21818 else
21821 extract
21827 else
21830 extract
21836 else
21842 else
21848 else
21853 }
21856 {
21859 }
21861 {
21862 /* Shift higher 8 bytes to lower 8 bytes. */
21867 }
21868 else
21872 }
21873 else
21874 {
21878 {
21882 else
21888 else
21894 else
21899 }
21903 else
21910 }
21911 }
21913 /* Expand conditional increment or decrement using adb/sbb instructions.
21914 The default case using setcc followed by the conditional move can be
21915 done by generic code. */
21916 bool
21918 {
21920 rtx flags;
21922 rtx compare_op;
21940 {
21943 }
21946 {
21950 reverse_condition_maybe_unordered
21952 else
21954 }
21958 /* Construct either adc or sbb insn. */
21960 {
21962 {
21977 }
21978 }
21979 else
21980 {
21982 {
21997 }
21998 }
22002 }
22005 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22006 but works for floating pointer parameters and nonoffsetable memories.
22007 For pushes, it returns just stack offsets; the values will be saved
22008 in the right order. Maximally three parts are generated. */
22010 static int
22012 {
22017 else
22023 /* Optimize constant pool reference to immediates. This is used by fp
22024 moves, that force all constants to memory to allow combining. */
22026 {
22030 }
22033 {
22034 /* The only non-offsetable memories we handle are pushes. */
22043 }
22046 {
22048 /* Caution: if we looked through a constant pool memory above,
22049 the operand may actually have a different mode now. That's
22050 ok, since we want to pun this all the way back to an integer. */
22054 }
22057 {
22060 else
22061 {
22065 {
22069 }
22071 {
22076 }
22078 {
22079 REAL_VALUE_TYPE r;
22084 {
22091 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22092 long double may not be 80-bit. */
22101 }
22104 }
22105 else
22107 }
22108 }
22109 else
22110 {
22114 {
22117 {
22121 }
22123 {
22127 }
22129 {
22130 REAL_VALUE_TYPE r;
22136 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22139 = gen_int_mode
22142 DImode);
22143 else
22150 = gen_int_mode
22153 DImode);
22154 else
22156 }
22157 else
22159 }
22160 }
22163 }
22165 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22166 Return false when normal moves are needed; true when all required
22167 insns have been emitted. Operands 2-4 contain the input values
22168 int the correct order; operands 5-7 contain the output values. */
22170 void
22172 {
22180 /* The DFmode expanders may ask us to move double.
22181 For 64bit target this is single move. By hiding the fact
22182 here we simplify i386.md splitters. */
22184 {
22185 /* Optimize constant pool reference to immediates. This is used by
22186 fp moves, that force all constants to memory to allow combining. */
22193 {
22196 }
22197 else
22202 }
22204 /* The only non-offsettable memory we handle is push. */
22207 else
22214 /* When emitting push, take care for source operands on the stack. */
22217 {
22220 /* Compensate for the stack decrement by 4. */
22225 /* src_base refers to the stack pointer and is
22226 automatically decreased by emitted push. */
22230 }
22232 /* We need to do copy in the right order in case an address register
22233 of the source overlaps the destination. */
22235 {
22236 rtx tmp;
22239 {
22243 collisions++;
22244 }
22246 /* Collision in the middle part can be handled by reordering. */
22248 {
22251 }
22255 {
22257 {
22260 }
22261 else
22262 {
22265 }
22266 }
22268 /* If there are more collisions, we can't handle it by reordering.
22269 Do an lea to the last part and use only one colliding move. */
22271 {
22272 rtx base;
22278 /* Handle the case when the last part isn't valid for lea.
22279 Happens in 64-bit mode storing the 12-byte XFmode. */
22286 {
22289 }
22290 }
22291 }
22294 {
22296 {
22298 {
22303 }
22305 {
22308 }
22309 }
22310 else
22311 {
22312 /* In 64bit mode we don't have 32bit push available. In case this is
22313 register, it is OK - we will just use larger counterpart. We also
22314 retype memory - these comes from attempt to avoid REX prefix on
22315 moving of second half of TFmode value. */
22317 {
22319 {
22330 }
22334 }
22335 }
22339 }
22341 /* Choose correct order to not overwrite the source before it is copied. */
22351 {
22353 {
22356 }
22357 }
22358 else
22359 {
22361 {
22364 }
22365 }
22367 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22369 {
22378 }
22384 }
22386 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22387 left shift by a constant, either using a single shift or
22388 a sequence of add instructions. */
22390 static void
22392 {
22398 {
22402 }
22403 else
22404 {
22407 }
22408 }
22410 void
22412 {
22421 {
22426 {
22432 }
22433 else
22434 {
22442 }
22444 }
22451 {
22452 /* Assuming we've chosen a QImode capable registers, then 1 << N
22453 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22455 {
22471 }
22473 /* Otherwise, we can get the same results by manually performing
22474 a bit extract operation on bit 5/6, and then performing the two
22475 shifts. The two methods of getting 0/1 into low/high are exactly
22476 the same size. Avoiding the shift in the bit extract case helps
22477 pentium4 a bit; no one else seems to care much either way. */
22478 else
22479 {
22484 HOST_WIDE_INT bits;
22485 rtx x;
22488 {
22494 }
22495 else
22496 {
22502 }
22506 else
22514 }
22519 }
22522 {
22523 /* For -1 << N, we can avoid the shld instruction, because we
22524 know that we're shifting 0...31/63 ones into a -1. */
22528 else
22530 }
22531 else
22532 {
22540 }
22545 {
22551 }
22552 else
22553 {
22558 }
22559 }
22561 void
22563 {
22573 {
22578 {
22584 }
22586 {
22595 }
22596 else
22597 {
22605 }
22606 }
22607 else
22608 {
22620 {
22628 scratch));
22629 }
22630 else
22631 {
22636 }
22637 }
22638 }
22640 void
22642 {
22652 {
22657 {
22664 }
22665 else
22666 {
22674 }
22675 }
22676 else
22677 {
22689 {
22695 scratch));
22696 }
22697 else
22698 {
22703 }
22704 }
22705 }
22707 /* Predict just emitted jump instruction to be taken with probability PROB. */
22708 static void
22710 {
22714 }
22716 /* Helper function for the string operations below. Dest VARIABLE whether
22717 it is aligned to VALUE bytes. If true, jump to the label. */
22718 static rtx
22720 {
22725 else
22731 else
22734 }
22736 /* Adjust COUNTER by the VALUE. */
22737 static void
22739 {
22744 }
22746 /* Zero extend possibly SImode EXP to Pmode register. */
22747 rtx
22749 {
22751 }
22753 /* Divide COUNTREG by SCALE. */
22754 static rtx
22756 {
22757 rtx sc;
22769 }
22771 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22772 DImode for constant loop counts. */
22774 static enum machine_mode
22776 {
22784 }
22786 /* Copy the address to a Pmode register. This is used for x32 to
22787 truncate DImode TLS address to a SImode register. */
22789 static rtx
22791 {
22794 else
22795 {
22798 }
22799 }
22801 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22802 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22803 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22804 memory by VALUE (supposed to be in MODE).
22806 The size is rounded down to whole number of chunk size moved at once.
22807 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22810 static void
22815 {
22821 rtx size;
22830 /* Those two should combine. */
22832 {
22836 }
22843 /* This assert could be relaxed - in this case we'll need to compute
22844 smallest power of two, containing in PIECE_SIZE_N and pass it to
22845 offset_address. */
22851 {
22855 /* When unrolling for chips that reorder memory reads and writes,
22856 we can save registers by using single temporary.
22857 Also using 4 temporaries is overkill in 32bit mode. */
22859 {
22861 {
22863 {
22864 destmem =
22866 srcmem =
22868 }
22870 }
22871 }
22872 else
22873 {
22877 {
22880 {
22881 srcmem =
22883 }
22885 }
22887 {
22889 {
22890 destmem =
22892 }
22894 }
22895 }
22896 }
22897 else
22899 {
22901 destmem =
22904 }
22914 {
22920 else
22922 }
22923 else
22931 {
22936 }
22938 }
22940 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
22941 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
22942 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
22943 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
22944 ORIG_VALUE is the original value passed to memset to fill the memory with.
22945 Other arguments have same meaning as for previous function. */
22947 static void
22950 rtx count,
22952 {
22953 rtx destexp;
22954 rtx srcexp;
22955 rtx countreg;
22956 HOST_WIDE_INT rounded_count;
22958 /* If possible, it is shorter to use rep movs.
22959 TODO: Maybe it is better to move this logic to decide_alg. */
22970 {
22974 }
22975 else
22978 {
22983 }
22988 {
22991 }
22992 else
22993 {
22997 {
23001 }
23002 else
23005 {
23010 }
23011 else
23012 {
23015 }
23018 }
23019 }
23021 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23022 DESTMEM.
23023 SRC is passed by pointer to be updated on return.
23024 Return value is updated DST. */
23025 static rtx
23027 HOST_WIDE_INT size_to_move)
23028 {
23034 /* Find the widest mode in which we could perform moves.
23035 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23036 it until move of such size is supported. */
23041 {
23045 }
23047 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23048 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23050 {
23055 {
23059 }
23060 }
23066 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23070 {
23071 /* We move from memory to memory, so we'll need to do it via
23072 a temporary register. */
23083 piece_size);
23085 piece_size);
23086 }
23088 /* Update DST and SRC rtx. */
23091 }
23093 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23094 static void
23097 {
23100 {
23105 /* For now MAX_SIZE should be a power of 2. This assert could be
23106 relaxed, but it'll require a bit more complicated epilogue
23107 expanding. */
23110 {
23113 }
23115 }
23117 {
23123 }
23125 /* When there are stringops, we can cheaply increase dest and src pointers.
23126 Otherwise we save code size by maintaining offset (zero is readily
23127 available from preceding rep operation) and using x86 addressing modes.
23128 */
23130 {
23132 {
23139 }
23141 {
23148 }
23150 {
23157 }
23158 }
23159 else
23160 {
23162 rtx tmp;
23165 {
23176 }
23178 {
23191 }
23193 {
23202 }
23203 }
23204 }
23206 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23207 with value PROMOTED_VAL.
23208 SRC is passed by pointer to be updated on return.
23209 Return value is updated DST. */
23210 static rtx
23212 HOST_WIDE_INT size_to_move)
23213 {
23219 /* Find the widest mode in which we could perform moves.
23220 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23221 it until move of such size is supported. */
23226 {
23229 }
23236 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23240 {
23242 {
23245 piece_size);
23247 }
23255 piece_size);
23256 }
23258 /* Update DST rtx. */
23260 }
23261 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23262 static void
23265 {
23266 count =
23272 }
23274 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23275 static void
23278 {
23279 rtx dest;
23282 {
23287 /* For now MAX_SIZE should be a power of 2. This assert could be
23288 relaxed, but it'll require a bit more complicated epilogue
23289 expanding. */
23292 {
23294 {
23297 else
23299 }
23300 }
23302 }
23304 {
23307 }
23309 {
23312 {
23317 }
23318 else
23319 {
23328 }
23331 }
23333 {
23336 {
23339 }
23340 else
23341 {
23346 }
23349 }
23351 {
23357 }
23359 {
23365 }
23367 {
23373 }
23374 }
23376 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23377 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23378 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23379 ignored.
23380 Return value is updated DESTMEM. */
23381 static rtx
23386 {
23389 {
23391 {
23394 {
23397 else
23399 }
23400 else
23406 }
23407 }
23409 }
23411 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23412 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23413 and jump to DONE_LABEL. */
23414 static void
23420 {
23423 rtx modesize;
23426 /* If we do not have vector value to copy, we must reduce size. */
23428 {
23430 {
23435 }
23436 else
23438 }
23439 else
23440 {
23441 /* Choose appropriate vector mode. */
23447 }
23452 {
23455 else
23456 {
23459 }
23461 }
23467 {
23471 }
23473 {
23476 else
23477 {
23480 }
23482 }
23488 }
23490 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23491 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23492 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23493 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23494 DONE_LABEL is a label after the whole copying sequence. The label is created
23495 on demand if *DONE_LABEL is NULL.
23496 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23497 bounds after the initial copies.
23499 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23500 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23501 we will dispatch to a library call for large blocks.
23503 In pseudocode we do:
23505 if (COUNT < SIZE)
23506 {
23507 Assume that SIZE is 4. Bigger sizes are handled analogously
23508 if (COUNT & 4)
23509 {
23510 copy 4 bytes from SRCPTR to DESTPTR
23511 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23512 goto done_label
23513 }
23514 if (!COUNT)
23515 goto done_label;
23516 copy 1 byte from SRCPTR to DESTPTR
23517 if (COUNT & 2)
23518 {
23519 copy 2 bytes from SRCPTR to DESTPTR
23520 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23521 }
23522 }
23523 else
23524 {
23525 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23526 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23528 OLD_DESPTR = DESTPTR;
23529 Align DESTPTR up to DESIRED_ALIGN
23530 SRCPTR += DESTPTR - OLD_DESTPTR
23531 COUNT -= DEST_PTR - OLD_DESTPTR
23532 if (DYNAMIC_CHECK)
23533 Round COUNT down to multiple of SIZE
23534 << optional caller supplied zero size guard is here >>
23535 << optional caller suppplied dynamic check is here >>
23536 << caller supplied main copy loop is here >>
23537 }
23538 done_label:
23539 */
23540 static void
23553 {
23556 rtx modesize;
23558 rtx mode_value;
23560 /* Chose proper value to copy. */
23563 else
23567 /* See if block is big or small, handle small blocks. */
23569 {
23580 /* Handle sizes > 3. */
23587 /* Nothing to copy? Jump to DONE_LABEL if so */
23591 /* Do a byte copy. */
23595 else
23596 {
23599 }
23601 /* Handle sizes 2 and 3. */
23608 else
23609 {
23614 }
23620 }
23621 else
23625 /* Start memcpy for COUNT >= SIZE. */
23627 {
23630 }
23632 /* Copy first desired_align bytes. */
23638 {
23641 else
23642 {
23645 }
23648 }
23651 /* Copy last SIZE bytes. */
23658 else
23659 {
23665 }
23667 {
23671 else
23672 {
23675 }
23676 }
23678 /* Align destination. */
23680 {
23684 /* Align destptr up, place it to new register. */
23691 /* See how many bytes we skipped. */
23695 /* Adjust srcptr and count. */
23701 /* We copied at most size + prolog_size. */
23704 else
23707 /* Our loops always round down the bock size, but for dispatch to library
23708 we need precise value. */
23712 }
23713 else
23714 {
23716 /* Decrease count, so we won't end up copying last word twice. */
23720 else
23724 }
23725 }
23728 /* This function is like the previous one, except here we know how many bytes
23729 need to be copied. That allows us to update alignment not only of DST, which
23730 is returned, but also of SRC, which is passed as a pointer for that
23731 reason. */
23732 static rtx
23737 {
23745 {
23749 }
23754 {
23756 {
23758 {
23761 else
23763 }
23764 else
23767 }
23768 }
23775 {
23781 {
23784 {
23788 }
23793 }
23797 }
23800 }
23802 /* Return true if ALG can be used in current context.
23803 Assume we expand memset if MEMSET is true. */
23804 static bool
23806 {
23811 /* Algorithms using the rep prefix want at least edi and ecx;
23812 additionally, memset wants eax and memcpy wants esi. Don't
23813 consider such algorithms if the user has appropriated those
23814 registers for their own purposes. */
23821 }
23823 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23824 static enum stringop_alg
23828 {
23839 /* Even if the string operation call is cold, we still might spend a lot
23840 of time processing large blocks. */
23846 else
23852 else
23855 /* See maximal size for user defined algorithm. */
23857 {
23864 }
23866 /* If expected size is not known but max size is small enough
23867 so inline version is a win, set expected size into
23868 the range. */
23873 /* If user specified the algorithm, honnor it if possible. */
23877 /* rep; movq or rep; movl is the smallest variant. */
23879 {
23884 else
23887 }
23888 /* Very tiny blocks are best handled via the loop, REP is expensive to
23889 setup. */
23893 {
23897 {
23898 /* We get here if the algorithms that were not libcall-based
23899 were rep-prefix based and we are unable to use rep prefixes
23900 based on global register usage. Break out of the loop and
23901 use the heuristic below. */
23905 {
23909 {
23912 }
23913 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
23914 last non-libcall inline algorithm. */
23916 {
23917 /* When the current size is best to be copied by a libcall,
23918 but we are still forced to inline, run the heuristic below
23919 that will pick code for medium sized blocks. */
23921 {
23924 }
23926 }
23928 {
23931 }
23932 }
23933 }
23934 }
23935 /* When asked to inline the call anyway, try to pick meaningful choice.
23936 We look for maximal size of block that is faster to copy by hand and
23937 take blocks of at most of that size guessing that average size will
23938 be roughly half of the block.
23940 If this turns out to be bad, we might simply specify the preferred
23941 choice in ix86_costs. */
23945 {
23948 /* If there aren't any usable algorithms, then recursing on
23949 smaller sizes isn't going to find anything. Just return the
23950 simple byte-at-a-time copy loop. */
23952 {
23953 /* Pick something reasonable. */
23957 }
23967 }
23970 }
23972 /* Decide on alignment. We know that the operand is already aligned to ALIGN
23973 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
23974 static int
23979 {
23990 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
23991 copying whole cacheline at once. */
24004 }
24007 /* Helper function for memcpy. For QImode value 0xXY produce
24008 0xXYXYXYXY of wide specified by MODE. This is essentially
24009 a * 0x10101010, but we can do slightly better than
24010 synth_mult by unwinding the sequence by hand on CPUs with
24011 slow multiply. */
24012 static rtx
24014 {
24016 rtx tmp;
24023 {
24031 }
24040 nops--;
24045 {
24049 OPTAB_DIRECT);
24050 }
24051 else
24052 {
24058 else
24060 else
24061 {
24064 reg =
24066 }
24076 }
24077 }
24079 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24080 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24081 alignment from ALIGN to DESIRED_ALIGN. */
24082 static rtx
24085 {
24086 rtx promoted_val;
24095 else
24099 }
24101 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24102 operations when profitable. The code depends upon architecture, block size
24103 and alignment, but always has one of the following overall structures:
24105 Aligned move sequence:
24107 1) Prologue guard: Conditional that jumps up to epilogues for small
24108 blocks that can be handled by epilogue alone. This is faster
24109 but also needed for correctness, since prologue assume the block
24110 is larger than the desired alignment.
24112 Optional dynamic check for size and libcall for large
24113 blocks is emitted here too, with -minline-stringops-dynamically.
24115 2) Prologue: copy first few bytes in order to get destination
24116 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24117 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24118 copied. We emit either a jump tree on power of two sized
24119 blocks, or a byte loop.
24121 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24122 with specified algorithm.
24124 4) Epilogue: code copying tail of the block that is too small to be
24125 handled by main body (or up to size guarded by prologue guard).
24127 Misaligned move sequence
24129 1) missaligned move prologue/epilogue containing:
24130 a) Prologue handling small memory blocks and jumping to done_label
24131 (skipped if blocks are known to be large enough)
24132 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24133 needed by single possibly misaligned move
24134 (skipped if alignment is not needed)
24135 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24137 2) Zero size guard dispatching to done_label, if needed
24139 3) dispatch to library call, if needed,
24141 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24142 with specified algorithm. */
24143 bool
24149 {
24150 rtx destreg;
24153 rtx tmp;
24169 /* TODO: Once value ranges are available, fill in proper data. */
24177 /* i386 can do misaligned access on reasonably increased cost. */
24181 /* ALIGN is the minimum of destination and source alignment, but we care here
24182 just about destination alignment. */
24188 {
24191 /* When COUNT is 0, there is nothing to do. */
24194 }
24195 else
24196 {
24205 }
24207 /* Make sure we don't need to care about overflow later on. */
24211 /* Step 0: Decide on preferred algorithm, desired alignment and
24212 size of chunks to be copied by main loop. */
24214 issetmem,
24221 /* For now vector-version of memset is generated only for memory zeroing, as
24222 creating of promoted vector value is very cheap in this case. */
24235 {
24254 /* Find the widest supported mode. */
24260 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24261 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24263 {
24268 }
24280 }
24288 /* Step 1: Prologue guard. */
24290 /* Alignment code needs count to be in register. */
24292 {
24295 {
24296 align_bytes
24300 else
24302 }
24305 }
24308 /* Misaligned move sequences handle both prologue and epilogue at once.
24309 Default code generation results in a smaller code for large alignments
24310 and also avoids redundant job when sizes are known precisely. */
24311 misaligned_prologue_used
24312 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24318 /* Do the cheap promotion to allow better CSE across the
24319 main loop and epilogue (ie one load of the big constant in the
24320 front of all code.
24321 For now the misaligned move sequences do not have fast path
24322 without broadcasting. */
24324 {
24326 {
24332 }
24333 else
24334 {
24337 }
24338 }
24339 /* Misaligned move sequences handles both prologues and epilogues at once.
24340 Default code generation results in smaller code for large alignments and
24341 also avoids redundant job when sizes are known precisely. */
24343 {
24344 /* Misaligned move prologue handled small blocks by itself. */
24345 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24350 desired_align < align
24359 {
24360 /* It is possible that we copied enough so the main loop will not
24361 execute. */
24371 else
24373 }
24374 }
24375 /* Ensure that alignment prologue won't copy past end of block. */
24377 {
24379 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24380 Make sure it is power of 2. */
24383 /* To improve performance of small blocks, we jump around the VAL
24384 promoting mode. This mean that if the promoted VAL is not constant,
24385 we might not use it in the epilogue and have to use byte
24386 loop variant. */
24391 {
24392 /* If main algorithm works on QImode, no epilogue is needed.
24393 For small sizes just don't align anything. */
24396 else
24398 }
24401 {
24408 else
24410 }
24411 }
24413 /* Emit code to decide on runtime whether library call or inline should be
24414 used. */
24416 {
24418 {
24420 {
24424 }
24425 }
24426 else
24427 {
24437 else
24441 }
24442 }
24444 /* Step 2: Alignment prologue. */
24445 /* Do the expensive promotion once we branched off the small blocks. */
24451 {
24453 {
24454 /* Except for the first move in prologue, we no longer know
24455 constant offset in aliasing info. It don't seems to worth
24456 the pain to maintain it for the first move, so throw away
24457 the info early. */
24464 issetmem);
24465 /* At most desired_align - align bytes are copied. */
24468 else
24470 }
24471 else
24472 {
24473 /* If we know how many bytes need to be stored before dst is
24474 sufficiently aligned, maintain aliasing info accurately. */
24476 srcreg,
24477 promoted_val,
24478 vec_promoted_val,
24479 desired_align,
24480 align_bytes,
24481 issetmem);
24488 }
24490 && !min_size
24495 {
24496 /* It is possible that we copied enough so the main loop will not
24497 execute. */
24507 else
24509 }
24510 }
24512 {
24519 }
24523 /* Step 3: Main loop. */
24526 {
24549 }
24550 /* Adjust properly the offset of src and dest memory for aliasing. */
24552 {
24558 }
24559 else
24560 {
24564 }
24566 /* Step 4: Epilogue to copy the remaining bytes. */
24567 epilogue:
24569 {
24570 /* When the main loop is done, COUNT_EXP might hold original count,
24571 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24572 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24573 bytes. Compensate if needed. */
24576 {
24577 tmp =
24580 OPTAB_DIRECT);
24583 }
24586 }
24589 {
24592 epilogue_size_needed);
24593 else
24594 {
24598 epilogue_size_needed);
24599 else
24601 epilogue_size_needed);
24602 }
24603 }
24607 }
24610 /* Expand the appropriate insns for doing strlen if not just doing
24611 repnz; scasb
24613 out = result, initialized with the start address
24614 align_rtx = alignment of the address.
24615 scratch = scratch register, initialized with the startaddress when
24616 not aligned, otherwise undefined
24618 This is just the body. It needs the initializations mentioned above and
24619 some address computing at the end. These things are done in i386.md. */
24621 static void
24623 {
24625 rtx tmp;
24630 rtx mem;
24633 rtx cmp;
24639 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24641 /* Is there a known alignment and is it less than 4? */
24643 {
24646 /* Is there a known alignment and is it not 2? */
24648 {
24652 /* Leave just the 3 lower bits. */
24662 }
24663 else
24664 {
24665 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24666 check if is aligned to 4 - byte. */
24673 }
24677 /* Now compare the bytes. */
24679 /* Compare the first n unaligned byte on a byte per byte basis. */
24683 /* Increment the address. */
24686 /* Not needed with an alignment of 2 */
24688 {
24692 end_0_label);
24697 }
24700 end_0_label);
24703 }
24705 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24706 align this loop. It gives only huge programs, but does not help to
24707 speed up. */
24714 /* This formula yields a nonzero result iff one of the bytes is zero.
24715 This saves three branches inside loop and many cycles. */
24723 align_4_label);
24726 {
24732 /* If zero is not in the first two bytes, move two bytes forward. */
24738 reg,
24739 tmpreg)));
24740 /* Emit lea manually to avoid clobbering of flags. */
24748 reg2,
24749 out)));
24750 }
24751 else
24752 {
24754 /* Is zero in the first two bytes? */
24761 pc_rtx);
24765 /* Not in the first two. Move two bytes forward. */
24771 }
24773 /* Avoid branch in fixing the byte. */
24781 }
24783 /* Expand strlen. */
24785 bool
24787 {
24790 /* The generic case of strlen expander is long. Avoid it's
24791 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24794 && !TARGET_INLINE_ALL_STRINGOPS
24804 {
24805 /* Well it seems that some optimizer does not combine a call like
24806 foo(strlen(bar), strlen(bar));
24807 when the move and the subtraction is done here. It does calculate
24808 the length just once when these instructions are done inside of
24809 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24810 often used and I use one fewer register for the lifetime of
24811 output_strlen_unroll() this is better. */
24817 /* strlensi_unroll_1 returns the address of the zero at the end of
24818 the string, like memchr(), so compute the length by subtracting
24819 the start address. */
24821 }
24822 else
24823 {
24824 rtx unspec;
24826 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24839 /* If .md starts supporting :P, this can be done in .md. */
24845 }
24847 }
24849 /* For given symbol (function) construct code to compute address of it's PLT
24850 entry in large x86-64 PIC model. */
24851 static rtx
24853 {
24866 }
24868 rtx
24870 rtx callarg2,
24872 {
24873 unsigned int const cregs_size
24884 {
24885 #if TARGET_MACHO
24888 #endif
24889 }
24890 else
24891 {
24892 /* Static functions and indirect calls don't need the pic register. */
24894 && (!TARGET_64BIT
24900 }
24903 {
24907 }
24910 && !TARGET_PECOFF
24918 {
24921 }
24929 {
24933 }
24937 {
24941 UNSPEC_MS_TO_SYSV_CALL);
24944 {
24950 }
24951 }
24960 }
24962 /* Output the assembly for a call instruction. */
24966 {
24972 {
24975 /* SEH epilogue detection requires the indirect branch case
24976 to include REX.W. */
24979 else
24984 }
24986 /* SEH unwinding can require an extra nop to be emitted in several
24987 circumstances. Determine if we have one of those. */
24989 {
24990 rtx i;
24993 {
24994 /* If we get to another real insn, we don't need the nop. */
24998 /* If we get to the epilogue note, prevent a catch region from
24999 being adjacent to the standard epilogue sequence. If non-
25000 call-exceptions, we'll have done this during epilogue emission. */
25002 && !flag_non_call_exceptions
25004 {
25007 }
25008 }
25010 /* If we didn't find a real insn following the call, prevent the
25011 unwinder from looking into the next function. */
25014 }
25018 else
25027 }
25028 \f
25029 /* Clear stack slot assignments remembered from previous functions.
25030 This is called from INIT_EXPANDERS once before RTL is emitted for each
25031 function. */
25035 {
25043 }
25045 /* Return a MEM corresponding to a stack slot with mode MODE.
25046 Allocate a new slot if necessary.
25048 The RTL for a function can have several slots available: N is
25049 which slot to use. */
25051 rtx
25053 {
25070 }
25072 static void
25074 {
25080 }
25081 \f
25082 /* Check whether x86 address PARTS is a pc-relative address. */
25084 static bool
25086 {
25094 {
25096 {
25113 }
25114 }
25116 }
25118 /* Calculate the length of the memory address in the instruction encoding.
25119 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25120 or other prefixes. We never generate addr32 prefix for LEA insn. */
25122 int
25124 {
25141 /* If this is not LEA instruction, add the length of addr32 prefix. */
25146 len++;
25160 /* Rule of thumb:
25161 - esp as the base always wants an index,
25162 - ebp as the base always wants a displacement,
25163 - r12 as the base always wants an index,
25164 - r13 as the base always wants a displacement. */
25166 /* Register Indirect. */
25168 {
25169 /* esp (for its index) and ebp (for its displacement) need
25170 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25171 code. */
25178 len++;
25179 }
25181 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25182 is not disp32, but disp32(%rip), so for disp32
25183 SIB byte is needed, unless print_operand_address
25184 optimizes it into disp32(%rip) or (%rip) is implied
25185 by UNSPEC. */
25187 {
25190 len++;
25191 }
25192 else
25193 {
25194 /* Find the length of the displacement constant. */
25196 {
25199 else
25201 }
25202 /* ebp always wants a displacement. Similarly r13. */
25204 len++;
25206 /* An index requires the two-byte modrm form.... */
25208 /* ...like esp (or r12), which always wants an index. */
25212 len++;
25213 }
25216 }
25218 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25219 is set, expect that insn have 8bit immediate alternative. */
25220 int
25222 {
25228 {
25233 {
25236 {
25248 }
25250 {
25253 }
25254 }
25256 {
25266 /* Immediates for DImode instructions are encoded
25267 as 32bit sign extended values. */
25273 }
25274 }
25276 }
25278 /* Compute default value for "length_address" attribute. */
25279 int
25281 {
25285 {
25296 }
25301 {
25304 {
25309 constraints++;
25312 ;
25313 /* Skip ignored operands. */
25316 }
25318 }
25320 }
25322 /* Compute default value for "length_vex" attribute. It includes
25323 2 or 3 byte VEX prefix and 1 opcode byte. */
25325 int
25327 {
25330 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25331 byte VEX prefix. */
25335 /* We can always use 2 byte VEX prefix in 32bit. */
25343 {
25344 /* REX.W bit uses 3 byte VEX prefix. */
25348 }
25349 else
25350 {
25351 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25355 }
25358 }
25359 \f
25360 /* Return the maximum number of instructions a cpu can issue. */
25362 static int
25364 {
25366 {
25397 }
25398 }
25400 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25401 by DEP_INSN and nothing set by DEP_INSN. */
25403 static bool
25405 {
25408 /* Simplify the test for uninteresting insns. */
25416 {
25419 }
25424 {
25427 }
25428 else
25434 /* This test is true if the dependent insn reads the flags but
25435 not any other potentially set register. */
25443 }
25445 /* Return true iff USE_INSN has a memory address with operands set by
25446 SET_INSN. */
25448 bool
25450 {
25455 {
25458 }
25460 }
25462 /* Helper function for exact_store_load_dependency.
25463 Return true if addr is found in insn. */
25464 static bool
25466 {
25473 {
25479 CASE_CONST_ANY:
25488 }
25492 {
25494 {
25504 }
25505 }
25507 }
25509 /* Return true if there exists exact dependency for store & load, i.e.
25510 the same memory address is used in them. */
25511 static bool
25513 {
25527 }
25529 static int
25531 {
25537 /* Anti and output dependencies have zero cost on all CPUs. */
25543 /* If we can't recognize the insns, we can't really do anything. */
25551 {
25553 /* Address Generation Interlock adds a cycle of latency. */
25555 {
25566 }
25570 /* ??? Compares pair with jump/setcc. */
25574 /* Floating point stores require value to be ready one cycle earlier. */
25582 /* INT->FP conversion is expensive. */
25586 /* There is one cycle extra latency between an FP op and a store. */
25596 /* Show ability of reorder buffer to hide latency of load by executing
25597 in parallel with previous instruction in case
25598 previous instruction is not needed to compute the address. */
25601 {
25602 /* Claim moves to take one cycle, as core can issue one load
25603 at time and the next load can start cycle later. */
25608 cost--;
25609 }
25613 /* The esp dependency is resolved before
25614 the instruction is really finished. */
25619 /* INT->FP conversion is expensive. */
25625 /* Show ability of reorder buffer to hide latency of load by executing
25626 in parallel with previous instruction in case
25627 previous instruction is not needed to compute the address. */
25630 {
25631 /* Claim moves to take one cycle, as core can issue one load
25632 at time and the next load can start cycle later. */
25638 else
25640 }
25651 /* Stack engine allows to execute push&pop instructions in parall. */
25655 /* FALLTHRU */
25661 /* Show ability of reorder buffer to hide latency of load by executing
25662 in parallel with previous instruction in case
25663 previous instruction is not needed to compute the address. */
25666 {
25670 /* Because of the difference between the length of integer and
25671 floating unit pipeline preparation stages, the memory operands
25672 for floating point are cheaper.
25674 ??? For Athlon it the difference is most probably 2. */
25677 else
25682 else
25684 }
25691 /* Stack engine allows to execute push&pop instructions in parall. */
25698 /* Show ability of reorder buffer to hide latency of load by executing
25699 in parallel with previous instruction in case
25700 previous instruction is not needed to compute the address. */
25703 {
25706 else
25708 }
25716 /* Increase cost of integer loads. */
25719 {
25722 {
25725 else
25726 {
25727 /* Increase cost of ld/st for short int types only
25728 because of store forwarding issue. */
25732 {
25733 /* Increase cost of store/load insn if exact
25734 dependence exists and it is load insn. */
25739 }
25740 }
25741 }
25742 }
25746 }
25749 }
25751 /* How many alternative schedules to try. This should be as wide as the
25752 scheduling freedom in the DFA, but no wider. Making this value too
25753 large results extra work for the scheduler. */
25755 static int
25757 {
25759 {
25771 /* We use lookahead value 4 for BD both before and after reload
25772 schedules. Plan is to have value 8 included for O3. */
25782 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25783 as many instructions can be executed on a cycle, i.e.,
25784 issue_rate. I wonder why tuning for many CPUs does not do this. */
25787 /* Don't use lookahead for pre-reload schedule to save compile time. */
25792 }
25793 }
25795 /* Return true if target platform supports macro-fusion. */
25797 static bool
25799 {
25801 }
25803 /* Check whether current microarchitecture support macro fusion
25804 for insn pair "CONDGEN + CONDJMP". Refer to
25805 "Intel Architectures Optimization Reference Manual". */
25807 static bool
25809 {
25828 else
25829 {
25834 {
25838 else
25840 }
25841 }
25848 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
25849 supported. */
25856 /* No fusion for RIP-relative address. */
25863 ix86_address parts;
25869 }
25874 /* Check whether conditional jump use Sign or Overflow Flags. */
25882 /* Return true for TYPE_TEST and TYPE_ICMP. */
25887 /* The following is the case that macro-fusion for alu + jmp. */
25891 /* No fusion for alu op with memory destination operand. */
25896 /* Macro-fusion for inc/dec + unsigned conditional jump is not
25897 supported. */
25906 }
25908 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
25909 execution. It is applied if
25910 (1) IMUL instruction is on the top of list;
25911 (2) There exists the only producer of independent IMUL instruction in
25912 ready list.
25913 Return index of IMUL producer if it was found and -1 otherwise. */
25914 static int
25916 {
25918 sd_iterator_def sd_it;
25919 dep_t dep;
25926 /* Check that IMUL instruction is on the top of ready list. */
25935 /* Search for producer of independent IMUL instruction. */
25937 {
25941 /* Skip IMUL instruction. */
25951 {
25952 rtx con;
25963 {
25964 sd_iterator_def sd_it1;
25965 dep_t dep1;
25966 /* Check if there is no other dependee for IMUL. */
25969 {
25970 rtx pro;
25976 }
25979 }
25980 }
25983 }
25985 }
25987 /* Try to find the best candidate on the top of ready list if two insns
25988 have the same priority - candidate is best if its dependees were
25989 scheduled earlier. Applied for Silvermont only.
25990 Return true if top 2 insns must be interchanged. */
25991 static bool
25993 {
25996 rtx set;
25997 sd_iterator_def sd_it;
25998 dep_t dep;
26001 #define INSN_TICK(INSN) (HID (INSN)->tick)
26022 {
26025 /* Determine winner more precise. */
26027 {
26028 rtx pro;
26034 }
26036 {
26037 rtx pro;
26043 }
26046 {
26047 /* Determine winner - load must win. */
26053 }
26055 }
26057 #undef INSN_TICK
26058 }
26060 /* Perform possible reodering of ready list for Atom/Silvermont only.
26061 Return issue rate. */
26062 static int
26065 {
26069 rtx insn;
26072 /* Set up issue rate. */
26075 /* Do reodering for BONNELL/SILVERMONT only. */
26079 /* Nothing to do if ready list contains only 1 instruction. */
26083 /* Do reodering for post-reload scheduler only. */
26088 {
26093 /* Put IMUL producer (ready[index]) at the top of ready list. */
26099 }
26101 {
26105 /* Swap 2 top elements of ready list. */
26109 }
26111 }
26113 static bool
26116 /* Returns true if lhs of insn is HW function argument register and set up
26117 is_spilled to true if it is likely spilled HW register. */
26118 static bool
26120 {
26121 rtx dst;
26125 /* Call instructions are not movable, ignore it. */
26136 {
26137 /* Is it likely spilled HW register? */
26142 }
26144 }
26146 /* Add output dependencies for chain of function adjacent arguments if only
26147 there is a move to likely spilled HW register. Return first argument
26148 if at least one dependence was added or NULL otherwise. */
26149 static rtx
26151 {
26152 rtx insn;
26159 /* Find nearest to call argument passing instruction. */
26161 {
26170 }
26174 {
26181 {
26184 }
26186 {
26187 /* Add output depdendence between two function arguments if chain
26188 of output arguments contains likely spilled HW registers. */
26192 }
26193 else
26195 }
26199 }
26201 /* Add output or anti dependency from insn to first_arg to restrict its code
26202 motion. */
26203 static void
26205 {
26206 rtx set;
26207 rtx tmp;
26214 {
26215 /* Add output dependency to the first function argument. */
26218 }
26219 /* Add anti dependency. */
26221 }
26223 /* Avoid cross block motion of function argument through adding dependency
26224 from the first non-jump instruction in bb. */
26225 static void
26227 {
26231 {
26233 {
26236 {
26239 }
26240 }
26244 }
26245 }
26247 /* Hook for pre-reload schedule - avoid motion of function arguments
26248 passed in likely spilled HW registers. */
26249 static void
26251 {
26252 rtx insn;
26260 {
26263 {
26264 /* Add dependee for first argument to predecessors if only
26265 region contains more than one block. */
26269 /* Skip trivial regions and region head blocks that can have
26270 predecessors outside of region. */
26272 {
26273 edge e;
26274 edge_iterator ei;
26276 /* Regions are SCCs with the exception of selective
26277 scheduling with pipelining of outer blocks enabled.
26278 So also check that immediate predecessors of a non-head
26279 block are in the same region. */
26281 {
26282 /* Avoid creating of loop-carried dependencies through
26283 using topological ordering in the region. */
26287 }
26288 }
26292 }
26293 }
26296 }
26298 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26299 HW registers to maximum, to schedule them at soon as possible. These are
26300 moves from function argument registers at the top of the function entry
26301 and moves from function return value registers after call. */
26302 static int
26304 {
26305 rtx set;
26315 {
26322 }
26325 }
26327 /* Model decoder of Core 2/i7.
26328 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26329 track the instruction fetch block boundaries and make sure that long
26330 (9+ bytes) instructions are assigned to D0. */
26332 /* Maximum length of an insn that can be handled by
26333 a secondary decoder unit. '8' for Core 2/i7. */
26336 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26337 '16' for Core 2/i7. */
26340 /* Maximum number of instructions decoder can handle per cycle.
26341 '6' for Core 2/i7. */
26345 ix86_first_cycle_multipass_data_t;
26347 const_ix86_first_cycle_multipass_data_t;
26349 /* A variable to store target state across calls to max_issue within
26350 one cycle. */
26354 /* Initialize DATA. */
26355 static void
26357 {
26358 ix86_first_cycle_multipass_data_t data
26365 }
26367 /* Advancing the cycle; reset ifetch block counts. */
26368 static void
26370 {
26377 }
26381 /* Filter out insns from ready_try that the core will not be able to issue
26382 on current cycle due to decoder. */
26383 static void
26384 core2i7_first_cycle_multipass_filter_ready_try
26387 {
26389 {
26390 rtx insn;
26400 (!first_cycle_insn_p
26402 /* ... or it would not fit into the ifetch block ... */
26404 /* ... or the decoder is full already ... */
26406 /* ... mask the insn out. */
26407 {
26412 }
26413 }
26414 }
26416 /* Prepare for a new round of multipass lookahead scheduling. */
26417 static void
26421 {
26422 ix86_first_cycle_multipass_data_t data
26424 const_ix86_first_cycle_multipass_data_t prev_data
26427 /* Restore the state from the end of the previous round. */
26431 /* Filter instructions that cannot be issued on current cycle due to
26432 decoder restrictions. */
26434 first_cycle_insn_p);
26435 }
26437 /* INSN is being issued in current solution. Account for its impact on
26438 the decoder model. */
26439 static void
26443 {
26444 ix86_first_cycle_multipass_data_t data
26446 const_ix86_first_cycle_multipass_data_t prev_data
26456 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26458 {
26461 }
26463 {
26467 }
26470 /* Filter out insns from ready_try that the core will not be able to issue
26471 on current cycle due to decoder. */
26474 }
26476 /* Revert the effect on ready_try. */
26477 static void
26481 {
26482 const_ix86_first_cycle_multipass_data_t data
26485 sbitmap_iterator sbi;
26489 {
26491 }
26492 }
26494 /* Save the result of multipass lookahead scheduling for the next round. */
26495 static void
26497 {
26498 const_ix86_first_cycle_multipass_data_t data
26500 ix86_first_cycle_multipass_data_t next_data
26504 {
26507 }
26508 }
26510 /* Deallocate target data. */
26511 static void
26513 {
26514 ix86_first_cycle_multipass_data_t data
26518 {
26522 }
26523 }
26525 /* Prepare for scheduling pass. */
26526 static void
26530 {
26531 /* Install scheduling hooks for current CPU. Some of these hooks are used
26532 in time-critical parts of the scheduler, so we only set them up when
26533 they are actually used. */
26535 {
26540 /* Do not perform multipass scheduling for pre-reload schedule
26541 to save compile time. */
26543 {
26559 /* Set decoder parameters. */
26564 }
26565 /* ... Fall through ... */
26575 }
26576 }
26578 \f
26579 /* Compute the alignment given to a constant that is being placed in memory.
26580 EXP is the constant and ALIGN is the alignment that the object would
26581 ordinarily have.
26582 The value of this function is used instead of that alignment to align
26583 the object. */
26585 int
26587 {
26590 {
26595 }
26601 }
26603 /* Compute the alignment for a static variable.
26604 TYPE is the data type, and ALIGN is the alignment that
26605 the object would ordinarily have. The value of this function is used
26606 instead of that alignment to align the object. */
26608 int
26610 {
26611 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26612 for symbols from other compilation units or symbols that don't need
26613 to bind locally. In order to preserve some ABI compatibility with
26614 those compilers, ensure we don't decrease alignment from what we
26615 used to assume. */
26617 int max_align_compat
26620 /* A data structure, equal or greater than the size of a cache line
26621 (64 bytes in the Pentium 4 and other recent Intel processors, including
26622 processors based on Intel Core microarchitecture) should be aligned
26623 so that its base address is a multiple of a cache line size. */
26625 int max_align
26635 {
26642 }
26644 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26645 to 16byte boundary. */
26647 {
26654 }
26660 {
26665 }
26667 {
26674 }
26679 {
26684 }
26687 {
26692 }
26695 }
26697 /* Compute the alignment for a local variable or a stack slot. EXP is
26698 the data type or decl itself, MODE is the widest mode available and
26699 ALIGN is the alignment that the object would ordinarily have. The
26700 value of this macro is used instead of that alignment to align the
26701 object. */
26703 unsigned int
26706 {
26710 {
26713 }
26714 else
26715 {
26718 }
26720 /* Don't do dynamic stack realignment for long long objects with
26721 -mpreferred-stack-boundary=2. */
26730 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26731 register in MODE. We will return the largest alignment of XF
26732 and DF. */
26734 {
26738 }
26740 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26741 to 16byte boundary. Exact wording is:
26743 An array uses the same alignment as its elements, except that a local or
26744 global array variable of length at least 16 bytes or
26745 a C99 variable-length array variable always has alignment of at least 16 bytes.
26747 This was added to allow use of aligned SSE instructions at arrays. This
26748 rule is meant for static storage (where compiler can not do the analysis
26749 by itself). We follow it for automatic variables only when convenient.
26750 We fully control everything in the function compiled and functions from
26751 other unit can not rely on the alignment.
26753 Exclude va_list type. It is the common case of local array where
26754 we can not benefit from the alignment.
26756 TODO: Probably one should optimize for size only when var is not escaping. */
26759 {
26769 }
26771 {
26776 }
26778 {
26784 }
26789 {
26794 }
26797 {
26803 }
26805 }
26807 /* Compute the minimum required alignment for dynamic stack realignment
26808 purposes for a local variable, parameter or a stack slot. EXP is
26809 the data type or decl itself, MODE is its mode and ALIGN is the
26810 alignment that the object would ordinarily have. */
26812 unsigned int
26815 {
26819 {
26822 }
26823 else
26824 {
26827 }
26832 /* Don't do dynamic stack realignment for long long objects with
26833 -mpreferred-stack-boundary=2. */
26840 }
26841 \f
26842 /* Find a location for the static chain incoming to a nested function.
26843 This is a register, unless all free registers are used by arguments. */
26845 static rtx
26847 {
26854 {
26855 /* We always use R10 in 64-bit mode. */
26857 }
26858 else
26859 {
26860 tree fntype;
26863 /* By default in 32-bit mode we use ECX to pass the static chain. */
26869 {
26870 /* Fastcall functions use ecx/edx for arguments, which leaves
26871 us with EAX for the static chain.
26872 Thiscall functions use ecx for arguments, which also
26873 leaves us with EAX for the static chain. */
26875 }
26877 {
26878 /* Thiscall functions use ecx for arguments, which leaves
26879 us with EAX and EDX for the static chain.
26880 We are using for abi-compatibility EAX. */
26882 }
26884 {
26885 /* For regparm 3, we have no free call-clobbered registers in
26886 which to store the static chain. In order to implement this,
26887 we have the trampoline push the static chain to the stack.
26888 However, we can't push a value below the return address when
26889 we call the nested function directly, so we have to use an
26890 alternate entry point. For this we use ESI, and have the
26891 alternate entry point push ESI, so that things appear the
26892 same once we're executing the nested function. */
26894 {
26900 }
26902 }
26903 }
26906 }
26908 /* Emit RTL insns to initialize the variable parts of a trampoline.
26909 FNDECL is the decl of the target address; M_TRAMP is a MEM for
26910 the trampoline, and CHAIN_VALUE is an RTX for the static chain
26911 to be passed to the target function. */
26913 static void
26915 {
26923 {
26926 /* Load the function address to r11. Try to load address using
26927 the shorter movl instead of movabs. We may want to support
26928 movq for kernel mode, but kernel does not use trampolines at
26929 the moment. FNADDR is a 32bit address and may not be in
26930 DImode when ptr_mode == SImode. Always use movl in this
26931 case. */
26934 {
26943 }
26944 else
26945 {
26952 }
26954 /* Load static chain using movabs to r10. Use the shorter movl
26955 instead of movabs when ptr_mode == SImode. */
26957 {
26960 }
26961 else
26962 {
26965 }
26974 /* Jump to r11; the last (unused) byte is a nop, only there to
26975 pad the write out to a single 32-bit store. */
26979 }
26980 else
26981 {
26984 /* Depending on the static chain location, either load a register
26985 with a constant, or push the constant to the stack. All of the
26986 instructions are the same size. */
26989 {
26991 {
26998 }
26999 }
27000 else
27015 /* Compute offset from the end of the jmp to the target function.
27016 In the case in which the trampoline stores the static chain on
27017 the stack, we need to skip the first insn which pushes the
27018 (call-saved) register static chain; this push is 1 byte. */
27025 }
27029 #ifdef HAVE_ENABLE_EXECUTE_STACK
27030 #ifdef CHECK_EXECUTE_STACK_ENABLED
27032 #endif
27035 #endif
27036 }
27037 \f
27038 /* The following file contains several enumerations and data structures
27039 built from the definitions in i386-builtin-types.def. */
27043 /* Table for the ix86 builtin non-function types. */
27046 /* Retrieve an element from the above table, building some of
27047 the types lazily. */
27049 static tree
27051 {
27063 {
27071 }
27072 else
27073 {
27079 else
27087 }
27091 }
27093 /* Table for the ix86 builtin function types. */
27096 /* Retrieve an element from the above table, building some of
27097 the types lazily. */
27099 static tree
27101 {
27102 tree type;
27111 {
27119 {
27122 }
27125 }
27126 else
27127 {
27133 }
27137 }
27140 /* Codes for all the SSE/MMX builtins. */
27141 enum ix86_builtins
27142 {
27143 IX86_BUILTIN_ADDPS,
27144 IX86_BUILTIN_ADDSS,
27145 IX86_BUILTIN_DIVPS,
27146 IX86_BUILTIN_DIVSS,
27147 IX86_BUILTIN_MULPS,
27148 IX86_BUILTIN_MULSS,
27149 IX86_BUILTIN_SUBPS,
27150 IX86_BUILTIN_SUBSS,
27152 IX86_BUILTIN_CMPEQPS,
27153 IX86_BUILTIN_CMPLTPS,
27154 IX86_BUILTIN_CMPLEPS,
27155 IX86_BUILTIN_CMPGTPS,
27156 IX86_BUILTIN_CMPGEPS,
27157 IX86_BUILTIN_CMPNEQPS,
27158 IX86_BUILTIN_CMPNLTPS,
27159 IX86_BUILTIN_CMPNLEPS,
27160 IX86_BUILTIN_CMPNGTPS,
27161 IX86_BUILTIN_CMPNGEPS,
27162 IX86_BUILTIN_CMPORDPS,
27163 IX86_BUILTIN_CMPUNORDPS,
27164 IX86_BUILTIN_CMPEQSS,
27165 IX86_BUILTIN_CMPLTSS,
27166 IX86_BUILTIN_CMPLESS,
27167 IX86_BUILTIN_CMPNEQSS,
27168 IX86_BUILTIN_CMPNLTSS,
27169 IX86_BUILTIN_CMPNLESS,
27170 IX86_BUILTIN_CMPORDSS,
27171 IX86_BUILTIN_CMPUNORDSS,
27173 IX86_BUILTIN_COMIEQSS,
27174 IX86_BUILTIN_COMILTSS,
27175 IX86_BUILTIN_COMILESS,
27176 IX86_BUILTIN_COMIGTSS,
27177 IX86_BUILTIN_COMIGESS,
27178 IX86_BUILTIN_COMINEQSS,
27179 IX86_BUILTIN_UCOMIEQSS,
27180 IX86_BUILTIN_UCOMILTSS,
27181 IX86_BUILTIN_UCOMILESS,
27182 IX86_BUILTIN_UCOMIGTSS,
27183 IX86_BUILTIN_UCOMIGESS,
27184 IX86_BUILTIN_UCOMINEQSS,
27186 IX86_BUILTIN_CVTPI2PS,
27187 IX86_BUILTIN_CVTPS2PI,
27188 IX86_BUILTIN_CVTSI2SS,
27189 IX86_BUILTIN_CVTSI642SS,
27190 IX86_BUILTIN_CVTSS2SI,
27191 IX86_BUILTIN_CVTSS2SI64,
27192 IX86_BUILTIN_CVTTPS2PI,
27193 IX86_BUILTIN_CVTTSS2SI,
27194 IX86_BUILTIN_CVTTSS2SI64,
27196 IX86_BUILTIN_MAXPS,
27197 IX86_BUILTIN_MAXSS,
27198 IX86_BUILTIN_MINPS,
27199 IX86_BUILTIN_MINSS,
27201 IX86_BUILTIN_LOADUPS,
27202 IX86_BUILTIN_STOREUPS,
27203 IX86_BUILTIN_MOVSS,
27205 IX86_BUILTIN_MOVHLPS,
27206 IX86_BUILTIN_MOVLHPS,
27207 IX86_BUILTIN_LOADHPS,
27208 IX86_BUILTIN_LOADLPS,
27209 IX86_BUILTIN_STOREHPS,
27210 IX86_BUILTIN_STORELPS,
27212 IX86_BUILTIN_MASKMOVQ,
27213 IX86_BUILTIN_MOVMSKPS,
27214 IX86_BUILTIN_PMOVMSKB,
27216 IX86_BUILTIN_MOVNTPS,
27217 IX86_BUILTIN_MOVNTQ,
27219 IX86_BUILTIN_LOADDQU,
27220 IX86_BUILTIN_STOREDQU,
27222 IX86_BUILTIN_PACKSSWB,
27223 IX86_BUILTIN_PACKSSDW,
27224 IX86_BUILTIN_PACKUSWB,
27226 IX86_BUILTIN_PADDB,
27227 IX86_BUILTIN_PADDW,
27228 IX86_BUILTIN_PADDD,
27229 IX86_BUILTIN_PADDQ,
27230 IX86_BUILTIN_PADDSB,
27231 IX86_BUILTIN_PADDSW,
27232 IX86_BUILTIN_PADDUSB,
27233 IX86_BUILTIN_PADDUSW,
27234 IX86_BUILTIN_PSUBB,
27235 IX86_BUILTIN_PSUBW,
27236 IX86_BUILTIN_PSUBD,
27237 IX86_BUILTIN_PSUBQ,
27238 IX86_BUILTIN_PSUBSB,
27239 IX86_BUILTIN_PSUBSW,
27240 IX86_BUILTIN_PSUBUSB,
27241 IX86_BUILTIN_PSUBUSW,
27243 IX86_BUILTIN_PAND,
27244 IX86_BUILTIN_PANDN,
27245 IX86_BUILTIN_POR,
27246 IX86_BUILTIN_PXOR,
27248 IX86_BUILTIN_PAVGB,
27249 IX86_BUILTIN_PAVGW,
27251 IX86_BUILTIN_PCMPEQB,
27252 IX86_BUILTIN_PCMPEQW,
27253 IX86_BUILTIN_PCMPEQD,
27254 IX86_BUILTIN_PCMPGTB,
27255 IX86_BUILTIN_PCMPGTW,
27256 IX86_BUILTIN_PCMPGTD,
27258 IX86_BUILTIN_PMADDWD,
27260 IX86_BUILTIN_PMAXSW,
27261 IX86_BUILTIN_PMAXUB,
27262 IX86_BUILTIN_PMINSW,
27263 IX86_BUILTIN_PMINUB,
27265 IX86_BUILTIN_PMULHUW,
27266 IX86_BUILTIN_PMULHW,
27267 IX86_BUILTIN_PMULLW,
27269 IX86_BUILTIN_PSADBW,
27270 IX86_BUILTIN_PSHUFW,
27272 IX86_BUILTIN_PSLLW,
27273 IX86_BUILTIN_PSLLD,
27274 IX86_BUILTIN_PSLLQ,
27275 IX86_BUILTIN_PSRAW,
27276 IX86_BUILTIN_PSRAD,
27277 IX86_BUILTIN_PSRLW,
27278 IX86_BUILTIN_PSRLD,
27279 IX86_BUILTIN_PSRLQ,
27280 IX86_BUILTIN_PSLLWI,
27281 IX86_BUILTIN_PSLLDI,
27282 IX86_BUILTIN_PSLLQI,
27283 IX86_BUILTIN_PSRAWI,
27284 IX86_BUILTIN_PSRADI,
27285 IX86_BUILTIN_PSRLWI,
27286 IX86_BUILTIN_PSRLDI,
27287 IX86_BUILTIN_PSRLQI,
27289 IX86_BUILTIN_PUNPCKHBW,
27290 IX86_BUILTIN_PUNPCKHWD,
27291 IX86_BUILTIN_PUNPCKHDQ,
27292 IX86_BUILTIN_PUNPCKLBW,
27293 IX86_BUILTIN_PUNPCKLWD,
27294 IX86_BUILTIN_PUNPCKLDQ,
27296 IX86_BUILTIN_SHUFPS,
27298 IX86_BUILTIN_RCPPS,
27299 IX86_BUILTIN_RCPSS,
27300 IX86_BUILTIN_RSQRTPS,
27301 IX86_BUILTIN_RSQRTPS_NR,
27302 IX86_BUILTIN_RSQRTSS,
27303 IX86_BUILTIN_RSQRTF,
27304 IX86_BUILTIN_SQRTPS,
27305 IX86_BUILTIN_SQRTPS_NR,
27306 IX86_BUILTIN_SQRTSS,
27308 IX86_BUILTIN_UNPCKHPS,
27309 IX86_BUILTIN_UNPCKLPS,
27311 IX86_BUILTIN_ANDPS,
27312 IX86_BUILTIN_ANDNPS,
27313 IX86_BUILTIN_ORPS,
27314 IX86_BUILTIN_XORPS,
27316 IX86_BUILTIN_EMMS,
27317 IX86_BUILTIN_LDMXCSR,
27318 IX86_BUILTIN_STMXCSR,
27319 IX86_BUILTIN_SFENCE,
27321 IX86_BUILTIN_FXSAVE,
27322 IX86_BUILTIN_FXRSTOR,
27323 IX86_BUILTIN_FXSAVE64,
27324 IX86_BUILTIN_FXRSTOR64,
27326 IX86_BUILTIN_XSAVE,
27327 IX86_BUILTIN_XRSTOR,
27328 IX86_BUILTIN_XSAVE64,
27329 IX86_BUILTIN_XRSTOR64,
27331 IX86_BUILTIN_XSAVEOPT,
27332 IX86_BUILTIN_XSAVEOPT64,
27334 IX86_BUILTIN_XSAVEC,
27335 IX86_BUILTIN_XSAVEC64,
27337 IX86_BUILTIN_XSAVES,
27338 IX86_BUILTIN_XRSTORS,
27339 IX86_BUILTIN_XSAVES64,
27340 IX86_BUILTIN_XRSTORS64,
27342 /* 3DNow! Original */
27343 IX86_BUILTIN_FEMMS,
27344 IX86_BUILTIN_PAVGUSB,
27345 IX86_BUILTIN_PF2ID,
27346 IX86_BUILTIN_PFACC,
27347 IX86_BUILTIN_PFADD,
27348 IX86_BUILTIN_PFCMPEQ,
27349 IX86_BUILTIN_PFCMPGE,
27350 IX86_BUILTIN_PFCMPGT,
27351 IX86_BUILTIN_PFMAX,
27352 IX86_BUILTIN_PFMIN,
27353 IX86_BUILTIN_PFMUL,
27354 IX86_BUILTIN_PFRCP,
27355 IX86_BUILTIN_PFRCPIT1,
27356 IX86_BUILTIN_PFRCPIT2,
27357 IX86_BUILTIN_PFRSQIT1,
27358 IX86_BUILTIN_PFRSQRT,
27359 IX86_BUILTIN_PFSUB,
27360 IX86_BUILTIN_PFSUBR,
27361 IX86_BUILTIN_PI2FD,
27362 IX86_BUILTIN_PMULHRW,
27364 /* 3DNow! Athlon Extensions */
27365 IX86_BUILTIN_PF2IW,
27366 IX86_BUILTIN_PFNACC,
27367 IX86_BUILTIN_PFPNACC,
27368 IX86_BUILTIN_PI2FW,
27369 IX86_BUILTIN_PSWAPDSI,
27370 IX86_BUILTIN_PSWAPDSF,
27372 /* SSE2 */
27373 IX86_BUILTIN_ADDPD,
27374 IX86_BUILTIN_ADDSD,
27375 IX86_BUILTIN_DIVPD,
27376 IX86_BUILTIN_DIVSD,
27377 IX86_BUILTIN_MULPD,
27378 IX86_BUILTIN_MULSD,
27379 IX86_BUILTIN_SUBPD,
27380 IX86_BUILTIN_SUBSD,
27382 IX86_BUILTIN_CMPEQPD,
27383 IX86_BUILTIN_CMPLTPD,
27384 IX86_BUILTIN_CMPLEPD,
27385 IX86_BUILTIN_CMPGTPD,
27386 IX86_BUILTIN_CMPGEPD,
27387 IX86_BUILTIN_CMPNEQPD,
27388 IX86_BUILTIN_CMPNLTPD,
27389 IX86_BUILTIN_CMPNLEPD,
27390 IX86_BUILTIN_CMPNGTPD,
27391 IX86_BUILTIN_CMPNGEPD,
27392 IX86_BUILTIN_CMPORDPD,
27393 IX86_BUILTIN_CMPUNORDPD,
27394 IX86_BUILTIN_CMPEQSD,
27395 IX86_BUILTIN_CMPLTSD,
27396 IX86_BUILTIN_CMPLESD,
27397 IX86_BUILTIN_CMPNEQSD,
27398 IX86_BUILTIN_CMPNLTSD,
27399 IX86_BUILTIN_CMPNLESD,
27400 IX86_BUILTIN_CMPORDSD,
27401 IX86_BUILTIN_CMPUNORDSD,
27403 IX86_BUILTIN_COMIEQSD,
27404 IX86_BUILTIN_COMILTSD,
27405 IX86_BUILTIN_COMILESD,
27406 IX86_BUILTIN_COMIGTSD,
27407 IX86_BUILTIN_COMIGESD,
27408 IX86_BUILTIN_COMINEQSD,
27409 IX86_BUILTIN_UCOMIEQSD,
27410 IX86_BUILTIN_UCOMILTSD,
27411 IX86_BUILTIN_UCOMILESD,
27412 IX86_BUILTIN_UCOMIGTSD,
27413 IX86_BUILTIN_UCOMIGESD,
27414 IX86_BUILTIN_UCOMINEQSD,
27416 IX86_BUILTIN_MAXPD,
27417 IX86_BUILTIN_MAXSD,
27418 IX86_BUILTIN_MINPD,
27419 IX86_BUILTIN_MINSD,
27421 IX86_BUILTIN_ANDPD,
27422 IX86_BUILTIN_ANDNPD,
27423 IX86_BUILTIN_ORPD,
27424 IX86_BUILTIN_XORPD,
27426 IX86_BUILTIN_SQRTPD,
27427 IX86_BUILTIN_SQRTSD,
27429 IX86_BUILTIN_UNPCKHPD,
27430 IX86_BUILTIN_UNPCKLPD,
27432 IX86_BUILTIN_SHUFPD,
27434 IX86_BUILTIN_LOADUPD,
27435 IX86_BUILTIN_STOREUPD,
27436 IX86_BUILTIN_MOVSD,
27438 IX86_BUILTIN_LOADHPD,
27439 IX86_BUILTIN_LOADLPD,
27441 IX86_BUILTIN_CVTDQ2PD,
27442 IX86_BUILTIN_CVTDQ2PS,
27444 IX86_BUILTIN_CVTPD2DQ,
27445 IX86_BUILTIN_CVTPD2PI,
27446 IX86_BUILTIN_CVTPD2PS,
27447 IX86_BUILTIN_CVTTPD2DQ,
27448 IX86_BUILTIN_CVTTPD2PI,
27450 IX86_BUILTIN_CVTPI2PD,
27451 IX86_BUILTIN_CVTSI2SD,
27452 IX86_BUILTIN_CVTSI642SD,
27454 IX86_BUILTIN_CVTSD2SI,
27455 IX86_BUILTIN_CVTSD2SI64,
27456 IX86_BUILTIN_CVTSD2SS,
27457 IX86_BUILTIN_CVTSS2SD,
27458 IX86_BUILTIN_CVTTSD2SI,
27459 IX86_BUILTIN_CVTTSD2SI64,
27461 IX86_BUILTIN_CVTPS2DQ,
27462 IX86_BUILTIN_CVTPS2PD,
27463 IX86_BUILTIN_CVTTPS2DQ,
27465 IX86_BUILTIN_MOVNTI,
27466 IX86_BUILTIN_MOVNTI64,
27467 IX86_BUILTIN_MOVNTPD,
27468 IX86_BUILTIN_MOVNTDQ,
27470 IX86_BUILTIN_MOVQ128,
27472 /* SSE2 MMX */
27473 IX86_BUILTIN_MASKMOVDQU,
27474 IX86_BUILTIN_MOVMSKPD,
27475 IX86_BUILTIN_PMOVMSKB128,
27477 IX86_BUILTIN_PACKSSWB128,
27478 IX86_BUILTIN_PACKSSDW128,
27479 IX86_BUILTIN_PACKUSWB128,
27481 IX86_BUILTIN_PADDB128,
27482 IX86_BUILTIN_PADDW128,
27483 IX86_BUILTIN_PADDD128,
27484 IX86_BUILTIN_PADDQ128,
27485 IX86_BUILTIN_PADDSB128,
27486 IX86_BUILTIN_PADDSW128,
27487 IX86_BUILTIN_PADDUSB128,
27488 IX86_BUILTIN_PADDUSW128,
27489 IX86_BUILTIN_PSUBB128,
27490 IX86_BUILTIN_PSUBW128,
27491 IX86_BUILTIN_PSUBD128,
27492 IX86_BUILTIN_PSUBQ128,
27493 IX86_BUILTIN_PSUBSB128,
27494 IX86_BUILTIN_PSUBSW128,
27495 IX86_BUILTIN_PSUBUSB128,
27496 IX86_BUILTIN_PSUBUSW128,
27498 IX86_BUILTIN_PAND128,
27499 IX86_BUILTIN_PANDN128,
27500 IX86_BUILTIN_POR128,
27501 IX86_BUILTIN_PXOR128,
27503 IX86_BUILTIN_PAVGB128,
27504 IX86_BUILTIN_PAVGW128,
27506 IX86_BUILTIN_PCMPEQB128,
27507 IX86_BUILTIN_PCMPEQW128,
27508 IX86_BUILTIN_PCMPEQD128,
27509 IX86_BUILTIN_PCMPGTB128,
27510 IX86_BUILTIN_PCMPGTW128,
27511 IX86_BUILTIN_PCMPGTD128,
27513 IX86_BUILTIN_PMADDWD128,
27515 IX86_BUILTIN_PMAXSW128,
27516 IX86_BUILTIN_PMAXUB128,
27517 IX86_BUILTIN_PMINSW128,
27518 IX86_BUILTIN_PMINUB128,
27520 IX86_BUILTIN_PMULUDQ,
27521 IX86_BUILTIN_PMULUDQ128,
27522 IX86_BUILTIN_PMULHUW128,
27523 IX86_BUILTIN_PMULHW128,
27524 IX86_BUILTIN_PMULLW128,
27526 IX86_BUILTIN_PSADBW128,
27527 IX86_BUILTIN_PSHUFHW,
27528 IX86_BUILTIN_PSHUFLW,
27529 IX86_BUILTIN_PSHUFD,
27531 IX86_BUILTIN_PSLLDQI128,
27532 IX86_BUILTIN_PSLLWI128,
27533 IX86_BUILTIN_PSLLDI128,
27534 IX86_BUILTIN_PSLLQI128,
27535 IX86_BUILTIN_PSRAWI128,
27536 IX86_BUILTIN_PSRADI128,
27537 IX86_BUILTIN_PSRLDQI128,
27538 IX86_BUILTIN_PSRLWI128,
27539 IX86_BUILTIN_PSRLDI128,
27540 IX86_BUILTIN_PSRLQI128,
27542 IX86_BUILTIN_PSLLDQ128,
27543 IX86_BUILTIN_PSLLW128,
27544 IX86_BUILTIN_PSLLD128,
27545 IX86_BUILTIN_PSLLQ128,
27546 IX86_BUILTIN_PSRAW128,
27547 IX86_BUILTIN_PSRAD128,
27548 IX86_BUILTIN_PSRLW128,
27549 IX86_BUILTIN_PSRLD128,
27550 IX86_BUILTIN_PSRLQ128,
27552 IX86_BUILTIN_PUNPCKHBW128,
27553 IX86_BUILTIN_PUNPCKHWD128,
27554 IX86_BUILTIN_PUNPCKHDQ128,
27555 IX86_BUILTIN_PUNPCKHQDQ128,
27556 IX86_BUILTIN_PUNPCKLBW128,
27557 IX86_BUILTIN_PUNPCKLWD128,
27558 IX86_BUILTIN_PUNPCKLDQ128,
27559 IX86_BUILTIN_PUNPCKLQDQ128,
27561 IX86_BUILTIN_CLFLUSH,
27562 IX86_BUILTIN_MFENCE,
27563 IX86_BUILTIN_LFENCE,
27564 IX86_BUILTIN_PAUSE,
27566 IX86_BUILTIN_FNSTENV,
27567 IX86_BUILTIN_FLDENV,
27568 IX86_BUILTIN_FNSTSW,
27569 IX86_BUILTIN_FNCLEX,
27571 IX86_BUILTIN_BSRSI,
27572 IX86_BUILTIN_BSRDI,
27573 IX86_BUILTIN_RDPMC,
27574 IX86_BUILTIN_RDTSC,
27575 IX86_BUILTIN_RDTSCP,
27576 IX86_BUILTIN_ROLQI,
27577 IX86_BUILTIN_ROLHI,
27578 IX86_BUILTIN_RORQI,
27579 IX86_BUILTIN_RORHI,
27581 /* SSE3. */
27582 IX86_BUILTIN_ADDSUBPS,
27583 IX86_BUILTIN_HADDPS,
27584 IX86_BUILTIN_HSUBPS,
27585 IX86_BUILTIN_MOVSHDUP,
27586 IX86_BUILTIN_MOVSLDUP,
27587 IX86_BUILTIN_ADDSUBPD,
27588 IX86_BUILTIN_HADDPD,
27589 IX86_BUILTIN_HSUBPD,
27590 IX86_BUILTIN_LDDQU,
27592 IX86_BUILTIN_MONITOR,
27593 IX86_BUILTIN_MWAIT,
27595 /* SSSE3. */
27596 IX86_BUILTIN_PHADDW,
27597 IX86_BUILTIN_PHADDD,
27598 IX86_BUILTIN_PHADDSW,
27599 IX86_BUILTIN_PHSUBW,
27600 IX86_BUILTIN_PHSUBD,
27601 IX86_BUILTIN_PHSUBSW,
27602 IX86_BUILTIN_PMADDUBSW,
27603 IX86_BUILTIN_PMULHRSW,
27604 IX86_BUILTIN_PSHUFB,
27605 IX86_BUILTIN_PSIGNB,
27606 IX86_BUILTIN_PSIGNW,
27607 IX86_BUILTIN_PSIGND,
27608 IX86_BUILTIN_PALIGNR,
27609 IX86_BUILTIN_PABSB,
27610 IX86_BUILTIN_PABSW,
27611 IX86_BUILTIN_PABSD,
27613 IX86_BUILTIN_PHADDW128,
27614 IX86_BUILTIN_PHADDD128,
27615 IX86_BUILTIN_PHADDSW128,
27616 IX86_BUILTIN_PHSUBW128,
27617 IX86_BUILTIN_PHSUBD128,
27618 IX86_BUILTIN_PHSUBSW128,
27619 IX86_BUILTIN_PMADDUBSW128,
27620 IX86_BUILTIN_PMULHRSW128,
27621 IX86_BUILTIN_PSHUFB128,
27622 IX86_BUILTIN_PSIGNB128,
27623 IX86_BUILTIN_PSIGNW128,
27624 IX86_BUILTIN_PSIGND128,
27625 IX86_BUILTIN_PALIGNR128,
27626 IX86_BUILTIN_PABSB128,
27627 IX86_BUILTIN_PABSW128,
27628 IX86_BUILTIN_PABSD128,
27630 /* AMDFAM10 - SSE4A New Instructions. */
27631 IX86_BUILTIN_MOVNTSD,
27632 IX86_BUILTIN_MOVNTSS,
27633 IX86_BUILTIN_EXTRQI,
27634 IX86_BUILTIN_EXTRQ,
27635 IX86_BUILTIN_INSERTQI,
27636 IX86_BUILTIN_INSERTQ,
27638 /* SSE4.1. */
27639 IX86_BUILTIN_BLENDPD,
27640 IX86_BUILTIN_BLENDPS,
27641 IX86_BUILTIN_BLENDVPD,
27642 IX86_BUILTIN_BLENDVPS,
27643 IX86_BUILTIN_PBLENDVB128,
27644 IX86_BUILTIN_PBLENDW128,
27646 IX86_BUILTIN_DPPD,
27647 IX86_BUILTIN_DPPS,
27649 IX86_BUILTIN_INSERTPS128,
27651 IX86_BUILTIN_MOVNTDQA,
27652 IX86_BUILTIN_MPSADBW128,
27653 IX86_BUILTIN_PACKUSDW128,
27654 IX86_BUILTIN_PCMPEQQ,
27655 IX86_BUILTIN_PHMINPOSUW128,
27657 IX86_BUILTIN_PMAXSB128,
27658 IX86_BUILTIN_PMAXSD128,
27659 IX86_BUILTIN_PMAXUD128,
27660 IX86_BUILTIN_PMAXUW128,
27662 IX86_BUILTIN_PMINSB128,
27663 IX86_BUILTIN_PMINSD128,
27664 IX86_BUILTIN_PMINUD128,
27665 IX86_BUILTIN_PMINUW128,
27667 IX86_BUILTIN_PMOVSXBW128,
27668 IX86_BUILTIN_PMOVSXBD128,
27669 IX86_BUILTIN_PMOVSXBQ128,
27670 IX86_BUILTIN_PMOVSXWD128,
27671 IX86_BUILTIN_PMOVSXWQ128,
27672 IX86_BUILTIN_PMOVSXDQ128,
27674 IX86_BUILTIN_PMOVZXBW128,
27675 IX86_BUILTIN_PMOVZXBD128,
27676 IX86_BUILTIN_PMOVZXBQ128,
27677 IX86_BUILTIN_PMOVZXWD128,
27678 IX86_BUILTIN_PMOVZXWQ128,
27679 IX86_BUILTIN_PMOVZXDQ128,
27681 IX86_BUILTIN_PMULDQ128,
27682 IX86_BUILTIN_PMULLD128,
27684 IX86_BUILTIN_ROUNDSD,
27685 IX86_BUILTIN_ROUNDSS,
27687 IX86_BUILTIN_ROUNDPD,
27688 IX86_BUILTIN_ROUNDPS,
27690 IX86_BUILTIN_FLOORPD,
27691 IX86_BUILTIN_CEILPD,
27692 IX86_BUILTIN_TRUNCPD,
27693 IX86_BUILTIN_RINTPD,
27694 IX86_BUILTIN_ROUNDPD_AZ,
27696 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27697 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27698 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27700 IX86_BUILTIN_FLOORPS,
27701 IX86_BUILTIN_CEILPS,
27702 IX86_BUILTIN_TRUNCPS,
27703 IX86_BUILTIN_RINTPS,
27704 IX86_BUILTIN_ROUNDPS_AZ,
27706 IX86_BUILTIN_FLOORPS_SFIX,
27707 IX86_BUILTIN_CEILPS_SFIX,
27708 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27710 IX86_BUILTIN_PTESTZ,
27711 IX86_BUILTIN_PTESTC,
27712 IX86_BUILTIN_PTESTNZC,
27714 IX86_BUILTIN_VEC_INIT_V2SI,
27715 IX86_BUILTIN_VEC_INIT_V4HI,
27716 IX86_BUILTIN_VEC_INIT_V8QI,
27717 IX86_BUILTIN_VEC_EXT_V2DF,
27718 IX86_BUILTIN_VEC_EXT_V2DI,
27719 IX86_BUILTIN_VEC_EXT_V4SF,
27720 IX86_BUILTIN_VEC_EXT_V4SI,
27721 IX86_BUILTIN_VEC_EXT_V8HI,
27722 IX86_BUILTIN_VEC_EXT_V2SI,
27723 IX86_BUILTIN_VEC_EXT_V4HI,
27724 IX86_BUILTIN_VEC_EXT_V16QI,
27725 IX86_BUILTIN_VEC_SET_V2DI,
27726 IX86_BUILTIN_VEC_SET_V4SF,
27727 IX86_BUILTIN_VEC_SET_V4SI,
27728 IX86_BUILTIN_VEC_SET_V8HI,
27729 IX86_BUILTIN_VEC_SET_V4HI,
27730 IX86_BUILTIN_VEC_SET_V16QI,
27732 IX86_BUILTIN_VEC_PACK_SFIX,
27733 IX86_BUILTIN_VEC_PACK_SFIX256,
27735 /* SSE4.2. */
27736 IX86_BUILTIN_CRC32QI,
27737 IX86_BUILTIN_CRC32HI,
27738 IX86_BUILTIN_CRC32SI,
27739 IX86_BUILTIN_CRC32DI,
27741 IX86_BUILTIN_PCMPESTRI128,
27742 IX86_BUILTIN_PCMPESTRM128,
27743 IX86_BUILTIN_PCMPESTRA128,
27744 IX86_BUILTIN_PCMPESTRC128,
27745 IX86_BUILTIN_PCMPESTRO128,
27746 IX86_BUILTIN_PCMPESTRS128,
27747 IX86_BUILTIN_PCMPESTRZ128,
27748 IX86_BUILTIN_PCMPISTRI128,
27749 IX86_BUILTIN_PCMPISTRM128,
27750 IX86_BUILTIN_PCMPISTRA128,
27751 IX86_BUILTIN_PCMPISTRC128,
27752 IX86_BUILTIN_PCMPISTRO128,
27753 IX86_BUILTIN_PCMPISTRS128,
27754 IX86_BUILTIN_PCMPISTRZ128,
27756 IX86_BUILTIN_PCMPGTQ,
27758 /* AES instructions */
27759 IX86_BUILTIN_AESENC128,
27760 IX86_BUILTIN_AESENCLAST128,
27761 IX86_BUILTIN_AESDEC128,
27762 IX86_BUILTIN_AESDECLAST128,
27763 IX86_BUILTIN_AESIMC128,
27764 IX86_BUILTIN_AESKEYGENASSIST128,
27766 /* PCLMUL instruction */
27767 IX86_BUILTIN_PCLMULQDQ128,
27769 /* AVX */
27770 IX86_BUILTIN_ADDPD256,
27771 IX86_BUILTIN_ADDPS256,
27772 IX86_BUILTIN_ADDSUBPD256,
27773 IX86_BUILTIN_ADDSUBPS256,
27774 IX86_BUILTIN_ANDPD256,
27775 IX86_BUILTIN_ANDPS256,
27776 IX86_BUILTIN_ANDNPD256,
27777 IX86_BUILTIN_ANDNPS256,
27778 IX86_BUILTIN_BLENDPD256,
27779 IX86_BUILTIN_BLENDPS256,
27780 IX86_BUILTIN_BLENDVPD256,
27781 IX86_BUILTIN_BLENDVPS256,
27782 IX86_BUILTIN_DIVPD256,
27783 IX86_BUILTIN_DIVPS256,
27784 IX86_BUILTIN_DPPS256,
27785 IX86_BUILTIN_HADDPD256,
27786 IX86_BUILTIN_HADDPS256,
27787 IX86_BUILTIN_HSUBPD256,
27788 IX86_BUILTIN_HSUBPS256,
27789 IX86_BUILTIN_MAXPD256,
27790 IX86_BUILTIN_MAXPS256,
27791 IX86_BUILTIN_MINPD256,
27792 IX86_BUILTIN_MINPS256,
27793 IX86_BUILTIN_MULPD256,
27794 IX86_BUILTIN_MULPS256,
27795 IX86_BUILTIN_ORPD256,
27796 IX86_BUILTIN_ORPS256,
27797 IX86_BUILTIN_SHUFPD256,
27798 IX86_BUILTIN_SHUFPS256,
27799 IX86_BUILTIN_SUBPD256,
27800 IX86_BUILTIN_SUBPS256,
27801 IX86_BUILTIN_XORPD256,
27802 IX86_BUILTIN_XORPS256,
27803 IX86_BUILTIN_CMPSD,
27804 IX86_BUILTIN_CMPSS,
27805 IX86_BUILTIN_CMPPD,
27806 IX86_BUILTIN_CMPPS,
27807 IX86_BUILTIN_CMPPD256,
27808 IX86_BUILTIN_CMPPS256,
27809 IX86_BUILTIN_CVTDQ2PD256,
27810 IX86_BUILTIN_CVTDQ2PS256,
27811 IX86_BUILTIN_CVTPD2PS256,
27812 IX86_BUILTIN_CVTPS2DQ256,
27813 IX86_BUILTIN_CVTPS2PD256,
27814 IX86_BUILTIN_CVTTPD2DQ256,
27815 IX86_BUILTIN_CVTPD2DQ256,
27816 IX86_BUILTIN_CVTTPS2DQ256,
27817 IX86_BUILTIN_EXTRACTF128PD256,
27818 IX86_BUILTIN_EXTRACTF128PS256,
27819 IX86_BUILTIN_EXTRACTF128SI256,
27820 IX86_BUILTIN_VZEROALL,
27821 IX86_BUILTIN_VZEROUPPER,
27822 IX86_BUILTIN_VPERMILVARPD,
27823 IX86_BUILTIN_VPERMILVARPS,
27824 IX86_BUILTIN_VPERMILVARPD256,
27825 IX86_BUILTIN_VPERMILVARPS256,
27826 IX86_BUILTIN_VPERMILPD,
27827 IX86_BUILTIN_VPERMILPS,
27828 IX86_BUILTIN_VPERMILPD256,
27829 IX86_BUILTIN_VPERMILPS256,
27830 IX86_BUILTIN_VPERMIL2PD,
27831 IX86_BUILTIN_VPERMIL2PS,
27832 IX86_BUILTIN_VPERMIL2PD256,
27833 IX86_BUILTIN_VPERMIL2PS256,
27834 IX86_BUILTIN_VPERM2F128PD256,
27835 IX86_BUILTIN_VPERM2F128PS256,
27836 IX86_BUILTIN_VPERM2F128SI256,
27837 IX86_BUILTIN_VBROADCASTSS,
27838 IX86_BUILTIN_VBROADCASTSD256,
27839 IX86_BUILTIN_VBROADCASTSS256,
27840 IX86_BUILTIN_VBROADCASTPD256,
27841 IX86_BUILTIN_VBROADCASTPS256,
27842 IX86_BUILTIN_VINSERTF128PD256,
27843 IX86_BUILTIN_VINSERTF128PS256,
27844 IX86_BUILTIN_VINSERTF128SI256,
27845 IX86_BUILTIN_LOADUPD256,
27846 IX86_BUILTIN_LOADUPS256,
27847 IX86_BUILTIN_STOREUPD256,
27848 IX86_BUILTIN_STOREUPS256,
27849 IX86_BUILTIN_LDDQU256,
27850 IX86_BUILTIN_MOVNTDQ256,
27851 IX86_BUILTIN_MOVNTPD256,
27852 IX86_BUILTIN_MOVNTPS256,
27853 IX86_BUILTIN_LOADDQU256,
27854 IX86_BUILTIN_STOREDQU256,
27855 IX86_BUILTIN_MASKLOADPD,
27856 IX86_BUILTIN_MASKLOADPS,
27857 IX86_BUILTIN_MASKSTOREPD,
27858 IX86_BUILTIN_MASKSTOREPS,
27859 IX86_BUILTIN_MASKLOADPD256,
27860 IX86_BUILTIN_MASKLOADPS256,
27861 IX86_BUILTIN_MASKSTOREPD256,
27862 IX86_BUILTIN_MASKSTOREPS256,
27863 IX86_BUILTIN_MOVSHDUP256,
27864 IX86_BUILTIN_MOVSLDUP256,
27865 IX86_BUILTIN_MOVDDUP256,
27867 IX86_BUILTIN_SQRTPD256,
27868 IX86_BUILTIN_SQRTPS256,
27869 IX86_BUILTIN_SQRTPS_NR256,
27870 IX86_BUILTIN_RSQRTPS256,
27871 IX86_BUILTIN_RSQRTPS_NR256,
27873 IX86_BUILTIN_RCPPS256,
27875 IX86_BUILTIN_ROUNDPD256,
27876 IX86_BUILTIN_ROUNDPS256,
27878 IX86_BUILTIN_FLOORPD256,
27879 IX86_BUILTIN_CEILPD256,
27880 IX86_BUILTIN_TRUNCPD256,
27881 IX86_BUILTIN_RINTPD256,
27882 IX86_BUILTIN_ROUNDPD_AZ256,
27884 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
27885 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
27886 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
27888 IX86_BUILTIN_FLOORPS256,
27889 IX86_BUILTIN_CEILPS256,
27890 IX86_BUILTIN_TRUNCPS256,
27891 IX86_BUILTIN_RINTPS256,
27892 IX86_BUILTIN_ROUNDPS_AZ256,
27894 IX86_BUILTIN_FLOORPS_SFIX256,
27895 IX86_BUILTIN_CEILPS_SFIX256,
27896 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
27898 IX86_BUILTIN_UNPCKHPD256,
27899 IX86_BUILTIN_UNPCKLPD256,
27900 IX86_BUILTIN_UNPCKHPS256,
27901 IX86_BUILTIN_UNPCKLPS256,
27903 IX86_BUILTIN_SI256_SI,
27904 IX86_BUILTIN_PS256_PS,
27905 IX86_BUILTIN_PD256_PD,
27906 IX86_BUILTIN_SI_SI256,
27907 IX86_BUILTIN_PS_PS256,
27908 IX86_BUILTIN_PD_PD256,
27910 IX86_BUILTIN_VTESTZPD,
27911 IX86_BUILTIN_VTESTCPD,
27912 IX86_BUILTIN_VTESTNZCPD,
27913 IX86_BUILTIN_VTESTZPS,
27914 IX86_BUILTIN_VTESTCPS,
27915 IX86_BUILTIN_VTESTNZCPS,
27916 IX86_BUILTIN_VTESTZPD256,
27917 IX86_BUILTIN_VTESTCPD256,
27918 IX86_BUILTIN_VTESTNZCPD256,
27919 IX86_BUILTIN_VTESTZPS256,
27920 IX86_BUILTIN_VTESTCPS256,
27921 IX86_BUILTIN_VTESTNZCPS256,
27922 IX86_BUILTIN_PTESTZ256,
27923 IX86_BUILTIN_PTESTC256,
27924 IX86_BUILTIN_PTESTNZC256,
27926 IX86_BUILTIN_MOVMSKPD256,
27927 IX86_BUILTIN_MOVMSKPS256,
27929 /* AVX2 */
27930 IX86_BUILTIN_MPSADBW256,
27931 IX86_BUILTIN_PABSB256,
27932 IX86_BUILTIN_PABSW256,
27933 IX86_BUILTIN_PABSD256,
27934 IX86_BUILTIN_PACKSSDW256,
27935 IX86_BUILTIN_PACKSSWB256,
27936 IX86_BUILTIN_PACKUSDW256,
27937 IX86_BUILTIN_PACKUSWB256,
27938 IX86_BUILTIN_PADDB256,
27939 IX86_BUILTIN_PADDW256,
27940 IX86_BUILTIN_PADDD256,
27941 IX86_BUILTIN_PADDQ256,
27942 IX86_BUILTIN_PADDSB256,
27943 IX86_BUILTIN_PADDSW256,
27944 IX86_BUILTIN_PADDUSB256,
27945 IX86_BUILTIN_PADDUSW256,
27946 IX86_BUILTIN_PALIGNR256,
27947 IX86_BUILTIN_AND256I,
27948 IX86_BUILTIN_ANDNOT256I,
27949 IX86_BUILTIN_PAVGB256,
27950 IX86_BUILTIN_PAVGW256,
27951 IX86_BUILTIN_PBLENDVB256,
27952 IX86_BUILTIN_PBLENDVW256,
27953 IX86_BUILTIN_PCMPEQB256,
27954 IX86_BUILTIN_PCMPEQW256,
27955 IX86_BUILTIN_PCMPEQD256,
27956 IX86_BUILTIN_PCMPEQQ256,
27957 IX86_BUILTIN_PCMPGTB256,
27958 IX86_BUILTIN_PCMPGTW256,
27959 IX86_BUILTIN_PCMPGTD256,
27960 IX86_BUILTIN_PCMPGTQ256,
27961 IX86_BUILTIN_PHADDW256,
27962 IX86_BUILTIN_PHADDD256,
27963 IX86_BUILTIN_PHADDSW256,
27964 IX86_BUILTIN_PHSUBW256,
27965 IX86_BUILTIN_PHSUBD256,
27966 IX86_BUILTIN_PHSUBSW256,
27967 IX86_BUILTIN_PMADDUBSW256,
27968 IX86_BUILTIN_PMADDWD256,
27969 IX86_BUILTIN_PMAXSB256,
27970 IX86_BUILTIN_PMAXSW256,
27971 IX86_BUILTIN_PMAXSD256,
27972 IX86_BUILTIN_PMAXUB256,
27973 IX86_BUILTIN_PMAXUW256,
27974 IX86_BUILTIN_PMAXUD256,
27975 IX86_BUILTIN_PMINSB256,
27976 IX86_BUILTIN_PMINSW256,
27977 IX86_BUILTIN_PMINSD256,
27978 IX86_BUILTIN_PMINUB256,
27979 IX86_BUILTIN_PMINUW256,
27980 IX86_BUILTIN_PMINUD256,
27981 IX86_BUILTIN_PMOVMSKB256,
27982 IX86_BUILTIN_PMOVSXBW256,
27983 IX86_BUILTIN_PMOVSXBD256,
27984 IX86_BUILTIN_PMOVSXBQ256,
27985 IX86_BUILTIN_PMOVSXWD256,
27986 IX86_BUILTIN_PMOVSXWQ256,
27987 IX86_BUILTIN_PMOVSXDQ256,
27988 IX86_BUILTIN_PMOVZXBW256,
27989 IX86_BUILTIN_PMOVZXBD256,
27990 IX86_BUILTIN_PMOVZXBQ256,
27991 IX86_BUILTIN_PMOVZXWD256,
27992 IX86_BUILTIN_PMOVZXWQ256,
27993 IX86_BUILTIN_PMOVZXDQ256,
27994 IX86_BUILTIN_PMULDQ256,
27995 IX86_BUILTIN_PMULHRSW256,
27996 IX86_BUILTIN_PMULHUW256,
27997 IX86_BUILTIN_PMULHW256,
27998 IX86_BUILTIN_PMULLW256,
27999 IX86_BUILTIN_PMULLD256,
28000 IX86_BUILTIN_PMULUDQ256,
28001 IX86_BUILTIN_POR256,
28002 IX86_BUILTIN_PSADBW256,
28003 IX86_BUILTIN_PSHUFB256,
28004 IX86_BUILTIN_PSHUFD256,
28005 IX86_BUILTIN_PSHUFHW256,
28006 IX86_BUILTIN_PSHUFLW256,
28007 IX86_BUILTIN_PSIGNB256,
28008 IX86_BUILTIN_PSIGNW256,
28009 IX86_BUILTIN_PSIGND256,
28010 IX86_BUILTIN_PSLLDQI256,
28011 IX86_BUILTIN_PSLLWI256,
28012 IX86_BUILTIN_PSLLW256,
28013 IX86_BUILTIN_PSLLDI256,
28014 IX86_BUILTIN_PSLLD256,
28015 IX86_BUILTIN_PSLLQI256,
28016 IX86_BUILTIN_PSLLQ256,
28017 IX86_BUILTIN_PSRAWI256,
28018 IX86_BUILTIN_PSRAW256,
28019 IX86_BUILTIN_PSRADI256,
28020 IX86_BUILTIN_PSRAD256,
28021 IX86_BUILTIN_PSRLDQI256,
28022 IX86_BUILTIN_PSRLWI256,
28023 IX86_BUILTIN_PSRLW256,
28024 IX86_BUILTIN_PSRLDI256,
28025 IX86_BUILTIN_PSRLD256,
28026 IX86_BUILTIN_PSRLQI256,
28027 IX86_BUILTIN_PSRLQ256,
28028 IX86_BUILTIN_PSUBB256,
28029 IX86_BUILTIN_PSUBW256,
28030 IX86_BUILTIN_PSUBD256,
28031 IX86_BUILTIN_PSUBQ256,
28032 IX86_BUILTIN_PSUBSB256,
28033 IX86_BUILTIN_PSUBSW256,
28034 IX86_BUILTIN_PSUBUSB256,
28035 IX86_BUILTIN_PSUBUSW256,
28036 IX86_BUILTIN_PUNPCKHBW256,
28037 IX86_BUILTIN_PUNPCKHWD256,
28038 IX86_BUILTIN_PUNPCKHDQ256,
28039 IX86_BUILTIN_PUNPCKHQDQ256,
28040 IX86_BUILTIN_PUNPCKLBW256,
28041 IX86_BUILTIN_PUNPCKLWD256,
28042 IX86_BUILTIN_PUNPCKLDQ256,
28043 IX86_BUILTIN_PUNPCKLQDQ256,
28044 IX86_BUILTIN_PXOR256,
28045 IX86_BUILTIN_MOVNTDQA256,
28046 IX86_BUILTIN_VBROADCASTSS_PS,
28047 IX86_BUILTIN_VBROADCASTSS_PS256,
28048 IX86_BUILTIN_VBROADCASTSD_PD256,
28049 IX86_BUILTIN_VBROADCASTSI256,
28050 IX86_BUILTIN_PBLENDD256,
28051 IX86_BUILTIN_PBLENDD128,
28052 IX86_BUILTIN_PBROADCASTB256,
28053 IX86_BUILTIN_PBROADCASTW256,
28054 IX86_BUILTIN_PBROADCASTD256,
28055 IX86_BUILTIN_PBROADCASTQ256,
28056 IX86_BUILTIN_PBROADCASTB128,
28057 IX86_BUILTIN_PBROADCASTW128,
28058 IX86_BUILTIN_PBROADCASTD128,
28059 IX86_BUILTIN_PBROADCASTQ128,
28060 IX86_BUILTIN_VPERMVARSI256,
28061 IX86_BUILTIN_VPERMDF256,
28062 IX86_BUILTIN_VPERMVARSF256,
28063 IX86_BUILTIN_VPERMDI256,
28064 IX86_BUILTIN_VPERMTI256,
28065 IX86_BUILTIN_VEXTRACT128I256,
28066 IX86_BUILTIN_VINSERT128I256,
28067 IX86_BUILTIN_MASKLOADD,
28068 IX86_BUILTIN_MASKLOADQ,
28069 IX86_BUILTIN_MASKLOADD256,
28070 IX86_BUILTIN_MASKLOADQ256,
28071 IX86_BUILTIN_MASKSTORED,
28072 IX86_BUILTIN_MASKSTOREQ,
28073 IX86_BUILTIN_MASKSTORED256,
28074 IX86_BUILTIN_MASKSTOREQ256,
28075 IX86_BUILTIN_PSLLVV4DI,
28076 IX86_BUILTIN_PSLLVV2DI,
28077 IX86_BUILTIN_PSLLVV8SI,
28078 IX86_BUILTIN_PSLLVV4SI,
28079 IX86_BUILTIN_PSRAVV8SI,
28080 IX86_BUILTIN_PSRAVV4SI,
28081 IX86_BUILTIN_PSRLVV4DI,
28082 IX86_BUILTIN_PSRLVV2DI,
28083 IX86_BUILTIN_PSRLVV8SI,
28084 IX86_BUILTIN_PSRLVV4SI,
28086 IX86_BUILTIN_GATHERSIV2DF,
28087 IX86_BUILTIN_GATHERSIV4DF,
28088 IX86_BUILTIN_GATHERDIV2DF,
28089 IX86_BUILTIN_GATHERDIV4DF,
28090 IX86_BUILTIN_GATHERSIV4SF,
28091 IX86_BUILTIN_GATHERSIV8SF,
28092 IX86_BUILTIN_GATHERDIV4SF,
28093 IX86_BUILTIN_GATHERDIV8SF,
28094 IX86_BUILTIN_GATHERSIV2DI,
28095 IX86_BUILTIN_GATHERSIV4DI,
28096 IX86_BUILTIN_GATHERDIV2DI,
28097 IX86_BUILTIN_GATHERDIV4DI,
28098 IX86_BUILTIN_GATHERSIV4SI,
28099 IX86_BUILTIN_GATHERSIV8SI,
28100 IX86_BUILTIN_GATHERDIV4SI,
28101 IX86_BUILTIN_GATHERDIV8SI,
28103 /* AVX512F */
28104 IX86_BUILTIN_ADDPD512,
28105 IX86_BUILTIN_ADDPS512,
28106 IX86_BUILTIN_ADDSD_ROUND,
28107 IX86_BUILTIN_ADDSS_ROUND,
28108 IX86_BUILTIN_ALIGND512,
28109 IX86_BUILTIN_ALIGNQ512,
28110 IX86_BUILTIN_BLENDMD512,
28111 IX86_BUILTIN_BLENDMPD512,
28112 IX86_BUILTIN_BLENDMPS512,
28113 IX86_BUILTIN_BLENDMQ512,
28114 IX86_BUILTIN_BROADCASTF32X4_512,
28115 IX86_BUILTIN_BROADCASTF64X4_512,
28116 IX86_BUILTIN_BROADCASTI32X4_512,
28117 IX86_BUILTIN_BROADCASTI64X4_512,
28118 IX86_BUILTIN_BROADCASTSD512,
28119 IX86_BUILTIN_BROADCASTSS512,
28120 IX86_BUILTIN_CMPD512,
28121 IX86_BUILTIN_CMPPD512,
28122 IX86_BUILTIN_CMPPS512,
28123 IX86_BUILTIN_CMPQ512,
28124 IX86_BUILTIN_CMPSD_MASK,
28125 IX86_BUILTIN_CMPSS_MASK,
28126 IX86_BUILTIN_COMIDF,
28127 IX86_BUILTIN_COMISF,
28128 IX86_BUILTIN_COMPRESSPD512,
28129 IX86_BUILTIN_COMPRESSPDSTORE512,
28130 IX86_BUILTIN_COMPRESSPS512,
28131 IX86_BUILTIN_COMPRESSPSSTORE512,
28132 IX86_BUILTIN_CVTDQ2PD512,
28133 IX86_BUILTIN_CVTDQ2PS512,
28134 IX86_BUILTIN_CVTPD2DQ512,
28135 IX86_BUILTIN_CVTPD2PS512,
28136 IX86_BUILTIN_CVTPD2UDQ512,
28137 IX86_BUILTIN_CVTPH2PS512,
28138 IX86_BUILTIN_CVTPS2DQ512,
28139 IX86_BUILTIN_CVTPS2PD512,
28140 IX86_BUILTIN_CVTPS2PH512,
28141 IX86_BUILTIN_CVTPS2UDQ512,
28142 IX86_BUILTIN_CVTSD2SS_ROUND,
28143 IX86_BUILTIN_CVTSI2SD64,
28144 IX86_BUILTIN_CVTSI2SS32,
28145 IX86_BUILTIN_CVTSI2SS64,
28146 IX86_BUILTIN_CVTSS2SD_ROUND,
28147 IX86_BUILTIN_CVTTPD2DQ512,
28148 IX86_BUILTIN_CVTTPD2UDQ512,
28149 IX86_BUILTIN_CVTTPS2DQ512,
28150 IX86_BUILTIN_CVTTPS2UDQ512,
28151 IX86_BUILTIN_CVTUDQ2PD512,
28152 IX86_BUILTIN_CVTUDQ2PS512,
28153 IX86_BUILTIN_CVTUSI2SD32,
28154 IX86_BUILTIN_CVTUSI2SD64,
28155 IX86_BUILTIN_CVTUSI2SS32,
28156 IX86_BUILTIN_CVTUSI2SS64,
28157 IX86_BUILTIN_DIVPD512,
28158 IX86_BUILTIN_DIVPS512,
28159 IX86_BUILTIN_DIVSD_ROUND,
28160 IX86_BUILTIN_DIVSS_ROUND,
28161 IX86_BUILTIN_EXPANDPD512,
28162 IX86_BUILTIN_EXPANDPD512Z,
28163 IX86_BUILTIN_EXPANDPDLOAD512,
28164 IX86_BUILTIN_EXPANDPDLOAD512Z,
28165 IX86_BUILTIN_EXPANDPS512,
28166 IX86_BUILTIN_EXPANDPS512Z,
28167 IX86_BUILTIN_EXPANDPSLOAD512,
28168 IX86_BUILTIN_EXPANDPSLOAD512Z,
28169 IX86_BUILTIN_EXTRACTF32X4,
28170 IX86_BUILTIN_EXTRACTF64X4,
28171 IX86_BUILTIN_EXTRACTI32X4,
28172 IX86_BUILTIN_EXTRACTI64X4,
28173 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28174 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28175 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28176 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28177 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28178 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28179 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28180 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28181 IX86_BUILTIN_GETEXPPD512,
28182 IX86_BUILTIN_GETEXPPS512,
28183 IX86_BUILTIN_GETEXPSD128,
28184 IX86_BUILTIN_GETEXPSS128,
28185 IX86_BUILTIN_GETMANTPD512,
28186 IX86_BUILTIN_GETMANTPS512,
28187 IX86_BUILTIN_GETMANTSD128,
28188 IX86_BUILTIN_GETMANTSS128,
28189 IX86_BUILTIN_INSERTF32X4,
28190 IX86_BUILTIN_INSERTF64X4,
28191 IX86_BUILTIN_INSERTI32X4,
28192 IX86_BUILTIN_INSERTI64X4,
28193 IX86_BUILTIN_LOADAPD512,
28194 IX86_BUILTIN_LOADAPS512,
28195 IX86_BUILTIN_LOADDQUDI512,
28196 IX86_BUILTIN_LOADDQUSI512,
28197 IX86_BUILTIN_LOADUPD512,
28198 IX86_BUILTIN_LOADUPS512,
28199 IX86_BUILTIN_MAXPD512,
28200 IX86_BUILTIN_MAXPS512,
28201 IX86_BUILTIN_MAXSD_ROUND,
28202 IX86_BUILTIN_MAXSS_ROUND,
28203 IX86_BUILTIN_MINPD512,
28204 IX86_BUILTIN_MINPS512,
28205 IX86_BUILTIN_MINSD_ROUND,
28206 IX86_BUILTIN_MINSS_ROUND,
28207 IX86_BUILTIN_MOVAPD512,
28208 IX86_BUILTIN_MOVAPS512,
28209 IX86_BUILTIN_MOVDDUP512,
28210 IX86_BUILTIN_MOVDQA32LOAD512,
28211 IX86_BUILTIN_MOVDQA32STORE512,
28212 IX86_BUILTIN_MOVDQA32_512,
28213 IX86_BUILTIN_MOVDQA64LOAD512,
28214 IX86_BUILTIN_MOVDQA64STORE512,
28215 IX86_BUILTIN_MOVDQA64_512,
28216 IX86_BUILTIN_MOVNTDQ512,
28217 IX86_BUILTIN_MOVNTDQA512,
28218 IX86_BUILTIN_MOVNTPD512,
28219 IX86_BUILTIN_MOVNTPS512,
28220 IX86_BUILTIN_MOVSHDUP512,
28221 IX86_BUILTIN_MOVSLDUP512,
28222 IX86_BUILTIN_MULPD512,
28223 IX86_BUILTIN_MULPS512,
28224 IX86_BUILTIN_MULSD_ROUND,
28225 IX86_BUILTIN_MULSS_ROUND,
28226 IX86_BUILTIN_PABSD512,
28227 IX86_BUILTIN_PABSQ512,
28228 IX86_BUILTIN_PADDD512,
28229 IX86_BUILTIN_PADDQ512,
28230 IX86_BUILTIN_PANDD512,
28231 IX86_BUILTIN_PANDND512,
28232 IX86_BUILTIN_PANDNQ512,
28233 IX86_BUILTIN_PANDQ512,
28234 IX86_BUILTIN_PBROADCASTD512,
28235 IX86_BUILTIN_PBROADCASTD512_GPR,
28236 IX86_BUILTIN_PBROADCASTMB512,
28237 IX86_BUILTIN_PBROADCASTMW512,
28238 IX86_BUILTIN_PBROADCASTQ512,
28239 IX86_BUILTIN_PBROADCASTQ512_GPR,
28240 IX86_BUILTIN_PBROADCASTQ512_MEM,
28241 IX86_BUILTIN_PCMPEQD512_MASK,
28242 IX86_BUILTIN_PCMPEQQ512_MASK,
28243 IX86_BUILTIN_PCMPGTD512_MASK,
28244 IX86_BUILTIN_PCMPGTQ512_MASK,
28245 IX86_BUILTIN_PCOMPRESSD512,
28246 IX86_BUILTIN_PCOMPRESSDSTORE512,
28247 IX86_BUILTIN_PCOMPRESSQ512,
28248 IX86_BUILTIN_PCOMPRESSQSTORE512,
28249 IX86_BUILTIN_PEXPANDD512,
28250 IX86_BUILTIN_PEXPANDD512Z,
28251 IX86_BUILTIN_PEXPANDDLOAD512,
28252 IX86_BUILTIN_PEXPANDDLOAD512Z,
28253 IX86_BUILTIN_PEXPANDQ512,
28254 IX86_BUILTIN_PEXPANDQ512Z,
28255 IX86_BUILTIN_PEXPANDQLOAD512,
28256 IX86_BUILTIN_PEXPANDQLOAD512Z,
28257 IX86_BUILTIN_PMAXSD512,
28258 IX86_BUILTIN_PMAXSQ512,
28259 IX86_BUILTIN_PMAXUD512,
28260 IX86_BUILTIN_PMAXUQ512,
28261 IX86_BUILTIN_PMINSD512,
28262 IX86_BUILTIN_PMINSQ512,
28263 IX86_BUILTIN_PMINUD512,
28264 IX86_BUILTIN_PMINUQ512,
28265 IX86_BUILTIN_PMOVDB512,
28266 IX86_BUILTIN_PMOVDB512_MEM,
28267 IX86_BUILTIN_PMOVDW512,
28268 IX86_BUILTIN_PMOVDW512_MEM,
28269 IX86_BUILTIN_PMOVQB512,
28270 IX86_BUILTIN_PMOVQB512_MEM,
28271 IX86_BUILTIN_PMOVQD512,
28272 IX86_BUILTIN_PMOVQD512_MEM,
28273 IX86_BUILTIN_PMOVQW512,
28274 IX86_BUILTIN_PMOVQW512_MEM,
28275 IX86_BUILTIN_PMOVSDB512,
28276 IX86_BUILTIN_PMOVSDB512_MEM,
28277 IX86_BUILTIN_PMOVSDW512,
28278 IX86_BUILTIN_PMOVSDW512_MEM,
28279 IX86_BUILTIN_PMOVSQB512,
28280 IX86_BUILTIN_PMOVSQB512_MEM,
28281 IX86_BUILTIN_PMOVSQD512,
28282 IX86_BUILTIN_PMOVSQD512_MEM,
28283 IX86_BUILTIN_PMOVSQW512,
28284 IX86_BUILTIN_PMOVSQW512_MEM,
28285 IX86_BUILTIN_PMOVSXBD512,
28286 IX86_BUILTIN_PMOVSXBQ512,
28287 IX86_BUILTIN_PMOVSXDQ512,
28288 IX86_BUILTIN_PMOVSXWD512,
28289 IX86_BUILTIN_PMOVSXWQ512,
28290 IX86_BUILTIN_PMOVUSDB512,
28291 IX86_BUILTIN_PMOVUSDB512_MEM,
28292 IX86_BUILTIN_PMOVUSDW512,
28293 IX86_BUILTIN_PMOVUSDW512_MEM,
28294 IX86_BUILTIN_PMOVUSQB512,
28295 IX86_BUILTIN_PMOVUSQB512_MEM,
28296 IX86_BUILTIN_PMOVUSQD512,
28297 IX86_BUILTIN_PMOVUSQD512_MEM,
28298 IX86_BUILTIN_PMOVUSQW512,
28299 IX86_BUILTIN_PMOVUSQW512_MEM,
28300 IX86_BUILTIN_PMOVZXBD512,
28301 IX86_BUILTIN_PMOVZXBQ512,
28302 IX86_BUILTIN_PMOVZXDQ512,
28303 IX86_BUILTIN_PMOVZXWD512,
28304 IX86_BUILTIN_PMOVZXWQ512,
28305 IX86_BUILTIN_PMULDQ512,
28306 IX86_BUILTIN_PMULLD512,
28307 IX86_BUILTIN_PMULUDQ512,
28308 IX86_BUILTIN_PORD512,
28309 IX86_BUILTIN_PORQ512,
28310 IX86_BUILTIN_PROLD512,
28311 IX86_BUILTIN_PROLQ512,
28312 IX86_BUILTIN_PROLVD512,
28313 IX86_BUILTIN_PROLVQ512,
28314 IX86_BUILTIN_PRORD512,
28315 IX86_BUILTIN_PRORQ512,
28316 IX86_BUILTIN_PRORVD512,
28317 IX86_BUILTIN_PRORVQ512,
28318 IX86_BUILTIN_PSHUFD512,
28319 IX86_BUILTIN_PSLLD512,
28320 IX86_BUILTIN_PSLLDI512,
28321 IX86_BUILTIN_PSLLQ512,
28322 IX86_BUILTIN_PSLLQI512,
28323 IX86_BUILTIN_PSLLVV16SI,
28324 IX86_BUILTIN_PSLLVV8DI,
28325 IX86_BUILTIN_PSRAD512,
28326 IX86_BUILTIN_PSRADI512,
28327 IX86_BUILTIN_PSRAQ512,
28328 IX86_BUILTIN_PSRAQI512,
28329 IX86_BUILTIN_PSRAVV16SI,
28330 IX86_BUILTIN_PSRAVV8DI,
28331 IX86_BUILTIN_PSRLD512,
28332 IX86_BUILTIN_PSRLDI512,
28333 IX86_BUILTIN_PSRLQ512,
28334 IX86_BUILTIN_PSRLQI512,
28335 IX86_BUILTIN_PSRLVV16SI,
28336 IX86_BUILTIN_PSRLVV8DI,
28337 IX86_BUILTIN_PSUBD512,
28338 IX86_BUILTIN_PSUBQ512,
28339 IX86_BUILTIN_PTESTMD512,
28340 IX86_BUILTIN_PTESTMQ512,
28341 IX86_BUILTIN_PTESTNMD512,
28342 IX86_BUILTIN_PTESTNMQ512,
28343 IX86_BUILTIN_PUNPCKHDQ512,
28344 IX86_BUILTIN_PUNPCKHQDQ512,
28345 IX86_BUILTIN_PUNPCKLDQ512,
28346 IX86_BUILTIN_PUNPCKLQDQ512,
28347 IX86_BUILTIN_PXORD512,
28348 IX86_BUILTIN_PXORQ512,
28349 IX86_BUILTIN_RCP14PD512,
28350 IX86_BUILTIN_RCP14PS512,
28351 IX86_BUILTIN_RCP14SD,
28352 IX86_BUILTIN_RCP14SS,
28353 IX86_BUILTIN_RNDSCALEPD,
28354 IX86_BUILTIN_RNDSCALEPS,
28355 IX86_BUILTIN_RNDSCALESD,
28356 IX86_BUILTIN_RNDSCALESS,
28357 IX86_BUILTIN_RSQRT14PD512,
28358 IX86_BUILTIN_RSQRT14PS512,
28359 IX86_BUILTIN_RSQRT14SD,
28360 IX86_BUILTIN_RSQRT14SS,
28361 IX86_BUILTIN_SCALEFPD512,
28362 IX86_BUILTIN_SCALEFPS512,
28363 IX86_BUILTIN_SCALEFSD,
28364 IX86_BUILTIN_SCALEFSS,
28365 IX86_BUILTIN_SHUFPD512,
28366 IX86_BUILTIN_SHUFPS512,
28367 IX86_BUILTIN_SHUF_F32x4,
28368 IX86_BUILTIN_SHUF_F64x2,
28369 IX86_BUILTIN_SHUF_I32x4,
28370 IX86_BUILTIN_SHUF_I64x2,
28371 IX86_BUILTIN_SQRTPD512,
28372 IX86_BUILTIN_SQRTPD512_MASK,
28373 IX86_BUILTIN_SQRTPS512_MASK,
28374 IX86_BUILTIN_SQRTPS_NR512,
28375 IX86_BUILTIN_SQRTSD_ROUND,
28376 IX86_BUILTIN_SQRTSS_ROUND,
28377 IX86_BUILTIN_STOREAPD512,
28378 IX86_BUILTIN_STOREAPS512,
28379 IX86_BUILTIN_STOREDQUDI512,
28380 IX86_BUILTIN_STOREDQUSI512,
28381 IX86_BUILTIN_STOREUPD512,
28382 IX86_BUILTIN_STOREUPS512,
28383 IX86_BUILTIN_SUBPD512,
28384 IX86_BUILTIN_SUBPS512,
28385 IX86_BUILTIN_SUBSD_ROUND,
28386 IX86_BUILTIN_SUBSS_ROUND,
28387 IX86_BUILTIN_UCMPD512,
28388 IX86_BUILTIN_UCMPQ512,
28389 IX86_BUILTIN_UNPCKHPD512,
28390 IX86_BUILTIN_UNPCKHPS512,
28391 IX86_BUILTIN_UNPCKLPD512,
28392 IX86_BUILTIN_UNPCKLPS512,
28393 IX86_BUILTIN_VCVTSD2SI32,
28394 IX86_BUILTIN_VCVTSD2SI64,
28395 IX86_BUILTIN_VCVTSD2USI32,
28396 IX86_BUILTIN_VCVTSD2USI64,
28397 IX86_BUILTIN_VCVTSS2SI32,
28398 IX86_BUILTIN_VCVTSS2SI64,
28399 IX86_BUILTIN_VCVTSS2USI32,
28400 IX86_BUILTIN_VCVTSS2USI64,
28401 IX86_BUILTIN_VCVTTSD2SI32,
28402 IX86_BUILTIN_VCVTTSD2SI64,
28403 IX86_BUILTIN_VCVTTSD2USI32,
28404 IX86_BUILTIN_VCVTTSD2USI64,
28405 IX86_BUILTIN_VCVTTSS2SI32,
28406 IX86_BUILTIN_VCVTTSS2SI64,
28407 IX86_BUILTIN_VCVTTSS2USI32,
28408 IX86_BUILTIN_VCVTTSS2USI64,
28409 IX86_BUILTIN_VFMADDPD512_MASK,
28410 IX86_BUILTIN_VFMADDPD512_MASK3,
28411 IX86_BUILTIN_VFMADDPD512_MASKZ,
28412 IX86_BUILTIN_VFMADDPS512_MASK,
28413 IX86_BUILTIN_VFMADDPS512_MASK3,
28414 IX86_BUILTIN_VFMADDPS512_MASKZ,
28415 IX86_BUILTIN_VFMADDSD3_ROUND,
28416 IX86_BUILTIN_VFMADDSS3_ROUND,
28417 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28418 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28419 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28420 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28421 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28422 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28423 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28424 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28425 IX86_BUILTIN_VFMSUBPD512_MASK3,
28426 IX86_BUILTIN_VFMSUBPS512_MASK3,
28427 IX86_BUILTIN_VFMSUBSD3_MASK3,
28428 IX86_BUILTIN_VFMSUBSS3_MASK3,
28429 IX86_BUILTIN_VFNMADDPD512_MASK,
28430 IX86_BUILTIN_VFNMADDPS512_MASK,
28431 IX86_BUILTIN_VFNMSUBPD512_MASK,
28432 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28433 IX86_BUILTIN_VFNMSUBPS512_MASK,
28434 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28435 IX86_BUILTIN_VPCLZCNTD512,
28436 IX86_BUILTIN_VPCLZCNTQ512,
28437 IX86_BUILTIN_VPCONFLICTD512,
28438 IX86_BUILTIN_VPCONFLICTQ512,
28439 IX86_BUILTIN_VPERMDF512,
28440 IX86_BUILTIN_VPERMDI512,
28441 IX86_BUILTIN_VPERMI2VARD512,
28442 IX86_BUILTIN_VPERMI2VARPD512,
28443 IX86_BUILTIN_VPERMI2VARPS512,
28444 IX86_BUILTIN_VPERMI2VARQ512,
28445 IX86_BUILTIN_VPERMILPD512,
28446 IX86_BUILTIN_VPERMILPS512,
28447 IX86_BUILTIN_VPERMILVARPD512,
28448 IX86_BUILTIN_VPERMILVARPS512,
28449 IX86_BUILTIN_VPERMT2VARD512,
28450 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28451 IX86_BUILTIN_VPERMT2VARPD512,
28452 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28453 IX86_BUILTIN_VPERMT2VARPS512,
28454 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28455 IX86_BUILTIN_VPERMT2VARQ512,
28456 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28457 IX86_BUILTIN_VPERMVARDF512,
28458 IX86_BUILTIN_VPERMVARDI512,
28459 IX86_BUILTIN_VPERMVARSF512,
28460 IX86_BUILTIN_VPERMVARSI512,
28461 IX86_BUILTIN_VTERNLOGD512_MASK,
28462 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28463 IX86_BUILTIN_VTERNLOGQ512_MASK,
28464 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28466 /* Mask arithmetic operations */
28467 IX86_BUILTIN_KAND16,
28468 IX86_BUILTIN_KANDN16,
28469 IX86_BUILTIN_KNOT16,
28470 IX86_BUILTIN_KOR16,
28471 IX86_BUILTIN_KORTESTC16,
28472 IX86_BUILTIN_KORTESTZ16,
28473 IX86_BUILTIN_KUNPCKBW,
28474 IX86_BUILTIN_KXNOR16,
28475 IX86_BUILTIN_KXOR16,
28476 IX86_BUILTIN_KMOV16,
28478 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28479 where all operands are 32-byte or 64-byte wide respectively. */
28480 IX86_BUILTIN_GATHERALTSIV4DF,
28481 IX86_BUILTIN_GATHERALTDIV8SF,
28482 IX86_BUILTIN_GATHERALTSIV4DI,
28483 IX86_BUILTIN_GATHERALTDIV8SI,
28484 IX86_BUILTIN_GATHER3ALTDIV16SF,
28485 IX86_BUILTIN_GATHER3ALTDIV16SI,
28486 IX86_BUILTIN_GATHER3ALTSIV8DF,
28487 IX86_BUILTIN_GATHER3ALTSIV8DI,
28488 IX86_BUILTIN_GATHER3DIV16SF,
28489 IX86_BUILTIN_GATHER3DIV16SI,
28490 IX86_BUILTIN_GATHER3DIV8DF,
28491 IX86_BUILTIN_GATHER3DIV8DI,
28492 IX86_BUILTIN_GATHER3SIV16SF,
28493 IX86_BUILTIN_GATHER3SIV16SI,
28494 IX86_BUILTIN_GATHER3SIV8DF,
28495 IX86_BUILTIN_GATHER3SIV8DI,
28496 IX86_BUILTIN_SCATTERDIV16SF,
28497 IX86_BUILTIN_SCATTERDIV16SI,
28498 IX86_BUILTIN_SCATTERDIV8DF,
28499 IX86_BUILTIN_SCATTERDIV8DI,
28500 IX86_BUILTIN_SCATTERSIV16SF,
28501 IX86_BUILTIN_SCATTERSIV16SI,
28502 IX86_BUILTIN_SCATTERSIV8DF,
28503 IX86_BUILTIN_SCATTERSIV8DI,
28505 /* AVX512PF */
28506 IX86_BUILTIN_GATHERPFQPD,
28507 IX86_BUILTIN_GATHERPFDPS,
28508 IX86_BUILTIN_GATHERPFDPD,
28509 IX86_BUILTIN_GATHERPFQPS,
28510 IX86_BUILTIN_SCATTERPFDPD,
28511 IX86_BUILTIN_SCATTERPFDPS,
28512 IX86_BUILTIN_SCATTERPFQPD,
28513 IX86_BUILTIN_SCATTERPFQPS,
28515 /* AVX-512ER */
28516 IX86_BUILTIN_EXP2PD_MASK,
28517 IX86_BUILTIN_EXP2PS_MASK,
28518 IX86_BUILTIN_EXP2PS,
28519 IX86_BUILTIN_RCP28PD,
28520 IX86_BUILTIN_RCP28PS,
28521 IX86_BUILTIN_RCP28SD,
28522 IX86_BUILTIN_RCP28SS,
28523 IX86_BUILTIN_RSQRT28PD,
28524 IX86_BUILTIN_RSQRT28PS,
28525 IX86_BUILTIN_RSQRT28SD,
28526 IX86_BUILTIN_RSQRT28SS,
28528 /* SHA builtins. */
28529 IX86_BUILTIN_SHA1MSG1,
28530 IX86_BUILTIN_SHA1MSG2,
28531 IX86_BUILTIN_SHA1NEXTE,
28532 IX86_BUILTIN_SHA1RNDS4,
28533 IX86_BUILTIN_SHA256MSG1,
28534 IX86_BUILTIN_SHA256MSG2,
28535 IX86_BUILTIN_SHA256RNDS2,
28537 /* CLFLUSHOPT instructions. */
28538 IX86_BUILTIN_CLFLUSHOPT,
28540 /* TFmode support builtins. */
28541 IX86_BUILTIN_INFQ,
28542 IX86_BUILTIN_HUGE_VALQ,
28543 IX86_BUILTIN_FABSQ,
28544 IX86_BUILTIN_COPYSIGNQ,
28546 /* Vectorizer support builtins. */
28547 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28548 IX86_BUILTIN_CPYSGNPS,
28549 IX86_BUILTIN_CPYSGNPD,
28550 IX86_BUILTIN_CPYSGNPS256,
28551 IX86_BUILTIN_CPYSGNPS512,
28552 IX86_BUILTIN_CPYSGNPD256,
28553 IX86_BUILTIN_CPYSGNPD512,
28554 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28555 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28558 /* FMA4 instructions. */
28559 IX86_BUILTIN_VFMADDSS,
28560 IX86_BUILTIN_VFMADDSD,
28561 IX86_BUILTIN_VFMADDPS,
28562 IX86_BUILTIN_VFMADDPD,
28563 IX86_BUILTIN_VFMADDPS256,
28564 IX86_BUILTIN_VFMADDPD256,
28565 IX86_BUILTIN_VFMADDSUBPS,
28566 IX86_BUILTIN_VFMADDSUBPD,
28567 IX86_BUILTIN_VFMADDSUBPS256,
28568 IX86_BUILTIN_VFMADDSUBPD256,
28570 /* FMA3 instructions. */
28571 IX86_BUILTIN_VFMADDSS3,
28572 IX86_BUILTIN_VFMADDSD3,
28574 /* XOP instructions. */
28575 IX86_BUILTIN_VPCMOV,
28576 IX86_BUILTIN_VPCMOV_V2DI,
28577 IX86_BUILTIN_VPCMOV_V4SI,
28578 IX86_BUILTIN_VPCMOV_V8HI,
28579 IX86_BUILTIN_VPCMOV_V16QI,
28580 IX86_BUILTIN_VPCMOV_V4SF,
28581 IX86_BUILTIN_VPCMOV_V2DF,
28582 IX86_BUILTIN_VPCMOV256,
28583 IX86_BUILTIN_VPCMOV_V4DI256,
28584 IX86_BUILTIN_VPCMOV_V8SI256,
28585 IX86_BUILTIN_VPCMOV_V16HI256,
28586 IX86_BUILTIN_VPCMOV_V32QI256,
28587 IX86_BUILTIN_VPCMOV_V8SF256,
28588 IX86_BUILTIN_VPCMOV_V4DF256,
28590 IX86_BUILTIN_VPPERM,
28592 IX86_BUILTIN_VPMACSSWW,
28593 IX86_BUILTIN_VPMACSWW,
28594 IX86_BUILTIN_VPMACSSWD,
28595 IX86_BUILTIN_VPMACSWD,
28596 IX86_BUILTIN_VPMACSSDD,
28597 IX86_BUILTIN_VPMACSDD,
28598 IX86_BUILTIN_VPMACSSDQL,
28599 IX86_BUILTIN_VPMACSSDQH,
28600 IX86_BUILTIN_VPMACSDQL,
28601 IX86_BUILTIN_VPMACSDQH,
28602 IX86_BUILTIN_VPMADCSSWD,
28603 IX86_BUILTIN_VPMADCSWD,
28605 IX86_BUILTIN_VPHADDBW,
28606 IX86_BUILTIN_VPHADDBD,
28607 IX86_BUILTIN_VPHADDBQ,
28608 IX86_BUILTIN_VPHADDWD,
28609 IX86_BUILTIN_VPHADDWQ,
28610 IX86_BUILTIN_VPHADDDQ,
28611 IX86_BUILTIN_VPHADDUBW,
28612 IX86_BUILTIN_VPHADDUBD,
28613 IX86_BUILTIN_VPHADDUBQ,
28614 IX86_BUILTIN_VPHADDUWD,
28615 IX86_BUILTIN_VPHADDUWQ,
28616 IX86_BUILTIN_VPHADDUDQ,
28617 IX86_BUILTIN_VPHSUBBW,
28618 IX86_BUILTIN_VPHSUBWD,
28619 IX86_BUILTIN_VPHSUBDQ,
28621 IX86_BUILTIN_VPROTB,
28622 IX86_BUILTIN_VPROTW,
28623 IX86_BUILTIN_VPROTD,
28624 IX86_BUILTIN_VPROTQ,
28625 IX86_BUILTIN_VPROTB_IMM,
28626 IX86_BUILTIN_VPROTW_IMM,
28627 IX86_BUILTIN_VPROTD_IMM,
28628 IX86_BUILTIN_VPROTQ_IMM,
28630 IX86_BUILTIN_VPSHLB,
28631 IX86_BUILTIN_VPSHLW,
28632 IX86_BUILTIN_VPSHLD,
28633 IX86_BUILTIN_VPSHLQ,
28634 IX86_BUILTIN_VPSHAB,
28635 IX86_BUILTIN_VPSHAW,
28636 IX86_BUILTIN_VPSHAD,
28637 IX86_BUILTIN_VPSHAQ,
28639 IX86_BUILTIN_VFRCZSS,
28640 IX86_BUILTIN_VFRCZSD,
28641 IX86_BUILTIN_VFRCZPS,
28642 IX86_BUILTIN_VFRCZPD,
28643 IX86_BUILTIN_VFRCZPS256,
28644 IX86_BUILTIN_VFRCZPD256,
28646 IX86_BUILTIN_VPCOMEQUB,
28647 IX86_BUILTIN_VPCOMNEUB,
28648 IX86_BUILTIN_VPCOMLTUB,
28649 IX86_BUILTIN_VPCOMLEUB,
28650 IX86_BUILTIN_VPCOMGTUB,
28651 IX86_BUILTIN_VPCOMGEUB,
28652 IX86_BUILTIN_VPCOMFALSEUB,
28653 IX86_BUILTIN_VPCOMTRUEUB,
28655 IX86_BUILTIN_VPCOMEQUW,
28656 IX86_BUILTIN_VPCOMNEUW,
28657 IX86_BUILTIN_VPCOMLTUW,
28658 IX86_BUILTIN_VPCOMLEUW,
28659 IX86_BUILTIN_VPCOMGTUW,
28660 IX86_BUILTIN_VPCOMGEUW,
28661 IX86_BUILTIN_VPCOMFALSEUW,
28662 IX86_BUILTIN_VPCOMTRUEUW,
28664 IX86_BUILTIN_VPCOMEQUD,
28665 IX86_BUILTIN_VPCOMNEUD,
28666 IX86_BUILTIN_VPCOMLTUD,
28667 IX86_BUILTIN_VPCOMLEUD,
28668 IX86_BUILTIN_VPCOMGTUD,
28669 IX86_BUILTIN_VPCOMGEUD,
28670 IX86_BUILTIN_VPCOMFALSEUD,
28671 IX86_BUILTIN_VPCOMTRUEUD,
28673 IX86_BUILTIN_VPCOMEQUQ,
28674 IX86_BUILTIN_VPCOMNEUQ,
28675 IX86_BUILTIN_VPCOMLTUQ,
28676 IX86_BUILTIN_VPCOMLEUQ,
28677 IX86_BUILTIN_VPCOMGTUQ,
28678 IX86_BUILTIN_VPCOMGEUQ,
28679 IX86_BUILTIN_VPCOMFALSEUQ,
28680 IX86_BUILTIN_VPCOMTRUEUQ,
28682 IX86_BUILTIN_VPCOMEQB,
28683 IX86_BUILTIN_VPCOMNEB,
28684 IX86_BUILTIN_VPCOMLTB,
28685 IX86_BUILTIN_VPCOMLEB,
28686 IX86_BUILTIN_VPCOMGTB,
28687 IX86_BUILTIN_VPCOMGEB,
28688 IX86_BUILTIN_VPCOMFALSEB,
28689 IX86_BUILTIN_VPCOMTRUEB,
28691 IX86_BUILTIN_VPCOMEQW,
28692 IX86_BUILTIN_VPCOMNEW,
28693 IX86_BUILTIN_VPCOMLTW,
28694 IX86_BUILTIN_VPCOMLEW,
28695 IX86_BUILTIN_VPCOMGTW,
28696 IX86_BUILTIN_VPCOMGEW,
28697 IX86_BUILTIN_VPCOMFALSEW,
28698 IX86_BUILTIN_VPCOMTRUEW,
28700 IX86_BUILTIN_VPCOMEQD,
28701 IX86_BUILTIN_VPCOMNED,
28702 IX86_BUILTIN_VPCOMLTD,
28703 IX86_BUILTIN_VPCOMLED,
28704 IX86_BUILTIN_VPCOMGTD,
28705 IX86_BUILTIN_VPCOMGED,
28706 IX86_BUILTIN_VPCOMFALSED,
28707 IX86_BUILTIN_VPCOMTRUED,
28709 IX86_BUILTIN_VPCOMEQQ,
28710 IX86_BUILTIN_VPCOMNEQ,
28711 IX86_BUILTIN_VPCOMLTQ,
28712 IX86_BUILTIN_VPCOMLEQ,
28713 IX86_BUILTIN_VPCOMGTQ,
28714 IX86_BUILTIN_VPCOMGEQ,
28715 IX86_BUILTIN_VPCOMFALSEQ,
28716 IX86_BUILTIN_VPCOMTRUEQ,
28718 /* LWP instructions. */
28719 IX86_BUILTIN_LLWPCB,
28720 IX86_BUILTIN_SLWPCB,
28721 IX86_BUILTIN_LWPVAL32,
28722 IX86_BUILTIN_LWPVAL64,
28723 IX86_BUILTIN_LWPINS32,
28724 IX86_BUILTIN_LWPINS64,
28726 IX86_BUILTIN_CLZS,
28728 /* RTM */
28729 IX86_BUILTIN_XBEGIN,
28730 IX86_BUILTIN_XEND,
28731 IX86_BUILTIN_XABORT,
28732 IX86_BUILTIN_XTEST,
28734 /* BMI instructions. */
28735 IX86_BUILTIN_BEXTR32,
28736 IX86_BUILTIN_BEXTR64,
28737 IX86_BUILTIN_CTZS,
28739 /* TBM instructions. */
28740 IX86_BUILTIN_BEXTRI32,
28741 IX86_BUILTIN_BEXTRI64,
28743 /* BMI2 instructions. */
28744 IX86_BUILTIN_BZHI32,
28745 IX86_BUILTIN_BZHI64,
28746 IX86_BUILTIN_PDEP32,
28747 IX86_BUILTIN_PDEP64,
28748 IX86_BUILTIN_PEXT32,
28749 IX86_BUILTIN_PEXT64,
28751 /* ADX instructions. */
28752 IX86_BUILTIN_ADDCARRYX32,
28753 IX86_BUILTIN_ADDCARRYX64,
28755 /* FSGSBASE instructions. */
28756 IX86_BUILTIN_RDFSBASE32,
28757 IX86_BUILTIN_RDFSBASE64,
28758 IX86_BUILTIN_RDGSBASE32,
28759 IX86_BUILTIN_RDGSBASE64,
28760 IX86_BUILTIN_WRFSBASE32,
28761 IX86_BUILTIN_WRFSBASE64,
28762 IX86_BUILTIN_WRGSBASE32,
28763 IX86_BUILTIN_WRGSBASE64,
28765 /* RDRND instructions. */
28766 IX86_BUILTIN_RDRAND16_STEP,
28767 IX86_BUILTIN_RDRAND32_STEP,
28768 IX86_BUILTIN_RDRAND64_STEP,
28770 /* RDSEED instructions. */
28771 IX86_BUILTIN_RDSEED16_STEP,
28772 IX86_BUILTIN_RDSEED32_STEP,
28773 IX86_BUILTIN_RDSEED64_STEP,
28775 /* F16C instructions. */
28776 IX86_BUILTIN_CVTPH2PS,
28777 IX86_BUILTIN_CVTPH2PS256,
28778 IX86_BUILTIN_CVTPS2PH,
28779 IX86_BUILTIN_CVTPS2PH256,
28781 /* CFString built-in for darwin */
28782 IX86_BUILTIN_CFSTRING,
28784 /* Builtins to get CPU type and supported features. */
28785 IX86_BUILTIN_CPU_INIT,
28786 IX86_BUILTIN_CPU_IS,
28787 IX86_BUILTIN_CPU_SUPPORTS,
28789 /* Read/write FLAGS register built-ins. */
28790 IX86_BUILTIN_READ_FLAGS,
28791 IX86_BUILTIN_WRITE_FLAGS,
28793 IX86_BUILTIN_MAX
28794 };
28796 /* Table for the ix86 builtin decls. */
28799 /* Table of all of the builtin functions that are possible with different ISA's
28800 but are waiting to be built until a function is declared to use that
28801 ISA. */
28808 };
28813 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
28814 of which isa_flags to use in the ix86_builtins_isa array. Stores the
28815 function decl in the ix86_builtins array. Returns the function decl or
28816 NULL_TREE, if the builtin was not added.
28818 If the front end has a special hook for builtin functions, delay adding
28819 builtin functions that aren't in the current ISA until the ISA is changed
28820 with function specific optimization. Doing so, can save about 300K for the
28821 default compiler. When the builtin is expanded, check at that time whether
28822 it is valid.
28824 If the front end doesn't have a special hook, record all builtins, even if
28825 it isn't an instruction set in the current ISA in case the user uses
28826 function specific options for a different ISA, so that we don't get scope
28827 errors if a builtin is added in the middle of a function scope. */
28833 {
28837 {
28846 {
28852 }
28853 else
28854 {
28860 }
28861 }
28864 }
28866 /* Like def_builtin, but also marks the function decl "const". */
28871 {
28875 else
28879 }
28881 /* Add any new builtin functions for a given ISA that may not have been
28882 declared. This saves a bit of space compared to adding all of the
28883 declarations to the tree, even if we didn't use them. */
28885 static void
28887 {
28891 {
28894 {
28897 /* Don't define the builtin again. */
28903 NULL_TREE);
28908 }
28909 }
28910 }
28912 /* Bits for builtin_description.flag. */
28914 /* Set when we don't support the comparison natively, and should
28915 swap_comparison in order to support it. */
28916 #define BUILTIN_DESC_SWAP_OPERANDS 1
28918 struct builtin_description
28919 {
28926 };
28929 {
28930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
28931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
28932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
28933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
28934 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
28935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
28936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
28937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
28938 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
28939 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
28940 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
28941 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
28942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
28943 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
28944 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
28945 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
28946 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
28947 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
28948 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
28949 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
28950 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
28951 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
28952 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
28953 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
28954 };
28957 {
28958 /* SSE4.2 */
28959 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
28960 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
28961 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
28962 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
28963 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
28964 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
28965 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
28966 };
28969 {
28970 /* SSE4.2 */
28971 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
28972 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
28973 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
28974 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
28975 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
28976 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
28977 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
28978 };
28980 /* Special builtins with variable number of arguments. */
28982 {
28983 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
28984 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
28985 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
28987 /* 80387 (for use internally for atomic compound assignment). */
28988 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
28989 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
28990 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
28991 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
28993 /* MMX */
28994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28996 /* 3DNow! */
28997 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28999 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
29000 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
29001 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
29002 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29003 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29004 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29005 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29006 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29007 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29009 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29010 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29011 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29012 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29013 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29014 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29015 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29016 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29018 /* SSE */
29019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29023 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29024 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29025 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29026 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29028 /* SSE or 3DNow!A */
29029 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29030 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
29032 /* SSE2 */
29033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
29037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
29039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
29040 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
29041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
29042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29047 /* SSE3 */
29048 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29050 /* SSE4.1 */
29051 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
29053 /* SSE4A */
29054 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29055 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29057 /* AVX */
29058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
29059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
29061 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29062 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29063 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
29065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29070 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29072 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29073 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29076 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29079 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29080 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29081 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29082 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29083 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29084 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29085 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29086 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29088 /* AVX2 */
29089 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29090 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29091 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29092 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29093 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29094 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29095 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29096 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29097 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29099 /* AVX512F */
29100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29148 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29149 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29150 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29151 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29152 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29153 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29155 /* FSGSBASE */
29156 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29157 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29158 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29159 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29160 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29161 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29162 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29163 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29165 /* RTM */
29166 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29167 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29168 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29169 };
29171 /* Builtins with variable number of arguments. */
29173 {
29174 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29175 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29176 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29177 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29178 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29179 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29180 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29182 /* MMX */
29183 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29184 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29185 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29186 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29187 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29188 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29190 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29191 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29192 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29193 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29194 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29195 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29196 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29197 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29199 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29200 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29202 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29203 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29204 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29205 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29207 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29208 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29209 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29210 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29211 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29212 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29214 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29215 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29216 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29217 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29218 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29219 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29221 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29222 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29223 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29225 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29227 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29228 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29230 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29231 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29232 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29234 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29235 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29236 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29237 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29241 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29242 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29243 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29244 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29246 /* 3DNow! */
29247 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29248 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29249 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29250 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29252 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29253 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29254 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29255 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29256 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29257 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29258 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29259 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29260 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29261 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29262 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29263 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29264 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29265 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29266 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29268 /* 3DNow!A */
29269 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29270 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29271 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29272 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29273 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29274 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29276 /* SSE */
29277 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29278 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29279 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29280 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29281 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29282 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29283 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29284 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29285 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29286 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29287 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29288 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29290 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29292 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29293 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29294 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29295 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29296 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29297 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29298 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29299 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29301 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29302 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29303 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29304 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29306 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29308 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29309 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29310 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29312 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29313 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29314 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29315 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29316 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29317 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29318 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29319 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29320 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29322 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29323 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29325 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29327 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29328 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29329 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29330 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29332 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29334 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29335 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29336 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29337 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29338 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29340 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29341 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29342 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29344 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29346 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29347 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29348 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29350 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29351 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29353 /* SSE MMX or 3Dnow!A */
29354 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29355 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29356 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29358 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29359 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29360 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29361 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29363 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29364 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29366 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29368 /* SSE2 */
29369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29371 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29372 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29373 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29374 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29375 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29377 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29378 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29379 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29380 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29383 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29387 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29388 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29392 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29394 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29395 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29396 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29397 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29398 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29415 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29420 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29424 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29425 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29429 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29431 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29432 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29434 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29436 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29437 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29438 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29440 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29442 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29443 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29444 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29445 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29446 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29447 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29448 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29449 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29460 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29461 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29463 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29465 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29466 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29473 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29478 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29479 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29480 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29481 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29483 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29484 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29485 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29486 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29487 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29488 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29489 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29490 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29494 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29496 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29500 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29505 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29510 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29511 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29512 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29513 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29514 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29515 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29518 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29519 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29520 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29521 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29522 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29523 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29525 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29526 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29527 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29528 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29532 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29536 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29538 /* SSE2 MMX */
29539 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29540 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29542 /* SSE3 */
29543 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29544 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29546 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29547 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29548 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29549 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29550 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29551 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29553 /* SSSE3 */
29554 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29555 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29556 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29557 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29558 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29559 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29561 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29562 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29563 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29564 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29565 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29566 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29567 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29568 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29569 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29570 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29571 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29572 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29573 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29574 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29575 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29576 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29577 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29578 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29579 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29580 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29581 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29582 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29583 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29584 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29586 /* SSSE3. */
29587 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29588 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29590 /* SSE4.1 */
29591 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29592 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29593 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29594 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29595 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29596 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29597 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29598 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29599 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29600 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29602 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29603 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29604 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29605 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29606 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29607 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29608 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29609 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29610 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29611 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29612 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29613 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29614 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29616 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29617 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29618 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29619 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29620 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29621 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29622 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29623 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29624 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29625 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29626 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29627 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29629 /* SSE4.1 */
29630 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29631 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29632 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29633 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29635 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29636 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29637 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29638 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29640 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29641 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29643 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29644 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29646 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29647 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29648 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29649 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29651 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29652 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29654 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29655 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29657 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29658 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29659 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29661 /* SSE4.2 */
29662 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29663 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29664 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29665 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29666 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29668 /* SSE4A */
29669 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29670 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29671 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29672 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29674 /* AES */
29675 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29676 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29678 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29679 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29680 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29681 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29683 /* PCLMUL */
29684 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29686 /* AVX */
29687 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29688 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29690 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29691 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29692 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29693 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29695 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29696 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29698 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29699 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29701 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29702 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29703 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29704 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29705 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29706 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29707 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29708 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29709 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29710 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29711 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29712 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29735 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29736 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29740 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29742 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29758 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29759 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29760 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29762 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29764 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29767 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29769 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
29770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
29771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
29772 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
29774 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29775 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
29781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
29782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
29783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
29785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
29786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
29788 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29789 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29799 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
29800 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
29801 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
29803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
29820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
29822 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29823 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29825 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29827 /* AVX2 */
29828 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
29829 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
29830 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
29831 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
29832 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29833 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29834 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29835 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29836 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29837 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29838 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29839 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29840 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29841 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29842 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29843 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29844 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
29845 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29846 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29847 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29848 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29849 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
29850 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
29851 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29852 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29853 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29854 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29855 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29856 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29857 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29858 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29859 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29860 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29861 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29862 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29863 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29864 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29866 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
29867 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29868 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29869 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29870 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29871 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29872 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29873 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29874 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29875 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29876 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29877 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29878 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
29880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29892 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29894 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29895 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29896 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29897 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29898 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29899 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
29903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29909 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29910 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29911 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29912 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29913 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29914 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29915 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29916 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29917 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29918 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29919 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29920 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29921 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29922 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29923 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29924 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29925 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29926 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29927 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29928 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29929 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29931 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29932 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29933 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29934 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29935 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29936 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29937 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29938 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29939 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29940 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29941 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29942 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
29948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
29950 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
29951 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29952 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29953 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29954 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29955 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29956 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29957 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29958 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29959 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
29961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
29962 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
29963 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
29964 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29965 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29966 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29967 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29968 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29969 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29970 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29971 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29972 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29973 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29975 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29977 /* BMI */
29978 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29979 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29980 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29982 /* TBM */
29983 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29984 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29986 /* F16C */
29987 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
29988 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
29989 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
29990 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
29992 /* BMI2 */
29993 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29994 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29995 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29996 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29997 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29998 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30000 /* AVX512F */
30001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
30009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
30011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
30012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
30019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
30021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
30026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
30027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
30028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
30029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
30030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
30031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
30032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
30033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
30050 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
30051 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
30052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
30053 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30054 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30162 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30163 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30164 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30165 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30197 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30202 /* Mask arithmetic operations */
30203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30214 /* SHA */
30215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30222 };
30224 /* Builtins with rounding support. */
30226 {
30227 /* AVX512F */
30228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30247 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30249 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30256 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30258 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30308 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30309 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30310 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30312 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30314 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30316 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30318 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30320 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30321 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30322 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30323 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30324 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30325 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30326 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30327 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30328 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30329 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30330 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30331 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30332 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30333 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30334 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30335 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30336 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30337 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30338 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30339 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30340 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30341 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30342 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30343 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30344 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30345 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30346 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30348 /* AVX512ER */
30349 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30350 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30351 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30352 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30353 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30354 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30355 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30356 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30357 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30358 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30359 };
30361 /* FMA4 and XOP. */
30362 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30363 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30364 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30365 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30366 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30367 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30368 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30369 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30370 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30371 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30372 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30373 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30374 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30375 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30376 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30377 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30378 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30379 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30380 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30381 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30382 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30383 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30384 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30385 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30386 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30387 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30388 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30389 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30390 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30391 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30392 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30393 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30394 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30395 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30396 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30397 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30398 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30399 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30400 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30401 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30402 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30403 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30404 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30405 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30406 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30407 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30408 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30409 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30410 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30411 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30412 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30413 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30416 {
30457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30468 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30615 };
30616 \f
30617 /* TM vector builtins. */
30619 /* Reuse the existing x86-specific `struct builtin_description' cause
30620 we're lazy. Add casts to make them fit. */
30622 {
30623 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30624 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30625 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30626 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30627 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30628 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30629 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30631 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30632 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30633 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30634 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30635 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30636 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30637 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30639 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30640 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30641 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30642 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30643 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30644 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30645 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30647 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30648 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30649 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30650 };
30652 /* TM callbacks. */
30654 /* Return the builtin decl needed to load a vector of TYPE. */
30656 static tree
30658 {
30660 {
30662 {
30669 }
30670 }
30672 }
30674 /* Return the builtin decl needed to store a vector of TYPE. */
30676 static tree
30678 {
30680 {
30682 {
30689 }
30690 }
30692 }
30693 \f
30694 /* Initialize the transactional memory vector load/store builtins. */
30696 static void
30698 {
30702 tree decl;
30709 /* If there are no builtins defined, we must be compiling in a
30710 language without trans-mem support. */
30714 /* Use whatever attributes a normal TM load has. */
30718 /* Use whatever attributes a normal TM store has. */
30722 /* Use whatever attributes a normal TM log has. */
30730 {
30734 {
30742 {
30745 }
30747 {
30750 }
30751 else
30752 {
30755 }
30757 /* The builtin without the prefix for
30758 calling it directly. */
30760 attrs);
30761 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
30762 set the TYPE_ATTRIBUTES. */
30766 }
30767 }
30768 }
30770 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
30771 in the current target ISA to allow the user to compile particular modules
30772 with different target specific options that differ from the command line
30773 options. */
30774 static void
30776 {
30781 /* Add all special builtins with variable number of operands. */
30785 {
30791 }
30793 /* Add all builtins with variable number of operands. */
30797 {
30803 }
30805 /* Add all builtins with rounding. */
30809 {
30815 }
30817 /* pcmpestr[im] insns. */
30821 {
30824 else
30827 }
30829 /* pcmpistr[im] insns. */
30833 {
30836 else
30839 }
30841 /* comi/ucomi insns. */
30843 {
30846 else
30849 }
30851 /* SSE */
30857 /* SSE or 3DNow!A */
30860 IX86_BUILTIN_MASKMOVQ);
30862 /* SSE2 */
30871 /* SSE3. */
30877 /* AES */
30891 /* PCLMUL */
30895 /* RDRND */
30902 IX86_BUILTIN_RDRAND64_STEP);
30904 /* AVX2 */
30906 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
30907 IX86_BUILTIN_GATHERSIV2DF);
30910 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
30911 IX86_BUILTIN_GATHERSIV4DF);
30914 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
30915 IX86_BUILTIN_GATHERDIV2DF);
30918 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
30919 IX86_BUILTIN_GATHERDIV4DF);
30922 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
30923 IX86_BUILTIN_GATHERSIV4SF);
30926 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
30927 IX86_BUILTIN_GATHERSIV8SF);
30930 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
30931 IX86_BUILTIN_GATHERDIV4SF);
30934 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
30935 IX86_BUILTIN_GATHERDIV8SF);
30938 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
30939 IX86_BUILTIN_GATHERSIV2DI);
30942 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
30943 IX86_BUILTIN_GATHERSIV4DI);
30946 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
30947 IX86_BUILTIN_GATHERDIV2DI);
30950 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
30951 IX86_BUILTIN_GATHERDIV4DI);
30954 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
30955 IX86_BUILTIN_GATHERSIV4SI);
30958 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
30959 IX86_BUILTIN_GATHERSIV8SI);
30962 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
30963 IX86_BUILTIN_GATHERDIV4SI);
30966 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
30967 IX86_BUILTIN_GATHERDIV8SI);
30970 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
30971 IX86_BUILTIN_GATHERALTSIV4DF);
30974 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
30975 IX86_BUILTIN_GATHERALTDIV8SF);
30978 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
30979 IX86_BUILTIN_GATHERALTSIV4DI);
30982 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
30983 IX86_BUILTIN_GATHERALTDIV8SI);
30985 /* AVX512F */
30987 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
30988 IX86_BUILTIN_GATHER3SIV16SF);
30991 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
30992 IX86_BUILTIN_GATHER3SIV8DF);
30995 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
30996 IX86_BUILTIN_GATHER3DIV16SF);
30999 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
31000 IX86_BUILTIN_GATHER3DIV8DF);
31003 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
31004 IX86_BUILTIN_GATHER3SIV16SI);
31007 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
31008 IX86_BUILTIN_GATHER3SIV8DI);
31011 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
31012 IX86_BUILTIN_GATHER3DIV16SI);
31015 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
31016 IX86_BUILTIN_GATHER3DIV8DI);
31019 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
31020 IX86_BUILTIN_GATHER3ALTSIV8DF);
31023 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
31024 IX86_BUILTIN_GATHER3ALTDIV16SF);
31027 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
31028 IX86_BUILTIN_GATHER3ALTSIV8DI);
31031 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
31032 IX86_BUILTIN_GATHER3ALTDIV16SI);
31035 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
31036 IX86_BUILTIN_SCATTERSIV16SF);
31039 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
31040 IX86_BUILTIN_SCATTERSIV8DF);
31043 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
31044 IX86_BUILTIN_SCATTERDIV16SF);
31047 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
31048 IX86_BUILTIN_SCATTERDIV8DF);
31051 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
31052 IX86_BUILTIN_SCATTERSIV16SI);
31055 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
31056 IX86_BUILTIN_SCATTERSIV8DI);
31059 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
31060 IX86_BUILTIN_SCATTERDIV16SI);
31063 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
31064 IX86_BUILTIN_SCATTERDIV8DI);
31066 /* AVX512PF */
31068 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31069 IX86_BUILTIN_GATHERPFDPD);
31071 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31072 IX86_BUILTIN_GATHERPFDPS);
31074 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31075 IX86_BUILTIN_GATHERPFQPD);
31077 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31078 IX86_BUILTIN_GATHERPFQPS);
31080 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31081 IX86_BUILTIN_SCATTERPFDPD);
31083 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31084 IX86_BUILTIN_SCATTERPFDPS);
31086 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31087 IX86_BUILTIN_SCATTERPFQPD);
31089 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31090 IX86_BUILTIN_SCATTERPFQPS);
31092 /* SHA */
31108 /* RTM. */
31112 /* MMX access to the vec_init patterns. */
31117 V4HI_FTYPE_HI_HI_HI_HI,
31118 IX86_BUILTIN_VEC_INIT_V4HI);
31121 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31122 IX86_BUILTIN_VEC_INIT_V8QI);
31124 /* Access to the vec_extract patterns. */
31146 /* Access to the vec_set patterns. */
31167 /* RDSEED */
31176 /* ADCX */
31181 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31182 IX86_BUILTIN_ADDCARRYX64);
31184 /* Read/write FLAGS. */
31194 /* CLFLUSHOPT. */
31198 /* Add FMA4 multi-arg argument instructions */
31200 {
31206 }
31207 }
31209 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31210 to return a pointer to VERSION_DECL if the outcome of the expression
31211 formed by PREDICATE_CHAIN is true. This function will be called during
31212 version dispatch to decide which function version to execute. It returns
31213 the basic block at the end, to which more conditions can be added. */
31215 static basic_block
31218 {
31219 gimple return_stmt;
31221 gimple convert_stmt;
31222 gimple call_cond_stmt;
31223 gimple if_else_stmt;
31229 gimple_seq gseq;
31246 {
31254 }
31257 {
31272 else
31273 {
31274 gimple assign_stmt;
31275 /* Use MIN_EXPR to check if any integer is zero?.
31276 and_expr_var = min_expr <cond_var, and_expr_var> */
31284 }
31285 }
31288 integer_zero_node,
31318 }
31320 /* This parses the attribute arguments to target in DECL and determines
31321 the right builtin to use to match the platform specification.
31322 It returns the priority value for this version decl. If PREDICATE_LIST
31323 is not NULL, it stores the list of cpu features that need to be checked
31324 before dispatching this function. */
31326 static unsigned int
31328 {
31329 tree attrs;
31331 tree target_node;
31338 /* Priority of i386 features, greater value is higher priority. This is
31339 used to decide the order in which function dispatch must happen. For
31340 instance, a version specialized for SSE4.2 should be checked for dispatch
31341 before a version for SSE3, as SSE4.2 implies SSE3. */
31342 enum feature_priority
31343 {
31345 P_MMX,
31346 P_SSE,
31347 P_SSE2,
31348 P_SSE3,
31349 P_SSSE3,
31350 P_PROC_SSSE3,
31351 P_SSE4_A,
31352 P_PROC_SSE4_A,
31353 P_SSE4_1,
31354 P_SSE4_2,
31355 P_PROC_SSE4_2,
31356 P_POPCNT,
31357 P_AVX,
31358 P_PROC_AVX,
31359 P_FMA4,
31360 P_XOP,
31361 P_PROC_XOP,
31362 P_FMA,
31363 P_PROC_FMA,
31364 P_AVX2,
31365 P_PROC_AVX2
31366 };
31370 /* These are the target attribute strings for which a dispatcher is
31371 available, from fold_builtin_cpu. */
31373 static struct _feature_list
31374 {
31377 }
31379 {
31394 };
31397 static unsigned int NUM_FEATURES
31413 /* Return priority zero for default function. */
31417 /* Handle arch= if specified. For priority, set it to be 1 more than
31418 the best instruction set the processor can handle. For instance, if
31419 there is a version for atom and a version for ssse3 (the highest ISA
31420 priority for atom), the atom version must be checked for dispatch
31421 before the ssse3 version. */
31423 {
31433 {
31435 {
31443 else
31444 /* We translate "arch=corei7" and "arch=nehalem" to
31445 "corei7" so that it will be mapped to M_INTEL_COREI7
31446 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31453 else
31460 else
31500 }
31501 }
31506 {
31510 }
31513 {
31515 /* For a C string literal the length includes the trailing NULL. */
31518 predicate_chain);
31519 }
31520 }
31522 /* Process feature name. */
31529 {
31530 /* Do not process "arch=" */
31532 {
31535 }
31537 {
31539 {
31541 {
31546 predicate_chain);
31547 }
31548 /* Find the maximum priority feature. */
31553 }
31554 }
31556 {
31560 }
31562 }
31566 {
31569 attrs_str);
31571 }
31573 {
31576 }
31579 }
31581 /* This compares the priority of target features in function DECL1
31582 and DECL2. It returns positive value if DECL1 is higher priority,
31583 negative value if DECL2 is higher priority and 0 if they are the
31584 same. */
31586 static int
31588 {
31593 }
31595 /* V1 and V2 point to function versions with different priorities
31596 based on the target ISA. This function compares their priorities. */
31598 static int
31600 {
31602 {
31603 tree version_decl;
31604 tree predicate_chain;
31611 }
31613 /* This function generates the dispatch function for
31614 multi-versioned functions. DISPATCH_DECL is the function which will
31615 contain the dispatch logic. FNDECLS are the function choices for
31616 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31617 in DISPATCH_DECL in which the dispatch code is generated. */
31619 static int
31623 {
31624 tree default_decl;
31625 gimple ifunc_cpu_init_stmt;
31626 gimple_seq gseq;
31628 tree ele;
31634 struct _function_version_info
31635 {
31636 tree version_decl;
31637 tree predicate_chain;
31645 /*fndecls_p is actually a vector. */
31648 /* At least one more version other than the default. */
31655 /* The first version in the vector is the default decl. */
31661 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31662 constructors, so explicity call __builtin_cpu_init here. */
31673 {
31677 /* Get attribute string, parse it and find the right predicate decl.
31678 The predicate function could be a lengthy combination of many
31679 features, like arch-type and various isa-variants. */
31690 actual_versions++;
31691 }
31693 /* Sort the versions according to descending order of dispatch priority. The
31694 priority is based on the ISA. This is not a perfect solution. There
31695 could still be ambiguity. If more than one function version is suitable
31696 to execute, which one should be dispatched? In future, allow the user
31697 to specify a dispatch priority next to the version. */
31707 /* dispatch default version at the end. */
31713 }
31715 /* Comparator function to be used in qsort routine to sort attribute
31716 specification strings to "target". */
31718 static int
31720 {
31724 }
31726 /* ARGLIST is the argument to target attribute. This function tokenizes
31727 the comma separated arguments, sorts them and returns a string which
31728 is a unique identifier for the comma separated arguments. It also
31729 replaces non-identifier characters "=,-" with "_". */
31733 {
31734 tree arg;
31743 {
31748 argnum++;
31751 argnum++;
31752 }
31757 {
31763 }
31765 /* Replace "=,-" with "_". */
31778 {
31780 i++;
31782 }
31789 {
31794 }
31799 }
31801 /* This function changes the assembler name for functions that are
31802 versions. If DECL is a function version and has a "target"
31803 attribute, it appends the attribute string to its assembler name. */
31805 static tree
31807 {
31808 tree version_attr;
31816 "Function versions cannot be marked as gnu_inline,"
31825 /* target attribute string cannot be NULL. */
31829 version_string
31840 /* Allow assembler name to be modified if already set. */
31848 }
31850 /* This function returns true if FN1 and FN2 are versions of the same function,
31851 that is, the target strings of the function decls are different. This assumes
31852 that FN1 and FN2 have the same signature. */
31854 static bool
31856 {
31868 /* At least one function decl should have the target attribute specified. */
31872 /* Diagnose missing target attribute if one of the decls is already
31873 multi-versioned. */
31875 {
31877 {
31879 {
31884 }
31887 fn2);
31890 /* Prevent diagnosing of the same error multiple times. */
31895 }
31897 }
31902 /* The sorted target strings must be different for fn1 and fn2
31903 to be versions. */
31906 else
31913 }
31915 static tree
31917 {
31918 /* For function version, add the target suffix to the assembler name. */
31922 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
31924 #endif
31927 }
31929 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
31930 is true, append the full path name of the source file. */
31934 {
31942 /* Get a unique name that can be used globally without any chances
31943 of collision at link time. */
31953 /* Use '.' to concatenate names as it is demangler friendly. */
31956 suffix);
31957 else
31961 }
31963 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
31965 /* Make a dispatcher declaration for the multi-versioned function DECL.
31966 Calls to DECL function will be replaced with calls to the dispatcher
31967 by the front-end. Return the decl created. */
31969 static tree
31971 {
31972 tree func_decl;
31992 /* Mark this func as external, the resolver will flip it again if
31993 it gets generated. */
31995 /* This will be of type IFUNCs have to be externally visible. */
31999 }
32001 #endif
32003 /* Returns true if decl is multi-versioned and DECL is the default function,
32004 that is it is not tagged with target specific optimization. */
32006 static bool
32008 {
32017 }
32019 /* Make a dispatcher declaration for the multi-versioned function DECL.
32020 Calls to DECL function will be replaced with calls to the dispatcher
32021 by the front-end. Returns the decl of the dispatcher function. */
32023 static tree
32025 {
32047 /* Find the default version and make it the first node. */
32049 /* Go to the beginning of the chain. */
32054 {
32059 }
32061 /* If there is no default node, just return NULL. */
32065 /* Make default info the first node. */
32067 {
32074 }
32078 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32080 {
32085 /* Right now, the dispatching is done via ifunc. */
32091 dispatcher_version_info
32096 /* Set the dispatcher for all the versions. */
32099 {
32102 }
32103 }
32104 else
32105 #endif
32106 {
32108 "multiversioning needs ifunc which is not supported "
32110 }
32113 }
32115 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32116 it to CHAIN. */
32118 static tree
32120 {
32121 tree attr_name;
32122 tree attr_arg_name;
32123 tree attr_args;
32124 tree attr;
32131 }
32133 /* Make the resolver function decl to dispatch the versions of
32134 a multi-versioned function, DEFAULT_DECL. Create an
32135 empty basic block in the resolver and store the pointer in
32136 EMPTY_BB. Return the decl of the resolver function. */
32138 static tree
32142 {
32147 /* IFUNC's have to be globally visible. So, if the default_decl is
32148 not, then the name of the IFUNC should be made unique. */
32152 /* Append the filename to the resolver function if the versions are
32153 not externally visible. This is because the resolver function has
32154 to be externally visible for the loader to find it. So, appending
32155 the filename will prevent conflicts with a resolver function from
32156 another module which is based on the same version name. */
32159 /* The resolver function should return a (void *). */
32170 /* IFUNC resolvers have to be externally visible. */
32174 /* Resolver is not external, body is generated. */
32184 {
32185 /* In this case, each translation unit with a call to this
32186 versioned function will put out a resolver. Ensure it
32187 is comdat to keep just one copy. */
32190 }
32191 /* Build result decl and add to function_decl. */
32207 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32211 /* Create the alias for dispatch to resolver here. */
32212 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32216 }
32218 /* Generate the dispatching code body to dispatch multi-versioned function
32219 DECL. The target hook is called to process the "target" attributes and
32220 provide the code to dispatch the right function at run-time. NODE points
32221 to the dispatcher decl whose body will be created. */
32223 static tree
32225 {
32226 tree resolver_decl;
32227 basic_block empty_bb;
32228 tree default_ver_decl;
32244 /* The first version in the chain corresponds to the default version. */
32247 /* node is going to be an alias, so remove the finalized bit. */
32261 {
32263 /* Check for virtual functions here again, as by this time it should
32264 have been determined if this function needs a vtable index or
32265 not. This happens for methods in derived classes that override
32266 virtual methods in base classes but are not explicitly marked as
32267 virtual. */
32272 }
32278 }
32279 /* This builds the processor_model struct type defined in
32280 libgcc/config/i386/cpuinfo.c */
32282 static tree
32284 {
32291 /* The first 3 fields are unsigned int. */
32293 {
32299 }
32301 /* The last field is an array of unsigned integers of size one. */
32312 }
32314 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32316 static tree
32318 {
32319 tree new_decl;
32322 VAR_DECL,
32324 type);
32337 }
32339 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32340 into an integer defined in libgcc/config/i386/cpuinfo.c */
32342 static tree
32344 {
32350 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32351 enum processor_features
32352 {
32354 F_MMX,
32355 F_POPCNT,
32356 F_SSE,
32357 F_SSE2,
32358 F_SSE3,
32359 F_SSSE3,
32360 F_SSE4_1,
32361 F_SSE4_2,
32362 F_AVX,
32363 F_AVX2,
32364 F_SSE4_A,
32365 F_FMA4,
32366 F_XOP,
32367 F_FMA,
32368 F_MAX
32369 };
32371 /* These are the values for vendor types and cpu types and subtypes
32372 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32373 the corresponding start value. */
32374 enum processor_model
32375 {
32377 M_AMD,
32378 M_CPU_TYPE_START,
32379 M_INTEL_BONNELL,
32380 M_INTEL_CORE2,
32381 M_INTEL_COREI7,
32382 M_AMDFAM10H,
32383 M_AMDFAM15H,
32384 M_INTEL_SILVERMONT,
32385 M_AMD_BTVER1,
32386 M_AMD_BTVER2,
32387 M_CPU_SUBTYPE_START,
32388 M_INTEL_COREI7_NEHALEM,
32389 M_INTEL_COREI7_WESTMERE,
32390 M_INTEL_COREI7_SANDYBRIDGE,
32391 M_AMDFAM10H_BARCELONA,
32392 M_AMDFAM10H_SHANGHAI,
32393 M_AMDFAM10H_ISTANBUL,
32394 M_AMDFAM15H_BDVER1,
32395 M_AMDFAM15H_BDVER2,
32396 M_AMDFAM15H_BDVER3,
32397 M_AMDFAM15H_BDVER4,
32398 M_INTEL_COREI7_IVYBRIDGE,
32399 M_INTEL_COREI7_HASWELL
32400 };
32402 static struct _arch_names_table
32403 {
32406 }
32408 {
32433 };
32435 static struct _isa_names_table
32436 {
32439 }
32441 {
32457 };
32471 {
32472 /* *args must be a expr that can contain other EXPRS leading to a
32473 STRING_CST. */
32475 {
32478 }
32480 }
32485 {
32486 tree ref;
32487 tree field;
32488 tree final;
32491 unsigned int NUM_ARCH_NAMES
32500 {
32504 }
32509 /* CPU types are stored in the next field. */
32512 {
32515 }
32517 /* CPU subtypes are stored in the next field. */
32519 {
32522 }
32524 /* Get the appropriate field in __cpu_model. */
32528 /* Check the value. */
32532 }
32534 {
32535 tree ref;
32536 tree array_elt;
32537 tree field;
32538 tree final;
32541 unsigned int NUM_ISA_NAMES
32550 {
32554 }
32557 /* Get the last field, which is __cpu_features. */
32561 /* Get the appropriate field: __cpu_model.__cpu_features */
32565 /* Access the 0th element of __cpu_features array. */
32570 /* Return __cpu_model.__cpu_features[0] & field_val */
32574 }
32576 }
32578 static tree
32581 {
32583 {
32588 {
32591 }
32592 }
32594 #ifdef SUBTARGET_FOLD_BUILTIN
32596 #endif
32599 }
32601 /* Make builtins to detect cpu type and features supported. NAME is
32602 the builtin name, CODE is the builtin code, and FTYPE is the function
32603 type of the builtin. */
32605 static void
32608 {
32609 tree decl;
32610 tree type;
32618 }
32620 /* Make builtins to get CPU type and features supported. The created
32621 builtins are :
32623 __builtin_cpu_init (), to detect cpu type and features,
32624 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32625 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32626 */
32628 static void
32630 {
32637 }
32639 /* Internal method for ix86_init_builtins. */
32641 static void
32643 {
32655 sysv_va_ref =
32658 fnvoid_va_end_ms =
32660 fnvoid_va_start_ms =
32662 fnvoid_va_end_sysv =
32664 fnvoid_va_start_sysv =
32666 NULL_TREE);
32667 fnvoid_va_copy_ms =
32669 NULL_TREE);
32670 fnvoid_va_copy_sysv =
32686 }
32688 static void
32690 {
32693 /* The __float80 type. */
32696 {
32697 /* The __float80 type. */
32702 }
32705 /* The __float128 type. */
32711 /* This macro is built by i386-builtin-types.awk. */
32712 DEFINE_BUILTIN_PRIMITIVE_TYPES;
32713 }
32715 static void
32717 {
32718 tree t;
32722 /* Builtins to get CPU type and features. */
32725 /* TFmode support builtins. */
32731 /* We will expand them to normal call if SSE isn't available since
32732 they are used by libgcc. */
32751 #ifdef SUBTARGET_INIT_BUILTINS
32752 SUBTARGET_INIT_BUILTINS;
32753 #endif
32754 }
32756 /* Return the ix86 builtin for CODE. */
32758 static tree
32760 {
32765 }
32767 /* Errors in the source file can cause expand_expr to return const0_rtx
32768 where we expect a vector. To avoid crashing, use one of the vector
32769 clear instructions. */
32770 static rtx
32772 {
32776 }
32778 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
32780 static rtx
32782 {
32783 rtx pat;
32803 {
32807 }
32821 }
32823 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
32825 static rtx
32829 {
32830 rtx pat;
32838 rtx op;
32845 {
32925 }
32935 {
32942 {
32944 {
32947 {
32965 xop_rotl:
32967 {
32970 gcc_checking_assert
32972 }
32973 else
32974 {
32975 gcc_checking_assert
32986 }
32990 }
32991 }
32992 }
32993 else
32994 {
32995 non_constant:
32999 /* If we aren't optimizing, only allow one memory operand to be
33000 generated. */
33002 num_memory++;
33010 }
33014 }
33017 {
33028 else
33029 {
33035 }
33048 }
33055 }
33057 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
33058 insns with vec_merge. */
33060 static rtx
33062 rtx target)
33063 {
33064 rtx pat;
33091 }
33093 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33095 static rtx
33098 {
33099 rtx pat;
33104 rtx op2;
33115 /* Swap operands if we have a comparison that isn't available in
33116 hardware. */
33118 {
33123 }
33143 }
33145 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33147 static rtx
33149 rtx target)
33150 {
33151 rtx pat;
33165 /* Swap operands if we have a comparison that isn't available in
33166 hardware. */
33168 {
33172 }
33193 const0_rtx)));
33196 }
33198 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33200 static rtx
33202 rtx target)
33203 {
33204 rtx pat;
33229 }
33231 static rtx
33234 {
33235 rtx pat;
33240 rtx op2;
33267 }
33269 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33271 static rtx
33273 rtx target)
33274 {
33275 rtx pat;
33308 const0_rtx)));
33311 }
33313 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33315 static rtx
33318 {
33319 rtx pat;
33357 {
33360 }
33363 {
33372 }
33374 {
33383 }
33384 else
33385 {
33392 }
33400 {
33405 emit_insn
33409 FLAGS_REG),
33410 const0_rtx)));
33412 }
33413 else
33415 }
33418 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33420 static rtx
33423 {
33424 rtx pat;
33452 {
33455 }
33458 {
33467 }
33469 {
33478 }
33479 else
33480 {
33487 }
33495 {
33500 emit_insn
33504 FLAGS_REG),
33505 const0_rtx)));
33507 }
33508 else
33510 }
33512 /* Subroutine of ix86_expand_builtin to take care of insns with
33513 variable number of operands. */
33515 static rtx
33518 {
33524 struct
33525 {
33526 rtx op;
33538 {
33986 }
33991 {
33994 }
33997 {
34004 }
34005 else
34006 {
34009 }
34012 {
34019 {
34020 /* SIMD shift insns take either an 8-bit immediate or
34021 register as count. But builtin functions take int as
34022 count. If count doesn't match, we put it in register. */
34024 {
34028 }
34029 }
34032 {
34035 {
34111 {
34115 {
34118 }
34124 }
34126 }
34127 }
34128 else
34129 {
34133 /* If we aren't optimizing, only allow one memory operand to
34134 be generated. */
34136 num_memory++;
34139 {
34142 }
34143 else
34144 {
34147 }
34148 }
34152 }
34155 {
34180 }
34187 }
34189 /* Transform pattern of following layout:
34190 (parallel [
34191 set (A B)
34192 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34193 ])
34194 into:
34195 (set (A B))
34197 Or:
34198 (parallel [ A B
34199 ...
34200 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34201 ...
34202 ])
34203 into:
34204 (parallel [ A B ... ]) */
34206 static rtx
34208 {
34215 {
34224 }
34225 else
34226 {
34232 {
34237 }
34239 /* No more than 1 occurence was removed. */
34243 }
34244 }
34246 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34247 with rounding. */
34248 static rtx
34251 {
34268 /* See avxintrin.h for values. */
34270 {
34274 };
34276 {
34281 };
34284 {
34287 }
34289 {
34292 }
34295 {
34298 }
34321 ? CODE_FOR_sse_ucomi_round
34328 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34330 {
34336 }
34337 else
34338 {
34341 }
34347 set_dst,
34348 const0_rtx)));
34351 }
34353 static rtx
34356 {
34357 rtx pat;
34359 struct
34360 {
34361 rtx op;
34371 {
34448 }
34458 {
34465 {
34467 {
34469 {
34485 }
34486 }
34487 }
34489 {
34491 {
34494 }
34496 /* If there is no rounding use normal version of the pattern. */
34499 }
34500 else
34501 {
34506 {
34509 }
34510 else
34511 {
34514 }
34515 }
34519 }
34522 {
34547 }
34557 }
34559 /* Subroutine of ix86_expand_builtin to take care of special insns
34560 with variable number of operands. */
34562 static rtx
34565 {
34566 tree arg;
34570 struct
34571 {
34572 rtx op;
34582 {
34621 {
34629 }
34648 /* Reserve memory operand for target. */
34651 {
34652 /* These builtins and instructions require the memory
34653 to be properly aligned. */
34672 }
34697 {
34698 /* These builtins and instructions require the memory
34699 to be properly aligned. */
34708 }
34709 /* FALLTHRU */
34727 /* Reserve memory operand for target. */
34740 {
34741 /* These builtins and instructions require the memory
34742 to be properly aligned. */
34751 }
34764 }
34769 {
34774 {
34777 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
34778 on it. Try to improve it using get_pointer_alignment,
34779 and if the special builtin is one that requires strict
34780 mode alignment, also from it's GET_MODE_ALIGNMENT.
34781 Failure to do so could lead to ix86_legitimate_combined_insn
34782 rejecting all changes to such insns. */
34788 }
34789 else
34792 }
34793 else
34794 {
34801 }
34804 {
34813 {
34815 {
34821 else
34824 }
34825 }
34826 else
34827 {
34829 {
34830 /* This must be the memory operand. */
34833 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
34834 on it. Try to improve it using get_pointer_alignment,
34835 and if the special builtin is one that requires strict
34836 mode alignment, also from it's GET_MODE_ALIGNMENT.
34837 Failure to do so could lead to ix86_legitimate_combined_insn
34838 rejecting all changes to such insns. */
34844 }
34845 else
34846 {
34847 /* This must be register. */
34853 else
34854 {
34857 }
34858 }
34859 }
34863 }
34866 {
34881 }
34887 }
34889 /* Return the integer constant in ARG. Constrain it to be in the range
34890 of the subparts of VEC_TYPE; issue an error if not. */
34892 static int
34894 {
34899 {
34902 }
34905 }
34907 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34908 ix86_expand_vector_init. We DO have language-level syntax for this, in
34909 the form of (type){ init-list }. Except that since we can't place emms
34910 instructions from inside the compiler, we can't allow the use of MMX
34911 registers unless the user explicitly asks for it. So we do *not* define
34912 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
34913 we have builtins invoked by mmintrin.h that gives us license to emit
34914 these sorts of instructions. */
34916 static rtx
34918 {
34928 {
34931 }
34938 }
34940 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34941 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
34942 had a language-level syntax for referencing vector elements. */
34944 static rtx
34946 {
34950 rtx op0;
34970 }
34972 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34973 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
34974 a language-level syntax for referencing vector elements. */
34976 static rtx
34978 {
35002 /* OP0 is the source of these builtin functions and shouldn't be
35003 modified. Create a copy, use it and return it as target. */
35009 }
35011 /* Expand an expression EXP that calls a built-in function,
35012 with result going to TARGET if that's convenient
35013 (and in mode MODE if that's convenient).
35014 SUBTARGET may be used as the target for computing one of EXP's operands.
35015 IGNORE is nonzero if the value is to be ignored. */
35017 static rtx
35020 {
35030 /* For CPU builtins that can be folded, fold first and expand the fold. */
35032 {
35034 {
35035 /* Make it call __cpu_indicator_init in libgcc. */
35041 }
35044 {
35049 }
35050 }
35052 /* Determine whether the builtin function is available under the current ISA.
35053 Originally the builtin was not created if it wasn't applicable to the
35054 current ISA based on the command line switches. With function specific
35055 options, we need to check in the context of the function making the call
35056 whether it is supported. */
35059 {
35065 else
35066 {
35070 }
35072 }
35075 {
35079 ? CODE_FOR_mmx_maskmovq
35081 /* Note the arg order is different from the operand order. */
35192 {
35193 REAL_VALUE_TYPE inf;
35194 rtx tmp;
35206 }
35216 {
35222 insn = (TARGET_64BIT
35226 }
35228 {
35229 insn = (TARGET_64BIT
35233 }
35234 else
35235 {
35238 insn = (TARGET_64BIT
35246 {
35249 }
35251 }
35254 {
35255 /* mode is VOIDmode if __builtin_rd* has been called
35256 without lhs. */
35260 }
35263 {
35268 }
35282 {
35307 }
35313 {
35316 }
35342 {
35345 }
35351 {
35355 {
35394 }
35399 }
35400 else
35401 {
35403 {
35424 }
35426 }
35456 ? CODE_FOR_tbm_bextri_si
35459 {
35462 }
35463 else
35464 {
35473 }
35489 rdrand_step:
35496 {
35499 }
35505 /* Emit SImode conditional move. */
35507 {
35510 }
35513 else
35521 const0_rtx);
35540 rdseed_step:
35547 {
35550 }
35556 const0_rtx);
35575 addcarryx:
35583 /* Generate CF from input operand. */
35588 /* Gen ADCX instruction to compute X+Y+CF. */
35603 /* Store the result. */
35606 {
35609 }
35612 /* Return current CF value. */
35654 kortest:
35668 /* Emit kortest. */
35670 /* And use setcc to return result from flags. */
35821 gather_gen:
35822 rtx half;
35835 /* Note the arg order is different from the operand order. */
35846 else
35850 {
35872 else
35879 {
35884 }
35891 else
35898 {
35903 }
35907 }
35909 /* Force memory operand only with base register here. But we
35910 don't want to do it on memory operand for other builtin
35911 functions. */
35921 {
35924 }
35925 else
35926 {
35929 }
35931 {
35934 }
35936 /* Optimize. If mask is known to have all high bits set,
35937 replace op0 with pc_rtx to signal that the instruction
35938 overwrites the whole destination and doesn't use its
35939 previous contents. */
35941 {
35943 {
35946 }
35948 {
35951 {
35955 negative++;
35958 negative++;
35959 }
35962 }
35965 {
35966 /* Recognize also when mask is like:
35967 __v2df src = _mm_setzero_pd ();
35968 __v2df mask = _mm_cmpeq_pd (src, src);
35969 or
35970 __v8sf src = _mm256_setzero_ps ();
35971 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
35972 as that is a cheaper way to load all ones into
35973 a register than having to load a constant from
35974 memory. */
35977 {
35982 {
35989 /* FALLTHRU */
35999 }
36000 }
36001 }
36002 }
36010 {
36034 }
36037 scatter_gen:
36053 /* Force memory operand only with base register here. But we
36054 don't want to do it on memory operand for other builtin
36055 functions. */
36062 {
36065 }
36066 else
36067 {
36070 }
36079 {
36082 }
36091 vec_prefetch_gen:
36109 {
36112 }
36114 {
36117 }
36122 /* Force memory operand only with base register here. But we
36123 don't want to do it on memory operand for other builtin
36124 functions. */
36131 {
36134 }
36137 {
36140 }
36156 {
36159 }
36165 }
36178 {
36182 /* Emit a normal call if SSE isn't available. */
36186 }
36215 }
36217 /* This returns the target-specific builtin with code CODE if
36218 current_function_decl has visibility on this builtin, which is checked
36219 using isa flags. Returns NULL_TREE otherwise. */
36222 {
36226 /* Determine the isa flags of current_function_decl. */
36238 else
36240 }
36242 /* Returns a function decl for a vectorized version of the builtin function
36243 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36244 if it is not available. */
36246 static tree
36248 tree type_in)
36249 {
36265 {
36268 {
36275 }
36280 {
36283 }
36288 {
36295 }
36301 /* The round insn does not trap on denormals. */
36306 {
36313 }
36319 /* The round insn does not trap on denormals. */
36324 {
36329 }
36335 /* The round insn does not trap on denormals. */
36340 {
36347 }
36353 /* The round insn does not trap on denormals. */
36358 {
36363 }
36370 {
36375 }
36382 {
36387 }
36393 /* The round insn does not trap on denormals. */
36398 {
36405 }
36411 /* The round insn does not trap on denormals. */
36416 {
36421 }
36426 {
36433 }
36438 {
36445 }
36449 /* The round insn does not trap on denormals. */
36454 {
36459 }
36463 /* The round insn does not trap on denormals. */
36468 {
36473 }
36477 /* The round insn does not trap on denormals. */
36482 {
36487 }
36491 /* The round insn does not trap on denormals. */
36496 {
36501 }
36505 /* The round insn does not trap on denormals. */
36510 {
36515 }
36519 /* The round insn does not trap on denormals. */
36524 {
36529 }
36533 /* The round insn does not trap on denormals. */
36538 {
36543 }
36547 /* The round insn does not trap on denormals. */
36552 {
36557 }
36561 /* The round insn does not trap on denormals. */
36566 {
36571 }
36575 /* The round insn does not trap on denormals. */
36580 {
36585 }
36590 {
36595 }
36600 {
36605 }
36610 }
36612 /* Dispatch to a handler for a vectorization library. */
36615 type_in);
36618 }
36620 /* Handler for an SVML-style interface to
36621 a library with vectorized intrinsics. */
36623 static tree
36625 {
36633 /* The SVML is suitable for unsafe math only. */
36646 {
36693 }
36702 {
36705 }
36706 else
36709 /* Convert to uppercase. */
36714 args;
36716 arity++;
36720 else
36723 /* Build a function declaration for the vectorized function. */
36732 }
36734 /* Handler for an ACML-style interface to
36735 a library with vectorized intrinsics. */
36737 static tree
36739 {
36747 /* The ACML is 64bits only and suitable for unsafe math only as
36748 it does not correctly support parts of IEEE with the required
36749 precision such as denormals. */
36763 {
36793 }
36800 args;
36802 arity++;
36806 else
36809 /* Build a function declaration for the vectorized function. */
36818 }
36820 /* Returns a decl of a function that implements gather load with
36821 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
36822 Return NULL_TREE if it is not available. */
36824 static tree
36827 {
36843 /* v*gather* insn sign extends index to pointer mode. */
36855 {
36883 else
36889 else
36895 else
36901 else
36906 }
36909 }
36911 /* Returns a code for a target-specific builtin that implements
36912 reciprocal of the function, or NULL_TREE if not available. */
36914 static tree
36917 {
36924 /* Machine dependent builtins. */
36926 {
36927 /* Vectorized version of sqrt to rsqrt conversion. */
36936 }
36937 else
36938 /* Normal builtins. */
36940 {
36941 /* Sqrt to rsqrt conversion. */
36947 }
36948 }
36949 \f
36950 /* Helper for avx_vpermilps256_operand et al. This is also used by
36951 the expansion functions to turn the parallel back into a mask.
36952 The return value is 0 for no match and the imm8+1 for a match. */
36954 int
36956 {
36964 /* Validate that all of the elements are constants, and not totally
36965 out of range. Copy the data into an integral array to make the
36966 subsequent checks easier. */
36968 {
36978 }
36981 {
36983 /* In the 512-bit DFmode case, we can only move elements within
36984 a 128-bit lane. First fill the second part of the mask,
36985 then fallthru. */
36987 {
36991 }
36993 {
36997 }
36998 /* FALLTHRU */
37001 /* In the 256-bit DFmode case, we can only move elements within
37002 a 128-bit lane. */
37004 {
37008 }
37010 {
37014 }
37018 /* In 512 bit SFmode case, permutation in the upper 256 bits
37019 must mirror the permutation in the lower 256-bits. */
37023 /* FALLTHRU */
37026 /* In 256 bit SFmode case, we have full freedom of
37027 movement within the low 128-bit lane, but the high 128-bit
37028 lane must mirror the exact same pattern. */
37033 /* FALLTHRU */
37037 /* In the 128-bit case, we've full freedom in the placement of
37038 the elements from the source operand. */
37045 }
37047 /* Make sure success has a non-zero value by adding one. */
37049 }
37051 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
37052 the expansion functions to turn the parallel back into a mask.
37053 The return value is 0 for no match and the imm8+1 for a match. */
37055 int
37057 {
37065 /* Validate that all of the elements are constants, and not totally
37066 out of range. Copy the data into an integral array to make the
37067 subsequent checks easier. */
37069 {
37079 }
37081 /* Validate that the halves of the permute are halves. */
37089 /* Reconstruct the mask. */
37091 {
37097 }
37099 /* Make sure success has a non-zero value by adding one. */
37101 }
37102 \f
37103 /* Return a register priority for hard reg REGNO. */
37104 static int
37106 {
37107 /* ebp and r13 as the base always wants a displacement, r12 as the
37108 base always wants an index. So discourage their usage in an
37109 address. */
37114 /* New x86-64 int registers result in bigger code size. Discourage
37115 them. */
37118 /* New x86-64 SSE registers result in bigger code size. Discourage
37119 them. */
37122 /* Usage of AX register results in smaller code. Prefer it. */
37126 }
37128 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37130 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37131 QImode must go into class Q_REGS.
37132 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37133 movdf to do mem-to-mem moves through integer regs. */
37135 static reg_class_t
37137 {
37140 /* We're only allowed to return a subclass of CLASS. Many of the
37141 following checks fail for NO_REGS, so eliminate that early. */
37145 /* All classes can load zeros. */
37149 /* Force constants into memory if we are loading a (nonzero) constant into
37150 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37151 instructions to load from a constant. */
37158 /* Prefer SSE regs only, if we can use them for math. */
37162 /* Floating-point constants need more complex checks. */
37164 {
37165 /* General regs can load everything. */
37169 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37170 zero above. We only want to wind up preferring 80387 registers if
37171 we plan on doing computation with them. */
37174 {
37175 /* Limit class to non-sse. */
37184 }
37187 }
37189 /* Generally when we see PLUS here, it's the function invariant
37190 (plus soft-fp const_int). Which can only be computed into general
37191 regs. */
37195 /* QImode constants are easy to load, but non-constant QImode data
37196 must go into Q_REGS. */
37198 {
37204 }
37207 }
37209 /* Discourage putting floating-point values in SSE registers unless
37210 SSE math is being used, and likewise for the 387 registers. */
37211 static reg_class_t
37213 {
37216 /* Restrict the output reload class to the register bank that we are doing
37217 math on. If we would like not to return a subset of CLASS, reject this
37218 alternative: if reload cannot do this, it will still use its choice. */
37224 {
37229 else
37231 }
37234 }
37236 static reg_class_t
37239 {
37240 /* Double-word spills from general registers to non-offsettable memory
37241 references (zero-extended addresses) require special handling. */
37247 {
37249 ? CODE_FOR_reload_noff_load
37251 /* Add the cost of moving address to a temporary. */
37255 }
37257 /* QImode spills from non-QI registers require
37258 intermediate register on 32bit targets. */
37264 {
37269 else
37275 /* Return Q_REGS if the operand is in memory. */
37278 }
37280 /* This condition handles corner case where an expression involving
37281 pointers gets vectorized. We're trying to use the address of a
37282 stack slot as a vector initializer.
37284 (set (reg:V2DI 74 [ vect_cst_.2 ])
37285 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37287 Eventually frame gets turned into sp+offset like this:
37289 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37290 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37291 (const_int 392 [0x188]))))
37293 That later gets turned into:
37295 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37296 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37297 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37299 We'll have the following reload recorded:
37301 Reload 0: reload_in (DI) =
37302 (plus:DI (reg/f:DI 7 sp)
37303 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37304 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37305 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37306 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37307 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37308 reload_reg_rtx: (reg:V2DI 22 xmm1)
37310 Which isn't going to work since SSE instructions can't handle scalar
37311 additions. Returning GENERAL_REGS forces the addition into integer
37312 register and reload can handle subsequent reloads without problems. */
37320 }
37322 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37324 static bool
37326 {
37328 {
37343 }
37346 }
37348 /* If we are copying between general and FP registers, we need a memory
37349 location. The same is true for SSE and MMX registers.
37351 To optimize register_move_cost performance, allow inline variant.
37353 The macro can't work reliably when one of the CLASSES is class containing
37354 registers from multiple units (SSE, MMX, integer). We avoid this by never
37355 combining those units in single alternative in the machine description.
37356 Ensure that this constraint holds to avoid unexpected surprises.
37358 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37359 enforce these sanity checks. */
37364 {
37373 {
37376 }
37381 /* ??? This is a lie. We do have moves between mmx/general, and for
37382 mmx/sse2. But by saying we need secondary memory we discourage the
37383 register allocator from using the mmx registers unless needed. */
37388 {
37389 /* SSE1 doesn't have any direct moves from other classes. */
37393 /* If the target says that inter-unit moves are more expensive
37394 than moving through memory, then don't generate them. */
37399 /* Between SSE and general, we have moves no larger than word size. */
37402 }
37405 }
37407 bool
37410 {
37412 }
37414 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37416 On the 80386, this is the size of MODE in words,
37417 except in the FP regs, where a single reg is always enough. */
37419 static unsigned char
37421 {
37423 {
37428 else
37430 }
37431 else
37432 {
37435 else
37437 }
37438 }
37440 /* Return true if the registers in CLASS cannot represent the change from
37441 modes FROM to TO. */
37443 bool
37446 {
37450 /* x87 registers can't do subreg at all, as all values are reformatted
37451 to extended precision. */
37456 {
37457 /* Vector registers do not support QI or HImode loads. If we don't
37458 disallow a change to these modes, reload will assume it's ok to
37459 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37460 the vec_dupv4hi pattern. */
37464 /* Vector registers do not support subreg with nonzero offsets, which
37465 are otherwise valid for integer registers. Since we can't see
37466 whether we have a nonzero offset from here, prohibit all
37467 nonparadoxical subregs changing size. */
37470 }
37473 }
37475 /* Return the cost of moving data of mode M between a
37476 register and memory. A value of 2 is the default; this cost is
37477 relative to those in `REGISTER_MOVE_COST'.
37479 This function is used extensively by register_move_cost that is used to
37480 build tables at startup. Make it inline in this case.
37481 When IN is 2, return maximum of in and out move cost.
37483 If moving between registers and memory is more expensive than
37484 between two registers, you should define this macro to express the
37485 relative cost.
37487 Model also increased moving costs of QImode registers in non
37488 Q_REGS classes.
37489 */
37493 {
37496 {
37499 {
37511 }
37515 }
37517 {
37520 {
37532 }
37536 }
37538 {
37541 {
37550 }
37554 }
37556 {
37559 {
37565 else
37570 }
37571 else
37572 {
37577 else
37579 }
37586 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37593 else
37597 }
37598 }
37600 static int
37603 {
37605 }
37608 /* Return the cost of moving data from a register in class CLASS1 to
37609 one in class CLASS2.
37611 It is not required that the cost always equal 2 when FROM is the same as TO;
37612 on some machines it is expensive to move between registers if they are not
37613 general registers. */
37615 static int
37617 reg_class_t class2_i)
37618 {
37622 /* In case we require secondary memory, compute cost of the store followed
37623 by load. In order to avoid bad register allocation choices, we need
37624 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37627 {
37633 /* In case of copying from general_purpose_register we may emit multiple
37634 stores followed by single load causing memory size mismatch stall.
37635 Count this as arbitrarily high cost of 20. */
37640 /* In the case of FP/MMX moves, the registers actually overlap, and we
37641 have to switch modes in order to treat them differently. */
37647 }
37649 /* Moves between SSE/MMX and integer unit are expensive. */
37653 /* ??? By keeping returned value relatively high, we limit the number
37654 of moves between integer and MMX/SSE registers for all targets.
37655 Additionally, high value prevents problem with x86_modes_tieable_p(),
37656 where integer modes in MMX/SSE registers are not tieable
37657 because of missing QImode and HImode moves to, from or between
37658 MMX/SSE registers. */
37668 }
37670 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37671 MODE. */
37673 bool
37675 {
37676 /* Flags and only flags can only hold CCmode values. */
37688 {
37689 /* We implement the move patterns for all vector modes into and
37690 out of SSE registers, even when no operation instructions
37691 are available. */
37693 /* For AVX-512 we allow, regardless of regno:
37694 - XI mode
37695 - any of 512-bit wide vector mode
37696 - any scalar mode. */
37703 /* xmm16-xmm31 are only available for AVX-512. */
37707 /* OImode and AVX modes are available only when AVX is enabled. */
37714 }
37716 {
37717 /* We implement the move patterns for 3DNOW modes even in MMX mode,
37718 so if the register is available at all, then we can move data of
37719 the given mode into or out of it. */
37722 }
37725 {
37726 /* Take care for QImode values - they can be in non-QI regs,
37727 but then they do cause partial register stalls. */
37732 /* LRA checks if the hard register is OK for the given mode.
37733 QImode values can live in non-QI regs, so we allow all
37734 registers here. */
37738 }
37739 /* We handle both integer and floats in the general purpose registers. */
37746 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
37747 on to use that value in smaller contexts, this can easily force a
37748 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
37749 supporting DImode, allow it. */
37754 }
37756 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
37757 tieable integer mode. */
37759 static bool
37761 {
37763 {
37776 }
37777 }
37779 /* Return true if MODE1 is accessible in a register that can hold MODE2
37780 without copying. That is, all register classes that can hold MODE2
37781 can also hold MODE1. */
37783 bool
37785 {
37793 /* MODE2 being XFmode implies fp stack or general regs, which means we
37794 can tie any smaller floating point modes to it. Note that we do not
37795 tie this with TFmode. */
37799 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
37800 that we can tie it with SFmode. */
37804 /* If MODE2 is only appropriate for an SSE register, then tie with
37805 any other mode acceptable to SSE registers. */
37815 /* If MODE2 is appropriate for an MMX register, then tie
37816 with any other mode acceptable to MMX registers. */
37823 }
37825 /* Return the cost of moving between two registers of mode MODE. */
37827 static int
37829 {
37833 {
37865 }
37867 /* Return the cost of moving between two registers of mode MODE,
37868 assuming that the move will be in pieces of at most UNITS bytes. */
37870 }
37872 /* Compute a (partial) cost for rtx X. Return true if the complete
37873 cost has been computed, and false if subexpressions should be
37874 scanned. In either case, *TOTAL contains the cost result. */
37876 static bool
37879 {
37880 rtx mask;
37887 {
37891 {
37894 }
37906 && !(TARGET_64BIT
37911 else
37917 {
37920 }
37922 {
37932 }
37934 {
37937 {
37946 }
37947 }
37948 /* Fall back to (MEM (SYMBOL_REF)), since that's where
37949 it'll probably end up. Add a penalty for size. */
37956 /* The zero extensions is often completely free on x86_64, so make
37957 it as cheap as possible. */
37963 else
37975 {
37978 {
37981 }
37984 {
37987 }
37988 }
37989 /* FALLTHRU */
37996 {
37997 /* ??? Should be SSE vector operation cost. */
37998 /* At least for published AMD latencies, this really is the same
37999 as the latency for a simple fpu operation like fabs. */
38000 /* V*QImode is emulated with 1-11 insns. */
38002 {
38005 {
38006 /* For XOP we use vpshab, which requires a broadcast of the
38007 value to the variable shift insn. For constants this
38008 means a V16Q const in mem; even when we can perform the
38009 shift with one insn set the cost to prefer paddb. */
38011 {
38016 }
38018 }
38022 }
38023 else
38025 }
38027 {
38029 {
38032 else
38034 }
38035 else
38036 {
38039 else
38041 }
38042 }
38043 else
38044 {
38049 {
38050 /* Return the cost after shift-and truncation. */
38053 }
38054 else
38056 }
38060 {
38061 rtx sub;
38066 /* ??? SSE scalar/vector cost should be used here. */
38067 /* ??? Bald assumption that fma has the same cost as fmul. */
38071 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38082 }
38086 {
38087 /* ??? SSE scalar cost should be used here. */
38090 }
38092 {
38095 }
38097 {
38098 /* ??? SSE vector cost should be used here. */
38101 }
38103 {
38104 /* V*QImode is emulated with 7-13 insns. */
38106 {
38113 }
38114 /* V*DImode is emulated with 5-8 insns. */
38116 {
38119 else
38121 }
38122 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38123 insns, including two PMULUDQ. */
38126 else
38129 }
38130 else
38131 {
38136 {
38139 nbits++;
38140 }
38141 else
38142 /* This is arbitrary. */
38145 /* Compute costs correctly for widening multiplication. */
38149 {
38156 {
38160 else
38162 }
38166 }
38174 }
38181 /* ??? SSE cost should be used here. */
38186 /* ??? SSE vector cost should be used here. */
38188 else
38195 {
38200 {
38203 {
38211 }
38212 }
38215 {
38218 {
38224 }
38225 }
38227 {
38235 }
38236 }
38237 /* FALLTHRU */
38241 {
38242 /* ??? SSE cost should be used here. */
38245 }
38247 {
38250 }
38252 {
38253 /* ??? SSE vector cost should be used here. */
38256 }
38257 /* FALLTHRU */
38264 {
38271 }
38272 /* FALLTHRU */
38276 {
38277 /* ??? SSE cost should be used here. */
38280 }
38282 {
38285 }
38287 {
38288 /* ??? SSE vector cost should be used here. */
38291 }
38292 /* FALLTHRU */
38296 {
38297 /* ??? Should be SSE vector operation cost. */
38298 /* At least for published AMD latencies, this really is the same
38299 as the latency for a simple fpu operation like fabs. */
38301 }
38304 else
38313 {
38314 /* This kind of construct is implemented using test[bwl].
38315 Treat it as if we had an AND. */
38320 }
38330 /* ??? SSE cost should be used here. */
38335 /* ??? SSE vector cost should be used here. */
38341 /* ??? SSE cost should be used here. */
38346 /* ??? SSE vector cost should be used here. */
38358 /* ??? Assume all of these vector manipulation patterns are
38359 recognizable. In which case they all pretty much have the
38360 same cost. */
38365 /* This is masked instruction, assume the same cost,
38366 as nonmasked variant. */
38369 else
38375 }
38376 }
38378 #if TARGET_MACHO
38382 /* Given a symbol name and its associated stub, write out the
38383 definition of the stub. */
38385 void
38387 {
38392 /* For 64-bit we shouldn't get here. */
38395 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38412 else
38419 {
38421 }
38423 {
38424 /* PIC stub. */
38425 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38431 }
38432 else
38435 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38436 it needs no stub-binding-helper. */
38443 {
38446 }
38447 else
38452 /* N.B. Keep the correspondence of these
38453 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38454 old-pic/new-pic/non-pic stubs; altering this will break
38455 compatibility with existing dylibs. */
38457 {
38458 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38460 }
38461 else
38462 /* 16-byte -mdynamic-no-pic stub. */
38468 }
38471 /* Order the registers for register allocator. */
38473 void
38475 {
38479 /* First allocate the local general purpose registers. */
38484 /* Global general purpose registers. */
38489 /* x87 registers come first in case we are doing FP math
38490 using them. */
38495 /* SSE registers. */
38501 /* Extended REX SSE registers. */
38505 /* Mask register. */
38509 /* x87 registers. */
38517 /* Initialize the rest of array as we do not allocate some registers
38518 at all. */
38521 }
38523 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38524 in struct attribute_spec handler. */
38525 static tree
38527 tree args,
38530 {
38535 {
38537 name);
38540 }
38542 {
38544 name);
38547 }
38549 {
38550 tree cst;
38554 {
38557 name);
38559 }
38562 {
38565 name);
38567 }
38570 }
38573 }
38575 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38576 struct attribute_spec.handler. */
38577 static tree
38579 tree args ATTRIBUTE_UNUSED,
38581 {
38586 {
38588 name);
38591 }
38593 /* Can combine regparm with all attributes but fastcall. */
38595 {
38597 {
38599 }
38602 }
38604 {
38606 {
38608 }
38611 }
38614 }
38616 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38617 struct attribute_spec.handler. */
38618 static tree
38620 tree args ATTRIBUTE_UNUSED,
38622 {
38625 {
38628 }
38629 else
38633 {
38635 name);
38637 }
38643 {
38645 name);
38647 }
38650 }
38652 static tree
38654 tree args ATTRIBUTE_UNUSED,
38656 {
38658 {
38660 name);
38662 }
38664 }
38666 static bool
38668 {
38672 }
38674 /* Returns an expression indicating where the this parameter is
38675 located on entry to the FUNCTION. */
38677 static rtx
38679 {
38685 {
38690 else
38693 }
38698 {
38705 {
38710 }
38711 else
38712 {
38715 {
38721 }
38722 }
38724 }
38728 }
38730 /* Determine whether x86_output_mi_thunk can succeed. */
38732 static bool
38734 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
38736 {
38737 /* 64-bit can handle anything. */
38741 /* For 32-bit, everything's fine if we have one free register. */
38745 /* Need a free register for vcall_offset. */
38749 /* Need a free register for GOT references. */
38753 /* Otherwise ok. */
38755 }
38757 /* Output the assembler code for a thunk function. THUNK_DECL is the
38758 declaration for the thunk function itself, FUNCTION is the decl for
38759 the target function. DELTA is an immediate constant offset to be
38760 added to THIS. If VCALL_OFFSET is nonzero, the word at
38761 *(*this + vcall_offset) should be added to THIS. */
38763 static void
38767 {
38774 else
38775 {
38781 else
38783 }
38787 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
38788 pull it in now and let DELTA benefit. */
38792 {
38793 /* Put the this parameter into %eax. */
38796 }
38797 else
38800 /* Adjust the this parameter by a fixed constant. */
38802 {
38807 {
38809 {
38813 }
38814 }
38817 }
38819 /* Adjust the this parameter by a value stored in the vtable. */
38821 {
38831 /* Adjust the this parameter. */
38835 {
38839 }
38846 vcall_mem));
38847 else
38849 }
38851 /* If necessary, drop THIS back to its stack slot. */
38857 {
38860 ;
38861 else
38862 {
38866 }
38867 }
38868 else
38869 {
38871 ;
38872 #if TARGET_MACHO
38874 {
38877 }
38879 else
38880 {
38888 }
38889 }
38891 /* Our sibling call patterns do not allow memories, because we have no
38892 predicate that can distinguish between frame and non-frame memory.
38893 For our purposes here, we can get away with (ab)using a jump pattern,
38894 because we're going to do no optimization. */
38897 else
38898 {
38904 {
38910 }
38916 }
38919 /* Emit just enough of rest_of_compilation to get the insns emitted.
38920 Note that use_thunk calls assemble_start_function et al. */
38926 }
38928 static void
38930 {
38934 #if TARGET_MACHO
38936 #endif
38943 }
38945 int
38947 {
38959 }
38961 /* Output assembler code to FILE to increment profiler label # LABELNO
38962 for profiling a function entry. */
38963 void
38965 {
38970 {
38971 #ifndef NO_PROFILE_COUNTERS
38973 #endif
38977 else
38979 }
38981 {
38982 #ifndef NO_PROFILE_COUNTERS
38985 #endif
38987 }
38988 else
38989 {
38990 #ifndef NO_PROFILE_COUNTERS
38993 #endif
38995 }
38996 }
38998 /* We don't have exact information about the insn sizes, but we may assume
38999 quite safely that we are informed about all 1 byte insns and memory
39000 address sizes. This is enough to eliminate unnecessary padding in
39001 99% of cases. */
39003 static int
39005 {
39011 /* Discard alignments we've emit and jump instructions. */
39016 /* Important case - calls are always 5 bytes.
39017 It is common to have many calls in the row. */
39026 /* For normal instructions we rely on get_attr_length being exact,
39027 with a few exceptions. */
39029 {
39033 {
39043 /* Otherwise trust get_attr_length. */
39045 }
39050 }
39053 else
39055 }
39057 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39059 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39060 window. */
39062 static void
39064 {
39069 /* Look for all minimal intervals of instructions containing 4 jumps.
39070 The intervals are bounded by START and INSN. NBYTES is the total
39071 size of instructions in the interval including INSN and not including
39072 START. When the NBYTES is smaller than 16 bytes, it is possible
39073 that the end of START and INSN ends up in the same 16byte page.
39075 The smallest offset in the page INSN can start is the case where START
39076 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39077 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39079 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39080 have to, control transfer to label(s) can be performed through other
39081 means, and also we estimate minimum length of all asm stmts as 0. */
39083 {
39087 {
39093 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39094 already in the current 16 byte page, because otherwise
39095 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39096 bytes to reach 16 byte boundary. */
39104 {
39106 {
39111 else
39114 }
39115 }
39117 }
39126 njumps++;
39127 else
39131 {
39136 else
39139 }
39146 {
39153 }
39154 }
39155 }
39156 #endif
39158 /* AMD Athlon works faster
39159 when RET is not destination of conditional jump or directly preceded
39160 by other jump instruction. We avoid the penalty by inserting NOP just
39161 before the RET instructions in such cases. */
39162 static void
39164 {
39165 edge e;
39166 edge_iterator ei;
39169 {
39172 rtx prev;
39182 {
39183 edge e;
39184 edge_iterator ei;
39189 {
39192 }
39193 }
39195 {
39201 /* Empty functions get branch mispredict even when
39202 the jump destination is not visible to us. */
39205 }
39207 {
39210 }
39211 }
39212 }
39214 /* Count the minimum number of instructions in BB. Return 4 if the
39215 number of instructions >= 4. */
39217 static int
39219 {
39220 rtx insn;
39223 /* Count number of instructions in this block. Return 4 if the number
39224 of instructions >= 4. */
39226 {
39227 /* Only happen in exit blocks. */
39235 {
39236 insn_count++;
39239 }
39240 }
39243 }
39246 /* Count the minimum number of instructions in code path in BB.
39247 Return 4 if the number of instructions >= 4. */
39249 static int
39251 {
39252 edge e;
39253 edge_iterator ei;
39256 /* Only bother counting instructions along paths with no
39257 more than 2 basic blocks between entry and exit. Given
39258 that BB has an edge to exit, determine if a predecessor
39259 of BB has an edge from entry. If so, compute the number
39260 of instructions in the predecessor block. If there
39261 happen to be multiple such blocks, compute the minimum. */
39264 {
39265 edge prev_e;
39266 edge_iterator prev_ei;
39269 {
39272 }
39274 {
39276 {
39281 }
39282 }
39283 }
39289 }
39291 /* Pad short function to 4 instructions. */
39293 static void
39295 {
39296 edge e;
39297 edge_iterator ei;
39300 {
39303 {
39306 /* Pad short function. */
39308 {
39311 /* Find epilogue. */
39320 /* Two NOPs count as one instruction. */
39323 }
39324 }
39325 }
39326 }
39328 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39329 the epilogue, the Windows system unwinder will apply epilogue logic and
39330 produce incorrect offsets. This can be avoided by adding a nop between
39331 the last insn that can throw and the first insn of the epilogue. */
39333 static void
39335 {
39336 edge e;
39337 edge_iterator ei;
39340 {
39343 /* Find the beginning of the epilogue. */
39350 /* We only care about preceding insns that can throw. */
39355 /* Do not separate calls from their debug information. */
39361 else
39365 }
39366 }
39368 /* Implement machine specific optimizations. We implement padding of returns
39369 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39370 static void
39372 {
39373 /* We are freeing block_for_insn in the toplev to keep compatibility
39374 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39381 {
39386 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39389 #endif
39390 }
39391 }
39393 /* Return nonzero when QImode register that must be represented via REX prefix
39394 is used. */
39395 bool
39397 {
39405 }
39407 /* Return nonzero when P points to register encoded via REX prefix.
39408 Called via for_each_rtx. */
39409 static int
39411 {
39417 }
39419 /* Return true when INSN mentions register that must be encoded using REX
39420 prefix. */
39421 bool
39423 {
39426 }
39428 /* If profitable, negate (without causing overflow) integer constant
39429 of mode MODE at location LOC. Return true in this case. */
39430 bool
39432 {
39433 HOST_WIDE_INT val;
39439 {
39441 /* DImode x86_64 constants must fit in 32 bits. */
39454 }
39456 /* Avoid overflows. */
39462 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39463 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39466 {
39469 }
39472 }
39474 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39475 optabs would emit if we didn't have TFmode patterns. */
39477 void
39479 {
39513 }
39514 \f
39515 /* AVX512F does support 64-byte integer vector operations,
39516 thus the longest vector we are faced with is V64QImode. */
39517 #define MAX_VECT_LEN 64
39519 struct expand_vec_perm_d
39520 {
39527 };
39533 /* Get a vector mode of the same size as the original but with elements
39534 twice as wide. This is only guaranteed to apply to integral vectors. */
39538 {
39539 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39544 }
39546 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39547 fill target with val via vec_duplicate. */
39549 static bool
39551 {
39555 /* First attempt to recognize VAL as-is. */
39559 {
39560 rtx seq;
39561 /* If that fails, force VAL into a register. */
39572 }
39574 }
39576 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39577 with all elements equal to VAR. Return true if successful. */
39579 static bool
39582 {
39586 {
39591 /* FALLTHRU */
39611 {
39612 rtx x;
39619 }
39629 {
39633 permute:
39641 /* Extend to SImode using a paradoxical SUBREG. */
39645 /* Insert the SImode value as low element of a V4SImode vector. */
39654 }
39662 widen:
39663 /* Replicate the value once into the next wider mode and recurse. */
39664 {
39666 rtx x;
39683 }
39687 {
39696 }
39701 }
39702 }
39704 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39705 whose ONE_VAR element is VAR, and other elements are zero. Return true
39706 if successful. */
39708 static bool
39711 {
39713 rtx new_target;
39718 {
39720 /* For SSE4.1, we normally use vector set. But if the second
39721 element is zero and inter-unit moves are OK, we use movq
39722 instead. */
39724 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
39746 /* Use ix86_expand_vector_set in 64bit mode only. */
39751 }
39754 {
39759 }
39762 {
39767 /* FALLTHRU */
39782 else
39789 {
39790 /* We need to shuffle the value to the correct position, so
39791 create a new pseudo to store the intermediate result. */
39793 /* With SSE2, we can use the integer shuffle insns. */
39795 {
39797 const1_rtx,
39804 }
39806 /* Otherwise convert the intermediate result to V4SFmode and
39807 use the SSE1 shuffle instructions. */
39809 {
39812 }
39813 else
39817 const1_rtx,
39826 }
39841 widen:
39845 /* Zero extend the variable element to SImode and recurse. */
39858 }
39859 }
39861 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39862 consisting of the values in VALS. It is known that all elements
39863 except ONE_VAR are constants. Return true if successful. */
39865 static bool
39868 {
39878 {
39883 /* For the two element vectors, it's just as easy to use
39884 the general case. */
39888 /* Use ix86_expand_vector_set in 64bit mode only. */
39910 widen:
39911 /* There's no way to set one QImode entry easily. Combine
39912 the variable value with its adjacent constant value, and
39913 promote to an HImode set. */
39916 {
39921 }
39922 else
39923 {
39926 }
39940 }
39945 }
39947 /* A subroutine of ix86_expand_vector_init_general. Use vector
39948 concatenate to handle the most general case: all values variable,
39949 and none identical. */
39951 static void
39954 {
39957 rtvec v;
39961 {
39964 {
40009 }
40022 {
40037 }
40042 {
40061 }
40066 {
40079 }
40082 half:
40083 /* FIXME: We process inputs backward to help RA. PR 36222. */
40087 {
40092 }
40096 {
40100 {
40104 }
40107 {
40111 }
40114 }
40116 {
40119 {
40123 }
40126 }
40127 else
40133 }
40134 }
40136 /* A subroutine of ix86_expand_vector_init_general. Use vector
40137 interleave to handle the most general case: all values variable,
40138 and none identical. */
40140 static void
40143 {
40152 {
40173 }
40176 {
40177 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40181 /* Insert the SImode value as low element of V4SImode vector. */
40185 op0),
40187 const1_rtx);
40190 /* Cast the V4SImode vector back to a vector in orignal mode. */
40194 /* Load even elements into the second position. */
40198 const1_rtx));
40200 /* Cast vector to FIRST_IMODE vector. */
40203 }
40205 /* Interleave low FIRST_IMODE vectors. */
40207 {
40211 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40214 }
40216 /* Interleave low SECOND_IMODE vectors. */
40218 {
40221 {
40226 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40227 vector. */
40230 }
40233 /* FALLTHRU */
40240 /* Cast the SECOND_IMODE vector back to a vector on original
40241 mode. */
40248 }
40249 }
40251 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40252 all values variable, and none identical. */
40254 static void
40257 {
40263 {
40268 /* FALLTHRU */
40296 half:
40313 /* FALLTHRU */
40319 /* Don't use ix86_expand_vector_init_interleave if we can't
40320 move from GPR to SSE register directly. */
40336 }
40338 {
40350 {
40354 {
40360 else
40361 {
40366 }
40367 }
40370 }
40375 {
40381 }
40383 {
40389 }
40390 else
40392 }
40393 }
40395 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40396 instructions unless MMX_OK is true. */
40398 void
40400 {
40407 rtx x;
40410 {
40420 }
40422 /* Constants are best loaded from the constant pool. */
40424 {
40427 }
40429 /* If all values are identical, broadcast the value. */
40435 /* Values where only one field is non-constant are best loaded from
40436 the pool and overwritten via move later. */
40438 {
40442 one_var))
40447 }
40450 }
40452 void
40454 {
40459 rtx tmp;
40461 = {
40468 };
40470 = {
40477 };
40481 {
40485 {
40490 else
40494 }
40506 else
40512 {
40515 /* For the two element vectors, we implement a VEC_CONCAT with
40516 the extraction of the other element. */
40523 else
40528 }
40537 {
40543 /* tmp = target = A B C D */
40545 /* target = A A B B */
40547 /* target = X A B B */
40549 /* target = A X C D */
40556 /* tmp = target = A B C D */
40558 /* tmp = X B C D */
40560 /* target = A B X D */
40567 /* tmp = target = A B C D */
40569 /* tmp = X B C D */
40571 /* target = A B X D */
40579 }
40587 /* Element 0 handled by vec_merge below. */
40589 {
40592 }
40595 {
40596 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40597 store into element 0, then shuffle them back. */
40614 }
40615 else
40616 {
40617 /* For SSE1, we have to reuse the V4SF code. */
40621 }
40674 half:
40675 /* Compute offset. */
40681 /* Extract the half. */
40685 /* Put val in tmp at elt. */
40688 /* Put it back. */
40694 }
40697 {
40701 }
40702 else
40703 {
40712 }
40713 }
40715 void
40717 {
40721 rtx tmp;
40724 {
40729 /* FALLTHRU */
40742 {
40762 }
40774 {
40776 {
40796 }
40800 }
40801 else
40802 {
40803 /* For SSE1, we have to reuse the V4SF code. */
40807 }
40823 {
40827 else
40831 }
40836 {
40840 else
40844 }
40849 {
40853 else
40857 }
40862 {
40866 else
40870 }
40875 {
40879 else
40883 }
40888 {
40892 else
40896 }
40903 else
40912 else
40921 else
40930 else
40936 /* ??? Could extract the appropriate HImode element and shift. */
40939 }
40942 {
40946 /* Let the rtl optimizers know about the zero extension performed. */
40948 {
40951 }
40954 }
40955 else
40956 {
40963 }
40964 }
40966 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
40967 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
40968 The upper bits of DEST are undefined, though they shouldn't cause
40969 exceptions (some bits from src or all zeros are ok). */
40971 static void
40973 {
40976 {
40980 else
40998 else
41005 else
41013 {
41018 const1_rtx);
41019 }
41020 else
41021 {
41025 }
41045 else
41067 }
41071 }
41073 /* Expand a vector reduction. FN is the binary pattern to reduce;
41074 DEST is the destination; IN is the input vector. */
41076 void
41078 {
41083 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41087 {
41090 }
41095 {
41100 else
41104 }
41105 }
41106 \f
41107 /* Target hook for scalar_mode_supported_p. */
41108 static bool
41110 {
41115 else
41117 }
41119 /* Implements target hook vector_mode_supported_p. */
41120 static bool
41122 {
41136 }
41138 /* Target hook for c_mode_for_suffix. */
41139 static enum machine_mode
41141 {
41148 }
41150 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41152 We do this in the new i386 backend to maintain source compatibility
41153 with the old cc0-based compiler. */
41155 static tree
41157 tree inputs ATTRIBUTE_UNUSED,
41158 tree clobbers)
41159 {
41161 clobbers);
41163 clobbers);
41165 }
41167 /* Implements target vector targetm.asm.encode_section_info. */
41169 static void ATTRIBUTE_UNUSED
41171 {
41178 }
41180 /* Worker function for REVERSE_CONDITION. */
41182 enum rtx_code
41184 {
41188 }
41190 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41191 to OPERANDS[0]. */
41195 {
41197 {
41200 {
41204 }
41208 }
41210 {
41214 else
41215 {
41216 /* There is no non-popping store to memory for XFmode.
41217 So if we need one, follow the store with a load. */
41220 else
41222 }
41223 }
41224 else
41226 }
41228 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41229 FP status register is set. */
41231 void
41233 {
41235 rtx temp;
41240 {
41245 }
41246 else
41247 {
41252 }
41256 pc_rtx);
41261 }
41263 /* Output code to perform a log1p XFmode calculation. */
41266 {
41272 rtx test;
41278 XFmode));
41292 }
41294 /* Emit code for round calculation. */
41296 {
41303 rtx insn;
41308 {
41320 }
41323 {
41344 }
41352 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41354 /* scratch = fxam(op1) */
41357 UNSPEC_FXAM)));
41358 /* e1 = fabs(op1) */
41361 /* e2 = e1 + 0.5 */
41366 /* res = floor(e2) */
41368 {
41373 }
41374 else
41378 {
41381 {
41388 UNSPEC_TRUNC_NOOP)));
41389 }
41405 }
41407 /* flags = signbit(a) */
41410 /* if (flags) then res = -res */
41414 pc_rtx);
41425 }
41427 /* Output code to perform a Newton-Rhapson approximation of a single precision
41428 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41431 {
41439 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41443 /* x0 = rcp(b) estimate */
41447 UNSPEC_RCP14)));
41448 else
41451 UNSPEC_RCP)));
41453 /* e0 = x0 * b */
41457 /* e0 = x0 * e0 */
41461 /* e1 = x0 + x0 */
41465 /* x1 = e1 - e0 */
41469 /* res = a * x1 */
41472 }
41474 /* Output code to perform a Newton-Rhapson approximation of a
41475 single precision floating point [reciprocal] square root. */
41479 {
41481 REAL_VALUE_TYPE r;
41498 {
41501 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41504 }
41506 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41507 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41511 /* x0 = rsqrt(a) estimate */
41514 unspec)));
41516 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41518 {
41526 /* Handle masked compare. */
41528 {
41530 /* Imm value 0x4 corresponds to not-equal comparison. */
41533 }
41534 else
41535 {
41541 }
41542 }
41544 /* e0 = x0 * a */
41547 /* e1 = e0 * x0 */
41551 /* e2 = e1 - 3. */
41558 /* e3 = -.5 * x0 */
41561 else
41562 /* e3 = -.5 * e0 */
41565 /* ret = e2 * e3 */
41568 }
41570 #ifdef TARGET_SOLARIS
41571 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41573 static void
41575 tree decl)
41576 {
41577 /* With Binutils 2.15, the "@unwind" marker must be specified on
41578 every occurrence of the ".eh_frame" section, not just the first
41579 one. */
41582 {
41586 }
41588 #ifndef USE_GAS
41590 {
41593 }
41594 #endif
41597 }
41600 /* Return the mangling of TYPE if it is an extended fundamental type. */
41604 {
41612 {
41614 /* __float128 is "g". */
41617 /* "long double" or __float80 is "e". */
41621 }
41622 }
41624 /* For 32-bit code we can save PIC register setup by using
41625 __stack_chk_fail_local hidden function instead of calling
41626 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41627 register, so it is better to call __stack_chk_fail directly. */
41629 static tree ATTRIBUTE_UNUSED
41631 {
41632 return TARGET_64BIT
41635 }
41637 /* Select a format to encode pointers in exception handling data. CODE
41638 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41639 true if the symbol may be affected by dynamic relocations.
41641 ??? All x86 object file formats are capable of representing this.
41642 After all, the relocation needed is the same as for the call insn.
41643 Whether or not a particular assembler allows us to enter such, I
41644 guess we'll have to see. */
41645 int
41647 {
41649 {
41656 }
41661 }
41662 \f
41663 /* Expand copysign from SIGN to the positive value ABS_VALUE
41664 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41665 the sign-bit. */
41666 static void
41668 {
41672 {
41679 else
41684 {
41685 /* We need to generate a scalar mode mask in this case. */
41690 }
41691 }
41692 else
41698 }
41700 /* Expand fabs (OP0) and return a new rtx that holds the result. The
41701 mask for masking out the sign-bit is stored in *SMASK, if that is
41702 non-null. */
41703 static rtx
41705 {
41714 else
41718 {
41719 /* We need to generate a scalar mode mask in this case. */
41724 }
41732 }
41734 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
41735 swapping the operands if SWAP_OPERANDS is true. The expanded
41736 code is a forward jump to a newly created label in case the
41737 comparison is true. The generated label rtx is returned. */
41738 static rtx
41741 {
41746 {
41750 }
41763 }
41765 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
41766 using comparison code CODE. Operands are swapped for the comparison if
41767 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
41768 static rtx
41771 {
41777 {
41781 }
41788 }
41790 /* Generate and return a rtx of mode MODE for 2**n where n is the number
41791 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
41792 static rtx
41794 {
41795 REAL_VALUE_TYPE TWO52r;
41796 rtx TWO52;
41803 }
41805 /* Expand SSE sequence for computing lround from OP1 storing
41806 into OP0. */
41807 void
41809 {
41810 /* C code for the stuff we're doing below:
41811 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
41812 return (long)tmp;
41813 */
41817 rtx adj;
41819 /* load nextafter (0.5, 0.0) */
41824 /* adj = copysign (0.5, op1) */
41828 /* adj = op1 + adj */
41831 /* op0 = (imode)adj */
41833 }
41835 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
41836 into OPERAND0. */
41837 void
41839 {
41840 /* C code for the stuff we're doing below (for do_floor):
41841 xi = (long)op1;
41842 xi -= (double)xi > op1 ? 1 : 0;
41843 return xi;
41844 */
41849 /* reg = (long)op1 */
41853 /* freg = (double)reg */
41857 /* ireg = (freg > op1) ? ireg - 1 : ireg */
41868 }
41870 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
41871 result in OPERAND0. */
41872 void
41874 {
41875 /* C code for the stuff we're doing below:
41876 xa = fabs (operand1);
41877 if (!isless (xa, 2**52))
41878 return operand1;
41879 xa = xa + 2**52 - 2**52;
41880 return copysign (xa, operand1);
41881 */
41888 /* xa = abs (operand1) */
41891 /* if (!isless (xa, TWO52)) goto label; */
41904 }
41906 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41907 into OPERAND0. */
41908 void
41910 {
41911 /* C code for the stuff we expand below.
41912 double xa = fabs (x), x2;
41913 if (!isless (xa, TWO52))
41914 return x;
41915 xa = xa + TWO52 - TWO52;
41916 x2 = copysign (xa, x);
41917 Compensate. Floor:
41918 if (x2 > x)
41919 x2 -= 1;
41920 Compensate. Ceil:
41921 if (x2 < x)
41922 x2 -= -1;
41923 return x2;
41924 */
41930 /* Temporary for holding the result, initialized to the input
41931 operand to ease control flow. */
41935 /* xa = abs (operand1) */
41938 /* if (!isless (xa, TWO52)) goto label; */
41941 /* xa = xa + TWO52 - TWO52; */
41945 /* xa = copysign (xa, operand1) */
41948 /* generate 1.0 or -1.0 */
41953 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
41957 /* We always need to subtract here to preserve signed zero. */
41966 }
41968 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41969 into OPERAND0. */
41970 void
41972 {
41973 /* C code for the stuff we expand below.
41974 double xa = fabs (x), x2;
41975 if (!isless (xa, TWO52))
41976 return x;
41977 x2 = (double)(long)x;
41978 Compensate. Floor:
41979 if (x2 > x)
41980 x2 -= 1;
41981 Compensate. Ceil:
41982 if (x2 < x)
41983 x2 += 1;
41984 if (HONOR_SIGNED_ZEROS (mode))
41985 return copysign (x2, x);
41986 return x2;
41987 */
41993 /* Temporary for holding the result, initialized to the input
41994 operand to ease control flow. */
41998 /* xa = abs (operand1) */
42001 /* if (!isless (xa, TWO52)) goto label; */
42004 /* xa = (double)(long)x */
42009 /* generate 1.0 */
42012 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42027 }
42029 /* Expand SSE sequence for computing round from OPERAND1 storing
42030 into OPERAND0. Sequence that works without relying on DImode truncation
42031 via cvttsd2siq that is only available on 64bit targets. */
42032 void
42034 {
42035 /* C code for the stuff we expand below.
42036 double xa = fabs (x), xa2, x2;
42037 if (!isless (xa, TWO52))
42038 return x;
42039 Using the absolute value and copying back sign makes
42040 -0.0 -> -0.0 correct.
42041 xa2 = xa + TWO52 - TWO52;
42042 Compensate.
42043 dxa = xa2 - xa;
42044 if (dxa <= -0.5)
42045 xa2 += 1;
42046 else if (dxa > 0.5)
42047 xa2 -= 1;
42048 x2 = copysign (xa2, x);
42049 return x2;
42050 */
42056 /* Temporary for holding the result, initialized to the input
42057 operand to ease control flow. */
42061 /* xa = abs (operand1) */
42064 /* if (!isless (xa, TWO52)) goto label; */
42067 /* xa2 = xa + TWO52 - TWO52; */
42071 /* dxa = xa2 - xa; */
42074 /* generate 0.5, 1.0 and -0.5 */
42080 /* Compensate. */
42082 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42087 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42093 /* res = copysign (xa2, operand1) */
42100 }
42102 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42103 into OPERAND0. */
42104 void
42106 {
42107 /* C code for SSE variant we expand below.
42108 double xa = fabs (x), x2;
42109 if (!isless (xa, TWO52))
42110 return x;
42111 x2 = (double)(long)x;
42112 if (HONOR_SIGNED_ZEROS (mode))
42113 return copysign (x2, x);
42114 return x2;
42115 */
42121 /* Temporary for holding the result, initialized to the input
42122 operand to ease control flow. */
42126 /* xa = abs (operand1) */
42129 /* if (!isless (xa, TWO52)) goto label; */
42132 /* x = (double)(long)x */
42144 }
42146 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42147 into OPERAND0. */
42148 void
42150 {
42154 /* C code for SSE variant we expand below.
42155 double xa = fabs (x), x2;
42156 if (!isless (xa, TWO52))
42157 return x;
42158 xa2 = xa + TWO52 - TWO52;
42159 Compensate:
42160 if (xa2 > xa)
42161 xa2 -= 1.0;
42162 x2 = copysign (xa2, x);
42163 return x2;
42164 */
42168 /* Temporary for holding the result, initialized to the input
42169 operand to ease control flow. */
42173 /* xa = abs (operand1) */
42176 /* if (!isless (xa, TWO52)) goto label; */
42179 /* res = xa + TWO52 - TWO52; */
42184 /* generate 1.0 */
42187 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42195 /* res = copysign (res, operand1) */
42202 }
42204 /* Expand SSE sequence for computing round from OPERAND1 storing
42205 into OPERAND0. */
42206 void
42208 {
42209 /* C code for the stuff we're doing below:
42210 double xa = fabs (x);
42211 if (!isless (xa, TWO52))
42212 return x;
42213 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42214 return copysign (xa, x);
42215 */
42221 /* Temporary for holding the result, initialized to the input
42222 operand to ease control flow. */
42230 /* load nextafter (0.5, 0.0) */
42235 /* xa = xa + 0.5 */
42239 /* xa = (double)(int64_t)xa */
42244 /* res = copysign (xa, operand1) */
42251 }
42253 /* Expand SSE sequence for computing round
42254 from OP1 storing into OP0 using sse4 round insn. */
42255 void
42257 {
42266 {
42277 }
42279 /* round (a) = trunc (a + copysign (0.5, a)) */
42281 /* load nextafter (0.5, 0.0) */
42287 /* e1 = copysign (0.5, op1) */
42291 /* e2 = op1 + e1 */
42294 /* res = trunc (e2) */
42299 }
42300 \f
42302 /* Table of valid machine attributes. */
42304 {
42305 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42306 affects_type_identity } */
42307 /* Stdcall attribute says callee is responsible for popping arguments
42308 if they are not variable. */
42311 /* Fastcall attribute says callee is responsible for popping arguments
42312 if they are not variable. */
42315 /* Thiscall attribute says callee is responsible for popping arguments
42316 if they are not variable. */
42319 /* Cdecl attribute says the callee is a normal C declaration */
42322 /* Regparm attribute specifies how many integer arguments are to be
42323 passed in registers. */
42326 /* Sseregparm attribute says we are using x86_64 calling conventions
42327 for FP arguments. */
42330 /* The transactional memory builtins are implicitly regparm or fastcall
42331 depending on the ABI. Override the generic do-nothing attribute that
42332 these builtins were declared with. */
42335 /* force_align_arg_pointer says this function realigns the stack at entry. */
42338 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42343 #endif
42348 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42349 SUBTARGET_ATTRIBUTE_TABLE,
42350 #endif
42351 /* ms_abi and sysv_abi calling convention function attributes. */
42358 /* End element. */
42360 };
42362 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42363 static int
42365 tree vectype,
42367 {
42371 {
42416 }
42417 }
42419 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42420 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42421 insn every time. */
42425 /* Initialize vselect_insn. */
42427 static void
42429 {
42431 rtx x;
42442 }
42444 /* Construct (set target (vec_select op0 (parallel perm))) and
42445 return true if that's a valid instruction in the active ISA. */
42447 static bool
42450 {
42476 }
42478 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42480 static bool
42484 {
42486 rtx x;
42501 }
42503 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42504 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42506 static bool
42508 {
42517 ;
42519 ;
42521 ;
42522 else
42525 /* This is a blend, not a permute. Elements must stay in their
42526 respective lanes. */
42528 {
42532 }
42537 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42538 decision should be extracted elsewhere, so that we only try that
42539 sequence once all budget==3 options have been tried. */
42546 {
42570 /* See if bytes move in pairs so we can use pblendw with
42571 an immediate argument, rather than pblendvb with a vector
42572 argument. */
42575 {
42576 use_pblendvb:
42580 finish_pblendvb:
42586 else
42591 }
42596 /* FALLTHRU */
42598 do_subreg:
42605 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42609 /* See if bytes move in quadruplets. If yes, vpblendd
42610 with immediate can be used. */
42615 {
42616 /* See if bytes move the same in both lanes. If yes,
42617 vpblendw with immediate can be used. */
42622 /* Use vpblendw. */
42627 }
42629 /* Use vpblendd. */
42636 /* See if words move in pairs. If yes, vpblendd can be used. */
42641 {
42642 /* See if words move the same in both lanes. If not,
42643 vpblendvb must be used. */
42646 {
42647 /* Use vpblendvb. */
42657 }
42659 /* Use vpblendw. */
42663 }
42665 /* Use vpblendd. */
42672 /* Use vpblendd. */
42680 }
42682 /* This matches five different patterns with the different modes. */
42690 }
42692 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42693 in terms of the variable form of vpermilps.
42695 Note that we will have already failed the immediate input vpermilps,
42696 which requires that the high and low part shuffle be identical; the
42697 variable form doesn't require that. */
42699 static bool
42701 {
42708 /* We can only permute within the 128-bit lane. */
42710 {
42714 }
42720 {
42723 /* Within each 128-bit lane, the elements of op0 are numbered
42724 from 0 and the elements of op1 are numbered from 4. */
42731 }
42738 }
42740 /* Return true if permutation D can be performed as VMODE permutation
42741 instead. */
42743 static bool
42745 {
42760 else
42766 }
42768 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42769 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
42771 static bool
42773 {
42782 {
42784 {
42787 {
42791 /* Use vperm2i128 insn. The pattern uses
42792 V4DImode instead of V2TImode. */
42805 }
42807 }
42808 }
42809 else
42810 {
42812 {
42815 }
42817 {
42821 /* V4DImode should be already handled through
42822 expand_vselect by vpermq instruction. */
42829 {
42830 /* First see if vpermq can be used for
42831 V8SImode/V16HImode/V32QImode. */
42833 {
42841 {
42845 }
42847 }
42849 /* Next see if vpermd can be used. */
42852 }
42853 /* Or if vpermps can be used. */
42858 {
42859 /* vpshufb only works intra lanes, it is not
42860 possible to shuffle bytes in between the lanes. */
42864 }
42865 }
42866 else
42868 }
42876 else
42877 {
42883 else
42887 {
42891 }
42892 }
42903 {
42910 else
42912 }
42913 else
42914 {
42917 }
42922 }
42924 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
42925 in a single instruction. */
42927 static bool
42929 {
42933 /* Check plain VEC_SELECT first, because AVX has instructions that could
42934 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
42935 input where SEL+CONCAT may not. */
42937 {
42943 {
42949 }
42952 {
42956 }
42958 {
42959 /* Use vpbroadcast{b,w,d}. */
42962 {
42981 /* For other modes prefer other shuffles this function creates. */
42983 }
42985 {
42989 }
42990 }
42995 /* There are plenty of patterns in sse.md that are written for
42996 SEL+CONCAT and are not replicated for a single op. Perhaps
42997 that should be changed, to avoid the nastiness here. */
42999 /* Recognize interleave style patterns, which means incrementing
43000 every other permutation operand. */
43002 {
43005 }
43010 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
43012 {
43014 {
43019 }
43024 }
43025 }
43027 /* Finally, try the fully general two operand permute. */
43032 /* Recognize interleave style patterns with reversed operands. */
43034 {
43036 {
43040 else
43043 }
43048 }
43050 /* Try the SSE4.1 blend variable merge instructions. */
43054 /* Try one of the AVX vpermil variable permutations. */
43058 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43059 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43063 /* Try the AVX512F vpermi2 instructions. */
43077 }
43079 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43080 in terms of a pair of pshuflw + pshufhw instructions. */
43082 static bool
43084 {
43092 /* The two permutations only operate in 64-bit lanes. */
43103 /* Emit the pshuflw. */
43110 /* Emit the pshufhw. */
43118 }
43120 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43121 the permutation using the SSSE3 palignr instruction. This succeeds
43122 when all of the elements in PERM fit within one vector and we merely
43123 need to shift them down so that a single vector permutation has a
43124 chance to succeed. */
43126 static bool
43128 {
43135 /* Even with AVX, palignr only operates on 128-bit vectors. */
43141 {
43147 }
43151 /* Given that we have SSSE3, we know we'll be able to implement the
43152 single operand permutation after the palignr with pshufb. */
43167 {
43172 }
43174 /* Test for the degenerate case where the alignment by itself
43175 produces the desired permutation. */
43177 {
43180 }
43186 }
43190 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43191 a two vector permutation into a single vector permutation by using
43192 an interleave operation to merge the vectors. */
43194 static bool
43196 {
43201 rtx seq;
43205 {
43208 }
43210 {
43213 /* For 32-byte modes allow even d->one_operand_p.
43214 The lack of cross-lane shuffling in some instructions
43215 might prevent a single insn shuffle. */
43218 /* If expand_vec_perm_interleave3 can expand this into
43219 a 3 insn sequence, give up and let it be expanded as
43220 3 insn sequence. While that is one insn longer,
43221 it doesn't need a memory operand and in the common
43222 case that both interleave low and high permutations
43223 with the same operands are adjacent needs 4 insns
43224 for both after CSE. */
43227 }
43228 else
43231 /* Examine from whence the elements come. */
43240 {
43243 /* Split the two input vectors into 4 halves. */
43249 /* If the elements from the low halves use interleave low, and similarly
43250 for interleave high. If the elements are from mis-matched halves, we
43251 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43253 {
43254 /* punpckl* */
43256 {
43261 }
43264 }
43266 {
43267 /* punpckh* */
43269 {
43274 }
43277 }
43279 {
43280 /* shufps */
43282 {
43287 }
43289 {
43290 /* shufpd */
43295 }
43296 }
43298 {
43299 /* shufps */
43301 {
43306 }
43308 {
43309 /* shufpd */
43314 }
43315 }
43316 else
43318 }
43319 else
43320 {
43325 /* Split the two input vectors into 8 quarters. */
43331 {
43334 }
43337 {
43341 }
43343 {
43346 }
43349 {
43351 {
43352 /* Attempt to increase the likelihood that dfinal
43353 shuffle will be intra-lane. */
43357 }
43359 /* vperm2f128 or vperm2i128. */
43361 {
43366 }
43371 {
43375 {
43378 }
43379 }
43380 }
43385 {
43386 /* vpunpckl* */
43388 {
43397 }
43398 }
43401 {
43402 /* vpunpckh* */
43404 {
43413 }
43414 }
43415 else
43417 }
43419 /* Use the remapping array set up above to move the elements from their
43420 swizzled locations into their final destinations. */
43423 {
43426 /* If same_halves is true, both halves of the remapped vector are the
43427 same. Avoid cross-lane accesses if possible. */
43429 {
43432 }
43433 else
43435 }
43437 {
43440 }
43444 /* Test if the final remap can be done with a single insn. For V4SFmode or
43445 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43458 {
43461 }
43468 }
43470 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43471 a single vector cross-lane permutation into vpermq followed
43472 by any of the single insn permutations. */
43474 static bool
43476 {
43490 {
43493 }
43496 {
43501 }
43514 {
43521 }
43528 {
43533 ;
43536 else
43538 }
43547 }
43549 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43550 a vector permutation using two instructions, vperm2f128 resp.
43551 vperm2i128 followed by any single in-lane permutation. */
43553 static bool
43555 {
43569 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43570 immediate. For perm < 16 the second permutation uses
43571 d->op0 as first operand, for perm >= 16 it uses d->op1
43572 as first operand. The second operand is the result of
43573 vperm2[fi]128. */
43575 {
43576 /* Ignore permutations which do not move anything cross-lane. */
43578 {
43579 /* The second shuffle for e.g. V4DFmode has
43580 0123 and ABCD operands.
43581 Ignore AB23, as 23 is already in the second lane
43582 of the first operand. */
43584 /* And 01CD, as 01 is in the first lane of the first
43585 operand. */
43587 /* And 4567, as then the vperm2[fi]128 doesn't change
43588 anything on the original 4567 second operand. */
43590 }
43591 else
43592 {
43593 /* The second shuffle for e.g. V4DFmode has
43594 4567 and ABCD operands.
43595 Ignore AB67, as 67 is already in the second lane
43596 of the first operand. */
43598 /* And 45CD, as 45 is in the first lane of the first
43599 operand. */
43601 /* And 0123, as then the vperm2[fi]128 doesn't change
43602 anything on the original 0123 first operand. */
43604 }
43607 {
43613 else
43615 }
43618 {
43622 }
43623 else
43627 {
43631 /* Found a usable second shuffle. dfirst will be
43632 vperm2f128 on d->op0 and d->op1. */
43643 /* And dsecond is some single insn shuffle, taking
43644 d->op0 and result of vperm2f128 (if perm < 16) or
43645 d->op1 and result of vperm2f128 (otherwise). */
43654 }
43656 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43659 }
43662 }
43664 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43665 a two vector permutation using 2 intra-lane interleave insns
43666 and cross-lane shuffle for 32-byte vectors. */
43668 static bool
43670 {
43677 ;
43679 ;
43680 else
43695 {
43699 else
43705 else
43711 else
43717 else
43723 else
43729 else
43734 }
43738 }
43740 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
43741 a single vector permutation using a single intra-lane vector
43742 permutation, vperm2f128 swapping the lanes and vblend* insn blending
43743 the non-swapped and swapped vectors together. */
43745 static bool
43747 {
43750 rtx seq;
43755 || TARGET_AVX2
43764 {
43771 }
43806 }
43808 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
43809 permutation using two vperm2f128, followed by a vshufpd insn blending
43810 the two vectors together. */
43812 static bool
43814 {
43857 }
43859 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
43860 permutation with two pshufb insns and an ior. We should have already
43861 failed all two instruction sequences. */
43863 static bool
43865 {
43879 /* Generate two permutation masks. If the required element is within
43880 the given vector it is shuffled into the proper lane. If the required
43881 element is in the other vector, force a zero into the lane by setting
43882 bit 7 in the permutation mask. */
43885 {
43892 {
43895 }
43896 }
43920 }
43922 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
43923 with two vpshufb insns, vpermq and vpor. We should have already failed
43924 all two or three instruction sequences. */
43926 static bool
43928 {
43943 /* Generate two permutation masks. If the required element is within
43944 the same lane, it is shuffled in. If the required element from the
43945 other lane, force a zero by setting bit 7 in the permutation mask.
43946 In the other mask the mask has non-negative elements if element
43947 is requested from the other lane, but also moved to the other lane,
43948 so that the result of vpshufb can have the two V2TImode halves
43949 swapped. */
43952 {
43957 {
43960 }
43961 }
43970 /* Swap the 128-byte lanes of h into hp. */
43974 const1_rtx));
43991 }
43993 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
43994 and extract-odd permutations of two V32QImode and V16QImode operand
43995 with two vpshufb insns, vpor and vpermq. We should have already
43996 failed all two or three instruction sequences. */
43998 static bool
44000 {
44019 /* Generate two permutation masks. In the first permutation mask
44020 the first quarter will contain indexes for the first half
44021 of the op0, the second quarter will contain bit 7 set, third quarter
44022 will contain indexes for the second half of the op0 and the
44023 last quarter bit 7 set. In the second permutation mask
44024 the first quarter will contain bit 7 set, the second quarter
44025 indexes for the first half of the op1, the third quarter bit 7 set
44026 and last quarter indexes for the second half of the op1.
44027 I.e. the first mask e.g. for V32QImode extract even will be:
44028 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44029 (all values masked with 0xf except for -128) and second mask
44030 for extract even will be
44031 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44034 {
44040 {
44043 }
44044 }
44063 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44071 }
44073 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44074 and extract-odd permutations. */
44076 static bool
44078 {
44082 {
44089 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44093 /* Now an unpck[lh]pd will produce the result required. */
44096 else
44102 {
44111 /* Shuffle within the 128-bit lanes to produce:
44112 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44116 /* Shuffle the lanes around to produce:
44117 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44121 /* Shuffle within the 128-bit lanes to produce:
44122 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44125 /* Shuffle within the 128-bit lanes to produce:
44126 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44129 /* Shuffle the lanes around to produce:
44130 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44133 }
44140 /* These are always directly implementable by expand_vec_perm_1. */
44146 else
44147 {
44150 /* We need 2*log2(N)-1 operations to achieve odd/even
44151 with interleave. */
44160 else
44163 }
44169 else
44170 {
44184 else
44187 }
44196 {
44201 else
44206 {
44211 }
44213 }
44221 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44225 /* Now an vpunpck[lh]qdq will produce the result required. */
44228 else
44235 {
44240 else
44245 {
44250 }
44252 }
44263 /* Shuffle the lanes around into
44264 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44272 /* Swap the 2nd and 3rd position in each lane into
44273 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44279 /* Now an vpunpck[lh]qdq will produce
44280 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44284 else
44293 }
44296 }
44298 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44299 extract-even and extract-odd permutations. */
44301 static bool
44303 {
44315 }
44317 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44318 permutations. We assume that expand_vec_perm_1 has already failed. */
44320 static bool
44322 {
44330 {
44333 /* These are special-cased in sse.md so that we can optionally
44334 use the vbroadcast instruction. They expand to two insns
44335 if the input happens to be in a register. */
44342 /* These are always implementable using standard shuffle patterns. */
44347 /* These can be implemented via interleave. We save one insn by
44348 stopping once we have promoted to V4SImode and then use pshufd. */
44351 do
44352 {
44353 rtx dest;
44359 {
44363 }
44370 }
44385 /* For AVX2 broadcasts of the first element vpbroadcast* or
44386 vpermq should be used by expand_vec_perm_1. */
44392 }
44393 }
44395 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44396 broadcast permutations. */
44398 static bool
44400 {
44412 }
44414 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44415 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44416 all the shorter instruction sequences. */
44418 static bool
44420 {
44436 /* Generate 4 permutation masks. If the required element is within
44437 the same lane, it is shuffled in. If the required element from the
44438 other lane, force a zero by setting bit 7 in the permutation mask.
44439 In the other mask the mask has non-negative elements if element
44440 is requested from the other lane, but also moved to the other lane,
44441 so that the result of vpshufb can have the two V2TImode halves
44442 swapped. */
44445 {
44450 }
44456 {
44464 }
44467 {
44469 {
44472 }
44479 }
44481 /* Swap the 128-byte lanes of h[X]. */
44483 {
44489 const1_rtx));
44491 }
44494 {
44496 {
44499 }
44505 }
44508 {
44510 {
44514 }
44517 }
44527 }
44529 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44530 With all of the interface bits taken care of, perform the expansion
44531 in D and return true on success. */
44533 static bool
44535 {
44536 /* Try a single instruction expansion. */
44540 /* Try sequences of two instructions. */
44560 /* Try sequences of three instructions. */
44574 /* Try sequences of four instructions. */
44582 /* ??? Look for narrow permutations whose element orderings would
44583 allow the promotion to a wider mode. */
44585 /* ??? Look for sequences of interleave or a wider permute that place
44586 the data into the correct lanes for a half-vector shuffle like
44587 pshuf[lh]w or vpermilps. */
44589 /* ??? Look for sequences of interleave that produce the desired results.
44590 The combinatorics of punpck[lh] get pretty ugly... */
44595 /* Even longer sequences. */
44600 }
44602 /* If a permutation only uses one operand, make it clear. Returns true
44603 if the permutation references both operands. */
44605 static bool
44607 {
44615 {
44621 {
44624 }
44625 /* The elements of PERM do not suggest that only the first operand
44626 is used, but both operands are identical. Allow easier matching
44627 of the permutation by folding the permutation into the single
44628 input vector. */
44629 /* FALLTHRU */
44640 }
44643 }
44645 bool
44647 {
44652 rtx sel;
44669 {
44674 }
44681 /* If the selector says both arguments are needed, but the operands are the
44682 same, the above tried to expand with one_operand_p and flattened selector.
44683 If that didn't work, retry without one_operand_p; we succeeded with that
44684 during testing. */
44686 {
44690 }
44693 }
44695 /* Implement targetm.vectorize.vec_perm_const_ok. */
44697 static bool
44700 {
44709 /* Given sufficient ISA support we can just return true here
44710 for selected vector modes. */
44713 /* All implementable with a single vpermi2 insn. */
44716 {
44717 /* All implementable with a single vpperm insn. */
44720 /* All implementable with 2 pshufb + 1 ior. */
44723 /* All implementable with shufpd or unpck[lh]pd. */
44726 }
44728 /* Extract the values from the vector CST into the permutation
44729 array in D. */
44732 {
44736 }
44738 /* For all elements from second vector, fold the elements to first. */
44743 /* Check whether the mask can be applied to the vector type. */
44746 /* Implementable with shufps or pshufd. */
44750 /* Otherwise we have to go through the motions and see if we can
44751 figure out how to generate the requested permutation. */
44762 }
44764 void
44766 {
44781 /* We'll either be able to implement the permutation directly... */
44785 /* ... or we use the special-case patterns. */
44787 }
44789 static void
44791 {
44806 {
44809 }
44811 /* Note that for AVX this isn't one instruction. */
44814 }
44817 /* Expand a vector operation CODE for a V*QImode in terms of the
44818 same operation on V*HImode. */
44820 void
44822 {
44834 {
44847 }
44851 {
44853 /* Unpack data such that we've got a source byte in each low byte of
44854 each word. We don't care what goes into the high byte of each word.
44855 Rather than trying to get zero in there, most convenient is to let
44856 it be a copy of the low byte. */
44861 /* FALLTHRU */
44873 /* FALLTHRU */
44883 }
44885 /* Perform the operation. */
44892 /* Merge the data back into the right place. */
44902 {
44903 /* For SSE2, we used an full interleave, so the desired
44904 results are in the even elements. */
44907 }
44908 else
44909 {
44910 /* For AVX, the interleave used above was not cross-lane. So the
44911 extraction is evens but with the second and third quarter swapped.
44912 Happily, that is even one insn shorter than even extraction. */
44915 }
44922 }
44924 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
44925 if op is CONST_VECTOR with all odd elements equal to their
44926 preceding element. */
44928 static bool
44930 {
44940 }
44942 void
44945 {
44948 rtx x;
44956 /* We only play even/odd games with vectors of SImode. */
44959 /* If we're looking for the odd results, shift those members down to
44960 the even slots. For some cpus this is faster than a PSHUFD. */
44962 {
44963 /* For XOP use vpmacsdqh, but only for smult, as it is only
44964 signed. */
44966 {
44970 }
44981 }
44984 {
44987 else
44989 }
44991 {
44994 else
44996 }
45001 else
45002 {
45005 /* The easiest way to implement this without PMULDQ is to go through
45006 the motions as if we are performing a full 64-bit multiply. With
45007 the exception that we need to do less shuffling of the elements. */
45009 /* Compute the sign-extension, aka highparts, of the two operands. */
45015 /* Multiply LO(A) * HI(B), and vice-versa. */
45021 /* Multiply LO(A) * LO(B). */
45025 /* Combine and shift the highparts into place. */
45030 /* Combine high and low parts. */
45033 }
45035 }
45037 void
45040 {
45046 {
45051 {
45052 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45053 shuffle the elements once so that all elements are in the right
45054 place for immediate use: { A C B D }. */
45059 }
45060 else
45061 {
45062 /* Put the elements into place for the multiply. */
45066 }
45071 /* Shuffle the elements between the lanes. After this we
45072 have { A B E F | C D G H } for each operand. */
45082 /* Shuffle the elements within the lanes. After this we
45083 have { A A B B | C C D D } or { E E F F | G G H H }. */
45121 }
45122 }
45124 void
45126 {
45136 /* Move the results in element 2 down to element 1; we don't care
45137 what goes in elements 2 and 3. Then we can merge the parts
45138 back together with an interleave.
45140 Note that two other sequences were tried:
45141 (1) Use interleaves at the start instead of psrldq, which allows
45142 us to use a single shufps to merge things back at the end.
45143 (2) Use shufps here to combine the two vectors, then pshufd to
45144 put the elements in the correct order.
45145 In both cases the cost of the reformatting stall was too high
45146 and the overall sequence slower. */
45157 }
45159 void
45161 {
45166 {
45167 /* op1: A,B,C,D, op2: E,F,G,H */
45176 /* t1: B,A,D,C */
45183 /* t2: (B*E),(A*F),(D*G),(C*H) */
45186 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45189 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45192 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
45194 }
45195 else
45196 {
45201 {
45204 }
45206 {
45209 }
45211 {
45214 }
45215 else
45219 /* Multiply low parts. */
45223 /* Shift input vectors right 32 bits so we can multiply high parts. */
45228 /* Multiply high parts by low parts. */
45234 /* Combine and shift the highparts back. */
45238 /* Combine high and low parts. */
45240 }
45244 }
45246 /* Calculate integer abs() using only SSE2 instructions. */
45248 void
45250 {
45255 {
45256 /* For 32-bit signed integer X, the best way to calculate the absolute
45257 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45269 /* For 16-bit signed integer X, the best way to calculate the absolute
45270 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45278 /* For 8-bit signed integer X, the best way to calculate the absolute
45279 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45280 as SSE2 provides the PMINUB insn. */
45290 }
45294 }
45296 /* Expand an insert into a vector register through pinsr insn.
45297 Return true if successful. */
45299 bool
45301 {
45309 {
45312 }
45318 {
45323 {
45330 {
45362 }
45376 }
45380 }
45381 }
45382 \f
45383 /* This function returns the calling abi specific va_list type node.
45384 It returns the FNDECL specific va_list type. */
45386 static tree
45388 {
45395 else
45397 }
45399 /* Returns the canonical va_list type specified by TYPE. If there
45400 is no valid TYPE provided, it return NULL_TREE. */
45402 static tree
45404 {
45407 /* Resolve references and pointers to va_list type. */
45416 {
45421 {
45422 /* If va_list is an array type, the argument may have decayed
45423 to a pointer type, e.g. by being passed to another function.
45424 In that case, unwrap both types so that we can compare the
45425 underlying records. */
45428 {
45431 }
45432 }
45439 {
45440 /* If va_list is an array type, the argument may have decayed
45441 to a pointer type, e.g. by being passed to another function.
45442 In that case, unwrap both types so that we can compare the
45443 underlying records. */
45446 {
45449 }
45450 }
45457 {
45458 /* If va_list is an array type, the argument may have decayed
45459 to a pointer type, e.g. by being passed to another function.
45460 In that case, unwrap both types so that we can compare the
45461 underlying records. */
45464 {
45467 }
45468 }
45472 }
45474 }
45476 /* Iterate through the target-specific builtin types for va_list.
45477 IDX denotes the iterator, *PTREE is set to the result type of
45478 the va_list builtin, and *PNAME to its internal type.
45479 Returns zero if there is no element for this index, otherwise
45480 IDX should be increased upon the next call.
45481 Note, do not iterate a base builtin's name like __builtin_va_list.
45482 Used from c_common_nodes_and_builtins. */
45484 static int
45486 {
45488 {
45490 {
45503 }
45504 }
45507 }
45509 #undef TARGET_SCHED_DISPATCH
45510 #define TARGET_SCHED_DISPATCH has_dispatch
45511 #undef TARGET_SCHED_DISPATCH_DO
45512 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45513 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45514 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45515 #undef TARGET_SCHED_REORDER
45516 #define TARGET_SCHED_REORDER ix86_sched_reorder
45517 #undef TARGET_SCHED_ADJUST_PRIORITY
45518 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45519 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45520 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45521 ix86_dependencies_evaluation_hook
45523 /* The size of the dispatch window is the total number of bytes of
45524 object code allowed in a window. */
45525 #define DISPATCH_WINDOW_SIZE 16
45527 /* Number of dispatch windows considered for scheduling. */
45528 #define MAX_DISPATCH_WINDOWS 3
45530 /* Maximum number of instructions in a window. */
45531 #define MAX_INSN 4
45533 /* Maximum number of immediate operands in a window. */
45534 #define MAX_IMM 4
45536 /* Maximum number of immediate bits allowed in a window. */
45537 #define MAX_IMM_SIZE 128
45539 /* Maximum number of 32 bit immediates allowed in a window. */
45540 #define MAX_IMM_32 4
45542 /* Maximum number of 64 bit immediates allowed in a window. */
45543 #define MAX_IMM_64 2
45545 /* Maximum total of loads or prefetches allowed in a window. */
45546 #define MAX_LOAD 2
45548 /* Maximum total of stores allowed in a window. */
45549 #define MAX_STORE 1
45551 #undef BIG
45552 #define BIG 100
45555 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45558 disp_load,
45559 disp_store,
45560 disp_load_store,
45561 disp_prefetch,
45562 disp_imm,
45563 disp_imm_32,
45564 disp_imm_64,
45565 disp_branch,
45566 disp_cmp,
45567 disp_jcc,
45568 disp_last
45569 };
45571 /* Number of allowable groups in a dispatch window. It is an array
45572 indexed by dispatch_group enum. 100 is used as a big number,
45573 because the number of these kind of operations does not have any
45574 effect in dispatch window, but we need them for other reasons in
45575 the table. */
45578 };
45584 };
45586 /* Instruction path. */
45592 last_path
45593 };
45595 /* sched_insn_info defines a window to the instructions scheduled in
45596 the basic block. It contains a pointer to the insn_info table and
45597 the instruction scheduled.
45599 Windows are allocated for each basic block and are linked
45600 together. */
45602 rtx insn;
45609 /* Linked list of dispatch windows. This is a two way list of
45610 dispatch windows of a basic block. It contains information about
45611 the number of uops in the window and the total number of
45612 instructions and of bytes in the object code for this dispatch
45613 window. */
45631 /* Immediate valuse used in an insn. */
45633 {
45642 /* Get dispatch group of insn. */
45644 static enum dispatch_group
45646 {
45662 }
45664 /* Return true if insn is a compare instruction. */
45666 static bool
45668 {
45676 }
45678 /* Return true if a dispatch violation encountered. */
45680 static bool
45682 {
45686 }
45688 /* Return true if insn is a branch instruction. */
45690 static bool
45692 {
45694 }
45696 /* Return true if insn is a prefetch instruction. */
45698 static bool
45700 {
45702 }
45704 /* This function initializes a dispatch window and the list container holding a
45705 pointer to the window. */
45707 static void
45709 {
45715 else
45733 {
45739 }
45741 }
45743 /* This function allocates and initializes a dispatch window and the
45744 list container holding a pointer to the window. */
45748 {
45753 }
45755 /* This routine initializes the dispatch scheduling information. It
45756 initiates building dispatch scheduler tables and constructs the
45757 first dispatch window. */
45759 static void
45761 {
45762 /* Allocate a dispatch list and a window. */
45767 }
45769 /* This function returns true if a branch is detected. End of a basic block
45770 does not have to be a branch, but here we assume only branches end a
45771 window. */
45773 static bool
45775 {
45777 }
45779 /* This function is called when the end of a window processing is reached. */
45781 static void
45783 {
45786 {
45791 }
45793 }
45795 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
45796 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
45797 for 48 bytes of instructions. Note that these windows are not dispatch
45798 windows that their sizes are DISPATCH_WINDOW_SIZE. */
45802 {
45804 {
45809 }
45815 }
45817 /* Increment the number of immediate operands of an instruction. */
45819 static int
45821 {
45826 {
45833 else
45844 {
45847 }
45852 }
45855 }
45857 /* Compute number of immediate operands of an instruction. */
45859 static void
45861 {
45864 }
45866 /* Return total size of immediate operands of an instruction along with number
45867 of corresponding immediate-operands. It initializes its parameters to zero
45868 befor calling FIND_CONSTANT.
45869 INSN is the input instruction. IMM is the total of immediates.
45870 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
45871 bit immediates. */
45873 static int
45875 {
45883 }
45885 /* This function indicates if an operand of an instruction is an
45886 immediate. */
45888 static bool
45890 {
45899 }
45901 /* Return single or double path for instructions. */
45903 static enum insn_path
45905 {
45915 }
45917 /* Return insn dispatch group. */
45919 static enum dispatch_group
45921 {
45939 }
45941 /* Count number of GROUP restricted instructions in a dispatch
45942 window WINDOW_LIST. */
45944 static int
45946 {
45957 {
45976 }
45989 }
45991 /* This function returns true if insn satisfies dispatch rules on the
45992 last window scheduled. */
45994 static bool
45996 {
46004 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
46005 instructions should be given the lowest priority in the
46006 scheduling process in Haifa scheduler to make sure they will be
46007 scheduled in the same dispatch window as the reference to them. */
46011 /* Check nonrestricted. */
46015 /* Get last dispatch window. */
46020 {
46025 /* Window 1 is full. Go for next window. */
46027 }
46034 /* See if it fits in the first window. */
46036 {
46037 /* The first widow should have only single and double path
46038 uops. */
46044 }
46046 }
46048 /* Add an instruction INSN with NUM_UOPS micro-operations to the
46049 dispatch window WINDOW_LIST. */
46051 static void
46053 {
46071 /* Initialize window with new instruction. */
46092 {
46095 }
46096 }
46098 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46099 If the total bytes of instructions or the number of instructions in
46100 the window exceed allowable, it allocates a new window. */
46102 static void
46104 {
46127 /* Get the last dispatch window. */
46135 else
46138 /* If current window is full, get a new window.
46139 Window number zero is full, if MAX_INSN uops are scheduled in it.
46140 Window number one is full, if window zero's bytes plus window
46141 one's bytes is 32, or if the bytes of the new instruction added
46142 to the total makes it greater than 48, or it has already MAX_INSN
46143 instructions in it. */
46152 {
46155 }
46158 {
46162 {
46165 }
46166 }
46168 {
46173 {
46176 }
46179 }
46180 else
46184 {
46185 /* End of basic block is reached do end-basic-block process. */
46188 }
46189 }
46191 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46193 DEBUG_FUNCTION static void
46195 {
46201 else
46215 {
46218 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46224 }
46225 }
46227 /* Print to stdout a dispatch window. */
46229 DEBUG_FUNCTION void
46231 {
46233 }
46235 /* Print INSN dispatch information to FILE. */
46237 DEBUG_FUNCTION static void
46239 {
46262 }
46264 /* Print to STDERR the status of the ready list with respect to
46265 dispatch windows. */
46267 DEBUG_FUNCTION void
46269 {
46277 }
46279 /* This routine is the driver of the dispatch scheduler. */
46281 static void
46283 {
46288 }
46290 /* Return TRUE if Dispatch Scheduling is supported. */
46292 static bool
46294 {
46298 {
46314 }
46317 }
46319 /* Implementation of reassociation_width target hook used by
46320 reassoc phase to identify parallelism level in reassociated
46321 tree. Statements tree_code is passed in OPC. Arguments type
46322 is passed in MODE.
46324 Currently parallel reassociation is enabled for Atom
46325 processors only and we set reassociation width to be 2
46326 because Atom may issue up to 2 instructions per cycle.
46328 Return value should be fixed if parallel reassociation is
46329 enabled for other processors. */
46331 static int
46334 {
46343 }
46345 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46346 place emms and femms instructions. */
46348 static enum machine_mode
46350 {
46355 {
46372 else
46384 /* FALLTHRU */
46388 }
46389 }
46391 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46392 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46393 256bit and 128bit vectors. */
46395 static unsigned int
46397 {
46400 }
46402 \f
46404 /* Return class of registers which could be used for pseudo of MODE
46405 and of class RCLASS for spilling instead of memory. Return NO_REGS
46406 if it is not possible or non-profitable. */
46407 static reg_class_t
46409 {
46415 }
46417 /* Implement targetm.vectorize.init_cost. */
46421 {
46425 }
46427 /* Implement targetm.vectorize.add_stmt_cost. */
46429 static unsigned
46433 {
46440 /* Statements in an inner loop relative to the loop being
46441 vectorized are weighted more heavily. The value here is
46442 arbitrary and could potentially be improved with analysis. */
46448 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
46449 for Silvermont as it has out of order integer pipeline and can execute
46450 2 scalar instruction per tick, but has in order SIMD pipeline. */
46453 {
46457 }
46462 }
46464 /* Implement targetm.vectorize.finish_cost. */
46466 static void
46469 {
46474 }
46476 /* Implement targetm.vectorize.destroy_cost_data. */
46478 static void
46480 {
46482 }
46484 /* Validate target specific memory model bits in VAL. */
46486 static unsigned HOST_WIDE_INT
46488 {
46495 {
46499 }
46502 {
46506 }
46508 {
46512 }
46514 }
46516 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46517 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46518 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46519 or number of vecsize_mangle variants that should be emitted. */
46521 static int
46525 {
46532 {
46536 }
46541 {
46548 /* case SCmode: */
46549 /* case DCmode: */
46555 }
46557 tree t;
46561 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46563 {
46570 /* case SCmode: */
46571 /* case DCmode: */
46577 }
46580 {
46581 /* Parse here processor clause. If not present, default to 'b'. */
46583 }
46585 {
46586 /* If the function isn't exported, we can pick up just one ISA
46587 for the clones. */
46592 else
46595 }
46596 else
46597 {
46600 }
46602 {
46615 }
46617 {
46620 else
46625 }
46627 }
46629 /* Add target attribute to SIMD clone NODE if needed. */
46631 static void
46633 {
46637 {
46652 }
46662 }
46664 /* If SIMD clone NODE can't be used in a vectorized loop
46665 in current function, return -1, otherwise return a badness of using it
46666 (0 if it is most desirable from vecsize_mangle point of view, 1
46667 slightly less desirable, etc.). */
46669 static int
46671 {
46673 {
46691 }
46692 }
46694 /* This function gives out the number of memory references.
46695 This value determines the unrolling factor for
46696 bdver3 and bdver4 architectures. */
46698 static int
46700 {
46702 {
46711 else
46713 }
46715 }
46717 /* This function adjusts the unroll factor based on
46718 the hardware capabilities. For ex, bdver3 has
46719 a loop buffer which makes unrolling of smaller
46720 loops less important. This function decides the
46721 unroll factor using number of memory references
46722 (value 32 is used) as a heuristic. */
46724 static unsigned
46726 {
46728 rtx insn;
46735 /* Count the number of memory references within the loop body. */
46738 {
46742 }
46749 }
46752 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
46754 static bool
46756 {
46757 /* For x87 floating point with standard excess precision handling,
46758 there is no adddf3 pattern (since x87 floating point only has
46759 XFmode operations) so the default hook implementation gets this
46760 wrong. */
46762 }
46764 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
46766 static void
46768 {
46773 {
46788 hold_fnclex);
46802 }
46804 {
46813 mxcsr_orig_var,
46823 ldmxcsr_hold_call);
46826 else
46831 ldmxcsr_clear_call);
46832 else
46836 stxmcsr_update_call);
46838 {
46844 exceptions_assign);
46845 }
46846 else
46851 ldmxcsr_update_call);
46852 }
46853 tree atomic_feraiseexcept
46858 atomic_feraiseexcept_call);
46859 }
46861 /* Initialize the GCC target structure. */
46862 #undef TARGET_RETURN_IN_MEMORY
46863 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
46865 #undef TARGET_LEGITIMIZE_ADDRESS
46866 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
46868 #undef TARGET_ATTRIBUTE_TABLE
46869 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
46870 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
46871 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
46872 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46873 # undef TARGET_MERGE_DECL_ATTRIBUTES
46874 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
46875 #endif
46877 #undef TARGET_COMP_TYPE_ATTRIBUTES
46878 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
46880 #undef TARGET_INIT_BUILTINS
46881 #define TARGET_INIT_BUILTINS ix86_init_builtins
46882 #undef TARGET_BUILTIN_DECL
46883 #define TARGET_BUILTIN_DECL ix86_builtin_decl
46884 #undef TARGET_EXPAND_BUILTIN
46885 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
46887 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
46888 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
46889 ix86_builtin_vectorized_function
46891 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
46892 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
46894 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
46895 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
46897 #undef TARGET_VECTORIZE_BUILTIN_GATHER
46898 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
46900 #undef TARGET_BUILTIN_RECIPROCAL
46901 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
46903 #undef TARGET_ASM_FUNCTION_EPILOGUE
46904 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
46906 #undef TARGET_ENCODE_SECTION_INFO
46907 #ifndef SUBTARGET_ENCODE_SECTION_INFO
46908 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
46909 #else
46910 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
46911 #endif
46913 #undef TARGET_ASM_OPEN_PAREN
46915 #undef TARGET_ASM_CLOSE_PAREN
46918 #undef TARGET_ASM_BYTE_OP
46919 #define TARGET_ASM_BYTE_OP ASM_BYTE
46921 #undef TARGET_ASM_ALIGNED_HI_OP
46922 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
46923 #undef TARGET_ASM_ALIGNED_SI_OP
46924 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
46925 #ifdef ASM_QUAD
46926 #undef TARGET_ASM_ALIGNED_DI_OP
46927 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
46928 #endif
46930 #undef TARGET_PROFILE_BEFORE_PROLOGUE
46931 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
46933 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
46934 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
46936 #undef TARGET_ASM_UNALIGNED_HI_OP
46937 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
46938 #undef TARGET_ASM_UNALIGNED_SI_OP
46939 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
46940 #undef TARGET_ASM_UNALIGNED_DI_OP
46941 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
46943 #undef TARGET_PRINT_OPERAND
46944 #define TARGET_PRINT_OPERAND ix86_print_operand
46945 #undef TARGET_PRINT_OPERAND_ADDRESS
46946 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
46947 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
46948 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
46949 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
46950 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
46952 #undef TARGET_SCHED_INIT_GLOBAL
46953 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
46954 #undef TARGET_SCHED_ADJUST_COST
46955 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
46956 #undef TARGET_SCHED_ISSUE_RATE
46957 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
46958 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
46959 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
46960 ia32_multipass_dfa_lookahead
46961 #undef TARGET_SCHED_MACRO_FUSION_P
46962 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
46963 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
46964 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
46966 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
46967 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
46969 #undef TARGET_MEMMODEL_CHECK
46970 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
46972 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
46973 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
46975 #ifdef HAVE_AS_TLS
46976 #undef TARGET_HAVE_TLS
46977 #define TARGET_HAVE_TLS true
46978 #endif
46979 #undef TARGET_CANNOT_FORCE_CONST_MEM
46980 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
46981 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
46982 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
46984 #undef TARGET_DELEGITIMIZE_ADDRESS
46985 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
46987 #undef TARGET_MS_BITFIELD_LAYOUT_P
46988 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
46990 #if TARGET_MACHO
46991 #undef TARGET_BINDS_LOCAL_P
46992 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
46993 #endif
46994 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46995 #undef TARGET_BINDS_LOCAL_P
46996 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
46997 #endif
46999 #undef TARGET_ASM_OUTPUT_MI_THUNK
47000 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
47001 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
47002 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
47004 #undef TARGET_ASM_FILE_START
47005 #define TARGET_ASM_FILE_START x86_file_start
47007 #undef TARGET_OPTION_OVERRIDE
47008 #define TARGET_OPTION_OVERRIDE ix86_option_override
47010 #undef TARGET_REGISTER_MOVE_COST
47011 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
47012 #undef TARGET_MEMORY_MOVE_COST
47013 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
47014 #undef TARGET_RTX_COSTS
47015 #define TARGET_RTX_COSTS ix86_rtx_costs
47016 #undef TARGET_ADDRESS_COST
47017 #define TARGET_ADDRESS_COST ix86_address_cost
47019 #undef TARGET_FIXED_CONDITION_CODE_REGS
47020 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
47021 #undef TARGET_CC_MODES_COMPATIBLE
47022 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
47024 #undef TARGET_MACHINE_DEPENDENT_REORG
47025 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
47027 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
47028 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
47030 #undef TARGET_BUILD_BUILTIN_VA_LIST
47031 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
47033 #undef TARGET_FOLD_BUILTIN
47034 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
47036 #undef TARGET_COMPARE_VERSION_PRIORITY
47037 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
47039 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
47040 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
47041 ix86_generate_version_dispatcher_body
47043 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
47044 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
47045 ix86_get_function_versions_dispatcher
47047 #undef TARGET_ENUM_VA_LIST_P
47048 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
47050 #undef TARGET_FN_ABI_VA_LIST
47051 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
47053 #undef TARGET_CANONICAL_VA_LIST_TYPE
47054 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
47056 #undef TARGET_EXPAND_BUILTIN_VA_START
47057 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
47059 #undef TARGET_MD_ASM_CLOBBERS
47060 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47062 #undef TARGET_PROMOTE_PROTOTYPES
47063 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47064 #undef TARGET_SETUP_INCOMING_VARARGS
47065 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47066 #undef TARGET_MUST_PASS_IN_STACK
47067 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47068 #undef TARGET_FUNCTION_ARG_ADVANCE
47069 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47070 #undef TARGET_FUNCTION_ARG
47071 #define TARGET_FUNCTION_ARG ix86_function_arg
47072 #undef TARGET_FUNCTION_ARG_BOUNDARY
47073 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47074 #undef TARGET_PASS_BY_REFERENCE
47075 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47076 #undef TARGET_INTERNAL_ARG_POINTER
47077 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47078 #undef TARGET_UPDATE_STACK_BOUNDARY
47079 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47080 #undef TARGET_GET_DRAP_RTX
47081 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47082 #undef TARGET_STRICT_ARGUMENT_NAMING
47083 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47084 #undef TARGET_STATIC_CHAIN
47085 #define TARGET_STATIC_CHAIN ix86_static_chain
47086 #undef TARGET_TRAMPOLINE_INIT
47087 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47088 #undef TARGET_RETURN_POPS_ARGS
47089 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47091 #undef TARGET_LEGITIMATE_COMBINED_INSN
47092 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47094 #undef TARGET_ASAN_SHADOW_OFFSET
47095 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47097 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47098 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47100 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47101 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47103 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47104 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47106 #undef TARGET_C_MODE_FOR_SUFFIX
47107 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47109 #ifdef HAVE_AS_TLS
47110 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47111 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47112 #endif
47114 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47115 #undef TARGET_INSERT_ATTRIBUTES
47116 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47117 #endif
47119 #undef TARGET_MANGLE_TYPE
47120 #define TARGET_MANGLE_TYPE ix86_mangle_type
47122 #if !TARGET_MACHO
47123 #undef TARGET_STACK_PROTECT_FAIL
47124 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47125 #endif
47127 #undef TARGET_FUNCTION_VALUE
47128 #define TARGET_FUNCTION_VALUE ix86_function_value
47130 #undef TARGET_FUNCTION_VALUE_REGNO_P
47131 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47133 #undef TARGET_PROMOTE_FUNCTION_MODE
47134 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47136 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47137 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47139 #undef TARGET_INSTANTIATE_DECLS
47140 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47142 #undef TARGET_SECONDARY_RELOAD
47143 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47145 #undef TARGET_CLASS_MAX_NREGS
47146 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47148 #undef TARGET_PREFERRED_RELOAD_CLASS
47149 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47150 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47151 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47152 #undef TARGET_CLASS_LIKELY_SPILLED_P
47153 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47155 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47156 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47157 ix86_builtin_vectorization_cost
47158 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47159 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47160 ix86_vectorize_vec_perm_const_ok
47161 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47162 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47163 ix86_preferred_simd_mode
47164 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47165 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47166 ix86_autovectorize_vector_sizes
47167 #undef TARGET_VECTORIZE_INIT_COST
47168 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47169 #undef TARGET_VECTORIZE_ADD_STMT_COST
47170 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47171 #undef TARGET_VECTORIZE_FINISH_COST
47172 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47173 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47174 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47176 #undef TARGET_SET_CURRENT_FUNCTION
47177 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47179 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47180 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47182 #undef TARGET_OPTION_SAVE
47183 #define TARGET_OPTION_SAVE ix86_function_specific_save
47185 #undef TARGET_OPTION_RESTORE
47186 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47188 #undef TARGET_OPTION_PRINT
47189 #define TARGET_OPTION_PRINT ix86_function_specific_print
47191 #undef TARGET_OPTION_FUNCTION_VERSIONS
47192 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47194 #undef TARGET_CAN_INLINE_P
47195 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47197 #undef TARGET_EXPAND_TO_RTL_HOOK
47198 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47200 #undef TARGET_LEGITIMATE_ADDRESS_P
47201 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47203 #undef TARGET_LRA_P
47204 #define TARGET_LRA_P hook_bool_void_true
47206 #undef TARGET_REGISTER_PRIORITY
47207 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47209 #undef TARGET_REGISTER_USAGE_LEVELING_P
47210 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47212 #undef TARGET_LEGITIMATE_CONSTANT_P
47213 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47215 #undef TARGET_FRAME_POINTER_REQUIRED
47216 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47218 #undef TARGET_CAN_ELIMINATE
47219 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47221 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47222 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47224 #undef TARGET_ASM_CODE_END
47225 #define TARGET_ASM_CODE_END ix86_code_end
47227 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47228 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47230 #if TARGET_MACHO
47231 #undef TARGET_INIT_LIBFUNCS
47232 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47233 #endif
47235 #undef TARGET_LOOP_UNROLL_ADJUST
47236 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47238 #undef TARGET_SPILL_CLASS
47239 #define TARGET_SPILL_CLASS ix86_spill_class
47241 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47242 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47243 ix86_simd_clone_compute_vecsize_and_simdlen
47245 #undef TARGET_SIMD_CLONE_ADJUST
47246 #define TARGET_SIMD_CLONE_ADJUST \
47247 ix86_simd_clone_adjust
47249 #undef TARGET_SIMD_CLONE_USABLE
47250 #define TARGET_SIMD_CLONE_USABLE \
47251 ix86_simd_clone_usable
47253 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47254 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47255 ix86_float_exceptions_rounding_supported_p
47257 #undef TARGET_MODE_EMIT
47258 #define TARGET_MODE_EMIT ix86_emit_mode_set
47260 #undef TARGET_MODE_NEEDED
47261 #define TARGET_MODE_NEEDED ix86_mode_needed
47263 #undef TARGET_MODE_AFTER
47264 #define TARGET_MODE_AFTER ix86_mode_after
47266 #undef TARGET_MODE_ENTRY
47267 #define TARGET_MODE_ENTRY ix86_mode_entry
47269 #undef TARGET_MODE_EXIT
47270 #define TARGET_MODE_EXIT ix86_mode_exit
47272 #undef TARGET_MODE_PRIORITY
47273 #define TARGET_MODE_PRIORITY ix86_mode_priority
47276 \f