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1 /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu.
2 Copyright (C) 1994, 1995, 1997, 1998, 2007-2013
3 Free Software Foundation, Inc.
5 Sources derived from work done by Sankhya Technologies (www.sankhya.com) on
6 behalf of Synopsys Inc.
8 Position Independent Code support added,Code cleaned up,
9 Comments and Support For ARC700 instructions added by
10 Saurabh Verma (saurabh.verma@codito.com)
11 Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
13 This file is part of GCC.
15 GCC is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 3, or (at your option)
18 any later version.
20 GCC is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with GCC; see the file COPYING3. If not see
27 <http://www.gnu.org/licenses/>. */
29 #ifndef GCC_ARC_H
30 #define GCC_ARC_H
32 /* Things to do:
34 - incscc, decscc?
36 */
38 #define SYMBOL_FLAG_SHORT_CALL (SYMBOL_FLAG_MACH_DEP << 0)
39 #define SYMBOL_FLAG_MEDIUM_CALL (SYMBOL_FLAG_MACH_DEP << 1)
40 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 2)
42 /* Check if this symbol has a long_call attribute in its declaration */
43 #define SYMBOL_REF_LONG_CALL_P(X) \
44 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
46 /* Check if this symbol has a medium_call attribute in its declaration */
47 #define SYMBOL_REF_MEDIUM_CALL_P(X) \
48 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_MEDIUM_CALL) != 0)
50 /* Check if this symbol has a short_call attribute in its declaration */
51 #define SYMBOL_REF_SHORT_CALL_P(X) \
52 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SHORT_CALL) != 0)
54 #undef ASM_SPEC
55 #undef LINK_SPEC
56 #undef STARTFILE_SPEC
57 #undef ENDFILE_SPEC
58 #undef SIZE_TYPE
59 #undef PTRDIFF_TYPE
60 #undef WCHAR_TYPE
61 #undef WCHAR_TYPE_SIZE
62 #undef ASM_APP_ON
63 #undef ASM_APP_OFF
64 #undef CC1_SPEC
66 /* Names to predefine in the preprocessor for this target machine. */
67 #define TARGET_CPU_CPP_BUILTINS() \
68 do { \
70 if (TARGET_A5) \
72 else if (TARGET_ARC600) \
73 { \
76 } \
77 else if (TARGET_ARC601) \
78 { \
80 } \
81 else if (TARGET_ARC700) \
82 { \
85 } \
86 if (TARGET_NORM) \
87 { \
90 } \
91 if (TARGET_MUL64_SET) \
93 if (TARGET_MULMAC_32BY16_SET) \
95 if (TARGET_SIMD_SET) \
97 if (TARGET_BARREL_SHIFTER) \
101 builtin_define (TARGET_BIG_ENDIAN \
103 if (TARGET_BIG_ENDIAN) \
105 } while(0)
107 #if DEFAULT_LIBC == LIBC_UCLIBC
109 #define TARGET_OS_CPP_BUILTINS() \
110 do \
111 { \
112 GNU_USER_TARGET_OS_CPP_BUILTINS (); \
113 } \
114 while (0)
115 #endif
117 /* Match the macros used in the assembler. */
119 %{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \
120 %{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \
121 %{mspfp*:-D__Xspfp} %{mdpfp*:-D__Xdpfp} \
122 %{mmac-d16:-D__Xxmac_d16} %{mmac-24:-D__Xxmac_24} \
123 %{mdsp-packa:-D__Xdsp_packa} %{mcrc:-D__Xcrc} %{mdvbf:-D__Xdvbf} \
124 %{mtelephony:-D__Xtelephony} %{mxy:-D__Xxy} %{mmul64: -D__Xmult32} \
125 %{mlock:-D__Xlock} %{mswape:-D__Xswape} %{mrtsc:-D__Xrtsc} \
126 "
129 %{EB:%{EL:%emay not use both -EB and -EL}} \
130 %{EB:-mbig-endian} %{EL:-mlittle-endian} \
131 "
136 %{mbig-endian|EB:-EB} %{EL} \
137 %{mcpu=A5|mcpu=a5|mA5:-mA5} \
138 %{mcpu=ARC600:-mARC600} \
139 %{mcpu=ARC601:-mARC601} \
140 %{mcpu=ARC700:-mARC700} \
141 %{mcpu=ARC700:-mEA} \
143 %{mbarrel-shifter} %{mno-mpy} %{mmul64} %{mmul32x16:-mdsp-packa} %{mnorm} \
144 %{mswap} %{mEA} %{mmin-max} %{mspfp*} %{mdpfp*} \
145 %{msimd} \
146 %{mmac-d16} %{mmac-24} %{mdsp-packa} %{mcrc} %{mdvbf} %{mtelephony} %{mxy} \
147 %{mcpu=ARC700|!mcpu=*:%{mlock}} \
148 %{mcpu=ARC700|!mcpu=*:%{mswape}} \
149 %{mcpu=ARC700|!mcpu=*:%{mrtsc}} \
150 "
152 #if DEFAULT_LIBC == LIBC_UCLIBC
153 /* Note that the default is to link against dynamic libraries, if they are
154 available. Override with -static. */
156 %{static:-Bstatic} \
157 %{symbolic:-Bsymbolic} \
158 %{rdynamic:-export-dynamic}\
159 -dynamic-linker /lib/ld-uClibc.so.0 \
160 -X %{mbig-endian:-EB} \
161 %{EB} %{EL} \
162 %{marclinux*} \
163 %{!marclinux*: %{pg|p|profile:-marclinux_prof;: -marclinux}} \
164 %{!z:-z max-page-size=0x2000 -z common-page-size=0x2000} \
165 %{shared:-shared}"
166 /* Like the standard LINK_COMMAND_SPEC, but add %G when building
167 a shared library with -nostdlib, so that the hidden functions of libgcc
168 will be incorporated.
169 N.B., we don't want a plain -lgcc, as this would lead to re-exporting
170 non-hidden functions, so we have to consider libgcc_s.so.* first, which in
171 turn should be wrapped with --as-needed. */
173 %{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\
175 %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
176 %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
177 %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)}\
178 %(mflib)\
179 %{fprofile-arcs|fprofile-generate|coverage:-lgcov}\
180 %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}}\
181 %{!A:%{!nostdlib:%{!nostartfiles:%E}}} %{T*} }}}}}}"
183 #else
185 %{pg|p:-marcelf_prof;mA7|mARC700|mcpu=arc700|mcpu=ARC700: -marcelf}"
186 #endif
188 #if DEFAULT_LIBC != LIBC_UCLIBC
190 #else
192 %{!shared:%{pg|p|profile:crtg.o%s} crtbegin.o%s} %{shared:crtbeginS.o%s}"
194 #endif
196 #if DEFAULT_LIBC != LIBC_UCLIBC
198 #else
200 %{shared:crtendS.o%s} crtn.o%s"
202 #endif
204 #if DEFAULT_LIBC == LIBC_UCLIBC
205 #undef LIB_SPEC
206 #define LIB_SPEC \
207 "%{pthread:-lpthread} \
208 %{shared:-lc} \
209 %{!shared:%{pg|p|profile:-lgmon -u profil --defsym __profil=profil} -lc}"
210 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
211 #else
212 #undef LIB_SPEC
213 /* -lc_p not present for arc-elf32-* : ashwin */
215 #endif
217 #ifndef DRIVER_ENDIAN_SELF_SPECS
219 #endif
220 #ifndef TARGET_SDATA_DEFAULT
221 #define TARGET_SDATA_DEFAULT 1
222 #endif
223 #ifndef TARGET_MMEDIUM_CALLS_DEFAULT
224 #define TARGET_MMEDIUM_CALLS_DEFAULT 0
225 #endif
227 #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \
238 "%{multcost=*: -mmultcost=%* %<multcost=*}"
240 /* Run-time compilation parameters selecting different hardware subsets. */
242 #define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET)
244 #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET)
245 #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET)
247 #define SUBTARGET_SWITCHES
249 /* Instruction set characteristics.
250 These are internal macros, set by the appropriate -m option. */
252 /* Non-zero means the cpu supports norm instruction. This flag is set by
253 default for A7, and only for pre A7 cores when -mnorm is given. */
254 #define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET)
255 /* Indicate if an optimized floating point emulation library is available. */
256 #define TARGET_OPTFPE \
257 (TARGET_ARC700 \
259 || (TARGET_ARC600 && TARGET_NORM_SET))
261 /* Non-zero means the cpu supports swap instruction. This flag is set by
262 default for A7, and only for pre A7 cores when -mswap is given. */
263 #define TARGET_SWAP (TARGET_ARC700 || TARGET_SWAP_SET)
265 /* Provide some macros for size / scheduling features of the ARC700, so
266 that we can pick & choose features if we get a new cpu family member. */
268 /* Should we try to unalign likely taken branches without a delay slot. */
269 #define TARGET_UNALIGN_BRANCH (TARGET_ARC700 && !optimize_size)
271 /* Should we upsize short delayed branches with a short delay insn? */
272 #define TARGET_UPSIZE_DBR (TARGET_ARC700 && !optimize_size)
274 /* Should we add padding before a return insn to avoid mispredict? */
275 #define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size)
277 /* For an anulled-true delay slot insn for a delayed branch, should we only
278 use conditional execution? */
279 #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700)
281 #define TARGET_A5 (arc_cpu == PROCESSOR_A5)
282 #define TARGET_ARC600 (arc_cpu == PROCESSOR_ARC600)
283 #define TARGET_ARC601 (arc_cpu == PROCESSOR_ARC601)
284 #define TARGET_ARC700 (arc_cpu == PROCESSOR_ARC700)
286 /* Recast the cpu class to be the cpu attribute. */
287 #define arc_cpu_attr ((enum attr_cpu)arc_cpu)
289 #ifndef MULTILIB_DEFAULTS
291 #endif
293 /* Target machine storage layout. */
295 /* We want zero_extract to mean the same
296 no matter what the byte endianness is. */
297 #define BITS_BIG_ENDIAN 0
299 /* Define this if most significant byte of a word is the lowest numbered. */
300 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
302 /* Define this if most significant word of a multiword number is the lowest
303 numbered. */
304 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
306 /* Number of bits in an addressable storage unit. */
307 #define BITS_PER_UNIT 8
309 /* Width in bits of a "word", which is the contents of a machine register.
310 Note that this is not necessarily the width of data type `int';
311 if using 16-bit ints on a 68000, this would still be 32.
312 But on a machine with 16-bit registers, this would be 16. */
313 #define BITS_PER_WORD 32
315 /* Width of a word, in units (bytes). */
316 #define UNITS_PER_WORD 4
318 /* Define this macro if it is advisable to hold scalars in registers
319 in a wider mode than that declared by the program. In such cases,
320 the value is constrained to be within the bounds of the declared
321 type, but kept valid in the wider mode. The signedness of the
322 extension may differ from that of the type. */
323 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
324 if (GET_MODE_CLASS (MODE) == MODE_INT \
325 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
326 { \
327 (MODE) = SImode; \
328 }
330 /* Width in bits of a pointer.
331 See also the macro `Pmode' defined below. */
332 #define POINTER_SIZE 32
334 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
335 #define PARM_BOUNDARY 32
337 /* Boundary (in *bits*) on which stack pointer should be aligned. */
338 /* TOCHECK: Changed from 64 to 32 */
339 #define STACK_BOUNDARY 32
341 /* ALIGN FRAMES on word boundaries. */
342 #define ARC_STACK_ALIGN(LOC) \
343 (((LOC) + STACK_BOUNDARY / BITS_PER_UNIT - 1) & -STACK_BOUNDARY/BITS_PER_UNIT)
345 /* Allocation boundary (in *bits*) for the code of a function. */
346 #define FUNCTION_BOUNDARY 32
348 /* Alignment of field after `int : 0' in a structure. */
349 #define EMPTY_FIELD_BOUNDARY 32
351 /* Every structure's size must be a multiple of this. */
352 #define STRUCTURE_SIZE_BOUNDARY 8
354 /* A bitfield declared as `int' forces `int' alignment for the struct. */
355 #define PCC_BITFIELD_TYPE_MATTERS 1
357 /* An expression for the alignment of a structure field FIELD if the
358 alignment computed in the usual way (including applying of
359 `BIGGEST_ALIGNMENT' and `BIGGEST_FIELD_ALIGNMENT' to the
360 alignment) is COMPUTED. It overrides alignment only if the field
361 alignment has not been set by the `__attribute__ ((aligned (N)))'
362 construct.
363 */
365 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
366 (TYPE_MODE (strip_array_types (TREE_TYPE (FIELD))) == DFmode \
367 ? MIN ((COMPUTED), 32) : (COMPUTED))
371 /* No data type wants to be aligned rounder than this. */
372 /* This is bigger than currently necessary for the ARC. If 8 byte floats are
373 ever added it's not clear whether they'll need such alignment or not. For
374 now we assume they will. We can always relax it if necessary but the
375 reverse isn't true. */
376 /* TOCHECK: Changed from 64 to 32 */
377 #define BIGGEST_ALIGNMENT 32
379 /* The best alignment to use in cases where we have a choice. */
380 #define FASTEST_ALIGNMENT 32
382 /* Make strings word-aligned so strcpy from constants will be faster. */
383 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
384 ((TREE_CODE (EXP) == STRING_CST \
385 && (ALIGN) < FASTEST_ALIGNMENT) \
386 ? FASTEST_ALIGNMENT : (ALIGN))
389 /* Make arrays of chars word-aligned for the same reasons. */
390 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
391 (TREE_CODE (TYPE) == ARRAY_TYPE \
392 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
393 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
395 #define DATA_ALIGNMENT(TYPE, ALIGN) \
396 (TREE_CODE (TYPE) == ARRAY_TYPE \
397 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
398 && arc_size_opt_level < 3 \
399 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
401 /* Set this nonzero if move instructions will actually fail to work
402 when given unaligned data. */
403 /* On the ARC the lower address bits are masked to 0 as necessary. The chip
404 won't croak when given an unaligned address, but the insn will still fail
405 to produce the correct result. */
406 #define STRICT_ALIGNMENT 1
408 /* Layout of source language data types. */
410 #define SHORT_TYPE_SIZE 16
411 #define INT_TYPE_SIZE 32
412 #define LONG_TYPE_SIZE 32
413 #define LONG_LONG_TYPE_SIZE 64
414 #define FLOAT_TYPE_SIZE 32
415 #define DOUBLE_TYPE_SIZE 64
416 #define LONG_DOUBLE_TYPE_SIZE 64
418 /* Define this as 1 if `char' should by default be signed; else as 0. */
419 #define DEFAULT_SIGNED_CHAR 0
424 #define WCHAR_TYPE_SIZE 32
427 /* ashwin : shifted from arc.c:102 */
428 #define PROGRAM_COUNTER_REGNO 63
430 /* Standard register usage. */
432 /* Number of actual hardware registers.
433 The hardware registers are assigned numbers for the compiler
434 from 0 to just below FIRST_PSEUDO_REGISTER.
435 All registers that the compiler knows about must be given numbers,
436 even those that are not normally considered general registers.
438 Registers 61, 62, and 63 are not really registers and we needn't treat
439 them as such. We still need a register for the condition code and
440 argument pointer. */
442 /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs
443 r144, r145 = lp_start, lp_end
444 and therefore the pseudo registers start from r146. */
445 #define FIRST_PSEUDO_REGISTER 146
447 /* 1 for registers that have pervasive standard uses
448 and are not available for the register allocator.
450 0-28 - general purpose registers
451 29 - ilink1 (interrupt link register)
452 30 - ilink2 (interrupt link register)
453 31 - blink (branch link register)
454 32-59 - reserved for extensions
455 60 - LP_COUNT
456 61 - condition code
457 62 - argument pointer
458 63 - program counter
460 FWIW, this is how the 61-63 encodings are used by the hardware:
461 61 - reserved
462 62 - long immediate data indicator
463 63 - PCL (program counter aligned to 32 bit, read-only)
465 The general purpose registers are further broken down into:
467 0-7 - arguments/results
468 8-12 - call used (r11 - static chain pointer)
469 13-25 - call saved
470 26 - global pointer
471 27 - frame pointer
472 28 - stack pointer
473 29 - ilink1
474 30 - ilink2
475 31 - return address register
477 By default, the extension registers are not available. */
478 /* Present implementations only have VR0-VR23 only. */
479 /* ??? FIXME: r27 and r31 should not be fixed registers. */
480 #define FIXED_REGISTERS \
481 { 0, 0, 0, 0, 0, 0, 0, 0, \
482 0, 0, 0, 0, 0, 0, 0, 0, \
483 0, 0, 0, 0, 0, 0, 0, 0, \
484 0, 0, 1, 1, 1, 1, 1, 1, \
485 \
486 1, 1, 1, 1, 1, 1, 1, 1, \
487 0, 0, 0, 0, 1, 1, 1, 1, \
488 1, 1, 1, 1, 1, 1, 1, 1, \
489 1, 1, 1, 1, 0, 1, 1, 1, \
490 \
491 0, 0, 0, 0, 0, 0, 0, 0, \
492 0, 0, 0, 0, 0, 0, 0, 0, \
493 0, 0, 0, 0, 0, 0, 0, 0, \
494 1, 1, 1, 1, 1, 1, 1, 1, \
495 \
496 1, 1, 1, 1, 1, 1, 1, 1, \
497 1, 1, 1, 1, 1, 1, 1, 1, \
498 1, 1, 1, 1, 1, 1, 1, 1, \
499 1, 1, 1, 1, 1, 1, 1, 1, \
500 \
501 0, 0, 0, 0, 0, 0, 0, 0, \
502 0, 0, 0, 0, 0, 0, 0, 0, \
503 1, 1}
505 /* 1 for registers not available across function calls.
506 These must include the FIXED_REGISTERS and also any
507 registers that can be used without being saved.
508 The latter must include the registers where values are returned
509 and the register where structure-value addresses are passed.
510 Aside from that, you can include as many other registers as you like. */
511 #define CALL_USED_REGISTERS \
512 { \
513 1, 1, 1, 1, 1, 1, 1, 1, \
514 1, 1, 1, 1, 1, 0, 0, 0, \
515 0, 0, 0, 0, 0, 0, 0, 0, \
516 0, 0, 1, 1, 1, 1, 1, 1, \
517 \
518 1, 1, 1, 1, 1, 1, 1, 1, \
519 1, 1, 1, 1, 1, 1, 1, 1, \
520 1, 1, 1, 1, 1, 1, 1, 1, \
521 1, 1, 1, 1, 1, 1, 1, 1, \
522 \
523 0, 0, 0, 0, 0, 0, 0, 0, \
524 0, 0, 0, 0, 0, 0, 0, 0, \
525 0, 0, 0, 0, 0, 0, 0, 0, \
526 1, 1, 1, 1, 1, 1, 1, 1, \
527 \
528 1, 1, 1, 1, 1, 1, 1, 1, \
529 1, 1, 1, 1, 1, 1, 1, 1, \
530 1, 1, 1, 1, 1, 1, 1, 1, \
531 1, 1, 1, 1, 1, 1, 1, 1, \
532 \
533 0, 0, 0, 0, 0, 0, 0, 0, \
534 0, 0, 0, 0, 0, 0, 0, 0, \
535 1, 1}
537 /* If defined, an initializer for a vector of integers, containing the
538 numbers of hard registers in the order in which GCC should
539 prefer to use them (from most preferred to least). */
540 #define REG_ALLOC_ORDER \
541 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
542 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
543 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
544 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
545 27, 28, 29, 30, 31, 63}
547 /* Return number of consecutive hard regs needed starting at reg REGNO
548 to hold something of mode MODE.
549 This is ordinarily the length in words of a value of mode MODE
550 but can be less for certain modes in special long registers. */
551 #define HARD_REGNO_NREGS(REGNO, MODE) \
552 ((GET_MODE_SIZE (MODE) == 16 \
553 && REGNO >= ARC_FIRST_SIMD_VR_REG && REGNO <= ARC_LAST_SIMD_VR_REG) ? 1 \
554 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
556 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
559 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
560 ((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0)
562 /* A C expression that is nonzero if it is desirable to choose
563 register allocation so as to avoid move instructions between a
564 value of mode MODE1 and a value of mode MODE2.
566 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
567 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
568 MODE2)' must be zero. */
570 /* Tie QI/HI/SI modes together. */
571 #define MODES_TIEABLE_P(MODE1, MODE2) \
572 (GET_MODE_CLASS (MODE1) == MODE_INT \
573 && GET_MODE_CLASS (MODE2) == MODE_INT \
574 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
575 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
577 /* Internal macros to classify a register number as to whether it's a
578 general purpose register for compact insns (r0-r3,r12-r15), or
579 stack pointer (r28). */
581 #define COMPACT_GP_REG_P(REGNO) \
582 (((signed)(REGNO) >= 0 && (REGNO) <= 3) || ((REGNO) >= 12 && (REGNO) <= 15))
583 #define SP_REG_P(REGNO) ((REGNO) == 28)
587 /* Register classes and constants. */
589 /* Define the classes of registers for register constraints in the
590 machine description. Also define ranges of constants.
592 One of the classes must always be named ALL_REGS and include all hard regs.
593 If there is more than one class, another class must be named NO_REGS
594 and contain no registers.
596 The name GENERAL_REGS must be the name of a class (or an alias for
597 another name such as ALL_REGS). This is the class of registers
598 that is allowed by "g" or "r" in a register constraint.
599 Also, registers outside this class are allocated only when
600 instructions express preferences for them.
602 The classes must be numbered in nondecreasing order; that is,
603 a larger-numbered class must never be contained completely
604 in a smaller-numbered class.
606 For any two classes, it is very desirable that there be another
607 class that represents their union.
609 It is important that any condition codes have class NO_REGS.
610 See `register_operand'. */
612 enum reg_class
613 {
614 NO_REGS,
632 ALL_REGS,
633 LIM_REG_CLASSES
634 };
636 #define N_REG_CLASSES (int) LIM_REG_CLASSES
638 /* Give names of register classes as strings for dump file. */
639 #define REG_CLASS_NAMES \
640 { \
660 }
662 /* Define which registers fit in which classes.
663 This is an initializer for a vector of HARD_REG_SET
664 of length N_REG_CLASSES. */
666 #define REG_CLASS_CONTENTS \
667 { \
670 {0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rgp', Global Pointer, r26 */ \
673 {0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000}, /* 'l', LPCOUNT Register, r60 */ \
674 {0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'k', LINK Registers, r29-r31 */ \
677 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'V', DI0-7,DO0-7 Registers */ \
681 {0x9fffffff, 0xc0000000, 0x00000000, 0x00000000, 0x00000000}, /* 'r', r0-r28, blink, ap and pcl */ \
683 /* Include ap / pcl in WRITABLE_CORE_REGS for sake of symmetry. As these \
684 registers are fixed, it does not affect the literal meaning of the \
685 constraints, but it makes it a superset of GENERAL_REGS, thus \
691 }
693 /* Local macros to mark the first and last regs of different classes. */
694 #define ARC_FIRST_SIMD_VR_REG 64
695 #define ARC_LAST_SIMD_VR_REG 127
697 #define ARC_FIRST_SIMD_DMA_CONFIG_REG 128
698 #define ARC_FIRST_SIMD_DMA_CONFIG_IN_REG 128
699 #define ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG 136
700 #define ARC_LAST_SIMD_DMA_CONFIG_REG 143
702 /* The same information, inverted:
703 Return the class number of the smallest class containing
704 reg number REGNO. This could be a conditional expression
705 or could index an array. */
709 #define REGNO_REG_CLASS(REGNO) (arc_regno_reg_class[REGNO])
711 /* The class value for valid index registers. An index register is
712 one used in an address where its value is either multiplied by
713 a scale factor or added to another register (as well as added to a
714 displacement). */
716 #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS)
718 /* The class value for valid base registers. A base register is one used in
719 an address which is the register value plus a displacement. */
721 #define BASE_REG_CLASS (TARGET_MIXED_CODE ? AC16_BASE_REGS : GENERAL_REGS)
723 /* These assume that REGNO is a hard or pseudo reg number.
724 They give nonzero only if REGNO is a hard reg of the suitable class
725 or a pseudo reg currently allocated to a suitable hard reg.
726 Since they use reg_renumber, they are safe only once reg_renumber
727 has been allocated, which happens in local-alloc.c. */
728 #define REGNO_OK_FOR_BASE_P(REGNO) \
729 ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) ||\
730 (unsigned) reg_renumber[REGNO] < 29)
732 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
734 /* Given an rtx X being reloaded into a reg required to be
735 in class CLASS, return the class of reg to actually use.
736 In general this is just CLASS; but on some machines
737 in some cases it is preferable to use a more restrictive class. */
739 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
740 arc_preferred_reload_class((X), (CLASS))
744 /* Return the maximum number of consecutive registers
745 needed to represent mode MODE in a register of class CLASS. */
747 #define CLASS_MAX_NREGS(CLASS, MODE) \
748 (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \
749 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
751 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200)
752 #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \
753 ((unsigned) (((X) >> (SHIFT)) + 0x100) \
754 < 0x200 - ((unsigned) (OFFSET) >> (SHIFT)))
755 #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000)
756 #define LARGE_INT(X) \
757 (((X) < 0) \
758 ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \
759 : (unsigned HOST_WIDE_INT) (X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
760 #define UNSIGNED_INT3(X) ((unsigned) (X) < 0x8)
761 #define UNSIGNED_INT5(X) ((unsigned) (X) < 0x20)
762 #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40)
763 #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80)
764 #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100)
765 #define IS_ONE(X) ((X) == 1)
766 #define IS_ZERO(X) ((X) == 0)
768 /* Stack layout and stack pointer usage. */
770 /* Define this macro if pushing a word onto the stack moves the stack
771 pointer to a smaller address. */
772 #define STACK_GROWS_DOWNWARD
774 /* Define this if the nominal address of the stack frame
775 is at the high-address end of the local variables;
776 that is, each additional local variable allocated
777 goes at a more negative offset in the frame. */
778 #define FRAME_GROWS_DOWNWARD 1
780 /* Offset within stack frame to start allocating local variables at.
781 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
782 first local allocated. Otherwise, it is the offset to the BEGINNING
783 of the first local allocated. */
784 #define STARTING_FRAME_OFFSET 0
786 /* Offset from the stack pointer register to the first location at which
787 outgoing arguments are placed. */
788 #define STACK_POINTER_OFFSET (0)
790 /* Offset of first parameter from the argument pointer register value. */
791 #define FIRST_PARM_OFFSET(FNDECL) (0)
793 /* A C expression whose value is RTL representing the address in a
794 stack frame where the pointer to the caller's frame is stored.
795 Assume that FRAMEADDR is an RTL expression for the address of the
796 stack frame itself.
798 If you don't define this macro, the default is to return the value
799 of FRAMEADDR--that is, the stack frame address is also the address
800 of the stack word that points to the previous frame. */
801 /* ??? unfinished */
802 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
804 /* A C expression whose value is RTL representing the value of the
805 return address for the frame COUNT steps up from the current frame.
806 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
807 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
808 is defined. */
809 /* The current return address is in r31. The return address of anything
810 farther back is at [%fp,4]. */
812 #define RETURN_ADDR_RTX(COUNT, FRAME) \
813 arc_return_addr_rtx(COUNT,FRAME)
815 /* Register to use for pushing function arguments. */
816 #define STACK_POINTER_REGNUM 28
818 /* Base register for access to local variables of the function. */
819 #define FRAME_POINTER_REGNUM 27
821 /* Base register for access to arguments of the function. This register
822 will be eliminated into either fp or sp. */
823 #define ARG_POINTER_REGNUM 62
825 #define RETURN_ADDR_REGNUM 31
827 /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */
828 /* Register in which static-chain is passed to a function. This must
829 not be a register used by the prologue. */
830 #define STATIC_CHAIN_REGNUM 11
832 /* Function argument passing. */
834 /* If defined, the maximum amount of space required for outgoing
835 arguments will be computed and placed into the variable
836 `crtl->outgoing_args_size'. No space will be pushed
837 onto the stack for each call; instead, the function prologue should
838 increase the stack frame size by this amount. */
839 #define ACCUMULATE_OUTGOING_ARGS 1
841 /* Define a data type for recording info about an argument list
842 during the scan of that argument list. This data type should
843 hold all necessary information about the function itself
844 and about the args processed so far, enough to enable macros
845 such as FUNCTION_ARG to determine where the next arg should go. */
846 #define CUMULATIVE_ARGS int
848 /* Initialize a variable CUM of type CUMULATIVE_ARGS
849 for a call to a function whose data type is FNTYPE.
850 For a library call, FNTYPE is 0. */
851 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
852 ((CUM) = 0)
854 /* The number of registers used for parameter passing. Local to this file. */
855 #define MAX_ARC_PARM_REGS 8
857 /* 1 if N is a possible register number for function argument passing. */
858 #define FUNCTION_ARG_REGNO_P(N) \
859 ((unsigned) (N) < MAX_ARC_PARM_REGS)
861 /* The ROUND_ADVANCE* macros are local to this file. */
862 /* Round SIZE up to a word boundary. */
863 #define ROUND_ADVANCE(SIZE) \
864 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
866 /* Round arg MODE/TYPE up to the next word boundary. */
867 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
868 ((MODE) == BLKmode \
869 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
870 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
872 #define ARC_FUNCTION_ARG_BOUNDARY(MODE,TYPE) PARM_BOUNDARY
873 /* Round CUM up to the necessary point for argument MODE/TYPE. */
874 /* N.B. Vectors have alignment exceeding BIGGEST_ALIGNMENT.
875 ARC_FUNCTION_ARG_BOUNDARY reduces this to no more than 32 bit. */
876 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \
877 ((((CUM) - 1) | (ARC_FUNCTION_ARG_BOUNDARY ((MODE), (TYPE)) - 1)/BITS_PER_WORD)\
878 + 1)
880 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
881 a reg. This includes arguments that have to be passed by reference as the
882 pointer to them is passed in a reg if one is available (and that is what
883 we're given).
884 When passing arguments NAMED is always 1. When receiving arguments NAMED
885 is 1 for each argument except the last in a stdarg/varargs function. In
886 a stdarg function we want to treat the last named arg as named. In a
887 varargs function we want to treat the last named arg (which is
888 `__builtin_va_alist') as unnamed.
889 This macro is only used in this file. */
890 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
891 ((CUM) < MAX_ARC_PARM_REGS)
894 /* Function results. */
896 /* Define how to find the value returned by a library function
897 assuming the value has mode MODE. */
898 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
900 /* 1 if N is a possible register number for a function value
901 as seen by the caller. */
902 /* ??? What about r1 in DI/DF values. */
903 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
905 /* Tell GCC to use RETURN_IN_MEMORY. */
906 #define DEFAULT_PCC_STRUCT_RETURN 0
908 /* Register in which address to store a structure value
909 is passed to a function, or 0 to use `invisible' first argument. */
910 #define STRUCT_VALUE 0
912 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
913 the stack pointer does not matter. The value is tested only in
914 functions that have frame pointers.
915 No definition is equivalent to always zero. */
916 #define EXIT_IGNORE_STACK 0
918 #define EPILOGUE_USES(REGNO) arc_epilogue_uses ((REGNO))
920 /* Definitions for register eliminations.
922 This is an array of structures. Each structure initializes one pair
923 of eliminable registers. The "from" register number is given first,
924 followed by "to". Eliminations of the same "from" register are listed
925 in order of preference.
927 We have two registers that can be eliminated on the ARC. First, the
928 argument pointer register can always be eliminated in favor of the stack
929 pointer register or frame pointer register. Secondly, the frame pointer
930 register can often be eliminated in favor of the stack pointer register.
931 */
933 #define ELIMINABLE_REGS \
934 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
935 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
936 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
938 /* Define the offset between two registers, one to be eliminated, and the other
939 its replacement, at the start of a routine. */
941 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
942 (OFFSET) = arc_initial_elimination_offset ((FROM), (TO))
944 /* Output assembler code to FILE to increment profiler label # LABELNO
945 for profiling a function entry.
946 We actually emit the profiler code at the call site, so leave this one
947 empty. */
948 #define FUNCTION_PROFILER(FILE, LABELNO) \
949 if (TARGET_UCB_MCOUNT) \
952 #define NO_PROFILE_COUNTERS 1
954 /* Trampolines. */
956 /* Length in units of the trampoline for entering a nested function. */
957 #define TRAMPOLINE_SIZE 20
959 /* Alignment required for a trampoline in bits . */
960 /* For actual data alignment we just need 32, no more than the stack;
961 however, to reduce cache coherency issues, we want to make sure that
962 trampoline instructions always appear the same in any given cache line. */
963 #define TRAMPOLINE_ALIGNMENT 256
965 /* Library calls. */
967 /* Addressing modes, and classification of registers for them. */
969 /* Maximum number of registers that can appear in a valid memory address. */
970 /* The `ld' insn allows 2, but the `st' insn only allows 1. */
971 #define MAX_REGS_PER_ADDRESS 1
973 /* We have pre inc/dec (load/store with update). */
974 #define HAVE_PRE_INCREMENT 1
975 #define HAVE_PRE_DECREMENT 1
976 #define HAVE_POST_INCREMENT 1
977 #define HAVE_POST_DECREMENT 1
978 #define HAVE_PRE_MODIFY_DISP 1
979 #define HAVE_POST_MODIFY_DISP 1
980 #define HAVE_PRE_MODIFY_REG 1
981 #define HAVE_POST_MODIFY_REG 1
982 /* ??? should also do PRE_MODIFY_REG / POST_MODIFY_REG, but that requires
983 a special predicate for the memory operand of stores, like for the SH. */
985 /* Recognize any constant value that is a valid address. */
986 #define CONSTANT_ADDRESS_P(X) \
987 (flag_pic?arc_legitimate_pic_addr_p (X): \
988 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
989 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST))
991 /* Is the argument a const_int rtx, containing an exact power of 2 */
992 #define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X))
994 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
995 and check its validity for a certain class.
996 We have two alternate definitions for each of them.
997 The *_NONSTRICT definition accepts all pseudo regs; the other rejects
998 them unless they have been allocated suitable hard regs.
1000 Most source files want to accept pseudo regs in the hope that
1001 they will get allocated to the class that the insn wants them to be in.
1002 Source files for reload pass need to be strict.
1003 After reload, it makes no difference, since pseudo regs have
1004 been eliminated by then. */
1006 /* Nonzero if X is a hard reg that can be used as an index
1007 or if it is a pseudo reg. */
1008 #define REG_OK_FOR_INDEX_P_NONSTRICT(X) \
1009 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER || \
1010 (unsigned) REGNO (X) < 29 || \
1011 (unsigned) REGNO (X) == 63 || \
1012 (unsigned) REGNO (X) == ARG_POINTER_REGNUM)
1013 /* Nonzero if X is a hard reg that can be used as a base reg
1014 or if it is a pseudo reg. */
1015 #define REG_OK_FOR_BASE_P_NONSTRICT(X) \
1016 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER || \
1017 (unsigned) REGNO (X) < 29 || \
1018 (unsigned) REGNO (X) == 63 || \
1019 (unsigned) REGNO (X) == ARG_POINTER_REGNUM)
1021 /* Nonzero if X is a hard reg that can be used as an index. */
1022 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1023 /* Nonzero if X is a hard reg that can be used as a base reg. */
1024 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1026 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1027 that is a valid memory address for an instruction.
1028 The MODE argument is the machine mode for the MEM expression
1029 that wants to use this address. */
1030 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm]
1031 but the `st' insn only allows [reg],[reg+shimm],[limm].
1032 The only thing we can do is only allow the most strict case `st' and hope
1033 other parts optimize out the restrictions for `ld'. */
1035 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1036 (REG_P (X) \
1037 && ((STRICT) ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P_NONSTRICT (X)))
1039 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1040 (REG_P (X) \
1041 && ((STRICT) ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P_NONSTRICT (X)))
1043 /* A C compound statement that attempts to replace X, which is an address
1044 that needs reloading, with a valid memory address for an operand of
1045 mode MODE. WIN is a C statement label elsewhere in the code.
1047 We try to get a normal form
1048 of the address. That will allow inheritance of the address reloads. */
1050 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1051 do { \
1052 if (arc_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1053 goto WIN; \
1054 } while (0)
1056 /* Reading lp_count for anything but the lp instruction is very slow on the
1057 ARC700. */
1058 #define DONT_REALLOC(REGNO,MODE) \
1059 (TARGET_ARC700 && (REGNO) == 60)
1062 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1063 return the mode to be used for the comparison. */
1064 /*extern enum machine_mode arc_select_cc_mode ();*/
1065 #define SELECT_CC_MODE(OP, X, Y) \
1066 arc_select_cc_mode (OP, X, Y)
1068 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
1069 floating point inequality comparison. */
1072 /* Costs. */
1074 /* Compute extra cost of moving data between one register class
1075 and another. */
1076 #define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \
1077 arc_register_move_cost ((MODE), (CLASS), (TO_CLASS))
1079 /* Compute the cost of moving data between registers and memory. */
1080 /* Memory is 3 times as expensive as registers.
1081 ??? Is that the right way to look at it? */
1082 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1083 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1085 /* The cost of a branch insn. */
1086 /* ??? What's the right value here? Branches are certainly more
1087 expensive than reg->reg moves. */
1088 #define BRANCH_COST(speed_p, predictable_p) 2
1090 /* Nonzero if access to memory by bytes is slow and undesirable.
1091 For RISC chips, it means that access to memory by bytes is no
1092 better than access by words when possible, so grab a whole word
1093 and maybe make use of that. */
1094 #define SLOW_BYTE_ACCESS 0
1096 /* Define this macro if it is as good or better to call a constant
1097 function address than to call an address kept in a register. */
1098 /* On the ARC, calling through registers is slow. */
1099 #define NO_FUNCTION_CSE
1101 /* Section selection. */
1102 /* WARNING: These section names also appear in dwarfout.c. */
1111 /* Expression whose value is a string, including spacing, containing the
1112 assembler operation to identify the following data as initialization/termination
1113 code. If not defined, GCC will assume such a section does not exist. */
1117 /* Define this macro if jump tables (for tablejump insns) should be
1118 output in the text section, along with the assembler instructions.
1119 Otherwise, the readonly data section is used.
1120 This macro is irrelevant if there is no separate readonly data section. */
1121 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic || CASE_VECTOR_PC_RELATIVE)
1123 /* For DWARF. Marginally different than default so output is "prettier"
1124 (and consistent with above). */
1127 /* Tell crtstuff.c we're using ELF. */
1128 #define OBJECT_FORMAT_ELF
1130 /* PIC */
1132 /* The register number of the register used to address a table of static
1133 data addresses in memory. In some cases this register is defined by a
1134 processor's ``application binary interface'' (ABI). When this macro
1135 is defined, RTL is generated for this register once, as with the stack
1136 pointer and frame pointer registers. If this macro is not defined, it
1137 is up to the machine-dependent files to allocate such a register (if
1138 necessary). */
1139 #define PIC_OFFSET_TABLE_REGNUM 26
1141 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1142 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1143 is not defined. */
1144 /* This register is call-saved on the ARC. */
1145 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1147 /* A C expression that is nonzero if X is a legitimate immediate
1148 operand on the target machine when generating position independent code.
1149 You can assume that X satisfies CONSTANT_P, so you need not
1150 check this. You can also assume `flag_pic' is true, so you need not
1151 check it either. You need not define this macro if all constants
1152 (including SYMBOL_REF) can be immediate operands when generating
1153 position independent code. */
1154 #define LEGITIMATE_PIC_OPERAND_P(X) (arc_legitimate_pic_operand_p(X))
1156 /* PIC and small data don't mix on ARC because they use the same register. */
1157 #define SDATA_BASE_REGNUM 26
1159 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1160 (flag_pic \
1161 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1162 : DW_EH_PE_absptr)
1164 /* Control the assembler format that we output. */
1166 /* A C string constant describing how to begin a comment in the target
1167 assembler language. The compiler assumes that the comment will
1168 end at the end of the line. */
1169 /* Gas needs this to be "#" in order to recognize line directives. */
1172 /* Output to assembler file text saying following lines
1173 may contain character constants, extra white space, comments, etc. */
1176 /* Output to assembler file text saying following lines
1177 no longer contain unusual constructs. */
1180 /* Globalizing directive for a label. */
1183 /* This is how to output an assembler line defining a `char' constant. */
1184 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
1186 output_addr_const (FILE, (VALUE)), \
1189 /* This is how to output an assembler line defining a `short' constant. */
1190 #define ASM_OUTPUT_SHORT(FILE, VALUE) \
1192 output_addr_const (FILE, (VALUE)), \
1195 /* This is how to output an assembler line defining an `int' constant.
1196 We also handle symbol output here. Code addresses must be right shifted
1197 by 2 because that's how the jump instruction wants them. */
1198 #define ASM_OUTPUT_INT(FILE, VALUE) \
1199 do { \
1201 if (GET_CODE (VALUE) == LABEL_REF) \
1202 { \
1204 output_addr_const (FILE, (VALUE)); \
1206 } \
1207 else \
1208 output_addr_const (FILE, (VALUE)); \
1210 } while (0)
1212 /* This is how to output an assembler line defining a `float' constant. */
1213 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
1214 { \
1215 long t; \
1216 char str[30]; \
1217 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1220 t, ASM_COMMENT_START, str); \
1221 }
1223 /* This is how to output an assembler line defining a `double' constant. */
1224 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
1225 { \
1226 long t[2]; \
1227 char str[30]; \
1228 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1231 t[0], ASM_COMMENT_START, str, t[1]); \
1232 }
1234 /* This is how to output the definition of a user-level label named NAME,
1235 such as the label on a static function or variable NAME. */
1236 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1241 /* This is how to output a reference to a user-level label named NAME.
1242 `assemble_name' uses this. */
1243 /* We work around a dwarfout.c deficiency by watching for labels from it and
1244 not adding the '_' prefix. There is a comment in
1245 dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL. */
1246 #define ASM_OUTPUT_LABELREF(FILE, NAME1) \
1247 do { \
1248 const char *NAME; \
1249 NAME = (*targetm.strip_name_encoding)(NAME1); \
1252 else \
1253 { \
1254 if (!ASM_NAME_P (NAME1)) \
1257 } \
1258 } while (0)
1260 /* This is how to output a reference to a symbol_ref / label_ref as
1261 (part of) an operand. To disambiguate from register names like
1262 a1 / a2 / status etc, symbols are preceded by '@'. */
1263 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
1264 ASM_OUTPUT_LABEL_REF ((FILE), XSTR ((SYM), 0))
1265 #define ASM_OUTPUT_LABEL_REF(FILE,STR) \
1266 do \
1267 { \
1269 assemble_name ((FILE), (STR)); \
1270 } \
1271 while (0)
1273 /* Store in OUTPUT a string (made with alloca) containing
1274 an assembler-name for a local static variable named NAME.
1275 LABELNO is an integer which is different for each call. */
1276 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1277 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1280 /* The following macro defines the format used to output the second
1281 operand of the .type assembler directive. Different svr4 assemblers
1282 expect various different forms for this operand. The one given here
1283 is just a default. You may need to override it in your machine-
1284 specific tm.h file (depending upon the particulars of your assembler). */
1286 #undef TYPE_OPERAND_FMT
1289 /* A C string containing the appropriate assembler directive to
1290 specify the size of a symbol, without any arguments. On systems
1291 that use ELF, the default (in `config/elfos.h') is `"\t.size\t"';
1292 on other systems, the default is not to define this macro. */
1293 #undef SIZE_ASM_OP
1296 /* Assembler pseudo-op to equate one value with another. */
1297 /* ??? This is needed because dwarfout.c provides a default definition too
1298 late for defaults.h (which contains the default definition of ASM_OTPUT_DEF
1299 that we use). */
1300 #ifdef SET_ASM_OP
1301 #undef SET_ASM_OP
1302 #endif
1306 /* How to refer to registers in assembler output.
1307 This sequence is indexed by compiler's hard-register-number (see above). */
1308 #define REGISTER_NAMES \
1328 }
1330 /* Entry to the insn conditionalizer. */
1331 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1332 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS)
1334 /* A C expression which evaluates to true if CODE is a valid
1335 punctuation character for use in the `PRINT_OPERAND' macro. */
1337 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1338 arc_punct_chars[(unsigned char) (CHAR)]
1340 /* Print operand X (an rtx) in assembler syntax to file FILE.
1341 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1342 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1343 #define PRINT_OPERAND(FILE, X, CODE) \
1344 arc_print_operand (FILE, X, CODE)
1346 /* A C compound statement to output to stdio stream STREAM the
1347 assembler syntax for an instruction operand that is a memory
1348 reference whose address is ADDR. ADDR is an RTL expression.
1350 On some machines, the syntax for a symbolic address depends on
1351 the section that the address refers to. On these machines,
1352 define the macro `ENCODE_SECTION_INFO' to store the information
1353 into the `symbol_ref', and then check for it here. */
1354 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1355 arc_print_operand_address (FILE, ADDR)
1357 /* This is how to output an element of a case-vector that is absolute. */
1358 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1359 do { \
1360 char label[30]; \
1363 assemble_name (FILE, label); \
1365 } while (0)
1367 /* This is how to output an element of a case-vector that is relative. */
1368 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1369 do { \
1370 char label[30]; \
1372 switch (GET_MODE (BODY)) \
1373 { \
1377 default: gcc_unreachable (); \
1378 } \
1379 assemble_name (FILE, label); \
1382 assemble_name (FILE, label); \
1383 if (TARGET_COMPACT_CASESI) \
1386 } while (0)
1388 /* ADDR_DIFF_VECs are in the text section and thus can affect the
1389 current alignment. */
1390 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
1391 do \
1392 { \
1393 if (GET_CODE (PATTERN (JUMPTABLE)) == ADDR_DIFF_VEC \
1394 && ((GET_MODE_SIZE (GET_MODE (PATTERN (JUMPTABLE))) \
1395 * XVECLEN (PATTERN (JUMPTABLE), 1) + 1) \
1396 & 2)) \
1397 arc_toggle_unalign (); \
1398 } \
1399 while (0)
1401 #define JUMP_ALIGN(LABEL) (arc_size_opt_level < 2 ? 2 : 0)
1402 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
1403 (JUMP_ALIGN(LABEL) \
1404 ? JUMP_ALIGN(LABEL) \
1405 : GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
1406 ? 1 : 0)
1407 /* The desired alignment for the location counter at the beginning
1408 of a loop. */
1409 /* On the ARC, align loops to 4 byte boundaries unless doing all-out size
1410 optimization. */
1411 #define LOOP_ALIGN JUMP_ALIGN
1413 #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL))
1415 /* This is how to output an assembler line
1416 that says to advance the location counter
1417 to a multiple of 2**LOG bytes. */
1418 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1419 do { \
1421 if ((LOG) > 1) \
1422 arc_clear_unalign (); \
1423 } while (0)
1425 /* ASM_OUTPUT_ALIGNED_DECL_LOCAL (STREAM, DECL, NAME, SIZE, ALIGNMENT)
1426 Define this macro when you need to see the variable's decl in order to
1427 chose what to output. */
1428 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
1429 arc_asm_output_aligned_decl_local (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
1431 /* To translate the return value of arc_function_type into a register number
1432 to jump through for function return. */
1435 /* Debugging information. */
1437 /* Generate DBX and DWARF debugging information. */
1438 #ifdef DBX_DEBUGGING_INFO
1439 #undef DBX_DEBUGGING_INFO
1440 #endif
1441 #define DBX_DEBUGGING_INFO
1443 #ifdef DWARF2_DEBUGGING_INFO
1444 #undef DWARF2_DEBUGGING_INFO
1445 #endif
1446 #define DWARF2_DEBUGGING_INFO
1448 /* Prefer STABS (for now). */
1449 #undef PREFERRED_DEBUGGING_TYPE
1450 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1452 /* How to renumber registers for dbx and gdb. */
1453 #define DBX_REGISTER_NUMBER(REGNO) \
1454 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \
1455 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \
1456 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 59) \
1457 ? ((REGNO) == 57 \
1459 : ((REGNO) & 1) ^ TARGET_BIG_ENDIAN \
1462 : (REGNO))
1464 #define DWARF_FRAME_REGNUM(REG) (REG)
1466 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31)
1468 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31)
1470 /* Frame info. */
1472 /* Define this macro to 0 if your target supports DWARF 2 frame unwind
1473 information, but it does not yet work with exception handling. */
1474 /* N.B. the below test is valid in an #if, but not in a C expression. */
1475 #if DEFAULT_LIBC == LIBC_UCLIBC
1476 #define DWARF2_UNWIND_INFO 1
1477 #else
1478 #define DWARF2_UNWIND_INFO 0
1479 #endif
1481 #define EH_RETURN_DATA_REGNO(N) \
1482 ((N) < 4 ? (N) : INVALID_REGNUM)
1484 /* Turn off splitting of long stabs. */
1485 #define DBX_CONTIN_LENGTH 0
1487 /* Miscellaneous. */
1489 /* Specify the machine mode that this machine uses
1490 for the index in the tablejump instruction.
1491 If we have pc relative case vectors, we start the case vector shortening
1492 with QImode. */
1493 #define CASE_VECTOR_MODE \
1494 ((optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode)
1496 /* Define as C expression which evaluates to nonzero if the tablejump
1497 instruction expects the table to contain offsets from the address of the
1498 table.
1499 Do not define this if the table should contain absolute addresses. */
1500 #define CASE_VECTOR_PC_RELATIVE TARGET_CASE_VECTOR_PC_RELATIVE
1502 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1503 CASE_VECTOR_SHORTEN_MODE_1 \
1504 (MIN_OFFSET, TARGET_COMPACT_CASESI ? MAX_OFFSET + 6 : MAX_OFFSET, BODY)
1506 #define CASE_VECTOR_SHORTEN_MODE_1(MIN_OFFSET, MAX_OFFSET, BODY) \
1507 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1508 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1509 : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \
1510 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1511 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \
1512 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \
1513 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \
1514 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \
1515 : SImode)
1517 #define ADDR_VEC_ALIGN(VEC_INSN) \
1518 (exact_log2 (GET_MODE_SIZE (GET_MODE (PATTERN (VEC_INSN)))))
1519 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
1520 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \
1521 ASM_OUTPUT_ALIGN ((FILE), ADDR_VEC_ALIGN (TABLE));
1523 #define INSN_LENGTH_ALIGNMENT(INSN) \
1524 ((JUMP_P (INSN) \
1525 && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \
1526 && GET_MODE (PATTERN (INSN)) == QImode) \
1527 ? 0 : length_unit_log)
1529 /* Define if operations between registers always perform the operation
1530 on the full register even if a narrower mode is specified. */
1531 #define WORD_REGISTER_OPERATIONS
1533 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1534 will either zero-extend or sign-extend. The value of this macro should
1535 be the code that says which one of the two operations is implicitly
1536 done, NIL if none. */
1537 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1540 /* Max number of bytes we can move from memory to memory
1541 in one reasonably fast instruction. */
1542 #define MOVE_MAX 4
1544 /* Let the movmem expander handle small block moves. */
1545 #define MOVE_BY_PIECES_P(LEN, ALIGN) 0
1546 #define CAN_MOVE_BY_PIECES(SIZE, ALIGN) \
1547 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1548 < (unsigned int) MOVE_RATIO (!optimize_size))
1550 /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P . */
1551 #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3)
1553 /* Define this to be nonzero if shift instructions ignore all but the low-order
1554 few bits. Changed from 1 to 0 for rotate pattern testcases
1555 (e.g. 20020226-1.c). This change truncates the upper 27 bits of a word
1556 while rotating a word. Came to notice through a combine phase
1557 optimization viz. a << (32-b) is equivalent to a << (-b).
1558 */
1559 #define SHIFT_COUNT_TRUNCATED 0
1561 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1562 is done just by pretending it is already truncated. */
1563 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1565 /* We assume that the store-condition-codes instructions store 0 for false
1566 and some other value for true. This is the value stored for true. */
1567 #define STORE_FLAG_VALUE 1
1569 /* Specify the machine mode that pointers have.
1570 After generation of rtl, the compiler makes no further distinction
1571 between pointers and any other objects of this machine mode. */
1572 /* ARCompact has full 32-bit pointers. */
1573 #define Pmode SImode
1575 /* A function address in a call instruction. */
1576 #define FUNCTION_MODE SImode
1578 /* Define the information needed to generate branch and scc insns. This is
1579 stored from the compare operation. Note that we can't use "rtx" here
1580 since it hasn't been defined! */
1583 /* ARC function types. */
1586 /* These are interrupt handlers. The name corresponds to the register
1587 name that contains the return address. */
1588 ARC_FUNCTION_ILINK1, ARC_FUNCTION_ILINK2
1589 };
1590 #define ARC_INTERRUPT_P(TYPE) \
1591 ((TYPE) == ARC_FUNCTION_ILINK1 || (TYPE) == ARC_FUNCTION_ILINK2)
1593 /* Compute the type of a function from its DECL. Needed for EPILOGUE_USES. */
1597 /* Called by crtstuff.c to make calls to function FUNCTION that are defined in
1598 SECTION_OP, and then to switch back to text section. */
1599 #undef CRT_CALL_STATIC_FUNCTION
1600 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1603 TEXT_SECTION_ASM_OP);
1605 /* This macro expands to the name of the scratch register r12, used for
1606 temporary calculations according to the ABI. */
1609 /* The C++ compiler must use one bit to indicate whether the function
1610 that will be called through a pointer-to-member-function is
1611 virtual. Normally, we assume that the low-order bit of a function
1612 pointer must always be zero. Then, by ensuring that the
1613 vtable_index is odd, we can distinguish which variant of the union
1614 is in use. But, on some platforms function pointers can be odd,
1615 and so this doesn't work. In that case, we use the low-order bit
1616 of the `delta' field, and shift the remainder of the `delta' field
1617 to the left. We needed to do this for A4 because the address was always
1618 shifted and thus could be odd. */
1619 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
1620 (ptrmemfunc_vbit_in_pfn)
1622 #define INSN_SETS_ARE_DELAYED(X) \
1623 (GET_CODE (X) == INSN \
1624 && GET_CODE (PATTERN (X)) != SEQUENCE \
1625 && GET_CODE (PATTERN (X)) != USE \
1626 && GET_CODE (PATTERN (X)) != CLOBBER \
1627 && (get_attr_type (X) == TYPE_CALL || get_attr_type (X) == TYPE_SFUNC))
1629 #define INSN_REFERENCES_ARE_DELAYED(insn) INSN_SETS_ARE_DELAYED (insn)
1631 #define CALL_ATTR(X, NAME) \
1632 ((CALL_P (X) || NONJUMP_INSN_P (X)) \
1633 && GET_CODE (PATTERN (X)) != USE \
1634 && GET_CODE (PATTERN (X)) != CLOBBER \
1635 && get_attr_is_##NAME (X) == IS_##NAME##_YES) \
1637 #define REVERSE_CONDITION(CODE,MODE) \
1638 (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \
1639 || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \
1640 || (MODE) == CC_FPXmode) \
1641 ? reverse_condition_maybe_unordered ((CODE)) \
1642 : reverse_condition ((CODE)))
1644 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1645 ((LENGTH) \
1646 = (GET_CODE (PATTERN (X)) == SEQUENCE \
1647 ? ((LENGTH) \
1648 + arc_adjust_insn_length (XVECEXP (PATTERN (X), 0, 0), \
1649 get_attr_length (XVECEXP (PATTERN (X), \
1650 0, 0)), \
1651 true) \
1652 - get_attr_length (XVECEXP (PATTERN (X), 0, 0)) \
1653 + arc_adjust_insn_length (XVECEXP (PATTERN (X), 0, 1), \
1654 get_attr_length (XVECEXP (PATTERN (X), \
1655 0, 1)), \
1656 true) \
1657 - get_attr_length (XVECEXP (PATTERN (X), 0, 1))) \
1658 : arc_adjust_insn_length ((X), (LENGTH), false)))
1662 #define INIT_EXPANDERS arc_init_expanders ()
1664 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-arc_decl_pretend_args ((FUNDECL)))
1666 #define ARG_POINTER_CFA_OFFSET(FNDECL) \
1667 (FIRST_PARM_OFFSET (FNDECL) + arc_decl_pretend_args ((FNDECL)))
1669 enum
1670 {
1672 };
1674 /* The define_cond_exec construct is rather crude, as we can't have
1675 different ones with different conditions apply to different sets
1676 of instructions. We can't use an attribute test inside the condition,
1677 because that would lead to infinite recursion as the attribute test
1678 needs to recognize the insn. So, instead we have a clause for
1679 the pattern condition of all sfunc patterns which is only relevant for
1680 the predicated varaint. */
1681 #define SFUNC_CHECK_PREDICABLE \
1682 (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS)