1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
297 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
307 /* Return true if REGNO satisfies a memory constraint. */
311 return get_reg_class (regno
) == NO_REGS
;
314 /* If we have decided to substitute X with another value, return that
315 value, otherwise return X. */
317 get_equiv_substitution (rtx x
)
322 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
323 || ! ira_reg_equiv
[regno
].defined_p
324 || ! ira_reg_equiv
[regno
].profitable_p
325 || lra_get_regno_hard_regno (regno
) >= 0)
327 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
331 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
336 /* Set up curr_operand_mode. */
338 init_curr_operand_mode (void)
340 int nop
= curr_static_id
->n_operands
;
341 for (int i
= 0; i
< nop
; i
++)
343 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
344 if (mode
== VOIDmode
)
346 /* The .md mode for address operands is the mode of the
347 addressed value rather than the mode of the address itself. */
348 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
351 mode
= curr_static_id
->operand
[i
].mode
;
353 curr_operand_mode
[i
] = mode
;
359 /* The page contains code to reuse input reloads. */
361 /* Structure describes input reload of the current insns. */
364 /* Reloaded value. */
366 /* Reload pseudo used. */
370 /* The number of elements in the following array. */
371 static int curr_insn_input_reloads_num
;
372 /* Array containing info about input reloads. It is used to find the
373 same input reload and reuse the reload pseudo in this case. */
374 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
376 /* Initiate data concerning reuse of input reloads for the current
379 init_curr_insn_input_reloads (void)
381 curr_insn_input_reloads_num
= 0;
384 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
385 using TITLE. Output a new line if NL_P. */
387 change_class (int regno
, enum reg_class new_class
,
388 const char *title
, bool nl_p
)
390 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
391 if (lra_dump_file
!= NULL
)
392 fprintf (lra_dump_file
, "%s to class %s for r%d",
393 title
, reg_class_names
[new_class
], regno
);
394 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
395 if (lra_dump_file
!= NULL
&& nl_p
)
396 fprintf (lra_dump_file
, "\n");
399 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
400 created input reload pseudo (only if TYPE is not OP_OUT). The
401 result pseudo is returned through RESULT_REG. Return TRUE if we
402 created a new pseudo, FALSE if we reused the already created input
403 reload pseudo. Use TITLE to describe new registers for debug
406 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
407 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
410 enum reg_class new_class
;
415 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
418 /* Prevent reuse value of expression with side effects,
419 e.g. volatile memory. */
420 if (! side_effects_p (original
))
421 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
422 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
423 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
425 rtx reg
= curr_insn_input_reloads
[i
].reg
;
427 /* If input is equal to original and both are VOIDmode,
428 GET_MODE (reg) might be still different from mode.
429 Ensure we don't return *result_reg with wrong mode. */
430 if (GET_MODE (reg
) != mode
)
432 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
434 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
435 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
439 if (lra_dump_file
!= NULL
)
441 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
442 dump_value_slim (lra_dump_file
, original
, 1);
444 if (new_class
!= lra_get_allocno_class (regno
))
445 change_class (regno
, new_class
, ", change", false);
446 if (lra_dump_file
!= NULL
)
447 fprintf (lra_dump_file
, "\n");
450 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
451 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
452 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
453 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
459 /* The page contains code to extract memory address parts. */
461 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
463 ok_for_index_p_nonstrict (rtx reg
)
465 unsigned regno
= REGNO (reg
);
467 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
470 /* A version of regno_ok_for_base_p for use here, when all pseudos
471 should count as OK. Arguments as for regno_ok_for_base_p. */
473 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
474 enum rtx_code outer_code
, enum rtx_code index_code
)
476 unsigned regno
= REGNO (reg
);
478 if (regno
>= FIRST_PSEUDO_REGISTER
)
480 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
485 /* The page contains major code to choose the current insn alternative
486 and generate reloads for it. */
488 /* Return the offset from REGNO of the least significant register
491 This function is used to tell whether two registers satisfy
492 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
494 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
495 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
497 lra_constraint_offset (int regno
, enum machine_mode mode
)
499 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
500 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
501 && SCALAR_INT_MODE_P (mode
))
502 return hard_regno_nregs
[regno
][mode
] - 1;
506 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
507 if they are the same hard reg, and has special hacks for
508 auto-increment and auto-decrement. This is specifically intended for
509 process_alt_operands to use in determining whether two operands
510 match. X is the operand whose number is the lower of the two.
512 It is supposed that X is the output operand and Y is the input
513 operand. Y_HARD_REGNO is the final hard regno of register Y or
514 register in subreg Y as we know it now. Otherwise, it is a
517 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
520 RTX_CODE code
= GET_CODE (x
);
525 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
526 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
530 i
= get_hard_regno (x
);
534 if ((j
= y_hard_regno
) < 0)
537 i
+= lra_constraint_offset (i
, GET_MODE (x
));
538 j
+= lra_constraint_offset (j
, GET_MODE (y
));
543 /* If two operands must match, because they are really a single
544 operand of an assembler insn, then two post-increments are invalid
545 because the assembler insn would increment only once. On the
546 other hand, a post-increment matches ordinary indexing if the
547 post-increment is the output operand. */
548 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
549 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
551 /* Two pre-increments are invalid because the assembler insn would
552 increment only once. On the other hand, a pre-increment matches
553 ordinary indexing if the pre-increment is the input operand. */
554 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
555 || GET_CODE (y
) == PRE_MODIFY
)
556 return operands_match_p (x
, XEXP (y
, 0), -1);
560 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
561 && x
== SUBREG_REG (y
))
563 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
564 && SUBREG_REG (x
) == y
)
567 /* Now we have disposed of all the cases in which different rtx
569 if (code
!= GET_CODE (y
))
572 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
573 if (GET_MODE (x
) != GET_MODE (y
))
582 return XEXP (x
, 0) == XEXP (y
, 0);
584 return XSTR (x
, 0) == XSTR (y
, 0);
590 /* Compare the elements. If any pair of corresponding elements fail
591 to match, return false for the whole things. */
593 fmt
= GET_RTX_FORMAT (code
);
594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
600 if (XWINT (x
, i
) != XWINT (y
, i
))
605 if (XINT (x
, i
) != XINT (y
, i
))
610 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
619 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
623 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
629 /* It is believed that rtx's at this level will never
630 contain anything but integers and other rtx's, except for
631 within LABEL_REFs and SYMBOL_REFs. */
639 /* True if X is a constant that can be forced into the constant pool.
640 MODE is the mode of the operand, or VOIDmode if not known. */
641 #define CONST_POOL_OK_P(MODE, X) \
642 ((MODE) != VOIDmode \
644 && GET_CODE (X) != HIGH \
645 && !targetm.cannot_force_const_mem (MODE, X))
647 /* True if C is a non-empty register class that has too few registers
648 to be safely used as a reload target class. */
649 #define SMALL_REGISTER_CLASS_P(C) \
650 (reg_class_size [(C)] == 1 \
651 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
653 /* If REG is a reload pseudo, try to make its class satisfying CL. */
655 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
657 enum reg_class rclass
;
659 /* Do not make more accurate class from reloads generated. They are
660 mostly moves with a lot of constraints. Making more accurate
661 class may results in very narrow class and impossibility of find
662 registers for several reloads of one insn. */
663 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
665 if (GET_CODE (reg
) == SUBREG
)
666 reg
= SUBREG_REG (reg
);
667 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
669 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
670 change_class (REGNO (reg
), rclass
, " Change", true);
673 /* Generate reloads for matching OUT and INS (array of input operand
674 numbers with end marker -1) with reg class GOAL_CLASS. Add input
675 and output reloads correspondingly to the lists *BEFORE and *AFTER.
676 OUT might be negative. In this case we generate input reloads for
677 matched input operands INS. */
679 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
680 rtx
*before
, rtx
*after
)
683 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
684 enum machine_mode inmode
, outmode
;
685 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
686 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
688 inmode
= curr_operand_mode
[ins
[0]];
689 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
690 push_to_sequence (*before
);
691 if (inmode
!= outmode
)
693 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
696 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
698 if (SCALAR_INT_MODE_P (inmode
))
699 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
701 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
702 LRA_SUBREG_P (new_out_reg
) = 1;
703 /* If the input reg is dying here, we can use the same hard
704 register for REG and IN_RTX. We do it only for original
705 pseudos as reload pseudos can die although original
706 pseudos still live where reload pseudos dies. */
707 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
708 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
709 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
714 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
716 if (SCALAR_INT_MODE_P (outmode
))
717 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
719 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
720 /* NEW_IN_REG is non-paradoxical subreg. We don't want
721 NEW_OUT_REG living above. We add clobber clause for
722 this. This is just a temporary clobber. We can remove
723 it at the end of LRA work. */
724 clobber
= emit_clobber (new_out_reg
);
725 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
726 LRA_SUBREG_P (new_in_reg
) = 1;
727 if (GET_CODE (in_rtx
) == SUBREG
)
729 rtx subreg_reg
= SUBREG_REG (in_rtx
);
731 /* If SUBREG_REG is dying here and sub-registers IN_RTX
732 and NEW_IN_REG are similar, we can use the same hard
733 register for REG and SUBREG_REG. */
734 if (REG_P (subreg_reg
)
735 && (int) REGNO (subreg_reg
) < lra_new_regno_start
736 && GET_MODE (subreg_reg
) == outmode
737 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
738 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
739 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
745 /* Pseudos have values -- see comments for lra_reg_info.
746 Different pseudos with the same value do not conflict even if
747 they live in the same place. When we create a pseudo we
748 assign value of original pseudo (if any) from which we
749 created the new pseudo. If we create the pseudo from the
750 input pseudo, the new pseudo will no conflict with the input
751 pseudo which is wrong when the input pseudo lives after the
752 insn and as the new pseudo value is changed by the insn
753 output. Therefore we create the new pseudo from the output.
755 We cannot reuse the current output register because we might
756 have a situation like "a <- a op b", where the constraints
757 force the second input operand ("b") to match the output
758 operand ("a"). "b" must then be copied into a new register
759 so that it doesn't clobber the current value of "a". */
761 new_in_reg
= new_out_reg
762 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
765 /* In operand can be got from transformations before processing insn
766 constraints. One example of such transformations is subreg
767 reloading (see function simplify_operand_subreg). The new
768 pseudos created by the transformations might have inaccurate
769 class (ALL_REGS) and we should make their classes more
771 narrow_reload_pseudo_class (in_rtx
, goal_class
);
772 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
773 *before
= get_insns ();
775 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
778 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
779 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
780 *curr_id
->operand_loc
[in
] = new_in_reg
;
782 lra_update_dups (curr_id
, ins
);
785 /* See a comment for the input operand above. */
786 narrow_reload_pseudo_class (out_rtx
, goal_class
);
787 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
790 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
792 *after
= get_insns ();
795 *curr_id
->operand_loc
[out
] = new_out_reg
;
796 lra_update_dup (curr_id
, out
);
799 /* Return register class which is union of all reg classes in insn
800 constraint alternative string starting with P. */
801 static enum reg_class
802 reg_class_from_constraints (const char *p
)
805 enum reg_class op_class
= NO_REGS
;
808 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
815 op_class
= (reg_class_subunion
816 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
822 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
826 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
828 #ifdef EXTRA_CONSTRAINT_STR
829 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
831 = (reg_class_subunion
832 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
839 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
842 while ((p
+= len
), c
);
846 /* If OP is a register, return the class of the register as per
847 get_reg_class, otherwise return NO_REGS. */
848 static inline enum reg_class
849 get_op_class (rtx op
)
851 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
854 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
855 otherwise. If modes of MEM_PSEUDO and VAL are different, use
856 SUBREG for VAL to make them equal. */
858 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
860 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
862 lra_assert (GET_MODE_SIZE (GET_MODE (mem_pseudo
))
863 >= GET_MODE_SIZE (GET_MODE (val
)));
866 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
867 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
869 LRA_SUBREG_P (val
) = 1;
873 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
874 LRA_SUBREG_P (mem_pseudo
) = 1;
878 ? gen_move_insn (mem_pseudo
, val
)
879 : gen_move_insn (val
, mem_pseudo
));
882 /* Process a special case insn (register move), return true if we
883 don't need to process it anymore. INSN should be a single set
884 insn. Set up that RTL was changed through CHANGE_P and macro
885 SECONDARY_MEMORY_NEEDED says to use secondary memory through
888 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
891 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
892 enum reg_class dclass
, sclass
, secondary_class
;
893 enum machine_mode sreg_mode
;
894 secondary_reload_info sri
;
896 lra_assert (curr_insn_set
!= NULL_RTX
);
897 dreg
= dest
= SET_DEST (curr_insn_set
);
898 sreg
= src
= SET_SRC (curr_insn_set
);
899 if (GET_CODE (dest
) == SUBREG
)
900 dreg
= SUBREG_REG (dest
);
901 if (GET_CODE (src
) == SUBREG
)
902 sreg
= SUBREG_REG (src
);
903 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
905 sclass
= dclass
= NO_REGS
;
907 dclass
= get_reg_class (REGNO (dreg
));
908 if (dclass
== ALL_REGS
)
909 /* ALL_REGS is used for new pseudos created by transformations
910 like reload of SUBREG_REG (see function
911 simplify_operand_subreg). We don't know their class yet. We
912 should figure out the class from processing the insn
913 constraints not in this fast path function. Even if ALL_REGS
914 were a right class for the pseudo, secondary_... hooks usually
915 are not define for ALL_REGS. */
917 sreg_mode
= GET_MODE (sreg
);
920 sclass
= get_reg_class (REGNO (sreg
));
921 if (sclass
== ALL_REGS
)
922 /* See comments above. */
924 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
926 #ifdef SECONDARY_MEMORY_NEEDED
927 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
928 #ifdef SECONDARY_MEMORY_NEEDED_MODE
929 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
930 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
938 if (! REG_P (dreg
) || ! REG_P (sreg
))
941 sri
.icode
= CODE_FOR_nothing
;
943 secondary_class
= NO_REGS
;
944 /* Set up hard register for a reload pseudo for hook
945 secondary_reload because some targets just ignore unassigned
946 pseudos in the hook. */
947 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
949 dregno
= REGNO (dreg
);
950 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
954 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
956 sregno
= REGNO (sreg
);
957 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
961 if (sclass
!= NO_REGS
)
963 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
964 (reg_class_t
) sclass
,
965 GET_MODE (src
), &sri
);
966 if (sclass
== NO_REGS
967 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
968 && dclass
!= NO_REGS
))
970 enum reg_class old_sclass
= secondary_class
;
971 secondary_reload_info old_sri
= sri
;
974 sri
.icode
= CODE_FOR_nothing
;
977 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
978 (reg_class_t
) dclass
,
980 /* Check the target hook consistency. */
982 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
983 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
984 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
987 reg_renumber
[sregno
] = -1;
989 reg_renumber
[dregno
] = -1;
990 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
994 if (secondary_class
!= NO_REGS
)
995 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
999 if (old_sreg
!= sreg
)
1000 sreg
= copy_rtx (sreg
);
1001 if (sri
.icode
== CODE_FOR_nothing
)
1002 lra_emit_move (new_reg
, sreg
);
1005 enum reg_class scratch_class
;
1007 scratch_class
= (reg_class_from_constraints
1008 (insn_data
[sri
.icode
].operand
[2].constraint
));
1009 scratch_reg
= (lra_create_new_reg_with_unique_value
1010 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1011 scratch_class
, "scratch"));
1012 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1013 sreg
, scratch_reg
));
1015 before
= get_insns ();
1017 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1018 if (new_reg
!= NULL_RTX
)
1020 if (GET_CODE (src
) == SUBREG
)
1021 SUBREG_REG (src
) = new_reg
;
1023 SET_SRC (curr_insn_set
) = new_reg
;
1027 if (lra_dump_file
!= NULL
)
1029 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1030 dump_insn_slim (lra_dump_file
, curr_insn
);
1032 lra_set_insn_deleted (curr_insn
);
1038 /* The following data describe the result of process_alt_operands.
1039 The data are used in curr_insn_transform to generate reloads. */
1041 /* The chosen reg classes which should be used for the corresponding
1043 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1044 /* True if the operand should be the same as another operand and that
1045 other operand does not need a reload. */
1046 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1047 /* True if the operand does not need a reload. */
1048 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1049 /* True if the operand can be offsetable memory. */
1050 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1051 /* The number of an operand to which given operand can be matched to. */
1052 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1053 /* The number of elements in the following array. */
1054 static int goal_alt_dont_inherit_ops_num
;
1055 /* Numbers of operands whose reload pseudos should not be inherited. */
1056 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1057 /* True if the insn commutative operands should be swapped. */
1058 static bool goal_alt_swapped
;
1059 /* The chosen insn alternative. */
1060 static int goal_alt_number
;
1062 /* The following five variables are used to choose the best insn
1063 alternative. They reflect final characteristics of the best
1066 /* Number of necessary reloads and overall cost reflecting the
1067 previous value and other unpleasantness of the best alternative. */
1068 static int best_losers
, best_overall
;
1069 /* Overall number hard registers used for reloads. For example, on
1070 some targets we need 2 general registers to reload DFmode and only
1071 one floating point register. */
1072 static int best_reload_nregs
;
1073 /* Overall number reflecting distances of previous reloading the same
1074 value. The distances are counted from the current BB start. It is
1075 used to improve inheritance chances. */
1076 static int best_reload_sum
;
1078 /* True if the current insn should have no correspondingly input or
1080 static bool no_input_reloads_p
, no_output_reloads_p
;
1082 /* True if we swapped the commutative operands in the current
1084 static int curr_swapped
;
1086 /* Arrange for address element *LOC to be a register of class CL.
1087 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1088 automodified value; handle that case by adding the required output
1089 reloads to list AFTER. Return true if the RTL was changed. */
1091 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1094 enum reg_class rclass
, new_class
;
1097 enum machine_mode mode
;
1098 bool before_p
= false;
1100 loc
= strip_subreg (loc
);
1102 mode
= GET_MODE (reg
);
1105 /* Always reload memory in an address even if the target supports
1107 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1112 regno
= REGNO (reg
);
1113 rclass
= get_reg_class (regno
);
1114 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1116 if (lra_dump_file
!= NULL
)
1118 fprintf (lra_dump_file
,
1119 "Changing pseudo %d in address of insn %u on equiv ",
1120 REGNO (reg
), INSN_UID (curr_insn
));
1121 dump_value_slim (lra_dump_file
, *loc
, 1);
1122 fprintf (lra_dump_file
, "\n");
1124 *loc
= copy_rtx (*loc
);
1126 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1129 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1130 mode
, reg
, cl
, "address", &new_reg
))
1133 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1135 change_class (regno
, new_class
, " Change", true);
1143 push_to_sequence (*before
);
1144 lra_emit_move (new_reg
, reg
);
1145 *before
= get_insns ();
1152 lra_emit_move (reg
, new_reg
);
1154 *after
= get_insns ();
1160 /* Make reloads for subreg in operand NOP with internal subreg mode
1161 REG_MODE, add new reloads for further processing. Return true if
1162 any reload was generated. */
1164 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1168 enum machine_mode mode
;
1170 rtx operand
= *curr_id
->operand_loc
[nop
];
1172 before
= after
= NULL_RTX
;
1174 if (GET_CODE (operand
) != SUBREG
)
1177 mode
= GET_MODE (operand
);
1178 reg
= SUBREG_REG (operand
);
1179 /* If we change address for paradoxical subreg of memory, the
1180 address might violate the necessary alignment or the access might
1181 be slow. So take this into consideration. We should not worry
1182 about access beyond allocated memory for paradoxical memory
1183 subregs as we don't substitute such equiv memory (see processing
1184 equivalences in function lra_constraints) and because for spilled
1185 pseudos we allocate stack memory enough for the biggest
1186 corresponding paradoxical subreg. */
1188 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1189 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1190 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1192 alter_subreg (curr_id
->operand_loc
[nop
], false);
1195 /* Put constant into memory when we have mixed modes. It generates
1196 a better code in most cases as it does not need a secondary
1197 reload memory. It also prevents LRA looping when LRA is using
1198 secondary reload memory again and again. */
1199 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1200 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1202 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1203 alter_subreg (curr_id
->operand_loc
[nop
], false);
1206 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1207 if there may be a problem accessing OPERAND in the outer
1210 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1211 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1212 /* Don't reload paradoxical subregs because we could be looping
1213 having repeatedly final regno out of hard regs range. */
1214 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1215 >= hard_regno_nregs
[hard_regno
][mode
])
1216 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1217 SUBREG_BYTE (operand
), mode
) < 0
1218 /* Don't reload subreg for matching reload. It is actually
1219 valid subreg in LRA. */
1220 && ! LRA_SUBREG_P (operand
))
1221 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1223 enum op_type type
= curr_static_id
->operand
[nop
].type
;
1224 /* The class will be defined later in curr_insn_transform. */
1225 enum reg_class rclass
1226 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1228 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1229 rclass
, "subreg reg", &new_reg
))
1231 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1233 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
))
1235 push_to_sequence (before
);
1236 lra_emit_move (new_reg
, reg
);
1237 before
= get_insns ();
1243 lra_emit_move (reg
, new_reg
);
1245 after
= get_insns ();
1249 SUBREG_REG (operand
) = new_reg
;
1250 lra_process_new_insns (curr_insn
, before
, after
,
1251 "Inserting subreg reload");
1257 /* Return TRUE if X refers for a hard register from SET. */
1259 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1261 int i
, j
, x_hard_regno
;
1262 enum machine_mode mode
;
1268 code
= GET_CODE (x
);
1269 mode
= GET_MODE (x
);
1273 code
= GET_CODE (x
);
1274 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1275 mode
= GET_MODE (x
);
1280 x_hard_regno
= get_hard_regno (x
);
1281 return (x_hard_regno
>= 0
1282 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1286 struct address_info ad
;
1288 decompose_mem_address (&ad
, x
);
1289 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1291 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1294 fmt
= GET_RTX_FORMAT (code
);
1295 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1299 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1302 else if (fmt
[i
] == 'E')
1304 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1305 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1312 /* Return true if OP is a spilled pseudo. */
1314 spilled_pseudo_p (rtx op
)
1317 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1320 /* Return true if X is a general constant. */
1322 general_constant_p (rtx x
)
1324 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1328 reg_in_class_p (rtx reg
, enum reg_class cl
)
1331 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1332 return in_class_p (reg
, cl
, NULL
);
1335 /* Major function to choose the current insn alternative and what
1336 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1337 negative we should consider only this alternative. Return false if
1338 we can not choose the alternative or find how to reload the
1341 process_alt_operands (int only_alternative
)
1344 int nop
, overall
, nalt
;
1345 int n_alternatives
= curr_static_id
->n_alternatives
;
1346 int n_operands
= curr_static_id
->n_operands
;
1347 /* LOSERS counts the operands that don't fit this alternative and
1348 would require loading. */
1350 /* REJECT is a count of how undesirable this alternative says it is
1351 if any reloading is required. If the alternative matches exactly
1352 then REJECT is ignored, but otherwise it gets this much counted
1353 against it in addition to the reloading needed. */
1355 /* The number of elements in the following array. */
1356 int early_clobbered_regs_num
;
1357 /* Numbers of operands which are early clobber registers. */
1358 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1359 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1360 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1361 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1362 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1363 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1364 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1365 /* The number of elements in the following array. */
1366 int curr_alt_dont_inherit_ops_num
;
1367 /* Numbers of operands whose reload pseudos should not be inherited. */
1368 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1370 /* The register when the operand is a subreg of register, otherwise the
1372 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1373 /* The register if the operand is a register or subreg of register,
1375 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1376 int hard_regno
[MAX_RECOG_OPERANDS
];
1377 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1378 int reload_nregs
, reload_sum
;
1382 /* Calculate some data common for all alternatives to speed up the
1384 for (nop
= 0; nop
< n_operands
; nop
++)
1386 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1387 /* The real hard regno of the operand after the allocation. */
1388 hard_regno
[nop
] = get_hard_regno (op
);
1390 operand_reg
[nop
] = op
;
1391 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1392 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1394 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1395 if (GET_MODE_SIZE (biggest_mode
[nop
])
1396 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1397 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1399 if (REG_P (operand_reg
[nop
]))
1400 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1402 operand_reg
[nop
] = NULL_RTX
;
1405 /* The constraints are made of several alternatives. Each operand's
1406 constraint looks like foo,bar,... with commas separating the
1407 alternatives. The first alternatives for all operands go
1408 together, the second alternatives go together, etc.
1410 First loop over alternatives. */
1411 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1413 /* Loop over operands for one constraint alternative. */
1414 #if HAVE_ATTR_enabled
1415 if (curr_id
->alternative_enabled_p
!= NULL
1416 && ! curr_id
->alternative_enabled_p
[nalt
])
1420 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1424 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1425 for (nop
= 0; nop
< n_operands
; nop
++)
1426 reject
+= (curr_static_id
1427 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1428 early_clobbered_regs_num
= 0;
1430 for (nop
= 0; nop
< n_operands
; nop
++)
1434 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1435 bool win
, did_match
, offmemok
, early_clobber_p
;
1436 /* false => this operand can be reloaded somehow for this
1439 /* true => this operand can be reloaded if the alternative
1442 /* True if a constant forced into memory would be OK for
1445 enum reg_class this_alternative
, this_costly_alternative
;
1446 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1447 bool this_alternative_match_win
, this_alternative_win
;
1448 bool this_alternative_offmemok
;
1449 enum machine_mode mode
;
1451 opalt_num
= nalt
* n_operands
+ nop
;
1452 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1454 /* Fast track for no constraints at all. */
1455 curr_alt
[nop
] = NO_REGS
;
1456 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1457 curr_alt_win
[nop
] = true;
1458 curr_alt_match_win
[nop
] = false;
1459 curr_alt_offmemok
[nop
] = false;
1460 curr_alt_matches
[nop
] = -1;
1464 op
= no_subreg_reg_operand
[nop
];
1465 mode
= curr_operand_mode
[nop
];
1467 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1470 early_clobber_p
= false;
1471 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1473 this_costly_alternative
= this_alternative
= NO_REGS
;
1474 /* We update set of possible hard regs besides its class
1475 because reg class might be inaccurate. For example,
1476 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1477 is translated in HI_REGS because classes are merged by
1478 pairs and there is no accurate intermediate class. */
1479 CLEAR_HARD_REG_SET (this_alternative_set
);
1480 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1481 this_alternative_win
= false;
1482 this_alternative_match_win
= false;
1483 this_alternative_offmemok
= false;
1484 this_alternative_matches
= -1;
1486 /* An empty constraint should be excluded by the fast
1488 lra_assert (*p
!= 0 && *p
!= ',');
1490 /* Scan this alternative's specs for this operand; set WIN
1491 if the operand fits any letter in this alternative.
1492 Otherwise, clear BADOP if this operand could fit some
1493 letter after reloads, or set WINREG if this operand could
1494 fit after reloads provided the constraint allows some
1499 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1508 case '=': case '+': case '?': case '*': case '!':
1509 case ' ': case '\t':
1513 /* We only support one commutative marker, the first
1514 one. We already set commutative above. */
1518 early_clobber_p
= true;
1522 /* Ignore rest of this alternative. */
1526 case '0': case '1': case '2': case '3': case '4':
1527 case '5': case '6': case '7': case '8': case '9':
1532 m
= strtoul (p
, &end
, 10);
1535 lra_assert (nop
> m
);
1537 this_alternative_matches
= m
;
1538 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1539 /* We are supposed to match a previous operand.
1540 If we do, we win if that one did. If we do
1541 not, count both of the operands as losers.
1542 (This is too conservative, since most of the
1543 time only a single reload insn will be needed
1544 to make the two operands win. As a result,
1545 this alternative may be rejected when it is
1546 actually desirable.) */
1548 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1549 *curr_id
->operand_loc
[m
], m_hregno
))
1551 /* We should reject matching of an early
1552 clobber operand if the matching operand is
1553 not dying in the insn. */
1554 if (! curr_static_id
->operand
[m
].early_clobber
1555 || operand_reg
[nop
] == NULL_RTX
1556 || (find_regno_note (curr_insn
, REG_DEAD
,
1558 || REGNO (op
) == REGNO (operand_reg
[m
])))
1563 /* If we are matching a non-offsettable
1564 address where an offsettable address was
1565 expected, then we must reject this
1566 combination, because we can't reload
1568 if (curr_alt_offmemok
[m
]
1569 && MEM_P (*curr_id
->operand_loc
[m
])
1570 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1576 /* Operands don't match. Both operands must
1577 allow a reload register, otherwise we
1578 cannot make them match. */
1579 if (curr_alt
[m
] == NO_REGS
)
1581 /* Retroactively mark the operand we had to
1582 match as a loser, if it wasn't already and
1583 it wasn't matched to a register constraint
1584 (e.g it might be matched by memory). */
1586 && (operand_reg
[m
] == NULL_RTX
1587 || hard_regno
[m
] < 0))
1591 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1592 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1595 /* We prefer no matching alternatives because
1596 it gives more freedom in RA. */
1597 if (operand_reg
[nop
] == NULL_RTX
1598 || (find_regno_note (curr_insn
, REG_DEAD
,
1599 REGNO (operand_reg
[nop
]))
1603 /* If we have to reload this operand and some
1604 previous operand also had to match the same
1605 thing as this operand, we don't know how to do
1607 if (!match_p
|| !curr_alt_win
[m
])
1609 for (i
= 0; i
< nop
; i
++)
1610 if (curr_alt_matches
[i
] == m
)
1618 /* This can be fixed with reloads if the operand
1619 we are supposed to match can be fixed with
1622 this_alternative
= curr_alt
[m
];
1623 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1624 winreg
= this_alternative
!= NO_REGS
;
1629 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1631 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1632 IOR_HARD_REG_SET (this_alternative_set
,
1633 reg_class_contents
[cl
]);
1636 this_costly_alternative
1637 = reg_class_subunion
[this_costly_alternative
][cl
];
1638 IOR_HARD_REG_SET (this_costly_alternative_set
,
1639 reg_class_contents
[cl
]);
1645 case TARGET_MEM_CONSTRAINT
:
1646 if (MEM_P (op
) || spilled_pseudo_p (op
))
1648 /* We can put constant or pseudo value into memory
1649 to satisfy the constraint. */
1650 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1657 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1658 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1664 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1665 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1669 /* Memory op whose address is not offsettable. */
1672 && ! offsettable_nonstrict_memref_p (op
))
1676 /* Memory operand whose address is offsettable. */
1679 && offsettable_nonstrict_memref_p (op
))
1680 || spilled_pseudo_p (op
))
1682 /* We can put constant or pseudo value into memory
1683 or make memory address offsetable to satisfy the
1685 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1693 if (GET_CODE (op
) == CONST_DOUBLE
1694 || (GET_CODE (op
) == CONST_VECTOR
1695 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1701 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1702 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1707 if (CONST_SCALAR_INT_P (op
))
1711 if (general_constant_p (op
))
1716 if (CONST_SCALAR_INT_P (op
))
1728 if (CONST_INT_P (op
)
1729 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1734 /* This constraint should be excluded by the fast
1741 || general_constant_p (op
)
1742 || spilled_pseudo_p (op
))
1744 /* Drop through into 'r' case. */
1748 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1749 IOR_HARD_REG_SET (this_alternative_set
,
1750 reg_class_contents
[GENERAL_REGS
]);
1753 this_costly_alternative
1754 = (reg_class_subunion
1755 [this_costly_alternative
][GENERAL_REGS
]);
1756 IOR_HARD_REG_SET (this_costly_alternative_set
,
1757 reg_class_contents
[GENERAL_REGS
]);
1762 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1764 #ifdef EXTRA_CONSTRAINT_STR
1765 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1767 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1769 else if (spilled_pseudo_p (op
))
1772 /* If we didn't already win, we can reload
1773 constants via force_const_mem or put the
1774 pseudo value into memory, or make other
1775 memory by reloading the address like for
1777 if (CONST_POOL_OK_P (mode
, op
)
1778 || MEM_P (op
) || REG_P (op
))
1784 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1786 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1789 /* If we didn't already win, we can reload
1790 the address into a base register. */
1791 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1794 = reg_class_subunion
[this_alternative
][cl
];
1795 IOR_HARD_REG_SET (this_alternative_set
,
1796 reg_class_contents
[cl
]);
1799 this_costly_alternative
1800 = (reg_class_subunion
1801 [this_costly_alternative
][cl
]);
1802 IOR_HARD_REG_SET (this_costly_alternative_set
,
1803 reg_class_contents
[cl
]);
1809 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1815 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1816 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1817 IOR_HARD_REG_SET (this_alternative_set
,
1818 reg_class_contents
[cl
]);
1821 this_costly_alternative
1822 = reg_class_subunion
[this_costly_alternative
][cl
];
1823 IOR_HARD_REG_SET (this_costly_alternative_set
,
1824 reg_class_contents
[cl
]);
1827 if (mode
== BLKmode
)
1832 if (hard_regno
[nop
] >= 0
1833 && in_hard_reg_set_p (this_alternative_set
,
1834 mode
, hard_regno
[nop
]))
1836 else if (hard_regno
[nop
] < 0
1837 && in_class_p (op
, this_alternative
, NULL
))
1842 if (c
!= ' ' && c
!= '\t')
1843 costly_p
= c
== '*';
1845 while ((p
+= len
), c
);
1847 /* Record which operands fit this alternative. */
1850 this_alternative_win
= true;
1851 if (operand_reg
[nop
] != NULL_RTX
)
1853 if (hard_regno
[nop
] >= 0)
1855 if (in_hard_reg_set_p (this_costly_alternative_set
,
1856 mode
, hard_regno
[nop
]))
1861 /* Prefer won reg to spilled pseudo under other equal
1864 if (in_class_p (operand_reg
[nop
],
1865 this_costly_alternative
, NULL
))
1868 /* We simulate the behaviour of old reload here.
1869 Although scratches need hard registers and it
1870 might result in spilling other pseudos, no reload
1871 insns are generated for the scratches. So it
1872 might cost something but probably less than old
1873 reload pass believes. */
1874 if (lra_former_scratch_p (REGNO (operand_reg
[nop
])))
1875 reject
+= LRA_LOSER_COST_FACTOR
;
1879 this_alternative_match_win
= true;
1882 int const_to_mem
= 0;
1885 /* If this alternative asks for a specific reg class, see if there
1886 is at least one allocatable register in that class. */
1888 = (this_alternative
== NO_REGS
1889 || (hard_reg_set_subset_p
1890 (reg_class_contents
[this_alternative
],
1891 lra_no_alloc_regs
)));
1893 /* For asms, verify that the class for this alternative is possible
1894 for the mode that is specified. */
1895 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
1898 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1899 if (HARD_REGNO_MODE_OK (i
, mode
)
1900 && in_hard_reg_set_p (reg_class_contents
[this_alternative
], mode
, i
))
1902 if (i
== FIRST_PSEUDO_REGISTER
)
1906 /* If this operand accepts a register, and if the
1907 register class has at least one allocatable register,
1908 then this operand can be reloaded. */
1909 if (winreg
&& !no_regs_p
)
1915 this_alternative_offmemok
= offmemok
;
1916 if (this_costly_alternative
!= NO_REGS
)
1918 /* If the operand is dying, has a matching constraint,
1919 and satisfies constraints of the matched operand
1920 which failed to satisfy the own constraints, we do
1921 not need to generate a reload insn for this
1923 if (!(this_alternative_matches
>= 0
1924 && !curr_alt_win
[this_alternative_matches
]
1926 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
1927 && (hard_regno
[nop
] >= 0
1928 ? in_hard_reg_set_p (this_alternative_set
,
1929 mode
, hard_regno
[nop
])
1930 : in_class_p (op
, this_alternative
, NULL
))))
1932 /* Strict_low_part requires to reload the register
1933 not the sub-register. In this case we should
1934 check that a final reload hard reg can hold the
1936 if (curr_static_id
->operand
[nop
].strict_low
1938 && hard_regno
[nop
] < 0
1939 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
1940 && ira_class_hard_regs_num
[this_alternative
] > 0
1941 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
1942 [this_alternative
][0],
1944 (*curr_id
->operand_loc
[nop
])))
1948 if (operand_reg
[nop
] != NULL_RTX
1949 /* Output operands and matched input operands are
1950 not inherited. The following conditions do not
1951 exactly describe the previous statement but they
1952 are pretty close. */
1953 && curr_static_id
->operand
[nop
].type
!= OP_OUT
1954 && (this_alternative_matches
< 0
1955 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
1957 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
1961 if (last_reload
> bb_reload_num
)
1962 reload_sum
+= last_reload
- bb_reload_num
;
1964 /* If this is a constant that is reloaded into the
1965 desired class by copying it to memory first, count
1966 that as another reload. This is consistent with
1967 other code and is required to avoid choosing another
1968 alternative when the constant is moved into memory.
1969 Note that the test here is precisely the same as in
1970 the code below that calls force_const_mem. */
1971 if (CONST_POOL_OK_P (mode
, op
)
1972 && ((targetm
.preferred_reload_class
1973 (op
, this_alternative
) == NO_REGS
)
1974 || no_input_reloads_p
))
1981 /* Alternative loses if it requires a type of reload not
1982 permitted for this insn. We can always reload
1983 objects with a REG_UNUSED note. */
1984 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
1985 && no_output_reloads_p
1986 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
1987 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
1988 && no_input_reloads_p
&& ! const_to_mem
))
1991 /* Check strong discouragement of reload of non-constant
1992 into class THIS_ALTERNATIVE. */
1993 if (! CONSTANT_P (op
) && ! no_regs_p
1994 && (targetm
.preferred_reload_class
1995 (op
, this_alternative
) == NO_REGS
1996 || (curr_static_id
->operand
[nop
].type
== OP_OUT
1997 && (targetm
.preferred_output_reload_class
1998 (op
, this_alternative
) == NO_REGS
))))
1999 reject
+= LRA_MAX_REJECT
;
2001 if (! (MEM_P (op
) && offmemok
)
2002 && ! (const_to_mem
&& constmemok
))
2004 /* We prefer to reload pseudos over reloading other
2005 things, since such reloads may be able to be
2006 eliminated later. So bump REJECT in other cases.
2007 Don't do this in the case where we are forcing a
2008 constant into memory and it will then win since
2009 we don't want to have a different alternative
2011 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2016 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2018 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2019 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2022 /* We are trying to spill pseudo into memory. It is
2023 usually more costly than moving to a hard register
2024 although it might takes the same number of
2026 if (no_regs_p
&& REG_P (op
))
2029 #ifdef SECONDARY_MEMORY_NEEDED
2030 /* If reload requires moving value through secondary
2031 memory, it will need one more insn at least. */
2032 if (this_alternative
!= NO_REGS
2033 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2034 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2035 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2037 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2038 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2042 /* Input reloads can be inherited more often than output
2043 reloads can be removed, so penalize output
2045 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2050 if (early_clobber_p
)
2052 /* ??? We check early clobbers after processing all operands
2053 (see loop below) and there we update the costs more.
2054 Should we update the cost (may be approximately) here
2055 because of early clobber register reloads or it is a rare
2056 or non-important thing to be worth to do it. */
2057 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2058 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2060 if (lra_dump_file
!= NULL
)
2061 fprintf (lra_dump_file
,
2062 " alt=%d,overall=%d,losers=%d -- reject\n",
2063 nalt
, overall
, losers
);
2067 curr_alt
[nop
] = this_alternative
;
2068 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2069 curr_alt_win
[nop
] = this_alternative_win
;
2070 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2071 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2072 curr_alt_matches
[nop
] = this_alternative_matches
;
2074 if (this_alternative_matches
>= 0
2075 && !did_match
&& !this_alternative_win
)
2076 curr_alt_win
[this_alternative_matches
] = false;
2078 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2079 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2081 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2082 /* Prevent processing non-move insns. */
2083 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2084 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2085 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2086 && REG_P (no_subreg_reg_operand
[0])
2087 && REG_P (no_subreg_reg_operand
[1])
2088 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2089 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2090 || (! curr_alt_win
[0] && curr_alt_win
[1]
2091 && REG_P (no_subreg_reg_operand
[1])
2092 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2093 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2094 && REG_P (no_subreg_reg_operand
[0])
2095 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2096 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2097 no_subreg_reg_operand
[1])
2098 || (targetm
.preferred_reload_class
2099 (no_subreg_reg_operand
[1],
2100 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2101 /* If it is a result of recent elimination in move
2102 insn we can transform it into an add still by
2103 using this alternative. */
2104 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2105 /* We have a move insn and a new reload insn will be similar
2106 to the current insn. We should avoid such situation as it
2107 results in LRA cycling. */
2108 overall
+= LRA_MAX_REJECT
;
2110 curr_alt_dont_inherit_ops_num
= 0;
2111 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2113 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2114 HARD_REG_SET temp_set
;
2116 i
= early_clobbered_nops
[nop
];
2117 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2118 || hard_regno
[i
] < 0)
2120 lra_assert (operand_reg
[i
] != NULL_RTX
);
2121 clobbered_hard_regno
= hard_regno
[i
];
2122 CLEAR_HARD_REG_SET (temp_set
);
2123 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2124 first_conflict_j
= last_conflict_j
= -1;
2125 for (j
= 0; j
< n_operands
; j
++)
2127 /* We don't want process insides of match_operator and
2128 match_parallel because otherwise we would process
2129 their operands once again generating a wrong
2131 || curr_static_id
->operand
[j
].is_operator
)
2133 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2134 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2136 /* If we don't reload j-th operand, check conflicts. */
2137 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2138 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2140 if (first_conflict_j
< 0)
2141 first_conflict_j
= j
;
2142 last_conflict_j
= j
;
2144 if (last_conflict_j
< 0)
2146 /* If earlyclobber operand conflicts with another
2147 non-matching operand which is actually the same register
2148 as the earlyclobber operand, it is better to reload the
2149 another operand as an operand matching the earlyclobber
2150 operand can be also the same. */
2151 if (first_conflict_j
== last_conflict_j
2152 && operand_reg
[last_conflict_j
]
2153 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2154 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2156 curr_alt_win
[last_conflict_j
] = false;
2157 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2160 /* Early clobber was already reflected in REJECT. */
2161 lra_assert (reject
> 0);
2163 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2167 /* We need to reload early clobbered register and the
2168 matched registers. */
2169 for (j
= 0; j
< n_operands
; j
++)
2170 if (curr_alt_matches
[j
] == i
)
2172 curr_alt_match_win
[j
] = false;
2174 overall
+= LRA_LOSER_COST_FACTOR
;
2176 if (! curr_alt_match_win
[i
])
2177 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2180 /* Remember pseudos used for match reloads are never
2182 lra_assert (curr_alt_matches
[i
] >= 0);
2183 curr_alt_win
[curr_alt_matches
[i
]] = false;
2185 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2187 /* Early clobber was already reflected in REJECT. */
2188 lra_assert (reject
> 0);
2190 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2193 if (lra_dump_file
!= NULL
)
2194 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2195 nalt
, overall
, losers
, reload_nregs
);
2197 /* If this alternative can be made to work by reloading, and it
2198 needs less reloading than the others checked so far, record
2199 it as the chosen goal for reloading. */
2200 if ((best_losers
!= 0 && losers
== 0)
2201 || (((best_losers
== 0 && losers
== 0)
2202 || (best_losers
!= 0 && losers
!= 0))
2203 && (best_overall
> overall
2204 || (best_overall
== overall
2205 /* If the cost of the reloads is the same,
2206 prefer alternative which requires minimal
2207 number of reload regs. */
2208 && (reload_nregs
< best_reload_nregs
2209 || (reload_nregs
== best_reload_nregs
2210 && (best_reload_sum
< reload_sum
2211 || (best_reload_sum
== reload_sum
2212 && nalt
< goal_alt_number
))))))))
2214 for (nop
= 0; nop
< n_operands
; nop
++)
2216 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2217 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2218 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2219 goal_alt
[nop
] = curr_alt
[nop
];
2220 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2222 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2223 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2224 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2225 goal_alt_swapped
= curr_swapped
;
2226 best_overall
= overall
;
2227 best_losers
= losers
;
2228 best_reload_nregs
= reload_nregs
;
2229 best_reload_sum
= reload_sum
;
2230 goal_alt_number
= nalt
;
2233 /* Everything is satisfied. Do not process alternatives
2242 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2243 space AS, and check that each pseudo has the proper kind of hard
2246 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2247 rtx addr
, addr_space_t as
)
2249 #ifdef GO_IF_LEGITIMATE_ADDRESS
2250 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2251 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2257 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2261 /* Return whether address AD is valid. */
2264 valid_address_p (struct address_info
*ad
)
2266 /* Some ports do not check displacements for eliminable registers,
2267 so we replace them temporarily with the elimination target. */
2268 rtx saved_base_reg
= NULL_RTX
;
2269 rtx saved_index_reg
= NULL_RTX
;
2270 rtx
*base_term
= strip_subreg (ad
->base_term
);
2271 rtx
*index_term
= strip_subreg (ad
->index_term
);
2272 if (base_term
!= NULL
)
2274 saved_base_reg
= *base_term
;
2275 lra_eliminate_reg_if_possible (base_term
);
2276 if (ad
->base_term2
!= NULL
)
2277 *ad
->base_term2
= *ad
->base_term
;
2279 if (index_term
!= NULL
)
2281 saved_index_reg
= *index_term
;
2282 lra_eliminate_reg_if_possible (index_term
);
2284 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2285 if (saved_base_reg
!= NULL_RTX
)
2287 *base_term
= saved_base_reg
;
2288 if (ad
->base_term2
!= NULL
)
2289 *ad
->base_term2
= *ad
->base_term
;
2291 if (saved_index_reg
!= NULL_RTX
)
2292 *index_term
= saved_index_reg
;
2296 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2298 base_plus_disp_to_reg (struct address_info
*ad
)
2303 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2304 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2305 get_index_code (ad
));
2306 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2308 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2312 /* Return true if we can add a displacement to address AD, even if that
2313 makes the address invalid. The fix-up code requires any new address
2314 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2316 can_add_disp_p (struct address_info
*ad
)
2318 return (!ad
->autoinc_p
2319 && ad
->segment
== NULL
2320 && ad
->base
== ad
->base_term
2321 && ad
->disp
== ad
->disp_term
);
2324 /* Make equiv substitution in address AD. Return true if a substitution
2327 equiv_address_substitution (struct address_info
*ad
)
2329 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2330 HOST_WIDE_INT disp
, scale
;
2333 base_term
= strip_subreg (ad
->base_term
);
2334 if (base_term
== NULL
)
2335 base_reg
= new_base_reg
= NULL_RTX
;
2338 base_reg
= *base_term
;
2339 new_base_reg
= get_equiv_substitution (base_reg
);
2341 index_term
= strip_subreg (ad
->index_term
);
2342 if (index_term
== NULL
)
2343 index_reg
= new_index_reg
= NULL_RTX
;
2346 index_reg
= *index_term
;
2347 new_index_reg
= get_equiv_substitution (index_reg
);
2349 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2353 if (lra_dump_file
!= NULL
)
2355 fprintf (lra_dump_file
, "Changing address in insn %d ",
2356 INSN_UID (curr_insn
));
2357 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2359 if (base_reg
!= new_base_reg
)
2361 if (REG_P (new_base_reg
))
2363 *base_term
= new_base_reg
;
2366 else if (GET_CODE (new_base_reg
) == PLUS
2367 && REG_P (XEXP (new_base_reg
, 0))
2368 && CONST_INT_P (XEXP (new_base_reg
, 1))
2369 && can_add_disp_p (ad
))
2371 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2372 *base_term
= XEXP (new_base_reg
, 0);
2375 if (ad
->base_term2
!= NULL
)
2376 *ad
->base_term2
= *ad
->base_term
;
2378 if (index_reg
!= new_index_reg
)
2380 if (REG_P (new_index_reg
))
2382 *index_term
= new_index_reg
;
2385 else if (GET_CODE (new_index_reg
) == PLUS
2386 && REG_P (XEXP (new_index_reg
, 0))
2387 && CONST_INT_P (XEXP (new_index_reg
, 1))
2388 && can_add_disp_p (ad
)
2389 && (scale
= get_index_scale (ad
)))
2391 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2392 *index_term
= XEXP (new_index_reg
, 0);
2398 if (ad
->disp
!= NULL
)
2399 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2402 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2403 update_address (ad
);
2407 if (lra_dump_file
!= NULL
)
2410 fprintf (lra_dump_file
, " -- no change\n");
2413 fprintf (lra_dump_file
, " on equiv ");
2414 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2415 fprintf (lra_dump_file
, "\n");
2421 /* Major function to make reloads for an address in operand NOP.
2422 The supported cases are:
2424 1) an address that existed before LRA started, at which point it
2425 must have been valid. These addresses are subject to elimination
2426 and may have become invalid due to the elimination offset being out
2429 2) an address created by forcing a constant to memory
2430 (force_const_to_mem). The initial form of these addresses might
2431 not be valid, and it is this function's job to make them valid.
2433 3) a frame address formed from a register and a (possibly zero)
2434 constant offset. As above, these addresses might not be valid and
2435 this function must make them so.
2437 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2438 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2439 address. Return true for any RTL change. */
2441 process_address (int nop
, rtx
*before
, rtx
*after
)
2443 struct address_info ad
;
2445 rtx op
= *curr_id
->operand_loc
[nop
];
2446 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2449 if (constraint
[0] == 'p'
2450 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2451 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2452 else if (MEM_P (op
))
2453 decompose_mem_address (&ad
, op
);
2454 else if (GET_CODE (op
) == SUBREG
2455 && MEM_P (SUBREG_REG (op
)))
2456 decompose_mem_address (&ad
, SUBREG_REG (op
));
2459 change_p
= equiv_address_substitution (&ad
);
2460 if (ad
.base_term
!= NULL
2461 && (process_addr_reg
2462 (ad
.base_term
, before
,
2464 && !(REG_P (*ad
.base_term
)
2465 && find_regno_note (curr_insn
, REG_DEAD
,
2466 REGNO (*ad
.base_term
)) != NULL_RTX
)
2468 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2469 get_index_code (&ad
)))))
2472 if (ad
.base_term2
!= NULL
)
2473 *ad
.base_term2
= *ad
.base_term
;
2475 if (ad
.index_term
!= NULL
2476 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2479 #ifdef EXTRA_CONSTRAINT_STR
2480 /* Target hooks sometimes reject extra constraint addresses -- use
2481 EXTRA_CONSTRAINT_STR for the validation. */
2482 if (constraint
[0] != 'p'
2483 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2484 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2488 /* There are three cases where the shape of *AD.INNER may now be invalid:
2490 1) the original address was valid, but either elimination or
2491 equiv_address_substitution was applied and that made
2492 the address invalid.
2494 2) the address is an invalid symbolic address created by
2497 3) the address is a frame address with an invalid offset.
2499 All these cases involve a non-autoinc address, so there is no
2500 point revalidating other types. */
2501 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2504 /* Any index existed before LRA started, so we can assume that the
2505 presence and shape of the index is valid. */
2506 push_to_sequence (*before
);
2507 lra_assert (ad
.disp
== ad
.disp_term
);
2508 if (ad
.base
== NULL
)
2510 if (ad
.index
== NULL
)
2513 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2515 rtx addr
= *ad
.inner
;
2517 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2521 rtx last
= get_last_insn ();
2523 /* addr => lo_sum (new_base, addr), case (2) above. */
2524 insn
= emit_insn (gen_rtx_SET
2526 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2527 code
= recog_memoized (insn
);
2530 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2531 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2533 /* Try to put lo_sum into register. */
2534 insn
= emit_insn (gen_rtx_SET
2536 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2537 code
= recog_memoized (insn
);
2540 *ad
.inner
= new_reg
;
2541 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2551 delete_insns_since (last
);
2556 /* addr => new_base, case (2) above. */
2557 lra_emit_move (new_reg
, addr
);
2558 *ad
.inner
= new_reg
;
2563 /* index * scale + disp => new base + index * scale,
2565 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2566 GET_CODE (*ad
.index
));
2568 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2569 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2570 lra_emit_move (new_reg
, *ad
.disp
);
2571 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2572 new_reg
, *ad
.index
);
2575 else if (ad
.index
== NULL
)
2579 rtx set
, insns
, last_insn
;
2580 /* base + disp => new base, cases (1) and (3) above. */
2581 /* Another option would be to reload the displacement into an
2582 index register. However, postreload has code to optimize
2583 address reloads that have the same base and different
2584 displacements, so reloading into an index register would
2585 not necessarily be a win. */
2587 new_reg
= base_plus_disp_to_reg (&ad
);
2588 insns
= get_insns ();
2589 last_insn
= get_last_insn ();
2590 /* If we generated at least two insns, try last insn source as
2591 an address. If we succeed, we generate one less insn. */
2592 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2593 && GET_CODE (SET_SRC (set
)) == PLUS
2594 && REG_P (XEXP (SET_SRC (set
), 0))
2595 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2597 *ad
.inner
= SET_SRC (set
);
2598 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2600 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2601 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2602 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2603 get_index_code (&ad
));
2604 regno
= REGNO (*ad
.base_term
);
2605 if (regno
>= FIRST_PSEUDO_REGISTER
2606 && cl
!= lra_get_allocno_class (regno
))
2607 change_class (regno
, cl
, " Change", true);
2608 new_reg
= SET_SRC (set
);
2609 delete_insns_since (PREV_INSN (last_insn
));
2614 *ad
.inner
= new_reg
;
2618 /* base + scale * index + disp => new base + scale * index,
2620 new_reg
= base_plus_disp_to_reg (&ad
);
2621 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2622 new_reg
, *ad
.index
);
2624 *before
= get_insns ();
2629 /* Emit insns to reload VALUE into a new register. VALUE is an
2630 auto-increment or auto-decrement RTX whose operand is a register or
2631 memory location; so reloading involves incrementing that location.
2632 IN is either identical to VALUE, or some cheaper place to reload
2633 value being incremented/decremented from.
2635 INC_AMOUNT is the number to increment or decrement by (always
2636 positive and ignored for POST_MODIFY/PRE_MODIFY).
2638 Return pseudo containing the result. */
2640 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2642 /* REG or MEM to be copied and incremented. */
2643 rtx incloc
= XEXP (value
, 0);
2644 /* Nonzero if increment after copying. */
2645 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2646 || GET_CODE (value
) == POST_MODIFY
);
2651 rtx real_in
= in
== value
? incloc
: in
;
2655 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2657 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2658 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2659 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2660 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2661 inc
= XEXP (XEXP (value
, 1), 1);
2665 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2666 inc_amount
= -inc_amount
;
2668 inc
= GEN_INT (inc_amount
);
2671 if (! post
&& REG_P (incloc
))
2674 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2677 if (real_in
!= result
)
2679 /* First copy the location to the result register. */
2680 lra_assert (REG_P (result
));
2681 emit_insn (gen_move_insn (result
, real_in
));
2684 /* We suppose that there are insns to add/sub with the constant
2685 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2686 old reload worked with this assumption. If the assumption
2687 becomes wrong, we should use approach in function
2688 base_plus_disp_to_reg. */
2691 /* See if we can directly increment INCLOC. */
2692 last
= get_last_insn ();
2693 add_insn
= emit_insn (plus_p
2694 ? gen_add2_insn (incloc
, inc
)
2695 : gen_sub2_insn (incloc
, inc
));
2697 code
= recog_memoized (add_insn
);
2700 if (! post
&& result
!= incloc
)
2701 emit_insn (gen_move_insn (result
, incloc
));
2704 delete_insns_since (last
);
2707 /* If couldn't do the increment directly, must increment in RESULT.
2708 The way we do this depends on whether this is pre- or
2709 post-increment. For pre-increment, copy INCLOC to the reload
2710 register, increment it there, then save back. */
2713 if (real_in
!= result
)
2714 emit_insn (gen_move_insn (result
, real_in
));
2716 emit_insn (gen_add2_insn (result
, inc
));
2718 emit_insn (gen_sub2_insn (result
, inc
));
2719 if (result
!= incloc
)
2720 emit_insn (gen_move_insn (incloc
, result
));
2726 Because this might be a jump insn or a compare, and because
2727 RESULT may not be available after the insn in an input
2728 reload, we must do the incrementing before the insn being
2731 We have already copied IN to RESULT. Increment the copy in
2732 RESULT, save that back, then decrement RESULT so it has
2733 the original value. */
2735 emit_insn (gen_add2_insn (result
, inc
));
2737 emit_insn (gen_sub2_insn (result
, inc
));
2738 emit_insn (gen_move_insn (incloc
, result
));
2739 /* Restore non-modified value for the result. We prefer this
2740 way because it does not require an additional hard
2744 if (CONST_INT_P (inc
))
2745 emit_insn (gen_add2_insn (result
, GEN_INT (-INTVAL (inc
))));
2747 emit_insn (gen_sub2_insn (result
, inc
));
2750 emit_insn (gen_add2_insn (result
, inc
));
2755 /* Return true if the current move insn does not need processing as we
2756 already know that it satisfies its constraints. */
2758 simple_move_p (void)
2761 enum reg_class dclass
, sclass
;
2763 lra_assert (curr_insn_set
!= NULL_RTX
);
2764 dest
= SET_DEST (curr_insn_set
);
2765 src
= SET_SRC (curr_insn_set
);
2766 return ((dclass
= get_op_class (dest
)) != NO_REGS
2767 && (sclass
= get_op_class (src
)) != NO_REGS
2768 /* The backend guarantees that register moves of cost 2
2769 never need reloads. */
2770 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
2773 /* Swap operands NOP and NOP + 1. */
2775 swap_operands (int nop
)
2777 enum machine_mode mode
= curr_operand_mode
[nop
];
2778 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2779 curr_operand_mode
[nop
+ 1] = mode
;
2780 rtx x
= *curr_id
->operand_loc
[nop
];
2781 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2782 *curr_id
->operand_loc
[nop
+ 1] = x
;
2783 /* Swap the duplicates too. */
2784 lra_update_dup (curr_id
, nop
);
2785 lra_update_dup (curr_id
, nop
+ 1);
2788 /* Main entry point of the constraint code: search the body of the
2789 current insn to choose the best alternative. It is mimicking insn
2790 alternative cost calculation model of former reload pass. That is
2791 because machine descriptions were written to use this model. This
2792 model can be changed in future. Make commutative operand exchange
2795 Return true if some RTL changes happened during function call. */
2797 curr_insn_transform (void)
2803 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2804 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
2807 /* Flag that the insn has been changed through a transformation. */
2810 #ifdef SECONDARY_MEMORY_NEEDED
2813 int max_regno_before
;
2814 int reused_alternative_num
;
2816 curr_insn_set
= single_set (curr_insn
);
2817 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
2820 no_input_reloads_p
= no_output_reloads_p
= false;
2821 goal_alt_number
= -1;
2822 change_p
= sec_mem_p
= false;
2823 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
2824 reloads; neither are insns that SET cc0. Insns that use CC0 are
2825 not allowed to have any input reloads. */
2826 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
2827 no_output_reloads_p
= true;
2830 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
2831 no_input_reloads_p
= true;
2832 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
2833 no_output_reloads_p
= true;
2836 n_operands
= curr_static_id
->n_operands
;
2837 n_alternatives
= curr_static_id
->n_alternatives
;
2839 /* Just return "no reloads" if insn has no operands with
2841 if (n_operands
== 0 || n_alternatives
== 0)
2844 max_regno_before
= max_reg_num ();
2846 for (i
= 0; i
< n_operands
; i
++)
2848 goal_alt_matched
[i
][0] = -1;
2849 goal_alt_matches
[i
] = -1;
2852 commutative
= curr_static_id
->commutative
;
2854 /* Now see what we need for pseudos that didn't get hard regs or got
2855 the wrong kind of hard reg. For this, we must consider all the
2856 operands together against the register constraints. */
2858 best_losers
= best_overall
= INT_MAX
;
2859 best_reload_sum
= 0;
2861 curr_swapped
= false;
2862 goal_alt_swapped
= false;
2864 /* Make equivalence substitution and memory subreg elimination
2865 before address processing because an address legitimacy can
2866 depend on memory mode. */
2867 for (i
= 0; i
< n_operands
; i
++)
2869 rtx op
= *curr_id
->operand_loc
[i
];
2870 rtx subst
, old
= op
;
2871 bool op_change_p
= false;
2873 if (GET_CODE (old
) == SUBREG
)
2874 old
= SUBREG_REG (old
);
2875 subst
= get_equiv_substitution (old
);
2878 subst
= copy_rtx (subst
);
2879 lra_assert (REG_P (old
));
2880 if (GET_CODE (op
) == SUBREG
)
2881 SUBREG_REG (op
) = subst
;
2883 *curr_id
->operand_loc
[i
] = subst
;
2884 if (lra_dump_file
!= NULL
)
2886 fprintf (lra_dump_file
,
2887 "Changing pseudo %d in operand %i of insn %u on equiv ",
2888 REGNO (old
), i
, INSN_UID (curr_insn
));
2889 dump_value_slim (lra_dump_file
, subst
, 1);
2890 fprintf (lra_dump_file
, "\n");
2892 op_change_p
= change_p
= true;
2894 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
2897 lra_update_dup (curr_id
, i
);
2901 /* Reload address registers and displacements. We do it before
2902 finding an alternative because of memory constraints. */
2903 before
= after
= NULL_RTX
;
2904 for (i
= 0; i
< n_operands
; i
++)
2905 if (! curr_static_id
->operand
[i
].is_operator
2906 && process_address (i
, &before
, &after
))
2909 lra_update_dup (curr_id
, i
);
2913 /* If we've changed the instruction then any alternative that
2914 we chose previously may no longer be valid. */
2915 lra_set_used_insn_alternative (curr_insn
, -1);
2917 if (curr_insn_set
!= NULL_RTX
2918 && check_and_process_move (&change_p
, &sec_mem_p
))
2923 reused_alternative_num
= curr_id
->used_insn_alternative
;
2924 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
2925 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
2926 reused_alternative_num
, INSN_UID (curr_insn
));
2928 if (process_alt_operands (reused_alternative_num
))
2931 /* If insn is commutative (it's safe to exchange a certain pair of
2932 operands) then we need to try each alternative twice, the second
2933 time matching those two operands as if we had exchanged them. To
2934 do this, really exchange them in operands.
2936 If we have just tried the alternatives the second time, return
2937 operands to normal and drop through. */
2939 if (reused_alternative_num
< 0 && commutative
>= 0)
2941 curr_swapped
= !curr_swapped
;
2944 swap_operands (commutative
);
2948 swap_operands (commutative
);
2951 if (! alt_p
&& ! sec_mem_p
)
2953 /* No alternative works with reloads?? */
2954 if (INSN_CODE (curr_insn
) >= 0)
2955 fatal_insn ("unable to generate reloads for:", curr_insn
);
2956 error_for_asm (curr_insn
,
2957 "inconsistent operand constraints in an %<asm%>");
2958 /* Avoid further trouble with this insn. */
2959 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
2960 lra_invalidate_insn_data (curr_insn
);
2964 /* If the best alternative is with operands 1 and 2 swapped, swap
2965 them. Update the operand numbers of any reloads already
2968 if (goal_alt_swapped
)
2970 if (lra_dump_file
!= NULL
)
2971 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
2972 INSN_UID (curr_insn
));
2974 /* Swap the duplicates too. */
2975 swap_operands (commutative
);
2979 #ifdef SECONDARY_MEMORY_NEEDED
2980 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
2981 too conservatively. So we use the secondary memory only if there
2982 is no any alternative without reloads. */
2983 use_sec_mem_p
= false;
2985 use_sec_mem_p
= true;
2988 for (i
= 0; i
< n_operands
; i
++)
2989 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
2991 use_sec_mem_p
= i
< n_operands
;
2996 rtx new_reg
, src
, dest
, rld
;
2997 enum machine_mode sec_mode
, rld_mode
;
2999 lra_assert (sec_mem_p
);
3000 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3001 && curr_static_id
->operand
[1].type
== OP_IN
);
3002 dest
= *curr_id
->operand_loc
[0];
3003 src
= *curr_id
->operand_loc
[1];
3004 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3006 rld_mode
= GET_MODE (rld
);
3007 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3008 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3010 sec_mode
= rld_mode
;
3012 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3013 NO_REGS
, "secondary");
3014 /* If the mode is changed, it should be wider. */
3015 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3016 if (sec_mode
!= rld_mode
)
3018 /* If the target says specifically to use another mode for
3019 secondary memory moves we can not reuse the original
3021 after
= emit_spill_move (false, new_reg
, dest
);
3022 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3023 "Inserting the sec. move");
3024 /* We may have non null BEFORE here (e.g. after address
3026 push_to_sequence (before
);
3027 before
= emit_spill_move (true, new_reg
, src
);
3029 before
= get_insns ();
3031 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3032 lra_set_insn_deleted (curr_insn
);
3034 else if (dest
== rld
)
3036 *curr_id
->operand_loc
[0] = new_reg
;
3037 after
= emit_spill_move (false, new_reg
, dest
);
3038 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3039 "Inserting the sec. move");
3043 *curr_id
->operand_loc
[1] = new_reg
;
3044 /* See comments above. */
3045 push_to_sequence (before
);
3046 before
= emit_spill_move (true, new_reg
, src
);
3048 before
= get_insns ();
3050 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3051 "Inserting the sec. move");
3053 lra_update_insn_regno_info (curr_insn
);
3058 lra_assert (goal_alt_number
>= 0);
3059 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3061 if (lra_dump_file
!= NULL
)
3065 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3066 goal_alt_number
, INSN_UID (curr_insn
));
3067 for (i
= 0; i
< n_operands
; i
++)
3069 p
= (curr_static_id
->operand_alternative
3070 [goal_alt_number
* n_operands
+ i
].constraint
);
3073 fprintf (lra_dump_file
, " (%d) ", i
);
3074 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3075 fputc (*p
, lra_dump_file
);
3077 if (INSN_CODE (curr_insn
) >= 0
3078 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3079 fprintf (lra_dump_file
, " {%s}", p
);
3080 fprintf (lra_dump_file
, "\n");
3083 /* Right now, for any pair of operands I and J that are required to
3084 match, with J < I, goal_alt_matches[I] is J. Add I to
3085 goal_alt_matched[J]. */
3087 for (i
= 0; i
< n_operands
; i
++)
3088 if ((j
= goal_alt_matches
[i
]) >= 0)
3090 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3092 /* We allow matching one output operand and several input
3095 || (curr_static_id
->operand
[j
].type
== OP_OUT
3096 && curr_static_id
->operand
[i
].type
== OP_IN
3097 && (curr_static_id
->operand
3098 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3099 goal_alt_matched
[j
][k
] = i
;
3100 goal_alt_matched
[j
][k
+ 1] = -1;
3103 for (i
= 0; i
< n_operands
; i
++)
3104 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3106 /* Any constants that aren't allowed and can't be reloaded into
3107 registers are here changed into memory references. */
3108 for (i
= 0; i
< n_operands
; i
++)
3109 if (goal_alt_win
[i
])
3112 enum reg_class new_class
;
3113 rtx reg
= *curr_id
->operand_loc
[i
];
3115 if (GET_CODE (reg
) == SUBREG
)
3116 reg
= SUBREG_REG (reg
);
3118 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3120 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3122 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3125 change_class (regno
, new_class
, " Change", true);
3131 const char *constraint
;
3133 rtx op
= *curr_id
->operand_loc
[i
];
3134 rtx subreg
= NULL_RTX
;
3135 enum machine_mode mode
= curr_operand_mode
[i
];
3137 if (GET_CODE (op
) == SUBREG
)
3140 op
= SUBREG_REG (op
);
3141 mode
= GET_MODE (op
);
3144 if (CONST_POOL_OK_P (mode
, op
)
3145 && ((targetm
.preferred_reload_class
3146 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3147 || no_input_reloads_p
))
3149 rtx tem
= force_const_mem (mode
, op
);
3152 if (subreg
!= NULL_RTX
)
3153 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3155 *curr_id
->operand_loc
[i
] = tem
;
3156 lra_update_dup (curr_id
, i
);
3157 process_address (i
, &before
, &after
);
3159 /* If the alternative accepts constant pool refs directly
3160 there will be no reload needed at all. */
3161 if (subreg
!= NULL_RTX
)
3163 /* Skip alternatives before the one requested. */
3164 constraint
= (curr_static_id
->operand_alternative
3165 [goal_alt_number
* n_operands
+ i
].constraint
);
3167 (c
= *constraint
) && c
!= ',' && c
!= '#';
3168 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3170 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3172 #ifdef EXTRA_CONSTRAINT_STR
3173 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3174 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3178 if (c
== '\0' || c
== ',' || c
== '#')
3181 goal_alt_win
[i
] = true;
3185 for (i
= 0; i
< n_operands
; i
++)
3188 bool optional_p
= false;
3190 rtx op
= *curr_id
->operand_loc
[i
];
3192 if (goal_alt_win
[i
])
3194 if (goal_alt
[i
] == NO_REGS
3196 /* When we assign NO_REGS it means that we will not
3197 assign a hard register to the scratch pseudo by
3198 assigment pass and the scratch pseudo will be
3199 spilled. Spilled scratch pseudos are transformed
3200 back to scratches at the LRA end. */
3201 && lra_former_scratch_operand_p (curr_insn
, i
))
3203 int regno
= REGNO (op
);
3204 change_class (regno
, NO_REGS
, " Change", true);
3205 if (lra_get_regno_hard_regno (regno
) >= 0)
3206 /* We don't have to mark all insn affected by the
3207 spilled pseudo as there is only one such insn, the
3209 reg_renumber
[regno
] = -1;
3211 /* We can do an optional reload. If the pseudo got a hard
3212 reg, we might improve the code through inheritance. If
3213 it does not get a hard register we coalesce memory/memory
3214 moves later. Ignore move insns to avoid cycling. */
3215 if (0 && ! lra_simple_p
3216 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3217 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3218 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3219 && reg_renumber
[regno
] < 0
3220 && (curr_insn_set
== NULL_RTX
3221 || !(REG_P (SET_SRC (curr_insn_set
))
3222 || MEM_P (SET_SRC (curr_insn_set
))
3223 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)))
3229 /* Operands that match previous ones have already been handled. */
3230 if (goal_alt_matches
[i
] >= 0)
3233 /* We should not have an operand with a non-offsettable address
3234 appearing where an offsettable address will do. It also may
3235 be a case when the address should be special in other words
3236 not a general one (e.g. it needs no index reg). */
3237 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3239 enum reg_class rclass
;
3240 rtx
*loc
= &XEXP (op
, 0);
3241 enum rtx_code code
= GET_CODE (*loc
);
3243 push_to_sequence (before
);
3244 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3246 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3247 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3248 /* This value does not matter for MODIFY. */
3249 GET_MODE_SIZE (GET_MODE (op
)));
3250 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3251 "offsetable address", &new_reg
))
3252 lra_emit_move (new_reg
, *loc
);
3253 before
= get_insns ();
3256 lra_update_dup (curr_id
, i
);
3258 else if (goal_alt_matched
[i
][0] == -1)
3260 enum machine_mode mode
;
3262 int hard_regno
, byte
;
3263 enum op_type type
= curr_static_id
->operand
[i
].type
;
3265 loc
= curr_id
->operand_loc
[i
];
3266 mode
= curr_operand_mode
[i
];
3267 if (GET_CODE (*loc
) == SUBREG
)
3269 reg
= SUBREG_REG (*loc
);
3270 byte
= SUBREG_BYTE (*loc
);
3272 /* Strict_low_part requires reload the register not
3273 the sub-register. */
3274 && (curr_static_id
->operand
[i
].strict_low
3275 || (GET_MODE_SIZE (mode
)
3276 <= GET_MODE_SIZE (GET_MODE (reg
))
3278 = get_try_hard_regno (REGNO (reg
))) >= 0
3279 && (simplify_subreg_regno
3281 GET_MODE (reg
), byte
, mode
) < 0)
3282 && (goal_alt
[i
] == NO_REGS
3283 || (simplify_subreg_regno
3284 (ira_class_hard_regs
[goal_alt
[i
]][0],
3285 GET_MODE (reg
), byte
, mode
) >= 0)))))
3287 loc
= &SUBREG_REG (*loc
);
3288 mode
= GET_MODE (*loc
);
3292 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3295 push_to_sequence (before
);
3296 lra_emit_move (new_reg
, old
);
3297 before
= get_insns ();
3302 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3305 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3307 after
= get_insns ();
3311 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3312 if (goal_alt_dont_inherit_ops
[j
] == i
)
3314 lra_set_regno_unique_value (REGNO (new_reg
));
3317 lra_update_dup (curr_id
, i
);
3319 else if (curr_static_id
->operand
[i
].type
== OP_IN
3320 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3323 /* generate reloads for input and matched outputs. */
3324 match_inputs
[0] = i
;
3325 match_inputs
[1] = -1;
3326 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3327 goal_alt
[i
], &before
, &after
);
3329 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3330 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3332 /* Generate reloads for output and matched inputs. */
3333 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3334 else if (curr_static_id
->operand
[i
].type
== OP_IN
3335 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3338 /* Generate reloads for matched inputs. */
3339 match_inputs
[0] = i
;
3340 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3341 match_inputs
[j
+ 1] = k
;
3342 match_inputs
[j
+ 1] = -1;
3343 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3346 /* We must generate code in any case when function
3347 process_alt_operands decides that it is possible. */
3351 lra_assert (REG_P (op
));
3353 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3354 if (GET_CODE (op
) == SUBREG
)
3355 op
= SUBREG_REG (op
);
3356 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3357 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3358 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3359 if (lra_dump_file
!= NULL
)
3360 fprintf (lra_dump_file
,
3361 " Making reload reg %d for reg %d optional\n",
3365 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3366 || max_regno_before
!= max_reg_num ())
3370 lra_update_operator_dups (curr_id
);
3371 /* Something changes -- process the insn. */
3372 lra_update_insn_regno_info (curr_insn
);
3374 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3378 /* Return true if X is in LIST. */
3380 in_list_p (rtx x
, rtx list
)
3382 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3383 if (XEXP (list
, 0) == x
)
3388 /* Return true if X contains an allocatable hard register (if
3389 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3391 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3397 code
= GET_CODE (x
);
3400 int regno
= REGNO (x
);
3401 HARD_REG_SET alloc_regs
;
3405 if (regno
>= FIRST_PSEUDO_REGISTER
)
3406 regno
= lra_get_regno_hard_regno (regno
);
3409 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3410 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3414 if (regno
< FIRST_PSEUDO_REGISTER
)
3418 return lra_get_regno_hard_regno (regno
) < 0;
3421 fmt
= GET_RTX_FORMAT (code
);
3422 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3426 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3429 else if (fmt
[i
] == 'E')
3431 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3432 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3439 /* Process all regs in location *LOC and change them on equivalent
3440 substitution. Return true if any change was done. */
3442 loc_equivalence_change_p (rtx
*loc
)
3444 rtx subst
, reg
, x
= *loc
;
3445 bool result
= false;
3446 enum rtx_code code
= GET_CODE (x
);
3452 reg
= SUBREG_REG (x
);
3453 if ((subst
= get_equiv_substitution (reg
)) != reg
3454 && GET_MODE (subst
) == VOIDmode
)
3456 /* We cannot reload debug location. Simplify subreg here
3457 while we know the inner mode. */
3458 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3459 GET_MODE (reg
), SUBREG_BYTE (x
));
3463 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3469 /* Scan all the operand sub-expressions. */
3470 fmt
= GET_RTX_FORMAT (code
);
3471 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3474 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3475 else if (fmt
[i
] == 'E')
3476 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3478 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3483 /* Similar to loc_equivalence_change_p, but for use as
3484 simplify_replace_fn_rtx callback. */
3486 loc_equivalence_callback (rtx loc
, const_rtx
, void *)
3491 rtx subst
= get_equiv_substitution (loc
);
3498 /* Maximum number of generated reload insns per an insn. It is for
3499 preventing this pass cycling in a bug case. */
3500 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3502 /* The current iteration number of this LRA pass. */
3503 int lra_constraint_iter
;
3505 /* The current iteration number of this LRA pass after the last spill
3507 int lra_constraint_iter_after_spill
;
3509 /* True if we substituted equiv which needs checking register
3510 allocation correctness because the equivalent value contains
3511 allocatable hard registers or when we restore multi-register
3513 bool lra_risky_transformations_p
;
3515 /* Return true if REGNO is referenced in more than one block. */
3517 multi_block_pseudo_p (int regno
)
3519 basic_block bb
= NULL
;
3523 if (regno
< FIRST_PSEUDO_REGISTER
)
3526 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3528 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3529 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3534 /* Return true if LIST contains a deleted insn. */
3536 contains_deleted_insn_p (rtx list
)
3538 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3539 if (NOTE_P (XEXP (list
, 0))
3540 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3545 /* Return true if X contains a pseudo dying in INSN. */
3547 dead_pseudo_p (rtx x
, rtx insn
)
3554 return (insn
!= NULL_RTX
3555 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3556 code
= GET_CODE (x
);
3557 fmt
= GET_RTX_FORMAT (code
);
3558 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3562 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3565 else if (fmt
[i
] == 'E')
3567 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3568 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3575 /* Return true if INSN contains a dying pseudo in INSN right hand
3578 insn_rhs_dead_pseudo_p (rtx insn
)
3580 rtx set
= single_set (insn
);
3582 gcc_assert (set
!= NULL
);
3583 return dead_pseudo_p (SET_SRC (set
), insn
);
3586 /* Return true if any init insn of REGNO contains a dying pseudo in
3587 insn right hand side. */
3589 init_insn_rhs_dead_pseudo_p (int regno
)
3591 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3596 return insn_rhs_dead_pseudo_p (insns
);
3597 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3598 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3603 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3604 reverse only if we have one init insn with given REGNO as a
3607 reverse_equiv_p (int regno
)
3611 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3613 if (! INSN_P (XEXP (insns
, 0))
3614 || XEXP (insns
, 1) != NULL_RTX
)
3616 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3618 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3621 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3622 call this function only for non-reverse equivalence. */
3624 contains_reloaded_insn_p (int regno
)
3627 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3629 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3630 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3631 || ! REG_P (SET_DEST (set
))
3632 || (int) REGNO (SET_DEST (set
)) != regno
)
3637 /* Entry function of LRA constraint pass. Return true if the
3638 constraint pass did change the code. */
3640 lra_constraints (bool first_p
)
3643 int i
, hard_regno
, new_insns_num
;
3644 unsigned int min_len
, new_min_len
, uid
;
3645 rtx set
, x
, reg
, dest_reg
;
3646 basic_block last_bb
;
3647 bitmap_head equiv_insn_bitmap
;
3650 lra_constraint_iter
++;
3651 if (lra_dump_file
!= NULL
)
3652 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3653 lra_constraint_iter
);
3654 lra_constraint_iter_after_spill
++;
3655 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3657 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3658 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3660 lra_risky_transformations_p
= false;
3661 new_insn_uid_start
= get_max_uid ();
3662 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3663 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3664 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3665 if (lra_reg_info
[i
].nrefs
!= 0)
3667 ira_reg_equiv
[i
].profitable_p
= true;
3668 reg
= regno_reg_rtx
[i
];
3669 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3673 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3674 for (j
= 0; j
< nregs
; j
++)
3675 df_set_regs_ever_live (hard_regno
+ j
, true);
3677 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3679 bool pseudo_p
= contains_reg_p (x
, false, false);
3681 /* After RTL transformation, we can not guarantee that
3682 pseudo in the substitution was not reloaded which might
3683 make equivalence invalid. For example, in reverse
3690 the memory address register was reloaded before the 2nd
3692 if ((! first_p
&& pseudo_p
)
3693 /* We don't use DF for compilation speed sake. So it
3694 is problematic to update live info when we use an
3695 equivalence containing pseudos in more than one
3697 || (pseudo_p
&& multi_block_pseudo_p (i
))
3698 /* If an init insn was deleted for some reason, cancel
3699 the equiv. We could update the equiv insns after
3700 transformations including an equiv insn deletion
3701 but it is not worthy as such cases are extremely
3703 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3704 /* If it is not a reverse equivalence, we check that a
3705 pseudo in rhs of the init insn is not dying in the
3706 insn. Otherwise, the live info at the beginning of
3707 the corresponding BB might be wrong after we
3708 removed the insn. When the equiv can be a
3709 constant, the right hand side of the init insn can
3711 || (! reverse_equiv_p (i
)
3712 && (init_insn_rhs_dead_pseudo_p (i
)
3713 /* If we reloaded the pseudo in an equivalence
3714 init insn, we can not remove the equiv init
3715 insns and the init insns might write into
3716 const memory in this case. */
3717 || contains_reloaded_insn_p (i
)))
3718 /* Prevent access beyond equivalent memory for
3719 paradoxical subregs. */
3721 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
3722 > GET_MODE_SIZE (GET_MODE (x
)))))
3723 ira_reg_equiv
[i
].defined_p
= false;
3724 if (contains_reg_p (x
, false, true))
3725 ira_reg_equiv
[i
].profitable_p
= false;
3726 if (get_equiv_substitution (reg
) != reg
)
3727 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3730 /* We should add all insns containing pseudos which should be
3731 substituted by their equivalences. */
3732 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3733 lra_push_insn_by_uid (uid
);
3734 lra_eliminate (false);
3735 min_len
= lra_insn_stack_length ();
3739 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3741 curr_insn
= lra_pop_insn ();
3743 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3744 if (curr_bb
!= last_bb
)
3747 bb_reload_num
= lra_curr_reload_num
;
3749 if (min_len
> new_min_len
)
3751 min_len
= new_min_len
;
3754 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3756 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3757 MAX_RELOAD_INSNS_NUMBER
);
3759 if (DEBUG_INSN_P (curr_insn
))
3761 /* We need to check equivalence in debug insn and change
3762 pseudo to the equivalent value if necessary. */
3763 curr_id
= lra_get_insn_recog_data (curr_insn
);
3764 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
3766 rtx old
= *curr_id
->operand_loc
[0];
3767 *curr_id
->operand_loc
[0]
3768 = simplify_replace_fn_rtx (old
, NULL_RTX
,
3769 loc_equivalence_callback
, NULL
);
3770 if (old
!= *curr_id
->operand_loc
[0])
3772 lra_update_insn_regno_info (curr_insn
);
3777 else if (INSN_P (curr_insn
))
3779 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3781 dest_reg
= SET_DEST (set
);
3782 /* The equivalence pseudo could be set up as SUBREG in a
3783 case when it is a call restore insn in a mode
3784 different from the pseudo mode. */
3785 if (GET_CODE (dest_reg
) == SUBREG
)
3786 dest_reg
= SUBREG_REG (dest_reg
);
3787 if ((REG_P (dest_reg
)
3788 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3789 /* Check that this is actually an insn setting up
3791 && (in_list_p (curr_insn
,
3793 [REGNO (dest_reg
)].init_insns
)
3794 /* Init insns may contain not all insns setting
3795 up equivalence as we have live range
3796 splitting. So here we use another condition
3797 to check insn setting up the equivalence
3798 which should be removed, e.g. in case when
3799 the equivalence is a constant. */
3801 /* Remove insns which set up a pseudo whose value
3802 can not be changed. Such insns might be not in
3803 init_insns because we don't update equiv data
3804 during insn transformations.
3806 As an example, let suppose that a pseudo got
3807 hard register and on the 1st pass was not
3808 changed to equivalent constant. We generate an
3809 additional insn setting up the pseudo because of
3810 secondary memory movement. Then the pseudo is
3811 spilled and we use the equiv constant. In this
3812 case we should remove the additional insn and
3813 this insn is not init_insns list. */
3814 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3815 || in_list_p (curr_insn
,
3817 [REGNO (dest_reg
)].init_insns
)))
3818 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3820 && in_list_p (curr_insn
,
3822 [REGNO (SET_SRC (set
))].init_insns
)))
3824 /* This is equiv init insn of pseudo which did not get a
3825 hard register -- remove the insn. */
3826 if (lra_dump_file
!= NULL
)
3828 fprintf (lra_dump_file
,
3829 " Removing equiv init insn %i (freq=%d)\n",
3830 INSN_UID (curr_insn
),
3831 BLOCK_FOR_INSN (curr_insn
)->frequency
);
3832 dump_insn_slim (lra_dump_file
, curr_insn
);
3834 if (contains_reg_p (x
, true, false))
3835 lra_risky_transformations_p
= true;
3836 lra_set_insn_deleted (curr_insn
);
3840 curr_id
= lra_get_insn_recog_data (curr_insn
);
3841 curr_static_id
= curr_id
->insn_static_data
;
3842 init_curr_insn_input_reloads ();
3843 init_curr_operand_mode ();
3844 if (curr_insn_transform ())
3846 /* Check non-transformed insns too for equiv change as USE
3847 or CLOBBER don't need reloads but can contain pseudos
3848 being changed on their equivalences. */
3849 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3850 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
3852 lra_update_insn_regno_info (curr_insn
);
3857 bitmap_clear (&equiv_insn_bitmap
);
3858 /* If we used a new hard regno, changed_p should be true because the
3859 hard reg is assigned to a new pseudo. */
3860 #ifdef ENABLE_CHECKING
3863 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3864 if (lra_reg_info
[i
].nrefs
!= 0
3865 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3867 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3869 for (j
= 0; j
< nregs
; j
++)
3870 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
3877 /* Initiate the LRA constraint pass. It is done once per
3880 lra_constraints_init (void)
3884 /* Finalize the LRA constraint pass. It is done once per
3887 lra_constraints_finish (void)
3893 /* This page contains code to do inheritance/split
3896 /* Number of reloads passed so far in current EBB. */
3897 static int reloads_num
;
3899 /* Number of calls passed so far in current EBB. */
3900 static int calls_num
;
3902 /* Current reload pseudo check for validity of elements in
3904 static int curr_usage_insns_check
;
3906 /* Info about last usage of registers in EBB to do inheritance/split
3907 transformation. Inheritance transformation is done from a spilled
3908 pseudo and split transformations from a hard register or a pseudo
3909 assigned to a hard register. */
3912 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
3913 value INSNS is valid. The insns is chain of optional debug insns
3914 and a finishing non-debug insn using the corresponding reg. The
3915 value is also used to mark the registers which are set up in the
3916 current insn. The negated insn uid is used for this. */
3918 /* Value of global reloads_num at the last insn in INSNS. */
3920 /* Value of global reloads_nums at the last insn in INSNS. */
3922 /* It can be true only for splitting. And it means that the restore
3923 insn should be put after insn given by the following member. */
3925 /* Next insns in the current EBB which use the original reg and the
3926 original reg value is not changed between the current insn and
3927 the next insns. In order words, e.g. for inheritance, if we need
3928 to use the original reg value again in the next insns we can try
3929 to use the value in a hard register from a reload insn of the
3934 /* Map: regno -> corresponding pseudo usage insns. */
3935 static struct usage_insns
*usage_insns
;
3938 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
3940 usage_insns
[regno
].check
= curr_usage_insns_check
;
3941 usage_insns
[regno
].insns
= insn
;
3942 usage_insns
[regno
].reloads_num
= reloads_num
;
3943 usage_insns
[regno
].calls_num
= calls_num
;
3944 usage_insns
[regno
].after_p
= after_p
;
3947 /* The function is used to form list REGNO usages which consists of
3948 optional debug insns finished by a non-debug insn using REGNO.
3949 RELOADS_NUM is current number of reload insns processed so far. */
3951 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
3953 rtx next_usage_insns
;
3955 if (usage_insns
[regno
].check
== curr_usage_insns_check
3956 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
3957 && DEBUG_INSN_P (insn
))
3959 /* Check that we did not add the debug insn yet. */
3960 if (next_usage_insns
!= insn
3961 && (GET_CODE (next_usage_insns
) != INSN_LIST
3962 || XEXP (next_usage_insns
, 0) != insn
))
3963 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
3966 else if (NONDEBUG_INSN_P (insn
))
3967 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
3969 usage_insns
[regno
].check
= 0;
3972 /* Replace all references to register OLD_REGNO in *LOC with pseudo
3973 register NEW_REG. Return true if any change was made. */
3975 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
3978 bool result
= false;
3986 code
= GET_CODE (x
);
3987 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
3989 enum machine_mode mode
= GET_MODE (*loc
);
3990 enum machine_mode inner_mode
= GET_MODE (new_reg
);
3992 if (mode
!= inner_mode
)
3994 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
3995 || ! SCALAR_INT_MODE_P (inner_mode
))
3996 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
3998 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4004 /* Scan all the operand sub-expressions. */
4005 fmt
= GET_RTX_FORMAT (code
);
4006 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4010 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4013 else if (fmt
[i
] == 'E')
4015 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4016 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4023 /* Return first non-debug insn in list USAGE_INSNS. */
4025 skip_usage_debug_insns (rtx usage_insns
)
4029 /* Skip debug insns. */
4030 for (insn
= usage_insns
;
4031 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4032 insn
= XEXP (insn
, 1))
4037 /* Return true if we need secondary memory moves for insn in
4038 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4041 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4042 rtx usage_insns ATTRIBUTE_UNUSED
)
4044 #ifndef SECONDARY_MEMORY_NEEDED
4047 rtx insn
, set
, dest
;
4050 if (inher_cl
== ALL_REGS
4051 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4053 lra_assert (INSN_P (insn
));
4054 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4056 dest
= SET_DEST (set
);
4059 lra_assert (inher_cl
!= NO_REGS
);
4060 cl
= get_reg_class (REGNO (dest
));
4061 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4062 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4066 /* Registers involved in inheritance/split in the current EBB
4067 (inheritance/split pseudos and original registers). */
4068 static bitmap_head check_only_regs
;
4070 /* Do inheritance transformations for insn INSN, which defines (if
4071 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4072 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4073 form as the "insns" field of usage_insns. Return true if we
4074 succeed in such transformation.
4076 The transformations look like:
4079 ... p <- i (new insn)
4081 <- ... p ... <- ... i ...
4083 ... i <- p (new insn)
4084 <- ... p ... <- ... i ...
4086 <- ... p ... <- ... i ...
4087 where p is a spilled original pseudo and i is a new inheritance pseudo.
4090 The inheritance pseudo has the smallest class of two classes CL and
4091 class of ORIGINAL REGNO. */
4093 inherit_reload_reg (bool def_p
, int original_regno
,
4094 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4096 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4097 rtx original_reg
= regno_reg_rtx
[original_regno
];
4098 rtx new_reg
, new_insns
, usage_insn
;
4100 lra_assert (! usage_insns
[original_regno
].after_p
);
4101 if (lra_dump_file
!= NULL
)
4102 fprintf (lra_dump_file
,
4103 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4104 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4106 if (lra_dump_file
!= NULL
)
4108 fprintf (lra_dump_file
,
4109 " Rejecting inheritance for %d "
4110 "because of disjoint classes %s and %s\n",
4111 original_regno
, reg_class_names
[cl
],
4112 reg_class_names
[rclass
]);
4113 fprintf (lra_dump_file
,
4114 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4118 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4119 /* We don't use a subset of two classes because it can be
4120 NO_REGS. This transformation is still profitable in most
4121 cases even if the classes are not intersected as register
4122 move is probably cheaper than a memory load. */
4123 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4125 if (lra_dump_file
!= NULL
)
4126 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4127 reg_class_names
[cl
], reg_class_names
[rclass
]);
4131 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4133 /* Reject inheritance resulting in secondary memory moves.
4134 Otherwise, there is a danger in LRA cycling. Also such
4135 transformation will be unprofitable. */
4136 if (lra_dump_file
!= NULL
)
4138 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4139 rtx set
= single_set (insn
);
4141 lra_assert (set
!= NULL_RTX
);
4143 rtx dest
= SET_DEST (set
);
4145 lra_assert (REG_P (dest
));
4146 fprintf (lra_dump_file
,
4147 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4148 "as secondary mem is needed\n",
4149 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4150 original_regno
, reg_class_names
[rclass
]);
4151 fprintf (lra_dump_file
,
4152 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4156 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4157 rclass
, "inheritance");
4160 emit_move_insn (original_reg
, new_reg
);
4162 emit_move_insn (new_reg
, original_reg
);
4163 new_insns
= get_insns ();
4165 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4167 if (lra_dump_file
!= NULL
)
4169 fprintf (lra_dump_file
,
4170 " Rejecting inheritance %d->%d "
4171 "as it results in 2 or more insns:\n",
4172 original_regno
, REGNO (new_reg
));
4173 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4174 fprintf (lra_dump_file
,
4175 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4179 substitute_pseudo (&insn
, original_regno
, new_reg
);
4180 lra_update_insn_regno_info (insn
);
4182 /* We now have a new usage insn for original regno. */
4183 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4184 if (lra_dump_file
!= NULL
)
4185 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4186 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4187 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4188 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4189 bitmap_set_bit (&check_only_regs
, original_regno
);
4190 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4192 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4193 "Add original<-inheritance");
4195 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4196 "Add inheritance<-original");
4197 while (next_usage_insns
!= NULL_RTX
)
4199 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4201 usage_insn
= next_usage_insns
;
4202 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4203 next_usage_insns
= NULL
;
4207 usage_insn
= XEXP (next_usage_insns
, 0);
4208 lra_assert (DEBUG_INSN_P (usage_insn
));
4209 next_usage_insns
= XEXP (next_usage_insns
, 1);
4211 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4212 lra_update_insn_regno_info (usage_insn
);
4213 if (lra_dump_file
!= NULL
)
4215 fprintf (lra_dump_file
,
4216 " Inheritance reuse change %d->%d (bb%d):\n",
4217 original_regno
, REGNO (new_reg
),
4218 BLOCK_FOR_INSN (usage_insn
)->index
);
4219 dump_insn_slim (lra_dump_file
, usage_insn
);
4222 if (lra_dump_file
!= NULL
)
4223 fprintf (lra_dump_file
,
4224 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4228 /* Return true if we need a caller save/restore for pseudo REGNO which
4229 was assigned to a hard register. */
4231 need_for_call_save_p (int regno
)
4233 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4234 return (usage_insns
[regno
].calls_num
< calls_num
4235 && (overlaps_hard_reg_set_p
4237 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])));
4240 /* Global registers occurring in the current EBB. */
4241 static bitmap_head ebb_global_regs
;
4243 /* Return true if we need a split for hard register REGNO or pseudo
4244 REGNO which was assigned to a hard register.
4245 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4246 used for reloads since the EBB end. It is an approximation of the
4247 used hard registers in the split range. The exact value would
4248 require expensive calculations. If we were aggressive with
4249 splitting because of the approximation, the split pseudo will save
4250 the same hard register assignment and will be removed in the undo
4251 pass. We still need the approximation because too aggressive
4252 splitting would result in too inaccurate cost calculation in the
4253 assignment pass because of too many generated moves which will be
4254 probably removed in the undo pass. */
4256 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4258 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4260 lra_assert (hard_regno
>= 0);
4261 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4262 /* Don't split eliminable hard registers, otherwise we can
4263 split hard registers like hard frame pointer, which
4264 lives on BB start/end according to DF-infrastructure,
4265 when there is a pseudo assigned to the register and
4266 living in the same BB. */
4267 && (regno
>= FIRST_PSEUDO_REGISTER
4268 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4269 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4270 /* Don't split call clobbered hard regs living through
4271 calls, otherwise we might have a check problem in the
4272 assign sub-pass as in the most cases (exception is a
4273 situation when lra_risky_transformations_p value is
4274 true) the assign pass assumes that all pseudos living
4275 through calls are assigned to call saved hard regs. */
4276 && (regno
>= FIRST_PSEUDO_REGISTER
4277 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4278 || usage_insns
[regno
].calls_num
== calls_num
)
4279 /* We need at least 2 reloads to make pseudo splitting
4280 profitable. We should provide hard regno splitting in
4281 any case to solve 1st insn scheduling problem when
4282 moving hard register definition up might result in
4283 impossibility to find hard register for reload pseudo of
4284 small register class. */
4285 && (usage_insns
[regno
].reloads_num
4286 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4287 && (regno
< FIRST_PSEUDO_REGISTER
4288 /* For short living pseudos, spilling + inheritance can
4289 be considered a substitution for splitting.
4290 Therefore we do not splitting for local pseudos. It
4291 decreases also aggressiveness of splitting. The
4292 minimal number of references is chosen taking into
4293 account that for 2 references splitting has no sense
4294 as we can just spill the pseudo. */
4295 || (regno
>= FIRST_PSEUDO_REGISTER
4296 && lra_reg_info
[regno
].nrefs
> 3
4297 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4298 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4301 /* Return class for the split pseudo created from original pseudo with
4302 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4303 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4304 results in no secondary memory movements. */
4305 static enum reg_class
4306 choose_split_class (enum reg_class allocno_class
,
4307 int hard_regno ATTRIBUTE_UNUSED
,
4308 enum machine_mode mode ATTRIBUTE_UNUSED
)
4310 #ifndef SECONDARY_MEMORY_NEEDED
4311 return allocno_class
;
4314 enum reg_class cl
, best_cl
= NO_REGS
;
4315 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4316 = REGNO_REG_CLASS (hard_regno
);
4318 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4319 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4320 return allocno_class
;
4322 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4324 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4325 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4326 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4327 && (best_cl
== NO_REGS
4328 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4334 /* Do split transformations for insn INSN, which defines or uses
4335 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4336 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4337 "insns" field of usage_insns.
4339 The transformations look like:
4342 ... s <- p (new insn -- save)
4344 ... p <- s (new insn -- restore)
4345 <- ... p ... <- ... p ...
4347 <- ... p ... <- ... p ...
4348 ... s <- p (new insn -- save)
4350 ... p <- s (new insn -- restore)
4351 <- ... p ... <- ... p ...
4353 where p is an original pseudo got a hard register or a hard
4354 register and s is a new split pseudo. The save is put before INSN
4355 if BEFORE_P is true. Return true if we succeed in such
4358 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4360 enum reg_class rclass
;
4362 int hard_regno
, nregs
;
4363 rtx new_reg
, save
, restore
, usage_insn
;
4367 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4369 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4370 hard_regno
= original_regno
;
4371 call_save_p
= false;
4376 hard_regno
= reg_renumber
[original_regno
];
4377 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4378 rclass
= lra_get_allocno_class (original_regno
);
4379 original_reg
= regno_reg_rtx
[original_regno
];
4380 call_save_p
= need_for_call_save_p (original_regno
);
4382 original_reg
= regno_reg_rtx
[original_regno
];
4383 lra_assert (hard_regno
>= 0);
4384 if (lra_dump_file
!= NULL
)
4385 fprintf (lra_dump_file
,
4386 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4389 enum machine_mode sec_mode
;
4391 #ifdef SECONDARY_MEMORY_NEEDED_MODE
4392 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (original_reg
));
4394 sec_mode
= GET_MODE (original_reg
);
4396 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
4401 rclass
= choose_split_class (rclass
, hard_regno
,
4402 GET_MODE (original_reg
));
4403 if (rclass
== NO_REGS
)
4405 if (lra_dump_file
!= NULL
)
4407 fprintf (lra_dump_file
,
4408 " Rejecting split of %d(%s): "
4409 "no good reg class for %d(%s)\n",
4411 reg_class_names
[lra_get_allocno_class (original_regno
)],
4413 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4416 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4420 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4422 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4424 save
= emit_spill_move (true, new_reg
, original_reg
);
4425 if (NEXT_INSN (save
) != NULL_RTX
)
4427 lra_assert (! call_save_p
);
4428 if (lra_dump_file
!= NULL
)
4432 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4433 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4434 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4435 fprintf (lra_dump_file
,
4436 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4440 restore
= emit_spill_move (false, new_reg
, original_reg
);
4441 if (NEXT_INSN (restore
) != NULL_RTX
)
4443 lra_assert (! call_save_p
);
4444 if (lra_dump_file
!= NULL
)
4446 fprintf (lra_dump_file
,
4447 " Rejecting split %d->%d "
4448 "resulting in > 2 %s restore insns:\n",
4449 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4450 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4451 fprintf (lra_dump_file
,
4452 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4456 after_p
= usage_insns
[original_regno
].after_p
;
4457 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4458 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4459 bitmap_set_bit (&check_only_regs
, original_regno
);
4460 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4463 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4465 usage_insn
= next_usage_insns
;
4468 usage_insn
= XEXP (next_usage_insns
, 0);
4469 lra_assert (DEBUG_INSN_P (usage_insn
));
4470 next_usage_insns
= XEXP (next_usage_insns
, 1);
4471 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4472 lra_update_insn_regno_info (usage_insn
);
4473 if (lra_dump_file
!= NULL
)
4475 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4476 original_regno
, REGNO (new_reg
));
4477 dump_insn_slim (lra_dump_file
, usage_insn
);
4480 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4481 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4482 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4483 after_p
? restore
: NULL_RTX
,
4485 ? "Add reg<-save" : "Add reg<-split");
4486 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4487 before_p
? NULL_RTX
: save
,
4489 ? "Add save<-reg" : "Add split<-reg");
4491 /* If we are trying to split multi-register. We should check
4492 conflicts on the next assignment sub-pass. IRA can allocate on
4493 sub-register levels, LRA do this on pseudos level right now and
4494 this discrepancy may create allocation conflicts after
4496 lra_risky_transformations_p
= true;
4497 if (lra_dump_file
!= NULL
)
4498 fprintf (lra_dump_file
,
4499 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4503 /* Recognize that we need a split transformation for insn INSN, which
4504 defines or uses REGNO in its insn biggest MODE (we use it only if
4505 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4506 hard registers which might be used for reloads since the EBB end.
4507 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4508 uid before starting INSN processing. Return true if we succeed in
4509 such transformation. */
4511 split_if_necessary (int regno
, enum machine_mode mode
,
4512 HARD_REG_SET potential_reload_hard_regs
,
4513 bool before_p
, rtx insn
, int max_uid
)
4517 rtx next_usage_insns
;
4519 if (regno
< FIRST_PSEUDO_REGISTER
)
4520 nregs
= hard_regno_nregs
[regno
][mode
];
4521 for (i
= 0; i
< nregs
; i
++)
4522 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4523 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4524 /* To avoid processing the register twice or more. */
4525 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4526 && INSN_UID (next_usage_insns
) < max_uid
)
4527 || (GET_CODE (next_usage_insns
) == INSN_LIST
4528 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4529 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4530 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4535 /* Check only registers living at the current program point in the
4537 static bitmap_head live_regs
;
4539 /* Update live info in EBB given by its HEAD and TAIL insns after
4540 inheritance/split transformation. The function removes dead moves
4543 update_ebb_live_info (rtx head
, rtx tail
)
4550 basic_block last_bb
, prev_bb
, curr_bb
;
4552 struct lra_insn_reg
*reg
;
4556 last_bb
= BLOCK_FOR_INSN (tail
);
4558 for (curr_insn
= tail
;
4559 curr_insn
!= PREV_INSN (head
);
4560 curr_insn
= prev_insn
)
4562 prev_insn
= PREV_INSN (curr_insn
);
4563 /* We need to process empty blocks too. They contain
4564 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4565 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4567 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4568 if (curr_bb
!= prev_bb
)
4570 if (prev_bb
!= NULL
)
4572 /* Update df_get_live_in (prev_bb): */
4573 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4574 if (bitmap_bit_p (&live_regs
, j
))
4575 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4577 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4579 if (curr_bb
!= last_bb
)
4581 /* Update df_get_live_out (curr_bb): */
4582 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4584 live_p
= bitmap_bit_p (&live_regs
, j
);
4586 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4587 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4593 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4595 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4599 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4601 if (! NONDEBUG_INSN_P (curr_insn
))
4603 curr_id
= lra_get_insn_recog_data (curr_insn
);
4605 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4606 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4607 && bitmap_bit_p (&check_only_regs
, regno
)
4608 && ! bitmap_bit_p (&live_regs
, regno
))
4610 /* See which defined values die here. */
4611 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4612 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4613 bitmap_clear_bit (&live_regs
, reg
->regno
);
4614 /* Mark each used value as live. */
4615 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4616 if (reg
->type
!= OP_OUT
4617 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4618 bitmap_set_bit (&live_regs
, reg
->regno
);
4619 /* It is quite important to remove dead move insns because it
4620 means removing dead store. We don't need to process them for
4624 if (lra_dump_file
!= NULL
)
4626 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4627 dump_insn_slim (lra_dump_file
, curr_insn
);
4629 lra_set_insn_deleted (curr_insn
);
4634 /* The structure describes info to do an inheritance for the current
4635 insn. We need to collect such info first before doing the
4636 transformations because the transformations change the insn
4637 internal representation. */
4640 /* Original regno. */
4642 /* Subsequent insns which can inherit original reg value. */
4646 /* Array containing all info for doing inheritance from the current
4648 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4650 /* Number elements in the previous array. */
4651 static int to_inherit_num
;
4653 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4654 structure to_inherit. */
4656 add_to_inherit (int regno
, rtx insns
)
4660 for (i
= 0; i
< to_inherit_num
; i
++)
4661 if (to_inherit
[i
].regno
== regno
)
4663 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4664 to_inherit
[to_inherit_num
].regno
= regno
;
4665 to_inherit
[to_inherit_num
++].insns
= insns
;
4668 /* Return the last non-debug insn in basic block BB, or the block begin
4671 get_last_insertion_point (basic_block bb
)
4675 FOR_BB_INSNS_REVERSE (bb
, insn
)
4676 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4681 /* Set up RES by registers living on edges FROM except the edge (FROM,
4682 TO) or by registers set up in a jump insn in BB FROM. */
4684 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4687 struct lra_insn_reg
*reg
;
4691 lra_assert (to
!= NULL
);
4693 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4695 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4696 last
= get_last_insertion_point (from
);
4697 if (! JUMP_P (last
))
4699 curr_id
= lra_get_insn_recog_data (last
);
4700 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4701 if (reg
->type
!= OP_IN
)
4702 bitmap_set_bit (res
, reg
->regno
);
4705 /* Used as a temporary results of some bitmap calculations. */
4706 static bitmap_head temp_bitmap
;
4708 /* Do inheritance/split transformations in EBB starting with HEAD and
4709 finishing on TAIL. We process EBB insns in the reverse order.
4710 Return true if we did any inheritance/split transformation in the
4713 We should avoid excessive splitting which results in worse code
4714 because of inaccurate cost calculations for spilling new split
4715 pseudos in such case. To achieve this we do splitting only if
4716 register pressure is high in given basic block and there are reload
4717 pseudos requiring hard registers. We could do more register
4718 pressure calculations at any given program point to avoid necessary
4719 splitting even more but it is to expensive and the current approach
4720 works well enough. */
4722 inherit_in_ebb (rtx head
, rtx tail
)
4724 int i
, src_regno
, dst_regno
, nregs
;
4725 bool change_p
, succ_p
;
4726 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4728 struct lra_insn_reg
*reg
;
4729 basic_block last_processed_bb
, curr_bb
= NULL
;
4730 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4734 bool head_p
, after_p
;
4737 curr_usage_insns_check
++;
4738 reloads_num
= calls_num
= 0;
4739 bitmap_clear (&check_only_regs
);
4740 last_processed_bb
= NULL
;
4741 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4742 CLEAR_HARD_REG_SET (live_hard_regs
);
4743 /* We don't process new insns generated in the loop. */
4744 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4746 prev_insn
= PREV_INSN (curr_insn
);
4747 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4748 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4749 if (last_processed_bb
!= curr_bb
)
4751 /* We are at the end of BB. Add qualified living
4752 pseudos for potential splitting. */
4753 to_process
= df_get_live_out (curr_bb
);
4754 if (last_processed_bb
!= NULL
)
4756 /* We are somewhere in the middle of EBB. */
4757 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4759 to_process
= &temp_bitmap
;
4761 last_processed_bb
= curr_bb
;
4762 last_insn
= get_last_insertion_point (curr_bb
);
4763 after_p
= (! JUMP_P (last_insn
)
4764 && (! CALL_P (last_insn
)
4765 || (find_reg_note (last_insn
,
4766 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4767 && ! SIBLING_CALL_P (last_insn
))));
4768 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4769 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4770 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4771 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4772 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4774 if ((int) j
>= lra_constraint_new_regno_start
)
4776 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4778 if (j
< FIRST_PSEUDO_REGISTER
)
4779 SET_HARD_REG_BIT (live_hard_regs
, j
);
4781 add_to_hard_reg_set (&live_hard_regs
,
4782 PSEUDO_REGNO_MODE (j
),
4784 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4788 src_regno
= dst_regno
= -1;
4789 if (NONDEBUG_INSN_P (curr_insn
)
4790 && (set
= single_set (curr_insn
)) != NULL_RTX
4791 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4793 src_regno
= REGNO (SET_SRC (set
));
4794 dst_regno
= REGNO (SET_DEST (set
));
4796 if (src_regno
< lra_constraint_new_regno_start
4797 && src_regno
>= FIRST_PSEUDO_REGISTER
4798 && reg_renumber
[src_regno
] < 0
4799 && dst_regno
>= lra_constraint_new_regno_start
4800 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4802 /* 'reload_pseudo <- original_pseudo'. */
4805 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4806 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4807 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4808 curr_insn
, next_usage_insns
);
4812 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4813 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4814 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4815 reg_class_contents
[cl
]);
4817 else if (src_regno
>= lra_constraint_new_regno_start
4818 && dst_regno
< lra_constraint_new_regno_start
4819 && dst_regno
>= FIRST_PSEUDO_REGISTER
4820 && reg_renumber
[dst_regno
] < 0
4821 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
4822 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4823 && (next_usage_insns
4824 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4827 /* 'original_pseudo <- reload_pseudo'. */
4828 if (! JUMP_P (curr_insn
)
4829 && inherit_reload_reg (true, dst_regno
, cl
,
4830 curr_insn
, next_usage_insns
))
4833 usage_insns
[dst_regno
].check
= 0;
4834 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4835 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4836 reg_class_contents
[cl
]);
4838 else if (INSN_P (curr_insn
))
4841 int max_uid
= get_max_uid ();
4843 curr_id
= lra_get_insn_recog_data (curr_insn
);
4844 curr_static_id
= curr_id
->insn_static_data
;
4846 /* Process insn definitions. */
4847 for (iter
= 0; iter
< 2; iter
++)
4848 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
4851 if (reg
->type
!= OP_IN
4852 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4854 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
4855 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
4856 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4857 && (next_usage_insns
4858 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4860 struct lra_insn_reg
*r
;
4862 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
4863 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
4865 /* Don't do inheritance if the pseudo is also
4866 used in the insn. */
4868 /* We can not do inheritance right now
4869 because the current insn reg info (chain
4870 regs) can change after that. */
4871 add_to_inherit (dst_regno
, next_usage_insns
);
4873 /* We can not process one reg twice here because of
4874 usage_insns invalidation. */
4875 if ((dst_regno
< FIRST_PSEUDO_REGISTER
4876 || reg_renumber
[dst_regno
] >= 0)
4877 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
4881 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
4882 potential_reload_hard_regs
,
4883 false, curr_insn
, max_uid
))
4885 CLEAR_HARD_REG_SET (s
);
4886 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
4887 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
4889 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
4890 reg_renumber
[dst_regno
]);
4891 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
4893 /* We should invalidate potential inheritance or
4894 splitting for the current insn usages to the next
4895 usage insns (see code below) as the output pseudo
4897 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
4898 && reg_renumber
[dst_regno
] < 0)
4899 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
4900 && (dst_regno
< FIRST_PSEUDO_REGISTER
4901 || reg_renumber
[dst_regno
] >= 0)))
4903 /* Invalidate and mark definitions. */
4904 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
4905 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
4908 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
4909 for (i
= 0; i
< nregs
; i
++)
4910 usage_insns
[dst_regno
+ i
].check
4911 = -(int) INSN_UID (curr_insn
);
4915 if (! JUMP_P (curr_insn
))
4916 for (i
= 0; i
< to_inherit_num
; i
++)
4917 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
4918 ALL_REGS
, curr_insn
,
4919 to_inherit
[i
].insns
))
4921 if (CALL_P (curr_insn
))
4923 rtx cheap
, pat
, dest
, restore
;
4924 int regno
, hard_regno
;
4927 if ((cheap
= find_reg_note (curr_insn
,
4928 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
4929 && ((cheap
= XEXP (cheap
, 0)), true)
4930 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
4931 && (hard_regno
= reg_renumber
[regno
]) >= 0
4932 /* If there are pending saves/restores, the
4933 optimization is not worth. */
4934 && usage_insns
[regno
].calls_num
== calls_num
- 1
4935 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
4937 /* Restore the pseudo from the call result as
4938 REG_RETURNED note says that the pseudo value is
4939 in the call result and the pseudo is an argument
4941 pat
= PATTERN (curr_insn
);
4942 if (GET_CODE (pat
) == PARALLEL
)
4943 pat
= XVECEXP (pat
, 0, 0);
4944 dest
= SET_DEST (pat
);
4946 emit_move_insn (cheap
, copy_rtx (dest
));
4947 restore
= get_insns ();
4949 lra_process_new_insns (curr_insn
, NULL
, restore
,
4950 "Inserting call parameter restore");
4951 /* We don't need to save/restore of the pseudo from
4953 usage_insns
[regno
].calls_num
= calls_num
;
4954 bitmap_set_bit (&check_only_regs
, regno
);
4958 /* Process insn usages. */
4959 for (iter
= 0; iter
< 2; iter
++)
4960 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
4963 if ((reg
->type
!= OP_OUT
4964 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
4965 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4967 if (src_regno
>= FIRST_PSEUDO_REGISTER
4968 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
4970 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4971 && (next_usage_insns
4972 = usage_insns
[src_regno
].insns
) != NULL_RTX
4973 && NONDEBUG_INSN_P (curr_insn
))
4974 add_to_inherit (src_regno
, next_usage_insns
);
4975 else if (usage_insns
[src_regno
].check
4976 != -(int) INSN_UID (curr_insn
))
4977 /* Add usages but only if the reg is not set up
4978 in the same insn. */
4979 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
4981 else if (src_regno
< FIRST_PSEUDO_REGISTER
4982 || reg_renumber
[src_regno
] >= 0)
4985 rtx use_insn
= curr_insn
;
4987 before_p
= (JUMP_P (curr_insn
)
4988 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
4989 if (NONDEBUG_INSN_P (curr_insn
)
4990 && split_if_necessary (src_regno
, reg
->biggest_mode
,
4991 potential_reload_hard_regs
,
4992 before_p
, curr_insn
, max_uid
))
4995 lra_risky_transformations_p
= true;
4998 usage_insns
[src_regno
].check
= 0;
5000 use_insn
= PREV_INSN (curr_insn
);
5002 if (NONDEBUG_INSN_P (curr_insn
))
5004 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5005 add_to_hard_reg_set (&live_hard_regs
,
5006 reg
->biggest_mode
, src_regno
);
5008 add_to_hard_reg_set (&live_hard_regs
,
5009 PSEUDO_REGNO_MODE (src_regno
),
5010 reg_renumber
[src_regno
]);
5012 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5015 for (i
= 0; i
< to_inherit_num
; i
++)
5017 src_regno
= to_inherit
[i
].regno
;
5018 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5019 curr_insn
, to_inherit
[i
].insns
))
5022 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5025 /* We reached the start of the current basic block. */
5026 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5027 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5029 /* We reached the beginning of the current block -- do
5030 rest of spliting in the current BB. */
5031 to_process
= df_get_live_in (curr_bb
);
5032 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5034 /* We are somewhere in the middle of EBB. */
5035 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5036 curr_bb
, &temp_bitmap
);
5037 to_process
= &temp_bitmap
;
5040 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5042 if ((int) j
>= lra_constraint_new_regno_start
)
5044 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5045 && usage_insns
[j
].check
== curr_usage_insns_check
5046 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5048 if (need_for_split_p (potential_reload_hard_regs
, j
))
5050 if (lra_dump_file
!= NULL
&& head_p
)
5052 fprintf (lra_dump_file
,
5053 " ----------------------------------\n");
5056 if (split_reg (false, j
, bb_note (curr_bb
),
5060 usage_insns
[j
].check
= 0;
5068 /* This value affects EBB forming. If probability of edge from EBB to
5069 a BB is not greater than the following value, we don't add the BB
5071 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5073 /* Current number of inheritance/split iteration. */
5074 int lra_inheritance_iter
;
5076 /* Entry function for inheritance/split pass. */
5078 lra_inheritance (void)
5081 basic_block bb
, start_bb
;
5084 lra_inheritance_iter
++;
5085 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5087 timevar_push (TV_LRA_INHERITANCE
);
5088 if (lra_dump_file
!= NULL
)
5089 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5090 lra_inheritance_iter
);
5091 curr_usage_insns_check
= 0;
5092 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5093 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5094 usage_insns
[i
].check
= 0;
5095 bitmap_initialize (&check_only_regs
, ®_obstack
);
5096 bitmap_initialize (&live_regs
, ®_obstack
);
5097 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5098 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5102 if (lra_dump_file
!= NULL
)
5103 fprintf (lra_dump_file
, "EBB");
5104 /* Form a EBB starting with BB. */
5105 bitmap_clear (&ebb_global_regs
);
5106 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5109 if (lra_dump_file
!= NULL
)
5110 fprintf (lra_dump_file
, " %d", bb
->index
);
5111 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
5113 e
= find_fallthru_edge (bb
->succs
);
5116 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5120 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5121 if (lra_dump_file
!= NULL
)
5122 fprintf (lra_dump_file
, "\n");
5123 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5124 /* Remember that the EBB head and tail can change in
5126 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5128 bitmap_clear (&ebb_global_regs
);
5129 bitmap_clear (&temp_bitmap
);
5130 bitmap_clear (&live_regs
);
5131 bitmap_clear (&check_only_regs
);
5134 timevar_pop (TV_LRA_INHERITANCE
);
5139 /* This page contains code to undo failed inheritance/split
5142 /* Current number of iteration undoing inheritance/split. */
5143 int lra_undo_inheritance_iter
;
5145 /* Fix BB live info LIVE after removing pseudos created on pass doing
5146 inheritance/split which are REMOVED_PSEUDOS. */
5148 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5153 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5154 if (bitmap_clear_bit (live
, regno
))
5155 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5158 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5163 if (GET_CODE (reg
) == SUBREG
)
5164 reg
= SUBREG_REG (reg
);
5170 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5171 return true if we did any change. The undo transformations for
5172 inheritance looks like
5176 p <- i, i <- p, and i <- i3
5177 where p is original pseudo from which inheritance pseudo i was
5178 created, i and i3 are removed inheritance pseudos, i2 is another
5179 not removed inheritance pseudo. All split pseudos or other
5180 occurrences of removed inheritance pseudos are changed on the
5181 corresponding original pseudos.
5183 The function also schedules insns changed and created during
5184 inheritance/split pass for processing by the subsequent constraint
5187 remove_inheritance_pseudos (bitmap remove_pseudos
)
5190 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5191 rtx set
, prev_set
, prev_insn
;
5192 bool change_p
, done_p
;
5194 change_p
= ! bitmap_empty_p (remove_pseudos
);
5195 /* We can not finish the function right away if CHANGE_P is true
5196 because we need to marks insns affected by previous
5197 inheritance/split pass for processing by the subsequent
5201 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5202 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5203 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5205 if (! INSN_P (curr_insn
))
5208 sregno
= dregno
= -1;
5209 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5210 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5212 dregno
= get_regno (SET_DEST (set
));
5213 sregno
= get_regno (SET_SRC (set
));
5216 if (sregno
>= 0 && dregno
>= 0)
5218 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5219 && (lra_reg_info
[sregno
].restore_regno
== dregno
5220 || (bitmap_bit_p (remove_pseudos
, dregno
)
5221 && (lra_reg_info
[sregno
].restore_regno
5222 == lra_reg_info
[dregno
].restore_regno
))))
5223 || (bitmap_bit_p (remove_pseudos
, dregno
)
5224 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5225 /* One of the following cases:
5226 original <- removed inheritance pseudo
5227 removed inherit pseudo <- another removed inherit pseudo
5228 removed inherit pseudo <- original pseudo
5230 removed_split_pseudo <- original_reg
5231 original_reg <- removed_split_pseudo */
5233 if (lra_dump_file
!= NULL
)
5235 fprintf (lra_dump_file
, " Removing %s:\n",
5236 bitmap_bit_p (&lra_split_regs
, sregno
)
5237 || bitmap_bit_p (&lra_split_regs
, dregno
)
5238 ? "split" : "inheritance");
5239 dump_insn_slim (lra_dump_file
, curr_insn
);
5241 lra_set_insn_deleted (curr_insn
);
5244 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5245 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5247 /* Search the following pattern:
5248 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5249 original_pseudo <- inherit_or_split_pseudo1
5250 where the 2nd insn is the current insn and
5251 inherit_or_split_pseudo2 is not removed. If it is found,
5252 change the current insn onto:
5253 original_pseudo <- inherit_or_split_pseudo2. */
5254 for (prev_insn
= PREV_INSN (curr_insn
);
5255 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5256 prev_insn
= PREV_INSN (prev_insn
))
5258 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5259 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5260 /* There should be no subregs in insn we are
5261 searching because only the original reg might
5262 be in subreg when we changed the mode of
5263 load/store for splitting. */
5264 && REG_P (SET_DEST (prev_set
))
5265 && REG_P (SET_SRC (prev_set
))
5266 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5267 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5268 >= FIRST_PSEUDO_REGISTER
)
5269 /* As we consider chain of inheritance or
5270 splitting described in above comment we should
5271 check that sregno and prev_sregno were
5272 inheritance/split pseudos created from the
5273 same original regno. */
5274 && (lra_reg_info
[sregno
].restore_regno
5275 == lra_reg_info
[prev_sregno
].restore_regno
)
5276 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5278 lra_assert (GET_MODE (SET_SRC (prev_set
))
5279 == GET_MODE (regno_reg_rtx
[sregno
]));
5280 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5281 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5283 SET_SRC (set
) = SET_SRC (prev_set
);
5284 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5285 lra_set_used_insn_alternative_by_uid
5286 (INSN_UID (curr_insn
), -1);
5288 if (lra_dump_file
!= NULL
)
5290 fprintf (lra_dump_file
, " Change reload insn:\n");
5291 dump_insn_slim (lra_dump_file
, curr_insn
);
5298 struct lra_insn_reg
*reg
;
5299 bool restored_regs_p
= false;
5300 bool kept_regs_p
= false;
5302 curr_id
= lra_get_insn_recog_data (curr_insn
);
5303 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5306 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5307 if (restore_regno
>= 0)
5309 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5311 substitute_pseudo (&curr_insn
, regno
,
5312 regno_reg_rtx
[restore_regno
]);
5313 restored_regs_p
= true;
5319 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5321 /* The instruction has changed since the previous
5322 constraints pass. */
5323 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5324 lra_set_used_insn_alternative_by_uid
5325 (INSN_UID (curr_insn
), -1);
5327 else if (restored_regs_p
)
5328 /* The instruction has been restored to the form that
5329 it had during the previous constraints pass. */
5330 lra_update_insn_regno_info (curr_insn
);
5331 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5333 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5334 dump_insn_slim (lra_dump_file
, curr_insn
);
5342 /* If optional reload pseudos failed to get a hard register or was not
5343 inherited, it is better to remove optional reloads. We do this
5344 transformation after undoing inheritance to figure out necessity to
5345 remove optional reloads easier. Return true if we do any
5348 undo_optional_reloads (void)
5351 unsigned int regno
, uid
;
5352 bitmap_iterator bi
, bi2
;
5353 rtx insn
, set
, src
, dest
;
5354 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5356 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5357 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5358 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5359 if (reg_renumber
[regno
] >= 0)
5360 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5362 insn
= lra_insn_recog_data
[uid
]->insn
;
5363 if ((set
= single_set (insn
)) == NULL_RTX
)
5365 src
= SET_SRC (set
);
5366 dest
= SET_DEST (set
);
5367 if (! REG_P (src
) || ! REG_P (dest
))
5369 if ((REGNO (src
) == regno
5370 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (dest
))
5371 || (REGNO (dest
) == regno
5372 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)))
5374 /* Optional reload was inherited. Keep it. */
5375 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5376 if (lra_dump_file
!= NULL
)
5377 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5380 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5381 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5382 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5384 if (lra_dump_file
!= NULL
)
5385 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5386 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5387 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5389 insn
= lra_insn_recog_data
[uid
]->insn
;
5390 if ((set
= single_set (insn
)) != NULL_RTX
)
5392 src
= SET_SRC (set
);
5393 dest
= SET_DEST (set
);
5394 if (REG_P (src
) && REG_P (dest
)
5395 && ((REGNO (src
) == regno
5396 && (lra_reg_info
[regno
].restore_regno
5397 == (int) REGNO (dest
)))
5398 || (REGNO (dest
) == regno
5399 && (lra_reg_info
[regno
].restore_regno
5400 == (int) REGNO (src
)))))
5402 if (lra_dump_file
!= NULL
)
5404 fprintf (lra_dump_file
, " Deleting move %u\n",
5406 dump_insn_slim (lra_dump_file
, insn
);
5408 lra_set_insn_deleted (insn
);
5411 /* We should not worry about generation memory-memory
5412 moves here as if the corresponding inheritance did
5413 not work (inheritance pseudo did not get a hard reg),
5414 we remove the inheritance pseudo and the optional
5417 substitute_pseudo (&insn
, regno
,
5418 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5419 lra_update_insn_regno_info (insn
);
5420 if (lra_dump_file
!= NULL
)
5422 fprintf (lra_dump_file
,
5423 " Restoring original insn:\n");
5424 dump_insn_slim (lra_dump_file
, insn
);
5428 /* Clear restore_regnos. */
5429 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5430 lra_reg_info
[regno
].restore_regno
= -1;
5431 bitmap_clear (&insn_bitmap
);
5432 bitmap_clear (&removed_optional_reload_pseudos
);
5436 /* Entry function for undoing inheritance/split transformation. Return true
5437 if we did any RTL change in this pass. */
5439 lra_undo_inheritance (void)
5442 int restore_regno
, hard_regno
;
5443 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5444 bitmap_head remove_pseudos
;
5448 lra_undo_inheritance_iter
++;
5449 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5451 if (lra_dump_file
!= NULL
)
5452 fprintf (lra_dump_file
,
5453 "\n********** Undoing inheritance #%d: **********\n\n",
5454 lra_undo_inheritance_iter
);
5455 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5456 n_inherit
= n_all_inherit
= 0;
5457 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5458 if (lra_reg_info
[regno
].restore_regno
>= 0)
5461 if (reg_renumber
[regno
] < 0)
5462 bitmap_set_bit (&remove_pseudos
, regno
);
5466 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5467 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5468 n_inherit
, n_all_inherit
,
5469 (double) n_inherit
/ n_all_inherit
* 100);
5470 n_split
= n_all_split
= 0;
5471 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5472 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5475 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5476 ? reg_renumber
[restore_regno
] : restore_regno
);
5477 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5478 bitmap_set_bit (&remove_pseudos
, regno
);
5482 if (lra_dump_file
!= NULL
)
5483 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5484 regno
, restore_regno
);
5487 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5488 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5489 n_split
, n_all_split
,
5490 (double) n_split
/ n_all_split
* 100);
5491 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5492 bitmap_clear (&remove_pseudos
);
5493 /* Clear restore_regnos. */
5494 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5495 lra_reg_info
[regno
].restore_regno
= -1;
5496 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5497 lra_reg_info
[regno
].restore_regno
= -1;
5498 change_p
= undo_optional_reloads () || change_p
;