1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2016 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (match_operand 0 "register_operand")
121 if (GET_CODE (op) == SUBREG)
122 op = SUBREG_REG (op);
127 return CA_REGNO_P (REGNO (op));
130 ;; Return 1 if op is a signed 5-bit constant integer.
131 (define_predicate "s5bit_cint_operand"
132 (and (match_code "const_int")
133 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
135 ;; Return 1 if op is a unsigned 3-bit constant integer.
136 (define_predicate "u3bit_cint_operand"
137 (and (match_code "const_int")
138 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
140 ;; Return 1 if op is a unsigned 5-bit constant integer.
141 (define_predicate "u5bit_cint_operand"
142 (and (match_code "const_int")
143 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
145 ;; Return 1 if op is a unsigned 6-bit constant integer.
146 (define_predicate "u6bit_cint_operand"
147 (and (match_code "const_int")
148 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63")))
150 ;; Return 1 if op is a signed 8-bit constant integer.
151 ;; Integer multiplication complete more quickly
152 (define_predicate "s8bit_cint_operand"
153 (and (match_code "const_int")
154 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
156 ;; Return 1 if op is a unsigned 10-bit constant integer.
157 (define_predicate "u10bit_cint_operand"
158 (and (match_code "const_int")
159 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
161 ;; Return 1 if op is a constant integer that can fit in a D field.
162 (define_predicate "short_cint_operand"
163 (and (match_code "const_int")
164 (match_test "satisfies_constraint_I (op)")))
166 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
167 (define_predicate "u_short_cint_operand"
168 (and (match_code "const_int")
169 (match_test "satisfies_constraint_K (op)")))
171 ;; Return 1 if op is a constant integer that is a signed 16-bit constant
172 ;; shifted left 16 bits
173 (define_predicate "upper16_cint_operand"
174 (and (match_code "const_int")
175 (match_test "satisfies_constraint_L (op)")))
177 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
178 (define_predicate "non_short_cint_operand"
179 (and (match_code "const_int")
180 (match_test "(unsigned HOST_WIDE_INT)
181 (INTVAL (op) + 0x8000) >= 0x10000")))
183 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
184 (define_predicate "exact_log2_cint_operand"
185 (and (match_code "const_int")
186 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
188 ;; Match op = 0 or op = 1.
189 (define_predicate "const_0_to_1_operand"
190 (and (match_code "const_int")
191 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
194 (define_predicate "const_0_to_3_operand"
195 (and (match_code "const_int")
196 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
198 ;; Match op = 2 or op = 3.
199 (define_predicate "const_2_to_3_operand"
200 (and (match_code "const_int")
201 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
204 (define_predicate "const_0_to_15_operand"
205 (and (match_code "const_int")
206 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
208 ;; Return 1 if op is a register that is not special.
209 (define_predicate "gpc_reg_operand"
210 (match_operand 0 "register_operand")
212 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
215 if (GET_CODE (op) == SUBREG)
216 op = SUBREG_REG (op);
221 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
224 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
227 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
230 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
233 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
234 ;; allow floating point or vector registers.
235 (define_predicate "int_reg_operand"
236 (match_operand 0 "register_operand")
238 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
241 if (GET_CODE (op) == SUBREG)
242 op = SUBREG_REG (op);
247 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
250 return INT_REGNO_P (REGNO (op));
253 ;; Like int_reg_operand, but don't return true for pseudo registers
254 (define_predicate "int_reg_operand_not_pseudo"
255 (match_operand 0 "register_operand")
257 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
260 if (GET_CODE (op) == SUBREG)
261 op = SUBREG_REG (op);
266 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
269 return INT_REGNO_P (REGNO (op));
272 ;; Like int_reg_operand, but only return true for base registers
273 (define_predicate "base_reg_operand"
274 (match_operand 0 "int_reg_operand")
276 if (GET_CODE (op) == SUBREG)
277 op = SUBREG_REG (op);
282 return (REGNO (op) != FIRST_GPR_REGNO);
286 ;; Return true if this is a traditional floating point register
287 (define_predicate "fpr_reg_operand"
288 (match_code "reg,subreg")
292 if (GET_CODE (op) == SUBREG)
293 op = SUBREG_REG (op);
299 if (r >= FIRST_PSEUDO_REGISTER)
302 return FP_REGNO_P (r);
305 ;; Return true if this is a register that can has D-form addressing (GPR and
306 ;; traditional FPR registers for scalars). ISA 3.0 (power9) adds D-form
307 ;; addressing for scalars in Altivec registers.
309 ;; If this is a pseudo only allow for GPR fusion in power8. If we have the
310 ;; power9 fusion allow the floating point types.
311 (define_predicate "toc_fusion_or_p9_reg_operand"
312 (match_code "reg,subreg")
315 bool gpr_p = (mode == QImode || mode == HImode || mode == SImode
317 || (TARGET_POWERPC64 && (mode == DImode || mode == DFmode)));
318 bool fpr_p = (TARGET_P9_FUSION
319 && (mode == DFmode || mode == SFmode
320 || (TARGET_POWERPC64 && mode == DImode)));
321 bool vmx_p = (TARGET_P9_FUSION && TARGET_P9_VECTOR
322 && (mode == DFmode || mode == SFmode));
324 if (!TARGET_P8_FUSION)
327 if (GET_CODE (op) == SUBREG)
328 op = SUBREG_REG (op);
334 if (r >= FIRST_PSEUDO_REGISTER)
335 return (gpr_p || fpr_p || vmx_p);
343 if (ALTIVEC_REGNO_P (r))
349 ;; Return 1 if op is a HTM specific SPR register.
350 (define_predicate "htm_spr_reg_operand"
351 (match_operand 0 "register_operand")
356 if (GET_CODE (op) == SUBREG)
357 op = SUBREG_REG (op);
376 ;; Return 1 if op is a general purpose register that is an even register
377 ;; which suitable for a load/store quad operation
378 ;; Subregs are not allowed here because when they are combine can
379 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
380 ;; think the innermost reg needs reloading, in TImode instead of
381 ;; PTImode. So reload will choose a reg in TImode which has no
382 ;; requirement that the reg be even.
383 (define_predicate "quad_int_reg_operand"
388 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
392 if (r >= FIRST_PSEUDO_REGISTER)
395 return (INT_REGNO_P (r) && ((r & 1) == 0));
398 ;; Return 1 if op is a register that is a condition register field.
399 (define_predicate "cc_reg_operand"
400 (match_operand 0 "register_operand")
402 if (GET_CODE (op) == SUBREG)
403 op = SUBREG_REG (op);
408 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
411 return CR_REGNO_P (REGNO (op));
414 ;; Return 1 if op is a register that is a condition register field not cr0.
415 (define_predicate "cc_reg_not_cr0_operand"
416 (match_operand 0 "register_operand")
418 if (GET_CODE (op) == SUBREG)
419 op = SUBREG_REG (op);
424 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
427 return CR_REGNO_NOT_CR0_P (REGNO (op));
430 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
431 (define_predicate "cc_reg_not_micro_cr0_operand"
432 (match_operand 0 "register_operand")
434 if (GET_CODE (op) == SUBREG)
435 op = SUBREG_REG (op);
440 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
443 if (rs6000_gen_cell_microcode)
444 return CR_REGNO_NOT_CR0_P (REGNO (op));
446 return CR_REGNO_P (REGNO (op));
449 ;; Return 1 if op is a constant integer valid for D field
450 ;; or non-special register register.
451 (define_predicate "reg_or_short_operand"
452 (if_then_else (match_code "const_int")
453 (match_operand 0 "short_cint_operand")
454 (match_operand 0 "gpc_reg_operand")))
456 ;; Return 1 if op is a constant integer valid for DS field
457 ;; or non-special register.
458 (define_predicate "reg_or_aligned_short_operand"
459 (if_then_else (match_code "const_int")
460 (and (match_operand 0 "short_cint_operand")
461 (match_test "!(INTVAL (op) & 3)"))
462 (match_operand 0 "gpc_reg_operand")))
464 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
465 ;; or non-special register.
466 (define_predicate "reg_or_u_short_operand"
467 (if_then_else (match_code "const_int")
468 (match_operand 0 "u_short_cint_operand")
469 (match_operand 0 "gpc_reg_operand")))
471 ;; Return 1 if op is any constant integer
472 ;; or non-special register.
473 (define_predicate "reg_or_cint_operand"
474 (ior (match_code "const_int")
475 (match_operand 0 "gpc_reg_operand")))
477 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
478 (define_predicate "add_cint_operand"
479 (and (match_code "const_int")
480 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
481 + (mode == SImode ? 0x80000000 : 0x80008000))
482 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
484 ;; Return 1 if op is a constant integer valid for addition
485 ;; or non-special register.
486 (define_predicate "reg_or_add_cint_operand"
487 (if_then_else (match_code "const_int")
488 (match_operand 0 "add_cint_operand")
489 (match_operand 0 "gpc_reg_operand")))
491 ;; Return 1 if op is a constant integer valid for subtraction
492 ;; or non-special register.
493 (define_predicate "reg_or_sub_cint_operand"
494 (if_then_else (match_code "const_int")
495 (match_test "(unsigned HOST_WIDE_INT)
496 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
497 < (unsigned HOST_WIDE_INT) 0x100000000ll")
498 (match_operand 0 "gpc_reg_operand")))
500 ;; Return 1 if op is any 32-bit unsigned constant integer
501 ;; or non-special register.
502 (define_predicate "reg_or_logical_cint_operand"
503 (if_then_else (match_code "const_int")
504 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
506 || ((INTVAL (op) & GET_MODE_MASK (mode)
507 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
508 (match_operand 0 "gpc_reg_operand")))
510 ;; Like reg_or_logical_cint_operand, but allow vsx registers
511 (define_predicate "vsx_reg_or_cint_operand"
512 (ior (match_operand 0 "vsx_register_operand")
513 (match_operand 0 "reg_or_logical_cint_operand")))
515 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
516 ;; with no more than one instruction per word.
517 (define_predicate "easy_fp_constant"
518 (match_code "const_double")
520 if (GET_MODE (op) != mode
521 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
524 /* Consider all constants with -msoft-float to be easy. */
525 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
526 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
530 /* The constant 0.0 is easy under VSX. */
531 if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode))
534 if (DECIMAL_FLOAT_MODE_P (mode))
537 /* If we are using V.4 style PIC, consider all constants to be hard. */
538 if (flag_pic && DEFAULT_ABI == ABI_V4)
541 #ifdef TARGET_RELOCATABLE
542 /* Similarly if we are using -mrelocatable, consider all constants
544 if (TARGET_RELOCATABLE)
548 /* If we have real FPRs, consider floating point constants hard (other than
549 0.0 under VSX), so that the constant gets pushed to memory during the
550 early RTL phases. This has the advantage that double precision constants
551 that can be represented in single precision without a loss of precision
552 will use single precision loads. */
564 return (num_insns_constant (op, DImode) <= 2);
574 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
575 ;; vector register without using memory.
576 (define_predicate "easy_vector_constant"
577 (match_code "const_vector")
579 /* As the paired vectors are actually FPRs it seems that there is
580 no easy way to load a CONST_VECTOR without using memory. */
581 if (TARGET_PAIRED_FLOAT)
584 /* Because IEEE 128-bit floating point is considered a vector type
585 in order to pass it in VSX registers, it might use this function
586 instead of easy_fp_constant. */
587 if (FLOAT128_VECTOR_P (mode))
588 return easy_fp_constant (op, mode);
590 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
592 if (zero_constant (op, mode))
595 return easy_altivec_constant (op, mode);
598 if (SPE_VECTOR_MODE (mode))
601 if (zero_constant (op, mode))
603 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
606 /* Limit SPE vectors to 15 bits signed. These we can generate with:
611 I don't know how efficient it would be to allow bigger constants,
612 considering we'll have an extra 'ori' for every 'li'. I doubt 5
613 instructions is better than a 64-bit memory load, but I don't
614 have the e500 timing specs. */
615 if (mode == V2SImode)
617 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
618 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
619 return cst >= -0x7fff && cst <= 0x7fff
620 && cst2 >= -0x7fff && cst2 <= 0x7fff;
627 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
628 (define_predicate "easy_vector_constant_add_self"
629 (and (match_code "const_vector")
630 (and (match_test "TARGET_ALTIVEC")
631 (match_test "easy_altivec_constant (op, mode)")))
635 if (mode == V2DImode || mode == V2DFmode)
637 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
638 val = const_vector_elt_as_int (op, elt);
639 val = ((val & 0xff) ^ 0x80) - 0x80;
640 return EASY_VECTOR_15_ADD_SELF (val);
643 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
644 (define_predicate "easy_vector_constant_msb"
645 (and (match_code "const_vector")
646 (and (match_test "TARGET_ALTIVEC")
647 (match_test "easy_altivec_constant (op, mode)")))
651 if (mode == V2DImode || mode == V2DFmode)
653 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
654 val = const_vector_elt_as_int (op, elt);
655 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
658 ;; Return true if this is an easy altivec constant that we form
660 (define_predicate "easy_vector_constant_vsldoi"
661 (and (match_code "const_vector")
662 (and (match_test "TARGET_ALTIVEC")
663 (and (match_test "easy_altivec_constant (op, mode)")
664 (match_test "vspltis_shifted (op) != 0")))))
666 ;; Return 1 if operand is constant zero (scalars and vectors).
667 (define_predicate "zero_constant"
668 (and (match_code "const_int,const_double,const_wide_int,const_vector")
669 (match_test "op == CONST0_RTX (mode)")))
671 ;; Return 1 if operand is 0.0.
672 (define_predicate "zero_fp_constant"
673 (and (match_code "const_double")
674 (match_test "SCALAR_FLOAT_MODE_P (mode)
675 && op == CONST0_RTX (mode)")))
677 ;; Return 1 if the operand is in volatile memory. Note that during the
678 ;; RTL generation phase, memory_operand does not return TRUE for volatile
679 ;; memory references. So this function allows us to recognize volatile
680 ;; references where it's safe.
681 (define_predicate "volatile_mem_operand"
682 (and (and (match_code "mem")
683 (match_test "MEM_VOLATILE_P (op)"))
684 (if_then_else (match_test "reload_completed")
685 (match_operand 0 "memory_operand")
686 (if_then_else (match_test "reload_in_progress")
687 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
688 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
690 ;; Return 1 if the operand is an offsettable memory operand.
691 (define_predicate "offsettable_mem_operand"
692 (and (match_operand 0 "memory_operand")
693 (match_test "offsettable_nonstrict_memref_p (op)")))
695 ;; Return 1 if the operand is suitable for load/store quad memory.
696 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
697 (define_predicate "quad_memory_operand"
703 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
706 else if (!memory_operand (op, mode))
709 else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
712 else if (MEM_ALIGN (op) < 128)
718 if (int_reg_operand (addr, Pmode))
721 else if (GET_CODE (addr) != PLUS)
726 op0 = XEXP (addr, 0);
727 op1 = XEXP (addr, 1);
728 ret = (int_reg_operand (op0, Pmode)
729 && GET_CODE (op1) == CONST_INT
730 && IN_RANGE (INTVAL (op1), -32768, 32767)
731 && (INTVAL (op1) & 15) == 0);
735 if (TARGET_DEBUG_ADDR)
737 fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
744 ;; Return 1 if the operand is an indexed or indirect memory operand.
745 (define_predicate "indexed_or_indirect_operand"
749 if (VECTOR_MEM_ALTIVEC_P (mode)
750 && GET_CODE (op) == AND
751 && GET_CODE (XEXP (op, 1)) == CONST_INT
752 && INTVAL (XEXP (op, 1)) == -16)
755 return indexed_or_indirect_address (op, mode);
758 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
759 ;; moves are supported.
760 (define_predicate "reg_or_indexed_operand"
761 (match_code "mem,reg,subreg")
764 return indexed_or_indirect_operand (op, mode);
765 else if (TARGET_DIRECT_MOVE)
766 return register_operand (op, mode);
771 ;; Return 1 if the operand is an indexed or indirect memory operand with an
772 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
773 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
774 ;; while VSX uses the full address and traps)
775 (define_predicate "altivec_indexed_or_indirect_operand"
779 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
780 && GET_CODE (op) == AND
781 && GET_CODE (XEXP (op, 1)) == CONST_INT
782 && INTVAL (XEXP (op, 1)) == -16)
783 return indexed_or_indirect_address (XEXP (op, 0), mode);
788 ;; Return 1 if the operand is an indexed or indirect address.
789 (define_special_predicate "indexed_or_indirect_address"
790 (and (match_test "REG_P (op)
791 || (GET_CODE (op) == PLUS
792 /* Omit testing REG_P (XEXP (op, 0)). */
793 && REG_P (XEXP (op, 1)))")
794 (match_operand 0 "address_operand")))
796 ;; Return 1 if the operand is an index-form address.
797 (define_special_predicate "indexed_address"
798 (match_test "(GET_CODE (op) == PLUS
799 && REG_P (XEXP (op, 0))
800 && REG_P (XEXP (op, 1)))"))
802 ;; Return 1 if the operand is a MEM with an update-form address. This may
803 ;; also include update-indexed form.
804 (define_special_predicate "update_address_mem"
805 (match_test "(MEM_P (op)
806 && (GET_CODE (XEXP (op, 0)) == PRE_INC
807 || GET_CODE (XEXP (op, 0)) == PRE_DEC
808 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
810 ;; Return 1 if the operand is a MEM with an indexed-form address.
811 (define_special_predicate "indexed_address_mem"
812 (match_test "(MEM_P (op)
813 && (indexed_address (XEXP (op, 0), mode)
814 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
815 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
817 ;; Return 1 if the operand is either a non-special register or can be used
818 ;; as the operand of a `mode' add insn.
819 (define_predicate "add_operand"
820 (if_then_else (match_code "const_int")
821 (match_test "satisfies_constraint_I (op)
822 || satisfies_constraint_L (op)")
823 (match_operand 0 "gpc_reg_operand")))
825 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
826 (define_predicate "adde_operand"
827 (if_then_else (match_code "const_int")
828 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
829 (match_operand 0 "gpc_reg_operand")))
831 ;; Return 1 if OP is a constant but not a valid add_operand.
832 (define_predicate "non_add_cint_operand"
833 (and (match_code "const_int")
834 (match_test "!satisfies_constraint_I (op)
835 && !satisfies_constraint_L (op)")))
837 ;; Return 1 if the operand is a constant that can be used as the operand
839 (define_predicate "logical_const_operand"
840 (match_code "const_int")
844 opl = INTVAL (op) & GET_MODE_MASK (mode);
846 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
847 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
850 ;; Return 1 if the operand is a non-special register or a constant that
851 ;; can be used as the operand of an OR or XOR.
852 (define_predicate "logical_operand"
853 (ior (match_operand 0 "gpc_reg_operand")
854 (match_operand 0 "logical_const_operand")))
856 ;; Return 1 if op is a constant that is not a logical operand, but could
857 ;; be split into one.
858 (define_predicate "non_logical_cint_operand"
859 (and (match_code "const_int,const_wide_int")
860 (and (not (match_operand 0 "logical_operand"))
861 (match_operand 0 "reg_or_logical_cint_operand"))))
863 ;; Return 1 if the operand is either a non-special register or a
864 ;; constant that can be used as the operand of a logical AND.
865 (define_predicate "and_operand"
866 (ior (and (match_code "const_int")
867 (match_test "rs6000_is_valid_and_mask (op, mode)"))
868 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
869 (match_operand 0 "gpc_reg_operand")
870 (match_operand 0 "logical_operand"))))
872 ;; Return 1 if the operand is either a logical operand or a short cint operand.
873 (define_predicate "scc_eq_operand"
874 (ior (match_operand 0 "logical_operand")
875 (match_operand 0 "short_cint_operand")))
877 ;; Return 1 if the operand is a general non-special register or memory operand.
878 (define_predicate "reg_or_mem_operand"
879 (ior (match_operand 0 "memory_operand")
880 (ior (and (match_code "mem")
881 (match_test "macho_lo_sum_memory_operand (op, mode)"))
882 (ior (match_operand 0 "volatile_mem_operand")
883 (match_operand 0 "gpc_reg_operand")))))
885 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
886 (define_predicate "reg_or_none500mem_operand"
887 (if_then_else (match_code "mem")
888 (and (match_test "!TARGET_E500_DOUBLE")
889 (ior (match_operand 0 "memory_operand")
890 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
891 (match_operand 0 "volatile_mem_operand"))))
892 (match_operand 0 "gpc_reg_operand")))
894 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
895 (define_predicate "zero_reg_mem_operand"
896 (ior (and (match_test "TARGET_VSX")
897 (match_operand 0 "zero_fp_constant"))
898 (match_operand 0 "reg_or_mem_operand")))
900 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
901 ;; data types inside of a vector that scalar instructions operate on
902 (define_predicate "vsx_scalar_64bit"
903 (match_code "const_int")
905 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
908 ;; Return 1 if the operand is a general register or memory operand without
909 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
911 (define_predicate "lwa_operand"
912 (match_code "reg,subreg,mem")
914 rtx inner, addr, offset;
917 if (reload_completed && GET_CODE (inner) == SUBREG)
918 inner = SUBREG_REG (inner);
920 if (gpc_reg_operand (inner, mode))
922 if (!memory_operand (inner, mode))
924 if (!rs6000_gen_cell_microcode)
927 addr = XEXP (inner, 0);
928 if (GET_CODE (addr) == PRE_INC
929 || GET_CODE (addr) == PRE_DEC
930 || (GET_CODE (addr) == PRE_MODIFY
931 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
933 if (GET_CODE (addr) == LO_SUM
934 && GET_CODE (XEXP (addr, 0)) == REG
935 && GET_CODE (XEXP (addr, 1)) == CONST)
936 addr = XEXP (XEXP (addr, 1), 0);
937 if (GET_CODE (addr) != PLUS)
939 offset = XEXP (addr, 1);
940 if (GET_CODE (offset) != CONST_INT)
942 return INTVAL (offset) % 4 == 0;
945 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
946 (define_predicate "symbol_ref_operand"
947 (and (match_code "symbol_ref")
948 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
949 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
951 ;; Return 1 if op is an operand that can be loaded via the GOT.
952 ;; or non-special register register field no cr0
953 (define_predicate "got_operand"
954 (match_code "symbol_ref,const,label_ref"))
956 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
957 ;; excluding labels involving addition.
958 (define_predicate "got_no_const_operand"
959 (match_code "symbol_ref,label_ref"))
961 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
962 (define_predicate "rs6000_tls_symbol_ref"
963 (and (match_code "symbol_ref")
964 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
966 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
967 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
968 (define_predicate "call_operand"
969 (if_then_else (match_code "reg")
970 (match_test "REGNO (op) == LR_REGNO
971 || REGNO (op) == CTR_REGNO
972 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
973 (match_code "symbol_ref")))
975 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
977 (define_predicate "current_file_function_operand"
978 (and (match_code "symbol_ref")
979 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
980 && (SYMBOL_REF_LOCAL_P (op)
981 || op == XEXP (DECL_RTL (current_function_decl), 0))
982 && !((DEFAULT_ABI == ABI_AIX
983 || DEFAULT_ABI == ABI_ELFv2)
984 && (SYMBOL_REF_EXTERNAL_P (op)
985 || SYMBOL_REF_WEAK (op)))")))
987 ;; Return 1 if this operand is a valid input for a move insn.
988 (define_predicate "input_operand"
989 (match_code "symbol_ref,const,reg,subreg,mem,
990 const_double,const_wide_int,const_vector,const_int")
992 /* Memory is always valid. */
993 if (memory_operand (op, mode))
996 /* For floating-point, easy constants are valid. */
997 if (SCALAR_FLOAT_MODE_P (mode)
998 && easy_fp_constant (op, mode))
1001 /* Allow any integer constant. */
1002 if (GET_MODE_CLASS (mode) == MODE_INT
1003 && CONST_SCALAR_INT_P (op))
1006 /* Allow easy vector constants. */
1007 if (GET_CODE (op) == CONST_VECTOR
1008 && easy_vector_constant (op, mode))
1011 /* Do not allow invalid E500 subregs. */
1012 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1013 && GET_CODE (op) == SUBREG
1014 && invalid_e500_subreg (op, mode))
1017 /* For floating-point or multi-word mode, the only remaining valid type
1019 if (SCALAR_FLOAT_MODE_P (mode)
1020 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1021 return register_operand (op, mode);
1023 /* We don't allow moving the carry bit around. */
1024 if (ca_operand (op, mode))
1027 /* The only cases left are integral modes one word or smaller (we
1028 do not get called for MODE_CC values). These can be in any
1030 if (register_operand (op, mode))
1033 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1035 if (DEFAULT_ABI == ABI_V4
1036 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1037 && small_data_operand (op, Pmode))
1043 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1044 (define_predicate "splat_input_operand"
1045 (match_code "symbol_ref,const,reg,subreg,mem,
1046 const_double,const_wide_int,const_vector,const_int")
1050 if (! volatile_ok && MEM_VOLATILE_P (op))
1054 else if (mode == DImode)
1058 return memory_address_addr_space_p (mode, XEXP (op, 0),
1059 MEM_ADDR_SPACE (op));
1061 return input_operand (op, mode);
1064 ;; Return true if OP is a non-immediate operand and not an invalid
1065 ;; SUBREG operation on the e500.
1066 (define_predicate "rs6000_nonimmediate_operand"
1067 (match_code "reg,subreg,mem")
1069 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1070 && GET_CODE (op) == SUBREG
1071 && invalid_e500_subreg (op, mode))
1074 return nonimmediate_operand (op, mode);
1077 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1078 (define_predicate "rotate_mask_operator"
1079 (match_code "rotate,ashift,lshiftrt"))
1081 ;; Return true if operand is boolean operator.
1082 (define_predicate "boolean_operator"
1083 (match_code "and,ior,xor"))
1085 ;; Return true if operand is OR-form of boolean operator.
1086 (define_predicate "boolean_or_operator"
1087 (match_code "ior,xor"))
1089 ;; Return true if operand is an equality operator.
1090 (define_special_predicate "equality_operator"
1091 (match_code "eq,ne"))
1093 ;; Return true if operand is MIN or MAX operator.
1094 (define_predicate "min_max_operator"
1095 (match_code "smin,smax,umin,umax"))
1097 ;; Return 1 if OP is a comparison operation that is valid for a branch
1098 ;; instruction. We check the opcode against the mode of the CC value.
1099 ;; validate_condition_mode is an assertion.
1100 (define_predicate "branch_comparison_operator"
1101 (and (match_operand 0 "comparison_operator")
1102 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1103 (match_test "validate_condition_mode (GET_CODE (op),
1104 GET_MODE (XEXP (op, 0))),
1107 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
1108 ;; If we're assuming that FP operations cannot generate user-visible traps,
1109 ;; then on e500 we can use the ordered-signaling instructions to implement
1110 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1111 (define_predicate "rs6000_cbranch_operator"
1112 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1113 (if_then_else (match_test "flag_trapping_math")
1114 (match_operand 0 "ordered_comparison_operator")
1115 (ior (match_operand 0 "ordered_comparison_operator")
1116 (match_code ("unlt,unle,ungt,unge"))))
1117 (match_operand 0 "comparison_operator")))
1119 ;; Return 1 if OP is an unsigned comparison operator.
1120 (define_predicate "unsigned_comparison_operator"
1121 (match_code "ltu,gtu,leu,geu"))
1123 ;; Return 1 if OP is a signed comparison operator.
1124 (define_predicate "signed_comparison_operator"
1125 (match_code "lt,gt,le,ge"))
1127 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1128 ;; it must be a positive comparison.
1129 (define_predicate "scc_comparison_operator"
1130 (and (match_operand 0 "branch_comparison_operator")
1131 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1133 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1135 (define_predicate "scc_rev_comparison_operator"
1136 (and (match_operand 0 "branch_comparison_operator")
1137 (match_code "ne,le,ge,leu,geu,ordered")))
1139 ;; Return 1 if OP is a comparison operation that is valid for a branch
1140 ;; insn, which is true if the corresponding bit in the CC register is set.
1141 (define_predicate "branch_positive_comparison_operator"
1142 (and (match_operand 0 "branch_comparison_operator")
1143 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1145 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1146 (define_predicate "load_multiple_operation"
1147 (match_code "parallel")
1149 int count = XVECLEN (op, 0);
1150 unsigned int dest_regno;
1154 /* Perform a quick check so we don't blow up below. */
1156 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1157 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1158 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1161 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1162 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1164 for (i = 1; i < count; i++)
1166 rtx elt = XVECEXP (op, 0, i);
1168 if (GET_CODE (elt) != SET
1169 || GET_CODE (SET_DEST (elt)) != REG
1170 || GET_MODE (SET_DEST (elt)) != SImode
1171 || REGNO (SET_DEST (elt)) != dest_regno + i
1172 || GET_CODE (SET_SRC (elt)) != MEM
1173 || GET_MODE (SET_SRC (elt)) != SImode
1174 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1175 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1176 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1177 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1184 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1185 ;; The second vector element is a CLOBBER.
1186 (define_predicate "store_multiple_operation"
1187 (match_code "parallel")
1189 int count = XVECLEN (op, 0) - 1;
1190 unsigned int src_regno;
1194 /* Perform a quick check so we don't blow up below. */
1196 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1197 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1198 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1201 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1202 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1204 for (i = 1; i < count; i++)
1206 rtx elt = XVECEXP (op, 0, i + 1);
1208 if (GET_CODE (elt) != SET
1209 || GET_CODE (SET_SRC (elt)) != REG
1210 || GET_MODE (SET_SRC (elt)) != SImode
1211 || REGNO (SET_SRC (elt)) != src_regno + i
1212 || GET_CODE (SET_DEST (elt)) != MEM
1213 || GET_MODE (SET_DEST (elt)) != SImode
1214 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1215 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1216 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1217 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1224 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1226 (define_predicate "save_world_operation"
1227 (match_code "parallel")
1232 int count = XVECLEN (op, 0);
1238 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1239 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1242 for (i=1; i <= 18; i++)
1244 elt = XVECEXP (op, 0, index++);
1245 if (GET_CODE (elt) != SET
1246 || GET_CODE (SET_DEST (elt)) != MEM
1247 || ! memory_operand (SET_DEST (elt), DFmode)
1248 || GET_CODE (SET_SRC (elt)) != REG
1249 || GET_MODE (SET_SRC (elt)) != DFmode)
1253 for (i=1; i <= 12; i++)
1255 elt = XVECEXP (op, 0, index++);
1256 if (GET_CODE (elt) != SET
1257 || GET_CODE (SET_DEST (elt)) != MEM
1258 || GET_CODE (SET_SRC (elt)) != REG
1259 || GET_MODE (SET_SRC (elt)) != V4SImode)
1263 for (i=1; i <= 19; i++)
1265 elt = XVECEXP (op, 0, index++);
1266 if (GET_CODE (elt) != SET
1267 || GET_CODE (SET_DEST (elt)) != MEM
1268 || ! memory_operand (SET_DEST (elt), Pmode)
1269 || GET_CODE (SET_SRC (elt)) != REG
1270 || GET_MODE (SET_SRC (elt)) != Pmode)
1274 elt = XVECEXP (op, 0, index++);
1275 if (GET_CODE (elt) != SET
1276 || GET_CODE (SET_DEST (elt)) != MEM
1277 || ! memory_operand (SET_DEST (elt), Pmode)
1278 || GET_CODE (SET_SRC (elt)) != REG
1279 || REGNO (SET_SRC (elt)) != CR2_REGNO
1280 || GET_MODE (SET_SRC (elt)) != Pmode)
1283 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1284 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1289 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1291 (define_predicate "restore_world_operation"
1292 (match_code "parallel")
1297 int count = XVECLEN (op, 0);
1303 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1304 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1305 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1306 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1309 elt = XVECEXP (op, 0, index++);
1310 if (GET_CODE (elt) != SET
1311 || GET_CODE (SET_SRC (elt)) != MEM
1312 || ! memory_operand (SET_SRC (elt), Pmode)
1313 || GET_CODE (SET_DEST (elt)) != REG
1314 || REGNO (SET_DEST (elt)) != CR2_REGNO
1315 || GET_MODE (SET_DEST (elt)) != Pmode)
1318 for (i=1; i <= 19; i++)
1320 elt = XVECEXP (op, 0, index++);
1321 if (GET_CODE (elt) != SET
1322 || GET_CODE (SET_SRC (elt)) != MEM
1323 || ! memory_operand (SET_SRC (elt), Pmode)
1324 || GET_CODE (SET_DEST (elt)) != REG
1325 || GET_MODE (SET_DEST (elt)) != Pmode)
1329 for (i=1; i <= 12; i++)
1331 elt = XVECEXP (op, 0, index++);
1332 if (GET_CODE (elt) != SET
1333 || GET_CODE (SET_SRC (elt)) != MEM
1334 || GET_CODE (SET_DEST (elt)) != REG
1335 || GET_MODE (SET_DEST (elt)) != V4SImode)
1339 for (i=1; i <= 18; i++)
1341 elt = XVECEXP (op, 0, index++);
1342 if (GET_CODE (elt) != SET
1343 || GET_CODE (SET_SRC (elt)) != MEM
1344 || ! memory_operand (SET_SRC (elt), DFmode)
1345 || GET_CODE (SET_DEST (elt)) != REG
1346 || GET_MODE (SET_DEST (elt)) != DFmode)
1350 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1351 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1352 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1353 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1354 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1359 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1360 (define_predicate "vrsave_operation"
1361 (match_code "parallel")
1363 int count = XVECLEN (op, 0);
1364 unsigned int dest_regno, src_regno;
1368 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1369 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1370 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1371 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1374 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1375 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1377 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1380 for (i = 1; i < count; i++)
1382 rtx elt = XVECEXP (op, 0, i);
1384 if (GET_CODE (elt) != CLOBBER
1385 && GET_CODE (elt) != SET)
1392 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1393 (define_predicate "mfcr_operation"
1394 (match_code "parallel")
1396 int count = XVECLEN (op, 0);
1399 /* Perform a quick check so we don't blow up below. */
1401 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1402 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1403 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1406 for (i = 0; i < count; i++)
1408 rtx exp = XVECEXP (op, 0, i);
1413 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1415 if (GET_CODE (src_reg) != REG
1416 || GET_MODE (src_reg) != CCmode
1417 || ! CR_REGNO_P (REGNO (src_reg)))
1420 if (GET_CODE (exp) != SET
1421 || GET_CODE (SET_DEST (exp)) != REG
1422 || GET_MODE (SET_DEST (exp)) != SImode
1423 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1425 unspec = SET_SRC (exp);
1426 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1428 if (GET_CODE (unspec) != UNSPEC
1429 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1430 || XVECLEN (unspec, 0) != 2
1431 || XVECEXP (unspec, 0, 0) != src_reg
1432 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1433 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1439 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1440 (define_predicate "mtcrf_operation"
1441 (match_code "parallel")
1443 int count = XVECLEN (op, 0);
1447 /* Perform a quick check so we don't blow up below. */
1449 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1450 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1451 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1453 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1455 if (GET_CODE (src_reg) != REG
1456 || GET_MODE (src_reg) != SImode
1457 || ! INT_REGNO_P (REGNO (src_reg)))
1460 for (i = 0; i < count; i++)
1462 rtx exp = XVECEXP (op, 0, i);
1466 if (GET_CODE (exp) != SET
1467 || GET_CODE (SET_DEST (exp)) != REG
1468 || GET_MODE (SET_DEST (exp)) != CCmode
1469 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1471 unspec = SET_SRC (exp);
1472 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1474 if (GET_CODE (unspec) != UNSPEC
1475 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1476 || XVECLEN (unspec, 0) != 2
1477 || XVECEXP (unspec, 0, 0) != src_reg
1478 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1479 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1485 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1486 (define_predicate "crsave_operation"
1487 (match_code "parallel")
1489 int count = XVECLEN (op, 0);
1492 for (i = 1; i < count; i++)
1494 rtx exp = XVECEXP (op, 0, i);
1496 if (GET_CODE (exp) != USE
1497 || GET_CODE (XEXP (exp, 0)) != REG
1498 || GET_MODE (XEXP (exp, 0)) != CCmode
1499 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1505 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1506 (define_predicate "lmw_operation"
1507 (match_code "parallel")
1509 int count = XVECLEN (op, 0);
1510 unsigned int dest_regno;
1512 unsigned int base_regno;
1513 HOST_WIDE_INT offset;
1516 /* Perform a quick check so we don't blow up below. */
1518 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1519 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1520 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1523 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1524 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1527 || count != 32 - (int) dest_regno)
1530 if (legitimate_indirect_address_p (src_addr, 0))
1533 base_regno = REGNO (src_addr);
1534 if (base_regno == 0)
1537 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1539 offset = INTVAL (XEXP (src_addr, 1));
1540 base_regno = REGNO (XEXP (src_addr, 0));
1545 for (i = 0; i < count; i++)
1547 rtx elt = XVECEXP (op, 0, i);
1550 HOST_WIDE_INT newoffset;
1552 if (GET_CODE (elt) != SET
1553 || GET_CODE (SET_DEST (elt)) != REG
1554 || GET_MODE (SET_DEST (elt)) != SImode
1555 || REGNO (SET_DEST (elt)) != dest_regno + i
1556 || GET_CODE (SET_SRC (elt)) != MEM
1557 || GET_MODE (SET_SRC (elt)) != SImode)
1559 newaddr = XEXP (SET_SRC (elt), 0);
1560 if (legitimate_indirect_address_p (newaddr, 0))
1565 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1567 addr_reg = XEXP (newaddr, 0);
1568 newoffset = INTVAL (XEXP (newaddr, 1));
1572 if (REGNO (addr_reg) != base_regno
1573 || newoffset != offset + 4 * i)
1580 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1581 (define_predicate "stmw_operation"
1582 (match_code "parallel")
1584 int count = XVECLEN (op, 0);
1585 unsigned int src_regno;
1587 unsigned int base_regno;
1588 HOST_WIDE_INT offset;
1591 /* Perform a quick check so we don't blow up below. */
1593 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1594 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1595 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1598 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1599 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1602 || count != 32 - (int) src_regno)
1605 if (legitimate_indirect_address_p (dest_addr, 0))
1608 base_regno = REGNO (dest_addr);
1609 if (base_regno == 0)
1612 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1614 offset = INTVAL (XEXP (dest_addr, 1));
1615 base_regno = REGNO (XEXP (dest_addr, 0));
1620 for (i = 0; i < count; i++)
1622 rtx elt = XVECEXP (op, 0, i);
1625 HOST_WIDE_INT newoffset;
1627 if (GET_CODE (elt) != SET
1628 || GET_CODE (SET_SRC (elt)) != REG
1629 || GET_MODE (SET_SRC (elt)) != SImode
1630 || REGNO (SET_SRC (elt)) != src_regno + i
1631 || GET_CODE (SET_DEST (elt)) != MEM
1632 || GET_MODE (SET_DEST (elt)) != SImode)
1634 newaddr = XEXP (SET_DEST (elt), 0);
1635 if (legitimate_indirect_address_p (newaddr, 0))
1640 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1642 addr_reg = XEXP (newaddr, 0);
1643 newoffset = INTVAL (XEXP (newaddr, 1));
1647 if (REGNO (addr_reg) != base_regno
1648 || newoffset != offset + 4 * i)
1655 ;; Return 1 if OP is a stack tie operand.
1656 (define_predicate "tie_operand"
1657 (match_code "parallel")
1659 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1660 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1661 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1662 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1665 ;; Match a small code model toc reference (or medium and large
1666 ;; model toc references before reload).
1667 (define_predicate "small_toc_ref"
1668 (match_code "unspec,plus")
1670 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1673 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1676 ;; Match the TOC memory operand that can be fused with an addis instruction.
1677 ;; This is used in matching a potential fused address before register
1679 (define_predicate "toc_fusion_mem_raw"
1682 if (!TARGET_TOC_FUSION_INT || !can_create_pseudo_p ())
1685 return small_toc_ref (XEXP (op, 0), Pmode);
1688 ;; Match the memory operand that has been fused with an addis instruction and
1689 ;; wrapped inside of an (unspec [...] UNSPEC_FUSION_ADDIS) wrapper.
1690 (define_predicate "toc_fusion_mem_wrapped"
1695 if (!TARGET_TOC_FUSION_INT)
1701 addr = XEXP (op, 0);
1702 return (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS);
1705 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1706 ;; GPR registers on power8.
1707 (define_predicate "fusion_gpr_addis"
1708 (match_code "const_int,high,plus")
1710 HOST_WIDE_INT value;
1713 if (GET_CODE (op) == HIGH)
1716 if (CONST_INT_P (op))
1719 else if (GET_CODE (op) == PLUS
1720 && base_reg_operand (XEXP (op, 0), Pmode)
1721 && CONST_INT_P (XEXP (op, 1)))
1722 int_const = XEXP (op, 1);
1727 value = INTVAL (int_const);
1728 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1731 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1734 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1735 value are all 1's or 0's. Ignore this restriction if we are testing
1737 if (TARGET_P9_FUSION)
1740 return (IN_RANGE (value >> 16, -32, 31));
1743 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1744 ;; and loads to GPR registers on power8.
1745 (define_predicate "fusion_gpr_mem_load"
1746 (match_code "mem,sign_extend,zero_extend")
1748 rtx addr, base, offset;
1750 /* Handle sign/zero extend. */
1751 if (GET_CODE (op) == ZERO_EXTEND
1752 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1755 mode = GET_MODE (op);
1769 if (!TARGET_POWERPC64)
1777 addr = XEXP (op, 0);
1778 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1781 base = XEXP (addr, 0);
1782 if (!base_reg_operand (base, GET_MODE (base)))
1785 offset = XEXP (addr, 1);
1787 if (GET_CODE (addr) == PLUS)
1788 return satisfies_constraint_I (offset);
1790 else if (GET_CODE (addr) == LO_SUM)
1792 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1793 return small_toc_ref (offset, GET_MODE (offset));
1795 else if (TARGET_ELF && !TARGET_POWERPC64)
1796 return CONSTANT_P (offset);
1802 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1803 ;; memory field with both the addis and the memory offset. Sign extension
1804 ;; is not handled here, since lha and lwa are not fused.
1805 ;; With extended fusion, also match a FPR load (lfd, lfs) and float_extend
1806 (define_predicate "fusion_addis_mem_combo_load"
1807 (match_code "mem,zero_extend,float_extend")
1809 rtx addr, base, offset;
1811 /* Handle zero/float extend. */
1812 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
1815 mode = GET_MODE (op);
1829 if (!TARGET_POWERPC64)
1835 if (!TARGET_P9_FUSION)
1843 addr = XEXP (op, 0);
1844 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1847 base = XEXP (addr, 0);
1848 if (!fusion_gpr_addis (base, GET_MODE (base)))
1851 offset = XEXP (addr, 1);
1852 if (GET_CODE (addr) == PLUS)
1853 return satisfies_constraint_I (offset);
1855 else if (GET_CODE (addr) == LO_SUM)
1857 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1858 return small_toc_ref (offset, GET_MODE (offset));
1860 else if (TARGET_ELF && !TARGET_POWERPC64)
1861 return CONSTANT_P (offset);
1867 ;; Like fusion_addis_mem_combo_load, but for stores
1868 (define_predicate "fusion_addis_mem_combo_store"
1871 rtx addr, base, offset;
1873 if (!MEM_P (op) || !TARGET_P9_FUSION)
1884 if (!TARGET_POWERPC64)
1902 addr = XEXP (op, 0);
1903 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1906 base = XEXP (addr, 0);
1907 if (!fusion_gpr_addis (base, GET_MODE (base)))
1910 offset = XEXP (addr, 1);
1911 if (GET_CODE (addr) == PLUS)
1912 return satisfies_constraint_I (offset);
1914 else if (GET_CODE (addr) == LO_SUM)
1916 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1917 return small_toc_ref (offset, GET_MODE (offset));
1919 else if (TARGET_ELF && !TARGET_POWERPC64)
1920 return CONSTANT_P (offset);
1926 ;; Return true if the operand is a float_extend or zero extend of an
1927 ;; offsettable memory operand suitable for use in fusion
1928 (define_predicate "fusion_offsettable_mem_operand"
1929 (match_code "mem,zero_extend,float_extend")
1931 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
1934 mode = GET_MODE (op);
1937 if (!memory_operand (op, mode))
1940 return offsettable_nonstrict_memref_p (op);