gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2017 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  28    It is used in nds32_encode_section_info() to store flag in symbol_ref
  29    in case the symbol should be placed in .rodata section.
  30    So that we can check it in nds32_legitimate_address_p().  */
  31 #define NDS32_SYMBOL_FLAG_RODATA \
  32   (SYMBOL_FLAG_MACH_DEP << 0)
  33 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  34   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  35
  36 /* Computing the Length of an Insn.  */
  37 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  38   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  39
  40 /* Check instruction LS-37-FP-implied form.
  41    Note: actually its immediate range is imm9u
  42          since it is used for lwi37/swi37 instructions.  */
  43 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  44   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  45    && REGNO (ra) == FP_REGNUM               \
  46    && satisfies_constraint_Iu09 (imm))
  47
  48 /* Check instruction LS-37-SP-implied form.
  49    Note: actually its immediate range is imm9u
  50          since it is used for lwi37/swi37 instructions.  */
  51 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  52   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  53    && REGNO (ra) == SP_REGNUM               \
  54    && satisfies_constraint_Iu09 (imm))
  55
  56
  57 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  58 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  59
  60 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  61    Note: no need to check ra because Ra5 means it covers all registers.  */
  62 #define NDS32_LS_450_P(rt, ra, imm)                     \
  63   ((imm == const0_rtx)                                  \
  64    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  65        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  66
  67 /* Check instruction RRI-333-form.  */
  68 #define NDS32_RRI_333_P(rt, ra, imm)           \
  69   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  70    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  71    && satisfies_constraint_Iu03 (imm))
  72
  73 /* Check instruction RI-45-form.  */
  74 #define NDS32_RI_45_P(rt, ra, imm)                     \
  75   (REGNO (rt) == REGNO (ra)                            \
  76    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  77        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  78    && satisfies_constraint_Iu05 (imm))
  79
  80
  81 /* Check instruction RR-33-form.  */
  82 #define NDS32_RR_33_P(rt, ra)                   \
  83   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  84    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  85
  86 /* Check instruction RRR-333-form.  */
  87 #define NDS32_RRR_333_P(rt, ra, rb)             \
  88   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  89    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  90    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  91
  92 /* Check instruction RR-45-form.
  93    Note: no need to check rb because Rb5 means it covers all registers.  */
  94 #define NDS32_RR_45_P(rt, ra, rb)               \
  95   (REGNO (rt) == REGNO (ra)                     \
  96    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  97        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  98
  99 /* Classifies address type to distinguish 16-bit/32-bit format.  */
 100 enum nds32_16bit_address_type
 101 {
 102   /* [reg]: 45 format address.  */
 103   ADDRESS_REG,
 104   /* [lo_reg + imm3u]: 333 format address.  */
 105   ADDRESS_LO_REG_IMM3U,
 106   /* post_inc [lo_reg + imm3u]: 333 format address.  */
 107   ADDRESS_POST_INC_LO_REG_IMM3U,
 108   /* [$fp + imm7u]: fp imply address.  */
 109   ADDRESS_FP_IMM7U,
 110   /* [$sp + imm7u]: sp imply address.  */
 111   ADDRESS_SP_IMM7U,
 112   /* Other address format.  */
 113   ADDRESS_NOT_16BIT_FORMAT
 114 };
 115
 116
 117 /* ------------------------------------------------------------------------ */
 118
 119 /* Define maximum numbers of registers for passing arguments.  */
 120 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
 121
 122 /* Define the register number for first argument.  */
 123 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 124
 125 /* Define the register number for return value.  */
 126 #define NDS32_GPR_RET_FIRST_REGNUM 0
 127
 128 /* Define the first integer register number.  */
 129 #define NDS32_FIRST_GPR_REGNUM 0
 130 /* Define the last integer register number.  */
 131 #define NDS32_LAST_GPR_REGNUM 31
 132
 133 /* Define double word alignment bits.  */
 134 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 135
 136 /* Define alignment checking macros for convenience.  */
 137 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 138 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 139 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 140
 141 /* Get alignment according to mode or type information.
 142    When 'type' is nonnull, there is no need to look at 'mode'.  */
 143 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 144   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 145
 146 /* Round X up to the nearest double word.  */
 147 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 148
 149
 150 /* This macro is used to calculate the numbers of registers for
 151    containing 'size' bytes of the argument.
 152    The size of a register is a word in nds32 target.
 153    So we use UNITS_PER_WORD to do the calculation.  */
 154 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 155   ((mode == BLKmode)                                                     \
 156    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 157    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 158
 159 /* This macro is used to return the register number for passing argument.
 160    We need to obey the following rules:
 161      1. If it is required MORE THAN one register,
 162         we need to further check if it really needs to be
 163         aligned on double words.
 164           a) If double word alignment is necessary,
 165              the register number must be even value.
 166           b) Otherwise, the register number can be odd or even value.
 167      2. If it is required ONLY one register,
 168         the register number can be odd or even value.  */
 169 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 170   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 171    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 172       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 173       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 174    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 175
 176 /* This macro is to check if there are still available registers
 177    for passing argument, which must be entirely in registers.  */
 178 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 179   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 180     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 181    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 182        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 183
 184 /* This macro is to check if there are still available registers
 185    for passing argument, either entirely in registers or partially
 186    in registers.  */
 187 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 188   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 189    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 190
 191 /* This macro is to check if the register is required to be saved on stack.
 192    If call_used_regs[regno] == 0, regno is the callee-saved register.
 193    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 194    As long as the register satisfies both criteria above,
 195    it is required to be saved.  */
 196 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 197   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 198
 199 /* ------------------------------------------------------------------------ */
 200
 201 /* A C structure for machine-specific, per-function data.
 202    This is added to the cfun structure.  */
 203 struct GTY(()) machine_function
 204 {
 205   /* Number of bytes allocated on the stack for variadic args
 206      if we want to push them into stack as pretend arguments by ourself.  */
 207   int va_args_size;
 208   /* Number of bytes reserved on the stack for
 209      local and temporary variables.  */
 210   int local_size;
 211   /* Number of bytes allocated on the stack for outgoing arguments.  */
 212   int out_args_size;
 213
 214   /* Number of bytes on the stack for saving $fp.  */
 215   int fp_size;
 216   /* Number of bytes on the stack for saving $gp.  */
 217   int gp_size;
 218   /* Number of bytes on the stack for saving $lp.  */
 219   int lp_size;
 220
 221   /* Number of bytes on the stack for saving general purpose
 222      callee-saved registers.  */
 223   int callee_saved_gpr_regs_size;
 224
 225   /* The padding bytes in callee-saved area may be required.  */
 226   int callee_saved_area_gpr_padding_bytes;
 227
 228   /* The first required general purpose callee-saved register.  */
 229   int callee_saved_first_gpr_regno;
 230   /* The last required general purpose callee-saved register.  */
 231   int callee_saved_last_gpr_regno;
 232
 233   /* The padding bytes in varargs area may be required.  */
 234   int va_args_area_padding_bytes;
 235
 236   /* The first required register that should be saved on stack for va_args.  */
 237   int va_args_first_regno;
 238   /* The last required register that should be saved on stack for va_args.  */
 239   int va_args_last_regno;
 240
 241   /* Indicate that whether this function needs
 242      prologue/epilogue code generation.  */
 243   int naked_p;
 244   /* Indicate that whether this function
 245      uses fp_as_gp optimization.  */
 246   int fp_as_gp_p;
 247 };
 248
 249 /* A C structure that contains the arguments information.  */
 250 typedef struct
 251 {
 252   unsigned int gpr_offset;
 253 } nds32_cumulative_args;
 254
 255 /* ------------------------------------------------------------------------ */
 256
 257 /* The following we define C-ISR related stuff.
 258    In nds32 architecture, we have 73 vectors for interrupt/exception.
 259    For each vector (except for vector 0, which is used for reset behavior),
 260    we allow users to set its register saving scheme and interrupt level.  */
 261
 262 /* There are 73 vectors in nds32 architecture.
 263    0 for reset handler,
 264    1-8 for exception handler,
 265    and 9-72 for interrupt handler.
 266    We use an array, which is defined in nds32.c, to record
 267    essential information for each vector.  */
 268 #define NDS32_N_ISR_VECTORS 73
 269
 270 /* Define possible isr category.  */
 271 enum nds32_isr_category
 272 {
 273   NDS32_ISR_NONE,
 274   NDS32_ISR_INTERRUPT,
 275   NDS32_ISR_EXCEPTION,
 276   NDS32_ISR_RESET
 277 };
 278
 279 /* Define isr register saving scheme.  */
 280 enum nds32_isr_save_reg
 281 {
 282   NDS32_SAVE_ALL,
 283   NDS32_PARTIAL_SAVE
 284 };
 285
 286 /* Define isr nested type.  */
 287 enum nds32_isr_nested_type
 288 {
 289   NDS32_NESTED,
 290   NDS32_NOT_NESTED,
 291   NDS32_NESTED_READY
 292 };
 293
 294 /* Define structure to record isr information.
 295    The isr vector array 'isr_vectors[]' with this structure
 296    is defined in nds32.c.  */
 297 struct nds32_isr_info
 298 {
 299   /* The field to identify isr category.
 300      It should be set to NDS32_ISR_NONE by default.
 301      If user specifies a function as isr by using attribute,
 302      this field will be set accordingly.  */
 303   enum nds32_isr_category category;
 304
 305   /* A string for the applied function name.
 306      It should be set to empty string by default.  */
 307   char func_name[100];
 308
 309   /* The register saving scheme.
 310      It should be set to NDS32_PARTIAL_SAVE by default
 311      unless user specifies attribute to change it.  */
 312   enum nds32_isr_save_reg save_reg;
 313
 314   /* The nested type.
 315      It should be set to NDS32_NOT_NESTED by default
 316      unless user specifies attribute to change it.  */
 317   enum nds32_isr_nested_type nested_type;
 318
 319   /* Total vectors.
 320      The total vectors = interrupt + exception numbers + reset.
 321      It should be set to 0 by default.
 322      This field is ONLY used in NDS32_ISR_RESET category.  */
 323   unsigned int total_n_vectors;
 324
 325   /* A string for nmi handler name.
 326      It should be set to empty string by default.
 327      This field is ONLY used in NDS32_ISR_RESET category.  */
 328   char nmi_name[100];
 329
 330   /* A string for warm handler name.
 331      It should be set to empty string by default.
 332      This field is ONLY used in NDS32_ISR_RESET category.  */
 333   char warm_name[100];
 334 };
 335
 336 /* ------------------------------------------------------------------------ */
 337
 338 /* Define code for all nds32 builtins.  */
 339 enum nds32_builtins
 340 {
 341   NDS32_BUILTIN_ISYNC,
 342   NDS32_BUILTIN_ISB,
 343   NDS32_BUILTIN_MFSR,
 344   NDS32_BUILTIN_MFUSR,
 345   NDS32_BUILTIN_MTSR,
 346   NDS32_BUILTIN_MTUSR,
 347   NDS32_BUILTIN_SETGIE_EN,
 348   NDS32_BUILTIN_SETGIE_DIS
 349 };
 350
 351 /* ------------------------------------------------------------------------ */
 352
 353 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 354 #define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
 355 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 356
 357 #define TARGET_CMODEL_SMALL \
 358    (nds32_cmodel_option == CMODEL_SMALL)
 359 #define TARGET_CMODEL_MEDIUM \
 360    (nds32_cmodel_option == CMODEL_MEDIUM)
 361 #define TARGET_CMODEL_LARGE \
 362    (nds32_cmodel_option == CMODEL_LARGE)
 363
 364 /* When -mcmodel=small or -mcmodel=medium,
 365    compiler may generate gp-base instruction directly.  */
 366 #define TARGET_GP_DIRECT \
 367    (nds32_cmodel_option == CMODEL_SMALL\
 368     || nds32_cmodel_option == CMODEL_MEDIUM)
 369
 370 #define TARGET_SOFT_FLOAT 1
 371 #define TARGET_HARD_FLOAT 0
 372
 373 /* ------------------------------------------------------------------------ */
 374 \f
 375 /* Controlling the Compilation Driver.  */
 376
 377 #define OPTION_DEFAULT_SPECS \
 378   {"arch", "%{!march=*:-march=%(VALUE)}" }
 379
 380 #define CC1_SPEC \
 381   ""
 382
 383 #define ASM_SPEC \
 384   " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 385
 386 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 387 #define LINK_SPEC \
 388   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 389   " %{mrelax:--relax}"
 390
 391 #define LIB_SPEC \
 392   " -lc -lgloss"
 393
 394 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 395    by applying different crt stuff.  In the convention, crt0.o is the
 396    startup file without constructor/destructor;
 397    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 398    startup files with constructor/destructor.
 399    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 400    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 401    currently provided by GCC for nds32 target.
 402
 403    For nds32 target so far:
 404    If -mno-ctor-dtor, we are going to link
 405    "crt0.o [user objects]".
 406    If general cases, we are going to link
 407    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 408 #define STARTFILE_SPEC \
 409   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 410   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 411 #define ENDFILE_SPEC \
 412   " %{!mno-ctor-dtor:crtend1.o%s}"
 413
 414 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 415    configure gcc with --target=nds32be-* setting.
 416    Check gcc/config.gcc for more information.  */
 417 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 418 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 419 #else
 420 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 421 #endif
 422
 423 /* Currently we only have elf toolchain,
 424    where -mcmodel=medium is always the default.  */
 425 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 426
 427 #define MULTILIB_DEFAULTS \
 428   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 429
 430 \f
 431 /* Run-time Target Specification.  */
 432
 433 #define TARGET_CPU_CPP_BUILTINS()                     \
 434   do                                                  \
 435     {                                                 \
 436       builtin_define ("__nds32__");                   \
 437                                                       \
 438       if (TARGET_ISA_V2)                              \
 439         builtin_define ("__NDS32_ISA_V2__");          \
 440       if (TARGET_ISA_V3)                              \
 441         builtin_define ("__NDS32_ISA_V3__");          \
 442       if (TARGET_ISA_V3M)                             \
 443         builtin_define ("__NDS32_ISA_V3M__");         \
 444                                                       \
 445       if (TARGET_BIG_ENDIAN)                          \
 446         builtin_define ("__big_endian__");            \
 447       if (TARGET_REDUCED_REGS)                        \
 448         builtin_define ("__NDS32_REDUCED_REGS__");    \
 449       if (TARGET_CMOV)                                \
 450         builtin_define ("__NDS32_CMOV__");            \
 451       if (TARGET_PERF_EXT)                            \
 452         builtin_define ("__NDS32_PERF_EXT__");        \
 453       if (TARGET_16_BIT)                              \
 454         builtin_define ("__NDS32_16_BIT__");          \
 455       if (TARGET_GP_DIRECT)                           \
 456         builtin_define ("__NDS32_GP_DIRECT__");       \
 457                                                       \
 458       builtin_assert ("cpu=nds32");                   \
 459       builtin_assert ("machine=nds32");               \
 460     } while (0)
 461
 462 \f
 463 /* Defining Data Structures for Per-function Information.  */
 464
 465 /* This macro is called once per function,
 466    before generation of any RTL has begun.  */
 467 #define INIT_EXPANDERS  nds32_init_expanders ()
 468
 469 \f
 470 /* Storage Layout.  */
 471
 472 #define BITS_BIG_ENDIAN 0
 473
 474 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 475
 476 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 477
 478 #define UNITS_PER_WORD 4
 479
 480 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 481   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 482     {                                                                       \
 483       (m) = SImode;                                                         \
 484     }
 485
 486 #define PARM_BOUNDARY 32
 487
 488 #define STACK_BOUNDARY 64
 489
 490 #define FUNCTION_BOUNDARY 32
 491
 492 #define BIGGEST_ALIGNMENT 64
 493
 494 #define EMPTY_FIELD_BOUNDARY 32
 495
 496 #define STRUCTURE_SIZE_BOUNDARY 8
 497
 498 #define STRICT_ALIGNMENT 1
 499
 500 #define PCC_BITFIELD_TYPE_MATTERS 1
 501
 502 \f
 503 /* Layout of Source Language Data Types.  */
 504
 505 #define INT_TYPE_SIZE           32
 506 #define SHORT_TYPE_SIZE         16
 507 #define LONG_TYPE_SIZE          32
 508 #define LONG_LONG_TYPE_SIZE     64
 509
 510 #define FLOAT_TYPE_SIZE         32
 511 #define DOUBLE_TYPE_SIZE        64
 512 #define LONG_DOUBLE_TYPE_SIZE   64
 513
 514 #define DEFAULT_SIGNED_CHAR 1
 515
 516 #define SIZE_TYPE "long unsigned int"
 517 #define PTRDIFF_TYPE "long int"
 518 #define WCHAR_TYPE "short unsigned int"
 519 #define WCHAR_TYPE_SIZE 16
 520
 521 \f
 522 /* Register Usage.  */
 523
 524 /* Number of actual hardware registers.
 525    The hardware registers are assigned numbers for the compiler
 526    from 0 to just below FIRST_PSEUDO_REGISTER.
 527    All registers that the compiler knows about must be given numbers,
 528    even those that are not normally considered general registers.  */
 529 #define FIRST_PSEUDO_REGISTER 34
 530
 531 /* An initializer that says which registers are used for fixed
 532    purposes all throughout the compiled code and are therefore
 533    not available for general allocation.
 534
 535    $r28 : $fp
 536    $r29 : $gp
 537    $r30 : $lp
 538    $r31 : $sp
 539
 540    caller-save registers: $r0 ~ $r5, $r16 ~ $r23
 541    callee-save registers: $r6 ~ $r10, $r11 ~ $r14
 542
 543    reserved for assembler : $r15
 544    reserved for other use : $r24, $r25, $r26, $r27 */
 545 #define FIXED_REGISTERS                 \
 546 { /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
 547       0,  0,  0,  0,  0,  0,  0,  0,    \
 548   /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
 549       0,  0,  0,  0,  0,  0,  0,  1,    \
 550   /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
 551       0,  0,  0,  0,  0,  0,  0,  0,    \
 552   /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
 553       1,  1,  1,  1,  0,  1,  0,  1,    \
 554   /* ARG_POINTER:32 */                  \
 555       1,                                \
 556   /* FRAME_POINTER:33 */                \
 557       1                                 \
 558 }
 559
 560 /* Identifies the registers that are not available for
 561    general allocation of values that must live across
 562    function calls -- so they are caller-save registers.
 563
 564    0 : callee-save registers
 565    1 : caller-save registers */
 566 #define CALL_USED_REGISTERS             \
 567 { /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
 568       1,  1,  1,  1,  1,  1,  0,  0,    \
 569   /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
 570       0,  0,  0,  0,  0,  0,  0,  1,    \
 571   /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
 572       1,  1,  1,  1,  1,  1,  1,  1,    \
 573   /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
 574       1,  1,  1,  1,  0,  1,  0,  1,    \
 575   /* ARG_POINTER:32 */                  \
 576       1,                                \
 577   /* FRAME_POINTER:33 */                \
 578       1                                 \
 579 }
 580
 581 /* In nds32 target, we have three levels of registers:
 582      LOW_COST_REGS    : $r0 ~ $r7
 583      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 584      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 585 #define REG_ALLOC_ORDER           \
 586 {                                 \
 587    0,  1,  2,  3,  4,  5,  6,  7, \
 588    8,  9, 10, 11, 16, 17, 18, 19, \
 589   12, 13, 14, 15, 20, 21, 22, 23, \
 590   24, 25, 26, 27, 28, 29, 30, 31, \
 591   32,                             \
 592   33                              \
 593 }
 594
 595 /* Tell IRA to use the order we define rather than messing it up with its
 596    own cost calculations.  */
 597 #define HONOR_REG_ALLOC_ORDER optimize_size
 598
 599 \f
 600 /* Register Classes.  */
 601
 602 /* In nds32 target, we have three levels of registers:
 603      Low cost regsiters    : $r0 ~ $r7
 604      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 605      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 606
 607    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 608    so that it provides more chance to use low cost registers.  */
 609 enum reg_class
 610 {
 611   NO_REGS,
 612   R15_TA_REG,
 613   STACK_REG,
 614   LOW_REGS,
 615   MIDDLE_REGS,
 616   HIGH_REGS,
 617   GENERAL_REGS,
 618   FRAME_REGS,
 619   ALL_REGS,
 620   LIM_REG_CLASSES
 621 };
 622
 623 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 624
 625 #define REG_CLASS_NAMES \
 626 {                       \
 627   "NO_REGS",            \
 628   "R15_TA_REG",         \
 629   "STACK_REG",          \
 630   "LOW_REGS",           \
 631   "MIDDLE_REGS",        \
 632   "HIGH_REGS",          \
 633   "GENERAL_REGS",       \
 634   "FRAME_REGS",         \
 635   "ALL_REGS"            \
 636 }
 637
 638 #define REG_CLASS_CONTENTS \
 639 {                                                            \
 640   {0x00000000, 0x00000000}, /* NO_REGS     :              */ \
 641   {0x00008000, 0x00000000}, /* R15_TA_REG  : 15           */ \
 642   {0x80000000, 0x00000000}, /* STACK_REG   : 31           */ \
 643   {0x000000ff, 0x00000000}, /* LOW_REGS    : 0-7          */ \
 644   {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19  */ \
 645   {0xfff07000, 0x00000000}, /* HIGH_REGS   : 12-14, 20-31 */ \
 646   {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31         */ \
 647   {0x00000000, 0x00000003}, /* FRAME_REGS  : 32, 33       */ \
 648   {0xffffffff, 0x00000003}  /* ALL_REGS    : 0-31, 32, 33 */ \
 649 }
 650
 651 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 652
 653 #define BASE_REG_CLASS GENERAL_REGS
 654 #define INDEX_REG_CLASS GENERAL_REGS
 655
 656 /* Return nonzero if it is suitable for use as a
 657    base register in operand addresses.
 658    So far, we return nonzero only if "num" is a hard reg
 659    of the suitable class or a pseudo register which is
 660    allocated to a suitable hard reg.  */
 661 #define REGNO_OK_FOR_BASE_P(num) \
 662   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 663
 664 /* Return nonzero if it is suitable for use as a
 665    index register in operand addresses.
 666    So far, we return nonzero only if "num" is a hard reg
 667    of the suitable class or a pseudo register which is
 668    allocated to a suitable hard reg.
 669    The difference between an index register and a base register is that
 670    the index register may be scaled.  */
 671 #define REGNO_OK_FOR_INDEX_P(num) \
 672   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 673
 674 \f
 675 /* Obsolete Macros for Defining Constraints.  */
 676
 677 \f
 678 /* Stack Layout and Calling Conventions.  */
 679
 680 #define STACK_GROWS_DOWNWARD 1
 681
 682 #define FRAME_GROWS_DOWNWARD 1
 683
 684 #define STACK_POINTER_OFFSET 0
 685
 686 #define FIRST_PARM_OFFSET(fundecl) \
 687   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 688
 689 #define RETURN_ADDR_RTX(count, frameaddr) \
 690   nds32_return_addr_rtx (count, frameaddr)
 691
 692 /* A C expression whose value is RTL representing the location
 693    of the incoming return address at the beginning of any function
 694    before the prologue.
 695    If this RTL is REG, you should also define
 696    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 697 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 698 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 699
 700 #define STACK_POINTER_REGNUM SP_REGNUM
 701
 702 #define FRAME_POINTER_REGNUM 33
 703
 704 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 705
 706 #define ARG_POINTER_REGNUM 32
 707
 708 #define STATIC_CHAIN_REGNUM 16
 709
 710 #define ELIMINABLE_REGS                                \
 711 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 712   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 713   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 714   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 715
 716 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 717   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 718
 719 #define ACCUMULATE_OUTGOING_ARGS 1
 720
 721 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 722
 723 #define CUMULATIVE_ARGS nds32_cumulative_args
 724
 725 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 726   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 727
 728 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
 729    We better cast REGNO into signed integer so that we can avoid
 730    'comparison of unsigned expression >= 0 is always true' warning.  */
 731 #define FUNCTION_ARG_REGNO_P(regno)                                        \
 732   (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
 733    && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
 734
 735 #define DEFAULT_PCC_STRUCT_RETURN 0
 736
 737 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 738    from a function, the stack pointer does not matter.
 739    The value is tested only in functions that have frame pointers.
 740    In nds32 target, the function epilogue recovers the
 741    stack pointer from the frame.  */
 742 #define EXIT_IGNORE_STACK 1
 743
 744 #define FUNCTION_PROFILER(file, labelno) \
 745   fprintf (file, "/* profiler %d */", (labelno))
 746
 747 \f
 748 /* Implementing the Varargs Macros.  */
 749
 750 \f
 751 /* Trampolines for Nested Functions.  */
 752
 753 /* Giving A-function and B-function,
 754    if B-function wants to call A-function's nested function,
 755    we need to fill trampoline code into A-function's stack
 756    so that B-function can execute the code in stack to indirectly
 757    jump to (like 'trampoline' action) desired nested function.
 758
 759    The trampoline code for nds32 target must contains following parts:
 760
 761      1. instructions (4 * 4 = 16 bytes):
 762           get $pc first
 763           load chain_value to static chain register via $pc
 764           load nested function address to $r15 via $pc
 765           jump to desired nested function via $r15
 766      2. data (4 * 2 = 8 bytes):
 767           chain_value
 768           nested function address
 769
 770    Please check nds32.c implementation for more information.  */
 771 #define TRAMPOLINE_SIZE 24
 772
 773 /* Because all instructions/data in trampoline template are 4-byte size,
 774    we set trampoline alignment 8*4=32 bits.  */
 775 #define TRAMPOLINE_ALIGNMENT 32
 776
 777 \f
 778 /* Implicit Calls to Library Routines.  */
 779
 780 \f
 781 /* Addressing Modes.  */
 782
 783 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
 784 #define HAVE_POST_INCREMENT 1
 785 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
 786 #define HAVE_POST_DECREMENT 1
 787
 788 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
 789 #define HAVE_POST_MODIFY_DISP 1
 790 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
 791 #define HAVE_POST_MODIFY_REG  1
 792
 793 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
 794
 795 #define MAX_REGS_PER_ADDRESS 2
 796
 797 \f
 798 /* Anchored Addresses.  */
 799
 800 \f
 801 /* Condition Code Status.  */
 802
 803 \f
 804 /* Describing Relative Costs of Operations.  */
 805
 806 /* A C expression for the cost of a branch instruction.
 807    A value of 1 is the default;
 808    other values are interpreted relative to that.  */
 809 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
 810
 811 #define SLOW_BYTE_ACCESS 1
 812
 813 #define NO_FUNCTION_CSE 1
 814
 815 \f
 816 /* Adjusting the Instruction Scheduler.  */
 817
 818 \f
 819 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
 820
 821 #define TEXT_SECTION_ASM_OP     "\t.text"
 822 #define DATA_SECTION_ASM_OP     "\t.data"
 823
 824 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
 825    So we use '.section .bss' alternatively.  */
 826 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
 827
 828 /* Define this macro to be an expression with a nonzero value if jump tables
 829    (for tablejump insns) should be output in the text section,
 830    along with the assembler instructions.
 831    Otherwise, the readonly data section is used.  */
 832 #define JUMP_TABLES_IN_TEXT_SECTION 1
 833
 834 \f
 835 /* Position Independent Code.  */
 836
 837 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
 838
 839 \f
 840 /* Defining the Output Assembler Language.  */
 841
 842 #define ASM_COMMENT_START "!"
 843
 844 #define ASM_APP_ON "! #APP"
 845
 846 #define ASM_APP_OFF "! #NO_APP\n"
 847
 848 #define ASM_OUTPUT_LABELREF(stream, name) \
 849   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
 850
 851 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
 852   assemble_name (stream, XSTR (sym, 0))
 853
 854 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
 855   assemble_name (stream, buf)
 856
 857 #define LOCAL_LABEL_PREFIX "."
 858
 859 #define REGISTER_NAMES                                            \
 860 {                                                                 \
 861   "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
 862   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
 863   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
 864   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
 865   "$AP",                                                          \
 866   "$SFP"                                                          \
 867 }
 868
 869 /* Output normal jump table entry.  */
 870 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 871   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
 872
 873 /* Output pc relative jump table entry.  */
 874 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
 875   do                                                                    \
 876     {                                                                   \
 877       switch (GET_MODE (body))                                          \
 878         {                                                               \
 879         case E_QImode:                                                    \
 880           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
 881           break;                                                        \
 882         case E_HImode:                                                    \
 883           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
 884           break;                                                        \
 885         case E_SImode:                                                    \
 886           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
 887           break;                                                        \
 888         default:                                                        \
 889           gcc_unreachable();                                            \
 890         }                                                               \
 891     } while (0)
 892
 893 /* We have to undef it first because elfos.h formerly define it
 894    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
 895 #undef  ASM_OUTPUT_CASE_LABEL
 896 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
 897   do                                                               \
 898     {                                                              \
 899       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
 900       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
 901     } while (0)
 902
 903 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
 904   do                                                   \
 905     {                                                  \
 906       /* Because our jump table is in text section,    \
 907          we need to make sure 2-byte alignment after   \
 908          the jump table for instructions fetch.  */    \
 909       if (GET_MODE (PATTERN (table)) == QImode)        \
 910         ASM_OUTPUT_ALIGN (stream, 1);                  \
 911       asm_fprintf (stream, "\t! Jump Table End\n");    \
 912     }  while (0)
 913
 914 /* This macro is not documented yet.
 915    But we do need it to make jump table vector aligned.  */
 916 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
 917
 918 #define DWARF2_UNWIND_INFO 1
 919
 920 #define JUMP_ALIGN(x) \
 921   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
 922
 923 #define LOOP_ALIGN(x) \
 924   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
 925
 926 #define LABEL_ALIGN(x) \
 927   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
 928
 929 #define ASM_OUTPUT_ALIGN(stream, power) \
 930   fprintf (stream, "\t.align\t%d\n", power)
 931
 932 \f
 933 /* Controlling Debugging Information Format.  */
 934
 935 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 936
 937 #define DWARF2_DEBUGGING_INFO 1
 938
 939 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 940
 941 \f
 942 /* Cross Compilation and Floating Point.  */
 943
 944 \f
 945 /* Mode Switching Instructions.  */
 946
 947 \f
 948 /* Defining target-specific uses of __attribute__.  */
 949
 950 \f
 951 /* Emulating TLS.  */
 952
 953 \f
 954 /* Defining coprocessor specifics for MIPS targets.  */
 955
 956 \f
 957 /* Parameters for Precompiled Header Validity Checking.  */
 958
 959 \f
 960 /* C++ ABI parameters.  */
 961
 962 \f
 963 /* Adding support for named address spaces.  */
 964
 965 \f
 966 /* Miscellaneous Parameters.  */
 967
 968 /* This is the machine mode that elements of a jump-table should have.  */
 969 #define CASE_VECTOR_MODE Pmode
 970
 971 /* Return the preferred mode for and addr_diff_vec when the mininum
 972    and maximum offset are known.  */
 973 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
 974    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
 975    : (max_offset >= 100) ? HImode                               \
 976    : QImode)
 977
 978 /* Generate pc relative jump table when -fpic or -Os.  */
 979 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
 980
 981 /* Define this macro if operations between registers with integral mode
 982    smaller than a word are always performed on the entire register.  */
 983 #define WORD_REGISTER_OPERATIONS 1
 984
 985 /* A C expression indicating when insns that read memory in mem_mode,
 986    an integral mode narrower than a word, set the bits outside of mem_mode
 987    to be either the sign-extension or the zero-extension of the data read.  */
 988 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 989
 990 /* The maximum number of bytes that a single instruction can move quickly
 991    between memory and registers or between two memory locations.  */
 992 #define MOVE_MAX 4
 993
 994 /* A C expression that is nonzero if on this machine the number of bits
 995    actually used for the count of a shift operation is equal to the number
 996    of bits needed to represent the size of the object being shifted.  */
 997 #define SHIFT_COUNT_TRUNCATED 1
 998
 999 /* A C expression describing the value returned by a comparison operator with
1000    an integral mode and stored by a store-flag instruction ('cstoremode4')
1001    when the condition is true.  */
1002 #define STORE_FLAG_VALUE 1
1003
1004 /* An alias for the machine mode for pointers.  */
1005 #define Pmode SImode
1006
1007 /* An alias for the machine mode used for memory references to functions
1008    being called, in call RTL expressions.  */
1009 #define FUNCTION_MODE SImode
1010
1011 /* ------------------------------------------------------------------------ */