1 /* Copyright (C) 1997-2017 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
30 #include "stringpool.h"
36 #include "diagnostic-core.h"
37 #include "fold-const.h"
39 #include "stor-layout.h"
41 #include "insn-attr.h"
45 #include "langhooks.h"
51 /* This file should be included last. */
52 #include "target-def.h"
55 #define FRV_INLINE inline
58 /* The maximum number of distinct NOP patterns. There are three:
59 nop, fnop and mnop. */
60 #define NUM_NOP_PATTERNS 3
62 /* Classification of instructions and units: integer, floating-point/media,
63 branch and control. */
64 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
66 /* The DFA names of the units, in packet order. */
67 static const char *const frv_unit_names
[] =
77 /* The classification of each unit in frv_unit_names[]. */
78 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
88 /* Return the DFA unit code associated with the Nth unit of integer
89 or floating-point group GROUP, */
90 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
92 /* Return the number of integer or floating-point unit UNIT
93 (1 for I1, 2 for F2, etc.). */
94 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
96 /* The DFA unit number for each unit in frv_unit_names[]. */
97 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
99 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
100 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
101 no instruction of type T has been seen. */
102 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
104 /* An array of dummy nop INSNs, one for each type of nop that the
106 static GTY(()) rtx_insn
*frv_nops
[NUM_NOP_PATTERNS
];
108 /* The number of nop instructions in frv_nops[]. */
109 static unsigned int frv_num_nops
;
111 /* The type of access. FRV_IO_UNKNOWN means the access can be either
112 a read or a write. */
113 enum frv_io_type
{ FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
};
115 /* Information about one __builtin_read or __builtin_write access, or
116 the combination of several such accesses. The most general value
117 is all-zeros (an unknown access to an unknown address). */
119 enum frv_io_type type
;
121 /* The constant address being accessed, or zero if not known. */
122 HOST_WIDE_INT const_address
;
124 /* The run-time address, as used in operand 0 of the membar pattern. */
128 /* Return true if instruction INSN should be packed with the following
130 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
132 /* Set the value of PACKING_FLAG_P(INSN). */
133 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
134 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
136 /* Loop with REG set to each hard register in rtx X. */
137 #define FOR_EACH_REGNO(REG, X) \
138 for (REG = REGNO (X); REG < END_REGNO (X); REG++)
140 /* This structure contains machine specific function data. */
141 struct GTY(()) machine_function
143 /* True if we have created an rtx that relies on the stack frame. */
146 /* True if this function contains at least one __builtin_{read,write}*. */
150 /* Temporary register allocation support structure. */
151 typedef struct frv_tmp_reg_struct
153 HARD_REG_SET regs
; /* possible registers to allocate */
154 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
158 /* Register state information for VLIW re-packing phase. */
159 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
160 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
161 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
162 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
164 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
166 typedef unsigned char regstate_t
;
168 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
176 /* Information required by frv_frame_access. */
179 /* This field is FRV_LOAD if registers are to be loaded from the stack and
180 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
181 the move is being done by the prologue code while FRV_LOAD implies it
182 is being done by the epilogue. */
183 enum frv_stack_op op
;
185 /* The base register to use when accessing the stack. This may be the
186 frame pointer, stack pointer, or a temporary. The choice of register
187 depends on which part of the frame is being accessed and how big the
191 /* The offset of BASE from the bottom of the current frame, in bytes. */
193 } frv_frame_accessor_t
;
195 /* Conditional execution support gathered together in one structure. */
198 /* Linked list of insns to add if the conditional execution conversion was
199 successful. Each link points to an EXPR_LIST which points to the pattern
200 of the insn to add, and the insn to be inserted before. */
201 rtx added_insns_list
;
203 /* Identify which registers are safe to allocate for if conversions to
204 conditional execution. We keep the last allocated register in the
205 register classes between COND_EXEC statements. This will mean we allocate
206 different registers for each different COND_EXEC group if we can. This
207 might allow the scheduler to intermix two different COND_EXEC sections. */
208 frv_tmp_reg_t tmp_reg
;
210 /* For nested IFs, identify which CC registers are used outside of setting
211 via a compare isnsn, and using via a check insn. This will allow us to
212 know if we can rewrite the register to use a different register that will
213 be paired with the CR register controlling the nested IF-THEN blocks. */
214 HARD_REG_SET nested_cc_ok_rewrite
;
216 /* Temporary registers allocated to hold constants during conditional
218 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
220 /* Current number of temp registers available. */
221 int cur_scratch_regs
;
223 /* Number of nested conditional execution blocks. */
224 int num_nested_cond_exec
;
226 /* Map of insns that set up constants in scratch registers. */
227 bitmap scratch_insns_bitmap
;
229 /* Conditional execution test register (CC0..CC7). */
232 /* Conditional execution compare register that is paired with cr_reg, so that
233 nested compares can be done. The csubcc and caddcc instructions don't
234 have enough bits to specify both a CC register to be set and a CR register
235 to do the test on, so the same bit number is used for both. Needless to
236 say, this is rather inconvenient for GCC. */
239 /* Extra CR registers used for &&, ||. */
243 /* Previous CR used in nested if, to make sure we are dealing with the same
244 nested if as the previous statement. */
245 rtx last_nested_if_cr
;
249 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
251 /* Map register number to smallest register class. */
252 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
254 /* Cached value of frv_stack_info. */
255 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
257 /* Forward references */
259 static void frv_option_override (void);
260 static bool frv_legitimate_address_p (machine_mode
, rtx
, bool);
261 static int frv_default_flags_for_cpu (void);
262 static int frv_string_begins_with (const char *, const char *);
263 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
264 static void frv_print_operand (FILE *, rtx
, int);
265 static void frv_print_operand_address (FILE *, machine_mode
, rtx
);
266 static bool frv_print_operand_punct_valid_p (unsigned char code
);
267 static void frv_print_operand_memory_reference_reg
269 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
270 static int frv_print_operand_jump_hint (rtx_insn
*);
271 static const char *comparison_string (enum rtx_code
, rtx
);
272 static rtx
frv_function_value (const_tree
, const_tree
,
274 static rtx
frv_libcall_value (machine_mode
,
276 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
277 static rtx
single_set_pattern (rtx
);
278 static int frv_function_contains_far_jump (void);
279 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
283 static rtx
frv_frame_offset_rtx (int);
284 static rtx
frv_frame_mem (machine_mode
, rtx
, int);
285 static rtx
frv_dwarf_store (rtx
, int);
286 static void frv_frame_insn (rtx
, rtx
);
287 static void frv_frame_access (frv_frame_accessor_t
*,
289 static void frv_frame_access_multi (frv_frame_accessor_t
*,
291 static void frv_frame_access_standard_regs (enum frv_stack_op
,
293 static struct machine_function
*frv_init_machine_status (void);
294 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
295 static machine_mode
frv_matching_accg_mode (machine_mode
);
296 static rtx
frv_read_argument (tree
, unsigned int);
297 static rtx
frv_read_iacc_argument (machine_mode
, tree
, unsigned int);
298 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
299 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
300 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
301 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
302 static rtx
frv_legitimize_address (rtx
, rtx
, machine_mode
);
303 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
304 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
305 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
306 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
307 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
308 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
309 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
310 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
311 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
312 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
313 static rtx
frv_expand_mclracc_builtin (tree
);
314 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
315 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
316 static rtx
frv_expand_noargs_builtin (enum insn_code
);
317 static void frv_split_iacc_move (rtx
, rtx
);
318 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
319 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
320 static rtx
frv_ifcvt_rewrite_mem (rtx
, machine_mode
, rtx
);
321 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
322 static unsigned int frv_insn_unit (rtx_insn
*);
323 static bool frv_issues_to_branch_unit_p (rtx_insn
*);
324 static int frv_cond_flags (rtx
);
325 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
326 static bool frv_registers_conflict_p (rtx
);
327 static void frv_registers_update_1 (rtx
, const_rtx
, void *);
328 static void frv_registers_update (rtx
);
329 static void frv_start_packet (void);
330 static void frv_start_packet_block (void);
331 static void frv_finish_packet (void (*) (void));
332 static bool frv_pack_insn_p (rtx_insn
*);
333 static void frv_add_insn_to_packet (rtx_insn
*);
334 static void frv_insert_nop_in_packet (rtx_insn
*);
335 static bool frv_for_each_packet (void (*) (void));
336 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
337 unsigned int, unsigned int,
338 unsigned int, unsigned int,
340 static int frv_compare_insns (const void *, const void *);
341 static void frv_sort_insn_group (enum frv_insn_group
);
342 static void frv_reorder_packet (void);
343 static void frv_fill_unused_units (enum frv_insn_group
);
344 static void frv_align_label (void);
345 static void frv_reorg_packet (void);
346 static void frv_register_nop (rtx
);
347 static void frv_reorg (void);
348 static void frv_pack_insns (void);
349 static void frv_function_prologue (FILE *);
350 static void frv_function_epilogue (FILE *);
351 static bool frv_assemble_integer (rtx
, unsigned, int);
352 static void frv_init_builtins (void);
353 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
354 static void frv_init_libfuncs (void);
355 static bool frv_in_small_data_p (const_tree
);
356 static void frv_asm_output_mi_thunk
357 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
358 static void frv_setup_incoming_varargs (cumulative_args_t
,
361 static rtx
frv_expand_builtin_saveregs (void);
362 static void frv_expand_builtin_va_start (tree
, rtx
);
363 static bool frv_rtx_costs (rtx
, machine_mode
, int, int,
365 static int frv_register_move_cost (machine_mode
,
366 reg_class_t
, reg_class_t
);
367 static int frv_memory_move_cost (machine_mode
,
369 static void frv_asm_out_constructor (rtx
, int);
370 static void frv_asm_out_destructor (rtx
, int);
371 static bool frv_function_symbol_referenced_p (rtx
);
372 static bool frv_legitimate_constant_p (machine_mode
, rtx
);
373 static bool frv_cannot_force_const_mem (machine_mode
, rtx
);
374 static const char *unspec_got_name (int);
375 static void frv_output_const_unspec (FILE *,
376 const struct frv_unspec
*);
377 static bool frv_function_ok_for_sibcall (tree
, tree
);
378 static rtx
frv_struct_value_rtx (tree
, int);
379 static bool frv_must_pass_in_stack (machine_mode mode
, const_tree type
);
380 static int frv_arg_partial_bytes (cumulative_args_t
, machine_mode
,
382 static rtx
frv_function_arg (cumulative_args_t
, machine_mode
,
384 static rtx
frv_function_incoming_arg (cumulative_args_t
, machine_mode
,
386 static void frv_function_arg_advance (cumulative_args_t
, machine_mode
,
388 static unsigned int frv_function_arg_boundary (machine_mode
,
390 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
392 static reg_class_t
frv_secondary_reload (bool, rtx
, reg_class_t
,
394 secondary_reload_info
*);
395 static bool frv_frame_pointer_required (void);
396 static bool frv_can_eliminate (const int, const int);
397 static void frv_conditional_register_usage (void);
398 static void frv_trampoline_init (rtx
, tree
, rtx
);
399 static bool frv_class_likely_spilled_p (reg_class_t
);
400 static unsigned int frv_hard_regno_nregs (unsigned int, machine_mode
);
401 static bool frv_hard_regno_mode_ok (unsigned int, machine_mode
);
402 static bool frv_modes_tieable_p (machine_mode
, machine_mode
);
404 /* Initialize the GCC target structure. */
405 #undef TARGET_PRINT_OPERAND
406 #define TARGET_PRINT_OPERAND frv_print_operand
407 #undef TARGET_PRINT_OPERAND_ADDRESS
408 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
409 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
410 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
411 #undef TARGET_ASM_FUNCTION_PROLOGUE
412 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
413 #undef TARGET_ASM_FUNCTION_EPILOGUE
414 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
415 #undef TARGET_ASM_INTEGER
416 #define TARGET_ASM_INTEGER frv_assemble_integer
417 #undef TARGET_OPTION_OVERRIDE
418 #define TARGET_OPTION_OVERRIDE frv_option_override
419 #undef TARGET_INIT_BUILTINS
420 #define TARGET_INIT_BUILTINS frv_init_builtins
421 #undef TARGET_EXPAND_BUILTIN
422 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
423 #undef TARGET_INIT_LIBFUNCS
424 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
425 #undef TARGET_IN_SMALL_DATA_P
426 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
427 #undef TARGET_REGISTER_MOVE_COST
428 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
429 #undef TARGET_MEMORY_MOVE_COST
430 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
431 #undef TARGET_RTX_COSTS
432 #define TARGET_RTX_COSTS frv_rtx_costs
433 #undef TARGET_ASM_CONSTRUCTOR
434 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
435 #undef TARGET_ASM_DESTRUCTOR
436 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
438 #undef TARGET_ASM_OUTPUT_MI_THUNK
439 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
440 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
441 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
443 #undef TARGET_SCHED_ISSUE_RATE
444 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
446 #undef TARGET_LEGITIMIZE_ADDRESS
447 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
449 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
450 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
451 #undef TARGET_LEGITIMATE_CONSTANT_P
452 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
453 #undef TARGET_CANNOT_FORCE_CONST_MEM
454 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
456 #undef TARGET_HAVE_TLS
457 #define TARGET_HAVE_TLS HAVE_AS_TLS
459 #undef TARGET_STRUCT_VALUE_RTX
460 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
461 #undef TARGET_MUST_PASS_IN_STACK
462 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
463 #undef TARGET_PASS_BY_REFERENCE
464 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
465 #undef TARGET_ARG_PARTIAL_BYTES
466 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
467 #undef TARGET_FUNCTION_ARG
468 #define TARGET_FUNCTION_ARG frv_function_arg
469 #undef TARGET_FUNCTION_INCOMING_ARG
470 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
471 #undef TARGET_FUNCTION_ARG_ADVANCE
472 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
473 #undef TARGET_FUNCTION_ARG_BOUNDARY
474 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
476 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
477 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
478 #undef TARGET_SETUP_INCOMING_VARARGS
479 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
480 #undef TARGET_MACHINE_DEPENDENT_REORG
481 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
483 #undef TARGET_EXPAND_BUILTIN_VA_START
484 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
487 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
488 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
491 #undef TARGET_CLASS_LIKELY_SPILLED_P
492 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
494 #undef TARGET_SECONDARY_RELOAD
495 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
498 #define TARGET_LRA_P hook_bool_void_false
500 #undef TARGET_LEGITIMATE_ADDRESS_P
501 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
503 #undef TARGET_FRAME_POINTER_REQUIRED
504 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
506 #undef TARGET_CAN_ELIMINATE
507 #define TARGET_CAN_ELIMINATE frv_can_eliminate
509 #undef TARGET_CONDITIONAL_REGISTER_USAGE
510 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
512 #undef TARGET_TRAMPOLINE_INIT
513 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
515 #undef TARGET_FUNCTION_VALUE
516 #define TARGET_FUNCTION_VALUE frv_function_value
517 #undef TARGET_LIBCALL_VALUE
518 #define TARGET_LIBCALL_VALUE frv_libcall_value
520 #undef TARGET_HARD_REGNO_NREGS
521 #define TARGET_HARD_REGNO_NREGS frv_hard_regno_nregs
522 #undef TARGET_HARD_REGNO_MODE_OK
523 #define TARGET_HARD_REGNO_MODE_OK frv_hard_regno_mode_ok
524 #undef TARGET_MODES_TIEABLE_P
525 #define TARGET_MODES_TIEABLE_P frv_modes_tieable_p
526 #undef TARGET_CONSTANT_ALIGNMENT
527 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
529 struct gcc_target targetm
= TARGET_INITIALIZER
;
531 #define FRV_SYMBOL_REF_TLS_P(RTX) \
532 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
535 /* Any function call that satisfies the machine-independent
536 requirements is eligible on FR-V. */
539 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
540 tree exp ATTRIBUTE_UNUSED
)
545 /* Return true if SYMBOL is a small data symbol and relocation RELOC
546 can be used to access it directly in a load or store. */
548 static FRV_INLINE
bool
549 frv_small_data_reloc_p (rtx symbol
, int reloc
)
551 return (GET_CODE (symbol
) == SYMBOL_REF
552 && SYMBOL_REF_SMALL_P (symbol
)
553 && (!TARGET_FDPIC
|| flag_pic
== 1)
554 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
557 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
561 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
563 if (GET_CODE (x
) == CONST
)
567 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
569 unspec
->offset
+= INTVAL (XEXP (x
, 1));
572 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
574 unspec
->symbol
= XVECEXP (x
, 0, 0);
575 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
577 if (unspec
->offset
== 0)
580 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
581 && unspec
->offset
> 0
582 && unspec
->offset
< g_switch_value
)
589 /* Decide whether we can force certain constants to memory. If we
590 decide we can't, the caller should be able to cope with it in
593 We never allow constants to be forced into memory for TARGET_FDPIC.
594 This is necessary for several reasons:
596 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
597 target-independent code will try to force them into the constant
598 pool, thus leading to infinite recursion.
600 2. We can never introduce new constant pool references during reload.
601 Any such reference would require use of the pseudo FDPIC register.
603 3. We can't represent a constant added to a function pointer (which is
604 not the same as a pointer to a function+constant).
606 4. In many cases, it's more efficient to calculate the constant in-line. */
609 frv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
,
610 rtx x ATTRIBUTE_UNUSED
)
616 frv_default_flags_for_cpu (void)
618 switch (frv_cpu_type
)
620 case FRV_CPU_GENERIC
:
621 return MASK_DEFAULT_FRV
;
624 return MASK_DEFAULT_FR550
;
628 return MASK_DEFAULT_FR500
;
631 return MASK_DEFAULT_FR450
;
635 return MASK_DEFAULT_FR400
;
639 return MASK_DEFAULT_SIMPLE
;
646 /* Implement TARGET_OPTION_OVERRIDE. */
649 frv_option_override (void)
654 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
656 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
657 linker about linking pic and non-pic code. */
660 if (!flag_pic
) /* -fPIC */
663 if (!global_options_set
.x_g_switch_value
) /* -G0 */
669 /* A C expression whose value is a register class containing hard
670 register REGNO. In general there is more than one such class;
671 choose a class which is "minimal", meaning that no smaller class
672 also contains the register. */
674 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
676 enum reg_class rclass
;
680 int gpr_reg
= regno
- GPR_FIRST
;
682 if (gpr_reg
== GR8_REG
)
685 else if (gpr_reg
== GR9_REG
)
688 else if (gpr_reg
== GR14_REG
)
689 rclass
= FDPIC_FPTR_REGS
;
691 else if (gpr_reg
== FDPIC_REGNO
)
694 else if ((gpr_reg
& 3) == 0)
697 else if ((gpr_reg
& 1) == 0)
704 else if (FPR_P (regno
))
706 int fpr_reg
= regno
- GPR_FIRST
;
707 if ((fpr_reg
& 3) == 0)
708 rclass
= QUAD_FPR_REGS
;
710 else if ((fpr_reg
& 1) == 0)
717 else if (regno
== LR_REGNO
)
720 else if (regno
== LCR_REGNO
)
723 else if (ICC_P (regno
))
726 else if (FCC_P (regno
))
729 else if (ICR_P (regno
))
732 else if (FCR_P (regno
))
735 else if (ACC_P (regno
))
737 int r
= regno
- ACC_FIRST
;
739 rclass
= QUAD_ACC_REGS
;
740 else if ((r
& 1) == 0)
741 rclass
= EVEN_ACC_REGS
;
746 else if (ACCG_P (regno
))
752 regno_reg_class
[regno
] = rclass
;
755 /* Check for small data option */
756 if (!global_options_set
.x_g_switch_value
&& !TARGET_LIBPIC
)
757 g_switch_value
= SDATA_DEFAULT_SIZE
;
759 /* There is no single unaligned SI op for PIC code. Sometimes we
760 need to use ".4byte" and sometimes we need to use ".picptr".
761 See frv_assemble_integer for details. */
762 if (flag_pic
|| TARGET_FDPIC
)
763 targetm
.asm_out
.unaligned_op
.si
= 0;
765 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
766 target_flags
|= MASK_LINKED_FP
;
768 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
769 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
771 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
772 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
774 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
775 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
777 init_machine_status
= frv_init_machine_status
;
781 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
784 frv_string_begins_with (const char *name
, const char *prefix
)
786 const int prefix_len
= strlen (prefix
);
788 /* Remember: NAME's length includes the null terminator. */
789 return (strncmp (name
, prefix
, prefix_len
) == 0);
792 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
795 frv_conditional_register_usage (void)
799 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
800 fixed_regs
[i
] = call_used_regs
[i
] = 1;
802 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
803 fixed_regs
[i
] = call_used_regs
[i
] = 1;
805 /* Reserve the registers used for conditional execution. At present, we need
806 1 ICC and 1 ICR register. */
807 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
808 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
812 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
813 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
814 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
815 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
819 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
820 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
823 /* If -fpic, SDA_BASE_REG is the PIC register. */
824 if (g_switch_value
== 0 && !flag_pic
)
825 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
828 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
834 * Compute the stack frame layout
837 * +---------------+-----------------------+-----------------------+
838 * |Register |type |caller-save/callee-save|
839 * +---------------+-----------------------+-----------------------+
840 * |GR0 |Zero register | - |
841 * |GR1 |Stack pointer(SP) | - |
842 * |GR2 |Frame pointer(FP) | - |
843 * |GR3 |Hidden parameter | caller save |
844 * |GR4-GR7 | - | caller save |
845 * |GR8-GR13 |Argument register | caller save |
846 * |GR14-GR15 | - | caller save |
847 * |GR16-GR31 | - | callee save |
848 * |GR32-GR47 | - | caller save |
849 * |GR48-GR63 | - | callee save |
850 * |FR0-FR15 | - | caller save |
851 * |FR16-FR31 | - | callee save |
852 * |FR32-FR47 | - | caller save |
853 * |FR48-FR63 | - | callee save |
854 * +---------------+-----------------------+-----------------------+
858 * SP-> |-----------------------------------|
860 * |-----------------------------------|
861 * | Register save area |
862 * |-----------------------------------|
863 * | Local variable save area |
864 * FP-> |-----------------------------------|
866 * |-----------------------------------|
867 * | Hidden parameter save area |
868 * |-----------------------------------|
869 * | Return address(LR) storage area |
870 * |-----------------------------------|
871 * | Padding for alignment |
872 * |-----------------------------------|
873 * | Register argument area |
874 * OLD SP-> |-----------------------------------|
876 * |-----------------------------------|
879 * Argument area/Parameter area:
881 * When a function is called, this area is used for argument transfer. When
882 * the argument is set up by the caller function, this area is referred to as
883 * the argument area. When the argument is referenced by the callee function,
884 * this area is referred to as the parameter area. The area is allocated when
885 * all arguments cannot be placed on the argument register at the time of
888 * Register save area:
890 * This is a register save area that must be guaranteed for the caller
891 * function. This area is not secured when the register save operation is not
894 * Local variable save area:
896 * This is the area for local variables and temporary variables.
900 * This area stores the FP value of the caller function.
902 * Hidden parameter save area:
904 * This area stores the start address of the return value storage
905 * area for a struct/union return function.
906 * When a struct/union is used as the return value, the caller
907 * function stores the return value storage area start address in
908 * register GR3 and passes it to the caller function.
909 * The callee function interprets the address stored in the GR3
910 * as the return value storage area start address.
911 * When register GR3 needs to be saved into memory, the callee
912 * function saves it in the hidden parameter save area. This
913 * area is not secured when the save operation is not needed.
915 * Return address(LR) storage area:
917 * This area saves the LR. The LR stores the address of a return to the caller
918 * function for the purpose of function calling.
920 * Argument register area:
922 * This area saves the argument register. This area is not secured when the
923 * save operation is not needed.
927 * Arguments, the count of which equals the count of argument registers (6
928 * words), are positioned in registers GR8 to GR13 and delivered to the callee
929 * function. When a struct/union return function is called, the return value
930 * area address is stored in register GR3. Arguments not placed in the
931 * argument registers will be stored in the stack argument area for transfer
932 * purposes. When an 8-byte type argument is to be delivered using registers,
933 * it is divided into two and placed in two registers for transfer. When
934 * argument registers must be saved to memory, the callee function secures an
935 * argument register save area in the stack. In this case, a continuous
936 * argument register save area must be established in the parameter area. The
937 * argument register save area must be allocated as needed to cover the size of
938 * the argument register to be saved. If the function has a variable count of
939 * arguments, it saves all argument registers in the argument register save
942 * Argument Extension Format:
944 * When an argument is to be stored in the stack, its type is converted to an
945 * extended type in accordance with the individual argument type. The argument
946 * is freed by the caller function after the return from the callee function is
949 * +-----------------------+---------------+------------------------+
950 * | Argument Type |Extended Type |Stack Storage Size(byte)|
951 * +-----------------------+---------------+------------------------+
953 * |signed char |int | 4 |
954 * |unsigned char |int | 4 |
955 * |[signed] short int |int | 4 |
956 * |unsigned short int |int | 4 |
957 * |[signed] int |No extension | 4 |
958 * |unsigned int |No extension | 4 |
959 * |[signed] long int |No extension | 4 |
960 * |unsigned long int |No extension | 4 |
961 * |[signed] long long int |No extension | 8 |
962 * |unsigned long long int |No extension | 8 |
963 * |float |double | 8 |
964 * |double |No extension | 8 |
965 * |long double |No extension | 8 |
966 * |pointer |No extension | 4 |
967 * |struct/union |- | 4 (*1) |
968 * +-----------------------+---------------+------------------------+
970 * When a struct/union is to be delivered as an argument, the caller copies it
971 * to the local variable area and delivers the address of that area.
975 * +-------------------------------+----------------------+
976 * |Return Value Type |Return Value Interface|
977 * +-------------------------------+----------------------+
979 * |[signed|unsigned] char |GR8 |
980 * |[signed|unsigned] short int |GR8 |
981 * |[signed|unsigned] int |GR8 |
982 * |[signed|unsigned] long int |GR8 |
984 * |[signed|unsigned] long long int|GR8 & GR9 |
986 * |double |GR8 & GR9 |
987 * |long double |GR8 & GR9 |
988 * |struct/union |(*1) |
989 * +-------------------------------+----------------------+
991 * When a struct/union is used as the return value, the caller function stores
992 * the start address of the return value storage area into GR3 and then passes
993 * it to the callee function. The callee function interprets GR3 as the start
994 * address of the return value storage area. When this address needs to be
995 * saved in memory, the callee function secures the hidden parameter save area
996 * and saves the address in that area.
1000 frv_stack_info (void)
1002 static frv_stack_t info
, zero_info
;
1003 frv_stack_t
*info_ptr
= &info
;
1004 tree fndecl
= current_function_decl
;
1012 /* If we've already calculated the values and reload is complete,
1014 if (frv_stack_cache
)
1015 return frv_stack_cache
;
1017 /* Zero all fields. */
1020 /* Set up the register range information. */
1021 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1022 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1023 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1024 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1026 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1027 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1028 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1029 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1031 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1032 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1033 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1034 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1036 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1037 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1038 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1039 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1041 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1042 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1043 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1045 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1046 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1047 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1048 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1049 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1051 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1052 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1053 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1054 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1056 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1057 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1058 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1059 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1061 /* Determine if this is a stdarg function. If so, allocate space to store
1068 /* Find the last argument, and see if it is __builtin_va_alist. */
1069 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1071 next_arg
= DECL_CHAIN (cur_arg
);
1072 if (next_arg
== (tree
)0)
1074 if (DECL_NAME (cur_arg
)
1075 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1083 /* Iterate over all of the register ranges. */
1084 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1086 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1087 int first
= reg_ptr
->first
;
1088 int last
= reg_ptr
->last
;
1090 int size_2words
= 0;
1093 /* Calculate which registers need to be saved & save area size. */
1097 for (regno
= first
; regno
<= last
; regno
++)
1099 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1100 || (crtl
->calls_eh_return
1101 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1102 || (!TARGET_FDPIC
&& flag_pic
1103 && crtl
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1105 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1106 size_1word
+= UNITS_PER_WORD
;
1111 /* Calculate whether we need to create a frame after everything else
1112 has been processed. */
1117 if (df_regs_ever_live_p (LR_REGNO
)
1119 /* This is set for __builtin_return_address, etc. */
1120 || cfun
->machine
->frame_needed
1121 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1122 || (!TARGET_FDPIC
&& flag_pic
1123 && crtl
->uses_pic_offset_table
))
1125 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1126 size_1word
+= UNITS_PER_WORD
;
1130 case STACK_REGS_STDARG
:
1133 /* If this is a stdarg function with a non varardic
1134 argument split between registers and the stack,
1135 adjust the saved registers downward. */
1136 last
-= (ADDR_ALIGN (crtl
->args
.pretend_args_size
, UNITS_PER_WORD
)
1139 for (regno
= first
; regno
<= last
; regno
++)
1141 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1142 size_1word
+= UNITS_PER_WORD
;
1145 info_ptr
->stdarg_size
= size_1word
;
1149 case STACK_REGS_STRUCT
:
1150 if (cfun
->returns_struct
)
1152 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1153 size_1word
+= UNITS_PER_WORD
;
1161 /* If this is a field, it only takes one word. */
1162 if (reg_ptr
->field_p
)
1163 size_1word
= UNITS_PER_WORD
;
1165 /* Determine which register pairs can be saved together. */
1166 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1168 for (regno
= first
; regno
< last
; regno
+= 2)
1170 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1172 size_2words
+= 2 * UNITS_PER_WORD
;
1173 size_1word
-= 2 * UNITS_PER_WORD
;
1174 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1175 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1180 reg_ptr
->size_1word
= size_1word
;
1181 reg_ptr
->size_2words
= size_2words
;
1183 if (! reg_ptr
->special_p
)
1185 info_ptr
->regs_size_1word
+= size_1word
;
1186 info_ptr
->regs_size_2words
+= size_2words
;
1191 /* Set up the sizes of each field in the frame body, making the sizes
1192 of each be divisible by the size of a dword if dword operations might
1193 be used, or the size of a word otherwise. */
1194 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1196 info_ptr
->parameter_size
= ADDR_ALIGN (crtl
->outgoing_args_size
, alignment
);
1197 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1198 + info_ptr
->regs_size_1word
,
1200 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1202 info_ptr
->pretend_size
= crtl
->args
.pretend_args_size
;
1204 /* Work out the size of the frame, excluding the header. Both the frame
1205 body and register parameter area will be dword-aligned. */
1206 info_ptr
->total_size
1207 = (ADDR_ALIGN (info_ptr
->parameter_size
1208 + info_ptr
->regs_size
1209 + info_ptr
->vars_size
,
1211 + ADDR_ALIGN (info_ptr
->pretend_size
1212 + info_ptr
->stdarg_size
,
1213 2 * UNITS_PER_WORD
));
1215 /* See if we need to create a frame at all, if so add header area. */
1216 if (info_ptr
->total_size
> 0
1217 || frame_pointer_needed
1218 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1219 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1221 offset
= info_ptr
->parameter_size
;
1222 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1223 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1225 /* Calculate the offsets to save normal register pairs. */
1226 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1228 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1229 if (! reg_ptr
->special_p
)
1231 int first
= reg_ptr
->first
;
1232 int last
= reg_ptr
->last
;
1235 for (regno
= first
; regno
<= last
; regno
++)
1236 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1237 && regno
!= FRAME_POINTER_REGNUM
1238 && (regno
< FIRST_ARG_REGNUM
1239 || regno
> LAST_ARG_REGNUM
))
1241 info_ptr
->reg_offset
[regno
] = offset
;
1242 offset
+= 2 * UNITS_PER_WORD
;
1247 /* Calculate the offsets to save normal single registers. */
1248 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1250 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1251 if (! reg_ptr
->special_p
)
1253 int first
= reg_ptr
->first
;
1254 int last
= reg_ptr
->last
;
1257 for (regno
= first
; regno
<= last
; regno
++)
1258 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1259 && regno
!= FRAME_POINTER_REGNUM
1260 && (regno
< FIRST_ARG_REGNUM
1261 || regno
> LAST_ARG_REGNUM
))
1263 info_ptr
->reg_offset
[regno
] = offset
;
1264 offset
+= UNITS_PER_WORD
;
1269 /* Calculate the offset to save the local variables at. */
1270 offset
= ADDR_ALIGN (offset
, alignment
);
1271 if (info_ptr
->vars_size
)
1273 info_ptr
->vars_offset
= offset
;
1274 offset
+= info_ptr
->vars_size
;
1277 /* Align header to a dword-boundary. */
1278 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1280 /* Calculate the offsets in the fixed frame. */
1281 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1282 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1283 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1285 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1286 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1287 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1289 if (cfun
->returns_struct
)
1291 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1292 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1293 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1296 /* Calculate the offsets to store the arguments passed in registers
1297 for stdarg functions. The register pairs are first and the single
1298 register if any is last. The register save area starts on a
1300 if (info_ptr
->stdarg_size
)
1302 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1303 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1306 /* Skip the header. */
1307 offset
+= 4 * UNITS_PER_WORD
;
1308 for (regno
= first
; regno
<= last
; regno
++)
1310 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1312 info_ptr
->reg_offset
[regno
] = offset
;
1313 offset
+= 2 * UNITS_PER_WORD
;
1315 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1317 info_ptr
->reg_offset
[regno
] = offset
;
1318 offset
+= UNITS_PER_WORD
;
1324 if (reload_completed
)
1325 frv_stack_cache
= info_ptr
;
1331 /* Print the information about the frv stack offsets, etc. when debugging. */
1334 frv_debug_stack (frv_stack_t
*info
)
1339 info
= frv_stack_info ();
1341 fprintf (stderr
, "\nStack information for function %s:\n",
1342 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1343 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1346 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1347 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1348 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1349 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1350 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1352 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1353 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1354 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1355 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1357 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1359 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1360 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1362 int first
= regs
->first
;
1363 int last
= regs
->last
;
1366 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1367 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1368 regs
->size_1word
, regs
->size_2words
);
1370 for (regno
= first
; regno
<= last
; regno
++)
1372 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1373 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1374 info
->reg_offset
[regno
]);
1376 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1377 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1378 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1381 fputc ('\n', stderr
);
1391 /* Used during final to control the packing of insns. The value is
1392 1 if the current instruction should be packed with the next one,
1393 0 if it shouldn't or -1 if packing is disabled altogether. */
1395 static int frv_insn_packing_flag
;
1397 /* True if the current function contains a far jump. */
1400 frv_function_contains_far_jump (void)
1402 rtx_insn
*insn
= get_insns ();
1405 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1406 insn
= NEXT_INSN (insn
);
1407 return (insn
!= NULL
);
1410 /* For the FRV, this function makes sure that a function with far jumps
1411 will return correctly. It also does the VLIW packing. */
1414 frv_function_prologue (FILE *file
)
1416 rtx_insn
*insn
, *next
, *last_call
;
1418 /* If no frame was created, check whether the function uses a call
1419 instruction to implement a far jump. If so, save the link in gr3 and
1420 replace all returns to LR with returns to GR3. GR3 is used because it
1421 is call-clobbered, because is not available to the register allocator,
1422 and because all functions that take a hidden argument pointer will have
1424 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1428 /* Just to check that the above comment is true. */
1429 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1431 /* Generate the instruction that saves the link register. */
1432 fprintf (file
, "\tmovsg lr,gr3\n");
1434 /* Replace the LR with GR3 in *return_internal patterns. The insn
1435 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1436 simply emit a different assembly directive because bralr and jmpl
1437 execute in different units. */
1438 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1441 rtx pattern
= PATTERN (insn
);
1442 if (GET_CODE (pattern
) == PARALLEL
1443 && XVECLEN (pattern
, 0) >= 2
1444 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1445 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1447 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1448 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1449 SET_REGNO (address
, GPR_FIRST
+ 3);
1456 /* Allow the garbage collector to free the nops created by frv_reorg. */
1457 memset (frv_nops
, 0, sizeof (frv_nops
));
1459 /* Locate CALL_ARG_LOCATION notes that have been misplaced
1460 and move them back to where they should be located. */
1462 for (insn
= get_insns (); insn
; insn
= next
)
1464 next
= NEXT_INSN (insn
);
1466 || (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
1467 && CALL_P (XVECEXP (PATTERN (insn
), 0, 0))))
1470 if (!NOTE_P (insn
) || NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
1473 if (NEXT_INSN (last_call
) == insn
)
1476 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1477 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1478 SET_PREV_INSN (insn
) = last_call
;
1479 SET_NEXT_INSN (insn
) = NEXT_INSN (last_call
);
1480 SET_PREV_INSN (NEXT_INSN (insn
)) = insn
;
1481 SET_NEXT_INSN (PREV_INSN (insn
)) = insn
;
1487 /* Return the next available temporary register in a given class. */
1490 frv_alloc_temp_reg (
1491 frv_tmp_reg_t
*info
, /* which registers are available */
1492 enum reg_class rclass
, /* register class desired */
1493 machine_mode mode
, /* mode to allocate register with */
1494 int mark_as_used
, /* register not available after allocation */
1495 int no_abort
) /* return NULL instead of aborting */
1497 int regno
= info
->next_reg
[ (int)rclass
];
1498 int orig_regno
= regno
;
1499 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)rclass
];
1504 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1505 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1508 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1510 if (regno
== orig_regno
)
1512 gcc_assert (no_abort
);
1517 nr
= hard_regno_nregs (regno
, mode
);
1518 info
->next_reg
[ (int)rclass
] = regno
+ nr
;
1521 for (i
= 0; i
< nr
; i
++)
1522 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1524 return gen_rtx_REG (mode
, regno
);
1528 /* Return an rtx with the value OFFSET, which will either be a register or a
1529 signed 12-bit integer. It can be used as the second operand in an "add"
1530 instruction, or as the index in a load or store.
1532 The function returns a constant rtx if OFFSET is small enough, otherwise
1533 it loads the constant into register OFFSET_REGNO and returns that. */
1535 frv_frame_offset_rtx (int offset
)
1537 rtx offset_rtx
= GEN_INT (offset
);
1538 if (IN_RANGE (offset
, -2048, 2047))
1542 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1543 if (IN_RANGE (offset
, -32768, 32767))
1544 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1547 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1548 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1554 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1555 prologue and epilogue uses such expressions to access the stack. */
1557 frv_frame_mem (machine_mode mode
, rtx base
, int offset
)
1559 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1561 frv_frame_offset_rtx (offset
)));
1564 /* Generate a frame-related expression:
1566 (set REG (mem (plus (sp) (const_int OFFSET)))).
1568 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1569 instructions. Marking the expressions as frame-related is superfluous if
1570 the note contains just a single set. But if the note contains a PARALLEL
1571 or SEQUENCE that has several sets, each set must be individually marked
1572 as frame-related. */
1574 frv_dwarf_store (rtx reg
, int offset
)
1576 rtx set
= gen_rtx_SET (gen_rtx_MEM (GET_MODE (reg
),
1577 plus_constant (Pmode
, stack_pointer_rtx
,
1580 RTX_FRAME_RELATED_P (set
) = 1;
1584 /* Emit a frame-related instruction whose pattern is PATTERN. The
1585 instruction is the last in a sequence that cumulatively performs the
1586 operation described by DWARF_PATTERN. The instruction is marked as
1587 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1590 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1592 rtx insn
= emit_insn (pattern
);
1593 RTX_FRAME_RELATED_P (insn
) = 1;
1594 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1599 /* Emit instructions that transfer REG to or from the memory location (sp +
1600 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1601 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1602 function to store registers and only the epilogue uses it to load them.
1604 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1605 The generated instruction will use BASE as its base register. BASE may
1606 simply be the stack pointer, but if several accesses are being made to a
1607 region far away from the stack pointer, it may be more efficient to set
1608 up a temporary instead.
1610 Store instructions will be frame-related and will be annotated with the
1611 overall effect of the store. Load instructions will be followed by a
1612 (use) to prevent later optimizations from zapping them.
1614 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1615 as a temporary in such cases. */
1617 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1619 machine_mode mode
= GET_MODE (reg
);
1620 rtx mem
= frv_frame_mem (mode
,
1622 stack_offset
- accessor
->base_offset
);
1624 if (accessor
->op
== FRV_LOAD
)
1626 if (SPR_P (REGNO (reg
)))
1628 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1629 emit_insn (gen_rtx_SET (temp
, mem
));
1630 emit_insn (gen_rtx_SET (reg
, temp
));
1634 /* We cannot use reg+reg addressing for DImode access. */
1636 && GET_CODE (XEXP (mem
, 0)) == PLUS
1637 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1638 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1640 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1642 emit_move_insn (temp
,
1643 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1644 XEXP (XEXP (mem
, 0), 1)));
1645 mem
= gen_rtx_MEM (DImode
, temp
);
1647 emit_insn (gen_rtx_SET (reg
, mem
));
1653 if (SPR_P (REGNO (reg
)))
1655 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1656 emit_insn (gen_rtx_SET (temp
, reg
));
1657 frv_frame_insn (gen_rtx_SET (mem
, temp
),
1658 frv_dwarf_store (reg
, stack_offset
));
1660 else if (mode
== DImode
)
1662 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1663 with a separate save for each register. */
1664 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1665 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1666 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1667 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1669 /* Also we cannot use reg+reg addressing. */
1670 if (GET_CODE (XEXP (mem
, 0)) == PLUS
1671 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1672 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1674 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1675 emit_move_insn (temp
,
1676 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1677 XEXP (XEXP (mem
, 0), 1)));
1678 mem
= gen_rtx_MEM (DImode
, temp
);
1681 frv_frame_insn (gen_rtx_SET (mem
, reg
),
1682 gen_rtx_PARALLEL (VOIDmode
,
1683 gen_rtvec (2, set1
, set2
)));
1686 frv_frame_insn (gen_rtx_SET (mem
, reg
),
1687 frv_dwarf_store (reg
, stack_offset
));
1691 /* A function that uses frv_frame_access to transfer a group of registers to
1692 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1693 is the stack information generated by frv_stack_info, and REG_SET is the
1694 number of the register set to transfer. */
1696 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1700 frv_stack_regs_t
*regs_info
;
1703 regs_info
= &info
->regs
[reg_set
];
1704 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1705 if (info
->save_p
[regno
])
1706 frv_frame_access (accessor
,
1707 info
->save_p
[regno
] == REG_SAVE_2WORDS
1708 ? gen_rtx_REG (DImode
, regno
)
1709 : gen_rtx_REG (SImode
, regno
),
1710 info
->reg_offset
[regno
]);
1713 /* Save or restore callee-saved registers that are kept outside the frame
1714 header. The function saves the registers if OP is FRV_STORE and restores
1715 them if OP is FRV_LOAD. INFO is the stack information generated by
1718 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1720 frv_frame_accessor_t accessor
;
1723 accessor
.base
= stack_pointer_rtx
;
1724 accessor
.base_offset
= 0;
1725 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1726 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1727 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1731 /* Called after register allocation to add any instructions needed for the
1732 prologue. Using a prologue insn is favored compared to putting all of the
1733 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1734 it allows the scheduler to intermix instructions with the saves of
1735 the caller saved registers. In some cases, it might be necessary
1736 to emit a barrier instruction as the last insn to prevent such
1739 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1740 so that the debug info generation code can handle them properly. */
1742 frv_expand_prologue (void)
1744 frv_stack_t
*info
= frv_stack_info ();
1745 rtx sp
= stack_pointer_rtx
;
1746 rtx fp
= frame_pointer_rtx
;
1747 frv_frame_accessor_t accessor
;
1749 if (TARGET_DEBUG_STACK
)
1750 frv_debug_stack (info
);
1752 if (flag_stack_usage_info
)
1753 current_function_static_stack_size
= info
->total_size
;
1755 if (info
->total_size
== 0)
1758 /* We're interested in three areas of the frame here:
1760 A: the register save area
1762 C: the header after B
1764 If the frame pointer isn't used, we'll have to set up A, B and C
1765 using the stack pointer. If the frame pointer is used, we'll access
1769 B: set up using sp or a temporary (see below)
1772 We set up B using the stack pointer if the frame is small enough.
1773 Otherwise, it's more efficient to copy the old stack pointer into a
1774 temporary and use that.
1776 Note that it's important to make sure the prologue and epilogue use the
1777 same registers to access A and C, since doing otherwise will confuse
1778 the aliasing code. */
1780 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1781 isn't used, the same method will serve for C. */
1782 accessor
.op
= FRV_STORE
;
1783 if (frame_pointer_needed
&& info
->total_size
> 2048)
1785 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1786 accessor
.base_offset
= info
->total_size
;
1787 emit_insn (gen_movsi (accessor
.base
, sp
));
1791 accessor
.base
= stack_pointer_rtx
;
1792 accessor
.base_offset
= 0;
1795 /* Allocate the stack space. */
1797 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1798 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1800 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1801 gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1804 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1805 and point the new one to that location. */
1806 if (frame_pointer_needed
)
1808 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1810 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1811 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1813 rtx asm_src
= plus_constant (Pmode
, accessor
.base
,
1814 fp_offset
- accessor
.base_offset
);
1815 rtx dwarf_src
= plus_constant (Pmode
, sp
, fp_offset
);
1817 /* Store the old frame pointer at (sp + FP_OFFSET). */
1818 frv_frame_access (&accessor
, fp
, fp_offset
);
1820 /* Set up the new frame pointer. */
1821 frv_frame_insn (gen_rtx_SET (fp
, asm_src
),
1822 gen_rtx_SET (fp
, dwarf_src
));
1824 /* Access region C from the frame pointer. */
1826 accessor
.base_offset
= fp_offset
;
1829 /* Set up region C. */
1830 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1831 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1832 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1834 /* Set up region A. */
1835 frv_frame_access_standard_regs (FRV_STORE
, info
);
1837 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1838 scheduler from moving loads before the stores saving the registers. */
1839 if (info
->stdarg_size
> 0)
1840 emit_insn (gen_blockage ());
1842 /* Set up pic register/small data register for this function. */
1843 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
1844 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1845 gen_rtx_REG (Pmode
, LR_REGNO
),
1846 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1850 /* Under frv, all of the work is done via frv_expand_epilogue, but
1851 this function provides a convenient place to do cleanup. */
1854 frv_function_epilogue (FILE *)
1856 frv_stack_cache
= (frv_stack_t
*)0;
1858 /* Zap last used registers for conditional execution. */
1859 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1861 /* Release the bitmap of created insns. */
1862 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1866 /* Called after register allocation to add any instructions needed for the
1867 epilogue. Using an epilogue insn is favored compared to putting all of the
1868 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1869 it allows the scheduler to intermix instructions with the saves of
1870 the caller saved registers. In some cases, it might be necessary
1871 to emit a barrier instruction as the last insn to prevent such
1875 frv_expand_epilogue (bool emit_return
)
1877 frv_stack_t
*info
= frv_stack_info ();
1878 rtx fp
= frame_pointer_rtx
;
1879 rtx sp
= stack_pointer_rtx
;
1883 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1885 /* Restore the stack pointer to its original value if alloca or the like
1887 if (! crtl
->sp_is_unchanging
)
1888 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1890 /* Restore the callee-saved registers that were used in this function. */
1891 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1893 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1894 no return instruction should be emitted. */
1895 if (info
->save_p
[LR_REGNO
])
1900 /* Use the same method to access the link register's slot as we did in
1901 the prologue. In other words, use the frame pointer if available,
1902 otherwise use the stack pointer.
1904 LR_OFFSET is the offset of the link register's slot from the start
1905 of the frame and MEM is a memory rtx for it. */
1906 lr_offset
= info
->reg_offset
[LR_REGNO
];
1907 if (frame_pointer_needed
)
1908 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1910 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1912 /* Load the old link register into a GPR. */
1913 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1914 emit_insn (gen_rtx_SET (return_addr
, mem
));
1917 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1919 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1920 the load is preserved. */
1921 if (frame_pointer_needed
)
1923 emit_insn (gen_rtx_SET (fp
, gen_rtx_MEM (Pmode
, fp
)));
1927 /* Deallocate the stack frame. */
1928 if (info
->total_size
!= 0)
1930 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1931 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1934 /* If this function uses eh_return, add the final stack adjustment now. */
1935 if (crtl
->calls_eh_return
)
1936 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1939 emit_jump_insn (gen_epilogue_return (return_addr
));
1942 rtx lr
= return_addr
;
1944 if (REGNO (return_addr
) != LR_REGNO
)
1946 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1947 emit_move_insn (lr
, return_addr
);
1955 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1958 frv_asm_output_mi_thunk (FILE *file
,
1959 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1960 HOST_WIDE_INT delta
,
1961 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1964 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1965 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1966 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1967 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1969 /* Do the add using an addi if possible. */
1970 if (IN_RANGE (delta
, -2048, 2047))
1971 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1974 const char *const name_add
= reg_names
[TEMP_REGNO
];
1975 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1976 parallel
, delta
, name_add
);
1977 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1979 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1984 const char *name_pic
= reg_names
[FDPIC_REGNO
];
1985 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
1989 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
1990 assemble_name (file
, name_func
);
1991 fprintf (file
, "),%s\n", name_jmp
);
1993 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
1994 assemble_name (file
, name_func
);
1995 fprintf (file
, "),%s\n", name_jmp
);
1997 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
2001 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
2002 assemble_name (file
, name_func
);
2003 fprintf (file
, "\t)), %s\n", name_jmp
);
2008 fprintf (file
, "\tsethi%s #hi(", parallel
);
2009 assemble_name (file
, name_func
);
2010 fprintf (file
, "),%s\n", name_jmp
);
2012 fprintf (file
, "\tsetlo #lo(");
2013 assemble_name (file
, name_func
);
2014 fprintf (file
, "),%s\n", name_jmp
);
2018 /* Use JUMP_REGNO as a temporary PIC register. */
2019 const char *name_lr
= reg_names
[LR_REGNO
];
2020 const char *name_gppic
= name_jmp
;
2021 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2023 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2024 fprintf (file
, "\tcall 1f\n");
2025 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2026 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2027 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2028 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2029 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2031 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2032 assemble_name (file
, name_func
);
2033 fprintf (file
, "),%s\n", name_tmp
);
2035 fprintf (file
, "\tsetlo #gprello(");
2036 assemble_name (file
, name_func
);
2037 fprintf (file
, "),%s\n", name_tmp
);
2039 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2042 /* Jump to the function address. */
2043 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2048 /* On frv, create a frame whenever we need to create stack. */
2051 frv_frame_pointer_required (void)
2053 /* If we forgoing the usual linkage requirements, we only need
2054 a frame pointer if the stack pointer might change. */
2055 if (!TARGET_LINKED_FP
)
2056 return !crtl
->sp_is_unchanging
;
2058 if (! crtl
->is_leaf
)
2061 if (get_frame_size () != 0)
2067 if (!crtl
->sp_is_unchanging
)
2070 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
2076 if (cfun
->machine
->frame_needed
)
2083 /* Worker function for TARGET_CAN_ELIMINATE. */
2086 frv_can_eliminate (const int from
, const int to
)
2088 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
2089 ? ! frame_pointer_needed
2093 /* This function returns the initial difference between the specified
2094 pair of registers. */
2096 /* See frv_stack_info for more details on the frv stack frame. */
2099 frv_initial_elimination_offset (int from
, int to
)
2101 frv_stack_t
*info
= frv_stack_info ();
2104 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2105 ret
= info
->total_size
- info
->pretend_size
;
2107 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2108 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2110 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2111 ret
= (info
->total_size
2112 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2113 - info
->pretend_size
);
2118 if (TARGET_DEBUG_STACK
)
2119 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2120 reg_names
[from
], reg_names
[to
], ret
);
2126 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2129 frv_setup_incoming_varargs (cumulative_args_t cum_v
,
2131 tree type ATTRIBUTE_UNUSED
,
2135 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2137 if (TARGET_DEBUG_ARG
)
2139 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2140 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2144 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2147 frv_expand_builtin_saveregs (void)
2149 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2151 if (TARGET_DEBUG_ARG
)
2152 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2155 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2159 /* Expand __builtin_va_start to do the va_start macro. */
2162 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2165 int num
= crtl
->args
.info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2167 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2168 GEN_INT (UNITS_PER_WORD
* num
));
2170 if (TARGET_DEBUG_ARG
)
2172 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2173 crtl
->args
.info
, num
);
2175 debug_rtx (nextarg
);
2178 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2179 fold_convert (TREE_TYPE (valist
),
2180 make_tree (sizetype
, nextarg
)));
2181 TREE_SIDE_EFFECTS (t
) = 1;
2183 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2187 /* Expand a block move operation, and return 1 if successful. Return 0
2188 if we should let the compiler generate normal code.
2190 operands[0] is the destination
2191 operands[1] is the source
2192 operands[2] is the length
2193 operands[3] is the alignment */
2195 /* Maximum number of loads to do before doing the stores */
2196 #ifndef MAX_MOVE_REG
2197 #define MAX_MOVE_REG 4
2200 /* Maximum number of total loads to do. */
2201 #ifndef TOTAL_MOVE_REG
2202 #define TOTAL_MOVE_REG 8
2206 frv_expand_block_move (rtx operands
[])
2208 rtx orig_dest
= operands
[0];
2209 rtx orig_src
= operands
[1];
2210 rtx bytes_rtx
= operands
[2];
2211 rtx align_rtx
= operands
[3];
2212 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2225 rtx stores
[MAX_MOVE_REG
];
2229 /* If this is not a fixed size move, just call memcpy. */
2233 /* This should be a fixed size alignment. */
2234 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2236 align
= INTVAL (align_rtx
);
2238 /* Anything to move? */
2239 bytes
= INTVAL (bytes_rtx
);
2243 /* Don't support real large moves. */
2244 if (bytes
> TOTAL_MOVE_REG
*align
)
2247 /* Move the address into scratch registers. */
2248 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2249 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2251 num_reg
= offset
= 0;
2252 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2254 /* Calculate the correct offset for src/dest. */
2258 dest_addr
= dest_reg
;
2262 src_addr
= plus_constant (Pmode
, src_reg
, offset
);
2263 dest_addr
= plus_constant (Pmode
, dest_reg
, offset
);
2266 /* Generate the appropriate load and store, saving the stores
2268 if (bytes
>= 4 && align
>= 4)
2270 else if (bytes
>= 2 && align
>= 2)
2275 move_bytes
= GET_MODE_SIZE (mode
);
2276 tmp_reg
= gen_reg_rtx (mode
);
2277 src_mem
= change_address (orig_src
, mode
, src_addr
);
2278 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2279 emit_insn (gen_rtx_SET (tmp_reg
, src_mem
));
2280 stores
[num_reg
++] = gen_rtx_SET (dest_mem
, tmp_reg
);
2282 if (num_reg
>= MAX_MOVE_REG
)
2284 for (i
= 0; i
< num_reg
; i
++)
2285 emit_insn (stores
[i
]);
2290 for (i
= 0; i
< num_reg
; i
++)
2291 emit_insn (stores
[i
]);
2297 /* Expand a block clear operation, and return 1 if successful. Return 0
2298 if we should let the compiler generate normal code.
2300 operands[0] is the destination
2301 operands[1] is the length
2302 operands[3] is the alignment */
2305 frv_expand_block_clear (rtx operands
[])
2307 rtx orig_dest
= operands
[0];
2308 rtx bytes_rtx
= operands
[1];
2309 rtx align_rtx
= operands
[3];
2310 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2320 /* If this is not a fixed size move, just call memcpy. */
2324 /* This should be a fixed size alignment. */
2325 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2327 align
= INTVAL (align_rtx
);
2329 /* Anything to move? */
2330 bytes
= INTVAL (bytes_rtx
);
2334 /* Don't support real large clears. */
2335 if (bytes
> TOTAL_MOVE_REG
*align
)
2338 /* Move the address into a scratch register. */
2339 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2342 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2344 /* Calculate the correct offset for src/dest. */
2345 dest_addr
= ((offset
== 0)
2347 : plus_constant (Pmode
, dest_reg
, offset
));
2349 /* Generate the appropriate store of gr0. */
2350 if (bytes
>= 4 && align
>= 4)
2352 else if (bytes
>= 2 && align
>= 2)
2357 clear_bytes
= GET_MODE_SIZE (mode
);
2358 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2359 emit_insn (gen_rtx_SET (dest_mem
, const0_rtx
));
2366 /* The following variable is used to output modifiers of assembler
2367 code of the current output insn. */
2369 static rtx
*frv_insn_operands
;
2371 /* The following function is used to add assembler insn code suffix .p
2372 if it is necessary. */
2375 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2379 if (frv_insn_packing_flag
<= 0)
2382 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2385 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2386 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2388 int letter
= *ptr
++;
2391 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2392 while ((c
= *ptr
) >= '0' && c
<= '9')
2404 /* Set up the packing bit for the current output insn. Note that this
2405 function is not called for asm insns. */
2408 frv_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
,
2409 int noperands ATTRIBUTE_UNUSED
)
2413 if (frv_insn_packing_flag
>= 0)
2415 frv_insn_operands
= opvec
;
2416 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2418 else if (recog_memoized (insn
) >= 0
2419 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2420 /* Packing optimizations have been disabled, but INSN can only
2421 be issued in M1. Insert an mnop in M0. */
2422 fprintf (asm_out_file
, "\tmnop.p\n");
2428 /* A C expression whose value is RTL representing the address in a stack frame
2429 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2430 an RTL expression for the address of the stack frame itself.
2432 If you don't define this macro, the default is to return the value of
2433 FRAMEADDR--that is, the stack frame address is also the address of the stack
2434 word that points to the previous frame. */
2436 /* The default is correct, but we need to make sure the frame gets created. */
2438 frv_dynamic_chain_address (rtx frame
)
2440 cfun
->machine
->frame_needed
= 1;
2445 /* A C expression whose value is RTL representing the value of the return
2446 address for the frame COUNT steps up from the current frame, after the
2447 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2448 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2451 The value of the expression must always be the correct address when COUNT is
2452 zero, but may be `NULL_RTX' if there is not way to determine the return
2453 address of other frames. */
2456 frv_return_addr_rtx (int count
, rtx frame
)
2460 cfun
->machine
->frame_needed
= 1;
2461 return gen_rtx_MEM (Pmode
, plus_constant (Pmode
, frame
, 8));
2464 /* Given a memory reference MEMREF, interpret the referenced memory as
2465 an array of MODE values, and return a reference to the element
2466 specified by INDEX. Assume that any pre-modification implicit in
2467 MEMREF has already happened.
2469 MEMREF must be a legitimate operand for modes larger than SImode.
2470 frv_legitimate_address_p forbids register+register addresses, which
2471 this function cannot handle. */
2473 frv_index_memory (rtx memref
, machine_mode mode
, int index
)
2475 rtx base
= XEXP (memref
, 0);
2476 if (GET_CODE (base
) == PRE_MODIFY
)
2477 base
= XEXP (base
, 0);
2478 return change_address (memref
, mode
,
2479 plus_constant (Pmode
, base
,
2480 index
* GET_MODE_SIZE (mode
)));
2484 /* Print a memory address as an operand to reference that memory location. */
2486 frv_print_operand_address (FILE * stream
, machine_mode
/* mode */, rtx x
)
2488 if (GET_CODE (x
) == MEM
)
2491 switch (GET_CODE (x
))
2494 fputs (reg_names
[ REGNO (x
)], stream
);
2498 fprintf (stream
, "%ld", (long) INTVAL (x
));
2502 assemble_name (stream
, XSTR (x
, 0));
2507 output_addr_const (stream
, x
);
2511 /* Poorly constructed asm statements can trigger this alternative.
2512 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2513 frv_print_operand_memory_reference (stream
, x
, 0);
2520 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2525 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2527 int regno
= true_regnum (x
);
2529 fputs (reg_names
[regno
], stream
);
2531 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2534 /* Print a memory reference suitable for the ld/st instructions. */
2537 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2539 struct frv_unspec unspec
;
2543 switch (GET_CODE (x
))
2550 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2552 x1
= XEXP (XEXP (x
, 1), 1);
2562 if (GET_CODE (x0
) == CONST_INT
)
2570 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2579 else if (GET_CODE (x1
) != CONST_INT
)
2580 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2583 fputs ("@(", stream
);
2585 fputs (reg_names
[GPR_R0
], stream
);
2586 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2587 frv_print_operand_memory_reference_reg (stream
, x0
);
2589 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2591 fputs (",", stream
);
2593 fputs (reg_names
[GPR_R0
], stream
);
2597 switch (GET_CODE (x1
))
2601 frv_print_operand_memory_reference_reg (stream
, x1
);
2605 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2609 if (!frv_const_unspec_p (x1
, &unspec
))
2610 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2611 frv_output_const_unspec (stream
, &unspec
);
2615 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2619 fputs (")", stream
);
2623 /* Return 2 for likely branches and 0 for non-likely branches */
2625 #define FRV_JUMP_LIKELY 2
2626 #define FRV_JUMP_NOT_LIKELY 0
2629 frv_print_operand_jump_hint (rtx_insn
*insn
)
2634 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2636 gcc_assert (JUMP_P (insn
));
2638 /* Assume any non-conditional jump is likely. */
2639 if (! any_condjump_p (insn
))
2640 ret
= FRV_JUMP_LIKELY
;
2644 labelref
= condjump_label (insn
);
2647 rtx label
= XEXP (labelref
, 0);
2648 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2653 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2655 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2659 ret
= ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
2660 >= profile_probability::even ())
2662 : FRV_JUMP_NOT_LIKELY
);
2674 case UNKNOWN
: direction
= "unknown jump direction"; break;
2675 case BACKWARD
: direction
= "jump backward"; break;
2676 case FORWARD
: direction
= "jump forward"; break;
2680 "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n",
2681 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2682 (long)INSN_UID (insn
), direction
, prob
,
2683 REG_BR_PROB_BASE
, ret
);
2691 /* Return the comparison operator to use for CODE given that the ICC
2695 comparison_string (enum rtx_code code
, rtx op0
)
2697 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2700 default: output_operand_lossage ("bad condition code"); return "";
2701 case EQ
: return "eq";
2702 case NE
: return "ne";
2703 case LT
: return is_nz_p
? "n" : "lt";
2704 case LE
: return "le";
2705 case GT
: return "gt";
2706 case GE
: return is_nz_p
? "p" : "ge";
2707 case LTU
: return is_nz_p
? "no" : "c";
2708 case LEU
: return is_nz_p
? "eq" : "ls";
2709 case GTU
: return is_nz_p
? "ne" : "hi";
2710 case GEU
: return is_nz_p
? "ra" : "nc";
2714 /* Print an operand to an assembler instruction.
2716 `%' followed by a letter and a digit says to output an operand in an
2717 alternate fashion. Four letters have standard, built-in meanings
2718 described below. The hook `TARGET_PRINT_OPERAND' can define
2719 additional letters with nonstandard meanings.
2721 `%cDIGIT' can be used to substitute an operand that is a constant value
2722 without the syntax that normally indicates an immediate operand.
2724 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2727 `%aDIGIT' can be used to substitute an operand as if it were a memory
2728 reference, with the actual operand treated as the address. This may be
2729 useful when outputting a "load address" instruction, because often the
2730 assembler syntax for such an instruction requires you to write the operand
2731 as if it were a memory reference.
2733 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2735 `%=' outputs a number which is unique to each instruction in the entire
2736 compilation. This is useful for making local labels to be referred to more
2737 than once in a single template that generates multiple assembler
2740 `%' followed by a punctuation character specifies a substitution that
2741 does not use an operand. Only one case is standard: `%%' outputs a
2742 `%' into the assembler code. Other nonstandard cases can be defined
2743 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2744 punctuation characters are valid with the
2745 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2748 frv_print_operand (FILE * file
, rtx x
, int code
)
2750 struct frv_unspec unspec
;
2751 HOST_WIDE_INT value
;
2754 if (code
!= 0 && !ISALPHA (code
))
2757 else if (GET_CODE (x
) == CONST_INT
)
2760 else if (GET_CODE (x
) == CONST_DOUBLE
)
2762 if (GET_MODE (x
) == SFmode
)
2766 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
2770 else if (GET_MODE (x
) == VOIDmode
)
2771 value
= CONST_DOUBLE_LOW (x
);
2774 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2785 fputs (reg_names
[GPR_R0
], file
);
2789 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2793 /* Output small data area base register (gr16). */
2794 fputs (reg_names
[SDA_BASE_REG
], file
);
2798 /* Output pic register (gr17). */
2799 fputs (reg_names
[PIC_REGNO
], file
);
2803 /* Output the temporary integer CCR register. */
2804 fputs (reg_names
[ICR_TEMP
], file
);
2808 /* Output the temporary integer CC register. */
2809 fputs (reg_names
[ICC_TEMP
], file
);
2812 /* case 'a': print an address. */
2815 /* Print appropriate test for integer branch false operation. */
2816 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2817 XEXP (x
, 0)), file
);
2821 /* Print appropriate test for integer branch true operation. */
2822 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2826 /* Print 1 for a NE and 0 for an EQ to give the final argument
2827 for a conditional instruction. */
2828 if (GET_CODE (x
) == NE
)
2831 else if (GET_CODE (x
) == EQ
)
2835 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2839 /* Print appropriate test for floating point branch false operation. */
2840 switch (GET_CODE (x
))
2843 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2845 case EQ
: fputs ("ne", file
); break;
2846 case NE
: fputs ("eq", file
); break;
2847 case LT
: fputs ("uge", file
); break;
2848 case LE
: fputs ("ug", file
); break;
2849 case GT
: fputs ("ule", file
); break;
2850 case GE
: fputs ("ul", file
); break;
2855 /* Print appropriate test for floating point branch true operation. */
2856 switch (GET_CODE (x
))
2859 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2861 case EQ
: fputs ("eq", file
); break;
2862 case NE
: fputs ("ne", file
); break;
2863 case LT
: fputs ("lt", file
); break;
2864 case LE
: fputs ("le", file
); break;
2865 case GT
: fputs ("gt", file
); break;
2866 case GE
: fputs ("ge", file
); break;
2871 /* Print appropriate GOT function. */
2872 if (GET_CODE (x
) != CONST_INT
)
2873 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2874 fputs (unspec_got_name (INTVAL (x
)), file
);
2878 /* Print 'i' if the operand is a constant, or is a memory reference that
2880 if (GET_CODE (x
) == MEM
)
2881 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2882 ? XEXP (XEXP (x
, 0), 1)
2884 else if (GET_CODE (x
) == PLUS
)
2887 switch (GET_CODE (x
))
2901 /* For jump instructions, print 'i' if the operand is a constant or
2902 is an expression that adds a constant. */
2903 if (GET_CODE (x
) == CONST_INT
)
2908 if (GET_CODE (x
) == CONST_INT
2909 || (GET_CODE (x
) == PLUS
2910 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2911 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2917 /* Print the lower register of a double word register pair */
2918 if (GET_CODE (x
) == REG
)
2919 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2921 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2924 /* case 'l': print a LABEL_REF. */
2928 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2929 for the second word of double memory operations. */
2930 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2931 switch (GET_CODE (x
))
2934 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2937 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2945 frv_print_operand_memory_reference (file
, x
, offset
);
2951 /* Print the opcode of a command. */
2952 switch (GET_CODE (x
))
2955 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2957 case PLUS
: fputs ("add", file
); break;
2958 case MINUS
: fputs ("sub", file
); break;
2959 case AND
: fputs ("and", file
); break;
2960 case IOR
: fputs ("or", file
); break;
2961 case XOR
: fputs ("xor", file
); break;
2962 case ASHIFT
: fputs ("sll", file
); break;
2963 case ASHIFTRT
: fputs ("sra", file
); break;
2964 case LSHIFTRT
: fputs ("srl", file
); break;
2968 /* case 'n': negate and print a constant int. */
2971 /* Print PIC label using operand as the number. */
2972 if (GET_CODE (x
) != CONST_INT
)
2973 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
2975 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2979 /* Print 'u' if the operand is a update load/store. */
2980 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2985 /* If value is 0, print gr0, otherwise it must be a register. */
2986 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
2987 fputs (reg_names
[GPR_R0
], file
);
2989 else if (GET_CODE (x
) == REG
)
2990 fputs (reg_names
[REGNO (x
)], file
);
2993 fatal_insn ("bad insn in frv_print_operand, z case", x
);
2997 /* Print constant in hex. */
2998 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3000 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3007 if (GET_CODE (x
) == REG
)
3008 fputs (reg_names
[REGNO (x
)], file
);
3010 else if (GET_CODE (x
) == CONST_INT
3011 || GET_CODE (x
) == CONST_DOUBLE
)
3012 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3014 else if (frv_const_unspec_p (x
, &unspec
))
3015 frv_output_const_unspec (file
, &unspec
);
3017 else if (GET_CODE (x
) == MEM
)
3018 frv_print_operand_address (file
, GET_MODE (x
), XEXP (x
, 0));
3020 else if (CONSTANT_ADDRESS_P (x
))
3021 frv_print_operand_address (file
, VOIDmode
, x
);
3024 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3029 fatal_insn ("frv_print_operand: unknown code", x
);
3037 frv_print_operand_punct_valid_p (unsigned char code
)
3039 return (code
== '.' || code
== '#' || code
== '@' || code
== '~'
3040 || code
== '*' || code
== '&');
3044 /* A C statement (sans semicolon) for initializing the variable CUM for the
3045 state at the beginning of the argument list. The variable has type
3046 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3047 of the function which will receive the args, or 0 if the args are to a
3048 compiler support library function. The value of INDIRECT is nonzero when
3049 processing an indirect call, for example a call through a function pointer.
3050 The value of INDIRECT is zero for a call to an explicitly named function, a
3051 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3052 arguments for the function being compiled.
3054 When processing a call to a compiler support library function, LIBNAME
3055 identifies which one. It is a `symbol_ref' rtx which contains the name of
3056 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3057 being processed. Thus, each time this macro is called, either LIBNAME or
3058 FNTYPE is nonzero, but never both of them at once. */
3061 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3067 *cum
= FIRST_ARG_REGNUM
;
3069 if (TARGET_DEBUG_ARG
)
3071 fprintf (stderr
, "\ninit_cumulative_args:");
3072 if (!fndecl
&& fntype
)
3073 fputs (" indirect", stderr
);
3076 fputs (" incoming", stderr
);
3080 tree ret_type
= TREE_TYPE (fntype
);
3081 fprintf (stderr
, " return=%s,",
3082 get_tree_code_name (TREE_CODE (ret_type
)));
3085 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3086 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3088 if (cfun
->returns_struct
)
3089 fprintf (stderr
, " return-struct");
3091 putc ('\n', stderr
);
3096 /* Return true if we should pass an argument on the stack rather than
3100 frv_must_pass_in_stack (machine_mode mode
, const_tree type
)
3102 if (mode
== BLKmode
)
3106 return AGGREGATE_TYPE_P (type
);
3109 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3110 argument with the specified mode and type. If it is not defined,
3111 `PARM_BOUNDARY' is used for all arguments. */
3114 frv_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
3115 const_tree type ATTRIBUTE_UNUSED
)
3117 return BITS_PER_WORD
;
3121 frv_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
3122 const_tree type ATTRIBUTE_UNUSED
, bool named
,
3123 bool incoming ATTRIBUTE_UNUSED
)
3125 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3127 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3132 /* Return a marker for use in the call instruction. */
3133 if (xmode
== VOIDmode
)
3139 else if (arg_num
<= LAST_ARG_REGNUM
)
3141 ret
= gen_rtx_REG (xmode
, arg_num
);
3142 debstr
= reg_names
[arg_num
];
3151 if (TARGET_DEBUG_ARG
)
3153 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3154 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3160 frv_function_arg (cumulative_args_t cum
, machine_mode mode
,
3161 const_tree type
, bool named
)
3163 return frv_function_arg_1 (cum
, mode
, type
, named
, false);
3167 frv_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
3168 const_tree type
, bool named
)
3170 return frv_function_arg_1 (cum
, mode
, type
, named
, true);
3174 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3175 advance past an argument in the argument list. The values MODE, TYPE and
3176 NAMED describe that argument. Once this is done, the variable CUM is
3177 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3179 This macro need not do anything if the argument in question was passed on
3180 the stack. The compiler knows how to track the amount of stack space used
3181 for arguments without any special help. */
3184 frv_function_arg_advance (cumulative_args_t cum_v
,
3186 const_tree type ATTRIBUTE_UNUSED
,
3189 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3191 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3192 int bytes
= GET_MODE_SIZE (xmode
);
3193 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3196 *cum
= arg_num
+ words
;
3198 if (TARGET_DEBUG_ARG
)
3200 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3201 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3205 /* A C expression for the number of words, at the beginning of an argument,
3206 must be put in registers. The value must be zero for arguments that are
3207 passed entirely in registers or that are entirely pushed on the stack.
3209 On some machines, certain arguments must be passed partially in registers
3210 and partially in memory. On these machines, typically the first N words of
3211 arguments are passed in registers, and the rest on the stack. If a
3212 multi-word argument (a `double' or a structure) crosses that boundary, its
3213 first few words must be passed in registers and the rest must be pushed.
3214 This macro tells the compiler when this occurs, and how many of the words
3215 should go in registers.
3217 `FUNCTION_ARG' for these arguments should return the first register to be
3218 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3219 the called function. */
3222 frv_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
3223 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3226 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3227 int bytes
= GET_MODE_SIZE (xmode
);
3228 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3229 int arg_num
= *get_cumulative_args (cum
);
3232 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3233 ? LAST_ARG_REGNUM
- arg_num
+ 1
3235 ret
*= UNITS_PER_WORD
;
3237 if (TARGET_DEBUG_ARG
&& ret
)
3238 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3244 /* Implements TARGET_FUNCTION_VALUE. */
3247 frv_function_value (const_tree valtype
,
3248 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
3249 bool outgoing ATTRIBUTE_UNUSED
)
3251 return gen_rtx_REG (TYPE_MODE (valtype
), RETURN_VALUE_REGNUM
);
3255 /* Implements TARGET_LIBCALL_VALUE. */
3258 frv_libcall_value (machine_mode mode
,
3259 const_rtx fun ATTRIBUTE_UNUSED
)
3261 return gen_rtx_REG (mode
, RETURN_VALUE_REGNUM
);
3265 /* Implements FUNCTION_VALUE_REGNO_P. */
3268 frv_function_value_regno_p (const unsigned int regno
)
3270 return (regno
== RETURN_VALUE_REGNUM
);
3273 /* Return true if a register is ok to use as a base or index register. */
3275 static FRV_INLINE
int
3276 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3282 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3284 if (regno
== ARG_POINTER_REGNUM
)
3287 return (regno
>= FIRST_PSEUDO_REGISTER
);
3291 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3292 RTX) is a legitimate memory address on the target machine for a memory
3293 operand of mode MODE.
3295 It usually pays to define several simpler macros to serve as subroutines for
3296 this one. Otherwise it may be too complicated to understand.
3298 This macro must exist in two variants: a strict variant and a non-strict
3299 one. The strict variant is used in the reload pass. It must be defined so
3300 that any pseudo-register that has not been allocated a hard register is
3301 considered a memory reference. In contexts where some kind of register is
3302 required, a pseudo-register with no hard register must be rejected.
3304 The non-strict variant is used in other passes. It must be defined to
3305 accept all pseudo-registers in every context where some kind of register is
3308 Compiler source files that want to use the strict variant of this macro
3309 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3310 conditional to define the strict variant in that case and the non-strict
3313 Normally, constant addresses which are the sum of a `symbol_ref' and an
3314 integer are stored inside a `const' RTX to mark them as constant.
3315 Therefore, there is no need to recognize such sums specifically as
3316 legitimate addresses. Normally you would simply recognize any `const' as
3319 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3320 constant sums that are not marked with `const'. It assumes that a
3321 naked `plus' indicates indexing. If so, then you *must* reject such
3322 naked constant sums as illegitimate addresses, so that none of them
3323 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3326 frv_legitimate_address_p_1 (machine_mode mode
,
3330 int allow_double_reg_p
)
3334 HOST_WIDE_INT value
;
3337 if (FRV_SYMBOL_REF_TLS_P (x
))
3340 switch (GET_CODE (x
))
3347 if (GET_CODE (x
) != REG
)
3353 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3359 if (GET_CODE (x0
) != REG
3360 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3361 || GET_CODE (x1
) != PLUS
3362 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3363 || GET_CODE (XEXP (x1
, 1)) != REG
3364 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3371 /* 12-bit immediate */
3376 ret
= IN_RANGE (INTVAL (x
), -2048, 2047);
3378 /* If we can't use load/store double operations, make sure we can
3379 address the second word. */
3380 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3381 ret
= IN_RANGE (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3390 if (GET_CODE (x0
) == SUBREG
)
3391 x0
= SUBREG_REG (x0
);
3393 if (GET_CODE (x0
) != REG
)
3396 regno0
= REGNO (x0
);
3397 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3400 switch (GET_CODE (x1
))
3406 x1
= SUBREG_REG (x1
);
3407 if (GET_CODE (x1
) != REG
)
3413 /* Do not allow reg+reg addressing for modes > 1 word if we
3414 can't depend on having move double instructions. */
3415 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3418 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3422 /* 12-bit immediate */
3427 value
= INTVAL (x1
);
3428 ret
= IN_RANGE (value
, -2048, 2047);
3430 /* If we can't use load/store double operations, make sure we can
3431 address the second word. */
3432 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3433 ret
= IN_RANGE (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3438 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3446 if (TARGET_DEBUG_ADDR
)
3448 fprintf (stderr
, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3449 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3450 (condexec_p
) ? ", inside conditional code" : "");
3458 frv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
3460 return frv_legitimate_address_p_1 (mode
, x
, strict_p
, FALSE
, FALSE
);
3463 /* Given an ADDR, generate code to inline the PLT. */
3465 gen_inlined_tls_plt (rtx addr
)
3468 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3471 dest
= gen_reg_rtx (DImode
);
3478 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3479 calll #gettlsoff(ADDR)@(gr8, gr0)
3481 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3488 sethi.p #gottlsdeschi(ADDR), gr8
3489 setlo #gottlsdesclo(ADDR), gr8
3490 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3491 calll #gettlsoff(ADDR)@(gr8, gr0)
3493 rtx reguse
= gen_reg_rtx (Pmode
);
3494 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3495 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3498 retval
= gen_reg_rtx (Pmode
);
3499 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3503 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3504 the destination address. */
3506 gen_tlsmoff (rtx addr
, rtx reg
)
3508 rtx dest
= gen_reg_rtx (Pmode
);
3512 /* sethi.p #tlsmoffhi(x), grA
3513 setlo #tlsmofflo(x), grA
3515 dest
= gen_reg_rtx (Pmode
);
3516 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3517 GEN_INT (R_FRV_TLSMOFFHI
)));
3518 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3522 /* addi grB, #tlsmoff12(x), grC
3524 ld/st @(grB, #tlsmoff12(x)), grC
3526 dest
= gen_reg_rtx (Pmode
);
3527 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3528 GEN_INT (R_FRV_TLSMOFF12
)));
3533 /* Generate code for a TLS address. */
3535 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3537 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3538 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3542 case TLS_MODEL_INITIAL_EXEC
:
3546 ldi @(gr15, #gottlsoff12(x)), gr5
3548 dest
= gen_reg_rtx (Pmode
);
3549 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3550 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3554 /* -fPIC or anything else.
3556 sethi.p #gottlsoffhi(x), gr14
3557 setlo #gottlsofflo(x), gr14
3558 ld #tlsoff(x)@(gr15, gr14), gr9
3560 rtx tmp
= gen_reg_rtx (Pmode
);
3561 dest
= gen_reg_rtx (Pmode
);
3562 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3563 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3565 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3566 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3569 case TLS_MODEL_LOCAL_DYNAMIC
:
3573 if (TARGET_INLINE_PLT
)
3574 retval
= gen_inlined_tls_plt (GEN_INT (0));
3577 /* call #gettlsoff(0) */
3578 retval
= gen_reg_rtx (Pmode
);
3579 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3582 reg
= gen_reg_rtx (Pmode
);
3583 emit_insn (gen_rtx_SET (reg
, gen_rtx_PLUS (Pmode
, retval
, tp
)));
3585 dest
= gen_tlsmoff (addr
, reg
);
3588 dest = gen_reg_rtx (Pmode);
3589 emit_insn (gen_tlsoff_hilo (dest, addr,
3590 GEN_INT (R_FRV_TLSMOFFHI)));
3591 dest = gen_rtx_PLUS (Pmode, dest, reg);
3595 case TLS_MODEL_LOCAL_EXEC
:
3596 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3598 case TLS_MODEL_GLOBAL_DYNAMIC
:
3602 if (TARGET_INLINE_PLT
)
3603 retval
= gen_inlined_tls_plt (addr
);
3606 /* call #gettlsoff(x) */
3607 retval
= gen_reg_rtx (Pmode
);
3608 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3610 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3621 frv_legitimize_address (rtx x
,
3622 rtx oldx ATTRIBUTE_UNUSED
,
3623 machine_mode mode ATTRIBUTE_UNUSED
)
3625 if (GET_CODE (x
) == SYMBOL_REF
)
3627 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3629 return frv_legitimize_tls_address (x
, model
);
3635 /* Test whether a local function descriptor is canonical, i.e.,
3636 whether we can use FUNCDESC_GOTOFF to compute the address of the
3640 frv_local_funcdesc_p (rtx fnx
)
3643 enum symbol_visibility vis
;
3646 if (! SYMBOL_REF_LOCAL_P (fnx
))
3649 fn
= SYMBOL_REF_DECL (fnx
);
3654 vis
= DECL_VISIBILITY (fn
);
3656 if (vis
== VISIBILITY_PROTECTED
)
3657 /* Private function descriptors for protected functions are not
3658 canonical. Temporarily change the visibility to global. */
3659 vis
= VISIBILITY_DEFAULT
;
3660 else if (flag_shlib
)
3661 /* If we're already compiling for a shared library (that, unlike
3662 executables, can't assume that the existence of a definition
3663 implies local binding), we can skip the re-testing. */
3666 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3668 DECL_VISIBILITY (fn
) = vis
;
3673 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3677 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3679 tree gp
= get_identifier ("_gp");
3680 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3682 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3686 unspec_got_name (int i
)
3690 case R_FRV_GOT12
: return "got12";
3691 case R_FRV_GOTHI
: return "gothi";
3692 case R_FRV_GOTLO
: return "gotlo";
3693 case R_FRV_FUNCDESC
: return "funcdesc";
3694 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3695 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3696 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3697 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3698 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3699 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3700 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3701 case R_FRV_GOTOFF12
: return "gotoff12";
3702 case R_FRV_GOTOFFHI
: return "gotoffhi";
3703 case R_FRV_GOTOFFLO
: return "gotofflo";
3704 case R_FRV_GPREL12
: return "gprel12";
3705 case R_FRV_GPRELHI
: return "gprelhi";
3706 case R_FRV_GPRELLO
: return "gprello";
3707 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3708 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3709 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3710 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3711 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3712 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3713 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3714 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3715 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3716 default: gcc_unreachable ();
3720 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3721 is added inside the relocation operator. */
3724 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3726 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3727 output_addr_const (stream
, plus_constant (Pmode
, unspec
->symbol
,
3729 fputs (")", stream
);
3732 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3733 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3734 otherwise return ORIG_X. */
3737 frv_find_base_term (rtx x
)
3739 struct frv_unspec unspec
;
3741 if (frv_const_unspec_p (x
, &unspec
)
3742 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3743 return plus_constant (Pmode
, unspec
.symbol
, unspec
.offset
);
3748 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3749 the operand is used by a predicated instruction. */
3752 frv_legitimate_memory_operand (rtx op
, machine_mode mode
, int condexec_p
)
3754 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3755 && GET_CODE (op
) == MEM
3756 && frv_legitimate_address_p_1 (mode
, XEXP (op
, 0),
3757 reload_completed
, condexec_p
, FALSE
));
3761 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3763 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3764 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3770 rvrtx
= operands
[0];
3774 addr
= XEXP (operands
[0], 0);
3776 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3777 any calls that would involve a PLT, but can't tell, since we
3778 don't know whether an extern function is going to be provided by
3779 a separate translation unit or imported from a separate module.
3780 When compiling for shared libraries, if the function has default
3781 visibility, we assume it's overridable, so we inline the PLT, but
3782 for executables, we don't really have a way to make a good
3783 decision: a function is as likely to be imported from a shared
3784 library as it is to be defined in the executable itself. We
3785 assume executables will get global functions defined locally,
3786 whereas shared libraries will have them potentially overridden,
3787 so we only inline PLTs when compiling for shared libraries.
3789 In order to mark a function as local to a shared library, any
3790 non-default visibility attribute suffices. Unfortunately,
3791 there's no simple way to tag a function declaration as ``in a
3792 different module'', which we could then use to trigger PLT
3793 inlining on executables. There's -minline-plt, but it affects
3794 all external functions, so one would have to also mark function
3795 declarations available in the same module with non-default
3796 visibility, which is advantageous in itself. */
3797 if (GET_CODE (addr
) == SYMBOL_REF
3798 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3802 dest
= gen_reg_rtx (SImode
);
3804 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3805 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3807 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3808 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3810 crtl
->uses_pic_offset_table
= TRUE
;
3813 else if (GET_CODE (addr
) == SYMBOL_REF
)
3815 /* These are always either local, or handled through a local
3818 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3819 operands
[2], picreg
, lr
);
3821 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3825 else if (! ldd_address_operand (addr
, Pmode
))
3826 addr
= force_reg (Pmode
, addr
);
3828 picreg
= gen_reg_rtx (DImode
);
3829 emit_insn (gen_movdi_ldd (picreg
, addr
));
3831 if (sibcall
&& ret_value
)
3832 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3834 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3836 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3838 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3842 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3843 process these separately from any offsets, such that we add any
3844 offsets to the function descriptor (the actual pointer), not to the
3845 function address. */
3848 frv_function_symbol_referenced_p (rtx x
)
3854 if (GET_CODE (x
) == SYMBOL_REF
)
3855 return SYMBOL_REF_FUNCTION_P (x
);
3857 length
= GET_RTX_LENGTH (GET_CODE (x
));
3858 format
= GET_RTX_FORMAT (GET_CODE (x
));
3860 for (j
= 0; j
< length
; ++j
)
3865 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3871 if (XVEC (x
, j
) != 0)
3874 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3875 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3881 /* Nothing to do. */
3889 /* Return true if the memory operand is one that can be conditionally
3893 condexec_memory_operand (rtx op
, machine_mode mode
)
3895 machine_mode op_mode
= GET_MODE (op
);
3898 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3913 if (GET_CODE (op
) != MEM
)
3916 addr
= XEXP (op
, 0);
3917 return frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3920 /* Return true if the bare return instruction can be used outside of the
3921 epilog code. For frv, we only do it if there was no stack allocation. */
3924 direct_return_p (void)
3928 if (!reload_completed
)
3931 info
= frv_stack_info ();
3932 return (info
->total_size
== 0);
3937 frv_emit_move (machine_mode mode
, rtx dest
, rtx src
)
3939 if (GET_CODE (src
) == SYMBOL_REF
)
3941 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3943 src
= frv_legitimize_tls_address (src
, model
);
3949 if (frv_emit_movsi (dest
, src
))
3958 if (!reload_in_progress
3959 && !reload_completed
3960 && !register_operand (dest
, mode
)
3961 && !reg_or_0_operand (src
, mode
))
3962 src
= copy_to_mode_reg (mode
, src
);
3969 emit_insn (gen_rtx_SET (dest
, src
));
3972 /* Emit code to handle a MOVSI, adding in the small data register or pic
3973 register if needed to load up addresses. Return TRUE if the appropriate
3974 instructions are emitted. */
3977 frv_emit_movsi (rtx dest
, rtx src
)
3979 int base_regno
= -1;
3982 struct frv_unspec old_unspec
;
3984 if (!reload_in_progress
3985 && !reload_completed
3986 && !register_operand (dest
, SImode
)
3987 && (!reg_or_0_operand (src
, SImode
)
3988 /* Virtual registers will almost always be replaced by an
3989 add instruction, so expose this to CSE by copying to
3990 an intermediate register. */
3991 || (GET_CODE (src
) == REG
3992 && IN_RANGE (REGNO (src
),
3993 FIRST_VIRTUAL_REGISTER
,
3994 LAST_VIRTUAL_POINTER_REGISTER
))))
3996 emit_insn (gen_rtx_SET (dest
, copy_to_mode_reg (SImode
, src
)));
4000 /* Explicitly add in the PIC or small data register if needed. */
4001 switch (GET_CODE (src
))
4010 /* Using GPREL12, we use a single GOT entry for all symbols
4011 in read-only sections, but trade sequences such as:
4013 sethi #gothi(label), gr#
4014 setlo #gotlo(label), gr#
4019 ld @(gr15,#got12(_gp)), gr#
4020 sethi #gprelhi(label), gr##
4021 setlo #gprello(label), gr##
4024 We may often be able to share gr# for multiple
4025 computations of GPREL addresses, and we may often fold
4026 the final add into the pair of registers of a load or
4027 store instruction, so it's often profitable. Even when
4028 optimizing for size, we're trading a GOT entry for an
4029 additional instruction, which trades GOT space
4030 (read-write) for code size (read-only, shareable), as
4031 long as the symbol is not used in more than two different
4034 With -fpie/-fpic, we'd be trading a single load for a
4035 sequence of 4 instructions, because the offset of the
4036 label can't be assumed to be addressable with 12 bits, so
4037 we don't do this. */
4038 if (TARGET_GPREL_RO
)
4039 unspec
= R_FRV_GPREL12
;
4041 unspec
= R_FRV_GOT12
;
4044 base_regno
= PIC_REGNO
;
4049 if (frv_const_unspec_p (src
, &old_unspec
))
4052 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4055 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4056 emit_move_insn (dest
, src
);
4061 sym
= XEXP (sym
, 0);
4062 if (GET_CODE (sym
) == PLUS
4063 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4064 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4065 sym
= XEXP (sym
, 0);
4066 if (GET_CODE (sym
) == SYMBOL_REF
)
4068 else if (GET_CODE (sym
) == LABEL_REF
)
4071 goto handle_whatever
;
4079 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4083 src
= frv_legitimize_tls_address (src
, model
);
4084 emit_move_insn (dest
, src
);
4088 if (SYMBOL_REF_FUNCTION_P (sym
))
4090 if (frv_local_funcdesc_p (sym
))
4091 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4093 unspec
= R_FRV_FUNCDESC_GOT12
;
4097 if (CONSTANT_POOL_ADDRESS_P (sym
))
4098 switch (GET_CODE (get_pool_constant (sym
)))
4105 unspec
= R_FRV_GOTOFF12
;
4110 if (TARGET_GPREL_RO
)
4111 unspec
= R_FRV_GPREL12
;
4113 unspec
= R_FRV_GOT12
;
4116 else if (SYMBOL_REF_LOCAL_P (sym
)
4117 && !SYMBOL_REF_EXTERNAL_P (sym
)
4118 && SYMBOL_REF_DECL (sym
)
4119 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4120 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4122 tree decl
= SYMBOL_REF_DECL (sym
);
4123 tree init
= TREE_CODE (decl
) == VAR_DECL
4124 ? DECL_INITIAL (decl
)
4125 : TREE_CODE (decl
) == CONSTRUCTOR
4128 bool named_section
, readonly
;
4130 if (init
&& init
!= error_mark_node
)
4131 reloc
= compute_reloc_for_constant (init
);
4133 named_section
= TREE_CODE (decl
) == VAR_DECL
4134 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4135 readonly
= decl_readonly_section (decl
, reloc
);
4138 unspec
= R_FRV_GOT12
;
4140 unspec
= R_FRV_GOTOFF12
;
4141 else if (readonly
&& TARGET_GPREL_RO
)
4142 unspec
= R_FRV_GPREL12
;
4144 unspec
= R_FRV_GOT12
;
4147 unspec
= R_FRV_GOT12
;
4151 else if (SYMBOL_REF_SMALL_P (sym
))
4152 base_regno
= SDA_BASE_REG
;
4155 base_regno
= PIC_REGNO
;
4160 if (base_regno
>= 0)
4162 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4163 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4164 gen_rtx_REG (Pmode
, base_regno
),
4165 GEN_INT (R_FRV_GPREL12
)));
4167 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4168 gen_rtx_REG (Pmode
, base_regno
),
4169 GEN_INT (R_FRV_GPREL12
)));
4170 if (base_regno
== PIC_REGNO
)
4171 crtl
->uses_pic_offset_table
= TRUE
;
4179 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4180 new uses of it once reload has begun. */
4181 gcc_assert (!reload_in_progress
&& !reload_completed
);
4185 case R_FRV_GOTOFF12
:
4186 if (!frv_small_data_reloc_p (sym
, unspec
))
4187 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4190 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4193 if (!frv_small_data_reloc_p (sym
, unspec
))
4194 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4197 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4199 case R_FRV_FUNCDESC_GOTOFF12
:
4201 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4204 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4208 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4211 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4215 crtl
->uses_pic_offset_table
= TRUE
;
4224 /* Return a string to output a single word move. */
4227 output_move_single (rtx operands
[], rtx insn
)
4229 rtx dest
= operands
[0];
4230 rtx src
= operands
[1];
4232 if (GET_CODE (dest
) == REG
)
4234 int dest_regno
= REGNO (dest
);
4235 machine_mode mode
= GET_MODE (dest
);
4237 if (GPR_P (dest_regno
))
4239 if (GET_CODE (src
) == REG
)
4241 /* gpr <- some sort of register */
4242 int src_regno
= REGNO (src
);
4244 if (GPR_P (src_regno
))
4245 return "mov %1, %0";
4247 else if (FPR_P (src_regno
))
4248 return "movfg %1, %0";
4250 else if (SPR_P (src_regno
))
4251 return "movsg %1, %0";
4254 else if (GET_CODE (src
) == MEM
)
4263 return "ldsb%I1%U1 %M1,%0";
4266 return "ldsh%I1%U1 %M1,%0";
4270 return "ld%I1%U1 %M1, %0";
4274 else if (GET_CODE (src
) == CONST_INT
4275 || GET_CODE (src
) == CONST_DOUBLE
)
4277 /* gpr <- integer/floating constant */
4278 HOST_WIDE_INT value
;
4280 if (GET_CODE (src
) == CONST_INT
)
4281 value
= INTVAL (src
);
4283 else if (mode
== SFmode
)
4287 REAL_VALUE_TO_TARGET_SINGLE
4288 (*CONST_DOUBLE_REAL_VALUE (src
), l
);
4293 value
= CONST_DOUBLE_LOW (src
);
4295 if (IN_RANGE (value
, -32768, 32767))
4296 return "setlos %1, %0";
4301 else if (GET_CODE (src
) == SYMBOL_REF
4302 || GET_CODE (src
) == LABEL_REF
4303 || GET_CODE (src
) == CONST
)
4309 else if (FPR_P (dest_regno
))
4311 if (GET_CODE (src
) == REG
)
4313 /* fpr <- some sort of register */
4314 int src_regno
= REGNO (src
);
4316 if (GPR_P (src_regno
))
4317 return "movgf %1, %0";
4319 else if (FPR_P (src_regno
))
4321 if (TARGET_HARD_FLOAT
)
4322 return "fmovs %1, %0";
4324 return "mor %1, %1, %0";
4328 else if (GET_CODE (src
) == MEM
)
4337 return "ldbf%I1%U1 %M1,%0";
4340 return "ldhf%I1%U1 %M1,%0";
4344 return "ldf%I1%U1 %M1, %0";
4348 else if (ZERO_P (src
))
4349 return "movgf %., %0";
4352 else if (SPR_P (dest_regno
))
4354 if (GET_CODE (src
) == REG
)
4356 /* spr <- some sort of register */
4357 int src_regno
= REGNO (src
);
4359 if (GPR_P (src_regno
))
4360 return "movgs %1, %0";
4362 else if (ZERO_P (src
))
4363 return "movgs %., %0";
4367 else if (GET_CODE (dest
) == MEM
)
4369 if (GET_CODE (src
) == REG
)
4371 int src_regno
= REGNO (src
);
4372 machine_mode mode
= GET_MODE (dest
);
4374 if (GPR_P (src_regno
))
4382 return "stb%I0%U0 %1, %M0";
4385 return "sth%I0%U0 %1, %M0";
4389 return "st%I0%U0 %1, %M0";
4393 else if (FPR_P (src_regno
))
4401 return "stbf%I0%U0 %1, %M0";
4404 return "sthf%I0%U0 %1, %M0";
4408 return "stf%I0%U0 %1, %M0";
4413 else if (ZERO_P (src
))
4415 switch (GET_MODE (dest
))
4421 return "stb%I0%U0 %., %M0";
4424 return "sth%I0%U0 %., %M0";
4428 return "st%I0%U0 %., %M0";
4433 fatal_insn ("bad output_move_single operand", insn
);
4438 /* Return a string to output a double word move. */
4441 output_move_double (rtx operands
[], rtx insn
)
4443 rtx dest
= operands
[0];
4444 rtx src
= operands
[1];
4445 machine_mode mode
= GET_MODE (dest
);
4447 if (GET_CODE (dest
) == REG
)
4449 int dest_regno
= REGNO (dest
);
4451 if (GPR_P (dest_regno
))
4453 if (GET_CODE (src
) == REG
)
4455 /* gpr <- some sort of register */
4456 int src_regno
= REGNO (src
);
4458 if (GPR_P (src_regno
))
4461 else if (FPR_P (src_regno
))
4463 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4464 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4465 return "movfgd %1, %0";
4471 else if (GET_CODE (src
) == MEM
)
4474 if (dbl_memory_one_insn_operand (src
, mode
))
4475 return "ldd%I1%U1 %M1, %0";
4480 else if (GET_CODE (src
) == CONST_INT
4481 || GET_CODE (src
) == CONST_DOUBLE
)
4485 else if (FPR_P (dest_regno
))
4487 if (GET_CODE (src
) == REG
)
4489 /* fpr <- some sort of register */
4490 int src_regno
= REGNO (src
);
4492 if (GPR_P (src_regno
))
4494 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4495 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4496 return "movgfd %1, %0";
4501 else if (FPR_P (src_regno
))
4504 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4505 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4506 return "fmovd %1, %0";
4512 else if (GET_CODE (src
) == MEM
)
4515 if (dbl_memory_one_insn_operand (src
, mode
))
4516 return "lddf%I1%U1 %M1, %0";
4521 else if (ZERO_P (src
))
4526 else if (GET_CODE (dest
) == MEM
)
4528 if (GET_CODE (src
) == REG
)
4530 int src_regno
= REGNO (src
);
4532 if (GPR_P (src_regno
))
4534 if (((src_regno
- GPR_FIRST
) & 1) == 0
4535 && dbl_memory_one_insn_operand (dest
, mode
))
4536 return "std%I0%U0 %1, %M0";
4541 if (FPR_P (src_regno
))
4543 if (((src_regno
- FPR_FIRST
) & 1) == 0
4544 && dbl_memory_one_insn_operand (dest
, mode
))
4545 return "stdf%I0%U0 %1, %M0";
4551 else if (ZERO_P (src
))
4553 if (dbl_memory_one_insn_operand (dest
, mode
))
4554 return "std%I0%U0 %., %M0";
4560 fatal_insn ("bad output_move_double operand", insn
);
4565 /* Return a string to output a single word conditional move.
4566 Operand0 -- EQ/NE of ccr register and 0
4567 Operand1 -- CCR register
4568 Operand2 -- destination
4569 Operand3 -- source */
4572 output_condmove_single (rtx operands
[], rtx insn
)
4574 rtx dest
= operands
[2];
4575 rtx src
= operands
[3];
4577 if (GET_CODE (dest
) == REG
)
4579 int dest_regno
= REGNO (dest
);
4580 machine_mode mode
= GET_MODE (dest
);
4582 if (GPR_P (dest_regno
))
4584 if (GET_CODE (src
) == REG
)
4586 /* gpr <- some sort of register */
4587 int src_regno
= REGNO (src
);
4589 if (GPR_P (src_regno
))
4590 return "cmov %z3, %2, %1, %e0";
4592 else if (FPR_P (src_regno
))
4593 return "cmovfg %3, %2, %1, %e0";
4596 else if (GET_CODE (src
) == MEM
)
4605 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4608 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4612 return "cld%I3%U3 %M3, %2, %1, %e0";
4616 else if (ZERO_P (src
))
4617 return "cmov %., %2, %1, %e0";
4620 else if (FPR_P (dest_regno
))
4622 if (GET_CODE (src
) == REG
)
4624 /* fpr <- some sort of register */
4625 int src_regno
= REGNO (src
);
4627 if (GPR_P (src_regno
))
4628 return "cmovgf %3, %2, %1, %e0";
4630 else if (FPR_P (src_regno
))
4632 if (TARGET_HARD_FLOAT
)
4633 return "cfmovs %3,%2,%1,%e0";
4635 return "cmor %3, %3, %2, %1, %e0";
4639 else if (GET_CODE (src
) == MEM
)
4642 if (mode
== SImode
|| mode
== SFmode
)
4643 return "cldf%I3%U3 %M3, %2, %1, %e0";
4646 else if (ZERO_P (src
))
4647 return "cmovgf %., %2, %1, %e0";
4651 else if (GET_CODE (dest
) == MEM
)
4653 if (GET_CODE (src
) == REG
)
4655 int src_regno
= REGNO (src
);
4656 machine_mode mode
= GET_MODE (dest
);
4658 if (GPR_P (src_regno
))
4666 return "cstb%I2%U2 %3, %M2, %1, %e0";
4669 return "csth%I2%U2 %3, %M2, %1, %e0";
4673 return "cst%I2%U2 %3, %M2, %1, %e0";
4677 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4678 return "cstf%I2%U2 %3, %M2, %1, %e0";
4681 else if (ZERO_P (src
))
4683 machine_mode mode
= GET_MODE (dest
);
4690 return "cstb%I2%U2 %., %M2, %1, %e0";
4693 return "csth%I2%U2 %., %M2, %1, %e0";
4697 return "cst%I2%U2 %., %M2, %1, %e0";
4702 fatal_insn ("bad output_condmove_single operand", insn
);
4707 /* Emit the appropriate code to do a comparison, returning the register the
4708 comparison was done it. */
4711 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4713 machine_mode cc_mode
;
4716 /* Floating point doesn't have comparison against a constant. */
4717 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4718 op1
= force_reg (GET_MODE (op0
), op1
);
4720 /* Possibly disable using anything but a fixed register in order to work
4721 around cse moving comparisons past function calls. */
4722 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4723 cc_reg
= ((TARGET_ALLOC_CC
)
4724 ? gen_reg_rtx (cc_mode
)
4725 : gen_rtx_REG (cc_mode
,
4726 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4728 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4734 /* Emit code for a conditional branch.
4735 XXX: I originally wanted to add a clobber of a CCR register to use in
4736 conditional execution, but that confuses the rest of the compiler. */
4739 frv_emit_cond_branch (rtx operands
[])
4744 enum rtx_code test
= GET_CODE (operands
[0]);
4745 rtx cc_reg
= frv_emit_comparison (test
, operands
[1], operands
[2]);
4746 machine_mode cc_mode
= GET_MODE (cc_reg
);
4748 /* Branches generate:
4750 (if_then_else (<test>, <cc_reg>, (const_int 0))
4751 (label_ref <branch_label>)
4753 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
4754 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4755 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4756 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_else
));
4761 /* Emit code to set a gpr to 1/0 based on a comparison. */
4764 frv_emit_scc (rtx operands
[])
4770 enum rtx_code test
= GET_CODE (operands
[1]);
4771 rtx cc_reg
= frv_emit_comparison (test
, operands
[2], operands
[3]);
4773 /* SCC instructions generate:
4774 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4775 (clobber (<ccr_reg>))]) */
4776 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4777 set
= gen_rtx_SET (operands
[0], test_rtx
);
4779 cr_reg
= ((TARGET_ALLOC_CC
)
4780 ? gen_reg_rtx (CC_CCRmode
)
4781 : gen_rtx_REG (CC_CCRmode
,
4782 ((GET_MODE (cc_reg
) == CC_FPmode
)
4786 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4787 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4792 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4793 the separate insns. */
4796 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4802 /* Set the appropriate CCR bit. */
4803 emit_insn (gen_rtx_SET (cr_reg
,
4804 gen_rtx_fmt_ee (GET_CODE (test
),
4809 /* Move the value into the destination. */
4810 emit_move_insn (dest
, GEN_INT (value
));
4812 /* Move 0 into the destination if the test failed */
4813 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4814 gen_rtx_EQ (GET_MODE (cr_reg
),
4817 gen_rtx_SET (dest
, const0_rtx
)));
4819 /* Finish up, return sequence. */
4826 /* Emit the code for a conditional move, return TRUE if we could do the
4830 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4837 enum rtx_code test
= GET_CODE (test_rtx
);
4838 rtx cc_reg
= frv_emit_comparison (test
,
4839 XEXP (test_rtx
, 0), XEXP (test_rtx
, 1));
4840 machine_mode cc_mode
= GET_MODE (cc_reg
);
4842 /* Conditional move instructions generate:
4843 (parallel [(set <target>
4844 (if_then_else (<test> <cc_reg> (const_int 0))
4847 (clobber (<ccr_reg>))]) */
4849 /* Handle various cases of conditional move involving two constants. */
4850 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4852 HOST_WIDE_INT value1
= INTVAL (src1
);
4853 HOST_WIDE_INT value2
= INTVAL (src2
);
4855 /* Having 0 as one of the constants can be done by loading the other
4856 constant, and optionally moving in gr0. */
4857 if (value1
== 0 || value2
== 0)
4860 /* If the first value is within an addi range and also the difference
4861 between the two fits in an addi's range, load up the difference, then
4862 conditionally move in 0, and then unconditionally add the first
4864 else if (IN_RANGE (value1
, -2048, 2047)
4865 && IN_RANGE (value2
- value1
, -2048, 2047))
4868 /* If neither condition holds, just force the constant into a
4872 src1
= force_reg (GET_MODE (dest
), src1
);
4873 src2
= force_reg (GET_MODE (dest
), src2
);
4877 /* If one value is a register, insure the other value is either 0 or a
4881 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4882 src1
= force_reg (GET_MODE (dest
), src1
);
4884 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4885 src2
= force_reg (GET_MODE (dest
), src2
);
4888 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4889 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4891 set
= gen_rtx_SET (dest
, if_rtx
);
4893 cr_reg
= ((TARGET_ALLOC_CC
)
4894 ? gen_reg_rtx (CC_CCRmode
)
4895 : gen_rtx_REG (CC_CCRmode
,
4896 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4898 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4899 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4904 /* Split a conditional move into constituent parts, returning a SEQUENCE
4905 containing all of the insns. */
4908 frv_split_cond_move (rtx operands
[])
4910 rtx dest
= operands
[0];
4911 rtx test
= operands
[1];
4912 rtx cc_reg
= operands
[2];
4913 rtx src1
= operands
[3];
4914 rtx src2
= operands
[4];
4915 rtx cr_reg
= operands
[5];
4917 machine_mode cr_mode
= GET_MODE (cr_reg
);
4921 /* Set the appropriate CCR bit. */
4922 emit_insn (gen_rtx_SET (cr_reg
,
4923 gen_rtx_fmt_ee (GET_CODE (test
),
4928 /* Handle various cases of conditional move involving two constants. */
4929 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4931 HOST_WIDE_INT value1
= INTVAL (src1
);
4932 HOST_WIDE_INT value2
= INTVAL (src2
);
4934 /* Having 0 as one of the constants can be done by loading the other
4935 constant, and optionally moving in gr0. */
4938 emit_move_insn (dest
, src2
);
4939 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4940 gen_rtx_NE (cr_mode
, cr_reg
,
4942 gen_rtx_SET (dest
, src1
)));
4945 else if (value2
== 0)
4947 emit_move_insn (dest
, src1
);
4948 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4949 gen_rtx_EQ (cr_mode
, cr_reg
,
4951 gen_rtx_SET (dest
, src2
)));
4954 /* If the first value is within an addi range and also the difference
4955 between the two fits in an addi's range, load up the difference, then
4956 conditionally move in 0, and then unconditionally add the first
4958 else if (IN_RANGE (value1
, -2048, 2047)
4959 && IN_RANGE (value2
- value1
, -2048, 2047))
4961 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4963 : gen_rtx_SUBREG (SImode
, dest
, 0));
4965 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4966 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4967 gen_rtx_NE (cr_mode
, cr_reg
,
4969 gen_rtx_SET (dest_si
, const0_rtx
)));
4970 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
4978 /* Emit the conditional move for the test being true if needed. */
4979 if (! rtx_equal_p (dest
, src1
))
4980 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4981 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
4982 gen_rtx_SET (dest
, src1
)));
4984 /* Emit the conditional move for the test being false if needed. */
4985 if (! rtx_equal_p (dest
, src2
))
4986 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4987 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
4988 gen_rtx_SET (dest
, src2
)));
4991 /* Finish up, return sequence. */
4998 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
4999 memory location that is not known to be dword-aligned. */
5001 frv_split_double_load (rtx dest
, rtx source
)
5003 int regno
= REGNO (dest
);
5004 rtx dest1
= gen_highpart (SImode
, dest
);
5005 rtx dest2
= gen_lowpart (SImode
, dest
);
5006 rtx address
= XEXP (source
, 0);
5008 /* If the address is pre-modified, load the lower-numbered register
5009 first, then load the other register using an integer offset from
5010 the modified base register. This order should always be safe,
5011 since the pre-modification cannot affect the same registers as the
5014 The situation for other loads is more complicated. Loading one
5015 of the registers could affect the value of ADDRESS, so we must
5016 be careful which order we do them in. */
5017 if (GET_CODE (address
) == PRE_MODIFY
5018 || ! refers_to_regno_p (regno
, address
))
5020 /* It is safe to load the lower-numbered register first. */
5021 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5022 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5026 /* ADDRESS is not pre-modified and the address depends on the
5027 lower-numbered register. Load the higher-numbered register
5029 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5030 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5034 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5035 and SOURCE is either a double register or the constant zero. */
5037 frv_split_double_store (rtx dest
, rtx source
)
5039 rtx dest1
= change_address (dest
, SImode
, NULL
);
5040 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5041 if (ZERO_P (source
))
5043 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5044 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5048 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5049 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5054 /* Split a min/max operation returning a SEQUENCE containing all of the
5058 frv_split_minmax (rtx operands
[])
5060 rtx dest
= operands
[0];
5061 rtx minmax
= operands
[1];
5062 rtx src1
= operands
[2];
5063 rtx src2
= operands
[3];
5064 rtx cc_reg
= operands
[4];
5065 rtx cr_reg
= operands
[5];
5067 enum rtx_code test_code
;
5068 machine_mode cr_mode
= GET_MODE (cr_reg
);
5072 /* Figure out which test to use. */
5073 switch (GET_CODE (minmax
))
5078 case SMIN
: test_code
= LT
; break;
5079 case SMAX
: test_code
= GT
; break;
5080 case UMIN
: test_code
= LTU
; break;
5081 case UMAX
: test_code
= GTU
; break;
5084 /* Issue the compare instruction. */
5085 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (GET_MODE (cc_reg
),
5088 /* Set the appropriate CCR bit. */
5089 emit_insn (gen_rtx_SET (cr_reg
, gen_rtx_fmt_ee (test_code
,
5094 /* If are taking the min/max of a nonzero constant, load that first, and
5095 then do a conditional move of the other value. */
5096 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5098 gcc_assert (!rtx_equal_p (dest
, src1
));
5100 emit_move_insn (dest
, src2
);
5101 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5102 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5103 gen_rtx_SET (dest
, src1
)));
5106 /* Otherwise, do each half of the move. */
5109 /* Emit the conditional move for the test being true if needed. */
5110 if (! rtx_equal_p (dest
, src1
))
5111 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5112 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5113 gen_rtx_SET (dest
, src1
)));
5115 /* Emit the conditional move for the test being false if needed. */
5116 if (! rtx_equal_p (dest
, src2
))
5117 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5118 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5119 gen_rtx_SET (dest
, src2
)));
5122 /* Finish up, return sequence. */
5129 /* Split an integer abs operation returning a SEQUENCE containing all of the
5133 frv_split_abs (rtx operands
[])
5135 rtx dest
= operands
[0];
5136 rtx src
= operands
[1];
5137 rtx cc_reg
= operands
[2];
5138 rtx cr_reg
= operands
[3];
5143 /* Issue the compare < 0 instruction. */
5144 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5146 /* Set the appropriate CCR bit. */
5147 emit_insn (gen_rtx_SET (cr_reg
, gen_rtx_fmt_ee (LT
, CC_CCRmode
,
5148 cc_reg
, const0_rtx
)));
5150 /* Emit the conditional negate if the value is negative. */
5151 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5152 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5153 gen_negsi2 (dest
, src
)));
5155 /* Emit the conditional move for the test being false if needed. */
5156 if (! rtx_equal_p (dest
, src
))
5157 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5158 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5159 gen_rtx_SET (dest
, src
)));
5161 /* Finish up, return sequence. */
5168 /* Initialize machine-specific if-conversion data.
5169 On the FR-V, we don't have any extra fields per se, but it is useful hook to
5170 initialize the static storage. */
5172 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED
)
5174 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5175 frv_ifcvt
.cur_scratch_regs
= 0;
5176 frv_ifcvt
.num_nested_cond_exec
= 0;
5177 frv_ifcvt
.cr_reg
= NULL_RTX
;
5178 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5179 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5180 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5181 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5185 /* Internal function to add a potential insn to the list of insns to be inserted
5186 if the conditional execution conversion is successful. */
5189 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5191 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5193 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5194 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5195 frv_ifcvt
.added_insns_list
);
5197 if (TARGET_DEBUG_COND_EXEC
)
5200 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5201 (before_p
) ? "before" : "after",
5202 (int)INSN_UID (insn
));
5204 debug_rtx (pattern
);
5209 /* A C expression to modify the code described by the conditional if
5210 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5211 FALSE_EXPR for converting if-then and if-then-else code to conditional
5212 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5213 tests cannot be converted. */
5216 frv_ifcvt_modify_tests (ce_if_block
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5218 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5219 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5220 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5221 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5222 rtx true_expr
= *p_true
;
5226 machine_mode mode
= GET_MODE (true_expr
);
5230 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5232 rtx sub_cond_exec_reg
;
5234 enum rtx_code code_true
;
5235 enum rtx_code code_false
;
5236 enum reg_class cc_class
;
5237 enum reg_class cr_class
;
5240 reg_set_iterator rsi
;
5242 /* Make sure we are only dealing with hard registers. Also honor the
5243 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5245 if (!reload_completed
|| !TARGET_COND_EXEC
5246 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5249 /* Figure out which registers we can allocate for our own purposes. Only
5250 consider registers that are not preserved across function calls and are
5251 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5252 if we did not need to use them in reloading other registers. */
5253 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5254 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5255 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5256 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5257 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5259 /* If this is a nested IF, we need to discover whether the CC registers that
5260 are set/used inside of the block are used anywhere else. If not, we can
5261 change them to be the CC register that is paired with the CR register that
5262 controls the outermost IF block. */
5263 if (ce_info
->pass
> 1)
5265 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5266 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5267 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5269 if (REGNO_REG_SET_P (df_get_live_in (then_bb
), j
))
5273 && REGNO_REG_SET_P (df_get_live_in (else_bb
), j
))
5277 && REGNO_REG_SET_P (df_get_live_in (join_bb
), j
))
5280 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5284 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5285 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5287 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5288 frv_ifcvt
.cur_scratch_regs
= 0;
5290 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5291 * sizeof (basic_block
));
5297 /* Remove anything live at the beginning of the join block from being
5298 available for allocation. */
5299 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb
), 0, regno
, rsi
)
5301 if (regno
< FIRST_PSEUDO_REGISTER
)
5302 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5306 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5308 if (ce_info
->num_multiple_test_blocks
)
5310 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5312 while (multiple_test_bb
!= test_bb
)
5314 bb
[num_bb
++] = multiple_test_bb
;
5315 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5319 /* Add in the THEN and ELSE blocks to be scanned. */
5320 bb
[num_bb
++] = then_bb
;
5322 bb
[num_bb
++] = else_bb
;
5324 sub_cond_exec_reg
= NULL_RTX
;
5325 frv_ifcvt
.num_nested_cond_exec
= 0;
5327 /* Scan all of the blocks for registers that must not be allocated. */
5328 for (j
= 0; j
< num_bb
; j
++)
5330 rtx_insn
*last_insn
= BB_END (bb
[j
]);
5331 rtx_insn
*insn
= BB_HEAD (bb
[j
]);
5335 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5336 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5338 (int) INSN_UID (BB_HEAD (bb
[j
])),
5339 (int) INSN_UID (BB_END (bb
[j
])));
5341 /* Anything live at the beginning of the block is obviously unavailable
5343 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb
[j
]), 0, regno
, rsi
)
5345 if (regno
< FIRST_PSEUDO_REGISTER
)
5346 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5349 /* Loop through the insns in the block. */
5352 /* Mark any new registers that are created as being unavailable for
5353 allocation. Also see if the CC register used in nested IFs can be
5359 int skip_nested_if
= FALSE
;
5360 HARD_REG_SET mentioned_regs
;
5362 CLEAR_HARD_REG_SET (mentioned_regs
);
5363 find_all_hard_regs (PATTERN (insn
), &mentioned_regs
);
5364 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, mentioned_regs
);
5366 pattern
= PATTERN (insn
);
5367 if (GET_CODE (pattern
) == COND_EXEC
)
5369 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5371 if (reg
!= sub_cond_exec_reg
)
5373 sub_cond_exec_reg
= reg
;
5374 frv_ifcvt
.num_nested_cond_exec
++;
5378 set
= single_set_pattern (pattern
);
5381 rtx dest
= SET_DEST (set
);
5382 rtx src
= SET_SRC (set
);
5384 if (GET_CODE (dest
) == REG
)
5386 int regno
= REGNO (dest
);
5387 enum rtx_code src_code
= GET_CODE (src
);
5389 if (CC_P (regno
) && src_code
== COMPARE
)
5390 skip_nested_if
= TRUE
;
5392 else if (CR_P (regno
)
5393 && (src_code
== IF_THEN_ELSE
5394 || COMPARISON_P (src
)))
5395 skip_nested_if
= TRUE
;
5399 if (! skip_nested_if
)
5400 AND_COMPL_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
,
5404 if (insn
== last_insn
)
5407 insn
= NEXT_INSN (insn
);
5411 /* If this is a nested if, rewrite the CC registers that are available to
5412 include the ones that can be rewritten, to increase the chance of being
5413 able to allocate a paired CC/CR register combination. */
5414 if (ce_info
->pass
> 1)
5416 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5417 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5418 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5420 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5426 fprintf (dump_file
, "Available GPRs: ");
5428 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5429 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5431 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5432 if (++num_gprs
> GPR_TEMP_NUM
+2)
5436 fprintf (dump_file
, "%s\nAvailable CRs: ",
5437 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5439 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5440 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5441 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5443 fputs ("\n", dump_file
);
5445 if (ce_info
->pass
> 1)
5447 fprintf (dump_file
, "Modifiable CCs: ");
5448 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5449 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5450 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5452 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5453 frv_ifcvt
.num_nested_cond_exec
);
5457 /* Allocate the appropriate temporary condition code register. Try to
5458 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5459 that conditional cmp's can be done. */
5460 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5462 cr_class
= ICR_REGS
;
5463 cc_class
= ICC_REGS
;
5464 cc_first
= ICC_FIRST
;
5467 else if (mode
== CC_FPmode
)
5469 cr_class
= FCR_REGS
;
5470 cc_class
= FCC_REGS
;
5471 cc_first
= FCC_FIRST
;
5476 cc_first
= cc_last
= 0;
5477 cr_class
= cc_class
= NO_REGS
;
5480 cc
= XEXP (true_expr
, 0);
5481 nested_cc
= cr
= NULL_RTX
;
5482 if (cc_class
!= NO_REGS
)
5484 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5485 so we can execute a csubcc/caddcc/cfcmps instruction. */
5488 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5490 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5492 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5493 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5495 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5496 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5499 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5500 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5510 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5517 "Will use %s for conditional execution, %s for nested comparisons\n",
5518 reg_names
[ REGNO (cr
)],
5519 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5521 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5522 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5523 bit being true. We don't do this for floating point, because of NaNs. */
5524 code
= GET_CODE (true_expr
);
5525 if (GET_MODE (cc
) != CC_FPmode
)
5527 code
= reverse_condition (code
);
5537 check_insn
= gen_rtx_SET (cr
, gen_rtx_fmt_ee (code
, CC_CCRmode
,
5540 /* Record the check insn to be inserted later. */
5541 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5543 /* Update the tests. */
5544 frv_ifcvt
.cr_reg
= cr
;
5545 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5546 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5547 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5550 /* Fail, don't do this conditional execution. */
5553 *p_false
= NULL_RTX
;
5555 fprintf (dump_file
, "Disabling this conditional execution.\n");
5561 /* A C expression to modify the code described by the conditional if
5562 information CE_INFO, for the basic block BB, possibly updating the tests in
5563 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5564 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5565 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5567 /* p_true and p_false are given expressions of the form:
5569 (and (eq:CC_CCR (reg:CC_CCR)
5575 frv_ifcvt_modify_multiple_tests (ce_if_block
*ce_info
,
5580 rtx old_true
= XEXP (*p_true
, 0);
5581 rtx old_false
= XEXP (*p_false
, 0);
5582 rtx true_expr
= XEXP (*p_true
, 1);
5583 rtx false_expr
= XEXP (*p_false
, 1);
5586 rtx cr
= XEXP (old_true
, 0);
5588 rtx new_cr
= NULL_RTX
;
5589 rtx
*p_new_cr
= (rtx
*)0;
5593 enum reg_class cr_class
;
5594 machine_mode mode
= GET_MODE (true_expr
);
5595 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5597 if (TARGET_DEBUG_COND_EXEC
)
5600 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5601 ce_info
->and_and_p
? "&&" : "||");
5603 debug_rtx (*p_true
);
5605 fputs ("\nfalse insn:\n", stderr
);
5606 debug_rtx (*p_false
);
5609 if (!TARGET_MULTI_CE
)
5612 if (GET_CODE (cr
) != REG
)
5615 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5617 cr_class
= ICR_REGS
;
5618 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5620 else if (mode
== CC_FPmode
)
5622 cr_class
= FCR_REGS
;
5623 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5628 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5629 more &&/|| tests. */
5633 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5634 CC_CCRmode
, TRUE
, TRUE
);
5639 if (ce_info
->and_and_p
)
5641 old_test
= old_false
;
5642 test_expr
= true_expr
;
5643 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5644 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5645 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5649 old_test
= old_false
;
5650 test_expr
= false_expr
;
5651 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5652 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5653 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5656 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5657 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5659 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5661 /* Now add the conditional check insn. */
5662 cc
= XEXP (test_expr
, 0);
5663 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5664 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5666 check_insn
= gen_rtx_SET (new_cr
, if_else
);
5668 /* Add the new check insn to the list of check insns that need to be
5670 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5672 if (TARGET_DEBUG_COND_EXEC
)
5674 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5677 debug_rtx (*p_true
);
5679 fputs ("\nfalse insn:\n", stderr
);
5680 debug_rtx (*p_false
);
5686 *p_true
= *p_false
= NULL_RTX
;
5688 /* If we allocated a CR register, release it. */
5691 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5692 *p_new_cr
= NULL_RTX
;
5695 if (TARGET_DEBUG_COND_EXEC
)
5696 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5702 /* Return a register which will be loaded with a value if an IF block is
5703 converted to conditional execution. This is used to rewrite instructions
5704 that use constants to ones that just use registers. */
5707 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5709 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5713 /* We know gr0 == 0, so replace any errant uses. */
5714 if (value
== const0_rtx
)
5715 return gen_rtx_REG (SImode
, GPR_FIRST
);
5717 /* First search all registers currently loaded to see if we have an
5718 applicable constant. */
5719 if (CONSTANT_P (value
)
5720 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5722 for (i
= 0; i
< num_alloc
; i
++)
5724 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5725 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5729 /* Have we exhausted the number of registers available? */
5730 if (num_alloc
>= GPR_TEMP_NUM
)
5733 fprintf (dump_file
, "Too many temporary registers allocated\n");
5738 /* Allocate the new register. */
5739 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5743 fputs ("Could not find a scratch register\n", dump_file
);
5748 frv_ifcvt
.cur_scratch_regs
++;
5749 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (reg
, value
);
5753 if (GET_CODE (value
) == CONST_INT
)
5754 fprintf (dump_file
, "Register %s will hold %ld\n",
5755 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5757 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5758 fprintf (dump_file
, "Register %s will hold LR\n",
5759 reg_names
[ REGNO (reg
)]);
5762 fprintf (dump_file
, "Register %s will hold a saved value\n",
5763 reg_names
[ REGNO (reg
)]);
5770 /* Update a MEM used in conditional code that might contain an offset to put
5771 the offset into a scratch register, so that the conditional load/store
5772 operations can be used. This function returns the original pointer if the
5773 MEM is valid to use in conditional code, NULL if we can't load up the offset
5774 into a temporary register, or the new MEM if we were successful. */
5777 frv_ifcvt_rewrite_mem (rtx mem
, machine_mode mode
, rtx insn
)
5779 rtx addr
= XEXP (mem
, 0);
5781 if (!frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5783 if (GET_CODE (addr
) == PLUS
)
5785 rtx addr_op0
= XEXP (addr
, 0);
5786 rtx addr_op1
= XEXP (addr
, 1);
5788 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5790 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5794 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5801 else if (CONSTANT_P (addr
))
5802 addr
= frv_ifcvt_load_value (addr
, insn
);
5807 if (addr
== NULL_RTX
)
5810 else if (XEXP (mem
, 0) != addr
)
5811 return change_address (mem
, mode
, addr
);
5818 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5819 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5822 single_set_pattern (rtx pattern
)
5827 if (GET_CODE (pattern
) == COND_EXEC
)
5828 pattern
= COND_EXEC_CODE (pattern
);
5830 if (GET_CODE (pattern
) == SET
)
5833 else if (GET_CODE (pattern
) == PARALLEL
)
5835 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5837 rtx sub
= XVECEXP (pattern
, 0, i
);
5839 switch (GET_CODE (sub
))
5863 /* A C expression to modify the code described by the conditional if
5864 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5865 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5866 insn cannot be converted to be executed conditionally. */
5869 frv_ifcvt_modify_insn (ce_if_block
*ce_info
,
5873 rtx orig_ce_pattern
= pattern
;
5879 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5881 test
= COND_EXEC_TEST (pattern
);
5882 if (GET_CODE (test
) == AND
)
5884 rtx cr
= frv_ifcvt
.cr_reg
;
5887 op0
= XEXP (test
, 0);
5888 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5891 op1
= XEXP (test
, 1);
5892 test_reg
= XEXP (op1
, 0);
5893 if (GET_CODE (test_reg
) != REG
)
5896 /* Is this the first nested if block in this sequence? If so, generate
5897 an andcr or andncr. */
5898 if (! frv_ifcvt
.last_nested_if_cr
)
5902 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5903 if (GET_CODE (op0
) == NE
)
5904 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5906 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5908 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5911 /* If this isn't the first statement in the nested if sequence, see if we
5912 are dealing with the same register. */
5913 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5916 COND_EXEC_TEST (pattern
) = test
= op1
;
5919 /* If this isn't a nested if, reset state variables. */
5922 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5925 set
= single_set_pattern (pattern
);
5928 rtx dest
= SET_DEST (set
);
5929 rtx src
= SET_SRC (set
);
5930 machine_mode mode
= GET_MODE (dest
);
5932 /* Check for normal binary operators. */
5933 if (mode
== SImode
&& ARITHMETIC_P (src
))
5935 op0
= XEXP (src
, 0);
5936 op1
= XEXP (src
, 1);
5938 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5940 op1
= frv_ifcvt_load_value (op1
, insn
);
5942 COND_EXEC_CODE (pattern
)
5943 = gen_rtx_SET (dest
, gen_rtx_fmt_ee (GET_CODE (src
),
5951 /* For multiply by a constant, we need to handle the sign extending
5952 correctly. Add a USE of the value after the multiply to prevent flow
5953 from cratering because only one register out of the two were used. */
5954 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
5956 op0
= XEXP (src
, 0);
5957 op1
= XEXP (src
, 1);
5958 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
5960 op1
= frv_ifcvt_load_value (op1
, insn
);
5963 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
5964 COND_EXEC_CODE (pattern
)
5965 = gen_rtx_SET (dest
, gen_rtx_MULT (DImode
, op0
, op1
));
5971 frv_ifcvt_add_insn (gen_use (dest
), insn
, FALSE
);
5974 /* If we are just loading a constant created for a nested conditional
5975 execution statement, just load the constant without any conditional
5976 execution, since we know that the constant will not interfere with any
5978 else if (frv_ifcvt
.scratch_insns_bitmap
5979 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
5981 && REG_P (SET_DEST (set
))
5982 /* We must not unconditionally set a scratch reg chosen
5983 for a nested if-converted block if its incoming
5984 value from the TEST block (or the result of the THEN
5985 branch) could/should propagate to the JOIN block.
5986 It suffices to test whether the register is live at
5987 the JOIN point: if it's live there, we can infer
5988 that we set it in the former JOIN block of the
5989 nested if-converted block (otherwise it wouldn't
5990 have been available as a scratch register), and it
5991 is either propagated through or set in the other
5992 conditional block. It's probably not worth trying
5993 to catch the latter case, and it could actually
5994 limit scheduling of the combined block quite
5997 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->join_bb
),
5998 REGNO (SET_DEST (set
))))
5999 /* Similarly, we must not unconditionally set a reg
6000 used as scratch in the THEN branch if the same reg
6001 is live in the ELSE branch. */
6002 && (! ce_info
->else_bb
6003 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6004 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->else_bb
),
6005 REGNO (SET_DEST (set
))))))
6008 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6011 int changed_p
= FALSE
;
6013 /* Check for just loading up a constant */
6014 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6016 src
= frv_ifcvt_load_value (src
, insn
);
6023 /* See if we need to fix up stores */
6024 if (GET_CODE (dest
) == MEM
)
6026 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6031 else if (new_mem
!= dest
)
6038 /* See if we need to fix up loads */
6039 if (GET_CODE (src
) == MEM
)
6041 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6046 else if (new_mem
!= src
)
6053 /* If either src or destination changed, redo SET. */
6055 COND_EXEC_CODE (pattern
) = gen_rtx_SET (dest
, src
);
6058 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6059 rewriting the CC register to be the same as the paired CC/CR register
6061 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6063 int regno
= REGNO (XEXP (src
, 0));
6066 if (ce_info
->pass
> 1
6067 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6068 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6070 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6072 frv_ifcvt
.nested_cc_reg
,
6076 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6077 pattern
= gen_rtx_SET (dest
, if_else
);
6080 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6081 else if (ce_info
->pass
> 1
6082 && GET_CODE (dest
) == REG
6083 && CC_P (REGNO (dest
))
6084 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6085 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6087 && GET_CODE (src
) == COMPARE
)
6089 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6090 COND_EXEC_CODE (pattern
)
6091 = gen_rtx_SET (frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6095 if (TARGET_DEBUG_COND_EXEC
)
6097 rtx orig_pattern
= PATTERN (insn
);
6099 PATTERN (insn
) = pattern
;
6101 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6105 PATTERN (insn
) = orig_pattern
;
6111 if (TARGET_DEBUG_COND_EXEC
)
6113 rtx orig_pattern
= PATTERN (insn
);
6115 PATTERN (insn
) = orig_ce_pattern
;
6117 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6121 PATTERN (insn
) = orig_pattern
;
6128 /* A C expression to perform any final machine dependent modifications in
6129 converting code to conditional execution in the code described by the
6130 conditional if information CE_INFO. */
6133 frv_ifcvt_modify_final (ce_if_block
*ce_info ATTRIBUTE_UNUSED
)
6137 rtx p
= frv_ifcvt
.added_insns_list
;
6140 /* Loop inserting the check insns. The last check insn is the first test,
6141 and is the appropriate place to insert constants. */
6146 rtx check_and_insert_insns
= XEXP (p
, 0);
6149 check_insn
= XEXP (check_and_insert_insns
, 0);
6150 existing_insn
= XEXP (check_and_insert_insns
, 1);
6153 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6154 the existing insn, otherwise it is to be inserted AFTER. */
6155 if (check_and_insert_insns
->jump
)
6157 emit_insn_before (check_insn
, existing_insn
);
6158 check_and_insert_insns
->jump
= 0;
6161 emit_insn_after (check_insn
, existing_insn
);
6163 free_EXPR_LIST_node (check_and_insert_insns
);
6164 free_EXPR_LIST_node (old_p
);
6166 while (p
!= NULL_RTX
);
6168 /* Load up any constants needed into temp gprs */
6169 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6171 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6172 if (! frv_ifcvt
.scratch_insns_bitmap
)
6173 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6174 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6175 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6178 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6179 frv_ifcvt
.cur_scratch_regs
= 0;
6183 /* A C expression to cancel any machine dependent modifications in converting
6184 code to conditional execution in the code described by the conditional if
6185 information CE_INFO. */
6188 frv_ifcvt_modify_cancel (ce_if_block
*ce_info ATTRIBUTE_UNUSED
)
6191 rtx p
= frv_ifcvt
.added_insns_list
;
6193 /* Loop freeing up the EXPR_LIST's allocated. */
6194 while (p
!= NULL_RTX
)
6196 rtx check_and_jump
= XEXP (p
, 0);
6200 free_EXPR_LIST_node (check_and_jump
);
6201 free_EXPR_LIST_node (old_p
);
6204 /* Release any temporary gprs allocated. */
6205 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6206 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6208 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6209 frv_ifcvt
.cur_scratch_regs
= 0;
6213 /* A C expression for the size in bytes of the trampoline, as an integer.
6217 setlo #0, <static_chain>
6219 sethi #0, <static_chain>
6220 jmpl @(gr0,<jmp_reg>) */
6223 frv_trampoline_size (void)
6226 /* Allocate room for the function descriptor and the lddi
6229 return 5 /* instructions */ * 4 /* instruction size. */;
6233 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6234 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6235 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6236 should be passed to the function when it is called.
6241 setlo #0, <static_chain>
6243 sethi #0, <static_chain>
6244 jmpl @(gr0,<jmp_reg>) */
6247 frv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
6249 rtx addr
= XEXP (m_tramp
, 0);
6250 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6251 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6253 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6254 LCT_NORMAL
, VOIDmode
,
6256 GEN_INT (frv_trampoline_size ()), SImode
,
6262 /* Many machines have some registers that cannot be copied directly to or from
6263 memory or even from other types of registers. An example is the `MQ'
6264 register, which on most machines, can only be copied to or from general
6265 registers, but not memory. Some machines allow copying all registers to and
6266 from memory, but require a scratch register for stores to some memory
6267 locations (e.g., those with symbolic address on the RT, and those with
6268 certain symbolic address on the SPARC when compiling PIC). In some cases,
6269 both an intermediate and a scratch register are required.
6271 You should define these macros to indicate to the reload phase that it may
6272 need to allocate at least one register for a reload in addition to the
6273 register to contain the data. Specifically, if copying X to a register
6274 RCLASS in MODE requires an intermediate register, you should define
6275 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6276 whose registers can be used as intermediate registers or scratch registers.
6278 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6279 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6280 largest register class required. If the requirements for input and output
6281 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6282 instead of defining both macros identically.
6284 The values returned by these macros are often `GENERAL_REGS'. Return
6285 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6286 to or from a register of RCLASS in MODE without requiring a scratch register.
6287 Do not define this macro if it would always return `NO_REGS'.
6289 If a scratch register is required (either with or without an intermediate
6290 register), you should define patterns for `reload_inM' or `reload_outM', as
6291 required.. These patterns, which will normally be implemented with a
6292 `define_expand', should be similar to the `movM' patterns, except that
6293 operand 2 is the scratch register.
6295 Define constraints for the reload register and scratch register that contain
6296 a single register class. If the original reload register (whose class is
6297 RCLASS) can meet the constraint given in the pattern, the value returned by
6298 these macros is used for the class of the scratch register. Otherwise, two
6299 additional reload registers are required. Their classes are obtained from
6300 the constraints in the insn pattern.
6302 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6303 either be in a hard register or in memory. Use `true_regnum' to find out;
6304 it will return -1 if the pseudo is in memory and the hard register number if
6305 it is in a register.
6307 These macros should not be used in the case where a particular class of
6308 registers can only be copied to memory and not to another class of
6309 registers. In that case, secondary reload registers are not needed and
6310 would not be helpful. Instead, a stack location must be used to perform the
6311 copy and the `movM' pattern should use memory as an intermediate storage.
6312 This case often occurs between floating-point and general registers. */
6315 frv_secondary_reload_class (enum reg_class rclass
,
6316 machine_mode mode ATTRIBUTE_UNUSED
,
6327 /* Accumulators/Accumulator guard registers need to go through floating
6332 if (x
&& GET_CODE (x
) == REG
)
6334 int regno
= REGNO (x
);
6336 if (ACC_P (regno
) || ACCG_P (regno
))
6341 /* Nonzero constants should be loaded into an FPR through a GPR. */
6343 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6349 /* All of these types need gpr registers. */
6361 /* The accumulators need fpr registers. */
6371 /* This hook exists to catch the case where secondary_reload_class() is
6372 called from init_reg_autoinc() in regclass.c - before the reload optabs
6373 have been initialised. */
6376 frv_secondary_reload (bool in_p
, rtx x
, reg_class_t reload_class_i
,
6377 machine_mode reload_mode
,
6378 secondary_reload_info
* sri
)
6380 enum reg_class rclass
= NO_REGS
;
6381 enum reg_class reload_class
= (enum reg_class
) reload_class_i
;
6383 if (sri
->prev_sri
&& sri
->prev_sri
->t_icode
!= CODE_FOR_nothing
)
6385 sri
->icode
= sri
->prev_sri
->t_icode
;
6389 rclass
= frv_secondary_reload_class (reload_class
, reload_mode
, x
);
6391 if (rclass
!= NO_REGS
)
6393 enum insn_code icode
6394 = direct_optab_handler (in_p
? reload_in_optab
: reload_out_optab
,
6398 /* This happens when then the reload_[in|out]_optabs have
6399 not been initialised. */
6400 sri
->t_icode
= CODE_FOR_nothing
;
6405 /* Fall back to the default secondary reload handler. */
6406 return default_secondary_reload (in_p
, x
, reload_class
, reload_mode
, sri
);
6410 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6413 frv_class_likely_spilled_p (reg_class_t rclass
)
6423 case FDPIC_FPTR_REGS
:
6443 /* An expression for the alignment of a structure field FIELD if the
6444 alignment computed in the usual way is COMPUTED. GCC uses this
6445 value instead of the value in `BIGGEST_ALIGNMENT' or
6446 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6448 /* The definition type of the bit field data is either char, short, long or
6449 long long. The maximum bit size is the number of bits of its own type.
6451 The bit field data is assigned to a storage unit that has an adequate size
6452 for bit field data retention and is located at the smallest address.
6454 Consecutive bit field data are packed at consecutive bits having the same
6455 storage unit, with regard to the type, beginning with the MSB and continuing
6458 If a field to be assigned lies over a bit field type boundary, its
6459 assignment is completed by aligning it with a boundary suitable for the
6462 When a bit field having a bit length of 0 is declared, it is forcibly
6463 assigned to the next storage unit.
6476 &x 00000000 00000000 00000000 00000000
6479 &x+4 00000000 00000000 00000000 00000000
6482 &x+8 00000000 00000000 00000000 00000000
6485 &x+12 00000000 00000000 00000000 00000000
6491 frv_adjust_field_align (tree field
, int computed
)
6493 /* Make sure that the bitfield is not wider than the type. */
6495 && DECL_BIT_FIELD (field
)
6496 && !DECL_ARTIFICIAL (field
))
6498 tree parent
= DECL_CONTEXT (field
);
6499 tree prev
= NULL_TREE
;
6502 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= DECL_CHAIN (cur
))
6504 if (TREE_CODE (cur
) != FIELD_DECL
)
6512 /* If this isn't a :0 field and if the previous element is a bitfield
6513 also, see if the type is different, if so, we will need to align the
6514 bit-field to the next boundary. */
6516 && ! DECL_PACKED (field
)
6517 && ! integer_zerop (DECL_SIZE (field
))
6518 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6520 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6521 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6522 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6530 /* Implement TARGET_HARD_REGNO_MODE_OK. */
6533 frv_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
6543 return ICC_P (regno
) || GPR_P (regno
);
6546 return CR_P (regno
) || GPR_P (regno
);
6549 return FCC_P (regno
) || GPR_P (regno
);
6555 /* Set BASE to the first register in REGNO's class. Set MASK to the
6556 bits that must be clear in (REGNO - BASE) for the register to be
6558 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6562 /* ACCGs store one byte. Two-byte quantities must start in
6563 even-numbered registers, four-byte ones in registers whose
6564 numbers are divisible by four, and so on. */
6566 mask
= GET_MODE_SIZE (mode
) - 1;
6570 /* The other registers store one word. */
6571 if (GPR_P (regno
) || regno
== AP_FIRST
)
6574 else if (FPR_P (regno
))
6577 else if (ACC_P (regno
))
6580 else if (SPR_P (regno
))
6581 return mode
== SImode
;
6583 /* Fill in the table. */
6587 /* Anything smaller than an SI is OK in any word-sized register. */
6588 if (GET_MODE_SIZE (mode
) < 4)
6591 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6593 return (((regno
- base
) & mask
) == 0);
6599 /* Implement TARGET_MODES_TIEABLE_P. */
6602 frv_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
6604 return mode1
== mode2
;
6608 /* Implement TARGET_HARD_REGNO_NREGS.
6610 On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6611 that we can build the appropriate instructions to properly reload the
6612 values. Also, make the byte-sized accumulator guards use one guard
6616 frv_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
6619 return GET_MODE_SIZE (mode
);
6621 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6625 /* Implement CLASS_MAX_NREGS. */
6628 frv_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
6630 if (rclass
== ACCG_REGS
)
6631 /* An N-byte value requires N accumulator guards. */
6632 return GET_MODE_SIZE (mode
);
6634 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6638 /* A C expression that is nonzero if X is a legitimate constant for an
6639 immediate operand on the target machine. You can assume that X satisfies
6640 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6641 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6644 frv_legitimate_constant_p (machine_mode mode
, rtx x
)
6646 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6647 means that the move expanders will be expected to deal with most
6648 kinds of constant, regardless of what we return here.
6650 However, among its other duties, frv_legitimate_constant_p decides whether
6651 a constant can be entered into reg_equiv_constant[]. If we return true,
6652 reload can create new instances of the constant whenever it likes.
6654 The idea is therefore to accept as many constants as possible (to give
6655 reload more freedom) while rejecting constants that can only be created
6656 at certain times. In particular, anything with a symbolic component will
6657 require use of the pseudo FDPIC register, which is only available before
6660 return LEGITIMATE_PIC_OPERAND_P (x
);
6662 /* All of the integer constants are ok. */
6663 if (GET_CODE (x
) != CONST_DOUBLE
)
6666 /* double integer constants are ok. */
6667 if (GET_MODE (x
) == VOIDmode
|| mode
== DImode
)
6670 /* 0 is always ok. */
6671 if (x
== CONST0_RTX (mode
))
6674 /* If floating point is just emulated, allow any constant, since it will be
6675 constructed in the GPRs. */
6676 if (!TARGET_HAS_FPRS
)
6679 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6682 /* Otherwise store the constant away and do a load. */
6686 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6687 CC_NZ for comparisons against zero in which a single Z or N flag test
6688 is enough, CC_UNS for other unsigned comparisons, and CC for other
6689 signed comparisons. */
6692 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6694 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6703 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6709 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6717 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6719 #define HIGH_COST 40
6720 #define MEDIUM_COST 3
6724 frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
6725 reg_class_t from
, reg_class_t to
)
6738 case FDPIC_FPTR_REGS
:
6739 case FDPIC_CALL_REGS
:
6752 case FDPIC_FPTR_REGS
:
6753 case FDPIC_CALL_REGS
:
6778 case FDPIC_FPTR_REGS
:
6779 case FDPIC_CALL_REGS
:
6803 case FDPIC_FPTR_REGS
:
6804 case FDPIC_CALL_REGS
:
6825 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6828 frv_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
6829 reg_class_t rclass ATTRIBUTE_UNUSED
,
6830 bool in ATTRIBUTE_UNUSED
)
6836 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6837 use ".picptr" to generate safe relocations for PIC code. We also
6838 need a fixup entry for aligned (non-debugging) code. */
6841 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6843 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6845 if (GET_CODE (value
) == CONST
6846 || GET_CODE (value
) == SYMBOL_REF
6847 || GET_CODE (value
) == LABEL_REF
)
6849 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6850 && SYMBOL_REF_FUNCTION_P (value
))
6852 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6853 output_addr_const (asm_out_file
, value
);
6854 fputs (")\n", asm_out_file
);
6857 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6858 && frv_function_symbol_referenced_p (value
))
6860 if (aligned_p
&& !TARGET_FDPIC
)
6862 static int label_num
= 0;
6866 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6867 p
= (* targetm
.strip_name_encoding
) (buf
);
6869 fprintf (asm_out_file
, "%s:\n", p
);
6870 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6871 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6872 fprintf (asm_out_file
, "\t.previous\n");
6874 assemble_integer_with_op ("\t.picptr\t", value
);
6879 /* We've set the unaligned SI op to NULL, so we always have to
6880 handle the unaligned case here. */
6881 assemble_integer_with_op ("\t.4byte\t", value
);
6885 return default_assemble_integer (value
, size
, aligned_p
);
6888 /* Function to set up the backend function structure. */
6890 static struct machine_function
*
6891 frv_init_machine_status (void)
6893 return ggc_cleared_alloc
<machine_function
> ();
6896 /* Implement TARGET_SCHED_ISSUE_RATE. */
6899 frv_issue_rate (void)
6904 switch (frv_cpu_type
)
6908 case FRV_CPU_SIMPLE
:
6916 case FRV_CPU_GENERIC
:
6918 case FRV_CPU_TOMCAT
:
6926 /* Return the value of INSN's acc_group attribute. */
6929 frv_acc_group (rtx insn
)
6931 /* This distinction only applies to the FR550 packing constraints. */
6932 if (frv_cpu_type
== FRV_CPU_FR550
)
6934 subrtx_iterator::array_type array
;
6935 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
6938 unsigned int regno
= REGNO (*iter
);
6939 /* If REGNO refers to an accumulator, return ACC_GROUP_ODD if
6940 the bit 2 of the register number is set and ACC_GROUP_EVEN if
6943 return (regno
- ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
6945 return (regno
- ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
6948 return ACC_GROUP_NONE
;
6951 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
6952 INSN will try to claim first. Since this value depends only on the
6953 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
6956 frv_insn_unit (rtx_insn
*insn
)
6958 enum attr_type type
;
6960 type
= get_attr_type (insn
);
6961 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
6963 /* We haven't seen this type of instruction before. */
6967 /* Issue the instruction on its own to see which unit it prefers. */
6968 state
= alloca (state_size ());
6969 state_reset (state
);
6970 state_transition (state
, insn
);
6972 /* Find out which unit was taken. */
6973 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
6974 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
6977 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
6979 frv_type_to_unit
[type
] = unit
;
6981 return frv_type_to_unit
[type
];
6984 /* Return true if INSN issues to a branch unit. */
6987 frv_issues_to_branch_unit_p (rtx_insn
*insn
)
6989 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
6992 /* The instructions in the packet, partitioned into groups. */
6993 struct frv_packet_group
{
6994 /* How many instructions in the packet belong to this group. */
6995 unsigned int num_insns
;
6997 /* A list of the instructions that belong to this group, in the order
6998 they appear in the rtl stream. */
6999 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_codes
)];
7001 /* The contents of INSNS after they have been sorted into the correct
7002 assembly-language order. Element X issues to unit X. The list may
7003 contain extra nops. */
7004 rtx_insn
*sorted
[ARRAY_SIZE (frv_unit_codes
)];
7006 /* The member of frv_nops[] to use in sorted[]. */
7010 /* The current state of the packing pass, implemented by frv_pack_insns. */
7012 /* The state of the pipeline DFA. */
7015 /* Which hardware registers are set within the current packet,
7016 and the conditions under which they are set. */
7017 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7019 /* The memory locations that have been modified so far in this
7020 packet. MEM is the memref and COND is the regstate_t condition
7021 under which it is set. */
7027 /* The number of valid entries in MEMS. The value is larger than
7028 ARRAY_SIZE (mems) if there were too many mems to record. */
7029 unsigned int num_mems
;
7031 /* The maximum number of instructions that can be packed together. */
7032 unsigned int issue_rate
;
7034 /* The instructions in the packet, partitioned into groups. */
7035 struct frv_packet_group groups
[NUM_GROUPS
];
7037 /* The instructions that make up the current packet. */
7038 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_codes
)];
7039 unsigned int num_insns
;
7042 /* Return the regstate_t flags for the given COND_EXEC condition.
7043 Abort if the condition isn't in the right form. */
7046 frv_cond_flags (rtx cond
)
7048 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7049 && GET_CODE (XEXP (cond
, 0)) == REG
7050 && CR_P (REGNO (XEXP (cond
, 0)))
7051 && XEXP (cond
, 1) == const0_rtx
);
7052 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7053 | (GET_CODE (cond
) == NE
7055 : REGSTATE_IF_FALSE
));
7059 /* Return true if something accessed under condition COND2 can
7060 conflict with something written under condition COND1. */
7063 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7065 /* If either reference was unconditional, we have a conflict. */
7066 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7067 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7070 /* The references might conflict if they were controlled by
7072 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7075 /* They definitely conflict if they are controlled by the
7077 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7084 /* Return true if an instruction with pattern PAT depends on an
7085 instruction in the current packet. COND describes the condition
7086 under which PAT might be set or used. */
7089 frv_registers_conflict_p_1 (rtx pat
, regstate_t cond
)
7091 subrtx_var_iterator::array_type array
;
7092 FOR_EACH_SUBRTX_VAR (iter
, array
, pat
, NONCONST
)
7095 if (GET_CODE (x
) == REG
)
7098 FOR_EACH_REGNO (regno
, x
)
7099 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7100 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7103 else if (GET_CODE (x
) == MEM
)
7105 /* If we ran out of memory slots, assume a conflict. */
7106 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7109 /* Check for output or true dependencies with earlier MEMs. */
7110 for (unsigned int i
= 0; i
< frv_packet
.num_mems
; i
++)
7111 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7113 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
, x
))
7116 if (output_dependence (frv_packet
.mems
[i
].mem
, x
))
7121 /* The return values of calls aren't significant: they describe
7122 the effect of the call as a whole, not of the insn itself. */
7123 else if (GET_CODE (x
) == SET
&& GET_CODE (SET_SRC (x
)) == CALL
)
7124 iter
.substitute (SET_SRC (x
));
7130 /* Return true if something in X might depend on an instruction
7131 in the current packet. */
7134 frv_registers_conflict_p (rtx x
)
7139 if (GET_CODE (x
) == COND_EXEC
)
7141 if (frv_registers_conflict_p_1 (XEXP (x
, 0), flags
))
7144 flags
|= frv_cond_flags (XEXP (x
, 0));
7147 return frv_registers_conflict_p_1 (x
, flags
);
7151 /* A note_stores callback. DATA points to the regstate_t condition
7152 under which X is modified. Update FRV_PACKET accordingly. */
7155 frv_registers_update_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7159 if (GET_CODE (x
) == REG
)
7160 FOR_EACH_REGNO (regno
, x
)
7161 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7163 if (GET_CODE (x
) == MEM
)
7165 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7167 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7168 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7170 frv_packet
.num_mems
++;
7175 /* Update the register state information for an instruction whose
7179 frv_registers_update (rtx x
)
7183 flags
= REGSTATE_MODIFIED
;
7184 if (GET_CODE (x
) == COND_EXEC
)
7186 flags
|= frv_cond_flags (XEXP (x
, 0));
7189 note_stores (x
, frv_registers_update_1
, &flags
);
7193 /* Initialize frv_packet for the start of a new packet. */
7196 frv_start_packet (void)
7198 enum frv_insn_group group
;
7200 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7201 frv_packet
.num_mems
= 0;
7202 frv_packet
.num_insns
= 0;
7203 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7204 group
= (enum frv_insn_group
) (group
+ 1))
7205 frv_packet
.groups
[group
].num_insns
= 0;
7209 /* Likewise for the start of a new basic block. */
7212 frv_start_packet_block (void)
7214 state_reset (frv_packet
.dfa_state
);
7215 frv_start_packet ();
7219 /* Finish the current packet, if any, and start a new one. Call
7220 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7223 frv_finish_packet (void (*handle_packet
) (void))
7225 if (frv_packet
.num_insns
> 0)
7228 state_transition (frv_packet
.dfa_state
, 0);
7229 frv_start_packet ();
7234 /* Return true if INSN can be added to the current packet. Update
7235 the DFA state on success. */
7238 frv_pack_insn_p (rtx_insn
*insn
)
7240 /* See if the packet is already as long as it can be. */
7241 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7244 /* If the scheduler thought that an instruction should start a packet,
7245 it's usually a good idea to believe it. It knows much more about
7246 the latencies than we do.
7248 There are some exceptions though:
7250 - Conditional instructions are scheduled on the assumption that
7251 they will be executed. This is usually a good thing, since it
7252 tends to avoid unnecessary stalls in the conditional code.
7253 But we want to pack conditional instructions as tightly as
7254 possible, in order to optimize the case where they aren't
7257 - The scheduler will always put branches on their own, even
7258 if there's no real dependency.
7260 - There's no point putting a call in its own packet unless
7262 if (frv_packet
.num_insns
> 0
7263 && NONJUMP_INSN_P (insn
)
7264 && GET_MODE (insn
) == TImode
7265 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7268 /* Check for register conflicts. Don't do this for setlo since any
7269 conflict will be with the partnering sethi, with which it can
7271 if (get_attr_type (insn
) != TYPE_SETLO
)
7272 if (frv_registers_conflict_p (PATTERN (insn
)))
7275 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7279 /* Add instruction INSN to the current packet. */
7282 frv_add_insn_to_packet (rtx_insn
*insn
)
7284 struct frv_packet_group
*packet_group
;
7286 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7287 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7288 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7290 frv_registers_update (PATTERN (insn
));
7294 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7295 packet ends in a branch or call, insert the nop before it, otherwise
7299 frv_insert_nop_in_packet (rtx_insn
*insn
)
7301 struct frv_packet_group
*packet_group
;
7304 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7305 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7306 if (! NONJUMP_INSN_P (last
))
7308 insn
= emit_insn_before (PATTERN (insn
), last
);
7309 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7310 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7314 insn
= emit_insn_after (PATTERN (insn
), last
);
7315 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7317 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7321 /* If packing is enabled, divide the instructions into packets and
7322 return true. Call HANDLE_PACKET for each complete packet. */
7325 frv_for_each_packet (void (*handle_packet
) (void))
7327 rtx_insn
*insn
, *next_insn
;
7329 frv_packet
.issue_rate
= frv_issue_rate ();
7331 /* Early exit if we don't want to pack insns. */
7333 || !flag_schedule_insns_after_reload
7334 || !TARGET_VLIW_BRANCH
7335 || frv_packet
.issue_rate
== 1)
7338 /* Set up the initial packing state. */
7340 frv_packet
.dfa_state
= alloca (state_size ());
7342 frv_start_packet_block ();
7343 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7348 code
= GET_CODE (insn
);
7349 next_insn
= NEXT_INSN (insn
);
7351 if (code
== CODE_LABEL
)
7353 frv_finish_packet (handle_packet
);
7354 frv_start_packet_block ();
7358 switch (GET_CODE (PATTERN (insn
)))
7365 /* Calls mustn't be packed on a TOMCAT. */
7366 if (CALL_P (insn
) && frv_cpu_type
== FRV_CPU_TOMCAT
)
7367 frv_finish_packet (handle_packet
);
7369 /* Since the last instruction in a packet determines the EH
7370 region, any exception-throwing instruction must come at
7371 the end of reordered packet. Insns that issue to a
7372 branch unit are bound to come last; for others it's
7373 too hard to predict. */
7374 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7375 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7376 frv_finish_packet (handle_packet
);
7378 /* Finish the current packet if we can't add INSN to it.
7379 Simulate cycles until INSN is ready to issue. */
7380 if (!frv_pack_insn_p (insn
))
7382 frv_finish_packet (handle_packet
);
7383 while (!frv_pack_insn_p (insn
))
7384 state_transition (frv_packet
.dfa_state
, 0);
7387 /* Add the instruction to the packet. */
7388 frv_add_insn_to_packet (insn
);
7390 /* Calls and jumps end a packet, as do insns that throw
7392 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7393 frv_finish_packet (handle_packet
);
7397 frv_finish_packet (handle_packet
);
7402 /* Subroutine of frv_sort_insn_group. We are trying to sort
7403 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7404 language order. We have already picked a new position for
7405 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7406 These instructions will occupy elements [0, LOWER_SLOT) and
7407 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7408 the DFA state after issuing these instructions.
7410 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7411 of the unused instructions. Return true if one such permutation gives
7412 a valid ordering, leaving the successful permutation in sorted[].
7413 Do not modify sorted[] until a valid permutation is found. */
7416 frv_sort_insn_group_1 (enum frv_insn_group group
,
7417 unsigned int lower_slot
, unsigned int upper_slot
,
7418 unsigned int issued
, unsigned int num_insns
,
7421 struct frv_packet_group
*packet_group
;
7427 /* Early success if we've filled all the slots. */
7428 if (lower_slot
== upper_slot
)
7431 packet_group
= &frv_packet
.groups
[group
];
7432 dfa_size
= state_size ();
7433 test_state
= alloca (dfa_size
);
7435 /* Try issuing each unused instruction. */
7436 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7437 if (~issued
& (1 << i
))
7439 insn
= packet_group
->sorted
[i
];
7440 memcpy (test_state
, state
, dfa_size
);
7441 if (state_transition (test_state
, insn
) < 0
7442 && cpu_unit_reservation_p (test_state
,
7443 NTH_UNIT (group
, upper_slot
- 1))
7444 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7445 issued
| (1 << i
), num_insns
,
7448 packet_group
->sorted
[upper_slot
- 1] = insn
;
7456 /* Compare two instructions by their frv_insn_unit. */
7459 frv_compare_insns (const void *first
, const void *second
)
7461 rtx_insn
* const *insn1
= (rtx_insn
* const *) first
;
7462 rtx_insn
* const *insn2
= (rtx_insn
* const *) second
;
7463 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7466 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7467 and sort it into assembly language order. See frv.md for a description of
7471 frv_sort_insn_group (enum frv_insn_group group
)
7473 struct frv_packet_group
*packet_group
;
7474 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7475 state_t state
, test_state
;
7478 packet_group
= &frv_packet
.groups
[group
];
7480 /* Assume no nop is needed. */
7481 packet_group
->nop
= 0;
7483 if (packet_group
->num_insns
== 0)
7486 /* Copy insns[] to sorted[]. */
7487 memcpy (packet_group
->sorted
, packet_group
->insns
,
7488 sizeof (rtx
) * packet_group
->num_insns
);
7490 /* Sort sorted[] by the unit that each insn tries to take first. */
7491 if (packet_group
->num_insns
> 1)
7492 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7493 sizeof (rtx
), frv_compare_insns
);
7495 /* That's always enough for branch and control insns. */
7496 if (group
== GROUP_B
|| group
== GROUP_C
)
7499 dfa_size
= state_size ();
7500 state
= alloca (dfa_size
);
7501 test_state
= alloca (dfa_size
);
7503 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7504 consecutively and such that the DFA takes unit X when sorted[X]
7505 is added. Set STATE to the new DFA state. */
7506 state_reset (test_state
);
7507 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7509 memcpy (state
, test_state
, dfa_size
);
7510 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7511 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7515 /* If all the instructions issued in ascending order, we're done. */
7516 if (first
== packet_group
->num_insns
)
7519 /* Add nops to the end of sorted[] and try each permutation until
7520 we find one that works. */
7521 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7523 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7524 if (frv_unit_groups
[max_unit
] == group
)
7526 packet_group
->nop
= frv_nops
[nop
];
7527 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7528 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7529 packet_group
->sorted
[i
] = frv_nops
[nop
];
7530 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7531 (1 << first
) - 1, num_slots
, state
))
7538 /* Sort the current packet into assembly-language order. Set packing
7539 flags as appropriate. */
7542 frv_reorder_packet (void)
7544 unsigned int cursor
[NUM_GROUPS
];
7545 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_groups
)];
7546 unsigned int unit
, to
, from
;
7547 enum frv_insn_group group
;
7548 struct frv_packet_group
*packet_group
;
7550 /* First sort each group individually. */
7551 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7552 group
= (enum frv_insn_group
) (group
+ 1))
7555 frv_sort_insn_group (group
);
7558 /* Go through the unit template and try add an instruction from
7559 that unit's group. */
7561 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7563 group
= frv_unit_groups
[unit
];
7564 packet_group
= &frv_packet
.groups
[group
];
7565 if (cursor
[group
] < packet_group
->num_insns
)
7567 /* frv_reorg should have added nops for us. */
7568 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7569 != packet_group
->nop
);
7570 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7574 gcc_assert (to
== frv_packet
.num_insns
);
7576 /* Clear the last instruction's packing flag, thus marking the end of
7577 a packet. Reorder the other instructions relative to it. */
7578 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7579 for (from
= 0; from
< to
- 1; from
++)
7581 remove_insn (insns
[from
]);
7582 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7583 SET_PACKING_FLAG (insns
[from
]);
7588 /* Divide instructions into packets. Reorder the contents of each
7589 packet so that they are in the correct assembly-language order.
7591 Since this pass can change the raw meaning of the rtl stream, it must
7592 only be called at the last minute, just before the instructions are
7596 frv_pack_insns (void)
7598 if (frv_for_each_packet (frv_reorder_packet
))
7599 frv_insn_packing_flag
= 0;
7601 frv_insn_packing_flag
= -1;
7604 /* See whether we need to add nops to group GROUP in order to
7605 make a valid packet. */
7608 frv_fill_unused_units (enum frv_insn_group group
)
7610 unsigned int non_nops
, nops
, i
;
7611 struct frv_packet_group
*packet_group
;
7613 packet_group
= &frv_packet
.groups
[group
];
7615 /* Sort the instructions into assembly-language order.
7616 Use nops to fill slots that are otherwise unused. */
7617 frv_sort_insn_group (group
);
7619 /* See how many nops are needed before the final useful instruction. */
7621 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7622 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7625 /* Insert that many nops into the instruction stream. */
7627 frv_insert_nop_in_packet (packet_group
->nop
);
7630 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7633 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7635 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7636 return io1
->const_address
== io2
->const_address
;
7638 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7639 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7644 /* Return true if operations IO1 and IO2 are guaranteed to complete
7648 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7650 /* The order of writes is always preserved. */
7651 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7654 /* The order of reads isn't preserved. */
7655 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7658 /* One operation is a write and the other is (or could be) a read.
7659 The order is only guaranteed if the accesses are to the same
7661 return frv_same_doubleword_p (io1
, io2
);
7664 /* Generalize I/O operation X so that it covers both X and Y. */
7667 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7669 if (x
->type
!= y
->type
)
7670 x
->type
= FRV_IO_UNKNOWN
;
7671 if (!frv_same_doubleword_p (x
, y
))
7673 x
->const_address
= 0;
7678 /* Fill IO with information about the load or store associated with
7679 membar instruction INSN. */
7682 frv_extract_membar (struct frv_io
*io
, rtx_insn
*insn
)
7684 extract_insn (insn
);
7685 io
->type
= (enum frv_io_type
) INTVAL (recog_data
.operand
[2]);
7686 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7687 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7690 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7691 if X is a register and *DATA depends on X. */
7694 frv_io_check_address (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7696 rtx
*other
= (rtx
*) data
;
7698 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7702 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7703 Remove every modified register from the set. */
7706 frv_io_handle_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7708 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7712 FOR_EACH_REGNO (regno
, x
)
7713 CLEAR_HARD_REG_BIT (*set
, regno
);
7716 /* A note_uses callback that adds all registers in *X to hard register
7720 frv_io_handle_use (rtx
*x
, void *data
)
7722 find_all_hard_regs (*x
, (HARD_REG_SET
*) data
);
7725 /* Go through block BB looking for membars to remove. There are two
7726 cases where intra-block analysis is enough:
7728 - a membar is redundant if it occurs between two consecutive I/O
7729 operations and if those operations are guaranteed to complete
7732 - a membar for a __builtin_read is redundant if the result is
7733 used before the next I/O operation is issued.
7735 If the last membar in the block could not be removed, and there
7736 are guaranteed to be no I/O operations between that membar and
7737 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7740 Describe the block's first I/O operation in *NEXT_IO. Describe
7741 an unknown operation if the block doesn't do any I/O. */
7744 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7745 rtx_insn
**last_membar
)
7747 HARD_REG_SET used_regs
;
7749 rtx_insn
*insn
, *next_membar
;
7752 /* NEXT_IO is the next I/O operation to be performed after the current
7753 instruction. It starts off as being an unknown operation. */
7754 memset (next_io
, 0, sizeof (*next_io
));
7756 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7757 next_is_end_p
= true;
7759 /* If the current instruction is a __builtin_read or __builtin_write,
7760 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7761 is null if the membar has already been deleted.
7763 Note that the initialization here should only be needed to
7764 suppress warnings. */
7767 /* USED_REGS is the set of registers that are used before the
7768 next I/O instruction. */
7769 CLEAR_HARD_REG_SET (used_regs
);
7771 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7774 /* We can't predict what a call will do to volatile memory. */
7775 memset (next_io
, 0, sizeof (struct frv_io
));
7776 next_is_end_p
= false;
7777 CLEAR_HARD_REG_SET (used_regs
);
7779 else if (INSN_P (insn
))
7780 switch (recog_memoized (insn
))
7782 case CODE_FOR_optional_membar_qi
:
7783 case CODE_FOR_optional_membar_hi
:
7784 case CODE_FOR_optional_membar_si
:
7785 case CODE_FOR_optional_membar_di
:
7789 /* Local information isn't enough to decide whether this
7790 membar is needed. Stash it away for later. */
7791 *last_membar
= insn
;
7792 frv_extract_membar (next_io
, insn
);
7793 next_is_end_p
= false;
7797 /* Check whether the I/O operation before INSN could be
7798 reordered with one described by NEXT_IO. If it can't,
7799 INSN will not be needed. */
7800 struct frv_io prev_io
;
7802 frv_extract_membar (&prev_io
, insn
);
7803 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7807 ";; [Local] Removing membar %d since order"
7808 " of accesses is guaranteed\n",
7809 INSN_UID (next_membar
));
7811 insn
= NEXT_INSN (insn
);
7812 delete_insn (next_membar
);
7820 /* Invalidate NEXT_IO's address if it depends on something that
7821 is clobbered by INSN. */
7822 if (next_io
->var_address
)
7823 note_stores (PATTERN (insn
), frv_io_check_address
,
7824 &next_io
->var_address
);
7826 /* If the next membar is associated with a __builtin_read,
7827 see if INSN reads from that address. If it does, and if
7828 the destination register is used before the next I/O access,
7829 there is no need for the membar. */
7830 set
= PATTERN (insn
);
7831 if (next_io
->type
== FRV_IO_READ
7832 && next_io
->var_address
!= 0
7834 && GET_CODE (set
) == SET
7835 && GET_CODE (SET_DEST (set
)) == REG
7836 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7840 src
= SET_SRC (set
);
7841 if (GET_CODE (src
) == ZERO_EXTEND
)
7842 src
= XEXP (src
, 0);
7844 if (GET_CODE (src
) == MEM
7845 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7849 ";; [Local] Removing membar %d since the target"
7850 " of %d is used before the I/O operation\n",
7851 INSN_UID (next_membar
), INSN_UID (insn
));
7853 if (next_membar
== *last_membar
)
7856 delete_insn (next_membar
);
7861 /* If INSN has volatile references, forget about any registers
7862 that are used after it. Otherwise forget about uses that
7863 are (or might be) defined by INSN. */
7864 if (volatile_refs_p (PATTERN (insn
)))
7865 CLEAR_HARD_REG_SET (used_regs
);
7867 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
7869 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
7874 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7875 FIRST_IO[X] describes the first operation performed by basic block X. */
7878 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
7881 struct frv_io this_io
, next_io
;
7885 /* We need to keep the membar if there is an edge to the exit block. */
7886 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
7887 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
7888 if (succ
->dest
== EXIT_BLOCK_PTR_FOR_FN (cfun
))
7891 /* Work out the union of all successor blocks. */
7892 ei
= ei_start (bb
->succs
);
7893 ei_cond (ei
, &succ
);
7894 /* next_io = first_io[bb->succ->dest->index]; */
7895 next_io
= first_io
[succ
->dest
->index
];
7896 ei
= ei_start (bb
->succs
);
7897 if (ei_cond (ei
, &succ
))
7899 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
7900 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
7901 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
7906 frv_extract_membar (&this_io
, membar
);
7907 if (frv_io_fixed_order_p (&this_io
, &next_io
))
7911 ";; [Global] Removing membar %d since order of accesses"
7912 " is guaranteed\n", INSN_UID (membar
));
7914 delete_insn (membar
);
7918 /* Remove redundant membars from the current function. */
7921 frv_optimize_membar (void)
7924 struct frv_io
*first_io
;
7925 rtx_insn
**last_membar
;
7927 compute_bb_for_insn ();
7928 first_io
= XCNEWVEC (struct frv_io
, last_basic_block_for_fn (cfun
));
7929 last_membar
= XCNEWVEC (rtx_insn
*, last_basic_block_for_fn (cfun
));
7931 FOR_EACH_BB_FN (bb
, cfun
)
7932 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
7933 &last_membar
[bb
->index
]);
7935 FOR_EACH_BB_FN (bb
, cfun
)
7936 if (last_membar
[bb
->index
] != 0)
7937 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
7943 /* Used by frv_reorg to keep track of the current packet's address. */
7944 static unsigned int frv_packet_address
;
7946 /* If the current packet falls through to a label, try to pad the packet
7947 with nops in order to fit the label's alignment requirements. */
7950 frv_align_label (void)
7952 unsigned int alignment
, target
, nop
;
7953 rtx_insn
*x
, *last
, *barrier
, *label
;
7955 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
7956 maximum alignment of that packet, LABEL to the last label between
7957 the packets, and BARRIER to the last barrier. */
7958 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7959 label
= barrier
= 0;
7961 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
7965 unsigned int subalign
= 1 << label_to_alignment (x
);
7966 alignment
= MAX (alignment
, subalign
);
7973 /* If -malign-labels, and the packet falls through to an unaligned
7974 label, try introducing a nop to align that label to 8 bytes. */
7975 if (TARGET_ALIGN_LABELS
7978 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
7979 alignment
= MAX (alignment
, 8);
7981 /* Advance the address to the end of the current packet. */
7982 frv_packet_address
+= frv_packet
.num_insns
* 4;
7984 /* Work out the target address, after alignment. */
7985 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
7987 /* If the packet falls through to the label, try to find an efficient
7988 padding sequence. */
7991 /* First try adding nops to the current packet. */
7992 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7993 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
7995 frv_insert_nop_in_packet (frv_nops
[nop
]);
7996 frv_packet_address
+= 4;
7999 /* If we still haven't reached the target, add some new packets that
8000 contain only nops. If there are two types of nop, insert an
8001 alternating sequence of frv_nops[0] and frv_nops[1], which will
8002 lead to packets like:
8009 etc. Just emit frv_nops[0] if that's the only nop we have. */
8010 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8012 while (frv_packet_address
< target
)
8014 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8015 frv_packet_address
+= 4;
8016 if (frv_num_nops
> 1)
8021 frv_packet_address
= target
;
8024 /* Subroutine of frv_reorg, called after each packet has been constructed
8028 frv_reorg_packet (void)
8030 frv_fill_unused_units (GROUP_I
);
8031 frv_fill_unused_units (GROUP_FM
);
8035 /* Add an instruction with pattern NOP to frv_nops[]. */
8038 frv_register_nop (rtx nop
)
8040 rtx_insn
*nop_insn
= make_insn_raw (nop
);
8041 SET_NEXT_INSN (nop_insn
) = 0;
8042 SET_PREV_INSN (nop_insn
) = 0;
8043 frv_nops
[frv_num_nops
++] = nop_insn
;
8046 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8047 into packets and check whether we need to insert nops in order to
8048 fulfill the processor's issue requirements. Also, if the user has
8049 requested a certain alignment for a label, try to meet that alignment
8050 by inserting nops in the previous packet. */
8055 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8056 frv_optimize_membar ();
8059 frv_register_nop (gen_nop ());
8061 frv_register_nop (gen_mnop ());
8062 if (TARGET_HARD_FLOAT
)
8063 frv_register_nop (gen_fnop ());
8065 /* Estimate the length of each branch. Although this may change after
8066 we've inserted nops, it will only do so in big functions. */
8067 shorten_branches (get_insns ());
8069 frv_packet_address
= 0;
8070 frv_for_each_packet (frv_reorg_packet
);
8073 #define def_builtin(name, type, code) \
8074 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8076 struct builtin_description
8078 enum insn_code icode
;
8080 enum frv_builtins code
;
8081 enum rtx_code comparison
;
8085 /* Media intrinsics that take a single, constant argument. */
8087 static struct builtin_description bdesc_set
[] =
8089 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, UNKNOWN
, 0 }
8092 /* Media intrinsics that take just one argument. */
8094 static struct builtin_description bdesc_1arg
[] =
8096 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, UNKNOWN
, 0 },
8097 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, UNKNOWN
, 0 },
8098 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, UNKNOWN
, 0 },
8099 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, UNKNOWN
, 0},
8100 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, UNKNOWN
, 0 },
8101 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, UNKNOWN
, 0 }
8104 /* Media intrinsics that take two arguments. */
8106 static struct builtin_description bdesc_2arg
[] =
8108 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, UNKNOWN
, 0},
8109 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, UNKNOWN
, 0},
8110 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, UNKNOWN
, 0},
8111 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, UNKNOWN
, 0},
8112 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, UNKNOWN
, 0},
8113 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, UNKNOWN
, 0},
8114 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, UNKNOWN
, 0},
8115 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, UNKNOWN
, 0},
8116 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, UNKNOWN
, 0},
8117 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, UNKNOWN
, 0},
8118 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, UNKNOWN
, 0},
8119 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, UNKNOWN
, 0},
8120 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, UNKNOWN
, 0},
8121 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, UNKNOWN
, 0},
8122 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, UNKNOWN
, 0},
8123 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, UNKNOWN
, 0},
8124 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, UNKNOWN
, 0},
8125 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, UNKNOWN
, 0},
8126 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, UNKNOWN
, 0},
8127 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, UNKNOWN
, 0},
8128 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, UNKNOWN
, 0},
8129 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, UNKNOWN
, 0},
8130 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, UNKNOWN
, 0},
8131 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, UNKNOWN
, 0},
8132 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, UNKNOWN
, 0},
8133 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, UNKNOWN
, 0},
8134 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, UNKNOWN
, 0}
8137 /* Integer intrinsics that take two arguments and have no return value. */
8139 static struct builtin_description bdesc_int_void2arg
[] =
8141 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, UNKNOWN
, 0},
8142 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, UNKNOWN
, 0},
8143 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, UNKNOWN
, 0}
8146 static struct builtin_description bdesc_prefetches
[] =
8148 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, UNKNOWN
,
8150 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, UNKNOWN
, 0}
8153 /* Media intrinsics that take two arguments, the first being an ACC number. */
8155 static struct builtin_description bdesc_cut
[] =
8157 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, UNKNOWN
, 0},
8158 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, UNKNOWN
, 0},
8159 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, UNKNOWN
, 0}
8162 /* Two-argument media intrinsics with an immediate second argument. */
8164 static struct builtin_description bdesc_2argimm
[] =
8166 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, UNKNOWN
, 0},
8167 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, UNKNOWN
, 0},
8168 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, UNKNOWN
, 0},
8169 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, UNKNOWN
, 0},
8170 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, UNKNOWN
, 0},
8171 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, UNKNOWN
, 0},
8172 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, UNKNOWN
, 0},
8173 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, UNKNOWN
, 0},
8174 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, UNKNOWN
, 0},
8175 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, UNKNOWN
, 0},
8176 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, UNKNOWN
, 0},
8177 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, UNKNOWN
, 0},
8178 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, UNKNOWN
, 0},
8179 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, UNKNOWN
, 0},
8180 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, UNKNOWN
, 0},
8181 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, UNKNOWN
, 0},
8182 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, UNKNOWN
, 0}
8185 /* Media intrinsics that take two arguments and return void, the first argument
8186 being a pointer to 4 words in memory. */
8188 static struct builtin_description bdesc_void2arg
[] =
8190 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, UNKNOWN
, 0},
8191 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, UNKNOWN
, 0},
8194 /* Media intrinsics that take three arguments, the first being a const_int that
8195 denotes an accumulator, and that return void. */
8197 static struct builtin_description bdesc_void3arg
[] =
8199 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, UNKNOWN
, 0},
8200 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, UNKNOWN
, 0},
8201 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, UNKNOWN
, 0},
8202 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, UNKNOWN
, 0},
8203 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, UNKNOWN
, 0},
8204 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, UNKNOWN
, 0},
8205 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, UNKNOWN
, 0},
8206 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, UNKNOWN
, 0},
8207 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, UNKNOWN
, 0},
8208 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, UNKNOWN
, 0},
8209 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, UNKNOWN
, 0},
8210 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, UNKNOWN
, 0},
8211 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, UNKNOWN
, 0},
8212 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, UNKNOWN
, 0},
8213 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, UNKNOWN
, 0},
8214 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, UNKNOWN
, 0},
8215 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, UNKNOWN
, 0},
8216 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, UNKNOWN
, 0},
8217 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, UNKNOWN
, 0},
8218 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, UNKNOWN
, 0},
8219 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, UNKNOWN
, 0},
8220 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, UNKNOWN
, 0},
8221 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, UNKNOWN
, 0},
8222 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, UNKNOWN
, 0},
8223 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, UNKNOWN
, 0}
8226 /* Media intrinsics that take two accumulator numbers as argument and
8229 static struct builtin_description bdesc_voidacc
[] =
8231 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, UNKNOWN
, 0},
8232 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, UNKNOWN
, 0},
8233 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, UNKNOWN
, 0},
8234 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, UNKNOWN
, 0},
8235 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, UNKNOWN
, 0},
8236 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, UNKNOWN
, 0}
8239 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8240 a normal move and the ICODE is for the membar. */
8242 static struct builtin_description bdesc_loads
[] =
8244 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8245 FRV_BUILTIN_READ8
, UNKNOWN
, 0},
8246 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8247 FRV_BUILTIN_READ16
, UNKNOWN
, 0},
8248 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8249 FRV_BUILTIN_READ32
, UNKNOWN
, 0},
8250 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8251 FRV_BUILTIN_READ64
, UNKNOWN
, 0}
8254 /* Likewise stores. */
8256 static struct builtin_description bdesc_stores
[] =
8258 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8259 FRV_BUILTIN_WRITE8
, UNKNOWN
, 0},
8260 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8261 FRV_BUILTIN_WRITE16
, UNKNOWN
, 0},
8262 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8263 FRV_BUILTIN_WRITE32
, UNKNOWN
, 0},
8264 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8265 FRV_BUILTIN_WRITE64
, UNKNOWN
, 0},
8268 /* Initialize media builtins. */
8271 frv_init_builtins (void)
8273 tree accumulator
= integer_type_node
;
8274 tree integer
= integer_type_node
;
8275 tree voidt
= void_type_node
;
8276 tree uhalf
= short_unsigned_type_node
;
8277 tree sword1
= long_integer_type_node
;
8278 tree uword1
= long_unsigned_type_node
;
8279 tree sword2
= long_long_integer_type_node
;
8280 tree uword2
= long_long_unsigned_type_node
;
8281 tree uword4
= build_pointer_type (uword1
);
8282 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8283 tree ubyte
= unsigned_char_type_node
;
8284 tree iacc
= integer_type_node
;
8286 #define UNARY(RET, T1) \
8287 build_function_type_list (RET, T1, NULL_TREE)
8289 #define BINARY(RET, T1, T2) \
8290 build_function_type_list (RET, T1, T2, NULL_TREE)
8292 #define TRINARY(RET, T1, T2, T3) \
8293 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8295 #define QUAD(RET, T1, T2, T3, T4) \
8296 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE)
8298 tree void_ftype_void
= build_function_type_list (voidt
, NULL_TREE
);
8300 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8301 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8302 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8303 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8304 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8305 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8306 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8307 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8308 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8310 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8311 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8312 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8313 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8314 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8315 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8316 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8317 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8318 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8319 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8320 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8322 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8323 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8324 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8326 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8327 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8328 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8329 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8330 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8331 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8333 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8334 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8335 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8336 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8337 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8338 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8339 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8340 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8341 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8342 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8343 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8344 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8345 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8346 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8347 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8348 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8349 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8351 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8352 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8353 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8354 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8355 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8356 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8357 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8358 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8359 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8360 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8361 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8362 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8363 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8364 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8365 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8366 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8367 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8368 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8369 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8370 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8371 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8372 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8373 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8374 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8375 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8376 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8377 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8378 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8379 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8380 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8381 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8382 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8383 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8384 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8385 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8386 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8387 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8388 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8389 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8390 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8391 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8392 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8393 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8394 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8395 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8396 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8397 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8398 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8399 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8400 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8401 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8402 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8403 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8404 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8405 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8406 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8407 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8408 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8409 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8410 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8411 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8412 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8413 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8414 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8415 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8416 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8417 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8418 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8419 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8420 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8421 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8422 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8423 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8424 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8425 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8426 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8427 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8428 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8429 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8430 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8431 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8432 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8433 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8434 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8435 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8436 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8437 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8438 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8439 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8440 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8441 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8442 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8443 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8444 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8445 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8446 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8447 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8448 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8449 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8450 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8451 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8452 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8453 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8454 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8455 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8456 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8457 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8458 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8460 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8461 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8462 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8463 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8471 /* Set the names for various arithmetic operations according to the
8474 frv_init_libfuncs (void)
8476 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8477 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8479 set_optab_libfunc (add_optab
, DImode
, "__addll");
8480 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8481 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8482 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8483 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8484 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8485 set_optab_libfunc (and_optab
, DImode
, "__andll");
8486 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8487 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8488 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8490 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8491 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8492 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8493 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8495 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8496 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8497 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8498 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8500 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8501 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8503 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8504 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8505 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8506 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8508 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8509 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8510 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8511 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8513 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8514 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8515 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8516 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8519 /* Convert an integer constant to an accumulator register. ICODE is the
8520 code of the target instruction, OPNUM is the number of the
8521 accumulator operand and OPVAL is the constant integer. Try both
8522 ACC and ACCG registers; only report an error if neither fit the
8526 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8531 /* ACCs and ACCGs are implicit global registers if media intrinsics
8532 are being used. We set up this lazily to avoid creating lots of
8533 unnecessary call_insn rtl in non-media code. */
8534 for (i
= 0; i
<= ACC_MASK
; i
++)
8535 if ((i
& ACC_MASK
) == i
)
8536 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8538 if (GET_CODE (opval
) != CONST_INT
)
8540 error ("accumulator is not a constant integer");
8543 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8545 error ("accumulator number is out of bounds");
8549 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8550 ACC_FIRST
+ INTVAL (opval
));
8551 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8552 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8554 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8556 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8562 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8566 frv_matching_accg_mode (machine_mode mode
)
8584 /* Given that a __builtin_read or __builtin_write function is accessing
8585 address ADDRESS, return the value that should be used as operand 1
8589 frv_io_address_cookie (rtx address
)
8591 return (GET_CODE (address
) == CONST_INT
8592 ? GEN_INT (INTVAL (address
) / 8 * 8)
8596 /* Return the accumulator guard that should be paired with accumulator
8597 register ACC. The mode of the returned register is in the same
8598 class as ACC, but is four times smaller. */
8601 frv_matching_accg_for_acc (rtx acc
)
8603 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8604 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8607 /* Read the requested argument from the call EXP given by INDEX.
8608 Return the value as an rtx. */
8611 frv_read_argument (tree exp
, unsigned int index
)
8613 return expand_normal (CALL_EXPR_ARG (exp
, index
));
8616 /* Like frv_read_argument, but interpret the argument as the number
8617 of an IACC register and return a (reg:MODE ...) rtx for it. */
8620 frv_read_iacc_argument (machine_mode mode
, tree call
,
8626 op
= frv_read_argument (call
, index
);
8627 if (GET_CODE (op
) != CONST_INT
8629 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8630 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8632 error ("invalid IACC argument");
8636 /* IACCs are implicit global registers. We set up this lazily to
8637 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8639 regno
= INTVAL (op
) + IACC_FIRST
;
8640 for (i
= 0; i
< hard_regno_nregs (regno
, mode
); i
++)
8641 global_regs
[regno
+ i
] = 1;
8643 return gen_rtx_REG (mode
, regno
);
8646 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8647 The instruction should require a constant operand of some sort. The
8648 function prints an error if OPVAL is not valid. */
8651 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8653 if (GET_CODE (opval
) != CONST_INT
)
8655 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8658 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8660 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8666 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8667 if it's not null, has the right mode, and satisfies operand 0's
8671 frv_legitimize_target (enum insn_code icode
, rtx target
)
8673 machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8676 || GET_MODE (target
) != mode
8677 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8678 return gen_reg_rtx (mode
);
8683 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8684 check whether ARG satisfies the operand's constraints. If it doesn't,
8685 copy ARG to a temporary register and return that. Otherwise return ARG
8689 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8691 machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8693 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8696 return copy_to_mode_reg (mode
, arg
);
8699 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8702 frv_volatile_memref (machine_mode mode
, rtx arg
)
8706 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8707 MEM_VOLATILE_P (mem
) = 1;
8711 /* Expand builtins that take a single, constant argument. At the moment,
8712 only MHDSETS falls into this category. */
8715 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8718 rtx op0
= frv_read_argument (call
, 0);
8720 if (! frv_check_constant_argument (icode
, 1, op0
))
8723 target
= frv_legitimize_target (icode
, target
);
8724 pat
= GEN_FCN (icode
) (target
, op0
);
8732 /* Expand builtins that take one operand. */
8735 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8738 rtx op0
= frv_read_argument (call
, 0);
8740 target
= frv_legitimize_target (icode
, target
);
8741 op0
= frv_legitimize_argument (icode
, 1, op0
);
8742 pat
= GEN_FCN (icode
) (target
, op0
);
8750 /* Expand builtins that take two operands. */
8753 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8756 rtx op0
= frv_read_argument (call
, 0);
8757 rtx op1
= frv_read_argument (call
, 1);
8759 target
= frv_legitimize_target (icode
, target
);
8760 op0
= frv_legitimize_argument (icode
, 1, op0
);
8761 op1
= frv_legitimize_argument (icode
, 2, op1
);
8762 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8770 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8774 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8777 rtx op0
= frv_read_argument (call
, 0);
8778 rtx op1
= frv_read_argument (call
, 1);
8781 target
= frv_legitimize_target (icode
, target
);
8782 op0
= frv_int_to_acc (icode
, 1, op0
);
8786 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8788 if (! frv_check_constant_argument (icode
, 2, op1
))
8792 op1
= frv_legitimize_argument (icode
, 2, op1
);
8794 op2
= frv_matching_accg_for_acc (op0
);
8795 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8803 /* Expand builtins that take two operands and the second is immediate. */
8806 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8809 rtx op0
= frv_read_argument (call
, 0);
8810 rtx op1
= frv_read_argument (call
, 1);
8812 if (! frv_check_constant_argument (icode
, 2, op1
))
8815 target
= frv_legitimize_target (icode
, target
);
8816 op0
= frv_legitimize_argument (icode
, 1, op0
);
8817 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8825 /* Expand builtins that take two operands, the first operand being a pointer to
8826 ints and return void. */
8829 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8832 rtx op0
= frv_read_argument (call
, 0);
8833 rtx op1
= frv_read_argument (call
, 1);
8834 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8837 if (GET_CODE (op0
) != MEM
)
8841 if (! offsettable_address_p (0, mode0
, op0
))
8843 reg
= gen_reg_rtx (Pmode
);
8844 emit_insn (gen_rtx_SET (reg
, op0
));
8847 op0
= gen_rtx_MEM (SImode
, reg
);
8850 addr
= XEXP (op0
, 0);
8851 if (! offsettable_address_p (0, mode0
, addr
))
8852 addr
= copy_to_mode_reg (Pmode
, op0
);
8854 op0
= change_address (op0
, V4SImode
, addr
);
8855 op1
= frv_legitimize_argument (icode
, 1, op1
);
8856 pat
= GEN_FCN (icode
) (op0
, op1
);
8864 /* Expand builtins that take two long operands and return void. */
8867 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
8870 rtx op0
= frv_read_argument (call
, 0);
8871 rtx op1
= frv_read_argument (call
, 1);
8873 op0
= frv_legitimize_argument (icode
, 1, op0
);
8874 op1
= frv_legitimize_argument (icode
, 1, op1
);
8875 pat
= GEN_FCN (icode
) (op0
, op1
);
8883 /* Expand prefetch builtins. These take a single address as argument. */
8886 frv_expand_prefetches (enum insn_code icode
, tree call
)
8889 rtx op0
= frv_read_argument (call
, 0);
8891 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
8899 /* Expand builtins that take three operands and return void. The first
8900 argument must be a constant that describes a pair or quad accumulators. A
8901 fourth argument is created that is the accumulator guard register that
8902 corresponds to the accumulator. */
8905 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
8908 rtx op0
= frv_read_argument (call
, 0);
8909 rtx op1
= frv_read_argument (call
, 1);
8910 rtx op2
= frv_read_argument (call
, 2);
8913 op0
= frv_int_to_acc (icode
, 0, op0
);
8917 op1
= frv_legitimize_argument (icode
, 1, op1
);
8918 op2
= frv_legitimize_argument (icode
, 2, op2
);
8919 op3
= frv_matching_accg_for_acc (op0
);
8920 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
8928 /* Expand builtins that perform accumulator-to-accumulator operations.
8929 These builtins take two accumulator numbers as argument and return
8933 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
8936 rtx op0
= frv_read_argument (call
, 0);
8937 rtx op1
= frv_read_argument (call
, 1);
8941 op0
= frv_int_to_acc (icode
, 0, op0
);
8945 op1
= frv_int_to_acc (icode
, 1, op1
);
8949 op2
= frv_matching_accg_for_acc (op0
);
8950 op3
= frv_matching_accg_for_acc (op1
);
8951 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
8959 /* Expand a __builtin_read* function. ICODE is the instruction code for the
8960 membar and TARGET_MODE is the mode that the loaded value should have. */
8963 frv_expand_load_builtin (enum insn_code icode
, machine_mode target_mode
,
8964 tree call
, rtx target
)
8966 rtx op0
= frv_read_argument (call
, 0);
8967 rtx cookie
= frv_io_address_cookie (op0
);
8969 if (target
== 0 || !REG_P (target
))
8970 target
= gen_reg_rtx (target_mode
);
8971 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
8972 convert_move (target
, op0
, 1);
8973 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
8974 cfun
->machine
->has_membar_p
= 1;
8978 /* Likewise __builtin_write* functions. */
8981 frv_expand_store_builtin (enum insn_code icode
, tree call
)
8983 rtx op0
= frv_read_argument (call
, 0);
8984 rtx op1
= frv_read_argument (call
, 1);
8985 rtx cookie
= frv_io_address_cookie (op0
);
8987 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
8988 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
8989 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
8990 cfun
->machine
->has_membar_p
= 1;
8994 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
8995 each argument forms one word of the two double-word input registers.
8996 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
8997 to put the return value. */
9000 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9002 enum insn_code icode
= CODE_FOR_mdpackh
;
9004 rtx arg1
= frv_read_argument (call
, 0);
9005 rtx arg2
= frv_read_argument (call
, 1);
9006 rtx arg3
= frv_read_argument (call
, 2);
9007 rtx arg4
= frv_read_argument (call
, 3);
9009 target
= frv_legitimize_target (icode
, target
);
9010 op0
= gen_reg_rtx (DImode
);
9011 op1
= gen_reg_rtx (DImode
);
9013 /* The high half of each word is not explicitly initialized, so indicate
9014 that the input operands are not live before this point. */
9018 /* Move each argument into the low half of its associated input word. */
9019 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9020 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9021 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9022 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9024 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9032 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9033 number as argument. */
9036 frv_expand_mclracc_builtin (tree call
)
9038 enum insn_code icode
= CODE_FOR_mclracc
;
9040 rtx op0
= frv_read_argument (call
, 0);
9042 op0
= frv_int_to_acc (icode
, 0, op0
);
9046 pat
= GEN_FCN (icode
) (op0
);
9053 /* Expand builtins that take no arguments. */
9056 frv_expand_noargs_builtin (enum insn_code icode
)
9058 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9065 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9066 number or accumulator guard number as argument and return an SI integer. */
9069 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9072 rtx target
= gen_reg_rtx (SImode
);
9073 rtx op0
= frv_read_argument (call
, 0);
9075 op0
= frv_int_to_acc (icode
, 1, op0
);
9079 pat
= GEN_FCN (icode
) (target
, op0
);
9087 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9088 accumulator guard as their first argument and an SImode value as their
9092 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9095 rtx op0
= frv_read_argument (call
, 0);
9096 rtx op1
= frv_read_argument (call
, 1);
9098 op0
= frv_int_to_acc (icode
, 0, op0
);
9102 op1
= frv_legitimize_argument (icode
, 1, op1
);
9103 pat
= GEN_FCN (icode
) (op0
, op1
);
9110 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9111 to move DImode values into and out of IACC0. */
9114 frv_split_iacc_move (rtx dest
, rtx src
)
9119 inner
= GET_MODE (dest
);
9120 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9121 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9122 simplify_gen_subreg (SImode
, src
, inner
, i
));
9125 /* Expand builtins. */
9128 frv_expand_builtin (tree exp
,
9130 rtx subtarget ATTRIBUTE_UNUSED
,
9131 machine_mode mode ATTRIBUTE_UNUSED
,
9132 int ignore ATTRIBUTE_UNUSED
)
9134 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9135 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9137 struct builtin_description
*d
;
9139 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9141 error ("media functions are not available unless -mmedia is used");
9147 case FRV_BUILTIN_MCOP1
:
9148 case FRV_BUILTIN_MCOP2
:
9149 case FRV_BUILTIN_MDUNPACKH
:
9150 case FRV_BUILTIN_MBTOHE
:
9151 if (! TARGET_MEDIA_REV1
)
9153 error ("this media function is only available on the fr500");
9158 case FRV_BUILTIN_MQXMACHS
:
9159 case FRV_BUILTIN_MQXMACXHS
:
9160 case FRV_BUILTIN_MQMACXHS
:
9161 case FRV_BUILTIN_MADDACCS
:
9162 case FRV_BUILTIN_MSUBACCS
:
9163 case FRV_BUILTIN_MASACCS
:
9164 case FRV_BUILTIN_MDADDACCS
:
9165 case FRV_BUILTIN_MDSUBACCS
:
9166 case FRV_BUILTIN_MDASACCS
:
9167 case FRV_BUILTIN_MABSHS
:
9168 case FRV_BUILTIN_MDROTLI
:
9169 case FRV_BUILTIN_MCPLHI
:
9170 case FRV_BUILTIN_MCPLI
:
9171 case FRV_BUILTIN_MDCUTSSI
:
9172 case FRV_BUILTIN_MQSATHS
:
9173 case FRV_BUILTIN_MHSETLOS
:
9174 case FRV_BUILTIN_MHSETLOH
:
9175 case FRV_BUILTIN_MHSETHIS
:
9176 case FRV_BUILTIN_MHSETHIH
:
9177 case FRV_BUILTIN_MHDSETS
:
9178 case FRV_BUILTIN_MHDSETH
:
9179 if (! TARGET_MEDIA_REV2
)
9181 error ("this media function is only available on the fr400"
9187 case FRV_BUILTIN_SMASS
:
9188 case FRV_BUILTIN_SMSSS
:
9189 case FRV_BUILTIN_SMU
:
9190 case FRV_BUILTIN_ADDSS
:
9191 case FRV_BUILTIN_SUBSS
:
9192 case FRV_BUILTIN_SLASS
:
9193 case FRV_BUILTIN_SCUTSS
:
9194 case FRV_BUILTIN_IACCreadll
:
9195 case FRV_BUILTIN_IACCreadl
:
9196 case FRV_BUILTIN_IACCsetll
:
9197 case FRV_BUILTIN_IACCsetl
:
9198 if (!TARGET_FR405_BUILTINS
)
9200 error ("this builtin function is only available"
9201 " on the fr405 and fr450");
9206 case FRV_BUILTIN_PREFETCH
:
9207 if (!TARGET_FR500_FR550_BUILTINS
)
9209 error ("this builtin function is only available on the fr500"
9215 case FRV_BUILTIN_MQLCLRHS
:
9216 case FRV_BUILTIN_MQLMTHS
:
9217 case FRV_BUILTIN_MQSLLHI
:
9218 case FRV_BUILTIN_MQSRAHI
:
9219 if (!TARGET_MEDIA_FR450
)
9221 error ("this builtin function is only available on the fr450");
9230 /* Expand unique builtins. */
9234 case FRV_BUILTIN_MTRAP
:
9235 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9237 case FRV_BUILTIN_MCLRACC
:
9238 return frv_expand_mclracc_builtin (exp
);
9240 case FRV_BUILTIN_MCLRACCA
:
9242 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9244 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9246 case FRV_BUILTIN_MRDACC
:
9247 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9249 case FRV_BUILTIN_MRDACCG
:
9250 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9252 case FRV_BUILTIN_MWTACC
:
9253 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9255 case FRV_BUILTIN_MWTACCG
:
9256 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9258 case FRV_BUILTIN_MDPACKH
:
9259 return frv_expand_mdpackh_builtin (exp
, target
);
9261 case FRV_BUILTIN_IACCreadll
:
9263 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9264 if (target
== 0 || !REG_P (target
))
9265 target
= gen_reg_rtx (DImode
);
9266 frv_split_iacc_move (target
, src
);
9270 case FRV_BUILTIN_IACCreadl
:
9271 return frv_read_iacc_argument (SImode
, exp
, 0);
9273 case FRV_BUILTIN_IACCsetll
:
9275 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9276 rtx src
= frv_read_argument (exp
, 1);
9277 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9281 case FRV_BUILTIN_IACCsetl
:
9283 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9284 rtx src
= frv_read_argument (exp
, 1);
9285 emit_move_insn (dest
, force_reg (SImode
, src
));
9293 /* Expand groups of builtins. */
9295 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9296 if (d
->code
== fcode
)
9297 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9299 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9300 if (d
->code
== fcode
)
9301 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9303 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9304 if (d
->code
== fcode
)
9305 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9307 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9308 if (d
->code
== fcode
)
9309 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9311 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9312 if (d
->code
== fcode
)
9313 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9315 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9316 if (d
->code
== fcode
)
9317 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9319 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9320 if (d
->code
== fcode
)
9321 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9323 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9324 if (d
->code
== fcode
)
9325 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9327 for (i
= 0, d
= bdesc_int_void2arg
;
9328 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9329 if (d
->code
== fcode
)
9330 return frv_expand_int_void2arg (d
->icode
, exp
);
9332 for (i
= 0, d
= bdesc_prefetches
;
9333 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9334 if (d
->code
== fcode
)
9335 return frv_expand_prefetches (d
->icode
, exp
);
9337 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9338 if (d
->code
== fcode
)
9339 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9342 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9343 if (d
->code
== fcode
)
9344 return frv_expand_store_builtin (d
->icode
, exp
);
9350 frv_in_small_data_p (const_tree decl
)
9353 const char *section_name
;
9355 /* Don't apply the -G flag to internal compiler structures. We
9356 should leave such structures in the main data section, partly
9357 for efficiency and partly because the size of some of them
9358 (such as C++ typeinfos) is not known until later. */
9359 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9362 /* If we already know which section the decl should be in, see if
9363 it's a small data section. */
9364 section_name
= DECL_SECTION_NAME (decl
);
9367 if (frv_string_begins_with (section_name
, ".sdata"))
9369 if (frv_string_begins_with (section_name
, ".sbss"))
9374 size
= int_size_in_bytes (TREE_TYPE (decl
));
9375 if (size
> 0 && size
<= g_switch_value
)
9382 frv_rtx_costs (rtx x
,
9385 int opno ATTRIBUTE_UNUSED
,
9387 bool speed ATTRIBUTE_UNUSED
)
9389 int code
= GET_CODE (x
);
9391 if (outer_code
== MEM
)
9393 /* Don't differentiate between memory addresses. All the ones
9394 we accept have equal cost. */
9395 *total
= COSTS_N_INSNS (0);
9402 /* Make 12-bit integers really cheap. */
9403 if (IN_RANGE (INTVAL (x
), -2048, 2047))
9414 *total
= COSTS_N_INSNS (2);
9429 *total
= COSTS_N_INSNS (1);
9430 else if (mode
== DImode
)
9431 *total
= COSTS_N_INSNS (2);
9433 *total
= COSTS_N_INSNS (3);
9438 *total
= COSTS_N_INSNS (2);
9440 *total
= COSTS_N_INSNS (6); /* guess */
9447 *total
= COSTS_N_INSNS (18);
9451 *total
= COSTS_N_INSNS (3);
9460 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9462 switch_to_section (ctors_section
);
9463 assemble_align (POINTER_SIZE
);
9466 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9471 assemble_integer_with_op ("\t.picptr\t", symbol
);
9475 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9477 switch_to_section (dtors_section
);
9478 assemble_align (POINTER_SIZE
);
9481 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9486 assemble_integer_with_op ("\t.picptr\t", symbol
);
9489 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9492 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9493 int incoming ATTRIBUTE_UNUSED
)
9495 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9498 #define TLS_BIAS (2048 - 16)
9500 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9501 We need to emit DTP-relative relocations. */
9504 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9506 gcc_assert (size
== 4);
9507 fputs ("\t.picptr\ttlsmoff(", file
);
9508 /* We want the unbiased TLS offset, so add the bias to the
9509 expression, such that the implicit biasing cancels out. */
9510 output_addr_const (file
, plus_constant (Pmode
, x
, TLS_BIAS
));