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re PR rtl-optimization/39110 (Revision 143939 breaks bootstrap on Linux/ia64)
[official-gcc.git] / gcc / longlong.h
blob9bfd322d59f66bcd09ff6a955b46bee15626aff9
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5
6 This file is part of the GNU C Library.
7
8 The GNU C Library is free software; you can redistribute it and/or
9 modify it under the terms of the GNU Lesser General Public
10 License as published by the Free Software Foundation; either
11 version 2.1 of the License, or (at your option) any later version.
12
13 In addition to the permissions in the GNU Lesser General Public
14 License, the Free Software Foundation gives you unlimited
15 permission to link the compiled version of this file into
16 combinations with other programs, and to distribute those
17 combinations without any restriction coming from the use of this
18 file. (The Lesser General Public License restrictions do apply in
19 other respects; for example, they cover modification of the file,
20 and distribution when not linked into a combine executable.)
21
22 The GNU C Library is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 Lesser General Public License for more details.
26
27 You should have received a copy of the GNU Lesser General Public
28 License along with the GNU C Library; if not, write to the Free
29 Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
30 MA 02110-1301, USA. */
31
32 /* You have to define the following before including this file:
33
34 UWtype -- An unsigned type, default type for operations (typically a "word")
35 UHWtype -- An unsigned type, at least half the size of UWtype.
36 UDWtype -- An unsigned type, at least twice as large a UWtype
37 W_TYPE_SIZE -- size in bits of UWtype
38
39 UQItype -- Unsigned 8 bit type.
40 SItype, USItype -- Signed and unsigned 32 bit types.
41 DItype, UDItype -- Signed and unsigned 64 bit types.
42
43 On a 32 bit machine UWtype should typically be USItype;
44 on a 64 bit machine, UWtype should typically be UDItype. */
45
46 #define __BITS4 (W_TYPE_SIZE / 4)
47 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
48 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
49 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
50
51 #ifndef W_TYPE_SIZE
52 #define W_TYPE_SIZE 32
53 #define UWtype USItype
54 #define UHWtype USItype
55 #define UDWtype UDItype
56 #endif
57
58 /* Used in glibc only. */
59 #ifndef attribute_hidden
60 #define attribute_hidden
61 #endif
62
63 extern const UQItype __clz_tab[256] attribute_hidden;
64
65 /* Define auxiliary asm macros.
66
67 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
68 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
69 word product in HIGH_PROD and LOW_PROD.
70
71 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
72 UDWtype product. This is just a variant of umul_ppmm.
73
74 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
75 denominator) divides a UDWtype, composed by the UWtype integers
76 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
77 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
78 than DENOMINATOR for correct operation. If, in addition, the most
79 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
80 UDIV_NEEDS_NORMALIZATION is defined to 1.
81
82 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
83 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
84 is rounded towards 0.
85
86 5) count_leading_zeros(count, x) counts the number of zero-bits from the
87 msb to the first nonzero bit in the UWtype X. This is the number of
88 steps X needs to be shifted left to set the msb. Undefined for X == 0,
89 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
90
91 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
92 from the least significant end.
93
94 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
95 high_addend_2, low_addend_2) adds two UWtype integers, composed by
96 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
97 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
98 (i.e. carry out) is not stored anywhere, and is lost.
99
100 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
101 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
102 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
103 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
104 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
105 and is lost.
106
107 If any of these macros are left undefined for a particular CPU,
108 C macros are used. */
109
110 /* The CPUs come in alphabetical order below.
111
112 Please add support for more CPUs here, or improve the current support
113 for the CPUs below!
114 (E.g. WE32100, IBM360.) */
115
116 #if defined (__GNUC__) && !defined (NO_ASM)
117
118 /* We sometimes need to clobber "cc" with gcc2, but that would not be
119 understood by gcc1. Use cpp to avoid major code duplication. */
120 #if __GNUC__ < 2
121 #define __CLOBBER_CC
122 #define __AND_CLOBBER_CC
123 #else /* __GNUC__ >= 2 */
124 #define __CLOBBER_CC : "cc"
125 #define __AND_CLOBBER_CC , "cc"
126 #endif /* __GNUC__ < 2 */
127
128 #if defined (__alpha) && W_TYPE_SIZE == 64
129 #define umul_ppmm(ph, pl, m0, m1) \
130 do { \
131 UDItype __m0 = (m0), __m1 = (m1); \
132 (ph) = __builtin_alpha_umulh (__m0, __m1); \
133 (pl) = __m0 * __m1; \
134 } while (0)
135 #define UMUL_TIME 46
136 #ifndef LONGLONG_STANDALONE
137 #define udiv_qrnnd(q, r, n1, n0, d) \
138 do { UDItype __r; \
139 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
140 (r) = __r; \
141 } while (0)
142 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
143 #define UDIV_TIME 220
144 #endif /* LONGLONG_STANDALONE */
145 #ifdef __alpha_cix__
146 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
147 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
148 #define COUNT_LEADING_ZEROS_0 64
149 #else
150 #define count_leading_zeros(COUNT,X) \
151 do { \
152 UDItype __xr = (X), __t, __a; \
153 __t = __builtin_alpha_cmpbge (0, __xr); \
154 __a = __clz_tab[__t ^ 0xff] - 1; \
155 __t = __builtin_alpha_extbl (__xr, __a); \
156 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
157 } while (0)
158 #define count_trailing_zeros(COUNT,X) \
159 do { \
160 UDItype __xr = (X), __t, __a; \
161 __t = __builtin_alpha_cmpbge (0, __xr); \
162 __t = ~__t & -~__t; \
163 __a = ((__t & 0xCC) != 0) * 2; \
164 __a += ((__t & 0xF0) != 0) * 4; \
165 __a += ((__t & 0xAA) != 0); \
166 __t = __builtin_alpha_extbl (__xr, __a); \
167 __a <<= 3; \
168 __t &= -__t; \
169 __a += ((__t & 0xCC) != 0) * 2; \
170 __a += ((__t & 0xF0) != 0) * 4; \
171 __a += ((__t & 0xAA) != 0); \
172 (COUNT) = __a; \
173 } while (0)
174 #endif /* __alpha_cix__ */
175 #endif /* __alpha */
176
177 #if defined (__arc__) && W_TYPE_SIZE == 32
178 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
179 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
180 : "=r" ((USItype) (sh)), \
181 "=&r" ((USItype) (sl)) \
182 : "%r" ((USItype) (ah)), \
183 "rIJ" ((USItype) (bh)), \
184 "%r" ((USItype) (al)), \
185 "rIJ" ((USItype) (bl)))
186 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
187 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
188 : "=r" ((USItype) (sh)), \
189 "=&r" ((USItype) (sl)) \
190 : "r" ((USItype) (ah)), \
191 "rIJ" ((USItype) (bh)), \
192 "r" ((USItype) (al)), \
193 "rIJ" ((USItype) (bl)))
194 /* Call libgcc routine. */
195 #define umul_ppmm(w1, w0, u, v) \
196 do { \
197 DWunion __w; \
198 __w.ll = __umulsidi3 (u, v); \
199 w1 = __w.s.high; \
200 w0 = __w.s.low; \
201 } while (0)
202 #define __umulsidi3 __umulsidi3
203 UDItype __umulsidi3 (USItype, USItype);
204 #endif
205
206 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
207 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
208 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
209 : "=r" ((USItype) (sh)), \
210 "=&r" ((USItype) (sl)) \
211 : "%r" ((USItype) (ah)), \
212 "rI" ((USItype) (bh)), \
213 "%r" ((USItype) (al)), \
214 "rI" ((USItype) (bl)) __CLOBBER_CC)
215 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
216 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
217 : "=r" ((USItype) (sh)), \
218 "=&r" ((USItype) (sl)) \
219 : "r" ((USItype) (ah)), \
220 "rI" ((USItype) (bh)), \
221 "r" ((USItype) (al)), \
222 "rI" ((USItype) (bl)) __CLOBBER_CC)
223 #define umul_ppmm(xh, xl, a, b) \
224 {register USItype __t0, __t1, __t2; \
225 __asm__ ("%@ Inlined umul_ppmm\n" \
226 " mov %2, %5, lsr #16\n" \
227 " mov %0, %6, lsr #16\n" \
228 " bic %3, %5, %2, lsl #16\n" \
229 " bic %4, %6, %0, lsl #16\n" \
230 " mul %1, %3, %4\n" \
231 " mul %4, %2, %4\n" \
232 " mul %3, %0, %3\n" \
233 " mul %0, %2, %0\n" \
234 " adds %3, %4, %3\n" \
235 " addcs %0, %0, #65536\n" \
236 " adds %1, %1, %3, lsl #16\n" \
237 " adc %0, %0, %3, lsr #16" \
238 : "=&r" ((USItype) (xh)), \
239 "=r" ((USItype) (xl)), \
240 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
241 : "r" ((USItype) (a)), \
242 "r" ((USItype) (b)) __CLOBBER_CC );}
243 #define UMUL_TIME 20
244 #define UDIV_TIME 100
245 #endif /* __arm__ */
246
247 #if defined(__arm__)
248 /* Let gcc decide how best to implement count_leading_zeros. */
249 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
250 #define COUNT_LEADING_ZEROS_0 32
251 #endif
252
253 #if defined (__CRIS__) && __CRIS_arch_version >= 3
254 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
255 #if __CRIS_arch_version >= 8
256 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
257 #endif
258 #endif /* __CRIS__ */
259
260 #if defined (__hppa) && W_TYPE_SIZE == 32
261 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
262 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
263 : "=r" ((USItype) (sh)), \
264 "=&r" ((USItype) (sl)) \
265 : "%rM" ((USItype) (ah)), \
266 "rM" ((USItype) (bh)), \
267 "%rM" ((USItype) (al)), \
268 "rM" ((USItype) (bl)))
269 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
270 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
271 : "=r" ((USItype) (sh)), \
272 "=&r" ((USItype) (sl)) \
273 : "rM" ((USItype) (ah)), \
274 "rM" ((USItype) (bh)), \
275 "rM" ((USItype) (al)), \
276 "rM" ((USItype) (bl)))
277 #if defined (_PA_RISC1_1)
278 #define umul_ppmm(w1, w0, u, v) \
279 do { \
280 union \
281 { \
282 UDItype __f; \
283 struct {USItype __w1, __w0;} __w1w0; \
284 } __t; \
285 __asm__ ("xmpyu %1,%2,%0" \
286 : "=x" (__t.__f) \
287 : "x" ((USItype) (u)), \
288 "x" ((USItype) (v))); \
289 (w1) = __t.__w1w0.__w1; \
290 (w0) = __t.__w1w0.__w0; \
291 } while (0)
292 #define UMUL_TIME 8
293 #else
294 #define UMUL_TIME 30
295 #endif
296 #define UDIV_TIME 40
297 #define count_leading_zeros(count, x) \
298 do { \
299 USItype __tmp; \
300 __asm__ ( \
301 "ldi 1,%0\n" \
302 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
303 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
304 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
305 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
306 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
307 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
308 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
309 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
310 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
311 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
312 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
313 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
314 " extru %1,30,1,%1 ; Extract bit 1.\n" \
315 " sub %0,%1,%0 ; Subtract it.\n" \
316 : "=r" (count), "=r" (__tmp) : "1" (x)); \
317 } while (0)
318 #endif
319
320 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
321 #define smul_ppmm(xh, xl, m0, m1) \
322 do { \
323 union {DItype __ll; \
324 struct {USItype __h, __l;} __i; \
325 } __x; \
326 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
327 : "=&r" (__x.__ll) \
328 : "r" (m0), "r" (m1)); \
329 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
330 } while (0)
331 #define sdiv_qrnnd(q, r, n1, n0, d) \
332 do { \
333 union {DItype __ll; \
334 struct {USItype __h, __l;} __i; \
335 } __x; \
336 __x.__i.__h = n1; __x.__i.__l = n0; \
337 __asm__ ("dr %0,%2" \
338 : "=r" (__x.__ll) \
339 : "0" (__x.__ll), "r" (d)); \
340 (q) = __x.__i.__l; (r) = __x.__i.__h; \
341 } while (0)
342 #endif
343
344 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
345 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
346 __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
347 : "=r" ((USItype) (sh)), \
348 "=&r" ((USItype) (sl)) \
349 : "%0" ((USItype) (ah)), \
350 "g" ((USItype) (bh)), \
351 "%1" ((USItype) (al)), \
352 "g" ((USItype) (bl)))
353 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
354 __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
355 : "=r" ((USItype) (sh)), \
356 "=&r" ((USItype) (sl)) \
357 : "0" ((USItype) (ah)), \
358 "g" ((USItype) (bh)), \
359 "1" ((USItype) (al)), \
360 "g" ((USItype) (bl)))
361 #define umul_ppmm(w1, w0, u, v) \
362 __asm__ ("mul{l} %3" \
363 : "=a" ((USItype) (w0)), \
364 "=d" ((USItype) (w1)) \
365 : "%0" ((USItype) (u)), \
366 "rm" ((USItype) (v)))
367 #define udiv_qrnnd(q, r, n1, n0, dv) \
368 __asm__ ("div{l} %4" \
369 : "=a" ((USItype) (q)), \
370 "=d" ((USItype) (r)) \
371 : "0" ((USItype) (n0)), \
372 "1" ((USItype) (n1)), \
373 "rm" ((USItype) (dv)))
374 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
375 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
376 #define UMUL_TIME 40
377 #define UDIV_TIME 40
378 #endif /* 80x86 */
379
380 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
381 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
382 __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
383 : "=r" ((UDItype) (sh)), \
384 "=&r" ((UDItype) (sl)) \
385 : "%0" ((UDItype) (ah)), \
386 "rme" ((UDItype) (bh)), \
387 "%1" ((UDItype) (al)), \
388 "rme" ((UDItype) (bl)))
389 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
390 __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
391 : "=r" ((UDItype) (sh)), \
392 "=&r" ((UDItype) (sl)) \
393 : "0" ((UDItype) (ah)), \
394 "rme" ((UDItype) (bh)), \
395 "1" ((UDItype) (al)), \
396 "rme" ((UDItype) (bl)))
397 #define umul_ppmm(w1, w0, u, v) \
398 __asm__ ("mul{q} %3" \
399 : "=a" ((UDItype) (w0)), \
400 "=d" ((UDItype) (w1)) \
401 : "%0" ((UDItype) (u)), \
402 "rm" ((UDItype) (v)))
403 #define udiv_qrnnd(q, r, n1, n0, dv) \
404 __asm__ ("div{q} %4" \
405 : "=a" ((UDItype) (q)), \
406 "=d" ((UDItype) (r)) \
407 : "0" ((UDItype) (n0)), \
408 "1" ((UDItype) (n1)), \
409 "rm" ((UDItype) (dv)))
410 #define count_leading_zeros(count, x) ((count) = __builtin_clzl (x))
411 #define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x))
412 #define UMUL_TIME 40
413 #define UDIV_TIME 40
414 #endif /* x86_64 */
415
416 #if defined (__i960__) && W_TYPE_SIZE == 32
417 #define umul_ppmm(w1, w0, u, v) \
418 ({union {UDItype __ll; \
419 struct {USItype __l, __h;} __i; \
420 } __xx; \
421 __asm__ ("emul %2,%1,%0" \
422 : "=d" (__xx.__ll) \
423 : "%dI" ((USItype) (u)), \
424 "dI" ((USItype) (v))); \
425 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
426 #define __umulsidi3(u, v) \
427 ({UDItype __w; \
428 __asm__ ("emul %2,%1,%0" \
429 : "=d" (__w) \
430 : "%dI" ((USItype) (u)), \
431 "dI" ((USItype) (v))); \
432 __w; })
433 #endif /* __i960__ */
434
435 #if defined (__M32R__) && W_TYPE_SIZE == 32
436 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
437 /* The cmp clears the condition bit. */ \
438 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
439 : "=r" ((USItype) (sh)), \
440 "=&r" ((USItype) (sl)) \
441 : "0" ((USItype) (ah)), \
442 "r" ((USItype) (bh)), \
443 "1" ((USItype) (al)), \
444 "r" ((USItype) (bl)) \
445 : "cbit")
446 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
447 /* The cmp clears the condition bit. */ \
448 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
449 : "=r" ((USItype) (sh)), \
450 "=&r" ((USItype) (sl)) \
451 : "0" ((USItype) (ah)), \
452 "r" ((USItype) (bh)), \
453 "1" ((USItype) (al)), \
454 "r" ((USItype) (bl)) \
455 : "cbit")
456 #endif /* __M32R__ */
457
458 #if defined (__mc68000__) && W_TYPE_SIZE == 32
459 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
460 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
461 : "=d" ((USItype) (sh)), \
462 "=&d" ((USItype) (sl)) \
463 : "%0" ((USItype) (ah)), \
464 "d" ((USItype) (bh)), \
465 "%1" ((USItype) (al)), \
466 "g" ((USItype) (bl)))
467 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
468 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
469 : "=d" ((USItype) (sh)), \
470 "=&d" ((USItype) (sl)) \
471 : "0" ((USItype) (ah)), \
472 "d" ((USItype) (bh)), \
473 "1" ((USItype) (al)), \
474 "g" ((USItype) (bl)))
475
476 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
477 #if (defined (__mc68020__) && !defined (__mc68060__))
478 #define umul_ppmm(w1, w0, u, v) \
479 __asm__ ("mulu%.l %3,%1:%0" \
480 : "=d" ((USItype) (w0)), \
481 "=d" ((USItype) (w1)) \
482 : "%0" ((USItype) (u)), \
483 "dmi" ((USItype) (v)))
484 #define UMUL_TIME 45
485 #define udiv_qrnnd(q, r, n1, n0, d) \
486 __asm__ ("divu%.l %4,%1:%0" \
487 : "=d" ((USItype) (q)), \
488 "=d" ((USItype) (r)) \
489 : "0" ((USItype) (n0)), \
490 "1" ((USItype) (n1)), \
491 "dmi" ((USItype) (d)))
492 #define UDIV_TIME 90
493 #define sdiv_qrnnd(q, r, n1, n0, d) \
494 __asm__ ("divs%.l %4,%1:%0" \
495 : "=d" ((USItype) (q)), \
496 "=d" ((USItype) (r)) \
497 : "0" ((USItype) (n0)), \
498 "1" ((USItype) (n1)), \
499 "dmi" ((USItype) (d)))
500
501 #elif defined (__mcoldfire__) /* not mc68020 */
502
503 #define umul_ppmm(xh, xl, a, b) \
504 __asm__ ("| Inlined umul_ppmm\n" \
505 " move%.l %2,%/d0\n" \
506 " move%.l %3,%/d1\n" \
507 " move%.l %/d0,%/d2\n" \
508 " swap %/d0\n" \
509 " move%.l %/d1,%/d3\n" \
510 " swap %/d1\n" \
511 " move%.w %/d2,%/d4\n" \
512 " mulu %/d3,%/d4\n" \
513 " mulu %/d1,%/d2\n" \
514 " mulu %/d0,%/d3\n" \
515 " mulu %/d0,%/d1\n" \
516 " move%.l %/d4,%/d0\n" \
517 " clr%.w %/d0\n" \
518 " swap %/d0\n" \
519 " add%.l %/d0,%/d2\n" \
520 " add%.l %/d3,%/d2\n" \
521 " jcc 1f\n" \
522 " add%.l %#65536,%/d1\n" \
523 "1: swap %/d2\n" \
524 " moveq %#0,%/d0\n" \
525 " move%.w %/d2,%/d0\n" \
526 " move%.w %/d4,%/d2\n" \
527 " move%.l %/d2,%1\n" \
528 " add%.l %/d1,%/d0\n" \
529 " move%.l %/d0,%0" \
530 : "=g" ((USItype) (xh)), \
531 "=g" ((USItype) (xl)) \
532 : "g" ((USItype) (a)), \
533 "g" ((USItype) (b)) \
534 : "d0", "d1", "d2", "d3", "d4")
535 #define UMUL_TIME 100
536 #define UDIV_TIME 400
537 #else /* not ColdFire */
538 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
539 #define umul_ppmm(xh, xl, a, b) \
540 __asm__ ("| Inlined umul_ppmm\n" \
541 " move%.l %2,%/d0\n" \
542 " move%.l %3,%/d1\n" \
543 " move%.l %/d0,%/d2\n" \
544 " swap %/d0\n" \
545 " move%.l %/d1,%/d3\n" \
546 " swap %/d1\n" \
547 " move%.w %/d2,%/d4\n" \
548 " mulu %/d3,%/d4\n" \
549 " mulu %/d1,%/d2\n" \
550 " mulu %/d0,%/d3\n" \
551 " mulu %/d0,%/d1\n" \
552 " move%.l %/d4,%/d0\n" \
553 " eor%.w %/d0,%/d0\n" \
554 " swap %/d0\n" \
555 " add%.l %/d0,%/d2\n" \
556 " add%.l %/d3,%/d2\n" \
557 " jcc 1f\n" \
558 " add%.l %#65536,%/d1\n" \
559 "1: swap %/d2\n" \
560 " moveq %#0,%/d0\n" \
561 " move%.w %/d2,%/d0\n" \
562 " move%.w %/d4,%/d2\n" \
563 " move%.l %/d2,%1\n" \
564 " add%.l %/d1,%/d0\n" \
565 " move%.l %/d0,%0" \
566 : "=g" ((USItype) (xh)), \
567 "=g" ((USItype) (xl)) \
568 : "g" ((USItype) (a)), \
569 "g" ((USItype) (b)) \
570 : "d0", "d1", "d2", "d3", "d4")
571 #define UMUL_TIME 100
572 #define UDIV_TIME 400
573
574 #endif /* not mc68020 */
575
576 /* The '020, '030, '040 and '060 have bitfield insns.
577 cpu32 disguises as a 68020, but lacks them. */
578 #if defined (__mc68020__) && !defined (__mcpu32__)
579 #define count_leading_zeros(count, x) \
580 __asm__ ("bfffo %1{%b2:%b2},%0" \
581 : "=d" ((USItype) (count)) \
582 : "od" ((USItype) (x)), "n" (0))
583 /* Some ColdFire architectures have a ff1 instruction supported via
584 __builtin_clz. */
585 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
586 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
587 #define COUNT_LEADING_ZEROS_0 32
588 #endif
589 #endif /* mc68000 */
590
591 #if defined (__m88000__) && W_TYPE_SIZE == 32
592 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
593 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
594 : "=r" ((USItype) (sh)), \
595 "=&r" ((USItype) (sl)) \
596 : "%rJ" ((USItype) (ah)), \
597 "rJ" ((USItype) (bh)), \
598 "%rJ" ((USItype) (al)), \
599 "rJ" ((USItype) (bl)))
600 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
601 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
602 : "=r" ((USItype) (sh)), \
603 "=&r" ((USItype) (sl)) \
604 : "rJ" ((USItype) (ah)), \
605 "rJ" ((USItype) (bh)), \
606 "rJ" ((USItype) (al)), \
607 "rJ" ((USItype) (bl)))
608 #define count_leading_zeros(count, x) \
609 do { \
610 USItype __cbtmp; \
611 __asm__ ("ff1 %0,%1" \
612 : "=r" (__cbtmp) \
613 : "r" ((USItype) (x))); \
614 (count) = __cbtmp ^ 31; \
615 } while (0)
616 #define COUNT_LEADING_ZEROS_0 63 /* sic */
617 #if defined (__mc88110__)
618 #define umul_ppmm(wh, wl, u, v) \
619 do { \
620 union {UDItype __ll; \
621 struct {USItype __h, __l;} __i; \
622 } __xx; \
623 __asm__ ("mulu.d %0,%1,%2" \
624 : "=r" (__xx.__ll) \
625 : "r" ((USItype) (u)), \
626 "r" ((USItype) (v))); \
627 (wh) = __xx.__i.__h; \
628 (wl) = __xx.__i.__l; \
629 } while (0)
630 #define udiv_qrnnd(q, r, n1, n0, d) \
631 ({union {UDItype __ll; \
632 struct {USItype __h, __l;} __i; \
633 } __xx; \
634 USItype __q; \
635 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
636 __asm__ ("divu.d %0,%1,%2" \
637 : "=r" (__q) \
638 : "r" (__xx.__ll), \
639 "r" ((USItype) (d))); \
640 (r) = (n0) - __q * (d); (q) = __q; })
641 #define UMUL_TIME 5
642 #define UDIV_TIME 25
643 #else
644 #define UMUL_TIME 17
645 #define UDIV_TIME 150
646 #endif /* __mc88110__ */
647 #endif /* __m88000__ */
648
649 #if defined (__mips__) && W_TYPE_SIZE == 32
650 #define umul_ppmm(w1, w0, u, v) \
651 do { \
652 UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
653 (w1) = (USItype) (__x >> 32); \
654 (w0) = (USItype) (__x); \
655 } while (0)
656 #define UMUL_TIME 10
657 #define UDIV_TIME 100
658
659 #if (__mips == 32 || __mips == 64) && ! __mips16
660 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
661 #define COUNT_LEADING_ZEROS_0 32
662 #endif
663 #endif /* __mips__ */
664
665 #if defined (__ns32000__) && W_TYPE_SIZE == 32
666 #define umul_ppmm(w1, w0, u, v) \
667 ({union {UDItype __ll; \
668 struct {USItype __l, __h;} __i; \
669 } __xx; \
670 __asm__ ("meid %2,%0" \
671 : "=g" (__xx.__ll) \
672 : "%0" ((USItype) (u)), \
673 "g" ((USItype) (v))); \
674 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
675 #define __umulsidi3(u, v) \
676 ({UDItype __w; \
677 __asm__ ("meid %2,%0" \
678 : "=g" (__w) \
679 : "%0" ((USItype) (u)), \
680 "g" ((USItype) (v))); \
681 __w; })
682 #define udiv_qrnnd(q, r, n1, n0, d) \
683 ({union {UDItype __ll; \
684 struct {USItype __l, __h;} __i; \
685 } __xx; \
686 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
687 __asm__ ("deid %2,%0" \
688 : "=g" (__xx.__ll) \
689 : "0" (__xx.__ll), \
690 "g" ((USItype) (d))); \
691 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
692 #define count_trailing_zeros(count,x) \
693 do { \
694 __asm__ ("ffsd %2,%0" \
695 : "=r" ((USItype) (count)) \
696 : "0" ((USItype) 0), \
697 "r" ((USItype) (x))); \
698 } while (0)
699 #endif /* __ns32000__ */
700
701 /* FIXME: We should test _IBMR2 here when we add assembly support for the
702 system vendor compilers.
703 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
704 enough, since that hits ARM and m68k too. */
705 #if (defined (_ARCH_PPC) /* AIX */ \
706 || defined (_ARCH_PWR) /* AIX */ \
707 || defined (_ARCH_COM) /* AIX */ \
708 || defined (__powerpc__) /* gcc */ \
709 || defined (__POWERPC__) /* BEOS */ \
710 || defined (__ppc__) /* Darwin */ \
711 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
712 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
713 && CPU_FAMILY == PPC) \
714 ) && W_TYPE_SIZE == 32
715 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
716 do { \
717 if (__builtin_constant_p (bh) && (bh) == 0) \
718 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
719 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
720 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
721 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
722 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
723 else \
724 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
725 : "=r" (sh), "=&r" (sl) \
726 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
727 } while (0)
728 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
729 do { \
730 if (__builtin_constant_p (ah) && (ah) == 0) \
731 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
732 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
733 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
734 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
735 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
736 else if (__builtin_constant_p (bh) && (bh) == 0) \
737 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
738 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
739 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
740 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
741 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
742 else \
743 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
744 : "=r" (sh), "=&r" (sl) \
745 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
746 } while (0)
747 #define count_leading_zeros(count, x) \
748 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
749 #define COUNT_LEADING_ZEROS_0 32
750 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
751 || defined (__ppc__) \
752 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
753 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
754 && CPU_FAMILY == PPC)
755 #define umul_ppmm(ph, pl, m0, m1) \
756 do { \
757 USItype __m0 = (m0), __m1 = (m1); \
758 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
759 (pl) = __m0 * __m1; \
760 } while (0)
761 #define UMUL_TIME 15
762 #define smul_ppmm(ph, pl, m0, m1) \
763 do { \
764 SItype __m0 = (m0), __m1 = (m1); \
765 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
766 (pl) = __m0 * __m1; \
767 } while (0)
768 #define SMUL_TIME 14
769 #define UDIV_TIME 120
770 #elif defined (_ARCH_PWR)
771 #define UMUL_TIME 8
772 #define smul_ppmm(xh, xl, m0, m1) \
773 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
774 #define SMUL_TIME 4
775 #define sdiv_qrnnd(q, r, nh, nl, d) \
776 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
777 #define UDIV_TIME 100
778 #endif
779 #endif /* 32-bit POWER architecture variants. */
780
781 /* We should test _IBMR2 here when we add assembly support for the system
782 vendor compilers. */
783 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
784 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
785 do { \
786 if (__builtin_constant_p (bh) && (bh) == 0) \
787 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
788 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
789 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
790 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
791 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
792 else \
793 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
794 : "=r" (sh), "=&r" (sl) \
795 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
796 } while (0)
797 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
798 do { \
799 if (__builtin_constant_p (ah) && (ah) == 0) \
800 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
801 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
802 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
803 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
804 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
805 else if (__builtin_constant_p (bh) && (bh) == 0) \
806 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
807 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
808 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
809 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
810 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
811 else \
812 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
813 : "=r" (sh), "=&r" (sl) \
814 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
815 } while (0)
816 #define count_leading_zeros(count, x) \
817 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
818 #define COUNT_LEADING_ZEROS_0 64
819 #define umul_ppmm(ph, pl, m0, m1) \
820 do { \
821 UDItype __m0 = (m0), __m1 = (m1); \
822 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
823 (pl) = __m0 * __m1; \
824 } while (0)
825 #define UMUL_TIME 15
826 #define smul_ppmm(ph, pl, m0, m1) \
827 do { \
828 DItype __m0 = (m0), __m1 = (m1); \
829 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
830 (pl) = __m0 * __m1; \
831 } while (0)
832 #define SMUL_TIME 14 /* ??? */
833 #define UDIV_TIME 120 /* ??? */
834 #endif /* 64-bit PowerPC. */
835
836 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
837 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
838 __asm__ ("a %1,%5\n\tae %0,%3" \
839 : "=r" ((USItype) (sh)), \
840 "=&r" ((USItype) (sl)) \
841 : "%0" ((USItype) (ah)), \
842 "r" ((USItype) (bh)), \
843 "%1" ((USItype) (al)), \
844 "r" ((USItype) (bl)))
845 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
846 __asm__ ("s %1,%5\n\tse %0,%3" \
847 : "=r" ((USItype) (sh)), \
848 "=&r" ((USItype) (sl)) \
849 : "0" ((USItype) (ah)), \
850 "r" ((USItype) (bh)), \
851 "1" ((USItype) (al)), \
852 "r" ((USItype) (bl)))
853 #define umul_ppmm(ph, pl, m0, m1) \
854 do { \
855 USItype __m0 = (m0), __m1 = (m1); \
856 __asm__ ( \
857 "s r2,r2\n" \
858 " mts r10,%2\n" \
859 " m r2,%3\n" \
860 " m r2,%3\n" \
861 " m r2,%3\n" \
862 " m r2,%3\n" \
863 " m r2,%3\n" \
864 " m r2,%3\n" \
865 " m r2,%3\n" \
866 " m r2,%3\n" \
867 " m r2,%3\n" \
868 " m r2,%3\n" \
869 " m r2,%3\n" \
870 " m r2,%3\n" \
871 " m r2,%3\n" \
872 " m r2,%3\n" \
873 " m r2,%3\n" \
874 " m r2,%3\n" \
875 " cas %0,r2,r0\n" \
876 " mfs r10,%1" \
877 : "=r" ((USItype) (ph)), \
878 "=r" ((USItype) (pl)) \
879 : "%r" (__m0), \
880 "r" (__m1) \
881 : "r2"); \
882 (ph) += ((((SItype) __m0 >> 31) & __m1) \
883 + (((SItype) __m1 >> 31) & __m0)); \
884 } while (0)
885 #define UMUL_TIME 20
886 #define UDIV_TIME 200
887 #define count_leading_zeros(count, x) \
888 do { \
889 if ((x) >= 0x10000) \
890 __asm__ ("clz %0,%1" \
891 : "=r" ((USItype) (count)) \
892 : "r" ((USItype) (x) >> 16)); \
893 else \
894 { \
895 __asm__ ("clz %0,%1" \
896 : "=r" ((USItype) (count)) \
897 : "r" ((USItype) (x))); \
898 (count) += 16; \
899 } \
900 } while (0)
901 #endif
902
903 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
904 #ifndef __sh1__
905 #define umul_ppmm(w1, w0, u, v) \
906 __asm__ ( \
907 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
908 : "=r<" ((USItype)(w1)), \
909 "=r<" ((USItype)(w0)) \
910 : "r" ((USItype)(u)), \
911 "r" ((USItype)(v)) \
912 : "macl", "mach")
913 #define UMUL_TIME 5
914 #endif
915
916 /* This is the same algorithm as __udiv_qrnnd_c. */
917 #define UDIV_NEEDS_NORMALIZATION 1
918
919 #define udiv_qrnnd(q, r, n1, n0, d) \
920 do { \
921 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
922 __attribute__ ((visibility ("hidden"))); \
923 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
924 __asm__ ( \
925 "mov%M4 %4,r5\n" \
926 " swap.w %3,r4\n" \
927 " swap.w r5,r6\n" \
928 " jsr @%5\n" \
929 " shll16 r6\n" \
930 " swap.w r4,r4\n" \
931 " jsr @%5\n" \
932 " swap.w r1,%0\n" \
933 " or r1,%0" \
934 : "=r" (q), "=&z" (r) \
935 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
936 : "r1", "r2", "r4", "r5", "r6", "pr"); \
937 } while (0)
938
939 #define UDIV_TIME 80
940
941 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
942 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
943 : "=r" (sh), "=r" (sl) \
944 : "0" (ah), "1" (al), "r" (bh), "r" (bl))
945
946 #endif /* __sh__ */
947
948 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
949 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
950 #define count_leading_zeros(count, x) \
951 do \
952 { \
953 UDItype x_ = (USItype)(x); \
954 SItype c_; \
955 \
956 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
957 (count) = c_ - 31; \
958 } \
959 while (0)
960 #define COUNT_LEADING_ZEROS_0 32
961 #endif
962
963 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
964 && W_TYPE_SIZE == 32
965 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
966 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
967 : "=r" ((USItype) (sh)), \
968 "=&r" ((USItype) (sl)) \
969 : "%rJ" ((USItype) (ah)), \
970 "rI" ((USItype) (bh)), \
971 "%rJ" ((USItype) (al)), \
972 "rI" ((USItype) (bl)) \
973 __CLOBBER_CC)
974 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
975 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
976 : "=r" ((USItype) (sh)), \
977 "=&r" ((USItype) (sl)) \
978 : "rJ" ((USItype) (ah)), \
979 "rI" ((USItype) (bh)), \
980 "rJ" ((USItype) (al)), \
981 "rI" ((USItype) (bl)) \
982 __CLOBBER_CC)
983 #if defined (__sparc_v8__)
984 #define umul_ppmm(w1, w0, u, v) \
985 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
986 : "=r" ((USItype) (w1)), \
987 "=r" ((USItype) (w0)) \
988 : "r" ((USItype) (u)), \
989 "r" ((USItype) (v)))
990 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
991 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
992 : "=&r" ((USItype) (__q)), \
993 "=&r" ((USItype) (__r)) \
994 : "r" ((USItype) (__n1)), \
995 "r" ((USItype) (__n0)), \
996 "r" ((USItype) (__d)))
997 #else
998 #if defined (__sparclite__)
999 /* This has hardware multiply but not divide. It also has two additional
1000 instructions scan (ffs from high bit) and divscc. */
1001 #define umul_ppmm(w1, w0, u, v) \
1002 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1003 : "=r" ((USItype) (w1)), \
1004 "=r" ((USItype) (w0)) \
1005 : "r" ((USItype) (u)), \
1006 "r" ((USItype) (v)))
1007 #define udiv_qrnnd(q, r, n1, n0, d) \
1008 __asm__ ("! Inlined udiv_qrnnd\n" \
1009 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
1010 " tst %%g0\n" \
1011 " divscc %3,%4,%%g1\n" \
1012 " divscc %%g1,%4,%%g1\n" \
1013 " divscc %%g1,%4,%%g1\n" \
1014 " divscc %%g1,%4,%%g1\n" \
1015 " divscc %%g1,%4,%%g1\n" \
1016 " divscc %%g1,%4,%%g1\n" \
1017 " divscc %%g1,%4,%%g1\n" \
1018 " divscc %%g1,%4,%%g1\n" \
1019 " divscc %%g1,%4,%%g1\n" \
1020 " divscc %%g1,%4,%%g1\n" \
1021 " divscc %%g1,%4,%%g1\n" \
1022 " divscc %%g1,%4,%%g1\n" \
1023 " divscc %%g1,%4,%%g1\n" \
1024 " divscc %%g1,%4,%%g1\n" \
1025 " divscc %%g1,%4,%%g1\n" \
1026 " divscc %%g1,%4,%%g1\n" \
1027 " divscc %%g1,%4,%%g1\n" \
1028 " divscc %%g1,%4,%%g1\n" \
1029 " divscc %%g1,%4,%%g1\n" \
1030 " divscc %%g1,%4,%%g1\n" \
1031 " divscc %%g1,%4,%%g1\n" \
1032 " divscc %%g1,%4,%%g1\n" \
1033 " divscc %%g1,%4,%%g1\n" \
1034 " divscc %%g1,%4,%%g1\n" \
1035 " divscc %%g1,%4,%%g1\n" \
1036 " divscc %%g1,%4,%%g1\n" \
1037 " divscc %%g1,%4,%%g1\n" \
1038 " divscc %%g1,%4,%%g1\n" \
1039 " divscc %%g1,%4,%%g1\n" \
1040 " divscc %%g1,%4,%%g1\n" \
1041 " divscc %%g1,%4,%%g1\n" \
1042 " divscc %%g1,%4,%0\n" \
1043 " rd %%y,%1\n" \
1044 " bl,a 1f\n" \
1045 " add %1,%4,%1\n" \
1046 "1: ! End of inline udiv_qrnnd" \
1047 : "=r" ((USItype) (q)), \
1048 "=r" ((USItype) (r)) \
1049 : "r" ((USItype) (n1)), \
1050 "r" ((USItype) (n0)), \
1051 "rI" ((USItype) (d)) \
1052 : "g1" __AND_CLOBBER_CC)
1053 #define UDIV_TIME 37
1054 #define count_leading_zeros(count, x) \
1055 do { \
1056 __asm__ ("scan %1,1,%0" \
1057 : "=r" ((USItype) (count)) \
1058 : "r" ((USItype) (x))); \
1059 } while (0)
1060 /* Early sparclites return 63 for an argument of 0, but they warn that future
1061 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1062 undefined. */
1063 #else
1064 /* SPARC without integer multiplication and divide instructions.
1065 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1066 #define umul_ppmm(w1, w0, u, v) \
1067 __asm__ ("! Inlined umul_ppmm\n" \
1068 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1069 " sra %3,31,%%o5 ! Don't move this insn\n" \
1070 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1071 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1072 " mulscc %%g1,%3,%%g1\n" \
1073 " mulscc %%g1,%3,%%g1\n" \
1074 " mulscc %%g1,%3,%%g1\n" \
1075 " mulscc %%g1,%3,%%g1\n" \
1076 " mulscc %%g1,%3,%%g1\n" \
1077 " mulscc %%g1,%3,%%g1\n" \
1078 " mulscc %%g1,%3,%%g1\n" \
1079 " mulscc %%g1,%3,%%g1\n" \
1080 " mulscc %%g1,%3,%%g1\n" \
1081 " mulscc %%g1,%3,%%g1\n" \
1082 " mulscc %%g1,%3,%%g1\n" \
1083 " mulscc %%g1,%3,%%g1\n" \
1084 " mulscc %%g1,%3,%%g1\n" \
1085 " mulscc %%g1,%3,%%g1\n" \
1086 " mulscc %%g1,%3,%%g1\n" \
1087 " mulscc %%g1,%3,%%g1\n" \
1088 " mulscc %%g1,%3,%%g1\n" \
1089 " mulscc %%g1,%3,%%g1\n" \
1090 " mulscc %%g1,%3,%%g1\n" \
1091 " mulscc %%g1,%3,%%g1\n" \
1092 " mulscc %%g1,%3,%%g1\n" \
1093 " mulscc %%g1,%3,%%g1\n" \
1094 " mulscc %%g1,%3,%%g1\n" \
1095 " mulscc %%g1,%3,%%g1\n" \
1096 " mulscc %%g1,%3,%%g1\n" \
1097 " mulscc %%g1,%3,%%g1\n" \
1098 " mulscc %%g1,%3,%%g1\n" \
1099 " mulscc %%g1,%3,%%g1\n" \
1100 " mulscc %%g1,%3,%%g1\n" \
1101 " mulscc %%g1,%3,%%g1\n" \
1102 " mulscc %%g1,%3,%%g1\n" \
1103 " mulscc %%g1,%3,%%g1\n" \
1104 " mulscc %%g1,0,%%g1\n" \
1105 " add %%g1,%%o5,%0\n" \
1106 " rd %%y,%1" \
1107 : "=r" ((USItype) (w1)), \
1108 "=r" ((USItype) (w0)) \
1109 : "%rI" ((USItype) (u)), \
1110 "r" ((USItype) (v)) \
1111 : "g1", "o5" __AND_CLOBBER_CC)
1112 #define UMUL_TIME 39 /* 39 instructions */
1113 /* It's quite necessary to add this much assembler for the sparc.
1114 The default udiv_qrnnd (in C) is more than 10 times slower! */
1115 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1116 __asm__ ("! Inlined udiv_qrnnd\n" \
1117 " mov 32,%%g1\n" \
1118 " subcc %1,%2,%%g0\n" \
1119 "1: bcs 5f\n" \
1120 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1121 " sub %1,%2,%1 ! this kills msb of n\n" \
1122 " addx %1,%1,%1 ! so this can't give carry\n" \
1123 " subcc %%g1,1,%%g1\n" \
1124 "2: bne 1b\n" \
1125 " subcc %1,%2,%%g0\n" \
1126 " bcs 3f\n" \
1127 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1128 " b 3f\n" \
1129 " sub %1,%2,%1 ! this kills msb of n\n" \
1130 "4: sub %1,%2,%1\n" \
1131 "5: addxcc %1,%1,%1\n" \
1132 " bcc 2b\n" \
1133 " subcc %%g1,1,%%g1\n" \
1134 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1135 " bne 4b\n" \
1136 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1137 " sub %1,%2,%1\n" \
1138 "3: xnor %0,0,%0\n" \
1139 " ! End of inline udiv_qrnnd" \
1140 : "=&r" ((USItype) (__q)), \
1141 "=&r" ((USItype) (__r)) \
1142 : "r" ((USItype) (__d)), \
1143 "1" ((USItype) (__n1)), \
1144 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1145 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1146 #endif /* __sparclite__ */
1147 #endif /* __sparc_v8__ */
1148 #endif /* sparc32 */
1149
1150 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1151 && W_TYPE_SIZE == 64
1152 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1153 __asm__ ("addcc %r4,%5,%1\n\t" \
1154 "add %r2,%3,%0\n\t" \
1155 "bcs,a,pn %%xcc, 1f\n\t" \
1156 "add %0, 1, %0\n" \
1157 "1:" \
1158 : "=r" ((UDItype)(sh)), \
1159 "=&r" ((UDItype)(sl)) \
1160 : "%rJ" ((UDItype)(ah)), \
1161 "rI" ((UDItype)(bh)), \
1162 "%rJ" ((UDItype)(al)), \
1163 "rI" ((UDItype)(bl)) \
1164 __CLOBBER_CC)
1165
1166 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1167 __asm__ ("subcc %r4,%5,%1\n\t" \
1168 "sub %r2,%3,%0\n\t" \
1169 "bcs,a,pn %%xcc, 1f\n\t" \
1170 "sub %0, 1, %0\n\t" \
1171 "1:" \
1172 : "=r" ((UDItype)(sh)), \
1173 "=&r" ((UDItype)(sl)) \
1174 : "rJ" ((UDItype)(ah)), \
1175 "rI" ((UDItype)(bh)), \
1176 "rJ" ((UDItype)(al)), \
1177 "rI" ((UDItype)(bl)) \
1178 __CLOBBER_CC)
1179
1180 #define umul_ppmm(wh, wl, u, v) \
1181 do { \
1182 UDItype tmp1, tmp2, tmp3, tmp4; \
1183 __asm__ __volatile__ ( \
1184 "srl %7,0,%3\n\t" \
1185 "mulx %3,%6,%1\n\t" \
1186 "srlx %6,32,%2\n\t" \
1187 "mulx %2,%3,%4\n\t" \
1188 "sllx %4,32,%5\n\t" \
1189 "srl %6,0,%3\n\t" \
1190 "sub %1,%5,%5\n\t" \
1191 "srlx %5,32,%5\n\t" \
1192 "addcc %4,%5,%4\n\t" \
1193 "srlx %7,32,%5\n\t" \
1194 "mulx %3,%5,%3\n\t" \
1195 "mulx %2,%5,%5\n\t" \
1196 "sethi %%hi(0x80000000),%2\n\t" \
1197 "addcc %4,%3,%4\n\t" \
1198 "srlx %4,32,%4\n\t" \
1199 "add %2,%2,%2\n\t" \
1200 "movcc %%xcc,%%g0,%2\n\t" \
1201 "addcc %5,%4,%5\n\t" \
1202 "sllx %3,32,%3\n\t" \
1203 "add %1,%3,%1\n\t" \
1204 "add %5,%2,%0" \
1205 : "=r" ((UDItype)(wh)), \
1206 "=&r" ((UDItype)(wl)), \
1207 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1208 : "r" ((UDItype)(u)), \
1209 "r" ((UDItype)(v)) \
1210 __CLOBBER_CC); \
1211 } while (0)
1212 #define UMUL_TIME 96
1213 #define UDIV_TIME 230
1214 #endif /* sparc64 */
1215
1216 #if defined (__vax__) && W_TYPE_SIZE == 32
1217 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1218 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1219 : "=g" ((USItype) (sh)), \
1220 "=&g" ((USItype) (sl)) \
1221 : "%0" ((USItype) (ah)), \
1222 "g" ((USItype) (bh)), \
1223 "%1" ((USItype) (al)), \
1224 "g" ((USItype) (bl)))
1225 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1226 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1227 : "=g" ((USItype) (sh)), \
1228 "=&g" ((USItype) (sl)) \
1229 : "0" ((USItype) (ah)), \
1230 "g" ((USItype) (bh)), \
1231 "1" ((USItype) (al)), \
1232 "g" ((USItype) (bl)))
1233 #define umul_ppmm(xh, xl, m0, m1) \
1234 do { \
1235 union { \
1236 UDItype __ll; \
1237 struct {USItype __l, __h;} __i; \
1238 } __xx; \
1239 USItype __m0 = (m0), __m1 = (m1); \
1240 __asm__ ("emul %1,%2,$0,%0" \
1241 : "=r" (__xx.__ll) \
1242 : "g" (__m0), \
1243 "g" (__m1)); \
1244 (xh) = __xx.__i.__h; \
1245 (xl) = __xx.__i.__l; \
1246 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1247 + (((SItype) __m1 >> 31) & __m0)); \
1248 } while (0)
1249 #define sdiv_qrnnd(q, r, n1, n0, d) \
1250 do { \
1251 union {DItype __ll; \
1252 struct {SItype __l, __h;} __i; \
1253 } __xx; \
1254 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1255 __asm__ ("ediv %3,%2,%0,%1" \
1256 : "=g" (q), "=g" (r) \
1257 : "g" (__xx.__ll), "g" (d)); \
1258 } while (0)
1259 #endif /* __vax__ */
1260
1261 #if defined (__xtensa__) && W_TYPE_SIZE == 32
1262 /* This code is not Xtensa-configuration-specific, so rely on the compiler
1263 to expand builtin functions depending on what configuration features
1264 are available. This avoids library calls when the operation can be
1265 performed in-line. */
1266 #define umul_ppmm(w1, w0, u, v) \
1267 do { \
1268 DWunion __w; \
1269 __w.ll = __builtin_umulsidi3 (u, v); \
1270 w1 = __w.s.high; \
1271 w0 = __w.s.low; \
1272 } while (0)
1273 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
1274 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
1275 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
1276 #endif /* __xtensa__ */
1277
1278 #if defined (__z8000__) && W_TYPE_SIZE == 16
1279 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1280 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1281 : "=r" ((unsigned int)(sh)), \
1282 "=&r" ((unsigned int)(sl)) \
1283 : "%0" ((unsigned int)(ah)), \
1284 "r" ((unsigned int)(bh)), \
1285 "%1" ((unsigned int)(al)), \
1286 "rQR" ((unsigned int)(bl)))
1287 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1288 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1289 : "=r" ((unsigned int)(sh)), \
1290 "=&r" ((unsigned int)(sl)) \
1291 : "0" ((unsigned int)(ah)), \
1292 "r" ((unsigned int)(bh)), \
1293 "1" ((unsigned int)(al)), \
1294 "rQR" ((unsigned int)(bl)))
1295 #define umul_ppmm(xh, xl, m0, m1) \
1296 do { \
1297 union {long int __ll; \
1298 struct {unsigned int __h, __l;} __i; \
1299 } __xx; \
1300 unsigned int __m0 = (m0), __m1 = (m1); \
1301 __asm__ ("mult %S0,%H3" \
1302 : "=r" (__xx.__i.__h), \
1303 "=r" (__xx.__i.__l) \
1304 : "%1" (__m0), \
1305 "rQR" (__m1)); \
1306 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1307 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1308 + (((signed int) __m1 >> 15) & __m0)); \
1309 } while (0)
1310 #endif /* __z8000__ */
1311
1312 #endif /* __GNUC__ */
1313
1314 /* If this machine has no inline assembler, use C macros. */
1315
1316 #if !defined (add_ssaaaa)
1317 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1318 do { \
1319 UWtype __x; \
1320 __x = (al) + (bl); \
1321 (sh) = (ah) + (bh) + (__x < (al)); \
1322 (sl) = __x; \
1323 } while (0)
1324 #endif
1325
1326 #if !defined (sub_ddmmss)
1327 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1328 do { \
1329 UWtype __x; \
1330 __x = (al) - (bl); \
1331 (sh) = (ah) - (bh) - (__x > (al)); \
1332 (sl) = __x; \
1333 } while (0)
1334 #endif
1335
1336 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1337 smul_ppmm. */
1338 #if !defined (umul_ppmm) && defined (smul_ppmm)
1339 #define umul_ppmm(w1, w0, u, v) \
1340 do { \
1341 UWtype __w1; \
1342 UWtype __xm0 = (u), __xm1 = (v); \
1343 smul_ppmm (__w1, w0, __xm0, __xm1); \
1344 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1345 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1346 } while (0)
1347 #endif
1348
1349 /* If we still don't have umul_ppmm, define it using plain C. */
1350 #if !defined (umul_ppmm)
1351 #define umul_ppmm(w1, w0, u, v) \
1352 do { \
1353 UWtype __x0, __x1, __x2, __x3; \
1354 UHWtype __ul, __vl, __uh, __vh; \
1355 \
1356 __ul = __ll_lowpart (u); \
1357 __uh = __ll_highpart (u); \
1358 __vl = __ll_lowpart (v); \
1359 __vh = __ll_highpart (v); \
1360 \
1361 __x0 = (UWtype) __ul * __vl; \
1362 __x1 = (UWtype) __ul * __vh; \
1363 __x2 = (UWtype) __uh * __vl; \
1364 __x3 = (UWtype) __uh * __vh; \
1365 \
1366 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1367 __x1 += __x2; /* but this indeed can */ \
1368 if (__x1 < __x2) /* did we get it? */ \
1369 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1370 \
1371 (w1) = __x3 + __ll_highpart (__x1); \
1372 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1373 } while (0)
1374 #endif
1375
1376 #if !defined (__umulsidi3)
1377 #define __umulsidi3(u, v) \
1378 ({DWunion __w; \
1379 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1380 __w.ll; })
1381 #endif
1382
1383 /* Define this unconditionally, so it can be used for debugging. */
1384 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1385 do { \
1386 UWtype __d1, __d0, __q1, __q0; \
1387 UWtype __r1, __r0, __m; \
1388 __d1 = __ll_highpart (d); \
1389 __d0 = __ll_lowpart (d); \
1390 \
1391 __r1 = (n1) % __d1; \
1392 __q1 = (n1) / __d1; \
1393 __m = (UWtype) __q1 * __d0; \
1394 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1395 if (__r1 < __m) \
1396 { \
1397 __q1--, __r1 += (d); \
1398 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1399 if (__r1 < __m) \
1400 __q1--, __r1 += (d); \
1401 } \
1402 __r1 -= __m; \
1403 \
1404 __r0 = __r1 % __d1; \
1405 __q0 = __r1 / __d1; \
1406 __m = (UWtype) __q0 * __d0; \
1407 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1408 if (__r0 < __m) \
1409 { \
1410 __q0--, __r0 += (d); \
1411 if (__r0 >= (d)) \
1412 if (__r0 < __m) \
1413 __q0--, __r0 += (d); \
1414 } \
1415 __r0 -= __m; \
1416 \
1417 (q) = (UWtype) __q1 * __ll_B | __q0; \
1418 (r) = __r0; \
1419 } while (0)
1420
1421 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1422 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1423 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1424 #define udiv_qrnnd(q, r, nh, nl, d) \
1425 do { \
1426 USItype __r; \
1427 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1428 (r) = __r; \
1429 } while (0)
1430 #endif
1431
1432 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1433 #if !defined (udiv_qrnnd)
1434 #define UDIV_NEEDS_NORMALIZATION 1
1435 #define udiv_qrnnd __udiv_qrnnd_c
1436 #endif
1437
1438 #if !defined (count_leading_zeros)
1439 #define count_leading_zeros(count, x) \
1440 do { \
1441 UWtype __xr = (x); \
1442 UWtype __a; \
1443 \
1444 if (W_TYPE_SIZE <= 32) \
1445 { \
1446 __a = __xr < ((UWtype)1<<2*__BITS4) \
1447 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1448 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1449 } \
1450 else \
1451 { \
1452 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1453 if (((__xr >> __a) & 0xff) != 0) \
1454 break; \
1455 } \
1456 \
1457 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1458 } while (0)
1459 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1460 #endif
1461
1462 #if !defined (count_trailing_zeros)
1463 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1464 defined in asm, but if it is not, the C version above is good enough. */
1465 #define count_trailing_zeros(count, x) \
1466 do { \
1467 UWtype __ctz_x = (x); \
1468 UWtype __ctz_c; \
1469 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1470 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1471 } while (0)
1472 #endif
1473
1474 #ifndef UDIV_NEEDS_NORMALIZATION
1475 #define UDIV_NEEDS_NORMALIZATION 0
1476 #endif
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