| blob | 177efb3734c879ac52f9c225a224811fe7ee256d |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
58 /* Not really meaningful values, but at least something. */
59 #ifndef SIMULTANEOUS_PREFETCHES
60 #define SIMULTANEOUS_PREFETCHES 3
61 #endif
62 #ifndef PREFETCH_BLOCK
63 #define PREFETCH_BLOCK 32
64 #endif
65 #ifndef HAVE_prefetch
66 #define HAVE_prefetch 0
67 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
68 #endif
70 /* Give up the prefetch optimizations once we exceed a given threshhold.
71 It is unlikely that we would be able to optimize something in a loop
72 with so many detected prefetches. */
73 #define MAX_PREFETCHES 100
74 /* The number of prefetch blocks that are beneficial to fetch at once before
75 a loop with a known (and low) iteration count. */
76 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
77 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
78 since it is likely that the data are already in the cache. */
79 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
80 /* The minimal number of prefetch blocks that a loop must consume to make
81 the emitting of prefetch instruction in the body of loop worthwhile. */
82 #define PREFETCH_BLOCKS_IN_LOOP_MIN 6
84 /* Parameterize some prefetch heuristics so they can be turned on and off
85 easily for performance testing on new architecures. These can be
86 defined in target-dependent files. */
88 /* Prefetch is worthwhile only when loads/stores are dense. */
89 #ifndef PREFETCH_ONLY_DENSE_MEM
90 #define PREFETCH_ONLY_DENSE_MEM 1
91 #endif
93 /* Define what we mean by "dense" loads and stores; This value divided by 256
94 is the minimum percentage of memory references that worth prefetching. */
95 #ifndef PREFETCH_DENSE_MEM
96 #define PREFETCH_DENSE_MEM 220
97 #endif
99 /* Do not prefetch for a loop whose iteration count is known to be low. */
100 #ifndef PREFETCH_NO_LOW_LOOPCNT
101 #define PREFETCH_NO_LOW_LOOPCNT 1
102 #endif
104 /* Define what we mean by a "low" iteration count. */
105 #ifndef PREFETCH_LOW_LOOPCNT
106 #define PREFETCH_LOW_LOOPCNT 32
107 #endif
109 /* Do not prefetch for a loop that contains a function call; such a loop is
110 probably not an internal loop. */
111 #ifndef PREFETCH_NO_CALL
112 #define PREFETCH_NO_CALL 1
113 #endif
115 /* Do not prefetch accesses with an extreme stride. */
116 #ifndef PREFETCH_NO_EXTREME_STRIDE
117 #define PREFETCH_NO_EXTREME_STRIDE 1
118 #endif
120 /* Define what we mean by an "extreme" stride. */
121 #ifndef PREFETCH_EXTREME_STRIDE
122 #define PREFETCH_EXTREME_STRIDE 4096
123 #endif
125 /* Do not handle reversed order prefetches (negative stride). */
126 #ifndef PREFETCH_NO_REVERSE_ORDER
127 #define PREFETCH_NO_REVERSE_ORDER 1
128 #endif
130 /* Prefetch even if the GIV is not always executed. */
131 #ifndef PREFETCH_NOT_ALWAYS
132 #define PREFETCH_NOT_ALWAYS 0
133 #endif
135 /* If the loop requires more prefetches than the target can process in
136 parallel then don't prefetch anything in that loop. */
137 #ifndef PREFETCH_LIMIT_TO_SIMULTANEOUS
138 #define PREFETCH_LIMIT_TO_SIMULTANEOUS 1
139 #endif
141 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
142 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
144 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
145 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
146 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
148 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
149 ((REGNO) < FIRST_PSEUDO_REGISTER \
150 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
153 /* Vector mapping INSN_UIDs to luids.
154 The luids are like uids but increase monotonically always.
155 We use them to see whether a jump comes from outside a given loop. */
159 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
160 number the insn is contained in. */
164 /* 1 + largest uid of any insn. */
168 /* 1 + luid of last insn. */
172 /* Number of loops detected in current function. Used as index to the
173 next few tables. */
177 /* Bound on pseudo register number before loop optimization.
178 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
181 /* The value to pass to the next call of reg_scan_update. */
184 #define obstack_chunk_alloc xmalloc
185 #define obstack_chunk_free free
186 \f
187 /* During the analysis of a loop, a chain of `struct movable's
188 is made to record all the movable insns found.
189 Then the entire chain can be scanned to decide which to move. */
191 struct movable
192 {
197 of any registers used within the LIBCALL. */
199 that must be moved with this one. */
202 may be adjusted when matching movables
203 that load the same value are found. */
205 including other movables that force this
206 or match this one. */
210 /* If PARTIAL is 1, GLOBAL means something different:
211 that the reg is live outside the range from where it is set
212 to the following label. */
216 In particular, moving it does not make it
217 invariant. */
219 load SRC, rather than copying INSN. */
221 first insn of a consecutive sets group. */
224 that we should avoid changing when clearing
225 the rest of the reg. */
229 };
234 /* Forward declarations. */
248 #if 0
250 #endif
280 rtx *));
362 {
363 rtx r1;
364 rtx r2;
368 {
369 rtx match;
370 rtx replacement;
371 rtx insn;
374 /* Nonzero iff INSN is between START and END, inclusive. */
375 #define INSN_IN_RANGE_P(INSN, START, END) \
376 (INSN_UID (INSN) < max_uid_for_loop \
377 && INSN_LUID (INSN) >= INSN_LUID (START) \
378 && INSN_LUID (INSN) <= INSN_LUID (END))
380 /* Indirect_jump_in_function is computed once per function. */
388 rtx));
389 \f
390 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
391 copy the value of the strength reduced giv to its original register. */
394 /* Cost of using a register, to normalize the benefits of a giv. */
397 void
399 {
405 }
406 \f
407 /* Compute the mapping from uids to luids.
408 LUIDs are numbers assigned to insns, like uids,
409 except that luids increase monotonically through the code.
410 Start at insn START and stop just before END. Assign LUIDs
411 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
412 static int
416 {
418 rtx insn;
421 {
424 /* Don't assign luids to line-number NOTEs, so that the distance in
425 luids between two insns is not affected by -g. */
429 else
430 /* Give a line number note the same luid as preceding insn. */
432 }
434 }
435 \f
436 /* Entry point of this file. Perform loop optimization
437 on the current function. F is the first insn of the function
438 and DUMPFILE is a stream for output of a trace of actions taken
439 (or 0 if none should be output). */
441 void
443 /* f is the first instruction of a chain of insns for one function */
444 rtx f;
447 {
448 rtx insn;
463 /* Count the number of loops. */
467 {
470 max_loop_num++;
471 }
473 /* Don't waste time if no loops. */
479 /* Get size to use for tables indexed by uids.
480 Leave some space for labels allocated by find_and_verify_loops. */
487 /* Allocate storage for array of loops. */
491 /* Find and process each loop.
492 First, find them, and record them in order of their beginnings. */
495 /* Allocate and initialize auxiliary loop information. */
500 /* Now find all register lifetimes. This must be done after
501 find_and_verify_loops, because it might reorder the insns in the
502 function. */
505 /* This must occur after reg_scan so that registers created by gcse
506 will have entries in the register tables.
508 We could have added a call to reg_scan after gcse_main in toplev.c,
509 but moving this call to init_alias_analysis is more efficient. */
512 /* See if we went too far. Note that get_max_uid already returns
513 one more that the maximum uid of all insn. */
516 /* Now reset it to the actual size we need. See above. */
519 /* find_and_verify_loops has already called compute_luids, but it
520 might have rearranged code afterwards, so we need to recompute
521 the luids now. */
524 /* Don't leave gaps in uid_luid for insns that have been
525 deleted. It is possible that the first or last insn
526 using some register has been deleted by cross-jumping.
527 Make sure that uid_luid for that former insn's uid
528 points to the general area where that insn used to be. */
530 {
534 }
539 /* Determine if the function has indirect jump. On some systems
540 this prevents low overhead loop instructions from being used. */
543 /* Now scan the loops, last ones first, since this means inner ones are done
544 before outer ones. */
546 {
551 }
553 /* If there were lexical blocks inside the loop, they have been
554 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
555 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
556 the BLOCKs as well. */
562 /* Clean up. */
567 }
568 \f
569 /* Returns the next insn, in execution order, after INSN. START and
570 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
571 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
572 insn-stream; it is used with loops that are entered near the
573 bottom. */
575 static rtx
578 rtx insn;
579 {
583 {
585 /* Go to the top of the loop, and continue there. */
587 else
588 /* We're done. */
590 }
593 /* We're done. */
597 }
599 /* Optimize one loop described by LOOP. */
601 /* ??? Could also move memory writes out of loops if the destination address
602 is invariant, the source is invariant, the memory write is not volatile,
603 and if we can prove that no read inside the loop can read this address
604 before the write occurs. If there is a read of this address after the
605 write, then we can also mark the memory read as invariant. */
607 static void
611 {
617 rtx p;
618 /* 1 if we are scanning insns that could be executed zero times. */
620 /* 1 if we are scanning insns that might never be executed
621 due to a subroutine call which might exit before they are reached. */
623 /* Jump insn that enters the loop, or 0 if control drops in. */
625 /* Number of insns in the loop. */
629 /* The SET from an insn, if it is the only SET in the insn. */
631 /* Chain describing insns movable in current loop. */
633 /* Ratio of extra register life span we can justify
634 for saving an instruction. More if loop doesn't call subroutines
635 since in that case saving an insn makes more difference
636 and more registers are available. */
638 /* Nonzero if we are scanning instructions in a sub-loop. */
646 /* Determine whether this loop starts with a jump down to a test at
647 the end. This will occur for a small number of loops with a test
648 that is too complex to duplicate in front of the loop.
650 We search for the first insn or label in the loop, skipping NOTEs.
651 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
652 (because we might have a loop executed only once that contains a
653 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
654 (in case we have a degenerate loop).
656 Note that if we mistakenly think that a loop is entered at the top
657 when, in fact, it is entered at the exit test, the only effect will be
658 slightly poorer optimization. Making the opposite error can generate
659 incorrect code. Since very few loops now start with a jump to the
660 exit test, the code here to detect that case is very conservative. */
663 p != loop_end
669 ;
673 /* If loop end is the end of the current function, then emit a
674 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
675 note insn. This is the position we use when sinking insns out of
676 the loop. */
679 else
682 /* Set up variables describing this loop. */
686 /* If loop has a jump before the first label,
687 the true entry is the target of that jump.
688 Start scan from there.
689 But record in LOOP->TOP the place where the end-test jumps
690 back to so we can scan that after the end of the loop. */
692 {
695 /* Loop entry must be unconditional jump (and not a RETURN) */
698 /* Check to see whether the jump actually
699 jumps out of the loop (meaning it's no loop).
700 This case can happen for things like
701 do {..} while (0). If this label was generated previously
702 by loop, we can't tell anything about it and have to reject
703 the loop. */
705 {
708 }
709 }
711 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
712 as required by loop_reg_used_before_p. So skip such loops. (This
713 test may never be true, but it's best to play it safe.)
715 Also, skip loops where we do not start scanning at a label. This
716 test also rejects loops starting with a JUMP_INSN that failed the
717 test above. */
721 {
726 }
728 /* Allocate extra space for REGs that might be created by load_mems.
729 We allocate a little extra slop as well, in the hopes that we
730 won't have to reallocate the regs array. */
735 {
741 }
743 /* Scan through the loop finding insns that are safe to move.
744 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
745 this reg will be considered invariant for subsequent insns.
746 We consider whether subsequent insns use the reg
747 in deciding whether it is worth actually moving.
749 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
750 and therefore it is possible that the insns we are scanning
751 would never be executed. At such times, we must make sure
752 that it is safe to execute the insn once instead of zero times.
753 When MAYBE_NEVER is 0, all insns will be executed at least once
754 so that is not a problem. */
759 {
764 {
771 /* Figure out what to use as a source of this insn. If a REG_EQUIV
772 note is given or if a REG_EQUAL note with a constant operand is
773 specified, use it as the source and mark that we should move
774 this insn by calling emit_move_insn rather that duplicating the
775 insn.
777 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
778 is present. */
782 else
783 {
788 {
790 /* A libcall block can use regs that don't appear in
791 the equivalent expression. To move the libcall,
792 we must move those regs too. */
794 }
795 }
797 /* For parallels, add any possible uses to the depencies, as we can't move
798 the insn without resolving them first. */
800 {
802 {
806 }
807 }
809 /* Don't try to optimize a register that was made
810 by loop-optimization for an inner loop.
811 We don't know its life-span, so we can't compute the benefit. */
813 ;
815 than the one where it is set (meaning that
816 something after this point in the loop might
817 depend on its value before the set). */
819 /* And the set is not guaranteed to be executed once
820 the loop starts, or the value before the set is
821 needed before the set occurs...
823 ??? Note we have quadratic behaviour here, mitigated
824 by the fact that the previous test will often fail for
825 large loops. Rather than re-scanning the entire loop
826 each time for register usage, we should build tables
827 of the register usage and use them here instead. */
828 && (maybe_never
830 /* It is unsafe to move the set.
832 This code used to consider it OK to move a set of a variable
833 which was not created by the user and not used in an exit test.
834 That behavior is incorrect and was removed. */
835 ;
840 || (tem1
841 = consec_sets_invariant_p
844 p)))
845 /* If the insn can cause a trap (such as divide by zero),
846 can't move it unless it's guaranteed to be executed
847 once loop is entered. Even a function call might
848 prevent the trap insn from being reached
849 (since it might exit!) */
852 {
856 /* A potential lossage is where we have a case where two insns
857 can be combined as long as they are both in the loop, but
858 we move one of them outside the loop. For large loops,
859 this can lose. The most common case of this is the address
860 of a function being called.
862 Therefore, if this register is marked as being used exactly
863 once if we are in a loop with calls (a "large loop"), see if
864 we can replace the usage of this register with the source
865 of this SET. If we can, delete this insn.
867 Don't do this if P has a REG_RETVAL note or if we have
868 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
880 && (! SMALL_REGISTER_CLASSES
883 /* This test is not redundant; SET_SRC (set) might be
884 a call-clobbered register and the life of REGNO
885 might span a call. */
891 {
892 /* Replace any usage in a REG_EQUAL note. Must copy the
893 new source, so that we don't get rtx sharing between the
894 SET_SOURCE and REG_NOTES of insn p. */
903 }
921 /* Set M->cond if either loop_invariant_p
922 or consec_sets_invariant_p returned 2
923 (only conditionally invariant). */
933 /* Add M to the end of the chain MOVABLES. */
937 {
938 /* It is possible for the first instruction to have a
939 REG_EQUAL note but a non-invariant SET_SRC, so we must
940 remember the status of the first instruction in case
941 the last instruction doesn't have a REG_EQUAL note. */
944 /* Skip this insn, not checking REG_LIBCALL notes. */
946 /* Skip the consecutive insns, if there are any. */
948 /* Back up to the last insn of the consecutive group. */
951 /* We must now reset m->move_insn, m->is_equiv, and possibly
952 m->set_src to correspond to the effects of all the
953 insns. */
957 else
958 {
962 else
965 }
967 }
968 }
969 /* If this register is always set within a STRICT_LOW_PART
970 or set to zero, then its high bytes are constant.
971 So clear them outside the loop and within the loop
972 just load the low bytes.
973 We must check that the machine has an instruction to do so.
974 Also, if the value loaded into the register
975 depends on the same register, this cannot be done. */
985 {
988 {
1002 /* If the insn may not be executed on some cycles,
1003 we can't clear the whole reg; clear just high part.
1004 Not even if the reg is used only within this loop.
1005 Consider this:
1006 while (1)
1007 while (s != t) {
1008 if (foo ()) x = *s;
1009 use (x);
1010 }
1011 Clearing x before the inner loop could clobber a value
1012 being saved from the last time around the outer loop.
1013 However, if the reg is not used outside this loop
1014 and all uses of the register are in the same
1015 basic block as the store, there is no problem.
1017 If this insn was made by loop, we don't know its
1018 INSN_LUID and hence must make a conservative
1019 assumption. */
1022 || (labels_in_range_p
1026 else
1035 /* Add M to the end of the chain MOVABLES. */
1037 }
1038 }
1039 }
1040 /* Past a call insn, we get to insns which might not be executed
1041 because the call might exit. This matters for insns that trap.
1042 Constant and pure call insns always return, so they don't count. */
1045 /* Past a label or a jump, we get to insns for which we
1046 can't count on whether or how many times they will be
1047 executed during each iteration. Therefore, we can
1048 only move out sets of trivial variables
1049 (those not used after the loop). */
1050 /* Similar code appears twice in strength_reduce. */
1052 /* If we enter the loop in the middle, and scan around to the
1053 beginning, don't set maybe_never for that. This must be an
1054 unconditional jump, otherwise the code at the top of the
1055 loop might never be executed. Unconditional jumps are
1056 followed by a barrier then the loop_end. */
1062 {
1063 /* At the virtual top of a converted loop, insns are again known to
1064 be executed: logically, the loop begins here even though the exit
1065 code has been duplicated. */
1069 loop_depth++;
1071 loop_depth--;
1072 }
1073 }
1075 /* If one movable subsumes another, ignore that other. */
1079 /* For each movable insn, see if the reg that it loads
1080 leads when it dies right into another conditionally movable insn.
1081 If so, record that the second insn "forces" the first one,
1082 since the second can be moved only if the first is. */
1086 /* See if there are multiple movable insns that load the same value.
1087 If there are, make all but the first point at the first one
1088 through the `match' field, and add the priorities of them
1089 all together as the priority of the first. */
1093 /* Now consider each movable insn to decide whether it is worth moving.
1094 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1096 Generally this increases code size, so do not move moveables when
1097 optimizing for code size. */
1102 /* Now candidates that still are negative are those not moved.
1103 Change regs->array[I].set_in_loop to indicate that those are not actually
1104 invariant. */
1109 /* Now that we've moved some things out of the loop, we might be able to
1110 hoist even more memory references. */
1113 /* Recalculate regs->array if load_mems has created new registers. */
1121 ;
1128 {
1130 /* Ensure our label doesn't go away. */
1141 }
1144 /* The movable information is required for strength reduction. */
1150 }
1151 \f
1152 /* Add elements to *OUTPUT to record all the pseudo-regs
1153 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1155 void
1159 {
1167 {
1185 }
1189 {
1193 {
1202 }
1203 }
1204 }
1205 \f
1206 /* Check what regs are referred to in the libcall block ending with INSN,
1207 aside from those mentioned in the equivalent value.
1208 If there are none, return 0.
1209 If there are one or more, return an EXPR_LIST containing all of them. */
1211 rtx
1214 {
1219 /* First, find all the regs used in the libcall block
1220 that are not mentioned as inputs to the result. */
1223 {
1228 }
1231 }
1232 \f
1233 /* Return 1 if all uses of REG
1234 are between INSN and the end of the basic block. */
1236 static int
1239 {
1241 rtx p;
1246 /* Search this basic block for the already recorded last use of the reg. */
1248 {
1250 {
1256 /* Ordinary insn: if this is the last use, we win. */
1262 /* Jump insn: if this is the last use, we win. */
1265 /* Otherwise, it's the end of the basic block, so we lose. */
1270 /* It's the end of the basic block, so we lose. */
1275 }
1276 }
1278 /* The "last use" that was recorded can't be found after the first
1279 use. This can happen when the last use was deleted while
1280 processing an inner loop, this inner loop was then completely
1281 unrolled, and the outer loop is always exited after the inner loop,
1282 so that everything after the first use becomes a single basic block. */
1284 }
1285 \f
1286 /* Compute the benefit of eliminating the insns in the block whose
1287 last insn is LAST. This may be a group of insns used to compute a
1288 value directly or can contain a library call. */
1290 static int
1292 rtx last;
1293 {
1294 rtx insn;
1299 {
1302 routine. */
1306 benefit++;
1307 }
1310 }
1311 \f
1312 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1314 static rtx
1316 rtx insn;
1318 {
1320 {
1321 rtx temp;
1323 /* If first insn of libcall sequence, skip to end. */
1324 /* Do this at start of loop, since INSN is guaranteed to
1325 be an insn here. */
1330 do
1333 }
1336 }
1338 /* Ignore any movable whose insn falls within a libcall
1339 which is part of another movable.
1340 We make use of the fact that the movable for the libcall value
1341 was made later and so appears later on the chain. */
1343 static void
1346 {
1350 {
1351 /* Is this a movable for the value of a libcall? */
1354 {
1355 rtx insn;
1356 /* Check for earlier movables inside that range,
1357 and mark them invalid. We cannot use LUIDs here because
1358 insns created by loop.c for prior loops don't have LUIDs.
1359 Rather than reject all such insns from movables, we just
1360 explicitly check each insn in the libcall (since invariant
1361 libcalls aren't that common). */
1366 }
1367 }
1368 }
1370 /* For each movable insn, see if the reg that it loads
1371 leads when it dies right into another conditionally movable insn.
1372 If so, record that the second insn "forces" the first one,
1373 since the second can be moved only if the first is. */
1375 static void
1378 {
1382 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1384 {
1387 /* ??? Could this be a bug? What if CSE caused the
1388 register of M1 to be used after this insn?
1389 Since CSE does not update regno_last_uid,
1390 this insn M->insn might not be where it dies.
1391 But very likely this doesn't matter; what matters is
1392 that M's reg is computed from M1's reg. */
1397 /* If m->consec, m->set_src isn't valid. */
1401 /* Increase the priority of the moving the first insn
1402 since it permits the second to be moved as well. */
1404 {
1408 }
1409 }
1410 }
1411 \f
1412 /* Find invariant expressions that are equal and can be combined into
1413 one register. */
1415 static void
1419 {
1424 /* Regs that are set more than once are not allowed to match
1425 or be matched. I'm no longer sure why not. */
1426 /* Perhaps testing m->consec_sets would be more appropriate here? */
1431 {
1438 /* We want later insns to match the first one. Don't make the first
1439 one match any later ones. So start this loop at m->next. */
1441 /* ??? HACK! move_movables does not verify that the replacement
1442 is valid, which can have disasterous effects with hard regs
1443 and match_dup. Turn combination off for now. */
1446 /* A reg used outside the loop mustn't be eliminated. */
1448 /* A reg used for zero-extending mustn't be eliminated. */
1451 ||
1452 (
1453 /* Can combine regs with different modes loaded from the
1454 same constant only if the modes are the same or
1455 if both are integer modes with M wider or the same
1456 width as M1. The check for integer is redundant, but
1457 safe, since the only case of differing destination
1458 modes with equal sources is when both sources are
1459 VOIDmode, i.e., CONST_INT. */
1465 /* See if the source of M1 says it matches M. */
1472 {
1478 }
1479 }
1481 /* Now combine the regs used for zero-extension.
1482 This can be done for those not marked `global'
1483 provided their lives don't overlap. */
1487 {
1490 /* Combine all the registers for extension from mode MODE.
1491 Don't combine any that are used outside this loop. */
1495 {
1502 {
1503 /* First one: don't check for overlap, just record it. */
1506 }
1508 /* Make sure they extend to the same mode.
1509 (Almost always true.) */
1513 /* We already have one: check for overlap with those
1514 already combined together. */
1521 /* No overlap: we can combine this with the others. */
1527 overlap:
1528 ;
1529 }
1530 }
1532 /* Clean up. */
1534 }
1536 /* Returns the number of movable instructions in LOOP that were not
1537 moved outside the loop. */
1539 static int
1542 {
1551 }
1553 \f
1554 /* Return 1 if regs X and Y will become the same if moved. */
1556 static int
1560 {
1577 }
1579 /* Return 1 if X and Y are identical-looking rtx's.
1580 This is the Lisp function EQUAL for rtx arguments.
1582 If two registers are matching movables or a movable register and an
1583 equivalent constant, consider them equal. */
1585 static int
1590 {
1604 /* If we have a register and a constant, they may sometimes be
1605 equal. */
1608 {
1613 }
1616 {
1621 }
1623 /* Otherwise, rtx's of different codes cannot be equal. */
1627 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1628 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1633 /* These three types of rtx's can be compared nonrecursively. */
1642 /* Compare the elements. If any pair of corresponding elements
1643 fail to match, return 0 for the whole things. */
1647 {
1649 {
1661 /* Two vectors must have the same length. */
1665 /* And the corresponding elements must match. */
1684 /* These are just backpointers, so they don't matter. */
1690 /* It is believed that rtx's at this level will never
1691 contain anything but integers and other rtx's,
1692 except for within LABEL_REFs and SYMBOL_REFs. */
1695 }
1696 }
1698 }
1699 \f
1700 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1701 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1702 references is incremented once for each added note. */
1704 static void
1706 rtx x;
1707 rtx insns;
1708 {
1712 rtx insn;
1715 {
1716 /* This code used to ignore labels that referred to dispatch tables to
1717 avoid flow generating (slighly) worse code.
1719 We no longer ignore such label references (see LABEL_REF handling in
1720 mark_jump_label for additional information). */
1723 {
1728 }
1729 }
1733 {
1739 }
1740 }
1741 \f
1742 /* Scan MOVABLES, and move the insns that deserve to be moved.
1743 If two matching movables are combined, replace one reg with the
1744 other throughout. */
1746 static void
1752 {
1757 rtx p;
1760 /* Map of pseudo-register replacements to handle combining
1761 when we move several insns that load the same value
1762 into different pseudo-registers. */
1767 {
1768 /* Describe this movable insn. */
1771 {
1792 }
1794 /* Ignore the insn if it's already done (it matched something else).
1795 Otherwise, see if it is now safe to move. */
1807 {
1809 rtx p;
1812 /* We have an insn that is safe to move.
1813 Compute its desirability. */
1824 /* An insn MUST be moved if we already moved something else
1825 which is safe only if this one is moved too: that is,
1826 if already_moved[REGNO] is nonzero. */
1828 /* An insn is desirable to move if the new lifetime of the
1829 register is no more than THRESHOLD times the old lifetime.
1830 If it's not desirable, it means the loop is so big
1831 that moving won't speed things up much,
1832 and it is liable to make register usage worse. */
1834 /* It is also desirable to move if it can be moved at no
1835 extra cost because something else was already moved. */
1838 || flag_move_all_movables
1843 {
1848 /* Now move the insns that set the reg. */
1851 {
1854 /* Find the end of this chain of matching regs.
1855 Thus, we load each reg in the chain from that one reg.
1856 And that reg is loaded with 0 directly,
1857 since it has ->match == 0. */
1863 /* Mark the moved, invariant reg as being allowed to
1864 share a hard reg with the other matching invariant. */
1868 regs_may_share
1871 regs_may_share));
1879 }
1880 /* If we are to re-generate the item being moved with a
1881 new move insn, first delete what we have and then emit
1882 the move insn before the loop. */
1884 {
1888 {
1889 /* If this is the first insn of a library call sequence,
1890 skip to the end. */
1895 /* If this is the last insn of a libcall sequence, then
1896 delete every insn in the sequence except the last.
1897 The last insn is handled in the normal manner. */
1900 {
1904 }
1909 /* simplify_giv_expr expects that it can walk the insns
1910 at m->insn forwards and see this old sequence we are
1911 tossing here. delete_insn does preserve the next
1912 pointers, but when we skip over a NOTE we must fix
1913 it up. Otherwise that code walks into the non-deleted
1914 insn stream. */
1917 }
1936 /* The more regs we move, the less we like moving them. */
1938 }
1939 else
1940 {
1942 {
1945 /* If first insn of libcall sequence, skip to end. */
1946 /* Do this at start of loop, since p is guaranteed to
1947 be an insn here. */
1952 /* If last insn of libcall sequence, move all
1953 insns except the last before the loop. The last
1954 insn is handled in the normal manner. */
1957 {
1965 {
1966 rtx body;
1967 rtx n;
1968 rtx next;
1975 /* Find the next insn after TEMP,
1976 not counting USE or NOTE insns. */
1984 /* If that is the call, this may be the insn
1985 that loads the function address.
1987 Extract the function address from the insn
1988 that loads it into a register.
1989 If this insn was cse'd, we get incorrect code.
1991 So emit a new move insn that copies the
1992 function address into the register that the
1993 call insn will use. flow.c will delete any
1994 redundant stores that we have created. */
1999 NULL_RTX)))
2000 {
2006 }
2007 /* We have the call insn.
2008 If it uses the register we suspect it might,
2009 load it with the correct address directly. */
2014 gen_move_insn
2018 {
2020 /* Because the USAGE information potentially
2021 contains objects other than hard registers
2022 we need to copy it. */
2026 }
2027 else
2036 }
2039 }
2041 {
2042 /* P sets REG to zero; but we should clear only
2043 the bits that are not covered by the mode
2044 m->savemode. */
2046 rtx sequence;
2047 rtx tem;
2050 tem = expand_simple_binop
2063 }
2065 {
2067 /* Because the USAGE information potentially
2068 contains objects other than hard registers
2069 we need to copy it. */
2073 }
2075 {
2076 rtx seq;
2077 /* The SET_SRC might not be invariant, so we must
2078 use the REG_EQUAL note. */
2091 }
2092 else
2096 {
2100 /* If there is a REG_EQUAL note present whose value
2101 is not loop invariant, then delete it, since it
2102 may cause problems with later optimization passes.
2103 It is possible for cse to create such notes
2104 like this as a result of record_jump_cond. */
2109 }
2118 /* If library call, now fix the REG_NOTES that contain
2119 insn pointers, namely REG_LIBCALL on FIRST
2120 and REG_RETVAL on I1. */
2122 {
2126 }
2132 /* simplify_giv_expr expects that it can walk the insns
2133 at m->insn forwards and see this old sequence we are
2134 tossing here. delete_insn does preserve the next
2135 pointers, but when we skip over a NOTE we must fix
2136 it up. Otherwise that code walks into the non-deleted
2137 insn stream. */
2140 }
2142 /* The more regs we move, the less we like moving them. */
2144 }
2146 /* Any other movable that loads the same register
2147 MUST be moved. */
2150 /* This reg has been moved out of one loop. */
2153 /* The reg set here is now invariant. */
2155 {
2159 }
2163 /* Change the length-of-life info for the register
2164 to say it lives at least the full length of this loop.
2165 This will help guide optimizations in outer loops. */
2168 /* This is the old insn before all the moved insns.
2169 We can't use the moved insn because it is out of range
2170 in uid_luid. Only the old insns have luids. */
2175 /* Combine with this moved insn any other matching movables. */
2180 {
2181 rtx temp;
2183 /* Schedule the reg loaded by M1
2184 for replacement so that shares the reg of M.
2185 If the modes differ (only possible in restricted
2186 circumstances, make a SUBREG.
2188 Note this assumes that the target dependent files
2189 treat REG and SUBREG equally, including within
2190 GO_IF_LEGITIMATE_ADDRESS and in all the
2191 predicates since we never verify that replacing the
2192 original register with a SUBREG results in a
2193 recognizable insn. */
2196 else
2201 /* Get rid of the matching insn
2202 and prevent further processing of it. */
2205 /* if library call, delete all insns. */
2207 NULL_RTX)))
2209 else
2212 /* Any other movable that loads the same register
2213 MUST be moved. */
2216 /* The reg merged here is now invariant,
2217 if the reg it matches is invariant. */
2219 {
2223 i++)
2225 }
2226 }
2227 }
2230 }
2236 }
2241 /* Go through all the instructions in the loop, making
2242 all the register substitutions scheduled in REG_MAP. */
2246 {
2250 }
2252 /* Clean up. */
2255 }
2258 static void
2262 {
2265 else
2268 }
2271 static void
2274 {
2279 {
2282 }
2283 }
2284 \f
2285 #if 0
2286 /* Scan X and replace the address of any MEM in it with ADDR.
2287 REG is the address that MEM should have before the replacement. */
2289 static void
2292 {
2301 {
2313 /* Short cut for very common case. */
2318 /* Short cut for very common case. */
2323 /* If this MEM uses a reg other than the one we expected,
2324 something is wrong. */
2332 }
2336 {
2340 {
2344 }
2345 }
2346 }
2347 #endif
2348 \f
2349 /* Return the number of memory refs to addresses that vary
2350 in the rtx X. */
2352 static int
2355 rtx x;
2356 {
2367 {
2384 }
2389 {
2393 {
2397 }
2398 }
2400 }
2401 \f
2402 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2403 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2404 `unknown_address_altered', `unknown_constant_address_altered', and
2405 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2406 list `store_mems' in LOOP. */
2408 static void
2411 {
2413 rtx insn;
2417 /* The label after END. Jumping here is just like falling off the
2418 end of the loop. We use next_nonnote_insn instead of next_label
2419 as a hedge against the (pathological) case where some actual insn
2420 might end up between the two. */
2442 {
2444 {
2447 }
2448 }
2452 {
2454 {
2457 {
2459 /* Count number of loops contained in this one. */
2461 }
2468 {
2471 }
2479 {
2483 {
2487 {
2490 }
2491 else
2492 {
2495 }
2497 do
2498 {
2500 {
2502 {
2503 /* Something tricky. */
2506 }
2509 {
2510 /* A jump outside the current loop. */
2513 }
2514 }
2518 }
2520 }
2521 else
2522 {
2523 /* A return, or something tricky. */
2525 }
2526 }
2527 /* FALLTHRU */
2548 }
2549 }
2551 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2553 anywhere. */
2555 /* We don't want loads for MEMs moved to a location before the
2556 one at which their stack memory becomes allocated. (Note
2557 that this is not a problem for malloc, etc., since those
2558 require actual function calls. */
2559 && ! current_function_calls_alloca
2560 /* There are ways to leave the loop other than falling off the
2561 end. */
2567 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2568 that loop_invariant_p and load_mems can use true_dependence
2569 to determine what is really clobbered. */
2571 {
2574 loop_info->store_mems
2576 }
2578 {
2582 loop_info->store_mems
2584 }
2585 }
2586 \f
2587 /* Scan the function looking for loops. Record the start and end of each loop.
2588 Also mark as invalid loops any loops that contain a setjmp or are branched
2589 to from outside the loop. */
2591 static void
2593 rtx f;
2595 {
2596 rtx insn;
2597 rtx label;
2607 /* If there are jumps to undefined labels,
2608 treat them as jumps out of any/all loops.
2609 This also avoids writing past end of tables when there are no loops. */
2612 /* Find boundaries of loops, mark which loops are contained within
2613 loops, and invalidate loops that have setjmp. */
2618 {
2621 {
2625 num_loops++;
2649 }
2653 {
2654 /* In this case, we must invalidate our current loop and any
2655 enclosing loop. */
2657 {
2663 }
2664 }
2666 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2667 enclosing loop, but this doesn't matter. */
2669 }
2671 /* Any loop containing a label used in an initializer must be invalidated,
2672 because it can be jumped into from anywhere. */
2675 {
2679 }
2681 /* Any loop containing a label used for an exception handler must be
2682 invalidated, because it can be jumped into from anywhere. */
2685 {
2689 }
2691 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2692 loop that it is not contained within, that loop is marked invalid.
2693 If any INSN or CALL_INSN uses a label's address, then the loop containing
2694 that label is marked invalid, because it could be jumped into from
2695 anywhere.
2697 Also look for blocks of code ending in an unconditional branch that
2698 exits the loop. If such a block is surrounded by a conditional
2699 branch around the block, move the block elsewhere (see below) and
2700 invert the jump to point to the code block. This may eliminate a
2701 label in our loop and will simplify processing by both us and a
2702 possible second cse pass. */
2706 {
2710 {
2713 {
2717 }
2718 }
2725 /* See if this is an unconditional branch outside the loop. */
2733 {
2734 rtx p;
2740 /* Go backwards until we reach the start of the loop, a label,
2741 or a JUMP_INSN. */
2748 ;
2750 /* Check for the case where we have a jump to an inner nested
2751 loop, and do not perform the optimization in that case. */
2754 {
2757 {
2762 }
2763 }
2765 /* Make sure that the target of P is within the current loop. */
2771 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2772 we have a block of code to try to move.
2774 We look backward and then forward from the target of INSN
2775 to find a BARRIER at the same loop depth as the target.
2776 If we find such a BARRIER, we make a new label for the start
2777 of the block, invert the jump in P and point it to that label,
2778 and move the block of code to the spot we found. */
2783 /* Just ignore jumps to labels that were never emitted.
2784 These always indicate compilation errors. */
2788 /* If it's not safe to move the sequence, then we
2789 mustn't try. */
2792 {
2793 rtx target
2797 rtx tmp;
2799 /* Search for possible garbage past the conditional jumps
2800 and look for the last barrier. */
2808 /* Don't move things inside a tablejump. */
2821 /* Don't move things inside a tablejump. */
2832 {
2836 /* Ensure our label doesn't go away. */
2839 /* Verify that uid_loop is large enough and that
2840 we can invert P. */
2842 {
2845 /* If no suitable BARRIER was found, create a suitable
2846 one before TARGET. Since TARGET is a fall through
2847 path, we'll need to insert an jump around our block
2848 and add a BARRIER before TARGET.
2850 This creates an extra unconditional jump outside
2851 the loop. However, the benefits of removing rarely
2852 executed instructions from inside the loop usually
2853 outweighs the cost of the extra unconditional jump
2854 outside the loop. */
2856 {
2857 rtx temp;
2864 }
2866 /* Include the BARRIER after INSN and copy the
2867 block after LOC. */
2872 /* All those insns are now in TARGET_LOOP. */
2878 /* The label jumped to by INSN is no longer a loop
2879 exit. Unless INSN does not have a label (e.g.,
2880 it is a RETURN insn), search loop->exit_labels
2881 to find its label_ref, and remove it. Also turn
2882 off LABEL_OUTSIDE_LOOP_P bit. */
2884 {
2886 r;
2889 {
2893 else
2896 }
2902 /* If we didn't find it, then something is
2903 wrong. */
2906 }
2908 /* P is now a jump outside the loop, so it must be put
2909 in loop->exit_labels, and marked as such.
2910 The easiest way to do this is to just call
2911 mark_loop_jump again for P. */
2914 /* If INSN now jumps to the insn after it,
2915 delete INSN. */
2920 }
2922 /* Continue the loop after where the conditional
2923 branch used to jump, since the only branch insn
2924 in the block (if it still remains) is an inter-loop
2925 branch and hence needs no processing. */
2931 /* This loop will be continued with NEXT_INSN (insn). */
2933 }
2934 }
2935 }
2936 }
2937 }
2939 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2940 loops it is contained in, mark the target loop invalid.
2942 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2944 static void
2946 rtx x;
2948 {
2954 {
2966 /* There could be a label reference in here. */
2978 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2990 /* Link together all labels that branch outside the loop. This
2991 is used by final_[bg]iv_value and the loop unrolling code. Also
2992 mark this LABEL_REF so we know that this branch should predict
2993 false. */
2995 /* A check to make sure the label is not in an inner nested loop,
2996 since this does not count as a loop exit. */
2998 {
3003 }
3004 else
3008 {
3017 }
3019 /* If this is inside a loop, but not in the current loop or one enclosed
3020 by it, it invalidates at least one loop. */
3025 /* We must invalidate every nested loop containing the target of this
3026 label, except those that also contain the jump insn. */
3029 {
3030 /* Stop when we reach a loop that also contains the jump insn. */
3035 /* If we get here, we know we need to invalidate a loop. */
3042 }
3046 /* If this is not setting pc, ignore. */
3068 /* Strictly speaking this is not a jump into the loop, only a possible
3069 jump out of the loop. However, we have no way to link the destination
3070 of this jump onto the list of exit labels. To be safe we mark this
3071 loop and any containing loops as invalid. */
3073 {
3075 {
3081 }
3082 }
3084 }
3085 }
3086 \f
3087 /* Return nonzero if there is a label in the range from
3088 insn INSN to and including the insn whose luid is END
3089 INSN must have an assigned luid (i.e., it must not have
3090 been previously created by loop.c). */
3092 static int
3094 rtx insn;
3096 {
3098 {
3102 }
3105 }
3107 /* Record that a memory reference X is being set. */
3109 static void
3111 rtx x;
3112 rtx y ATTRIBUTE_UNUSED;
3114 {
3120 /* Count number of memory writes.
3121 This affects heuristics in strength_reduce. */
3124 /* BLKmode MEM means all memory is clobbered. */
3126 {
3129 else
3133 }
3137 }
3139 /* X is a value modified by an INSN that references a biv inside a loop
3140 exit test (ie, X is somehow related to the value of the biv). If X
3141 is a pseudo that is used more than once, then the biv is (effectively)
3142 used more than once. DATA is a pointer to a loop_regs structure. */
3144 static void
3146 rtx x;
3147 rtx y ATTRIBUTE_UNUSED;
3149 {
3164 /* If we do not have usage information, or if we know the register
3165 is used more than once, note that fact for check_dbra_loop. */
3170 }
3171 \f
3172 /* Return nonzero if the rtx X is invariant over the current loop.
3174 The value is 2 if we refer to something only conditionally invariant.
3176 A memory ref is invariant if it is not volatile and does not conflict
3177 with anything stored in `loop_info->store_mems'. */
3179 int
3182 rtx x;
3183 {
3190 rtx mem_list_entry;
3196 {
3204 /* A LABEL_REF is normally invariant, however, if we are unrolling
3205 loops, and this label is inside the loop, then it isn't invariant.
3206 This is because each unrolled copy of the loop body will have
3207 a copy of this label. If this was invariant, then an insn loading
3208 the address of this label into a register might get moved outside
3209 the loop, and then each loop body would end up using the same label.
3211 We don't know the loop bounds here though, so just fail for all
3212 labels. */
3215 else
3224 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3225 since the reg might be set by initialization within the loop. */
3242 /* Volatile memory references must be rejected. Do this before
3243 checking for read-only items, so that volatile read-only items
3244 will be rejected also. */
3248 /* See if there is any dependence between a store and this load. */
3251 {
3257 }
3259 /* It's not invalidated by a store in memory
3260 but we must still verify the address is invariant. */
3264 /* Don't mess with insns declared volatile. */
3271 }
3275 {
3277 {
3283 }
3285 {
3288 {
3294 }
3296 }
3297 }
3300 }
3301 \f
3302 /* Return nonzero if all the insns in the loop that set REG
3303 are INSN and the immediately following insns,
3304 and if each of those insns sets REG in an invariant way
3305 (not counting uses of REG in them).
3307 The value is 2 if some of these insns are only conditionally invariant.
3309 We assume that INSN itself is the first set of REG
3310 and that its source is invariant. */
3312 static int
3317 {
3321 rtx temp;
3322 /* Number of sets we have to insist on finding after INSN. */
3328 /* If N_SETS hit the limit, we can't rely on its value. */
3335 {
3337 rtx set;
3342 /* If library call, skip to end of it. */
3351 {
3356 {
3357 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3358 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3359 notes are OK. */
3365 }
3366 }
3368 count--;
3370 {
3373 }
3374 }
3377 /* If loop_invariant_p ever returned 2, we return 2. */
3379 }
3381 #if 0
3382 /* I don't think this condition is sufficient to allow INSN
3383 to be moved, so we no longer test it. */
3385 /* Return 1 if all insns in the basic block of INSN and following INSN
3386 that set REG are invariant according to TABLE. */
3388 static int
3392 {
3397 {
3406 {
3409 }
3410 }
3411 }
3413 \f
3414 /* Look at all uses (not sets) of registers in X. For each, if it is
3415 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3416 a different insn, set USAGE[REGNO] to const0_rtx. */
3418 static void
3421 rtx insn;
3422 rtx x;
3423 {
3435 {
3436 /* Don't count SET_DEST if it is a REG; otherwise count things
3437 in SET_DEST because if a register is partially modified, it won't
3438 show up as a potential movable so we don't care how USAGE is set
3439 for it. */
3443 }
3444 else
3446 {
3452 }
3453 }
3454 \f
3455 /* Count and record any set in X which is contained in INSN. Update
3456 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3457 in X. */
3459 static void
3464 {
3466 /* Don't move a reg that has an explicit clobber.
3467 It's not worth the pain to try to do it correctly. */
3471 {
3479 {
3483 {
3484 /* If this is the first setting of this reg
3485 in current basic block, and it was set before,
3486 it must be set in two basic blocks, so it cannot
3487 be moved out of the loop. */
3491 /* If this is not first setting in current basic block,
3492 see if reg was used in between previous one and this.
3493 If so, neither one can be moved. */
3500 }
3501 }
3502 }
3503 }
3504 \f
3505 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3506 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3507 contained in insn INSN is used by any insn that precedes INSN in
3508 cyclic order starting from the loop entry point.
3510 We don't want to use INSN_LUID here because if we restrict INSN to those
3511 that have a valid INSN_LUID, it means we cannot move an invariant out
3512 from an inner loop past two loops. */
3514 static int
3518 {
3520 rtx p;
3522 /* Scan forward checking for register usage. If we hit INSN, we
3523 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3525 {
3531 }
3534 }
3535 \f
3537 /* Information we collect about arrays that we might want to prefetch. */
3538 struct prefetch_info
3539 {
3543 index. */
3544 HOST_WIDE_INT index;
3546 iteration. */
3548 prefetch area in one iteration. */
3550 This is set only for loops with known
3551 iteration counts and is 0xffffffff
3552 otherwise. */
3555 /* 1 for those chosen for prefetching. */
3557 /* 1 for those chosen for prefetching. */
3558 };
3560 /* Data used by check_store function. */
3561 struct check_store_data
3562 {
3563 rtx mem_address;
3565 };
3571 /* Set mem_write when mem_address is found. Used as callback to
3572 note_stores. */
3573 static void
3577 {
3582 }
3583 \f
3584 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3585 important to get some addresses combined. Later more sophisticated
3586 transformations can be added when necesary.
3588 ??? Same trick with swapping operand is done at several other places.
3589 It can be nice to develop some common way to handle this. */
3591 static int
3594 {
3608 {
3613 }
3614 /* Compare the elements. If any pair of corresponding elements fails to
3615 match, return 0 for the whole thing. */
3619 {
3621 {
3633 /* Two vectors must have the same length. */
3637 /* And the corresponding elements must match. */
3655 /* These are just backpointers, so they don't matter. */
3661 /* It is believed that rtx's at this level will never
3662 contain anything but integers and other rtx's,
3663 except for within LABEL_REFs and SYMBOL_REFs. */
3666 }
3667 }
3669 }
3670 \f
3671 /* Remove constant addition value from the expression X (when present)
3672 and return it. */
3674 static HOST_WIDE_INT
3677 {
3684 {
3687 }
3689 /* For plus expression recurse on ourself. */
3691 {
3695 /* In case our parameter was constant, remove extra zero from the
3696 expression. */
3701 }
3704 }
3706 /* Attempt to identify accesses to arrays that are most likely to cause cache
3707 misses, and emit prefetch instructions a few prefetch blocks forward.
3709 To detect the arrays we use the GIV information that was collected by the
3710 strength reduction pass.
3712 The prefetch instructions are generated after the GIV information is done
3713 and before the strength reduction process. The new GIVs are injected into
3714 the strength reduction tables, so the prefetch addresses are optimized as
3715 well.
3717 GIVs are split into base address, stride, and constant addition values.
3718 GIVs with the same address, stride and close addition values are combined
3719 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3720 for write instructions can be used for the block we write to, on machines
3721 that support write prefetches.
3723 Several heuristics are used to determine when to prefetch. They are
3724 controlled by defined symbols that can be overridden for each target. */
3726 static void
3729 {
3743 /* Consider only loops w/o calls. When a call is done, the loop is probably
3744 slow enough to read the memory. */
3746 {
3751 }
3756 {
3761 }
3763 /* Search all induction variables and pick those interesting for the prefetch
3764 machinery. */
3766 {
3772 /* Expect all BIVs to be executed in each iteration. This makes our
3773 analysis more conservative. */
3775 {
3776 /* Discard non-constant additions that we can't handle well yet, and
3777 BIVs that are executed multiple times; such BIVs ought to be
3778 handled in the nested loop. We accept not_every_iteration BIVs,
3779 since these only result in larger strides and make our
3780 heuristics more conservative.
3781 ??? What does the last sentence mean? */
3783 {
3785 {
3791 }
3793 }
3796 {
3798 {
3804 }
3806 }
3810 }
3816 {
3817 rtx address;
3818 rtx temp;
3821 HOST_WIDE_INT stride;
3825 /* There are several reasons why an induction variable is not
3826 interesting to us. */
3828 /* We are interested only in constant stride memory references
3829 in order to be able to compute density easily. */
3831 /* Don't handle reversed order prefetches, since they are usually
3832 ineffective. Later we may be able to reverse such BIVs. */
3833 || (PREFETCH_NO_REVERSE_ORDER
3835 /* Prefetching of accesses with such an extreme stride is probably
3836 not worthwhile, either. */
3837 || (PREFETCH_NO_EXTREME_STRIDE
3839 /* Ignore GIVs with varying add values; we can't predict the
3840 value for the next iteration. */
3842 /* Ignore GIVs in the nested loops; they ought to have been
3843 handled already. */
3845 {
3850 }
3852 /* Determine the pointer to the basic array we are examining. It is
3853 the sum of the BIV's initial value and the GIV's add_val. */
3866 /* When the GIV is not always executed, we might be better off by
3867 not dirtying the cache pages. */
3871 /* Attempt to find another prefetch to the same array and see if we
3872 can merge this one. */
3876 {
3877 /* In case both access same array (same location
3878 just with small difference in constant indexes), merge
3879 the prefetches. Just do the later and the earlier will
3880 get prefetched from previous iteration.
3881 4096 is artificial threshold. It should not be too small,
3882 but also not bigger than small portion of memory usually
3883 traversed by single loop. */
3885 {
3894 }
3897 {
3902 }
3903 }
3905 /* Merging failed. */
3907 {
3915 num_prefetches++;
3917 {
3922 }
3923 }
3924 }
3925 }
3928 {
3929 /* Attempt to calculate the number of bytes fetched by the loop.
3930 Avoid overflow. */
3935 else
3938 /* Prefetch is worthwhile only when the loads/stores are dense. */
3943 {
3948 }
3949 else
3953 {
3957 num_real_write_prefetches
3959 }
3960 }
3963 {
3965 {
3980 }
3984 }
3995 {
3997 {
4002 {
4004 rtx insn;
4009 /* We can save some effort by offsetting the address on
4010 architectures with offsettable memory references. */
4013 else
4014 {
4020 }
4024 before_insn);
4026 /* Check all insns emitted and record the new GIV
4027 information. */
4030 {
4035 }
4036 }
4037 }
4040 {
4043 /* Emit INSNs before the loop to fetch the first cache lines. */
4047 {
4059 loop_start);
4060 }
4061 }
4062 }
4065 }
4066 \f
4067 /* A "basic induction variable" or biv is a pseudo reg that is set
4068 (within this loop) only by incrementing or decrementing it. */
4069 /* A "general induction variable" or giv is a pseudo reg whose
4070 value is a linear function of a biv. */
4072 /* Bivs are recognized by `basic_induction_var';
4073 Givs by `general_induction_var'. */
4075 /* Communication with routines called via `note_stores'. */
4079 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4083 /* ??? Unfinished optimizations, and possible future optimizations,
4084 for the strength reduction code. */
4086 /* ??? The interaction of biv elimination, and recognition of 'constant'
4087 bivs, may cause problems. */
4089 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4090 performance problems.
4092 Perhaps don't eliminate things that can be combined with an addressing
4093 mode. Find all givs that have the same biv, mult_val, and add_val;
4094 then for each giv, check to see if its only use dies in a following
4095 memory address. If so, generate a new memory address and check to see
4096 if it is valid. If it is valid, then store the modified memory address,
4097 otherwise, mark the giv as not done so that it will get its own iv. */
4099 /* ??? Could try to optimize branches when it is known that a biv is always
4100 positive. */
4102 /* ??? When replace a biv in a compare insn, we should replace with closest
4103 giv so that an optimized branch can still be recognized by the combiner,
4104 e.g. the VAX acb insn. */
4106 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4107 was rerun in loop_optimize whenever a register was added or moved.
4108 Also, some of the optimizations could be a little less conservative. */
4109 \f
4110 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4111 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4112 callback.
4114 NOT_EVERY_ITERATION if current insn is not executed at least once for every
4115 loop iteration except for the last one.
4117 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4118 loop iteration.
4119 */
4120 void
4123 loop_insn_callback fncall;
4124 {
4125 /* This is 1 if current insn is not executed at least once for every loop
4126 iteration. */
4131 rtx p;
4133 /* If loop_scan_start points to the loop exit test, we have to be wary of
4134 subversive use of gotos inside expression statements. */
4138 /* Scan through loop to find all possible bivs. */
4143 {
4146 /* Past CODE_LABEL, we get to insns that may be executed multiple
4147 times. The only way we can be sure that they can't is if every
4148 jump insn between here and the end of the loop either
4149 returns, exits the loop, is a jump to a location that is still
4150 behind the label, or is a jump to the loop start. */
4153 {
4159 {
4164 {
4167 else
4171 }
4179 {
4182 }
4183 }
4184 }
4186 /* Past a jump, we get to insns for which we can't count
4187 on whether they will be executed during each iteration. */
4188 /* This code appears twice in strength_reduce. There is also similar
4189 code in scan_loop. */
4191 /* If we enter the loop in the middle, and scan around to the
4192 beginning, don't set not_every_iteration for that.
4193 This can be any kind of jump, since we want to know if insns
4194 will be executed if the loop is executed. */
4199 {
4202 /* If this is a jump outside the loop, then it also doesn't
4203 matter. Check to see if the target of this branch is on the
4204 loop->exits_labels list. */
4212 }
4215 {
4216 /* At the virtual top of a converted loop, insns are again known to
4217 be executed each iteration: logically, the loop begins here
4218 even though the exit code has been duplicated.
4220 Insns are also again known to be executed each iteration at
4221 the LOOP_CONT note. */
4227 loop_depth++;
4229 loop_depth--;
4230 }
4232 /* Note if we pass a loop latch. If we do, then we can not clear
4233 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4234 a loop since a jump before the last CODE_LABEL may have started
4235 a new loop iteration.
4237 Note that LOOP_TOP is only set for rotated loops and we need
4238 this check for all loops, so compare against the CODE_LABEL
4239 which immediately follows LOOP_START. */
4244 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4245 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4246 or not an insn is known to be executed each iteration of the
4247 loop, whether or not any iterations are known to occur.
4249 Therefore, if we have just passed a label and have no more labels
4250 between here and the test insn of the loop, and we have not passed
4251 a jump to the top of the loop, then we know these insns will be
4252 executed each iteration. */
4255 && !past_loop_latch
4260 }
4261 }
4262 \f
4263 static void
4266 {
4269 /* Temporary list pointers for traversing ivs->list. */
4276 /* Scan ivs->list to remove all regs that proved not to be bivs.
4277 Make a sanity check against regs->n_times_set. */
4279 {
4281 /* Above happens if register modified by subreg, etc. */
4282 /* Make sure it is not recognized as a basic induction var: */
4284 /* If never incremented, it is invariant that we decided not to
4285 move. So leave it alone. */
4287 {
4298 }
4299 else
4300 {
4305 }
4306 }
4307 }
4310 /* Determine how BIVS are initialised by looking through pre-header
4311 extended basic block. */
4312 static void
4315 {
4317 /* Temporary list pointers for traversing ivs->list. */
4320 rtx p;
4322 /* Find initial value for each biv by searching backwards from loop_start,
4323 halting at first label. Also record any test condition. */
4327 {
4328 rtx test;
4338 /* Record any test of a biv that branches around the loop if no store
4339 between it and the start of loop. We only care about tests with
4340 constants and registers and only certain of those. */
4350 {
4351 /* If an NE test, we have an initial value! */
4353 {
4357 }
4358 else
4360 }
4361 }
4362 }
4365 /* Look at the each biv and see if we can say anything better about its
4366 initial value from any initializing insns set up above. (This is done
4367 in two passes to avoid missing SETs in a PARALLEL.) */
4368 static void
4371 {
4373 /* Temporary list pointers for traversing ivs->list. */
4378 {
4379 rtx src;
4380 rtx note;
4385 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4386 is a constant, use the value of that. */
4392 else
4405 {
4409 {
4412 }
4413 }
4414 /* If we can't make it a giv,
4415 let biv keep initial value of "itself". */
4418 }
4419 }
4422 /* Search the loop for general induction variables. */
4424 static void
4427 {
4429 }
4432 /* For each giv for which we still don't know whether or not it is
4433 replaceable, check to see if it is replaceable because its final value
4434 can be calculated. */
4436 static void
4439 {
4444 {
4450 }
4451 }
4454 /* Return non-zero if it is possible to eliminate the biv BL provided
4455 all givs are reduced. This is possible if either the reg is not
4456 used outside the loop, or we can compute what its final value will
4457 be. */
4459 static int
4465 {
4466 /* For architectures with a decrement_and_branch_until_zero insn,
4467 don't do this if we put a REG_NONNEG note on the endtest for this
4468 biv. */
4470 #ifdef HAVE_decrement_and_branch_until_zero
4472 {
4477 }
4478 #endif
4480 /* Check that biv is used outside loop or if it has a final value.
4481 Compare against bl->init_insn rather than loop->start. We aren't
4482 concerned with any uses of the biv between init_insn and
4483 loop->start since these won't be affected by the value of the biv
4484 elsewhere in the function, so long as init_insn doesn't use the
4485 biv itself. */
4496 {
4504 }
4506 }
4509 /* Reduce each giv of BL that we have decided to reduce. */
4511 static void
4515 {
4519 {
4522 {
4525 /* If the code for derived givs immediately below has already
4526 allocated a new_reg, we must keep it. */
4530 #ifdef AUTO_INC_DEC
4531 /* If the target has auto-increment addressing modes, and
4532 this is an address giv, then try to put the increment
4533 immediately after its use, so that flow can create an
4534 auto-increment addressing mode. */
4537 /* We don't handle reversed biv's because bl->biv->insn
4538 does not have a valid INSN_LUID. */
4542 {
4543 /* If other giv's have been combined with this one, then
4544 this will work only if all uses of the other giv's occur
4545 before this giv's insn. This is difficult to check.
4547 We simplify this by looking for the common case where
4548 there is one DEST_REG giv, and this giv's insn is the
4549 last use of the dest_reg of that DEST_REG giv. If the
4550 increment occurs after the address giv, then we can
4551 perform the optimization. (Otherwise, the increment
4552 would have to go before other_giv, and we would not be
4553 able to combine it with the address giv to get an
4554 auto-inc address.) */
4556 {
4561 {
4564 else
4566 }
4573 }
4574 /* Check for case where increment is before the address
4575 giv. Do this test in "loop order". */
4584 else
4587 #ifdef HAVE_cc0
4588 {
4589 rtx prev;
4591 /* We can't put an insn immediately after one setting
4592 cc0, or immediately before one using cc0. */
4599 }
4600 #endif
4604 }
4605 #endif
4607 /* For each place where the biv is incremented, add an insn
4608 to increment the new, reduced reg for the giv. */
4610 {
4611 rtx insert_before;
4617 else
4625 /* A multiply is acceptable here
4626 since this is presumed to be seldom executed. */
4630 }
4632 /* Add code at loop start to initialize giv's reduced reg. */
4637 }
4638 }
4639 }
4642 /* Check for givs whose first use is their definition and whose
4643 last use is the definition of another giv. If so, it is likely
4644 dead and should not be used to derive another giv nor to
4645 eliminate a biv. */
4647 static void
4651 {
4655 {
4662 {
4668 }
4669 }
4670 }
4673 static void
4678 {
4682 {
4689 /* Update expression if this was combined, in case other giv was
4690 replaced. */
4695 /* See if this register is known to be a pointer to something. If
4696 so, see if we can find the alignment. First see if there is a
4697 destination register that is a pointer. If so, this shares the
4698 alignment too. Next see if we can deduce anything from the
4699 computational information. If not, and this is a DEST_ADDR
4700 giv, at least we know that it's a pointer, though we don't know
4701 the alignment. */
4709 {
4718 }
4722 {
4730 }
4735 /* Store reduced reg as the address in the memref where we found
4736 this giv. */
4739 {
4741 }
4742 else
4743 {
4744 /* Not replaceable; emit an insn to set the original giv reg from
4745 the reduced giv, same as above. */
4748 }
4750 /* When a loop is reversed, givs which depend on the reversed
4751 biv, and which are live outside the loop, must be set to their
4752 correct final value. This insn is only needed if the giv is
4753 not replaceable. The correct final value is the same as the
4754 value that the giv starts the reversed loop with. */
4764 {
4769 }
4770 }
4771 }
4774 static int
4779 rtx test_reg;
4780 {
4789 /* Reduce benefit if not replaceable, since we will insert a
4790 move-insn to replace the insn that calculates this giv. Don't do
4791 this unless the giv is a user variable, since it will often be
4792 marked non-replaceable because of the duplication of the exit
4793 code outside the loop. In such a case, the copies we insert are
4794 dead and will be deleted. So they don't have a cost. Similar
4795 situations exist. */
4796 /* ??? The new final_[bg]iv_value code does a much better job of
4797 finding replaceable giv's, and hence this code may no longer be
4798 necessary. */
4803 /* Decrease the benefit to count the add-insns that we will insert
4804 to increment the reduced reg for the giv. ??? This can
4805 overestimate the run-time cost of the additional insns, e.g. if
4806 there are multiple basic blocks that increment the biv, but only
4807 one of these blocks is executed during each iteration. There is
4808 no good way to detect cases like this with the current structure
4809 of the loop optimizer. This code is more accurate for
4810 determining code size than run-time benefits. */
4813 /* Decide whether to strength-reduce this giv or to leave the code
4814 unchanged (recompute it from the biv each time it is used). This
4815 decision can be made independently for each giv. */
4817 #ifdef AUTO_INC_DEC
4818 /* Attempt to guess whether autoincrement will handle some of the
4819 new add insns; if so, increase BENEFIT (undo the subtraction of
4820 add_cost that was done above). */
4822 /* Increasing the benefit is risky, since this is only a guess.
4823 Avoid increasing register pressure in cases where there would
4824 be no other benefit from reducing this giv. */
4827 {
4842 }
4843 #endif
4846 }
4849 /* Free IV structures for LOOP. */
4851 static void
4854 {
4861 {
4867 {
4870 }
4872 {
4875 }
4879 }
4880 }
4883 /* Perform strength reduction and induction variable elimination.
4885 Pseudo registers created during this function will be beyond the
4886 last valid index in several tables including
4887 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4888 problem here, because the added registers cannot be givs outside of
4889 their loop, and hence will never be reconsidered. But scan_loop
4890 must check regnos to make sure they are in bounds. */
4892 static void
4896 {
4900 rtx p;
4901 /* Temporary list pointer for traversing ivs->list. */
4903 /* Ratio of extra register life span we can justify
4904 for saving an instruction. More if loop doesn't call subroutines
4905 since in that case saving an insn makes more difference
4906 and more registers are available. */
4907 /* ??? could set this to last value of threshold in move_movables */
4909 /* Map of pseudo-register replacements. */
4921 /* Find all BIVs in loop. */
4924 /* Exit if there are no bivs. */
4926 {
4927 /* Can still unroll the loop anyways, but indicate that there is no
4928 strength reduction info available. */
4934 }
4936 /* Determine how BIVS are initialised by looking through pre-header
4937 extended basic block. */
4940 /* Look at the each biv and see if we can say anything better about its
4941 initial value from any initializing insns set up above. */
4944 /* Search the loop for general induction variables. */
4947 /* Try to calculate and save the number of loop iterations. This is
4948 set to zero if the actual number can not be calculated. This must
4949 be called after all giv's have been identified, since otherwise it may
4950 fail if the iteration variable is a giv. */
4953 #ifdef HAVE_prefetch
4956 #endif
4958 /* Now for each giv for which we still don't know whether or not it is
4959 replaceable, check to see if it is replaceable because its final value
4960 can be calculated. This must be done after loop_iterations is called,
4961 so that final_giv_value will work correctly. */
4964 /* Try to prove that the loop counter variable (if any) is always
4965 nonnegative; if so, record that fact with a REG_NONNEG note
4966 so that "decrement and branch until zero" insn can be used. */
4969 /* Create reg_map to hold substitutions for replaceable giv regs.
4970 Some givs might have been made from biv increments, so look at
4971 ivs->reg_iv_type for a suitable size. */
4975 /* Examine each iv class for feasibility of strength reduction/induction
4976 variable elimination. */
4979 {
4983 /* Test whether it will be possible to eliminate this biv
4984 provided all givs are reduced. */
4987 /* This will be true at the end, if all givs which depend on this
4988 biv have been strength reduced.
4989 We can't (currently) eliminate the biv unless this is so. */
4992 /* Check each extension dependent giv in this class to see if its
4993 root biv is safe from wrapping in the interior mode. */
4996 /* Combine all giv's for this iv_class. */
5000 {
5008 /* If an insn is not to be strength reduced, then set its ignore
5009 flag, and clear bl->all_reduced. */
5011 /* A giv that depends on a reversed biv must be reduced if it is
5012 used after the loop exit, otherwise, it would have the wrong
5013 value after the loop exit. To make it simple, just reduce all
5014 of such giv's whether or not we know they are used after the loop
5015 exit. */
5020 {
5028 }
5029 else
5030 {
5031 /* Check that we can increment the reduced giv without a
5032 multiply insn. If not, reject it. */
5037 {
5045 }
5046 }
5047 }
5049 /* Check for givs whose first use is their definition and whose
5050 last use is the definition of another giv. If so, it is likely
5051 dead and should not be used to derive another giv nor to
5052 eliminate a biv. */
5055 /* Reduce each giv that we decided to reduce. */
5058 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5059 as not reduced.
5061 For each giv register that can be reduced now: if replaceable,
5062 substitute reduced reg wherever the old giv occurs;
5063 else add new move insn "giv_reg = reduced_reg". */
5066 /* All the givs based on the biv bl have been reduced if they
5067 merit it. */
5069 /* For each giv not marked as maybe dead that has been combined with a
5070 second giv, clear any "maybe dead" mark on that second giv.
5071 v->new_reg will either be or refer to the register of the giv it
5072 combined with.
5074 Doing this clearing avoids problems in biv elimination where
5075 a giv's new_reg is a complex value that can't be put in the
5076 insn but the giv combined with (with a reg as new_reg) is
5077 marked maybe_dead. Since the register will be used in either
5078 case, we'd prefer it be used from the simpler giv. */
5084 /* Try to eliminate the biv, if it is a candidate.
5085 This won't work if ! bl->all_reduced,
5086 since the givs we planned to use might not have been reduced.
5088 We have to be careful that we didn't initially think we could
5089 eliminate this biv because of a giv that we now think may be
5090 dead and shouldn't be used as a biv replacement.
5092 Also, there is the possibility that we may have a giv that looks
5093 like it can be used to eliminate a biv, but the resulting insn
5094 isn't valid. This can happen, for example, on the 88k, where a
5095 JUMP_INSN can compare a register only with zero. Attempts to
5096 replace it with a compare with a constant will fail.
5098 Note that in cases where this call fails, we may have replaced some
5099 of the occurrences of the biv with a giv, but no harm was done in
5100 doing so in the rare cases where it can occur. */
5104 {
5105 /* ?? If we created a new test to bypass the loop entirely,
5106 or otherwise drop straight in, based on this test, then
5107 we might want to rewrite it also. This way some later
5108 pass has more hope of removing the initialization of this
5109 biv entirely. */
5111 /* If final_value != 0, then the biv may be used after loop end
5112 and we must emit an insn to set it just in case.
5114 Reversed bivs already have an insn after the loop setting their
5115 value, so we don't need another one. We can't calculate the
5116 proper final value for such a biv here anyways. */
5124 }
5125 }
5127 /* Go through all the instructions in the loop, making all the
5128 register substitutions scheduled in REG_MAP. */
5133 {
5137 }
5140 {
5141 /* When we completely unroll a loop we will likely not need the increment
5142 of the loop BIV and we will not need the conditional branch at the
5143 end of the loop. */
5146 #ifdef HAVE_cc0
5147 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5148 need the comparison before the conditional branch at the end of the
5149 loop. */
5151 #endif
5153 /* We'll need one copy for each loop iteration. */
5156 /* A little slop to account for the ability to remove initialization
5157 code, better CSE, and other secondary benefits of completely
5158 unrolling some loops. */
5161 /* Clamp the value. */
5164 }
5166 /* Unroll loops from within strength reduction so that we can use the
5167 induction variable information that strength_reduce has already
5168 collected. Always unroll loops that would be as small or smaller
5169 unrolled than when rolled. */
5175 #ifdef HAVE_doloop_end
5180 /* In case number of iterations is known, drop branch prediction note
5181 in the branch. Do that only in second loop pass, as loop unrolling
5182 may change the number of iterations performed. */
5185 {
5188 PRED_LOOP_ITERATIONS,
5190 }
5198 }
5199 \f
5200 /*Record all basic induction variables calculated in the insn. */
5201 static rtx
5204 rtx p;
5207 {
5209 rtx set;
5210 rtx dest_reg;
5211 rtx inc_val;
5212 rtx mult_val;
5218 {
5223 {
5228 {
5229 /* It is a possible basic induction variable.
5230 Create and initialize an induction structure for it. */
5238 }
5241 }
5242 }
5244 }
5245 \f
5246 /* Record all givs calculated in the insn.
5247 A register is a giv if: it is only set once, it is a function of a
5248 biv and a constant (or invariant), and it is not a biv. */
5249 static rtx
5252 rtx p;
5255 {
5258 rtx set;
5259 /* Look for a general induction variable in a register. */
5264 {
5265 rtx src_reg;
5266 rtx dest_reg;
5267 rtx add_val;
5268 rtx mult_val;
5269 rtx ext_val;
5272 rtx last_consec_insn;
5281 /* Equivalent expression is a giv. */
5286 /* Don't try to handle any regs made by loop optimization.
5287 We have nothing on them in regno_first_uid, etc. */
5289 /* Don't recognize a BASIC_INDUCT_VAR here. */
5291 /* This must be the only place where the register is set. */
5293 /* or all sets must be consecutive and make a giv. */
5298 {
5302 /* If this is a library call, increase benefit. */
5306 /* Skip the consecutive insns, if there are any. */
5314 }
5315 }
5317 #ifndef DONT_REDUCE_ADDR
5318 /* Look for givs which are memory addresses. */
5319 /* This resulted in worse code on a VAX 8600. I wonder if it
5320 still does. */
5323 maybe_multiple);
5324 #endif
5326 /* Update the status of whether giv can derive other givs. This can
5327 change when we pass a label or an insn that updates a biv. */
5332 }
5333 \f
5334 /* Return 1 if X is a valid source for an initial value (or as value being
5335 compared against in an initial test).
5337 X must be either a register or constant and must not be clobbered between
5338 the current insn and the start of the loop.
5340 INSN is the insn containing X. */
5342 static int
5344 rtx x;
5345 rtx insn;
5347 rtx loop_start;
5348 {
5352 /* Only consider pseudos we know about initialized in insns whose luids
5353 we know. */
5358 /* Don't use call-clobbered registers across a call which clobbers it. On
5359 some machines, don't use any hard registers at all. */
5361 && (SMALL_REGISTER_CLASSES
5365 /* Don't use registers that have been clobbered before the start of the
5366 loop. */
5371 }
5372 \f
5373 /* Scan X for memory refs and check each memory address
5374 as a possible giv. INSN is the insn whose pattern X comes from.
5375 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5376 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5377 more thanonce in each loop iteration. */
5379 static void
5382 rtx x;
5383 rtx insn;
5385 {
5395 {
5411 {
5412 rtx src_reg;
5413 rtx add_val;
5414 rtx mult_val;
5415 rtx ext_val;
5418 /* This code used to disable creating GIVs with mult_val == 1 and
5419 add_val == 0. However, this leads to lost optimizations when
5420 it comes time to combine a set of related DEST_ADDR GIVs, since
5421 this one would not be seen. */
5426 {
5427 /* Found one; record it. */
5436 }
5437 }
5442 }
5444 /* Recursively scan the subexpressions for other mem refs. */
5450 maybe_multiple);
5454 maybe_multiple);
5455 }
5456 \f
5457 /* Fill in the data about one biv update.
5458 V is the `struct induction' in which we record the biv. (It is
5459 allocated by the caller, with alloca.)
5460 INSN is the insn that sets it.
5461 DEST_REG is the biv's reg.
5463 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5464 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5465 being set to INC_VAL.
5467 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5468 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5469 can be executed more than once per iteration. If MAYBE_MULTIPLE
5470 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5471 executed exactly once per iteration. */
5473 static void
5478 rtx insn;
5479 rtx dest_reg;
5480 rtx inc_val;
5481 rtx mult_val;
5485 {
5501 /* Add this to the reg's iv_class, creating a class
5502 if this is the first incrementation of the reg. */
5506 {
5507 /* Create and initialize new iv_class. */
5517 /* Set initial value to the reg itself. */
5520 /* We haven't seen the initializing insn yet */
5530 /* Add this class to ivs->list. */
5534 /* Put it in the array of biv register classes. */
5536 }
5538 /* Update IV_CLASS entry for this biv. */
5547 }
5548 \f
5549 /* Fill in the data about one giv.
5550 V is the `struct induction' in which we record the giv. (It is
5551 allocated by the caller, with alloca.)
5552 INSN is the insn that sets it.
5553 BENEFIT estimates the savings from deleting this insn.
5554 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5555 into a register or is used as a memory address.
5557 SRC_REG is the biv reg which the giv is computed from.
5558 DEST_REG is the giv's reg (if the giv is stored in a reg).
5559 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5560 LOCATION points to the place where this giv's value appears in INSN. */
5562 static void
5567 rtx insn;
5568 rtx src_reg;
5569 rtx dest_reg;
5575 {
5580 rtx temp;
5582 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5583 undo the MULT canonicalization that we performed earlier. */
5613 /* The v->always_computable field is used in update_giv_derive, to
5614 determine whether a giv can be used to derive another giv. For a
5615 DEST_REG giv, INSN computes a new value for the giv, so its value
5616 isn't computable if INSN insn't executed every iteration.
5617 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5618 it does not compute a new value. Hence the value is always computable
5619 regardless of whether INSN is executed each iteration. */
5623 else
5629 {
5632 }
5634 {
5639 /* If the lifetime is zero, it means that this register is
5640 really a dead store. So mark this as a giv that can be
5641 ignored. This will not prevent the biv from being eliminated. */
5647 }
5649 /* Add the giv to the class of givs computed from one biv. */
5653 {
5656 /* Don't count DEST_ADDR. This is supposed to count the number of
5657 insns that calculate givs. */
5661 }
5662 else
5663 /* Fatal error, biv missing for this giv? */
5668 else
5669 {
5670 /* The giv can be replaced outright by the reduced register only if all
5671 of the following conditions are true:
5672 - the insn that sets the giv is always executed on any iteration
5673 on which the giv is used at all
5674 (there are two ways to deduce this:
5675 either the insn is executed on every iteration,
5676 or all uses follow that insn in the same basic block),
5677 - the giv is not used outside the loop
5678 - no assignments to the biv occur during the giv's lifetime. */
5681 /* Previous line always fails if INSN was moved by loop opt. */
5684 && (! not_every_iteration
5686 {
5687 /* Now check that there are no assignments to the biv within the
5688 giv's lifetime. This requires two separate checks. */
5690 /* Check each biv update, and fail if any are between the first
5691 and last use of the giv.
5693 If this loop contains an inner loop that was unrolled, then
5694 the insn modifying the biv may have been emitted by the loop
5695 unrolling code, and hence does not have a valid luid. Just
5696 mark the biv as not replaceable in this case. It is not very
5697 useful as a biv, because it is used in two different loops.
5698 It is very unlikely that we would be able to optimize the giv
5699 using this biv anyways. */
5703 {
5709 {
5713 }
5714 }
5716 /* If there are any backwards branches that go from after the
5717 biv update to before it, then this giv is not replaceable. */
5721 {
5725 }
5726 }
5727 else
5728 {
5729 /* May still be replaceable, we don't have enough info here to
5730 decide. */
5733 }
5734 }
5736 /* Record whether the add_val contains a const_int, for later use by
5737 combine_givs. */
5738 {
5743 ;
5747 {
5749 {
5754 else
5756 }
5759 }
5760 }
5764 }
5766 /* All this does is determine whether a giv can be made replaceable because
5767 its final value can be calculated. This code can not be part of record_giv
5768 above, because final_giv_value requires that the number of loop iterations
5769 be known, and that can not be accurately calculated until after all givs
5770 have been identified. */
5772 static void
5776 {
5783 /* DEST_ADDR givs will never reach here, because they are always marked
5784 replaceable above in record_giv. */
5786 /* The giv can be replaced outright by the reduced register only if all
5787 of the following conditions are true:
5788 - the insn that sets the giv is always executed on any iteration
5789 on which the giv is used at all
5790 (there are two ways to deduce this:
5791 either the insn is executed on every iteration,
5792 or all uses follow that insn in the same basic block),
5793 - its final value can be calculated (this condition is different
5794 than the one above in record_giv)
5795 - it's not used before the it's set
5796 - no assignments to the biv occur during the giv's lifetime. */
5798 #if 0
5799 /* This is only called now when replaceable is known to be false. */
5800 /* Clear replaceable, so that it won't confuse final_giv_value. */
5802 #endif
5806 {
5809 rtx last_giv_use;
5813 /* When trying to determine whether or not a biv increment occurs
5814 during the lifetime of the giv, we can ignore uses of the variable
5815 outside the loop because final_value is true. Hence we can not
5816 use regno_last_uid and regno_first_uid as above in record_giv. */
5818 /* Search the loop to determine whether any assignments to the
5819 biv occur during the giv's lifetime. Start with the insn
5820 that sets the giv, and search around the loop until we come
5821 back to that insn again.
5823 Also fail if there is a jump within the giv's lifetime that jumps
5824 to somewhere outside the lifetime but still within the loop. This
5825 catches spaghetti code where the execution order is not linear, and
5826 hence the above test fails. Here we assume that the giv lifetime
5827 does not extend from one iteration of the loop to the next, so as
5828 to make the test easier. Since the lifetime isn't known yet,
5829 this requires two loops. See also record_giv above. */
5834 {
5837 {
5840 }
5846 {
5847 /* It is possible for the BIV increment to use the GIV if we
5848 have a cycle. Thus we must be sure to check each insn for
5849 both BIV and GIV uses, and we must check for BIV uses
5850 first. */
5857 {
5859 {
5863 }
5865 }
5866 }
5867 }
5869 /* Now that the lifetime of the giv is known, check for branches
5870 from within the lifetime to outside the lifetime if it is still
5871 replaceable. */
5874 {
5877 {
5890 {
5899 }
5900 }
5901 }
5903 /* If it is replaceable, then save the final value. */
5906 }
5911 }
5912 \f
5913 /* Update the status of whether a giv can derive other givs.
5915 We need to do something special if there is or may be an update to the biv
5916 between the time the giv is defined and the time it is used to derive
5917 another giv.
5919 In addition, a giv that is only conditionally set is not allowed to
5920 derive another giv once a label has been passed.
5922 The cases we look at are when a label or an update to a biv is passed. */
5924 static void
5927 rtx p;
5928 {
5932 rtx tem;
5935 /* Search all IV classes, then all bivs, and finally all givs.
5937 There are three cases we are concerned with. First we have the situation
5938 of a giv that is only updated conditionally. In that case, it may not
5939 derive any givs after a label is passed.
5941 The second case is when a biv update occurs, or may occur, after the
5942 definition of a giv. For certain biv updates (see below) that are
5943 known to occur between the giv definition and use, we can adjust the
5944 giv definition. For others, or when the biv update is conditional,
5945 we must prevent the giv from deriving any other givs. There are two
5946 sub-cases within this case.
5948 If this is a label, we are concerned with any biv update that is done
5949 conditionally, since it may be done after the giv is defined followed by
5950 a branch here (actually, we need to pass both a jump and a label, but
5951 this extra tracking doesn't seem worth it).
5953 If this is a jump, we are concerned about any biv update that may be
5954 executed multiple times. We are actually only concerned about
5955 backward jumps, but it is probably not worth performing the test
5956 on the jump again here.
5958 If this is a biv update, we must adjust the giv status to show that a
5959 subsequent biv update was performed. If this adjustment cannot be done,
5960 the giv cannot derive further givs. */
5966 {
5968 {
5969 /* If cant_derive is already true, there is no point in
5970 checking all of these conditions again. */
5974 /* If this giv is conditionally set and we have passed a label,
5975 it cannot derive anything. */
5979 /* Skip givs that have mult_val == 0, since
5980 they are really invariants. Also skip those that are
5981 replaceable, since we know their lifetime doesn't contain
5982 any biv update. */
5986 /* The only way we can allow this giv to derive another
5987 is if this is a biv increment and we can form the product
5988 of biv->add_val and giv->mult_val. In this case, we will
5989 be able to compute a compensation. */
5991 {
5992 rtx ext_val_dummy;
6003 tem = simplify_giv_expr
6010 else
6012 }
6016 }
6017 }
6018 }
6019 \f
6020 /* Check whether an insn is an increment legitimate for a basic induction var.
6021 X is the source of insn P, or a part of it.
6022 MODE is the mode in which X should be interpreted.
6024 DEST_REG is the putative biv, also the destination of the insn.
6025 We accept patterns of these forms:
6026 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6027 REG = INVARIANT + REG
6029 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6030 store the additive term into *INC_VAL, and store the place where
6031 we found the additive term into *LOCATION.
6033 If X is an assignment of an invariant into DEST_REG, we set
6034 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6036 We also want to detect a BIV when it corresponds to a variable
6037 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6038 of the variable may be a PLUS that adds a SUBREG of that variable to
6039 an invariant and then sign- or zero-extends the result of the PLUS
6040 into the variable.
6042 Most GIVs in such cases will be in the promoted mode, since that is the
6043 probably the natural computation mode (and almost certainly the mode
6044 used for addresses) on the machine. So we view the pseudo-reg containing
6045 the variable as the BIV, as if it were simply incremented.
6047 Note that treating the entire pseudo as a BIV will result in making
6048 simple increments to any GIVs based on it. However, if the variable
6049 overflows in its declared mode but not its promoted mode, the result will
6050 be incorrect. This is acceptable if the variable is signed, since
6051 overflows in such cases are undefined, but not if it is unsigned, since
6052 those overflows are defined. So we only check for SIGN_EXTEND and
6053 not ZERO_EXTEND.
6055 If we cannot find a biv, we return 0. */
6057 static int
6060 rtx x;
6062 rtx dest_reg;
6063 rtx p;
6067 {
6075 {
6081 {
6083 }
6088 {
6090 }
6091 else
6104 /* If this is a SUBREG for a promoted variable, check the inner
6105 value. */
6113 /* If this register is assigned in a previous insn, look at its
6114 source, but don't go outside the loop or past a label. */
6116 /* If this sets a register to itself, we would repeat any previous
6117 biv increment if we applied this strategy blindly. */
6123 {
6124 rtx dest;
6125 do
6126 {
6128 }
6157 }
6158 /* Fall through. */
6160 /* Can accept constant setting of biv only when inside inner most loop.
6161 Otherwise, a biv of an inner loop may be incorrectly recognized
6162 as a biv of the outer loop,
6163 causing code to be moved INTO the inner loop. */
6170 /* convert_modes aborts if we try to convert to or from CCmode, so just
6171 exclude that case. It is very unlikely that a condition code value
6172 would be a useful iterator anyways. */
6176 {
6177 /* Possible bug here? Perhaps we don't know the mode of X. */
6181 }
6182 else
6190 /* Similar, since this can be a sign extension. */
6195 ;
6209 location);
6214 }
6215 }
6216 \f
6217 /* A general induction variable (giv) is any quantity that is a linear
6218 function of a basic induction variable,
6219 i.e. giv = biv * mult_val + add_val.
6220 The coefficients can be any loop invariant quantity.
6221 A giv need not be computed directly from the biv;
6222 it can be computed by way of other givs. */
6224 /* Determine whether X computes a giv.
6225 If it does, return a nonzero value
6226 which is the benefit from eliminating the computation of X;
6227 set *SRC_REG to the register of the biv that it is computed from;
6228 set *ADD_VAL and *MULT_VAL to the coefficients,
6229 such that the value of X is biv * mult + add; */
6231 static int
6235 rtx x;
6243 {
6247 /* If this is an invariant, forget it, it isn't a giv. */
6258 {
6261 /* Since this is now an invariant and wasn't before, it must be a giv
6262 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6263 with. */
6270 /* This is equivalent to a BIV. */
6277 /* Either (plus (biv) (invar)) or
6278 (plus (mult (biv) (invar_1)) (invar_2)). */
6280 {
6283 }
6284 else
6285 {
6288 }
6293 /* ADD_VAL is zero. */
6301 }
6303 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6304 unless they are CONST_INT). */
6312 else
6315 /* Always return true if this is a giv so it will be detected as such,
6316 even if the benefit is zero or negative. This allows elimination
6317 of bivs that might otherwise not be eliminated. */
6319 }
6320 \f
6321 /* Given an expression, X, try to form it as a linear function of a biv.
6322 We will canonicalize it to be of the form
6323 (plus (mult (BIV) (invar_1))
6324 (invar_2))
6325 with possible degeneracies.
6327 The invariant expressions must each be of a form that can be used as a
6328 machine operand. We surround then with a USE rtx (a hack, but localized
6329 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6330 routine; it is the caller's responsibility to strip them.
6332 If no such canonicalization is possible (i.e., two biv's are used or an
6333 expression that is neither invariant nor a biv or giv), this routine
6334 returns 0.
6336 For a non-zero return, the result will have a code of CONST_INT, USE,
6337 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6339 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6344 static rtx
6347 rtx x;
6350 {
6355 rtx tem;
6357 /* If this is not an integer mode, or if we cannot do arithmetic in this
6358 mode, this can't be a giv. */
6365 {
6372 /* Put constant last, CONST_INT last if both constant. */
6380 /* Handle addition of zero, then addition of an invariant. */
6385 {
6388 /* Adding two invariants must result in an invariant, so enclose
6389 addition operation inside a USE and return it. */
6399 else
6408 /* biv + invar or mult + invar. Return sum. */
6412 /* (a + invar_1) + invar_2. Associate. */
6413 return
6419 arg1)),
6424 }
6426 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6427 MULT to reduce cases. */
6433 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6434 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6435 Recurse to associate the second PLUS. */
6440 return
6448 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6464 /* Handle "a - b" as "a + b * (-1)". */
6470 constm1_rtx)),
6479 /* Put constant last, CONST_INT last if both constant. */
6484 /* If second argument is not now constant, not giv. */
6488 /* Handle multiply by 0 or 1. */
6496 {
6498 /* biv * invar. Done. */
6502 /* Product of two constants. */
6506 /* invar * invar is a giv, but attempt to simplify it somehow. */
6512 {
6513 /* (invar_0 * invar_1) * invar_2. Associate. */
6520 arg1)),
6522 }
6523 /* Porpagate the MULT expressions to the intermost nodes. */
6525 {
6526 /* (invar_0 + invar_1) * invar_2. Distribute. */
6532 arg1),
6536 arg1)),
6538 }
6542 /* (a * invar_1) * invar_2. Associate. */
6548 arg1)),
6552 /* (a + invar_1) * invar_2. Distribute. */
6557 arg1),
6560 arg1)),
6565 }
6568 /* Shift by constant is multiply by power of two. */
6572 return
6581 /* "-a" is "a * (-1)" */
6587 /* "~a" is "-a - 1". Silly, but easy. */
6591 const1_rtx),
6595 /* Already in proper form for invariant. */
6601 /* Conditionally recognize extensions of simple IVs. After we've
6602 computed loop traversal counts and verified the range of the
6603 source IV, we'll reevaluate this as a GIV. */
6605 {
6608 {
6611 }
6612 }
6616 /* If this is a new register, we can't deal with it. */
6620 /* Check for biv or giv. */
6622 {
6626 {
6629 /* Form expression from giv and add benefit. Ensure this giv
6630 can derive another and subtract any needed adjustment if so. */
6632 /* Increasing the benefit here is risky. The only case in which it
6633 is arguably correct is if this is the only use of V. In other
6634 cases, this will artificially inflate the benefit of the current
6635 giv, and lead to suboptimal code. Thus, it is disabled, since
6636 potentially not reducing an only marginally beneficial giv is
6637 less harmful than reducing many givs that are not really
6638 beneficial. */
6639 {
6643 }
6656 {
6659 }
6660 else
6661 {
6664 }
6666 }
6669 do_default:
6670 /* If it isn't an induction variable, and it is invariant, we
6671 may be able to simplify things further by looking through
6672 the bits we just moved outside the loop. */
6674 {
6680 {
6681 /* Ok, we found a match. Substitute and simplify. */
6683 /* If we match another movable, we must use that, as
6684 this one is going away. */
6689 /* If consec is non-zero, this is a member of a group of
6690 instructions that were moved together. We handle this
6691 case only to the point of seeking to the last insn and
6692 looking for a REG_EQUAL. Fail if we don't find one. */
6694 {
6697 do
6698 {
6700 }
6706 }
6707 else
6708 {
6712 }
6715 {
6716 /* What we are most interested in is pointer
6717 arithmetic on invariants -- only take
6718 patterns we may be able to do something with. */
6724 {
6726 benefit);
6729 }
6734 {
6739 }
6740 }
6742 }
6743 }
6745 }
6747 /* Fall through to general case. */
6749 /* If invariant, return as USE (unless CONST_INT).
6750 Otherwise, not giv. */
6755 {
6764 }
6765 else
6767 }
6768 }
6770 /* This routine folds invariants such that there is only ever one
6771 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6773 static rtx
6776 {
6782 {
6785 }
6788 {
6791 }
6792 else
6793 {
6796 }
6797 }
6799 static rtx
6803 {
6805 {
6809 else
6812 }
6815 else
6818 }
6819 \f
6820 /* Help detect a giv that is calculated by several consecutive insns;
6821 for example,
6822 giv = biv * M
6823 giv = giv + A
6824 The caller has already identified the first insn P as having a giv as dest;
6825 we check that all other insns that set the same register follow
6826 immediately after P, that they alter nothing else,
6827 and that the result of the last is still a giv.
6829 The value is 0 if the reg set in P is not really a giv.
6830 Otherwise, the value is the amount gained by eliminating
6831 all the consecutive insns that compute the value.
6833 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6834 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6836 The coefficients of the ultimate giv value are stored in
6837 *MULT_VAL and *ADD_VAL. */
6839 static int
6844 rtx p;
6845 rtx src_reg;
6846 rtx dest_reg;
6851 {
6857 rtx temp;
6858 rtx set;
6860 /* Indicate that this is a giv so that we can update the value produced in
6861 each insn of the multi-insn sequence.
6863 This induction structure will be used only by the call to
6864 general_induction_var below, so we can allocate it on our stack.
6865 If this is a giv, our caller will replace the induct var entry with
6866 a new induction structure. */
6887 {
6891 /* If libcall, skip to end of call sequence. */
6902 /* Giv created by equivalent expression. */
6908 {
6912 count--;
6916 }
6918 {
6919 /* Allow insns that set something other than this giv to a
6920 constant. Such insns are needed on machines which cannot
6921 include long constants and should not disqualify a giv. */
6930 }
6931 }
6936 }
6937 \f
6938 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6939 represented by G1. If no such expression can be found, or it is clear that
6940 it cannot possibly be a valid address, 0 is returned.
6942 To perform the computation, we note that
6943 G1 = x * v + a and
6944 G2 = y * v + b
6945 where `v' is the biv.
6947 So G2 = (y/b) * G1 + (b - a*y/x).
6949 Note that MULT = y/x.
6951 Update: A and B are now allowed to be additive expressions such that
6952 B contains all variables in A. That is, computing B-A will not require
6953 subtracting variables. */
6955 static rtx
6958 {
6959 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6964 /* If MULT is not 1, we cannot handle A with non-constants, since we
6965 would then be required to subtract multiples of the registers in A.
6966 This is theoretically possible, and may even apply to some Fortran
6967 constructs, but it is a lot of work and we do not attempt it here. */
6972 /* In general these structures are sorted top to bottom (down the PLUS
6973 chain), but not left to right across the PLUS. If B is a higher
6974 order giv than A, we can strip one level and recurse. If A is higher
6975 order, we'll eventually bail out, but won't know that until the end.
6976 If they are the same, we'll strip one level around this loop. */
6979 {
6991 /* We matched: remove one reg completely. */
6994 /* An alternate match. */
6997 /* An alternate match. */
6999 else
7000 {
7001 /* Indicates an extra register in B. Strip one level from B and
7002 recurse, hoping B was the higher order expression. */
7007 }
7008 }
7010 /* Here we are at the last level of A, go through the cases hoping to
7011 get rid of everything but a constant. */
7014 {
7027 }
7029 {
7031 }
7033 {
7038 }
7040 {
7045 else
7047 }
7052 }
7054 rtx
7057 {
7060 /* The value that G1 will be multiplied by must be a constant integer. Also,
7061 the only chance we have of getting a valid address is if b*c/a (see above
7062 for notation) is also an integer. */
7065 {
7070 }
7073 else
7074 {
7075 /* ??? Find out if the one is a multiple of the other? */
7077 }
7081 {
7082 /* Failed. If we've got a multiplication factor between G1 and G2,
7083 scale G1's addend and try again. */
7085 {
7089 {
7090 HOST_WIDE_INT m;
7094 }
7095 else
7096 {
7098 mult);
7099 }
7102 }
7103 }
7107 /* Form simplified final result. */
7112 else
7117 else
7118 {
7121 {
7125 }
7128 }
7129 }
7130 \f
7131 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7132 represented by G1. This indicates that G2 should be combined with G1 and
7133 that G2 can use (either directly or via an address expression) a register
7134 used to represent G1. */
7136 static rtx
7139 {
7142 /* With the introduction of ext dependent givs, we must care for modes.
7143 G2 must not use a wider mode than G1. */
7153 /* If these givs are identical, they can be combined. We use the results
7154 of express_from because the addends are not in a canonical form, so
7155 rtx_equal_p is a weaker test. */
7156 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7157 combination to be the other way round. */
7160 {
7162 }
7164 /* If G2 can be expressed as a function of G1 and that function is valid
7165 as an address and no more expensive than using a register for G2,
7166 the expression of G2 in terms of G1 can be used. */
7170 /* ??? Looses, especially with -fforce-addr, where *g2->location
7171 will always be a register, and so anything more complicated
7172 gets discarded. */
7173 #if 0
7174 #ifdef ADDRESS_COST
7176 #else
7178 #endif
7179 #endif
7180 )
7181 {
7183 }
7186 }
7187 \f
7188 /* Check each extension dependent giv in this class to see if its
7189 root biv is safe from wrapping in the interior mode, which would
7190 make the giv illegal. */
7192 static void
7196 {
7199 HOST_WIDE_INT start_val;
7205 /* Make sure the iteration data is available. We must have
7206 constants in order to be certain of no overflow. */
7207 /* ??? An unknown iteration count with an increment of +-1
7208 combined with friendly exit tests of against an invariant
7209 value is also ameanable to optimization. Not implemented. */
7215 /* Make sure the host can represent the arithmetic. */
7217 {
7219 HOST_WIDE_INT s_end_val;
7231 /* Check for host arithmatic overflow. */
7233 {
7235 HOST_WIDE_INT s_max;
7242 /* Check zero extension of biv ok. */
7244 /* Check for host arithmatic overflow. */
7245 && (neg_incr
7248 /* Check for target arithmetic overflow. */
7249 && (neg_incr
7252 {
7254 }
7256 /* Check sign extension of biv ok. */
7257 /* ??? While it is true that overflow with signed and pointer
7258 arithmetic is undefined, I fear too many programmers don't
7259 keep this fact in mind -- myself included on occasion.
7260 So leave alone with the signed overflow optimizations. */
7262 /* Check for host arithmatic overflow. */
7263 && (neg_incr
7266 /* Check for target arithmetic overflow. */
7267 && (neg_incr
7270 {
7272 }
7273 }
7274 }
7276 /* Invalidate givs that fail the tests. */
7279 {
7284 {
7293 /* We don't know whether this value is being used as either
7294 signed or unsigned, so to safely truncate we must satisfy
7295 both. The initial check here verifies the BIV itself;
7296 once that is successful we may check its range wrt the
7297 derived GIV. */
7299 {
7303 /* We know from the above that both endpoints are nonnegative,
7304 and that there is no wrapping. Verify that both endpoints
7305 are within the (signed) range of the outer mode. */
7308 }
7313 }
7316 {
7318 {
7322 }
7323 }
7324 else
7325 {
7327 {
7332 else
7333 {
7338 else
7340 }
7345 }
7348 }
7349 }
7350 }
7352 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7354 rtx
7357 rtx value;
7358 {
7364 /* Recall that check_ext_dependent_givs verified that the known bounds
7365 of a biv did not overflow or wrap with respect to the extension for
7366 the giv. Therefore, constants need no additional adjustment. */
7370 /* Otherwise, we must adjust the value to compensate for the
7371 differing modes of the biv and the giv. */
7373 }
7374 \f
7375 struct combine_givs_stats
7376 {
7379 };
7381 static int
7385 {
7392 /* Stabilize the sort. */
7396 }
7398 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7399 any other. If so, point SAME to the giv combined with and set NEW_REG to
7400 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7401 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7403 static void
7407 {
7408 /* Additional benefit to add for being combined multiple times. */
7416 /* Count givs, because bl->giv_count is incorrect here. */
7420 giv_count++;
7422 giv_array
7433 {
7435 rtx single_use;
7440 /* If a DEST_REG GIV is used only once, do not allow it to combine
7441 with anything, for in doing so we will gain nothing that cannot
7442 be had by simply letting the GIV with which we would have combined
7443 to be reduced on its own. The losage shows up in particular with
7444 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7445 be seen elsewhere as well. */
7452 /* Add an additional weight for zero addends. */
7457 {
7458 rtx this_combine;
7463 {
7466 }
7467 }
7469 }
7471 /* Iterate, combining until we can't. */
7472 restart:
7476 {
7479 {
7485 }
7487 }
7490 {
7496 /* If it has already been combined, skip. */
7501 {
7504 /* If it has already been combined, skip. */
7506 {
7511 /* For destination, we now may replace by mem expression instead
7512 of register. This changes the costs considerably, so add the
7513 compensation. */
7523 /* ??? The new final_[bg]iv_value code does a much better job
7524 of finding replaceable giv's, and hence this code may no
7525 longer be necessary. */
7529 /* To help optimize the next set of combinations, remove
7530 this giv from the benefits of other potential mates. */
7532 {
7536 }
7543 }
7544 }
7546 /* To help optimize the next set of combinations, remove
7547 this giv from the benefits of other potential mates. */
7549 {
7551 {
7555 }
7559 /* We've finished with this giv, and everything it touched.
7560 Restart the combination so that proper weights for the
7561 rest of the givs are properly taken into account. */
7562 /* ??? Ideally we would compact the arrays at this point, so
7563 as to not cover old ground. But sanely compacting
7564 can_combine is tricky. */
7566 }
7567 }
7569 /* Clean up. */
7572 }
7573 \f
7574 /* Generate sequence for REG = B * M + A. */
7576 static rtx
7582 {
7583 rtx seq;
7584 rtx result;
7587 /* Use unsigned arithmetic. */
7595 }
7598 /* Update registers created in insn sequence SEQ. */
7600 static void
7603 rtx seq;
7604 {
7605 /* Update register info for alias analysis. */
7608 {
7611 {
7615 }
7616 }
7617 else
7618 {
7622 }
7623 }
7626 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7628 void
7635 basic_block before_bb;
7636 rtx before_insn;
7637 {
7638 rtx seq;
7641 {
7644 }
7646 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7649 /* Increase the lifetime of any invariants moved further in code. */
7656 /* It is possible that the expansion created lots of new registers.
7657 Iterate over the sequence we just created and record them all. */
7659 }
7662 /* Emit insns in loop pre-header to set REG = B * M + A. */
7664 void
7671 {
7672 rtx seq;
7674 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7677 /* Increase the lifetime of any invariants moved further in code.
7678 ???? Is this really necessary? */
7685 /* It is possible that the expansion created lots of new registers.
7686 Iterate over the sequence we just created and record them all. */
7688 }
7691 /* Emit insns after loop to set REG = B * M + A. */
7693 void
7700 {
7701 rtx seq;
7703 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7708 /* It is possible that the expansion created lots of new registers.
7709 Iterate over the sequence we just created and record them all. */
7711 }
7715 /* Similar to gen_add_mult, but compute cost rather than generating
7716 sequence. */
7718 static int
7724 {
7734 {
7739 }
7742 }
7743 \f
7744 /* Test whether A * B can be computed without
7745 an actual multiply insn. Value is 1 if so. */
7747 static int
7749 rtx a;
7750 rtx b;
7751 {
7753 rtx tmp;
7756 /* If only one is constant, make it B. */
7760 /* If first constant, both constant, so don't need multiply. */
7764 /* If second not constant, neither is constant, so would need multiply. */
7768 /* One operand is constant, so might not need multiply insn. Generate the
7769 code for the multiply and see if a call or multiply, or long sequence
7770 of insns is generated. */
7778 {
7783 else
7785 {
7794 {
7797 }
7798 }
7799 }
7809 }
7810 \f
7811 /* Check to see if loop can be terminated by a "decrement and branch until
7812 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7813 Also try reversing an increment loop to a decrement loop
7814 to see if the optimization can be performed.
7815 Value is nonzero if optimization was performed. */
7817 /* This is useful even if the architecture doesn't have such an insn,
7818 because it might change a loops which increments from 0 to n to a loop
7819 which decrements from n to 0. A loop that decrements to zero is usually
7820 faster than one that increments from zero. */
7822 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7823 such as approx_final_value, biv_total_increment, loop_iterations, and
7824 final_[bg]iv_value. */
7826 static int
7830 {
7835 rtx reg;
7836 rtx jump_label;
7837 rtx final_value;
7838 rtx start_value;
7839 rtx new_add_val;
7840 rtx comparison;
7841 rtx before_comparison;
7842 rtx p;
7843 rtx jump;
7844 rtx first_compare;
7849 /* If last insn is a conditional branch, and the insn before tests a
7850 register value, try to optimize it. Otherwise, we can't do anything. */
7859 /* Try to compute whether the compare/branch at the loop end is one or
7860 two instructions. */
7866 else
7869 {
7870 /* If more than one condition is present to control the loop, then
7871 do not proceed, as this function does not know how to rewrite
7872 loop tests with more than one condition.
7874 Look backwards from the first insn in the last comparison
7875 sequence and see if we've got another comparison sequence. */
7877 rtx jump1;
7881 }
7883 /* Check all of the bivs to see if the compare uses one of them.
7884 Skip biv's set more than once because we can't guarantee that
7885 it will be zero on the last iteration. Also skip if the biv is
7886 used between its update and the test insn. */
7889 {
7894 first_compare))
7896 }
7901 /* Look for the case where the basic induction variable is always
7902 nonnegative, and equals zero on the last iteration.
7903 In this case, add a reg_note REG_NONNEG, which allows the
7904 m68k DBRA instruction to be used. */
7912 {
7913 /* Initial value must be greater than 0,
7914 init_val % -dec_value == 0 to ensure that it equals zero on
7915 the last iteration */
7921 {
7922 /* register always nonnegative, add REG_NOTE to branch */
7930 }
7932 /* If the decrement is 1 and the value was tested as >= 0 before
7933 the loop, then we can safely optimize. */
7935 {
7948 {
7956 }
7957 }
7958 }
7961 {
7962 /* Try to change inc to dec, so can apply above optimization. */
7963 /* Can do this if:
7964 all registers modified are induction variables or invariant,
7965 all memory references have non-overlapping addresses
7966 (obviously true if only one write)
7967 allow 2 insns for the compare/jump at the end of the loop. */
7968 /* Also, we must avoid any instructions which use both the reversed
7969 biv and another biv. Such instructions will fail if the loop is
7970 reversed. We meet this condition by requiring that either
7971 no_use_except_counting is true, or else that there is only
7972 one biv. */
7974 /* 1 if the iteration var is used only to count iterations. */
7976 /* 1 if the loop has no memory store, or it has a single memory store
7977 which is reversible. */
7983 {
7987 /* If there are no givs for this biv, and the only exit is the
7988 fall through at the end of the loop, then
7989 see if perhaps there are no uses except to count. */
7993 {
7998 /* An insn that sets the biv is okay. */
7999 ;
8003 {
8004 /* If either of these insns uses the biv and sets a pseudo
8005 that has more than one usage, then the biv has uses
8006 other than counting since it's used to derive a value
8007 that is used more than one time. */
8009 regs);
8011 {
8014 }
8015 }
8017 {
8020 }
8021 }
8023 /* A biv has uses besides counting if it is used to set
8024 another biv. */
8028 {
8031 }
8032 }
8035 /* No need to worry about MEMs. */
8036 ;
8038 {
8043 /* If the loop has a single store, and the destination address is
8044 invariant, then we can't reverse the loop, because this address
8045 might then have the wrong value at loop exit.
8046 This would work if the source was invariant also, however, in that
8047 case, the insn should have been moved out of the loop. */
8050 {
8053 /* If we could prove that each of the memory locations
8054 written to was different, then we could reverse the
8055 store -- but we don't presently have any way of
8056 knowing that. */
8059 /* If the store depends on a register that is set after the
8060 store, it depends on the initial value, and is thus not
8061 reversible. */
8063 {
8070 }
8071 }
8072 }
8073 else
8076 /* This code only acts for innermost loops. Also it simplifies
8077 the memory address check by only reversing loops with
8078 zero or one memory access.
8079 Two memory accesses could involve parts of the same array,
8080 and that can't be reversed.
8081 If the biv is used only for counting, than we don't need to worry
8082 about all these things. */
8087 && reversible_mem_store
8092 {
8093 rtx tem;
8095 /* Loop can be reversed. */
8099 /* Now check other conditions:
8101 The increment must be a constant, as must the initial value,
8102 and the comparison code must be LT.
8104 This test can probably be improved since +/- 1 in the constant
8105 can be obtained by changing LT to LE and vice versa; this is
8106 confusing. */
8109 /* for constants, LE gets turned into LT */
8113 {
8124 comparison_const_width
8126 else
8127 comparison_const_width
8131 comparison_sign_mask
8134 /* If the comparison value is not a loop invariant, then we
8135 can not reverse this loop.
8137 ??? If the insns which initialize the comparison value as
8138 a whole compute an invariant result, then we could move
8139 them out of the loop and proceed with loop reversal. */
8147 /* Normalize the initial value if it is an integer and
8148 has no other use except as a counter. This will allow
8149 a few more loops to be reversed. */
8153 {
8155 /* The code below requires comparison_val to be a multiple
8156 of add_val in order to do the loop reversal, so
8157 round up comparison_val to a multiple of add_val.
8158 Since comparison_value is constant, we know that the
8159 current comparison code is LT. */
8161 comparison_val
8163 /* We postpone overflow checks for COMPARISON_VAL here;
8164 even if there is an overflow, we might still be able to
8165 reverse the loop, if converting the loop exit test to
8166 NE is possible. */
8168 }
8170 /* First check if we can do a vanilla loop reversal. */
8172 /* If we have a decrement_and_branch_on_count,
8173 prefer the NE test, since this will allow that
8174 instruction to be generated. Note that we must
8175 use a vanilla loop reversal if the biv is used to
8176 calculate a giv or has a non-counting use. */
8177 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8178 && defined (HAVE_decrement_and_branch_on_count)
8182 #endif
8184 /* Now do postponed overflow checks on COMPARISON_VAL. */
8187 {
8188 /* Register will always be nonnegative, with value
8189 0 on last iteration */
8193 }
8197 {
8200 }
8201 else
8207 /* If the initial value is not zero, or if the comparison
8208 value is not an exact multiple of the increment, then we
8209 can not reverse this loop. */
8212 {
8215 }
8216 else
8217 {
8220 }
8224 /* Reset these in case we normalized the initial value
8225 and comparison value above. */
8228 {
8230 final_value
8232 }
8235 /* Save some info needed to produce the new insns. */
8240 /* Set start_value; if this is not a CONST_INT, we need
8241 to generate a SUB.
8242 Initialize biv to start_value before loop start.
8243 The old initializing insn will be deleted as a
8244 dead store by flow.c. */
8247 {
8250 }
8252 {
8260 start_value
8266 }
8268 {
8271 initial_value);
8275 start_value
8278 }
8279 else
8280 /* We could handle the other cases too, but it'll be
8281 better to have a testcase first. */
8284 /* We may not have a single insn which can increment a reg, so
8285 create a sequence to hold all the insns from expand_inc. */
8294 /* Update biv info to reflect its new status. */
8299 /* Update loop info. */
8308 /* Inc LABEL_NUSES so that delete_insn will
8309 not delete the label. */
8312 /* Emit an insn after the end of the loop to set the biv's
8313 proper exit value if it is used anywhere outside the loop. */
8319 /* Delete compare/branch at end of loop. */
8324 /* Add new compare/branch insn at end of loop. */
8336 ;
8342 {
8344 {
8345 /* Increment of LABEL_NUSES done above. */
8346 /* Register is now always nonnegative,
8347 so add REG_NONNEG note to the branch. */
8350 }
8352 }
8354 /* No insn may reference both the reversed and another biv or it
8355 will fail (see comment near the top of the loop reversal
8356 code).
8357 Earlier on, we have verified that the biv has no use except
8358 counting, or it is the only biv in this function.
8359 However, the code that computes no_use_except_counting does
8360 not verify reg notes. It's possible to have an insn that
8361 references another biv, and has a REG_EQUAL note with an
8362 expression based on the reversed biv. To avoid this case,
8363 remove all REG_EQUAL notes based on the reversed biv
8364 here. */
8367 {
8370 /* If this is a set of a GIV based on the reversed biv, any
8371 REG_EQUAL notes should still be correct. */
8378 {
8383 else
8385 }
8386 }
8388 /* Mark that this biv has been reversed. Each giv which depends
8389 on this biv, and which is also live past the end of the loop
8390 will have to be fixed up. */
8395 {
8399 else
8401 }
8404 }
8405 }
8406 }
8409 }
8410 \f
8411 /* Verify whether the biv BL appears to be eliminable,
8412 based on the insns in the loop that refer to it.
8414 If ELIMINATE_P is non-zero, actually do the elimination.
8416 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8417 determine whether invariant insns should be placed inside or at the
8418 start of the loop. */
8420 static int
8426 {
8429 rtx p;
8431 /* Scan all insns in the loop, stopping if we find one that uses the
8432 biv in a way that we cannot eliminate. */
8435 {
8440 /* If this is a libcall that sets a giv, skip ahead to its end. */
8442 {
8446 {
8451 {
8458 }
8459 }
8460 }
8465 {
8471 }
8472 }
8475 {
8480 }
8483 }
8484 \f
8485 /* INSN and REFERENCE are instructions in the same insn chain.
8486 Return non-zero if INSN is first. */
8488 int
8491 {
8495 {
8496 /* Start with test for not first so that INSN == REFERENCE yields not
8497 first. */
8503 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8504 previous insn, hence the <= comparison below does not work if
8505 P is a note. */
8516 }
8517 }
8519 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8520 the offset that we have to take into account due to auto-increment /
8521 div derivation is zero. */
8522 static int
8525 rtx insn;
8526 {
8527 /* If the giv V had the auto-inc address optimization applied
8528 to it, and INSN occurs between the giv insn and the biv
8529 insn, then we'd have to adjust the value used here.
8530 This is rare, so we don't bother to make this possible. */
8539 }
8541 /* If BL appears in X (part of the pattern of INSN), see if we can
8542 eliminate its use. If so, return 1. If not, return 0.
8544 If BIV does not appear in X, return 1.
8546 If ELIMINATE_P is non-zero, actually do the elimination.
8547 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8548 Depending on how many items have been moved out of the loop, it
8549 will either be before INSN (when WHERE_INSN is non-zero) or at the
8550 start of the loop (when WHERE_INSN is zero). */
8552 static int
8558 basic_block where_bb;
8559 rtx where_insn;
8560 {
8566 #ifdef HAVE_cc0
8568 #endif
8574 {
8576 /* If we haven't already been able to do something with this BIV,
8577 we can't eliminate it. */
8583 /* If this sets the BIV, it is not a problem. */
8587 /* If this is an insn that defines a giv, it is also ok because
8588 it will go away when the giv is reduced. */
8593 #ifdef HAVE_cc0
8595 {
8596 /* Can replace with any giv that was reduced and
8597 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8598 Require a constant for MULT_VAL, so we know it's nonzero.
8599 ??? We disable this optimization to avoid potential
8600 overflows. */
8608 {
8615 /* If the giv has the opposite direction of change,
8616 then reverse the comparison. */
8620 else
8623 /* We can probably test that giv's reduced reg. */
8626 }
8628 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8629 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8630 Require a constant for MULT_VAL, so we know it's nonzero.
8631 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8632 overflow problem. */
8644 {
8651 /* If the giv has the opposite direction of change,
8652 then reverse the comparison. */
8656 else
8660 /* Replace biv with the giv's reduced register. */
8665 /* Insn doesn't support that constant or invariant. Copy it
8666 into a register (it will be a loop invariant.) */
8673 /* Substitute the new register for its invariant value in
8674 the compare expression. */
8678 }
8679 }
8680 #endif
8687 /* See if either argument is the biv. */
8692 else
8696 {
8697 /* First try to replace with any giv that has constant positive
8698 mult_val and constant add_val. We might be able to support
8699 negative mult_val, but it seems complex to do it in general. */
8711 {
8718 /* Replace biv with the giv's reduced reg. */
8721 /* If all constants are actually constant integers and
8722 the derived constant can be directly placed in the COMPARE,
8723 do so. */
8727 {
8732 }
8733 else
8734 {
8735 /* Otherwise, load it into a register. */
8741 }
8744 }
8746 /* Look for giv with positive constant mult_val and nonconst add_val.
8747 Insert insns to calculate new compare value.
8748 ??? Turn this off due to possible overflow. */
8756 {
8757 rtx tem;
8767 /* Replace biv with giv's reduced register. */
8771 /* Compute value to compare against. */
8775 /* Use it in this insn. */
8779 }
8780 }
8782 {
8784 {
8785 /* Look for giv with constant positive mult_val and nonconst
8786 add_val. Insert insns to compute new compare value.
8787 ??? Turn this off due to possible overflow. */
8794 {
8795 rtx tem;
8805 /* Replace biv with giv's reduced register. */
8809 /* Compute value to compare against. */
8816 }
8817 }
8819 /* This code has problems. Basically, you can't know when
8820 seeing if we will eliminate BL, whether a particular giv
8821 of ARG will be reduced. If it isn't going to be reduced,
8822 we can't eliminate BL. We can try forcing it to be reduced,
8823 but that can generate poor code.
8825 The problem is that the benefit of reducing TV, below should
8826 be increased if BL can actually be eliminated, but this means
8827 we might have to do a topological sort of the order in which
8828 we try to process biv. It doesn't seem worthwhile to do
8829 this sort of thing now. */
8831 #if 0
8832 /* Otherwise the reg compared with had better be a biv. */
8837 /* Look for a pair of givs, one for each biv,
8838 with identical coefficients. */
8840 {
8852 {
8859 /* Replace biv with its giv's reduced reg. */
8861 /* Replace other operand with the other giv's
8862 reduced reg. */
8865 }
8866 }
8867 #endif
8868 }
8870 /* If we get here, the biv can't be eliminated. */
8874 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8875 biv is used in it, since it will be replaced. */
8883 }
8885 /* See if any subexpression fails elimination. */
8888 {
8890 {
8903 }
8904 }
8907 }
8908 \f
8909 /* Return nonzero if the last use of REG
8910 is in an insn following INSN in the same basic block. */
8912 static int
8914 rtx reg;
8915 rtx insn;
8916 {
8917 rtx n;
8921 {
8924 }
8926 }
8927 \f
8928 /* Called via `note_stores' to record the initial value of a biv. Here we
8929 just record the location of the set and process it later. */
8931 static void
8933 rtx dest;
8934 rtx set;
8936 {
8947 /* If this is the first set found, record it. */
8949 {
8952 }
8953 }
8954 \f
8955 /* If any of the registers in X are "old" and currently have a last use earlier
8956 than INSN, update them to have a last use of INSN. Their actual last use
8957 will be the previous insn but it will not have a valid uid_luid so we can't
8958 use it. X must be a source expression only. */
8960 static void
8962 rtx x;
8963 rtx insn;
8964 {
8965 /* Check for the case where INSN does not have a valid luid. In this case,
8966 there is no need to modify the regno_last_uid, as this can only happen
8967 when code is inserted after the loop_end to set a pseudo's final value,
8968 and hence this insn will never be the last use of x.
8969 ???? This comment is not correct. See for example loop_givs_reduce.
8970 This may insert an insn before another new insn. */
8974 {
8976 }
8977 else
8978 {
8982 {
8988 }
8989 }
8990 }
8991 \f
8992 /* Given an insn INSN and condition COND, return the condition in a
8993 canonical form to simplify testing by callers. Specifically:
8995 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8996 (2) Both operands will be machine operands; (cc0) will have been replaced.
8997 (3) If an operand is a constant, it will be the second operand.
8998 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8999 for GE, GEU, and LEU.
9001 If the condition cannot be understood, or is an inequality floating-point
9002 comparison which needs to be reversed, 0 will be returned.
9004 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9006 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9007 insn used in locating the condition was found. If a replacement test
9008 of the condition is desired, it should be placed in front of that
9009 insn and we will be sure that the inputs are still valid.
9011 If WANT_REG is non-zero, we wish the condition to be relative to that
9012 register, if possible. Therefore, do not canonicalize the condition
9013 further. */
9015 rtx
9017 rtx insn;
9018 rtx cond;
9021 rtx want_reg;
9022 {
9025 rtx set;
9026 rtx tem;
9044 /* If we are comparing a register with zero, see if the register is set
9045 in the previous insn to a COMPARE or a comparison operation. Perform
9046 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9047 in cse.c */
9052 {
9053 /* Set non-zero when we find something of interest. */
9056 #ifdef HAVE_cc0
9057 /* If comparison with cc0, import actual comparison from compare
9058 insn. */
9060 {
9071 }
9072 #endif
9074 /* If this is a COMPARE, pick up the two things being compared. */
9076 {
9080 }
9084 /* Go back to the previous insn. Stop if it is not an INSN. We also
9085 stop if it isn't a single set or if it has a REG_INC note because
9086 we don't want to bother dealing with it. */
9100 /* If this is setting OP0, get what it sets it to if it looks
9101 relevant. */
9103 {
9106 /* ??? We may not combine comparisons done in a CCmode with
9107 comparisons not done in a CCmode. This is to aid targets
9108 like Alpha that have an IEEE compliant EQ instruction, and
9109 a non-IEEE compliant BEQ instruction. The use of CCmode is
9110 actually artificial, simply to prevent the combination, but
9111 should not affect other platforms.
9113 However, we must allow VOIDmode comparisons to match either
9114 CCmode or non-CCmode comparison, because some ports have
9115 modeless comparisons inside branch patterns.
9117 ??? This mode check should perhaps look more like the mode check
9118 in simplify_comparison in combine. */
9126 && (STORE_FLAG_VALUE
9129 #ifdef FLOAT_STORE_FLAG_VALUE
9132 && (REAL_VALUE_NEGATIVE
9134 #endif
9135 ))
9146 && (STORE_FLAG_VALUE
9149 #ifdef FLOAT_STORE_FLAG_VALUE
9152 && (REAL_VALUE_NEGATIVE
9154 #endif
9155 ))
9161 {
9164 }
9165 else
9167 }
9170 /* If this sets OP0, but not directly, we have to give up. */
9174 {
9178 {
9183 }
9188 }
9189 }
9191 /* If constant is first, put it last. */
9195 /* If OP0 is the result of a comparison, we weren't able to find what
9196 was really being compared, so fail. */
9200 /* Canonicalize any ordered comparison with integers involving equality
9201 if we can do computations in the relevant mode and we do not
9202 overflow. */
9207 {
9210 unsigned HOST_WIDE_INT max_val
9214 {
9220 /* When cross-compiling, const_val might be sign-extended from
9221 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9241 }
9242 }
9244 #ifdef HAVE_cc0
9245 /* Never return CC0; return zero instead. */
9248 #endif
9251 }
9253 /* Given a jump insn JUMP, return the condition that will cause it to branch
9254 to its JUMP_LABEL. If the condition cannot be understood, or is an
9255 inequality floating-point comparison which needs to be reversed, 0 will
9256 be returned.
9258 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9259 insn used in locating the condition was found. If a replacement test
9260 of the condition is desired, it should be placed in front of that
9261 insn and we will be sure that the inputs are still valid. */
9263 rtx
9265 rtx jump;
9267 {
9268 rtx cond;
9270 rtx set;
9272 /* If this is not a standard conditional jump, we can't parse it. */
9280 /* If this branches to JUMP_LABEL when the condition is false, reverse
9281 the condition. */
9282 reverse
9287 }
9289 /* Similar to above routine, except that we also put an invariant last
9290 unless both operands are invariants. */
9292 rtx
9295 rtx x;
9296 {
9306 }
9308 /* Scan the function and determine whether it has indirect (computed) jumps.
9310 This is taken mostly from flow.c; similar code exists elsewhere
9311 in the compiler. It may be useful to put this into rtlanal.c. */
9312 static int
9314 rtx start;
9315 {
9316 rtx insn;
9323 }
9325 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9326 documentation for LOOP_MEMS for the definition of `appropriate'.
9327 This function is called from prescan_loop via for_each_rtx. */
9329 static int
9333 {
9342 {
9347 /* We're not interested in MEMs that are only clobbered. */
9351 /* We're not interested in the MEM associated with a
9352 CONST_DOUBLE, so there's no need to traverse into this. */
9356 /* We're not interested in any MEMs that only appear in notes. */
9360 /* This is not a MEM. */
9362 }
9364 /* See if we've already seen this MEM. */
9367 {
9369 /* The modes of the two memory accesses are different. If
9370 this happens, something tricky is going on, and we just
9371 don't optimize accesses to this MEM. */
9375 }
9377 /* Resize the array, if necessary. */
9379 {
9382 else
9388 }
9390 /* Actually insert the MEM. */
9392 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9393 because we can't put it in a register. We still store it in the
9394 table, though, so that if we see the same address later, but in a
9395 non-BLK mode, we'll not think we can optimize it at that point. */
9401 }
9404 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9406 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9407 register that is modified by an insn between FROM and TO. If the
9408 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9409 more, stop incrementing it, to avoid overflow.
9411 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9412 register I is used, if it is only used once. Otherwise, it is set
9413 to 0 (for no uses) or const0_rtx for more than one use. This
9414 parameter may be zero, in which case this processing is not done.
9416 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9417 optimize register I. */
9419 static void
9423 {
9426 /* last_set[n] is nonzero iff reg n has been set in the current
9427 basic block. In that case, it is the insn that last set reg n. */
9429 rtx insn;
9435 /* Grow the regs array if not allocated or too small. */
9437 {
9443 /* Zero the new elements. */
9446 }
9448 /* Clear previously scanned fields but do not clear n_times_set. */
9450 {
9454 }
9458 /* Scan the loop, recording register usage. */
9461 {
9463 {
9464 /* Record registers that have exactly one use. */
9467 /* Include uses in REG_EQUAL notes. */
9475 {
9479 last_set);
9480 }
9481 }
9485 }
9487 /* Invalidate all hard registers clobbered by calls. With one exception:
9488 a call-clobbered PIC register is still function-invariant for our
9489 purposes, since we can hoist any PIC calculations out of the loop.
9490 Thus the call to rtx_varies_p. */
9495 {
9498 }
9500 #ifdef AVOID_CCMODE_COPIES
9501 /* Don't try to move insns which set CC registers if we should not
9502 create CCmode register copies. */
9506 #endif
9508 /* Set regs->array[I].n_times_set for the new registers. */
9513 }
9515 /* Returns the number of real INSNs in the LOOP. */
9517 static int
9520 {
9522 rtx insn;
9530 }
9532 /* Move MEMs into registers for the duration of the loop. */
9534 static void
9537 {
9544 rtx end_label;
9545 /* Nonzero if the next instruction may never be executed. */
9552 /* We cannot use next_label here because it skips over normal insns. */
9557 /* Check to see if it's possible that some instructions in the loop are
9558 never executed. Also check if there is a goto out of the loop other
9559 than right after the end of the loop. */
9563 {
9567 /* If we enter the loop in the middle, and scan
9568 around to the beginning, don't set maybe_never
9569 for that. This must be an unconditional jump,
9570 otherwise the code at the top of the loop might
9571 never be executed. Unconditional jumps are
9572 followed a by barrier then loop end. */
9577 {
9578 /* If this is a jump outside of the loop but not right
9579 after the end of the loop, we would have to emit new fixup
9580 sequences for each such label. */
9582 JUMP_INSN is executed, we must be conservative. */
9591 /* Something complicated. */
9593 else
9594 /* If there are any more instructions in the loop, they
9595 might not be reached. */
9597 }
9600 }
9602 /* Find start of the extended basic block that enters the loop. */
9606 ;
9611 /* Build table of mems that get set to constant values before the
9612 loop. */
9616 /* Actually move the MEMs. */
9618 {
9619 regset_head load_copies;
9620 regset_head store_copies;
9622 rtx reg;
9624 rtx mem_list_entry;
9628 /* There's no telling whether or not MEM is modified. */
9631 /* Go through the MEMs written to in the loop to see if this
9632 one is aliased by one of them. */
9635 {
9640 {
9641 /* MEM is indeed aliased by this store. */
9644 }
9646 }
9652 /* If this MEM is written to, we must be sure that there
9653 are no reads from another MEM that aliases this one. */
9655 {
9659 {
9663 VOIDmode,
9665 rtx_varies_p))
9666 {
9667 /* It's not safe to hoist loop_info->mems[i] out of
9668 the loop because writes to it might not be
9669 seen by reads from loop_info->mems[j]. */
9672 }
9673 }
9674 }
9677 /* We can't access the MEM outside the loop; it might
9678 cause a trap that wouldn't have happened otherwise. */
9682 /* We thought we were going to lift this MEM out of the
9683 loop, but later discovered that we could not. */
9689 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9690 order to keep scan_loop from moving stores to this MEM
9691 out of the loop just because this REG is neither a
9692 user-variable nor used in the loop test. */
9697 /* Now, replace all references to the MEM with the
9698 corresponding pseudos. */
9703 {
9705 {
9706 rtx set;
9710 /* See if this copies the mem into a register that isn't
9711 modified afterwards. We'll try to do copy propagation
9712 a little further on. */
9714 /* @@@ This test is _way_ too conservative. */
9715 && ! maybe_never
9723 /* See if this copies the mem from a register that isn't
9724 modified afterwards. We'll try to remove the
9725 redundant copy later on by doing a little register
9726 renaming and copy propagation. This will help
9727 to untangle things for the BIV detection code. */
9729 && ! maybe_never
9737 /* Replace the memory reference with the shadow register. */
9740 }
9745 }
9748 /* We couldn't replace all occurrences of the MEM. */
9750 else
9751 {
9752 /* Load the memory immediately before LOOP->START, which is
9753 the NOTE_LOOP_BEG. */
9755 rtx set;
9761 {
9765 {
9769 /* Extending hard register lifetimes causes crash
9770 on SRC targets. Doing so on non-SRC is
9771 probably also not good idea, since we most
9772 probably have pseudoregister equivalence as
9773 well. */
9776 }
9777 /* Use the constant equivalence if that is cheap enough. */
9783 {
9786 }
9788 /* If best_equiv is nonzero, we know that MEM is set to a
9789 constant or register before the loop. We will use this
9790 knowledge to initialize the shadow register with that
9791 constant or reg rather than by loading from MEM. */
9794 }
9799 {
9802 {
9805 }
9806 }
9812 {
9814 {
9817 }
9819 /* Store the memory immediately after END, which is
9820 the NOTE_LOOP_END. */
9823 }
9826 {
9831 }
9833 /* Attempt a bit of copy propagation. This helps untangle the
9834 data flow, and enables {basic,general}_induction_var to find
9835 more bivs/givs. */
9836 EXECUTE_IF_SET_IN_REG_SET
9838 {
9840 });
9843 EXECUTE_IF_SET_IN_REG_SET
9845 {
9847 });
9849 }
9850 }
9853 {
9854 /* Now, we need to replace all references to the previous exit
9855 label with the new one. */
9856 rtx_pair rr;
9861 {
9864 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9865 field. This is not handled by for_each_rtx because it doesn't
9866 handle unprinted ('0') fields. We need to update JUMP_LABEL
9867 because the immediately following unroll pass will use it.
9868 replace_label would not work anyways, because that only handles
9869 LABEL_REFs. */
9872 }
9873 }
9876 }
9878 /* For communication between note_reg_stored and its caller. */
9879 struct note_reg_stored_arg
9880 {
9882 rtx reg;
9883 };
9885 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9886 is equal to ARG. */
9887 static void
9891 {
9895 }
9897 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9898 There must be exactly one insn that sets this pseudo; it will be
9899 deleted if all replacements succeed and we can prove that the register
9900 is not used after the loop. */
9902 static void
9905 rtx replacement;
9907 {
9908 /* This is the reg that we are copying from. */
9911 rtx insn;
9912 /* These help keep track of whether we replaced all uses of the reg. */
9919 {
9920 rtx set;
9922 /* Only substitute within one extended basic block from the initializing
9923 insn. */
9930 /* Is this the initializing insn? */
9935 {
9942 }
9944 /* Only substitute after seeing the initializing insn. */
9946 {
9953 /* Stop replacing when REPLACEMENT is modified. */
9958 {
9961 /* It is possible that we've turned previously valid REG_EQUAL to
9962 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
9963 REPLACEMENT is modified, we get different meaning. */
9967 }
9968 }
9969 }
9973 {
9977 {
9978 rtx first;
9979 rtx retval_note;
9981 /* Assume we're just deleting INIT_INSN. */
9983 /* Look for REG_RETVAL note. If we're deleting the end of
9984 the libcall sequence, the whole sequence can go. */
9986 /* If we found a REG_RETVAL note, find the first instruction
9987 in the sequence. */
9991 /* Delete the instructions. */
9993 }
9996 }
9997 }
9999 /* Replace all the instructions from FIRST up to and including LAST
10000 with NOTE_INSN_DELETED notes. */
10002 static void
10004 rtx first;
10005 rtx last;
10006 {
10008 {
10014 /* If this was the LAST instructions we're supposed to delete,
10015 we're done. */
10020 }
10021 }
10023 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10024 loop LOOP if the order of the sets of these registers can be
10025 swapped. There must be exactly one insn within the loop that sets
10026 this pseudo followed immediately by a move insn that sets
10027 REPLACEMENT with REGNO. */
10028 static void
10031 rtx replacement;
10033 {
10034 rtx insn;
10043 {
10044 /* Search for the insn that copies REGNO to NEW_REGNO? */
10052 }
10055 {
10056 rtx prev_insn;
10057 rtx prev_set;
10059 /* Some DEF-USE info would come in handy here to make this
10060 function more general. For now, just check the previous insn
10061 which is the most likely candidate for setting REGNO. */
10069 {
10070 /* We have:
10071 (set (reg regno) (expr))
10072 (set (reg new_regno) (reg regno))
10074 so try converting this to:
10075 (set (reg new_regno) (expr))
10076 (set (reg regno) (reg new_regno))
10078 The former construct is often generated when a global
10079 variable used for an induction variable is shadowed by a
10080 register (NEW_REGNO). The latter construct improves the
10081 chances of GIV replacement and BIV elimination. */
10091 {
10098 /* Update first use of REGNO. */
10102 /* Now perform copy propagation to hopefully
10103 remove all uses of REGNO within the loop. */
10105 }
10106 }
10107 }
10108 }
10110 /* Replace MEM with its associated pseudo register. This function is
10111 called from load_mems via for_each_rtx. DATA is actually a pointer
10112 to a structure describing the instruction currently being scanned
10113 and the MEM we are currently replacing. */
10115 static int
10119 {
10127 {
10132 /* We're not interested in the MEM associated with a
10133 CONST_DOUBLE, so there's no need to traverse into one. */
10137 /* This is not a MEM. */
10139 }
10142 /* This is not the MEM we are currently replacing. */
10145 /* Actually replace the MEM. */
10149 }
10151 static void
10153 rtx insn;
10154 rtx mem;
10155 rtx reg;
10156 {
10157 loop_replace_args args;
10164 }
10166 /* Replace one register with another. Called through for_each_rtx; PX points
10167 to the rtx being scanned. DATA is actually a pointer to
10168 a structure of arguments. */
10170 static int
10174 {
10185 }
10187 static void
10189 rtx insn;
10190 rtx reg;
10191 rtx replacement;
10192 {
10193 loop_replace_args args;
10200 }
10202 /* Replace occurrences of the old exit label for the loop with the new
10203 one. DATA is an rtx_pair containing the old and new labels,
10204 respectively. */
10206 static int
10210 {
10229 }
10230 \f
10231 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10232 (ignored in the interim). */
10234 static rtx
10237 basic_block where_bb ATTRIBUTE_UNUSED;
10238 rtx where_insn;
10239 rtx pattern;
10240 {
10242 }
10245 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10246 in basic block WHERE_BB (ignored in the interim) within the loop
10247 otherwise hoist PATTERN into the loop pre-header. */
10249 rtx
10252 basic_block where_bb ATTRIBUTE_UNUSED;
10253 rtx where_insn;
10254 rtx pattern;
10255 {
10259 }
10262 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10263 WHERE_BB (ignored in the interim) within the loop. */
10265 static rtx
10268 basic_block where_bb ATTRIBUTE_UNUSED;
10269 rtx where_insn;
10270 rtx pattern;
10271 {
10273 }
10276 /* Hoist insn for PATTERN into the loop pre-header. */
10278 rtx
10281 rtx pattern;
10282 {
10284 }
10287 /* Hoist call insn for PATTERN into the loop pre-header. */
10289 static rtx
10292 rtx pattern;
10293 {
10295 }
10298 /* Sink insn for PATTERN after the loop end. */
10300 rtx
10303 rtx pattern;
10304 {
10306 }
10309 /* If the loop has multiple exits, emit insn for PATTERN before the
10310 loop to ensure that it will always be executed no matter how the
10311 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10312 since this is slightly more efficient. */
10314 static rtx
10317 rtx pattern;
10318 {
10321 else
10323 }
10324 \f
10325 static void
10330 {
10338 iv_num++;
10343 {
10346 }
10347 }
10350 static void
10355 {
10357 rtx incr;
10368 {
10371 }
10373 {
10376 }
10380 {
10384 }
10387 {
10391 }
10393 /* List the increments. */
10395 {
10399 }
10401 /* List the givs. */
10403 {
10408 else
10411 }
10412 }
10415 static void
10420 {
10431 {
10435 }
10438 }
10441 static void
10446 {
10453 else
10469 {
10471 {
10483 }
10484 }
10495 {
10499 }
10502 }
10505 void
10508 {
10510 }
10513 void
10516 {
10518 }
10521 void
10524 {
10526 }
10529 void
10532 {
10534 }
10537 #define LOOP_BLOCK_NUM_1(INSN) \
10538 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10540 /* The notes do not have an assigned block, so look at the next insn. */
10541 #define LOOP_BLOCK_NUM(INSN) \
10542 ((INSN) ? (GET_CODE (INSN) == NOTE \
10543 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10544 : LOOP_BLOCK_NUM_1 (INSN)) \
10545 : -1)
10547 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10549 static void
10554 {
10555 rtx label;
10560 /* Print diagnostics to compare our concept of a loop with
10561 what the loop notes say. */
10576 {
10596 {
10599 {
10602 }
10603 }
10606 /* This can happen when a marked loop appears as two nested loops,
10607 say from while (a || b) {}. The inner loop won't match
10608 the loop markers but the outer one will. */
10611 }
10612 }
10614 /* Call this function from the debugger to dump LOOP. */
10616 void
10619 {
10621 }
10623 /* Call this function from the debugger to dump LOOPS. */
10625 void
10628 {
10630 }