1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 #include "integrate.h"
79 /* Next quantity number available for allocation. */
83 /* Information we maintain about each quantity. */
86 /* The number of refs to quantity Q. */
90 /* The frequency of uses of quantity Q. */
94 /* Insn number (counting from head of basic block)
95 where quantity Q was born. -1 if birth has not been recorded. */
99 /* Insn number (counting from head of basic block)
100 where given quantity died. Due to the way tying is done,
101 and the fact that we consider in this pass only regs that die but once,
102 a quantity can die only once. Each quantity's life span
103 is a set of consecutive insns. -1 if death has not been recorded. */
107 /* Number of words needed to hold the data in given quantity.
108 This depends on its machine mode. It is used for these purposes:
109 1. It is used in computing the relative importances of qtys,
110 which determines the order in which we look for regs for them.
111 2. It is used in rules that prevent tying several registers of
112 different sizes in a way that is geometrically impossible
113 (see combine_regs). */
117 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
121 /* The register number of one pseudo register whose reg_qty value is Q.
122 This register should be the head of the chain
123 maintained in reg_next_in_qty. */
127 /* Reg class contained in (smaller than) the preferred classes of all
128 the pseudo regs that are tied in given quantity.
129 This is the preferred class for allocating that quantity. */
131 enum reg_class min_class
;
133 /* Register class within which we allocate given qty if we can't get
134 its preferred class. */
136 enum reg_class alternate_class
;
138 /* This holds the mode of the registers that are tied to given qty,
139 or VOIDmode if registers with differing modes are tied together. */
141 enum machine_mode mode
;
143 /* the hard reg number chosen for given quantity,
144 or -1 if none was found. */
148 /* Nonzero if this quantity has been used in a SUBREG in some
149 way that is illegal. */
155 static struct qty
*qty
;
157 /* These fields are kept separately to speedup their clearing. */
159 /* We maintain two hard register sets that indicate suggested hard registers
160 for each quantity. The first, phys_copy_sugg, contains hard registers
161 that are tied to the quantity by a simple copy. The second contains all
162 hard registers that are tied to the quantity via an arithmetic operation.
164 The former register set is given priority for allocation. This tends to
165 eliminate copy insns. */
167 /* Element Q is a set of hard registers that are suggested for quantity Q by
170 static HARD_REG_SET
*qty_phys_copy_sugg
;
172 /* Element Q is a set of hard registers that are suggested for quantity Q by
175 static HARD_REG_SET
*qty_phys_sugg
;
177 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
179 static short *qty_phys_num_copy_sugg
;
181 /* Element Q is the number of suggested registers in qty_phys_sugg. */
183 static short *qty_phys_num_sugg
;
185 /* If (REG N) has been assigned a quantity number, is a register number
186 of another register assigned the same quantity number, or -1 for the
187 end of the chain. qty->first_reg point to the head of this chain. */
189 static int *reg_next_in_qty
;
191 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
193 of -1 if this register cannot be allocated by local-alloc,
194 or -2 if not known yet.
196 Note that if we see a use or death of pseudo register N with
197 reg_qty[N] == -2, register N must be local to the current block. If
198 it were used in more than one block, we would have reg_qty[N] == -1.
199 This relies on the fact that if reg_basic_block[N] is >= 0, register N
200 will not appear in any other block. We save a considerable number of
201 tests by exploiting this.
203 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
208 /* The offset (in words) of register N within its quantity.
209 This can be nonzero if register N is SImode, and has been tied
210 to a subreg of a DImode register. */
212 static char *reg_offset
;
214 /* Vector of substitutions of register numbers,
215 used to map pseudo regs into hardware regs.
216 This is set up as a result of register allocation.
217 Element N is the hard reg assigned to pseudo reg N,
218 or is -1 if no hard reg was assigned.
219 If N is a hard reg number, element N is N. */
223 /* Set of hard registers live at the current point in the scan
224 of the instructions in a basic block. */
226 static HARD_REG_SET regs_live
;
228 /* Each set of hard registers indicates registers live at a particular
229 point in the basic block. For N even, regs_live_at[N] says which
230 hard registers are needed *after* insn N/2 (i.e., they may not
231 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
233 If an object is to conflict with the inputs of insn J but not the
234 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
235 if it is to conflict with the outputs of insn J but not the inputs of
236 insn J + 1, it is said to die at index J*2 + 1. */
238 static HARD_REG_SET
*regs_live_at
;
240 /* Communicate local vars `insn_number' and `insn'
241 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
242 static int this_insn_number
;
243 static rtx this_insn
;
247 /* Set when an attempt should be made to replace a register
248 with the associated src_p entry. */
252 /* Set when a REG_EQUIV note is found or created. Use to
253 keep track of what memory accesses might be created later,
260 /* Loop depth is used to recognize equivalences which appear
261 to be present within the same loop (or in an inner loop). */
265 /* The list of each instruction which initializes this register. */
270 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
271 structure for that register. */
273 static struct equivalence
*reg_equiv
;
275 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
276 static int recorded_label_ref
;
278 static void alloc_qty
PARAMS ((int, enum machine_mode
, int, int));
279 static void validate_equiv_mem_from_store
PARAMS ((rtx
, rtx
, void *));
280 static int validate_equiv_mem
PARAMS ((rtx
, rtx
, rtx
));
281 static int equiv_init_varies_p
PARAMS ((rtx
));
282 static int equiv_init_movable_p
PARAMS ((rtx
, int));
283 static int contains_replace_regs
PARAMS ((rtx
));
284 static int memref_referenced_p
PARAMS ((rtx
, rtx
));
285 static int memref_used_between_p
PARAMS ((rtx
, rtx
, rtx
));
286 static void update_equiv_regs
PARAMS ((void));
287 static void no_equiv
PARAMS ((rtx
, rtx
, void *));
288 static void block_alloc
PARAMS ((int));
289 static int qty_sugg_compare
PARAMS ((int, int));
290 static int qty_sugg_compare_1
PARAMS ((const PTR
, const PTR
));
291 static int qty_compare
PARAMS ((int, int));
292 static int qty_compare_1
PARAMS ((const PTR
, const PTR
));
293 static int combine_regs
PARAMS ((rtx
, rtx
, int, int, rtx
, int));
294 static int reg_meets_class_p
PARAMS ((int, enum reg_class
));
295 static void update_qty_class
PARAMS ((int, int));
296 static void reg_is_set
PARAMS ((rtx
, rtx
, void *));
297 static void reg_is_born
PARAMS ((rtx
, int));
298 static void wipe_dead_reg
PARAMS ((rtx
, int));
299 static int find_free_reg
PARAMS ((enum reg_class
, enum machine_mode
,
300 int, int, int, int, int));
301 static void mark_life
PARAMS ((int, enum machine_mode
, int));
302 static void post_mark_life
PARAMS ((int, enum machine_mode
, int, int, int));
303 static int no_conflict_p
PARAMS ((rtx
, rtx
, rtx
));
304 static int requires_inout
PARAMS ((const char *));
306 /* Allocate a new quantity (new within current basic block)
307 for register number REGNO which is born at index BIRTH
308 within the block. MODE and SIZE are info on reg REGNO. */
311 alloc_qty (regno
, mode
, size
, birth
)
313 enum machine_mode mode
;
316 int qtyno
= next_qty
++;
318 reg_qty
[regno
] = qtyno
;
319 reg_offset
[regno
] = 0;
320 reg_next_in_qty
[regno
] = -1;
322 qty
[qtyno
].first_reg
= regno
;
323 qty
[qtyno
].size
= size
;
324 qty
[qtyno
].mode
= mode
;
325 qty
[qtyno
].birth
= birth
;
326 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
327 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
328 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
329 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
330 qty
[qtyno
].freq
= REG_FREQ (regno
);
331 qty
[qtyno
].changes_mode
= REG_CHANGES_MODE (regno
);
334 /* Main entry point of this file. */
342 /* We need to keep track of whether or not we recorded a LABEL_REF so
343 that we know if the jump optimizer needs to be rerun. */
344 recorded_label_ref
= 0;
346 /* Leaf functions and non-leaf functions have different needs.
347 If defined, let the machine say what kind of ordering we
349 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
350 ORDER_REGS_FOR_LOCAL_ALLOC
;
353 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
355 update_equiv_regs ();
357 /* This sets the maximum number of quantities we can have. Quantity
358 numbers start at zero and we can have one for each pseudo. */
359 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
361 /* Allocate vectors of temporary data.
362 See the declarations of these variables, above,
363 for what they mean. */
365 qty
= (struct qty
*) xmalloc (max_qty
* sizeof (struct qty
));
367 = (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
368 qty_phys_num_copy_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
369 qty_phys_sugg
= (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
370 qty_phys_num_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
372 reg_qty
= (int *) xmalloc (max_regno
* sizeof (int));
373 reg_offset
= (char *) xmalloc (max_regno
* sizeof (char));
374 reg_next_in_qty
= (int *) xmalloc (max_regno
* sizeof (int));
376 /* Determine which pseudo-registers can be allocated by local-alloc.
377 In general, these are the registers used only in a single block and
380 We need not be concerned with which block actually uses the register
381 since we will never see it outside that block. */
383 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
385 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1)
391 /* Force loop below to initialize entire quantity array. */
394 /* Allocate each block's local registers, block by block. */
396 for (b
= 0; b
< n_basic_blocks
; b
++)
398 /* NEXT_QTY indicates which elements of the `qty_...'
399 vectors might need to be initialized because they were used
400 for the previous block; it is set to the entire array before
401 block 0. Initialize those, with explicit loop if there are few,
402 else with bzero and bcopy. Do not initialize vectors that are
403 explicit set by `alloc_qty'. */
407 for (i
= 0; i
< next_qty
; i
++)
409 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
410 qty_phys_num_copy_sugg
[i
] = 0;
411 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
412 qty_phys_num_sugg
[i
] = 0;
417 #define CLEAR(vector) \
418 memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty);
420 CLEAR (qty_phys_copy_sugg
);
421 CLEAR (qty_phys_num_copy_sugg
);
422 CLEAR (qty_phys_sugg
);
423 CLEAR (qty_phys_num_sugg
);
432 free (qty_phys_copy_sugg
);
433 free (qty_phys_num_copy_sugg
);
434 free (qty_phys_sugg
);
435 free (qty_phys_num_sugg
);
439 free (reg_next_in_qty
);
441 return recorded_label_ref
;
444 /* Used for communication between the following two functions: contains
445 a MEM that we wish to ensure remains unchanged. */
446 static rtx equiv_mem
;
448 /* Set nonzero if EQUIV_MEM is modified. */
449 static int equiv_mem_modified
;
451 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
452 Called via note_stores. */
455 validate_equiv_mem_from_store (dest
, set
, data
)
457 rtx set ATTRIBUTE_UNUSED
;
458 void *data ATTRIBUTE_UNUSED
;
460 if ((GET_CODE (dest
) == REG
461 && reg_overlap_mentioned_p (dest
, equiv_mem
))
462 || (GET_CODE (dest
) == MEM
463 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
464 equiv_mem_modified
= 1;
467 /* Verify that no store between START and the death of REG invalidates
468 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
469 by storing into an overlapping memory location, or with a non-const
472 Return 1 if MEMREF remains valid. */
475 validate_equiv_mem (start
, reg
, memref
)
484 equiv_mem_modified
= 0;
486 /* If the memory reference has side effects or is volatile, it isn't a
487 valid equivalence. */
488 if (side_effects_p (memref
))
491 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
496 if (find_reg_note (insn
, REG_DEAD
, reg
))
499 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
500 && ! CONST_OR_PURE_CALL_P (insn
))
503 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
505 /* If a register mentioned in MEMREF is modified via an
506 auto-increment, we lose the equivalence. Do the same if one
507 dies; although we could extend the life, it doesn't seem worth
510 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
511 if ((REG_NOTE_KIND (note
) == REG_INC
512 || REG_NOTE_KIND (note
) == REG_DEAD
)
513 && GET_CODE (XEXP (note
, 0)) == REG
514 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
521 /* Returns zero if X is known to be invariant. */
524 equiv_init_varies_p (x
)
527 RTX_CODE code
= GET_CODE (x
);
534 return ! RTX_UNCHANGING_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
548 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
551 if (MEM_VOLATILE_P (x
))
560 fmt
= GET_RTX_FORMAT (code
);
561 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
564 if (equiv_init_varies_p (XEXP (x
, i
)))
567 else if (fmt
[i
] == 'E')
570 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
571 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
578 /* Returns non-zero if X (used to initialize register REGNO) is movable.
579 X is only movable if the registers it uses have equivalent initializations
580 which appear to be within the same loop (or in an inner loop) and movable
581 or if they are not candidates for local_alloc and don't vary. */
584 equiv_init_movable_p (x
, regno
)
590 enum rtx_code code
= GET_CODE (x
);
595 return equiv_init_movable_p (SET_SRC (x
), regno
);
610 return (reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
611 && reg_equiv
[REGNO (x
)].replace
)
612 || (REG_BASIC_BLOCK (REGNO (x
)) < 0 && ! rtx_varies_p (x
, 0));
614 case UNSPEC_VOLATILE
:
618 if (MEM_VOLATILE_P (x
))
627 fmt
= GET_RTX_FORMAT (code
);
628 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
632 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
636 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
637 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
645 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
648 contains_replace_regs (x
)
653 enum rtx_code code
= GET_CODE (x
);
669 return reg_equiv
[REGNO (x
)].replace
;
675 fmt
= GET_RTX_FORMAT (code
);
676 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
680 if (contains_replace_regs (XEXP (x
, i
)))
684 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
685 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
693 /* TRUE if X references a memory location that would be affected by a store
697 memref_referenced_p (memref
, x
)
703 enum rtx_code code
= GET_CODE (x
);
720 return (reg_equiv
[REGNO (x
)].replacement
721 && memref_referenced_p (memref
,
722 reg_equiv
[REGNO (x
)].replacement
));
725 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
730 /* If we are setting a MEM, it doesn't count (its address does), but any
731 other SET_DEST that has a MEM in it is referencing the MEM. */
732 if (GET_CODE (SET_DEST (x
)) == MEM
)
734 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
737 else if (memref_referenced_p (memref
, SET_DEST (x
)))
740 return memref_referenced_p (memref
, SET_SRC (x
));
746 fmt
= GET_RTX_FORMAT (code
);
747 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
751 if (memref_referenced_p (memref
, XEXP (x
, i
)))
755 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
756 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
764 /* TRUE if some insn in the range (START, END] references a memory location
765 that would be affected by a store to MEMREF. */
768 memref_used_between_p (memref
, start
, end
)
775 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
776 insn
= NEXT_INSN (insn
))
777 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
783 /* Return nonzero if the rtx X is invariant over the current function. */
784 /* ??? Actually, the places this is used in reload expect exactly what
785 is tested here, and not everything that is function invariant. In
786 particular, the frame pointer and arg pointer are special cased;
787 pic_offset_table_rtx is not, and this will cause aborts when we
788 go to spill these things to memory. */
791 function_invariant_p (x
)
796 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
798 if (GET_CODE (x
) == PLUS
799 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
800 && CONSTANT_P (XEXP (x
, 1)))
805 /* Find registers that are equivalent to a single value throughout the
806 compilation (either because they can be referenced in memory or are set once
807 from a single constant). Lower their priority for a register.
809 If such a register is only referenced once, try substituting its value
810 into the using insn. If it succeeds, we can eliminate the register
819 regset_head cleared_regs
;
820 int clear_regnos
= 0;
822 reg_equiv
= (struct equivalence
*) xcalloc (max_regno
, sizeof *reg_equiv
);
823 INIT_REG_SET (&cleared_regs
);
825 init_alias_analysis ();
827 /* Scan the insns and find which registers have equivalences. Do this
828 in a separate scan of the insns because (due to -fcse-follow-jumps)
829 a register can be set below its use. */
830 for (block
= 0; block
< n_basic_blocks
; block
++)
832 basic_block bb
= BASIC_BLOCK (block
);
833 loop_depth
= bb
->loop_depth
;
835 for (insn
= bb
->head
; insn
!= NEXT_INSN (bb
->end
); insn
= NEXT_INSN (insn
))
845 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
846 if (REG_NOTE_KIND (note
) == REG_INC
)
847 no_equiv (XEXP (note
, 0), note
, NULL
);
849 set
= single_set (insn
);
851 /* If this insn contains more (or less) than a single SET,
852 only mark all destinations as having no known equivalence. */
855 note_stores (PATTERN (insn
), no_equiv
, NULL
);
858 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
862 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
864 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
866 note_stores (part
, no_equiv
, NULL
);
870 dest
= SET_DEST (set
);
873 /* If this sets a MEM to the contents of a REG that is only used
874 in a single basic block, see if the register is always equivalent
875 to that memory location and if moving the store from INSN to the
876 insn that set REG is safe. If so, put a REG_EQUIV note on the
879 Don't add a REG_EQUIV note if the insn already has one. The existing
880 REG_EQUIV is likely more useful than the one we are adding.
882 If one of the regs in the address has reg_equiv[REGNO].replace set,
883 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
884 optimization may move the set of this register immediately before
885 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
886 the mention in the REG_EQUIV note would be to an uninitialized
888 /* ????? This test isn't good enough; we might see a MEM with a use of
889 a pseudo register before we see its setting insn that will cause
890 reg_equiv[].replace for that pseudo to be set.
891 Equivalences to MEMs should be made in another pass, after the
892 reg_equiv[].replace information has been gathered. */
894 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
895 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
896 && REG_BASIC_BLOCK (regno
) >= 0
897 && REG_N_SETS (regno
) == 1
898 && reg_equiv
[regno
].init_insns
!= 0
899 && reg_equiv
[regno
].init_insns
!= const0_rtx
900 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
902 && ! contains_replace_regs (XEXP (dest
, 0)))
904 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
905 if (validate_equiv_mem (init_insn
, src
, dest
)
906 && ! memref_used_between_p (dest
, init_insn
, insn
))
907 REG_NOTES (init_insn
)
908 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
911 /* We only handle the case of a pseudo register being set
912 once, or always to the same value. */
913 /* ??? The mn10200 port breaks if we add equivalences for
914 values that need an ADDRESS_REGS register and set them equivalent
915 to a MEM of a pseudo. The actual problem is in the over-conservative
916 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
917 calculate_needs, but we traditionally work around this problem
918 here by rejecting equivalences when the destination is in a register
919 that's likely spilled. This is fragile, of course, since the
920 preferred class of a pseudo depends on all instructions that set
923 if (GET_CODE (dest
) != REG
924 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
925 || reg_equiv
[regno
].init_insns
== const0_rtx
926 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
927 && GET_CODE (src
) == MEM
))
929 /* This might be seting a SUBREG of a pseudo, a pseudo that is
930 also set somewhere else to a constant. */
931 note_stores (set
, no_equiv
, NULL
);
935 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
937 /* cse sometimes generates function invariants, but doesn't put a
938 REG_EQUAL note on the insn. Since this note would be redundant,
939 there's no point creating it earlier than here. */
940 if (! note
&& ! rtx_varies_p (src
, 0))
941 note
= set_unique_reg_note (insn
, REG_EQUAL
, src
);
943 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
944 since it represents a function call */
945 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
948 if (REG_N_SETS (regno
) != 1
950 || rtx_varies_p (XEXP (note
, 0), 0)
951 || (reg_equiv
[regno
].replacement
952 && ! rtx_equal_p (XEXP (note
, 0),
953 reg_equiv
[regno
].replacement
))))
955 no_equiv (dest
, set
, NULL
);
958 /* Record this insn as initializing this register. */
959 reg_equiv
[regno
].init_insns
960 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
962 /* If this register is known to be equal to a constant, record that
963 it is always equivalent to the constant. */
964 if (note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
965 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
967 /* If this insn introduces a "constant" register, decrease the priority
968 of that register. Record this insn if the register is only used once
969 more and the equivalence value is the same as our source.
971 The latter condition is checked for two reasons: First, it is an
972 indication that it may be more efficient to actually emit the insn
973 as written (if no registers are available, reload will substitute
974 the equivalence). Secondly, it avoids problems with any registers
975 dying in this insn whose death notes would be missed.
977 If we don't have a REG_EQUIV note, see if this insn is loading
978 a register used only in one basic block from a MEM. If so, and the
979 MEM remains unchanged for the life of the register, add a REG_EQUIV
982 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
984 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
985 && GET_CODE (SET_SRC (set
)) == MEM
986 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
987 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
992 int regno
= REGNO (dest
);
994 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
995 We might end up substituting the LABEL_REF for uses of the
996 pseudo here or later. That kind of transformation may turn an
997 indirect jump into a direct jump, in which case we must rerun the
998 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
999 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
1000 || (GET_CODE (XEXP (note
, 0)) == CONST
1001 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
1002 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
1004 recorded_label_ref
= 1;
1006 reg_equiv
[regno
].replacement
= XEXP (note
, 0);
1007 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
1008 reg_equiv
[regno
].loop_depth
= loop_depth
;
1010 /* Don't mess with things live during setjmp. */
1011 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
1013 /* Note that the statement below does not affect the priority
1015 REG_LIVE_LENGTH (regno
) *= 2;
1018 /* If the register is referenced exactly twice, meaning it is
1019 set once and used once, indicate that the reference may be
1020 replaced by the equivalence we computed above. Do this
1021 even if the register is only used in one block so that
1022 dependencies can be handled where the last register is
1023 used in a different block (i.e. HIGH / LO_SUM sequences)
1024 and to reduce the number of registers alive across
1027 if (REG_N_REFS (regno
) == 2
1028 && (rtx_equal_p (XEXP (note
, 0), src
)
1029 || ! equiv_init_varies_p (src
))
1030 && GET_CODE (insn
) == INSN
1031 && equiv_init_movable_p (PATTERN (insn
), regno
))
1032 reg_equiv
[regno
].replace
= 1;
1038 /* Now scan all regs killed in an insn to see if any of them are
1039 registers only used that once. If so, see if we can replace the
1040 reference with the equivalent from. If we can, delete the
1041 initializing reference and this register will go away. If we
1042 can't replace the reference, and the initialzing reference is
1043 within the same loop (or in an inner loop), then move the register
1044 initialization just before the use, so that they are in the same
1046 for (block
= n_basic_blocks
- 1; block
>= 0; block
--)
1048 basic_block bb
= BASIC_BLOCK (block
);
1050 loop_depth
= bb
->loop_depth
;
1051 for (insn
= bb
->end
; insn
!= PREV_INSN (bb
->head
); insn
= PREV_INSN (insn
))
1055 if (! INSN_P (insn
))
1058 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1060 if (REG_NOTE_KIND (link
) == REG_DEAD
1061 /* Make sure this insn still refers to the register. */
1062 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1064 int regno
= REGNO (XEXP (link
, 0));
1067 if (! reg_equiv
[regno
].replace
1068 || reg_equiv
[regno
].loop_depth
< loop_depth
)
1071 /* reg_equiv[REGNO].replace gets set only when
1072 REG_N_REFS[REGNO] is 2, i.e. the register is set
1073 once and used once. (If it were only set, but not used,
1074 flow would have deleted the setting insns.) Hence
1075 there can only be one insn in reg_equiv[REGNO].init_insns. */
1076 if (reg_equiv
[regno
].init_insns
== NULL_RTX
1077 || XEXP (reg_equiv
[regno
].init_insns
, 1) != NULL_RTX
)
1079 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1081 /* We may not move instructions that can throw, since
1082 that changes basic block boundaries and we are not
1083 prepared to adjust the CFG to match. */
1084 if (can_throw_internal (equiv_insn
))
1087 if (asm_noperands (PATTERN (equiv_insn
)) < 0
1088 && validate_replace_rtx (regno_reg_rtx
[regno
],
1089 *(reg_equiv
[regno
].src_p
), insn
))
1095 /* Find the last note. */
1096 for (last_link
= link
; XEXP (last_link
, 1);
1097 last_link
= XEXP (last_link
, 1))
1100 /* Append the REG_DEAD notes from equiv_insn. */
1101 equiv_link
= REG_NOTES (equiv_insn
);
1105 equiv_link
= XEXP (equiv_link
, 1);
1106 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1108 remove_note (equiv_insn
, note
);
1109 XEXP (last_link
, 1) = note
;
1110 XEXP (note
, 1) = NULL_RTX
;
1115 remove_death (regno
, insn
);
1116 REG_N_REFS (regno
) = 0;
1117 REG_FREQ (regno
) = 0;
1118 delete_insn (equiv_insn
);
1120 reg_equiv
[regno
].init_insns
1121 = XEXP (reg_equiv
[regno
].init_insns
, 1);
1123 /* Move the initialization of the register to just before
1124 INSN. Update the flow information. */
1125 else if (PREV_INSN (insn
) != equiv_insn
)
1129 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
1130 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
1131 REG_NOTES (equiv_insn
) = 0;
1133 /* Make sure this insn is recognized before reload begins,
1134 otherwise eliminate_regs_in_insn will abort. */
1135 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
1137 delete_insn (equiv_insn
);
1139 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
1141 REG_BASIC_BLOCK (regno
) = block
>= 0 ? block
: 0;
1142 REG_N_CALLS_CROSSED (regno
) = 0;
1143 REG_LIVE_LENGTH (regno
) = 2;
1145 if (block
>= 0 && insn
== BLOCK_HEAD (block
))
1146 BLOCK_HEAD (block
) = PREV_INSN (insn
);
1148 /* Remember to clear REGNO from all basic block's live
1150 SET_REGNO_REG_SET (&cleared_regs
, regno
);
1158 /* Clear all dead REGNOs from all basic block's live info. */
1162 if (clear_regnos
> 8)
1164 for (l
= 0; l
< n_basic_blocks
; l
++)
1166 AND_COMPL_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
,
1168 AND_COMPL_REG_SET (BASIC_BLOCK (l
)->global_live_at_end
,
1173 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs
, 0, j
,
1175 for (l
= 0; l
< n_basic_blocks
; l
++)
1177 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
, j
);
1178 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_end
, j
);
1184 end_alias_analysis ();
1185 CLEAR_REG_SET (&cleared_regs
);
1189 /* Mark REG as having no known equivalence.
1190 Some instructions might have been proceessed before and furnished
1191 with REG_EQUIV notes for this register; these notes will have to be
1193 STORE is the piece of RTL that does the non-constant / conflicting
1194 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1195 but needs to be there because this function is called from note_stores. */
1197 no_equiv (reg
, store
, data
)
1198 rtx reg
, store ATTRIBUTE_UNUSED
;
1199 void *data ATTRIBUTE_UNUSED
;
1204 if (GET_CODE (reg
) != REG
)
1206 regno
= REGNO (reg
);
1207 list
= reg_equiv
[regno
].init_insns
;
1208 if (list
== const0_rtx
)
1210 for (; list
; list
= XEXP (list
, 1))
1212 rtx insn
= XEXP (list
, 0);
1213 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1215 reg_equiv
[regno
].init_insns
= const0_rtx
;
1216 reg_equiv
[regno
].replacement
= NULL_RTX
;
1219 /* Allocate hard regs to the pseudo regs used only within block number B.
1220 Only the pseudos that die but once can be handled. */
1229 int insn_number
= 0;
1231 int max_uid
= get_max_uid ();
1233 int no_conflict_combined_regno
= -1;
1235 /* Count the instructions in the basic block. */
1237 insn
= BLOCK_END (b
);
1240 if (GET_CODE (insn
) != NOTE
)
1241 if (++insn_count
> max_uid
)
1243 if (insn
== BLOCK_HEAD (b
))
1245 insn
= PREV_INSN (insn
);
1248 /* +2 to leave room for a post_mark_life at the last insn and for
1249 the birth of a CLOBBER in the first insn. */
1250 regs_live_at
= (HARD_REG_SET
*) xcalloc ((2 * insn_count
+ 2),
1251 sizeof (HARD_REG_SET
));
1253 /* Initialize table of hardware registers currently live. */
1255 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1257 /* This loop scans the instructions of the basic block
1258 and assigns quantities to registers.
1259 It computes which registers to tie. */
1261 insn
= BLOCK_HEAD (b
);
1264 if (GET_CODE (insn
) != NOTE
)
1271 rtx r0
, r1
= NULL_RTX
;
1272 int combined_regno
= -1;
1275 this_insn_number
= insn_number
;
1278 extract_insn (insn
);
1279 which_alternative
= -1;
1281 /* Is this insn suitable for tying two registers?
1282 If so, try doing that.
1283 Suitable insns are those with at least two operands and where
1284 operand 0 is an output that is a register that is not
1287 We can tie operand 0 with some operand that dies in this insn.
1288 First look for operands that are required to be in the same
1289 register as operand 0. If we find such, only try tying that
1290 operand or one that can be put into that operand if the
1291 operation is commutative. If we don't find an operand
1292 that is required to be in the same register as operand 0,
1293 we can tie with any operand.
1295 Subregs in place of regs are also ok.
1297 If tying is done, WIN is set nonzero. */
1300 && recog_data
.n_operands
> 1
1301 && recog_data
.constraints
[0][0] == '='
1302 && recog_data
.constraints
[0][1] != '&')
1304 /* If non-negative, is an operand that must match operand 0. */
1305 int must_match_0
= -1;
1306 /* Counts number of alternatives that require a match with
1308 int n_matching_alts
= 0;
1310 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1312 const char *p
= recog_data
.constraints
[i
];
1313 int this_match
= requires_inout (p
);
1315 n_matching_alts
+= this_match
;
1316 if (this_match
== recog_data
.n_alternatives
)
1320 r0
= recog_data
.operand
[0];
1321 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1323 /* Skip this operand if we found an operand that
1324 must match operand 0 and this operand isn't it
1325 and can't be made to be it by commutativity. */
1327 if (must_match_0
>= 0 && i
!= must_match_0
1328 && ! (i
== must_match_0
+ 1
1329 && recog_data
.constraints
[i
-1][0] == '%')
1330 && ! (i
== must_match_0
- 1
1331 && recog_data
.constraints
[i
][0] == '%'))
1334 /* Likewise if each alternative has some operand that
1335 must match operand zero. In that case, skip any
1336 operand that doesn't list operand 0 since we know that
1337 the operand always conflicts with operand 0. We
1338 ignore commutatity in this case to keep things simple. */
1339 if (n_matching_alts
== recog_data
.n_alternatives
1340 && 0 == requires_inout (recog_data
.constraints
[i
]))
1343 r1
= recog_data
.operand
[i
];
1345 /* If the operand is an address, find a register in it.
1346 There may be more than one register, but we only try one
1348 if (recog_data
.constraints
[i
][0] == 'p')
1349 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1352 /* Avoid making a call-saved register unnecessarily
1354 hard_reg
= get_hard_reg_initial_reg (cfun
, r1
);
1355 if (hard_reg
!= NULL_RTX
)
1357 if (GET_CODE (hard_reg
) == REG
1358 && IN_RANGE (REGNO (hard_reg
),
1359 0, FIRST_PSEUDO_REGISTER
- 1)
1360 && ! call_used_regs
[REGNO (hard_reg
)])
1364 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1366 /* We have two priorities for hard register preferences.
1367 If we have a move insn or an insn whose first input
1368 can only be in the same register as the output, give
1369 priority to an equivalence found from that insn. */
1371 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1373 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1374 win
= combine_regs (r1
, r0
, may_save_copy
,
1375 insn_number
, insn
, 0);
1382 /* Recognize an insn sequence with an ultimate result
1383 which can safely overlap one of the inputs.
1384 The sequence begins with a CLOBBER of its result,
1385 and ends with an insn that copies the result to itself
1386 and has a REG_EQUAL note for an equivalent formula.
1387 That note indicates what the inputs are.
1388 The result and the input can overlap if each insn in
1389 the sequence either doesn't mention the input
1390 or has a REG_NO_CONFLICT note to inhibit the conflict.
1392 We do the combining test at the CLOBBER so that the
1393 destination register won't have had a quantity number
1394 assigned, since that would prevent combining. */
1397 && GET_CODE (PATTERN (insn
)) == CLOBBER
1398 && (r0
= XEXP (PATTERN (insn
), 0),
1399 GET_CODE (r0
) == REG
)
1400 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1401 && XEXP (link
, 0) != 0
1402 && GET_CODE (XEXP (link
, 0)) == INSN
1403 && (set
= single_set (XEXP (link
, 0))) != 0
1404 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1405 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1408 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1409 /* Check that we have such a sequence. */
1410 && no_conflict_p (insn
, r0
, r1
))
1411 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1412 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1413 && (r1
= XEXP (XEXP (note
, 0), 0),
1414 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1415 && no_conflict_p (insn
, r0
, r1
))
1416 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1418 /* Here we care if the operation to be computed is
1420 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1421 || GET_CODE (XEXP (note
, 0)) == NE
1422 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1423 && (r1
= XEXP (XEXP (note
, 0), 1),
1424 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1425 && no_conflict_p (insn
, r0
, r1
))
1426 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1428 /* If we did combine something, show the register number
1429 in question so that we know to ignore its death. */
1431 no_conflict_combined_regno
= REGNO (r1
);
1434 /* If registers were just tied, set COMBINED_REGNO
1435 to the number of the register used in this insn
1436 that was tied to the register set in this insn.
1437 This register's qty should not be "killed". */
1441 while (GET_CODE (r1
) == SUBREG
)
1442 r1
= SUBREG_REG (r1
);
1443 combined_regno
= REGNO (r1
);
1446 /* Mark the death of everything that dies in this instruction,
1447 except for anything that was just combined. */
1449 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1450 if (REG_NOTE_KIND (link
) == REG_DEAD
1451 && GET_CODE (XEXP (link
, 0)) == REG
1452 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1453 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1454 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1456 wipe_dead_reg (XEXP (link
, 0), 0);
1458 /* Allocate qty numbers for all registers local to this block
1459 that are born (set) in this instruction.
1460 A pseudo that already has a qty is not changed. */
1462 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1464 /* If anything is set in this insn and then unused, mark it as dying
1465 after this insn, so it will conflict with our outputs. This
1466 can't match with something that combined, and it doesn't matter
1467 if it did. Do this after the calls to reg_is_set since these
1468 die after, not during, the current insn. */
1470 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1471 if (REG_NOTE_KIND (link
) == REG_UNUSED
1472 && GET_CODE (XEXP (link
, 0)) == REG
)
1473 wipe_dead_reg (XEXP (link
, 0), 1);
1475 /* If this is an insn that has a REG_RETVAL note pointing at a
1476 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1477 block, so clear any register number that combined within it. */
1478 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1479 && GET_CODE (XEXP (note
, 0)) == INSN
1480 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1481 no_conflict_combined_regno
= -1;
1484 /* Set the registers live after INSN_NUMBER. Note that we never
1485 record the registers live before the block's first insn, since no
1486 pseudos we care about are live before that insn. */
1488 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1489 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1491 if (insn
== BLOCK_END (b
))
1494 insn
= NEXT_INSN (insn
);
1497 /* Now every register that is local to this basic block
1498 should have been given a quantity, or else -1 meaning ignore it.
1499 Every quantity should have a known birth and death.
1501 Order the qtys so we assign them registers in order of the
1502 number of suggested registers they need so we allocate those with
1503 the most restrictive needs first. */
1505 qty_order
= (int *) xmalloc (next_qty
* sizeof (int));
1506 for (i
= 0; i
< next_qty
; i
++)
1509 #define EXCHANGE(I1, I2) \
1510 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1515 /* Make qty_order[2] be the one to allocate last. */
1516 if (qty_sugg_compare (0, 1) > 0)
1518 if (qty_sugg_compare (1, 2) > 0)
1521 /* ... Fall through ... */
1523 /* Put the best one to allocate in qty_order[0]. */
1524 if (qty_sugg_compare (0, 1) > 0)
1527 /* ... Fall through ... */
1531 /* Nothing to do here. */
1535 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1538 /* Try to put each quantity in a suggested physical register, if it has one.
1539 This may cause registers to be allocated that otherwise wouldn't be, but
1540 this seems acceptable in local allocation (unlike global allocation). */
1541 for (i
= 0; i
< next_qty
; i
++)
1544 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1545 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1546 0, 1, qty
[q
].birth
, qty
[q
].death
);
1548 qty
[q
].phys_reg
= -1;
1551 /* Order the qtys so we assign them registers in order of
1552 decreasing length of life. Normally call qsort, but if we
1553 have only a very small number of quantities, sort them ourselves. */
1555 for (i
= 0; i
< next_qty
; i
++)
1558 #define EXCHANGE(I1, I2) \
1559 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1564 /* Make qty_order[2] be the one to allocate last. */
1565 if (qty_compare (0, 1) > 0)
1567 if (qty_compare (1, 2) > 0)
1570 /* ... Fall through ... */
1572 /* Put the best one to allocate in qty_order[0]. */
1573 if (qty_compare (0, 1) > 0)
1576 /* ... Fall through ... */
1580 /* Nothing to do here. */
1584 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1587 /* Now for each qty that is not a hardware register,
1588 look for a hardware register to put it in.
1589 First try the register class that is cheapest for this qty,
1590 if there is more than one class. */
1592 for (i
= 0; i
< next_qty
; i
++)
1595 if (qty
[q
].phys_reg
< 0)
1597 #ifdef INSN_SCHEDULING
1598 /* These values represent the adjusted lifetime of a qty so
1599 that it conflicts with qtys which appear near the start/end
1600 of this qty's lifetime.
1602 The purpose behind extending the lifetime of this qty is to
1603 discourage the register allocator from creating false
1606 The adjustment value is chosen to indicate that this qty
1607 conflicts with all the qtys in the instructions immediately
1608 before and after the lifetime of this qty.
1610 Experiments have shown that higher values tend to hurt
1611 overall code performance.
1613 If allocation using the extended lifetime fails we will try
1614 again with the qty's unadjusted lifetime. */
1615 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1616 int fake_death
= MIN (insn_number
* 2 + 1,
1617 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1620 if (N_REG_CLASSES
> 1)
1622 #ifdef INSN_SCHEDULING
1623 /* We try to avoid using hard registers allocated to qtys which
1624 are born immediately after this qty or die immediately before
1627 This optimization is only appropriate when we will run
1628 a scheduling pass after reload and we are not optimizing
1630 if (flag_schedule_insns_after_reload
1632 && !SMALL_REGISTER_CLASSES
)
1634 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1635 qty
[q
].mode
, q
, 0, 0,
1636 fake_birth
, fake_death
);
1637 if (qty
[q
].phys_reg
>= 0)
1641 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1642 qty
[q
].mode
, q
, 0, 0,
1643 qty
[q
].birth
, qty
[q
].death
);
1644 if (qty
[q
].phys_reg
>= 0)
1648 #ifdef INSN_SCHEDULING
1649 /* Similarly, avoid false dependencies. */
1650 if (flag_schedule_insns_after_reload
1652 && !SMALL_REGISTER_CLASSES
1653 && qty
[q
].alternate_class
!= NO_REGS
)
1654 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1655 qty
[q
].mode
, q
, 0, 0,
1656 fake_birth
, fake_death
);
1658 if (qty
[q
].alternate_class
!= NO_REGS
)
1659 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1660 qty
[q
].mode
, q
, 0, 0,
1661 qty
[q
].birth
, qty
[q
].death
);
1665 /* Now propagate the register assignments
1666 to the pseudo regs belonging to the qtys. */
1668 for (q
= 0; q
< next_qty
; q
++)
1669 if (qty
[q
].phys_reg
>= 0)
1671 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1672 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1676 free (regs_live_at
);
1680 /* Compare two quantities' priority for getting real registers.
1681 We give shorter-lived quantities higher priority.
1682 Quantities with more references are also preferred, as are quantities that
1683 require multiple registers. This is the identical prioritization as
1684 done by global-alloc.
1686 We used to give preference to registers with *longer* lives, but using
1687 the same algorithm in both local- and global-alloc can speed up execution
1688 of some programs by as much as a factor of three! */
1690 /* Note that the quotient will never be bigger than
1691 the value of floor_log2 times the maximum number of
1692 times a register can occur in one insn (surely less than 100)
1693 weighted by frequency (max REG_FREQ_MAX).
1694 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1695 QTY_CMP_PRI is also used by qty_sugg_compare. */
1697 #define QTY_CMP_PRI(q) \
1698 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1699 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1702 qty_compare (q1
, q2
)
1705 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1709 qty_compare_1 (q1p
, q2p
)
1713 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1714 int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1719 /* If qtys are equally good, sort by qty number,
1720 so that the results of qsort leave nothing to chance. */
1724 /* Compare two quantities' priority for getting real registers. This version
1725 is called for quantities that have suggested hard registers. First priority
1726 goes to quantities that have copy preferences, then to those that have
1727 normal preferences. Within those groups, quantities with the lower
1728 number of preferences have the highest priority. Of those, we use the same
1729 algorithm as above. */
1731 #define QTY_CMP_SUGG(q) \
1732 (qty_phys_num_copy_sugg[q] \
1733 ? qty_phys_num_copy_sugg[q] \
1734 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1737 qty_sugg_compare (q1
, q2
)
1740 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1745 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1749 qty_sugg_compare_1 (q1p
, q2p
)
1753 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1754 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1759 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1763 /* If qtys are equally good, sort by qty number,
1764 so that the results of qsort leave nothing to chance. */
1771 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1772 Returns 1 if have done so, or 0 if cannot.
1774 Combining registers means marking them as having the same quantity
1775 and adjusting the offsets within the quantity if either of
1778 We don't actually combine a hard reg with a pseudo; instead
1779 we just record the hard reg as the suggestion for the pseudo's quantity.
1780 If we really combined them, we could lose if the pseudo lives
1781 across an insn that clobbers the hard reg (eg, movstr).
1783 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1784 there is no REG_DEAD note on INSN. This occurs during the processing
1785 of REG_NO_CONFLICT blocks.
1787 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1788 SETREG or if the input and output must share a register.
1789 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1791 There are elaborate checks for the validity of combining. */
1794 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1795 rtx usedreg
, setreg
;
1806 /* Determine the numbers and sizes of registers being used. If a subreg
1807 is present that does not change the entire register, don't consider
1808 this a copy insn. */
1810 while (GET_CODE (usedreg
) == SUBREG
)
1812 rtx subreg
= SUBREG_REG (usedreg
);
1814 if (GET_CODE (subreg
) == REG
)
1816 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1819 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1820 offset
+= subreg_regno_offset (REGNO (subreg
),
1822 SUBREG_BYTE (usedreg
),
1823 GET_MODE (usedreg
));
1825 offset
+= (SUBREG_BYTE (usedreg
)
1826 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1832 if (GET_CODE (usedreg
) != REG
)
1835 ureg
= REGNO (usedreg
);
1836 if (ureg
< FIRST_PSEUDO_REGISTER
)
1837 usize
= HARD_REGNO_NREGS (ureg
, GET_MODE (usedreg
));
1839 usize
= ((GET_MODE_SIZE (GET_MODE (usedreg
))
1840 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)) - 1))
1841 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1843 while (GET_CODE (setreg
) == SUBREG
)
1845 rtx subreg
= SUBREG_REG (setreg
);
1847 if (GET_CODE (subreg
) == REG
)
1849 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1852 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1853 offset
-= subreg_regno_offset (REGNO (subreg
),
1855 SUBREG_BYTE (setreg
),
1858 offset
-= (SUBREG_BYTE (setreg
)
1859 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1865 if (GET_CODE (setreg
) != REG
)
1868 sreg
= REGNO (setreg
);
1869 if (sreg
< FIRST_PSEUDO_REGISTER
)
1870 ssize
= HARD_REGNO_NREGS (sreg
, GET_MODE (setreg
));
1872 ssize
= ((GET_MODE_SIZE (GET_MODE (setreg
))
1873 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg
)) - 1))
1874 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1876 /* If UREG is a pseudo-register that hasn't already been assigned a
1877 quantity number, it means that it is not local to this block or dies
1878 more than once. In either event, we can't do anything with it. */
1879 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1880 /* Do not combine registers unless one fits within the other. */
1881 || (offset
> 0 && usize
+ offset
> ssize
)
1882 || (offset
< 0 && usize
+ offset
< ssize
)
1883 /* Do not combine with a smaller already-assigned object
1884 if that smaller object is already combined with something bigger. */
1885 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1886 && usize
< qty
[reg_qty
[ureg
]].size
)
1887 /* Can't combine if SREG is not a register we can allocate. */
1888 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1889 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1890 These have already been taken care of. This probably wouldn't
1891 combine anyway, but don't take any chances. */
1892 || (ureg
>= FIRST_PSEUDO_REGISTER
1893 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1894 /* Don't tie something to itself. In most cases it would make no
1895 difference, but it would screw up if the reg being tied to itself
1896 also dies in this insn. */
1898 /* Don't try to connect two different hardware registers. */
1899 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1900 /* Don't connect two different machine modes if they have different
1901 implications as to which registers may be used. */
1902 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1905 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1906 qty_phys_sugg for the pseudo instead of tying them.
1908 Return "failure" so that the lifespan of UREG is terminated here;
1909 that way the two lifespans will be disjoint and nothing will prevent
1910 the pseudo reg from being given this hard reg. */
1912 if (ureg
< FIRST_PSEUDO_REGISTER
)
1914 /* Allocate a quantity number so we have a place to put our
1916 if (reg_qty
[sreg
] == -2)
1917 reg_is_born (setreg
, 2 * insn_number
);
1919 if (reg_qty
[sreg
] >= 0)
1922 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1924 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1925 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1927 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1929 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1930 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1936 /* Similarly for SREG a hard register and UREG a pseudo register. */
1938 if (sreg
< FIRST_PSEUDO_REGISTER
)
1941 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1943 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1944 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1946 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1948 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1949 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1954 /* At this point we know that SREG and UREG are both pseudos.
1955 Do nothing if SREG already has a quantity or is a register that we
1957 if (reg_qty
[sreg
] >= -1
1958 /* If we are not going to let any regs live across calls,
1959 don't tie a call-crossing reg to a non-call-crossing reg. */
1960 || (current_function_has_nonlocal_label
1961 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1962 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1965 /* We don't already know about SREG, so tie it to UREG
1966 if this is the last use of UREG, provided the classes they want
1969 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1970 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1972 /* Add SREG to UREG's quantity. */
1973 sqty
= reg_qty
[ureg
];
1974 reg_qty
[sreg
] = sqty
;
1975 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1976 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1977 qty
[sqty
].first_reg
= sreg
;
1979 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1980 update_qty_class (sqty
, sreg
);
1982 /* Update info about quantity SQTY. */
1983 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1984 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1985 qty
[sqty
].freq
+= REG_FREQ (sreg
);
1990 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1991 reg_offset
[i
] -= offset
;
1993 qty
[sqty
].size
= ssize
;
1994 qty
[sqty
].mode
= GET_MODE (setreg
);
2003 /* Return 1 if the preferred class of REG allows it to be tied
2004 to a quantity or register whose class is CLASS.
2005 True if REG's reg class either contains or is contained in CLASS. */
2008 reg_meets_class_p (reg
, class)
2010 enum reg_class
class;
2012 enum reg_class rclass
= reg_preferred_class (reg
);
2013 return (reg_class_subset_p (rclass
, class)
2014 || reg_class_subset_p (class, rclass
));
2017 /* Update the class of QTYNO assuming that REG is being tied to it. */
2020 update_qty_class (qtyno
, reg
)
2024 enum reg_class rclass
= reg_preferred_class (reg
);
2025 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
2026 qty
[qtyno
].min_class
= rclass
;
2028 rclass
= reg_alternate_class (reg
);
2029 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
2030 qty
[qtyno
].alternate_class
= rclass
;
2032 if (REG_CHANGES_MODE (reg
))
2033 qty
[qtyno
].changes_mode
= 1;
2036 /* Handle something which alters the value of an rtx REG.
2038 REG is whatever is set or clobbered. SETTER is the rtx that
2039 is modifying the register.
2041 If it is not really a register, we do nothing.
2042 The file-global variables `this_insn' and `this_insn_number'
2043 carry info from `block_alloc'. */
2046 reg_is_set (reg
, setter
, data
)
2049 void *data ATTRIBUTE_UNUSED
;
2051 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2052 a hard register. These may actually not exist any more. */
2054 if (GET_CODE (reg
) != SUBREG
2055 && GET_CODE (reg
) != REG
)
2058 /* Mark this register as being born. If it is used in a CLOBBER, mark
2059 it as being born halfway between the previous insn and this insn so that
2060 it conflicts with our inputs but not the outputs of the previous insn. */
2062 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
2065 /* Handle beginning of the life of register REG.
2066 BIRTH is the index at which this is happening. */
2069 reg_is_born (reg
, birth
)
2075 if (GET_CODE (reg
) == SUBREG
)
2077 regno
= REGNO (SUBREG_REG (reg
));
2078 if (regno
< FIRST_PSEUDO_REGISTER
)
2079 regno
= subreg_hard_regno (reg
, 1);
2082 regno
= REGNO (reg
);
2084 if (regno
< FIRST_PSEUDO_REGISTER
)
2086 mark_life (regno
, GET_MODE (reg
), 1);
2088 /* If the register was to have been born earlier that the present
2089 insn, mark it as live where it is actually born. */
2090 if (birth
< 2 * this_insn_number
)
2091 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
2095 if (reg_qty
[regno
] == -2)
2096 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
2098 /* If this register has a quantity number, show that it isn't dead. */
2099 if (reg_qty
[regno
] >= 0)
2100 qty
[reg_qty
[regno
]].death
= -1;
2104 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2105 REG is an output that is dying (i.e., it is never used), otherwise it
2106 is an input (the normal case).
2107 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2110 wipe_dead_reg (reg
, output_p
)
2114 int regno
= REGNO (reg
);
2116 /* If this insn has multiple results,
2117 and the dead reg is used in one of the results,
2118 extend its life to after this insn,
2119 so it won't get allocated together with any other result of this insn.
2121 It is unsafe to use !single_set here since it will ignore an unused
2122 output. Just because an output is unused does not mean the compiler
2123 can assume the side effect will not occur. Consider if REG appears
2124 in the address of an output and we reload the output. If we allocate
2125 REG to the same hard register as an unused output we could set the hard
2126 register before the output reload insn. */
2127 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
2128 && multiple_sets (this_insn
))
2131 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
2133 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
2134 if (GET_CODE (set
) == SET
2135 && GET_CODE (SET_DEST (set
)) != REG
2136 && !rtx_equal_p (reg
, SET_DEST (set
))
2137 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2142 /* If this register is used in an auto-increment address, then extend its
2143 life to after this insn, so that it won't get allocated together with
2144 the result of this insn. */
2145 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
2148 if (regno
< FIRST_PSEUDO_REGISTER
)
2150 mark_life (regno
, GET_MODE (reg
), 0);
2152 /* If a hard register is dying as an output, mark it as in use at
2153 the beginning of this insn (the above statement would cause this
2156 post_mark_life (regno
, GET_MODE (reg
), 1,
2157 2 * this_insn_number
, 2 * this_insn_number
+ 1);
2160 else if (reg_qty
[regno
] >= 0)
2161 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
2164 /* Find a block of SIZE words of hard regs in reg_class CLASS
2165 that can hold something of machine-mode MODE
2166 (but actually we test only the first of the block for holding MODE)
2167 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2168 and return the number of the first of them.
2169 Return -1 if such a block cannot be found.
2170 If QTYNO crosses calls, insist on a register preserved by calls,
2171 unless ACCEPT_CALL_CLOBBERED is nonzero.
2173 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2174 register is available. If not, return -1. */
2177 find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, just_try_suggested
,
2178 born_index
, dead_index
)
2179 enum reg_class
class;
2180 enum machine_mode mode
;
2182 int accept_call_clobbered
;
2183 int just_try_suggested
;
2184 int born_index
, dead_index
;
2188 /* Declare it register if it's a scalar. */
2191 HARD_REG_SET used
, first_used
;
2192 #ifdef ELIMINABLE_REGS
2193 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2196 /* Validate our parameters. */
2197 if (born_index
< 0 || born_index
> dead_index
)
2200 /* Don't let a pseudo live in a reg across a function call
2201 if we might get a nonlocal goto. */
2202 if (current_function_has_nonlocal_label
2203 && qty
[qtyno
].n_calls_crossed
> 0)
2206 if (accept_call_clobbered
)
2207 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
2208 else if (qty
[qtyno
].n_calls_crossed
== 0)
2209 COPY_HARD_REG_SET (used
, fixed_reg_set
);
2211 COPY_HARD_REG_SET (used
, call_used_reg_set
);
2213 if (accept_call_clobbered
)
2214 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
2216 for (ins
= born_index
; ins
< dead_index
; ins
++)
2217 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
2219 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
2221 /* Don't use the frame pointer reg in local-alloc even if
2222 we may omit the frame pointer, because if we do that and then we
2223 need a frame pointer, reload won't know how to move the pseudo
2224 to another hard reg. It can move only regs made by global-alloc.
2226 This is true of any register that can be eliminated. */
2227 #ifdef ELIMINABLE_REGS
2228 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2229 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2230 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2231 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2232 that it might be eliminated into. */
2233 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2236 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2239 #ifdef CLASS_CANNOT_CHANGE_MODE
2240 if (qty
[qtyno
].changes_mode
)
2241 IOR_HARD_REG_SET (used
,
2242 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
]);
2245 /* Normally, the registers that can be used for the first register in
2246 a multi-register quantity are the same as those that can be used for
2247 subsequent registers. However, if just trying suggested registers,
2248 restrict our consideration to them. If there are copy-suggested
2249 register, try them. Otherwise, try the arithmetic-suggested
2251 COPY_HARD_REG_SET (first_used
, used
);
2253 if (just_try_suggested
)
2255 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2256 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2258 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2261 /* If all registers are excluded, we can't do anything. */
2262 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2264 /* If at least one would be suitable, test each hard reg. */
2266 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2268 #ifdef REG_ALLOC_ORDER
2269 int regno
= reg_alloc_order
[i
];
2273 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2274 && HARD_REGNO_MODE_OK (regno
, mode
)
2275 && (qty
[qtyno
].n_calls_crossed
== 0
2276 || accept_call_clobbered
2277 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2280 int size1
= HARD_REGNO_NREGS (regno
, mode
);
2281 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2284 /* Mark that this register is in use between its birth and death
2286 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2289 #ifndef REG_ALLOC_ORDER
2290 /* Skip starting points we know will lose. */
2297 /* If we are just trying suggested register, we have just tried copy-
2298 suggested registers, and there are arithmetic-suggested registers,
2301 /* If it would be profitable to allocate a call-clobbered register
2302 and save and restore it around calls, do that. */
2303 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2304 && qty_phys_num_sugg
[qtyno
] != 0)
2306 /* Don't try the copy-suggested regs again. */
2307 qty_phys_num_copy_sugg
[qtyno
] = 0;
2308 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2309 born_index
, dead_index
);
2312 /* We need not check to see if the current function has nonlocal
2313 labels because we don't put any pseudos that are live over calls in
2314 registers in that case. */
2316 if (! accept_call_clobbered
2317 && flag_caller_saves
2318 && ! just_try_suggested
2319 && qty
[qtyno
].n_calls_crossed
!= 0
2320 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2321 qty
[qtyno
].n_calls_crossed
))
2323 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2325 caller_save_needed
= 1;
2331 /* Mark that REGNO with machine-mode MODE is live starting from the current
2332 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2336 mark_life (regno
, mode
, life
)
2338 enum machine_mode mode
;
2341 int j
= HARD_REGNO_NREGS (regno
, mode
);
2344 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2347 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2350 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2351 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2352 to insn number DEATH (exclusive). */
2355 post_mark_life (regno
, mode
, life
, birth
, death
)
2357 enum machine_mode mode
;
2358 int life
, birth
, death
;
2360 int j
= HARD_REGNO_NREGS (regno
, mode
);
2362 /* Declare it register if it's a scalar. */
2365 HARD_REG_SET this_reg
;
2367 CLEAR_HARD_REG_SET (this_reg
);
2369 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2372 while (birth
< death
)
2374 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2378 while (birth
< death
)
2380 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2385 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2386 is the register being clobbered, and R1 is a register being used in
2387 the equivalent expression.
2389 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2390 in which it is used, return 1.
2392 Otherwise, return 0. */
2395 no_conflict_p (insn
, r0
, r1
)
2396 rtx insn
, r0 ATTRIBUTE_UNUSED
, r1
;
2399 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2402 /* If R1 is a hard register, return 0 since we handle this case
2403 when we scan the insns that actually use it. */
2406 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2407 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2408 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2411 last
= XEXP (note
, 0);
2413 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2416 if (find_reg_note (p
, REG_DEAD
, r1
))
2419 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2420 some earlier optimization pass has inserted instructions into
2421 the sequence, and it is not safe to perform this optimization.
2422 Note that emit_no_conflict_block always ensures that this is
2423 true when these sequences are created. */
2424 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2431 /* Return the number of alternatives for which the constraint string P
2432 indicates that the operand must be equal to operand 0 and that no register
2441 int reg_allowed
= 0;
2442 int num_matching_alts
= 0;
2447 case '=': case '+': case '?':
2448 case '#': case '&': case '!':
2450 case 'm': case '<': case '>': case 'V': case 'o':
2451 case 'E': case 'F': case 'G': case 'H':
2452 case 's': case 'i': case 'n':
2453 case 'I': case 'J': case 'K': case 'L':
2454 case 'M': case 'N': case 'O': case 'P':
2456 /* These don't say anything we care about. */
2460 if (found_zero
&& ! reg_allowed
)
2461 num_matching_alts
++;
2463 found_zero
= reg_allowed
= 0;
2470 case '1': case '2': case '3': case '4': case '5':
2471 case '6': case '7': case '8': case '9':
2472 /* Skip the balance of the matching constraint. */
2473 while (ISDIGIT (*p
))
2478 if (REG_CLASS_FROM_LETTER (c
) == NO_REGS
)
2487 if (found_zero
&& ! reg_allowed
)
2488 num_matching_alts
++;
2490 return num_matching_alts
;
2494 dump_local_alloc (file
)
2498 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2499 if (reg_renumber
[i
] != -1)
2500 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);