1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36 #include "addresses.h"
38 #include "hard-reg-set.h"
39 #include "function-abi.h"
41 /* Forward declarations */
42 static void set_of_1 (rtx
, const_rtx
, void *);
43 static bool covers_regno_p (const_rtx
, unsigned int);
44 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
45 static int computed_jump_p_1 (const_rtx
);
46 static void parms_set (rtx
, const_rtx
, void *);
48 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, scalar_int_mode
,
49 const_rtx
, machine_mode
,
50 unsigned HOST_WIDE_INT
);
51 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, scalar_int_mode
,
52 const_rtx
, machine_mode
,
53 unsigned HOST_WIDE_INT
);
54 static unsigned int cached_num_sign_bit_copies (const_rtx
, scalar_int_mode
,
55 const_rtx
, machine_mode
,
57 static unsigned int num_sign_bit_copies1 (const_rtx
, scalar_int_mode
,
58 const_rtx
, machine_mode
,
61 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
62 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
64 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
65 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
66 SIGN_EXTEND then while narrowing we also have to enforce the
67 representation and sign-extend the value to mode DESTINATION_REP.
69 If the value is already sign-extended to DESTINATION_REP mode we
70 can just switch to DESTINATION mode on it. For each pair of
71 integral modes SOURCE and DESTINATION, when truncating from SOURCE
72 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
73 contains the number of high-order bits in SOURCE that have to be
74 copies of the sign-bit so that we can do this mode-switch to
78 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
80 /* Store X into index I of ARRAY. ARRAY is known to have at least I
81 elements. Return the new base of ARRAY. */
84 typename
T::value_type
*
85 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
87 size_t i
, value_type x
)
89 if (base
== array
.stack
)
96 gcc_checking_assert (i
== LOCAL_ELEMS
);
97 /* A previous iteration might also have moved from the stack to the
98 heap, in which case the heap array will already be big enough. */
99 if (vec_safe_length (array
.heap
) <= i
)
100 vec_safe_grow (array
.heap
, i
+ 1);
101 base
= array
.heap
->address ();
102 memcpy (base
, array
.stack
, sizeof (array
.stack
));
103 base
[LOCAL_ELEMS
] = x
;
106 unsigned int length
= array
.heap
->length ();
109 gcc_checking_assert (base
== array
.heap
->address ());
115 gcc_checking_assert (i
== length
);
116 vec_safe_push (array
.heap
, x
);
117 return array
.heap
->address ();
121 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
122 number of elements added to the worklist. */
124 template <typename T
>
126 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
128 size_t end
, rtx_type x
)
130 enum rtx_code code
= GET_CODE (x
);
131 const char *format
= GET_RTX_FORMAT (code
);
132 size_t orig_end
= end
;
133 if (__builtin_expect (INSN_P (x
), false))
135 /* Put the pattern at the top of the queue, since that's what
136 we're likely to want most. It also allows for the SEQUENCE
138 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
139 if (format
[i
] == 'e')
141 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
142 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
145 base
= add_single_to_queue (array
, base
, end
++, subx
);
149 for (int i
= 0; format
[i
]; ++i
)
150 if (format
[i
] == 'e')
152 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
153 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
156 base
= add_single_to_queue (array
, base
, end
++, subx
);
158 else if (format
[i
] == 'E')
160 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
161 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
162 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
163 for (unsigned int j
= 0; j
< length
; j
++)
164 base
[end
++] = T::get_value (vec
[j
]);
166 for (unsigned int j
= 0; j
< length
; j
++)
167 base
= add_single_to_queue (array
, base
, end
++,
168 T::get_value (vec
[j
]));
169 if (code
== SEQUENCE
&& end
== length
)
170 /* If the subrtxes of the sequence fill the entire array then
171 we know that no other parts of a containing insn are queued.
172 The caller is therefore iterating over the sequence as a
173 PATTERN (...), so we also want the patterns of the
175 for (unsigned int j
= 0; j
< length
; j
++)
177 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
179 base
[j
] = T::get_value (PATTERN (x
));
182 return end
- orig_end
;
185 template <typename T
>
187 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
189 vec_free (array
.heap
);
192 template <typename T
>
193 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
195 template class generic_subrtx_iterator
<const_rtx_accessor
>;
196 template class generic_subrtx_iterator
<rtx_var_accessor
>;
197 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
199 /* Return 1 if the value of X is unstable
200 (would be different at a different point in the program).
201 The frame pointer, arg pointer, etc. are considered stable
202 (within one function) and so is anything marked `unchanging'. */
205 rtx_unstable_p (const_rtx x
)
207 const RTX_CODE code
= GET_CODE (x
);
214 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
223 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
224 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
225 /* The arg pointer varies if it is not a fixed register. */
226 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
228 /* ??? When call-clobbered, the value is stable modulo the restore
229 that must happen after a call. This currently screws up local-alloc
230 into believing that the restore is not needed. */
231 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
236 if (MEM_VOLATILE_P (x
))
245 fmt
= GET_RTX_FORMAT (code
);
246 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
249 if (rtx_unstable_p (XEXP (x
, i
)))
252 else if (fmt
[i
] == 'E')
255 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
256 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
263 /* Return 1 if X has a value that can vary even between two
264 executions of the program. 0 means X can be compared reliably
265 against certain constants or near-constants.
266 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
267 zero, we are slightly more conservative.
268 The frame pointer and the arg pointer are considered constant. */
271 rtx_varies_p (const_rtx x
, bool for_alias
)
284 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
293 /* Note that we have to test for the actual rtx used for the frame
294 and arg pointers and not just the register number in case we have
295 eliminated the frame and/or arg pointer and are using it
297 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
298 /* The arg pointer varies if it is not a fixed register. */
299 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
301 if (x
== pic_offset_table_rtx
302 /* ??? When call-clobbered, the value is stable modulo the restore
303 that must happen after a call. This currently screws up
304 local-alloc into believing that the restore is not needed, so we
305 must return 0 only if we are called from alias analysis. */
306 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
311 /* The operand 0 of a LO_SUM is considered constant
312 (in fact it is related specifically to operand 1)
313 during alias analysis. */
314 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
315 || rtx_varies_p (XEXP (x
, 1), for_alias
);
318 if (MEM_VOLATILE_P (x
))
327 fmt
= GET_RTX_FORMAT (code
);
328 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
331 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
334 else if (fmt
[i
] == 'E')
337 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
338 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
345 /* Compute an approximation for the offset between the register
346 FROM and TO for the current function, as it was at the start
350 get_initial_register_offset (int from
, int to
)
352 static const struct elim_table_t
356 } table
[] = ELIMINABLE_REGS
;
357 poly_int64 offset1
, offset2
;
363 /* It is not safe to call INITIAL_ELIMINATION_OFFSET before the epilogue
364 is completed, but we need to give at least an estimate for the stack
365 pointer based on the frame size. */
366 if (!epilogue_completed
)
368 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
369 #if !STACK_GROWS_DOWNWARD
372 if (to
== STACK_POINTER_REGNUM
)
374 else if (from
== STACK_POINTER_REGNUM
)
380 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
381 if (table
[i
].from
== from
)
383 if (table
[i
].to
== to
)
385 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
389 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
391 if (table
[j
].to
== to
392 && table
[j
].from
== table
[i
].to
)
394 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
396 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
398 return offset1
+ offset2
;
400 if (table
[j
].from
== to
401 && table
[j
].to
== table
[i
].to
)
403 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
405 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
407 return offset1
- offset2
;
411 else if (table
[i
].to
== from
)
413 if (table
[i
].from
== to
)
415 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
419 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
421 if (table
[j
].to
== to
422 && table
[j
].from
== table
[i
].from
)
424 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
426 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
428 return - offset1
+ offset2
;
430 if (table
[j
].from
== to
431 && table
[j
].to
== table
[i
].from
)
433 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
435 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
437 return - offset1
- offset2
;
442 /* If the requested register combination was not found,
443 try a different more simple combination. */
444 if (from
== ARG_POINTER_REGNUM
)
445 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
446 else if (to
== ARG_POINTER_REGNUM
)
447 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
448 else if (from
== HARD_FRAME_POINTER_REGNUM
)
449 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
450 else if (to
== HARD_FRAME_POINTER_REGNUM
)
451 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
456 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
457 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
458 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
459 references on strict alignment machines. */
462 rtx_addr_can_trap_p_1 (const_rtx x
, poly_int64 offset
, poly_int64 size
,
463 machine_mode mode
, bool unaligned_mems
)
465 enum rtx_code code
= GET_CODE (x
);
466 gcc_checking_assert (mode
== BLKmode
|| known_size_p (size
));
469 /* The offset must be a multiple of the mode size if we are considering
470 unaligned memory references on strict alignment machines. */
471 if (STRICT_ALIGNMENT
&& unaligned_mems
&& mode
!= BLKmode
)
473 poly_int64 actual_offset
= offset
;
475 #ifdef SPARC_STACK_BOUNDARY_HACK
476 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
477 the real alignment of %sp. However, when it does this, the
478 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
479 if (SPARC_STACK_BOUNDARY_HACK
480 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
481 actual_offset
-= STACK_POINTER_OFFSET
;
484 if (!multiple_p (actual_offset
, GET_MODE_SIZE (mode
)))
491 if (SYMBOL_REF_WEAK (x
))
493 if (!CONSTANT_POOL_ADDRESS_P (x
) && !SYMBOL_REF_FUNCTION_P (x
))
496 poly_int64 decl_size
;
498 if (maybe_lt (offset
, 0))
500 if (!known_size_p (size
))
501 return maybe_ne (offset
, 0);
503 /* If the size of the access or of the symbol is unknown,
505 decl
= SYMBOL_REF_DECL (x
);
507 /* Else check that the access is in bounds. TODO: restructure
508 expr_size/tree_expr_size/int_expr_size and just use the latter. */
511 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
513 if (!poly_int_tree_p (DECL_SIZE_UNIT (decl
), &decl_size
))
516 else if (TREE_CODE (decl
) == STRING_CST
)
517 decl_size
= TREE_STRING_LENGTH (decl
);
518 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
519 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
523 return (!known_size_p (decl_size
) || known_eq (decl_size
, 0)
524 ? maybe_ne (offset
, 0)
525 : !known_subrange_p (offset
, size
, 0, decl_size
));
534 /* Stack references are assumed not to trap, but we need to deal with
535 nonsensical offsets. */
536 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
537 || x
== stack_pointer_rtx
538 /* The arg pointer varies if it is not a fixed register. */
539 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
542 poly_int64 red_zone_size
= RED_ZONE_SIZE
;
544 poly_int64 red_zone_size
= 0;
546 poly_int64 stack_boundary
= PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
;
547 poly_int64 low_bound
, high_bound
;
549 if (!known_size_p (size
))
552 if (x
== frame_pointer_rtx
)
554 if (FRAME_GROWS_DOWNWARD
)
556 high_bound
= targetm
.starting_frame_offset ();
557 low_bound
= high_bound
- get_frame_size ();
561 low_bound
= targetm
.starting_frame_offset ();
562 high_bound
= low_bound
+ get_frame_size ();
565 else if (x
== hard_frame_pointer_rtx
)
568 = get_initial_register_offset (STACK_POINTER_REGNUM
,
569 HARD_FRAME_POINTER_REGNUM
);
571 = get_initial_register_offset (ARG_POINTER_REGNUM
,
572 HARD_FRAME_POINTER_REGNUM
);
574 #if STACK_GROWS_DOWNWARD
575 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
576 high_bound
= ap_offset
577 + FIRST_PARM_OFFSET (current_function_decl
)
578 #if !ARGS_GROW_DOWNWARD
583 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
584 low_bound
= ap_offset
585 + FIRST_PARM_OFFSET (current_function_decl
)
586 #if ARGS_GROW_DOWNWARD
592 else if (x
== stack_pointer_rtx
)
595 = get_initial_register_offset (ARG_POINTER_REGNUM
,
596 STACK_POINTER_REGNUM
);
598 #if STACK_GROWS_DOWNWARD
599 low_bound
= - red_zone_size
- stack_boundary
;
600 high_bound
= ap_offset
601 + FIRST_PARM_OFFSET (current_function_decl
)
602 #if !ARGS_GROW_DOWNWARD
607 high_bound
= red_zone_size
+ stack_boundary
;
608 low_bound
= ap_offset
609 + FIRST_PARM_OFFSET (current_function_decl
)
610 #if ARGS_GROW_DOWNWARD
618 /* We assume that accesses are safe to at least the
620 Examples are varargs and __builtin_return_address. */
621 #if ARGS_GROW_DOWNWARD
622 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
624 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
625 - crtl
->args
.size
- stack_boundary
;
627 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
629 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
630 + crtl
->args
.size
+ stack_boundary
;
634 if (known_ge (offset
, low_bound
)
635 && known_le (offset
, high_bound
- size
))
639 /* All of the virtual frame registers are stack references. */
640 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
641 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
646 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
647 mode
, unaligned_mems
);
650 /* An address is assumed not to trap if:
651 - it is the pic register plus a const unspec without offset. */
652 if (XEXP (x
, 0) == pic_offset_table_rtx
653 && GET_CODE (XEXP (x
, 1)) == CONST
654 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == UNSPEC
655 && known_eq (offset
, 0))
658 /* - or it is an address that can't trap plus a constant integer. */
659 if (poly_int_rtx_p (XEXP (x
, 1), &const_x1
)
660 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ const_x1
,
661 size
, mode
, unaligned_mems
))
668 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
669 mode
, unaligned_mems
);
676 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
677 mode
, unaligned_mems
);
683 /* If it isn't one of the case above, it can cause a trap. */
687 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
690 rtx_addr_can_trap_p (const_rtx x
)
692 return rtx_addr_can_trap_p_1 (x
, 0, -1, BLKmode
, false);
695 /* Return true if X contains a MEM subrtx. */
698 contains_mem_rtx_p (rtx x
)
700 subrtx_iterator::array_type array
;
701 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
708 /* Return true if X is an address that is known to not be zero. */
711 nonzero_address_p (const_rtx x
)
713 const enum rtx_code code
= GET_CODE (x
);
718 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
724 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
725 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
726 || x
== stack_pointer_rtx
727 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
729 /* All of the virtual frame registers are stack references. */
730 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
731 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
736 return nonzero_address_p (XEXP (x
, 0));
739 /* Handle PIC references. */
740 if (XEXP (x
, 0) == pic_offset_table_rtx
741 && CONSTANT_P (XEXP (x
, 1)))
746 /* Similar to the above; allow positive offsets. Further, since
747 auto-inc is only allowed in memories, the register must be a
749 if (CONST_INT_P (XEXP (x
, 1))
750 && INTVAL (XEXP (x
, 1)) > 0)
752 return nonzero_address_p (XEXP (x
, 0));
755 /* Similarly. Further, the offset is always positive. */
762 return nonzero_address_p (XEXP (x
, 0));
765 return nonzero_address_p (XEXP (x
, 1));
771 /* If it isn't one of the case above, might be zero. */
775 /* Return 1 if X refers to a memory location whose address
776 cannot be compared reliably with constant addresses,
777 or if X refers to a BLKmode memory object.
778 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
779 zero, we are slightly more conservative. */
782 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
793 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
795 fmt
= GET_RTX_FORMAT (code
);
796 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
799 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
802 else if (fmt
[i
] == 'E')
805 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
806 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
812 /* Return the CALL in X if there is one. */
815 get_call_rtx_from (const rtx_insn
*insn
)
817 rtx x
= PATTERN (insn
);
818 if (GET_CODE (x
) == PARALLEL
)
819 x
= XVECEXP (x
, 0, 0);
820 if (GET_CODE (x
) == SET
)
822 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
827 /* Get the declaration of the function called by INSN. */
830 get_call_fndecl (const rtx_insn
*insn
)
834 note
= find_reg_note (insn
, REG_CALL_DECL
, NULL_RTX
);
835 if (note
== NULL_RTX
)
838 datum
= XEXP (note
, 0);
839 if (datum
!= NULL_RTX
)
840 return SYMBOL_REF_DECL (datum
);
845 /* Return the value of the integer term in X, if one is apparent;
847 Only obvious integer terms are detected.
848 This is used in cse.c with the `related_value' field. */
851 get_integer_term (const_rtx x
)
853 if (GET_CODE (x
) == CONST
)
856 if (GET_CODE (x
) == MINUS
857 && CONST_INT_P (XEXP (x
, 1)))
858 return - INTVAL (XEXP (x
, 1));
859 if (GET_CODE (x
) == PLUS
860 && CONST_INT_P (XEXP (x
, 1)))
861 return INTVAL (XEXP (x
, 1));
865 /* If X is a constant, return the value sans apparent integer term;
867 Only obvious integer terms are detected. */
870 get_related_value (const_rtx x
)
872 if (GET_CODE (x
) != CONST
)
875 if (GET_CODE (x
) == PLUS
876 && CONST_INT_P (XEXP (x
, 1)))
878 else if (GET_CODE (x
) == MINUS
879 && CONST_INT_P (XEXP (x
, 1)))
884 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
885 to somewhere in the same object or object_block as SYMBOL. */
888 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
892 if (GET_CODE (symbol
) != SYMBOL_REF
)
900 if (CONSTANT_POOL_ADDRESS_P (symbol
)
901 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
904 decl
= SYMBOL_REF_DECL (symbol
);
905 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
909 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
910 && SYMBOL_REF_BLOCK (symbol
)
911 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
912 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
913 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
919 /* Split X into a base and a constant offset, storing them in *BASE_OUT
920 and *OFFSET_OUT respectively. */
923 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
925 if (GET_CODE (x
) == CONST
)
928 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
930 *base_out
= XEXP (x
, 0);
931 *offset_out
= XEXP (x
, 1);
936 *offset_out
= const0_rtx
;
939 /* Express integer value X as some value Y plus a polynomial offset,
940 where Y is either const0_rtx, X or something within X (as opposed
941 to a new rtx). Return the Y and store the offset in *OFFSET_OUT. */
944 strip_offset (rtx x
, poly_int64_pod
*offset_out
)
946 rtx base
= const0_rtx
;
948 if (GET_CODE (test
) == CONST
)
949 test
= XEXP (test
, 0);
950 if (GET_CODE (test
) == PLUS
)
952 base
= XEXP (test
, 0);
953 test
= XEXP (test
, 1);
955 if (poly_int_rtx_p (test
, offset_out
))
961 /* Return the argument size in REG_ARGS_SIZE note X. */
964 get_args_size (const_rtx x
)
966 gcc_checking_assert (REG_NOTE_KIND (x
) == REG_ARGS_SIZE
);
967 return rtx_to_poly_int64 (XEXP (x
, 0));
970 /* Return the number of places FIND appears within X. If COUNT_DEST is
971 zero, we do not count occurrences inside the destination of a SET. */
974 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
978 const char *format_ptr
;
997 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
999 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
1003 if (MEM_P (find
) && rtx_equal_p (x
, find
))
1008 if (SET_DEST (x
) == find
&& ! count_dest
)
1009 return count_occurrences (SET_SRC (x
), find
, count_dest
);
1016 format_ptr
= GET_RTX_FORMAT (code
);
1019 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
1021 switch (*format_ptr
++)
1024 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
1028 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1029 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
1037 /* Return TRUE if OP is a register or subreg of a register that
1038 holds an unsigned quantity. Otherwise, return FALSE. */
1041 unsigned_reg_p (rtx op
)
1045 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1048 if (GET_CODE (op
) == SUBREG
1049 && SUBREG_PROMOTED_SIGN (op
))
1056 /* Nonzero if register REG appears somewhere within IN.
1057 Also works if REG is not a register; in this case it checks
1058 for a subexpression of IN that is Lisp "equal" to REG. */
1061 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1073 if (GET_CODE (in
) == LABEL_REF
)
1074 return reg
== label_ref_label (in
);
1076 code
= GET_CODE (in
);
1080 /* Compare registers by number. */
1082 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1084 /* These codes have no constituent expressions
1092 /* These are kept unique for a given value. */
1099 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1102 fmt
= GET_RTX_FORMAT (code
);
1104 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1109 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1110 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1113 else if (fmt
[i
] == 'e'
1114 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1120 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1121 no CODE_LABEL insn. */
1124 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1129 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1135 /* Nonzero if register REG is used in an insn between
1136 FROM_INSN and TO_INSN (exclusive of those two). */
1139 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1140 const rtx_insn
*to_insn
)
1144 if (from_insn
== to_insn
)
1147 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1148 if (NONDEBUG_INSN_P (insn
)
1149 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1150 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1155 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1156 is entirely replaced by a new value and the only use is as a SET_DEST,
1157 we do not consider it a reference. */
1160 reg_referenced_p (const_rtx x
, const_rtx body
)
1164 switch (GET_CODE (body
))
1167 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1170 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1171 of a REG that occupies all of the REG, the insn references X if
1172 it is mentioned in the destination. */
1173 if (GET_CODE (SET_DEST (body
)) != CC0
1174 && GET_CODE (SET_DEST (body
)) != PC
1175 && !REG_P (SET_DEST (body
))
1176 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1177 && REG_P (SUBREG_REG (SET_DEST (body
)))
1178 && !read_modify_subreg_p (SET_DEST (body
)))
1179 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1184 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1185 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1192 return reg_overlap_mentioned_p (x
, body
);
1195 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1198 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1201 case UNSPEC_VOLATILE
:
1202 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1203 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1208 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1209 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1214 if (MEM_P (XEXP (body
, 0)))
1215 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1220 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1222 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1229 /* Nonzero if register REG is set or clobbered in an insn between
1230 FROM_INSN and TO_INSN (exclusive of those two). */
1233 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1234 const rtx_insn
*to_insn
)
1236 const rtx_insn
*insn
;
1238 if (from_insn
== to_insn
)
1241 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1242 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1247 /* Return true if REG is set or clobbered inside INSN. */
1250 reg_set_p (const_rtx reg
, const_rtx insn
)
1252 /* After delay slot handling, call and branch insns might be in a
1253 sequence. Check all the elements there. */
1254 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1256 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1257 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1263 /* We can be passed an insn or part of one. If we are passed an insn,
1264 check if a side-effect of the insn clobbers REG. */
1266 && (FIND_REG_INC_NOTE (insn
, reg
)
1269 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1270 && (insn_callee_abi (as_a
<const rtx_insn
*> (insn
))
1271 .clobbers_reg_p (GET_MODE (reg
), REGNO (reg
))))
1273 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1276 /* There are no REG_INC notes for SP autoinc. */
1277 if (reg
== stack_pointer_rtx
&& INSN_P (insn
))
1279 subrtx_var_iterator::array_type array
;
1280 FOR_EACH_SUBRTX_VAR (iter
, array
, PATTERN (insn
), NONCONST
)
1285 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
1287 if (XEXP (XEXP (mem
, 0), 0) == stack_pointer_rtx
)
1289 iter
.skip_subrtxes ();
1294 return set_of (reg
, insn
) != NULL_RTX
;
1297 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1298 only if none of them are modified between START and END. Return 1 if
1299 X contains a MEM; this routine does use memory aliasing. */
1302 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1304 const enum rtx_code code
= GET_CODE (x
);
1325 if (modified_between_p (XEXP (x
, 0), start
, end
))
1327 if (MEM_READONLY_P (x
))
1329 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1330 if (memory_modified_in_insn_p (x
, insn
))
1335 return reg_set_between_p (x
, start
, end
);
1341 fmt
= GET_RTX_FORMAT (code
);
1342 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1344 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1347 else if (fmt
[i
] == 'E')
1348 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1349 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1356 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1357 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1358 does use memory aliasing. */
1361 modified_in_p (const_rtx x
, const_rtx insn
)
1363 const enum rtx_code code
= GET_CODE (x
);
1380 if (modified_in_p (XEXP (x
, 0), insn
))
1382 if (MEM_READONLY_P (x
))
1384 if (memory_modified_in_insn_p (x
, insn
))
1389 return reg_set_p (x
, insn
);
1395 fmt
= GET_RTX_FORMAT (code
);
1396 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1398 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1401 else if (fmt
[i
] == 'E')
1402 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1403 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1410 /* Return true if X is a SUBREG and if storing a value to X would
1411 preserve some of its SUBREG_REG. For example, on a normal 32-bit
1412 target, using a SUBREG to store to one half of a DImode REG would
1413 preserve the other half. */
1416 read_modify_subreg_p (const_rtx x
)
1418 if (GET_CODE (x
) != SUBREG
)
1420 poly_uint64 isize
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)));
1421 poly_uint64 osize
= GET_MODE_SIZE (GET_MODE (x
));
1422 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x
)));
1423 /* The inner and outer modes of a subreg must be ordered, so that we
1424 can tell whether they're paradoxical or partial. */
1425 gcc_checking_assert (ordered_p (isize
, osize
));
1426 return (maybe_gt (isize
, osize
) && maybe_gt (isize
, regsize
));
1429 /* Helper function for set_of. */
1437 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1439 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1440 if (rtx_equal_p (x
, data
->pat
)
1441 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1445 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1446 (either directly or via STRICT_LOW_PART and similar modifiers). */
1448 set_of (const_rtx pat
, const_rtx insn
)
1450 struct set_of_data data
;
1451 data
.found
= NULL_RTX
;
1453 note_pattern_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1457 /* Add all hard register in X to *PSET. */
1459 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1461 subrtx_iterator::array_type array
;
1462 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1464 const_rtx x
= *iter
;
1465 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1466 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1470 /* This function, called through note_stores, collects sets and
1471 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1474 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1476 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1477 if (REG_P (x
) && HARD_REGISTER_P (x
))
1478 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1481 /* Examine INSN, and compute the set of hard registers written by it.
1482 Store it in *PSET. Should only be called after reload.
1484 IMPLICIT is true if we should include registers that are fully-clobbered
1485 by calls. This should be used with caution, since it doesn't include
1486 partially-clobbered registers. */
1488 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1492 CLEAR_HARD_REG_SET (*pset
);
1493 note_stores (insn
, record_hard_reg_sets
, pset
);
1494 if (CALL_P (insn
) && implicit
)
1495 *pset
|= insn_callee_abi (insn
).full_reg_clobbers ();
1496 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1497 if (REG_NOTE_KIND (link
) == REG_INC
)
1498 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1501 /* Like record_hard_reg_sets, but called through note_uses. */
1503 record_hard_reg_uses (rtx
*px
, void *data
)
1505 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1508 /* Given an INSN, return a SET expression if this insn has only a single SET.
1509 It may also have CLOBBERs, USEs, or SET whose output
1510 will not be used, which we ignore. */
1513 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1516 int set_verified
= 1;
1519 if (GET_CODE (pat
) == PARALLEL
)
1521 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1523 rtx sub
= XVECEXP (pat
, 0, i
);
1524 switch (GET_CODE (sub
))
1531 /* We can consider insns having multiple sets, where all
1532 but one are dead as single set insns. In common case
1533 only single set is present in the pattern so we want
1534 to avoid checking for REG_UNUSED notes unless necessary.
1536 When we reach set first time, we just expect this is
1537 the single set we are looking for and only when more
1538 sets are found in the insn, we check them. */
1541 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1542 && !side_effects_p (set
))
1548 set
= sub
, set_verified
= 0;
1549 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1550 || side_effects_p (sub
))
1562 /* Given an INSN, return nonzero if it has more than one SET, else return
1566 multiple_sets (const_rtx insn
)
1571 /* INSN must be an insn. */
1572 if (! INSN_P (insn
))
1575 /* Only a PARALLEL can have multiple SETs. */
1576 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1578 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1579 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1581 /* If we have already found a SET, then return now. */
1589 /* Either zero or one SET. */
1593 /* Return nonzero if the destination of SET equals the source
1594 and there are no side effects. */
1597 set_noop_p (const_rtx set
)
1599 rtx src
= SET_SRC (set
);
1600 rtx dst
= SET_DEST (set
);
1602 if (dst
== pc_rtx
&& src
== pc_rtx
)
1605 if (MEM_P (dst
) && MEM_P (src
))
1606 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1608 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1609 return rtx_equal_p (XEXP (dst
, 0), src
)
1610 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1611 && !side_effects_p (src
);
1613 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1614 dst
= XEXP (dst
, 0);
1616 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1618 if (maybe_ne (SUBREG_BYTE (src
), SUBREG_BYTE (dst
)))
1620 src
= SUBREG_REG (src
);
1621 dst
= SUBREG_REG (dst
);
1624 /* It is a NOOP if destination overlaps with selected src vector
1626 if (GET_CODE (src
) == VEC_SELECT
1627 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1628 && HARD_REGISTER_P (XEXP (src
, 0))
1629 && HARD_REGISTER_P (dst
))
1632 rtx par
= XEXP (src
, 1);
1633 rtx src0
= XEXP (src
, 0);
1635 if (!poly_int_rtx_p (XVECEXP (par
, 0, 0), &c0
))
1637 poly_int64 offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1639 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1642 if (!poly_int_rtx_p (XVECEXP (par
, 0, i
), &c0i
)
1643 || maybe_ne (c0i
, c0
+ i
))
1647 REG_CAN_CHANGE_MODE_P (REGNO (dst
), GET_MODE (src0
), GET_MODE (dst
))
1648 && simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1649 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1652 return (REG_P (src
) && REG_P (dst
)
1653 && REGNO (src
) == REGNO (dst
));
1656 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1660 noop_move_p (const rtx_insn
*insn
)
1662 rtx pat
= PATTERN (insn
);
1664 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1667 /* Insns carrying these notes are useful later on. */
1668 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1671 /* Check the code to be executed for COND_EXEC. */
1672 if (GET_CODE (pat
) == COND_EXEC
)
1673 pat
= COND_EXEC_CODE (pat
);
1675 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1678 if (GET_CODE (pat
) == PARALLEL
)
1681 /* If nothing but SETs of registers to themselves,
1682 this insn can also be deleted. */
1683 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1685 rtx tem
= XVECEXP (pat
, 0, i
);
1687 if (GET_CODE (tem
) == USE
|| GET_CODE (tem
) == CLOBBER
)
1690 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1700 /* Return nonzero if register in range [REGNO, ENDREGNO)
1701 appears either explicitly or implicitly in X
1702 other than being stored into.
1704 References contained within the substructure at LOC do not count.
1705 LOC may be zero, meaning don't ignore anything. */
1708 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1712 unsigned int x_regno
;
1717 /* The contents of a REG_NONNEG note is always zero, so we must come here
1718 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1722 code
= GET_CODE (x
);
1727 x_regno
= REGNO (x
);
1729 /* If we modifying the stack, frame, or argument pointer, it will
1730 clobber a virtual register. In fact, we could be more precise,
1731 but it isn't worth it. */
1732 if ((x_regno
== STACK_POINTER_REGNUM
1733 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1734 && x_regno
== ARG_POINTER_REGNUM
)
1735 || x_regno
== FRAME_POINTER_REGNUM
)
1736 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1739 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1742 /* If this is a SUBREG of a hard reg, we can see exactly which
1743 registers are being modified. Otherwise, handle normally. */
1744 if (REG_P (SUBREG_REG (x
))
1745 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1747 unsigned int inner_regno
= subreg_regno (x
);
1748 unsigned int inner_endregno
1749 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1750 ? subreg_nregs (x
) : 1);
1752 return endregno
> inner_regno
&& regno
< inner_endregno
;
1758 if (&SET_DEST (x
) != loc
1759 /* Note setting a SUBREG counts as referring to the REG it is in for
1760 a pseudo but not for hard registers since we can
1761 treat each word individually. */
1762 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1763 && loc
!= &SUBREG_REG (SET_DEST (x
))
1764 && REG_P (SUBREG_REG (SET_DEST (x
)))
1765 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1766 && refers_to_regno_p (regno
, endregno
,
1767 SUBREG_REG (SET_DEST (x
)), loc
))
1768 || (!REG_P (SET_DEST (x
))
1769 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1772 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1781 /* X does not match, so try its subexpressions. */
1783 fmt
= GET_RTX_FORMAT (code
);
1784 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1786 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1794 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1797 else if (fmt
[i
] == 'E')
1800 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1801 if (loc
!= &XVECEXP (x
, i
, j
)
1802 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1809 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1810 we check if any register number in X conflicts with the relevant register
1811 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1812 contains a MEM (we don't bother checking for memory addresses that can't
1813 conflict because we expect this to be a rare case. */
1816 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1818 unsigned int regno
, endregno
;
1820 /* If either argument is a constant, then modifying X cannot
1821 affect IN. Here we look at IN, we can profitably combine
1822 CONSTANT_P (x) with the switch statement below. */
1823 if (CONSTANT_P (in
))
1827 switch (GET_CODE (x
))
1830 case STRICT_LOW_PART
:
1833 /* Overly conservative. */
1838 regno
= REGNO (SUBREG_REG (x
));
1839 if (regno
< FIRST_PSEUDO_REGISTER
)
1840 regno
= subreg_regno (x
);
1841 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1842 ? subreg_nregs (x
) : 1);
1847 endregno
= END_REGNO (x
);
1849 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1859 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1860 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1863 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1866 else if (fmt
[i
] == 'E')
1869 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1870 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1880 return reg_mentioned_p (x
, in
);
1886 /* If any register in here refers to it we return true. */
1887 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1888 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1889 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1895 gcc_assert (CONSTANT_P (x
));
1900 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1901 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1902 ignored by note_stores, but passed to FUN.
1904 FUN receives three arguments:
1905 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1906 2. the SET or CLOBBER rtx that does the store,
1907 3. the pointer DATA provided to note_stores.
1909 If the item being stored in or clobbered is a SUBREG of a hard register,
1910 the SUBREG will be passed. */
1913 note_pattern_stores (const_rtx x
,
1914 void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1918 if (GET_CODE (x
) == COND_EXEC
)
1919 x
= COND_EXEC_CODE (x
);
1921 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1923 rtx dest
= SET_DEST (x
);
1925 while ((GET_CODE (dest
) == SUBREG
1926 && (!REG_P (SUBREG_REG (dest
))
1927 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1928 || GET_CODE (dest
) == ZERO_EXTRACT
1929 || GET_CODE (dest
) == STRICT_LOW_PART
)
1930 dest
= XEXP (dest
, 0);
1932 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1933 each of whose first operand is a register. */
1934 if (GET_CODE (dest
) == PARALLEL
)
1936 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1937 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1938 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1941 (*fun
) (dest
, x
, data
);
1944 else if (GET_CODE (x
) == PARALLEL
)
1945 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1946 note_pattern_stores (XVECEXP (x
, 0, i
), fun
, data
);
1949 /* Same, but for an instruction. If the instruction is a call, include
1950 any CLOBBERs in its CALL_INSN_FUNCTION_USAGE. */
1953 note_stores (const rtx_insn
*insn
,
1954 void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1957 for (rtx link
= CALL_INSN_FUNCTION_USAGE (insn
);
1958 link
; link
= XEXP (link
, 1))
1959 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1960 note_pattern_stores (XEXP (link
, 0), fun
, data
);
1961 note_pattern_stores (PATTERN (insn
), fun
, data
);
1964 /* Like notes_stores, but call FUN for each expression that is being
1965 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1966 FUN for each expression, not any interior subexpressions. FUN receives a
1967 pointer to the expression and the DATA passed to this function.
1969 Note that this is not quite the same test as that done in reg_referenced_p
1970 since that considers something as being referenced if it is being
1971 partially set, while we do not. */
1974 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1979 switch (GET_CODE (body
))
1982 (*fun
) (&COND_EXEC_TEST (body
), data
);
1983 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1987 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1988 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1992 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1993 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1997 (*fun
) (&XEXP (body
, 0), data
);
2001 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
2002 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
2006 (*fun
) (&TRAP_CONDITION (body
), data
);
2010 (*fun
) (&XEXP (body
, 0), data
);
2014 case UNSPEC_VOLATILE
:
2015 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
2016 (*fun
) (&XVECEXP (body
, 0, i
), data
);
2020 if (MEM_P (XEXP (body
, 0)))
2021 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
2026 rtx dest
= SET_DEST (body
);
2028 /* For sets we replace everything in source plus registers in memory
2029 expression in store and operands of a ZERO_EXTRACT. */
2030 (*fun
) (&SET_SRC (body
), data
);
2032 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2034 (*fun
) (&XEXP (dest
, 1), data
);
2035 (*fun
) (&XEXP (dest
, 2), data
);
2038 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
2039 dest
= XEXP (dest
, 0);
2042 (*fun
) (&XEXP (dest
, 0), data
);
2047 /* All the other possibilities never store. */
2048 (*fun
) (pbody
, data
);
2053 /* Return nonzero if X's old contents don't survive after INSN.
2054 This will be true if X is (cc0) or if X is a register and
2055 X dies in INSN or because INSN entirely sets X.
2057 "Entirely set" means set directly and not through a SUBREG, or
2058 ZERO_EXTRACT, so no trace of the old contents remains.
2059 Likewise, REG_INC does not count.
2061 REG may be a hard or pseudo reg. Renumbering is not taken into account,
2062 but for this use that makes no difference, since regs don't overlap
2063 during their lifetimes. Therefore, this function may be used
2064 at any time after deaths have been computed.
2066 If REG is a hard reg that occupies multiple machine registers, this
2067 function will only return 1 if each of those registers will be replaced
2071 dead_or_set_p (const rtx_insn
*insn
, const_rtx x
)
2073 unsigned int regno
, end_regno
;
2076 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
2077 if (GET_CODE (x
) == CC0
)
2080 gcc_assert (REG_P (x
));
2083 end_regno
= END_REGNO (x
);
2084 for (i
= regno
; i
< end_regno
; i
++)
2085 if (! dead_or_set_regno_p (insn
, i
))
2091 /* Return TRUE iff DEST is a register or subreg of a register, is a
2092 complete rather than read-modify-write destination, and contains
2093 register TEST_REGNO. */
2096 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2098 unsigned int regno
, endregno
;
2100 if (GET_CODE (dest
) == SUBREG
&& !read_modify_subreg_p (dest
))
2101 dest
= SUBREG_REG (dest
);
2106 regno
= REGNO (dest
);
2107 endregno
= END_REGNO (dest
);
2108 return (test_regno
>= regno
&& test_regno
< endregno
);
2111 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2112 any member matches the covers_regno_no_parallel_p criteria. */
2115 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2117 if (GET_CODE (dest
) == PARALLEL
)
2119 /* Some targets place small structures in registers for return
2120 values of functions, and those registers are wrapped in
2121 PARALLELs that we may see as the destination of a SET. */
2124 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2126 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2127 if (inner
!= NULL_RTX
2128 && covers_regno_no_parallel_p (inner
, test_regno
))
2135 return covers_regno_no_parallel_p (dest
, test_regno
);
2138 /* Utility function for dead_or_set_p to check an individual register. */
2141 dead_or_set_regno_p (const rtx_insn
*insn
, unsigned int test_regno
)
2145 /* See if there is a death note for something that includes TEST_REGNO. */
2146 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2150 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2153 pattern
= PATTERN (insn
);
2155 /* If a COND_EXEC is not executed, the value survives. */
2156 if (GET_CODE (pattern
) == COND_EXEC
)
2159 if (GET_CODE (pattern
) == SET
|| GET_CODE (pattern
) == CLOBBER
)
2160 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2161 else if (GET_CODE (pattern
) == PARALLEL
)
2165 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2167 rtx body
= XVECEXP (pattern
, 0, i
);
2169 if (GET_CODE (body
) == COND_EXEC
)
2170 body
= COND_EXEC_CODE (body
);
2172 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2173 && covers_regno_p (SET_DEST (body
), test_regno
))
2181 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2182 If DATUM is nonzero, look for one whose datum is DATUM. */
2185 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2189 gcc_checking_assert (insn
);
2191 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2192 if (! INSN_P (insn
))
2196 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2197 if (REG_NOTE_KIND (link
) == kind
)
2202 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2203 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2208 /* Return the reg-note of kind KIND in insn INSN which applies to register
2209 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2210 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2211 it might be the case that the note overlaps REGNO. */
2214 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2218 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2219 if (! INSN_P (insn
))
2222 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2223 if (REG_NOTE_KIND (link
) == kind
2224 /* Verify that it is a register, so that scratch and MEM won't cause a
2226 && REG_P (XEXP (link
, 0))
2227 && REGNO (XEXP (link
, 0)) <= regno
2228 && END_REGNO (XEXP (link
, 0)) > regno
)
2233 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2237 find_reg_equal_equiv_note (const_rtx insn
)
2244 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2245 if (REG_NOTE_KIND (link
) == REG_EQUAL
2246 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2248 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2249 insns that have multiple sets. Checking single_set to
2250 make sure of this is not the proper check, as explained
2251 in the comment in set_unique_reg_note.
2253 This should be changed into an assert. */
2254 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2261 /* Check whether INSN is a single_set whose source is known to be
2262 equivalent to a constant. Return that constant if so, otherwise
2266 find_constant_src (const rtx_insn
*insn
)
2270 set
= single_set (insn
);
2273 x
= avoid_constant_pool_reference (SET_SRC (set
));
2278 note
= find_reg_equal_equiv_note (insn
);
2279 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2280 return XEXP (note
, 0);
2285 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2286 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2289 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2291 /* If it's not a CALL_INSN, it can't possibly have a
2292 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2302 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2304 link
= XEXP (link
, 1))
2305 if (GET_CODE (XEXP (link
, 0)) == code
2306 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2311 unsigned int regno
= REGNO (datum
);
2313 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2314 to pseudo registers, so don't bother checking. */
2316 if (regno
< FIRST_PSEUDO_REGISTER
)
2318 unsigned int end_regno
= END_REGNO (datum
);
2321 for (i
= regno
; i
< end_regno
; i
++)
2322 if (find_regno_fusage (insn
, code
, i
))
2330 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2331 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2334 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2338 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2339 to pseudo registers, so don't bother checking. */
2341 if (regno
>= FIRST_PSEUDO_REGISTER
2345 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2349 if (GET_CODE (op
= XEXP (link
, 0)) == code
2350 && REG_P (reg
= XEXP (op
, 0))
2351 && REGNO (reg
) <= regno
2352 && END_REGNO (reg
) > regno
)
2360 /* Return true if KIND is an integer REG_NOTE. */
2363 int_reg_note_p (enum reg_note kind
)
2365 return kind
== REG_BR_PROB
;
2368 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2369 stored as the pointer to the next register note. */
2372 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2376 gcc_checking_assert (!int_reg_note_p (kind
));
2381 case REG_LABEL_TARGET
:
2382 case REG_LABEL_OPERAND
:
2384 /* These types of register notes use an INSN_LIST rather than an
2385 EXPR_LIST, so that copying is done right and dumps look
2387 note
= alloc_INSN_LIST (datum
, list
);
2388 PUT_REG_NOTE_KIND (note
, kind
);
2392 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2399 /* Add register note with kind KIND and datum DATUM to INSN. */
2402 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2404 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2407 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2410 add_int_reg_note (rtx_insn
*insn
, enum reg_note kind
, int datum
)
2412 gcc_checking_assert (int_reg_note_p (kind
));
2413 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2414 datum
, REG_NOTES (insn
));
2417 /* Add a REG_ARGS_SIZE note to INSN with value VALUE. */
2420 add_args_size_note (rtx_insn
*insn
, poly_int64 value
)
2422 gcc_checking_assert (!find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
));
2423 add_reg_note (insn
, REG_ARGS_SIZE
, gen_int_mode (value
, Pmode
));
2426 /* Add a register note like NOTE to INSN. */
2429 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2431 if (GET_CODE (note
) == INT_LIST
)
2432 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2434 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2437 /* Duplicate NOTE and return the copy. */
2439 duplicate_reg_note (rtx note
)
2441 reg_note kind
= REG_NOTE_KIND (note
);
2443 if (GET_CODE (note
) == INT_LIST
)
2444 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2445 else if (GET_CODE (note
) == EXPR_LIST
)
2446 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2448 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2451 /* Remove register note NOTE from the REG_NOTES of INSN. */
2454 remove_note (rtx_insn
*insn
, const_rtx note
)
2458 if (note
== NULL_RTX
)
2461 if (REG_NOTES (insn
) == note
)
2462 REG_NOTES (insn
) = XEXP (note
, 1);
2464 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2465 if (XEXP (link
, 1) == note
)
2467 XEXP (link
, 1) = XEXP (note
, 1);
2471 switch (REG_NOTE_KIND (note
))
2475 df_notes_rescan (insn
);
2482 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2483 Return true if any note has been removed. */
2486 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2491 loc
= ®_NOTES (insn
);
2494 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2495 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2497 *loc
= XEXP (*loc
, 1);
2501 loc
= &XEXP (*loc
, 1);
2506 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2509 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2516 /* This loop is a little tricky. We cannot just go down the chain because
2517 it is being modified by some actions in the loop. So we just iterate
2518 over the head. We plan to drain the list anyway. */
2519 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2521 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2522 rtx note
= find_reg_equal_equiv_note (insn
);
2524 /* This assert is generally triggered when someone deletes a REG_EQUAL
2525 or REG_EQUIV note by hacking the list manually rather than calling
2529 remove_note (insn
, note
);
2533 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2534 return 1 if it is found. A simple equality test is used to determine if
2538 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2542 for (x
= listp
; x
; x
= XEXP (x
, 1))
2543 if (node
== XEXP (x
, 0))
2549 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2550 remove that entry from the list if it is found.
2552 A simple equality test is used to determine if NODE matches. */
2555 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2557 rtx_expr_list
*temp
= *listp
;
2558 rtx_expr_list
*prev
= NULL
;
2562 if (node
== temp
->element ())
2564 /* Splice the node out of the list. */
2566 XEXP (prev
, 1) = temp
->next ();
2568 *listp
= temp
->next ();
2574 temp
= temp
->next ();
2578 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2579 remove that entry from the list if it is found.
2581 A simple equality test is used to determine if NODE matches. */
2584 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2586 rtx_insn_list
*temp
= *listp
;
2587 rtx_insn_list
*prev
= NULL
;
2591 if (node
== temp
->insn ())
2593 /* Splice the node out of the list. */
2595 XEXP (prev
, 1) = temp
->next ();
2597 *listp
= temp
->next ();
2603 temp
= temp
->next ();
2607 /* Nonzero if X contains any volatile instructions. These are instructions
2608 which may cause unpredictable machine state instructions, and thus no
2609 instructions or register uses should be moved or combined across them.
2610 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2613 volatile_insn_p (const_rtx x
)
2615 const RTX_CODE code
= GET_CODE (x
);
2633 case UNSPEC_VOLATILE
:
2638 if (MEM_VOLATILE_P (x
))
2645 /* Recursively scan the operands of this expression. */
2648 const char *const fmt
= GET_RTX_FORMAT (code
);
2651 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2655 if (volatile_insn_p (XEXP (x
, i
)))
2658 else if (fmt
[i
] == 'E')
2661 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2662 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2670 /* Nonzero if X contains any volatile memory references
2671 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2674 volatile_refs_p (const_rtx x
)
2676 const RTX_CODE code
= GET_CODE (x
);
2692 case UNSPEC_VOLATILE
:
2698 if (MEM_VOLATILE_P (x
))
2705 /* Recursively scan the operands of this expression. */
2708 const char *const fmt
= GET_RTX_FORMAT (code
);
2711 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2715 if (volatile_refs_p (XEXP (x
, i
)))
2718 else if (fmt
[i
] == 'E')
2721 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2722 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2730 /* Similar to above, except that it also rejects register pre- and post-
2734 side_effects_p (const_rtx x
)
2736 const RTX_CODE code
= GET_CODE (x
);
2753 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2754 when some combination can't be done. If we see one, don't think
2755 that we can simplify the expression. */
2756 return (GET_MODE (x
) != VOIDmode
);
2765 case UNSPEC_VOLATILE
:
2771 if (MEM_VOLATILE_P (x
))
2778 /* Recursively scan the operands of this expression. */
2781 const char *fmt
= GET_RTX_FORMAT (code
);
2784 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2788 if (side_effects_p (XEXP (x
, i
)))
2791 else if (fmt
[i
] == 'E')
2794 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2795 if (side_effects_p (XVECEXP (x
, i
, j
)))
2803 /* Return nonzero if evaluating rtx X might cause a trap.
2804 FLAGS controls how to consider MEMs. A nonzero means the context
2805 of the access may have changed from the original, such that the
2806 address may have become invalid. */
2809 may_trap_p_1 (const_rtx x
, unsigned flags
)
2815 /* We make no distinction currently, but this function is part of
2816 the internal target-hooks ABI so we keep the parameter as
2817 "unsigned flags". */
2818 bool code_changed
= flags
!= 0;
2822 code
= GET_CODE (x
);
2825 /* Handle these cases quickly. */
2837 return targetm
.unspec_may_trap_p (x
, flags
);
2839 case UNSPEC_VOLATILE
:
2845 return MEM_VOLATILE_P (x
);
2847 /* Memory ref can trap unless it's a static var or a stack slot. */
2849 /* Recognize specific pattern of stack checking probes. */
2850 if (flag_stack_check
2851 && MEM_VOLATILE_P (x
)
2852 && XEXP (x
, 0) == stack_pointer_rtx
)
2854 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2855 reference; moving it out of context such as when moving code
2856 when optimizing, might cause its address to become invalid. */
2858 || !MEM_NOTRAP_P (x
))
2860 poly_int64 size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : -1;
2861 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2862 GET_MODE (x
), code_changed
);
2867 /* Division by a non-constant might trap. */
2872 if (HONOR_SNANS (x
))
2874 if (FLOAT_MODE_P (GET_MODE (x
)))
2875 return flag_trapping_math
;
2876 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2878 if (GET_CODE (XEXP (x
, 1)) == CONST_VECTOR
)
2880 /* For CONST_VECTOR, return 1 if any element is or might be zero. */
2881 unsigned int n_elts
;
2882 rtx op
= XEXP (x
, 1);
2883 if (!GET_MODE_NUNITS (GET_MODE (op
)).is_constant (&n_elts
))
2885 if (!CONST_VECTOR_DUPLICATE_P (op
))
2887 for (unsigned i
= 0; i
< (unsigned int) XVECLEN (op
, 0); i
++)
2888 if (CONST_VECTOR_ENCODED_ELT (op
, i
) == const0_rtx
)
2892 for (unsigned i
= 0; i
< n_elts
; i
++)
2893 if (CONST_VECTOR_ELT (op
, i
) == const0_rtx
)
2899 /* An EXPR_LIST is used to represent a function call. This
2900 certainly may trap. */
2909 /* Some floating point comparisons may trap. */
2910 if (!flag_trapping_math
)
2912 /* ??? There is no machine independent way to check for tests that trap
2913 when COMPARE is used, though many targets do make this distinction.
2914 For instance, sparc uses CCFPE for compares which generate exceptions
2915 and CCFP for compares which do not generate exceptions. */
2918 /* But often the compare has some CC mode, so check operand
2920 if (HONOR_NANS (XEXP (x
, 0))
2921 || HONOR_NANS (XEXP (x
, 1)))
2927 if (HONOR_SNANS (x
))
2929 /* Often comparison is CC mode, so check operand modes. */
2930 if (HONOR_SNANS (XEXP (x
, 0))
2931 || HONOR_SNANS (XEXP (x
, 1)))
2936 /* Conversion of floating point might trap. */
2937 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2948 /* These operations don't trap even with floating point. */
2952 /* Any floating arithmetic may trap. */
2953 if (FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2957 fmt
= GET_RTX_FORMAT (code
);
2958 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2962 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2965 else if (fmt
[i
] == 'E')
2968 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2969 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2976 /* Return nonzero if evaluating rtx X might cause a trap. */
2979 may_trap_p (const_rtx x
)
2981 return may_trap_p_1 (x
, 0);
2984 /* Same as above, but additionally return nonzero if evaluating rtx X might
2985 cause a fault. We define a fault for the purpose of this function as a
2986 erroneous execution condition that cannot be encountered during the normal
2987 execution of a valid program; the typical example is an unaligned memory
2988 access on a strict alignment machine. The compiler guarantees that it
2989 doesn't generate code that will fault from a valid program, but this
2990 guarantee doesn't mean anything for individual instructions. Consider
2991 the following example:
2993 struct S { int d; union { char *cp; int *ip; }; };
2995 int foo(struct S *s)
3003 on a strict alignment machine. In a valid program, foo will never be
3004 invoked on a structure for which d is equal to 1 and the underlying
3005 unique field of the union not aligned on a 4-byte boundary, but the
3006 expression *s->ip might cause a fault if considered individually.
3008 At the RTL level, potentially problematic expressions will almost always
3009 verify may_trap_p; for example, the above dereference can be emitted as
3010 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
3011 However, suppose that foo is inlined in a caller that causes s->cp to
3012 point to a local character variable and guarantees that s->d is not set
3013 to 1; foo may have been effectively translated into pseudo-RTL as:
3016 (set (reg:SI) (mem:SI (%fp - 7)))
3018 (set (reg:QI) (mem:QI (%fp - 7)))
3020 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
3021 memory reference to a stack slot, but it will certainly cause a fault
3022 on a strict alignment machine. */
3025 may_trap_or_fault_p (const_rtx x
)
3027 return may_trap_p_1 (x
, 1);
3030 /* Replace any occurrence of FROM in X with TO. The function does
3031 not enter into CONST_DOUBLE for the replace.
3033 Note that copying is not done so X must not be shared unless all copies
3036 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
3037 those pointer-equal ones. */
3040 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
3048 /* Allow this function to make replacements in EXPR_LISTs. */
3055 && REGNO (x
) == REGNO (from
))
3057 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
3060 else if (GET_CODE (x
) == SUBREG
)
3062 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
3064 if (CONST_INT_P (new_rtx
))
3066 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
3067 GET_MODE (SUBREG_REG (x
)),
3072 SUBREG_REG (x
) = new_rtx
;
3076 else if (GET_CODE (x
) == ZERO_EXTEND
)
3078 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
3080 if (CONST_INT_P (new_rtx
))
3082 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3083 new_rtx
, GET_MODE (XEXP (x
, 0)));
3087 XEXP (x
, 0) = new_rtx
;
3092 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3093 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3096 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
3097 else if (fmt
[i
] == 'E')
3098 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3099 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3100 from
, to
, all_regs
);
3106 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3107 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3110 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3112 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3114 if (JUMP_TABLE_DATA_P (x
))
3117 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3118 int len
= GET_NUM_ELEM (vec
);
3119 for (int i
= 0; i
< len
; ++i
)
3121 rtx ref
= RTVEC_ELT (vec
, i
);
3122 if (XEXP (ref
, 0) == old_label
)
3124 XEXP (ref
, 0) = new_label
;
3125 if (update_label_nuses
)
3127 ++LABEL_NUSES (new_label
);
3128 --LABEL_NUSES (old_label
);
3135 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3136 field. This is not handled by the iterator because it doesn't
3137 handle unprinted ('0') fields. */
3138 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3139 JUMP_LABEL (x
) = new_label
;
3141 subrtx_ptr_iterator::array_type array
;
3142 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3147 if (GET_CODE (x
) == SYMBOL_REF
3148 && CONSTANT_POOL_ADDRESS_P (x
))
3150 rtx c
= get_pool_constant (x
);
3151 if (rtx_referenced_p (old_label
, c
))
3153 /* Create a copy of constant C; replace the label inside
3154 but do not update LABEL_NUSES because uses in constant pool
3156 rtx new_c
= copy_rtx (c
);
3157 replace_label (&new_c
, old_label
, new_label
, false);
3159 /* Add the new constant NEW_C to constant pool and replace
3160 the old reference to constant by new reference. */
3161 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3162 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3166 if ((GET_CODE (x
) == LABEL_REF
3167 || GET_CODE (x
) == INSN_LIST
)
3168 && XEXP (x
, 0) == old_label
)
3170 XEXP (x
, 0) = new_label
;
3171 if (update_label_nuses
)
3173 ++LABEL_NUSES (new_label
);
3174 --LABEL_NUSES (old_label
);
3182 replace_label_in_insn (rtx_insn
*insn
, rtx_insn
*old_label
,
3183 rtx_insn
*new_label
, bool update_label_nuses
)
3185 rtx insn_as_rtx
= insn
;
3186 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3187 gcc_checking_assert (insn_as_rtx
== insn
);
3190 /* Return true if X is referenced in BODY. */
3193 rtx_referenced_p (const_rtx x
, const_rtx body
)
3195 subrtx_iterator::array_type array
;
3196 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3197 if (const_rtx y
= *iter
)
3199 /* Check if a label_ref Y refers to label X. */
3200 if (GET_CODE (y
) == LABEL_REF
3202 && label_ref_label (y
) == x
)
3205 if (rtx_equal_p (x
, y
))
3208 /* If Y is a reference to pool constant traverse the constant. */
3209 if (GET_CODE (y
) == SYMBOL_REF
3210 && CONSTANT_POOL_ADDRESS_P (y
))
3211 iter
.substitute (get_pool_constant (y
));
3216 /* If INSN is a tablejump return true and store the label (before jump table) to
3217 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3220 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3221 rtx_jump_table_data
**tablep
)
3226 rtx target
= JUMP_LABEL (insn
);
3227 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3230 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3231 rtx_insn
*table
= next_insn (label
);
3232 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3238 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3242 /* For INSN known to satisfy tablejump_p, determine if it actually is a
3243 CASESI. Return the insn pattern if so, NULL_RTX otherwise. */
3246 tablejump_casesi_pattern (const rtx_insn
*insn
)
3250 if ((tmp
= single_set (insn
)) != NULL
3251 && SET_DEST (tmp
) == pc_rtx
3252 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
3253 && GET_CODE (XEXP (SET_SRC (tmp
), 2)) == LABEL_REF
)
3259 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3260 constant that is not in the constant pool and not in the condition
3261 of an IF_THEN_ELSE. */
3264 computed_jump_p_1 (const_rtx x
)
3266 const enum rtx_code code
= GET_CODE (x
);
3283 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3284 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3287 return (computed_jump_p_1 (XEXP (x
, 1))
3288 || computed_jump_p_1 (XEXP (x
, 2)));
3294 fmt
= GET_RTX_FORMAT (code
);
3295 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3298 && computed_jump_p_1 (XEXP (x
, i
)))
3301 else if (fmt
[i
] == 'E')
3302 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3303 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3310 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3312 Tablejumps and casesi insns are not considered indirect jumps;
3313 we can recognize them by a (use (label_ref)). */
3316 computed_jump_p (const rtx_insn
*insn
)
3321 rtx pat
= PATTERN (insn
);
3323 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3324 if (JUMP_LABEL (insn
) != NULL
)
3327 if (GET_CODE (pat
) == PARALLEL
)
3329 int len
= XVECLEN (pat
, 0);
3330 int has_use_labelref
= 0;
3332 for (i
= len
- 1; i
>= 0; i
--)
3333 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3334 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3337 has_use_labelref
= 1;
3341 if (! has_use_labelref
)
3342 for (i
= len
- 1; i
>= 0; i
--)
3343 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3344 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3345 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3348 else if (GET_CODE (pat
) == SET
3349 && SET_DEST (pat
) == pc_rtx
3350 && computed_jump_p_1 (SET_SRC (pat
)))
3358 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3359 the equivalent add insn and pass the result to FN, using DATA as the
3363 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3365 rtx x
= XEXP (mem
, 0);
3366 switch (GET_CODE (x
))
3371 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3372 rtx r1
= XEXP (x
, 0);
3373 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3374 return fn (mem
, x
, r1
, r1
, c
, data
);
3380 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3381 rtx r1
= XEXP (x
, 0);
3382 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3383 return fn (mem
, x
, r1
, r1
, c
, data
);
3389 rtx r1
= XEXP (x
, 0);
3390 rtx add
= XEXP (x
, 1);
3391 return fn (mem
, x
, r1
, add
, NULL
, data
);
3399 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3400 For each such autoinc operation found, call FN, passing it
3401 the innermost enclosing MEM, the operation itself, the RTX modified
3402 by the operation, two RTXs (the second may be NULL) that, once
3403 added, represent the value to be held by the modified RTX
3404 afterwards, and DATA. FN is to return 0 to continue the
3405 traversal or any other value to have it returned to the caller of
3406 for_each_inc_dec. */
3409 for_each_inc_dec (rtx x
,
3410 for_each_inc_dec_fn fn
,
3413 subrtx_var_iterator::array_type array
;
3414 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3419 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3421 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3424 iter
.skip_subrtxes ();
3431 /* Searches X for any reference to REGNO, returning the rtx of the
3432 reference found if any. Otherwise, returns NULL_RTX. */
3435 regno_use_in (unsigned int regno
, rtx x
)
3441 if (REG_P (x
) && REGNO (x
) == regno
)
3444 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3445 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3449 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3452 else if (fmt
[i
] == 'E')
3453 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3454 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3461 /* Return a value indicating whether OP, an operand of a commutative
3462 operation, is preferred as the first or second operand. The more
3463 positive the value, the stronger the preference for being the first
3467 commutative_operand_precedence (rtx op
)
3469 enum rtx_code code
= GET_CODE (op
);
3471 /* Constants always become the second operand. Prefer "nice" constants. */
3472 if (code
== CONST_INT
)
3474 if (code
== CONST_WIDE_INT
)
3476 if (code
== CONST_POLY_INT
)
3478 if (code
== CONST_DOUBLE
)
3480 if (code
== CONST_FIXED
)
3482 op
= avoid_constant_pool_reference (op
);
3483 code
= GET_CODE (op
);
3485 switch (GET_RTX_CLASS (code
))
3488 if (code
== CONST_INT
)
3490 if (code
== CONST_WIDE_INT
)
3492 if (code
== CONST_POLY_INT
)
3494 if (code
== CONST_DOUBLE
)
3496 if (code
== CONST_FIXED
)
3501 /* SUBREGs of objects should come second. */
3502 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3507 /* Complex expressions should be the first, so decrease priority
3508 of objects. Prefer pointer objects over non pointer objects. */
3509 if ((REG_P (op
) && REG_POINTER (op
))
3510 || (MEM_P (op
) && MEM_POINTER (op
)))
3514 case RTX_COMM_ARITH
:
3515 /* Prefer operands that are themselves commutative to be first.
3516 This helps to make things linear. In particular,
3517 (and (and (reg) (reg)) (not (reg))) is canonical. */
3521 /* If only one operand is a binary expression, it will be the first
3522 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3523 is canonical, although it will usually be further simplified. */
3527 /* Then prefer NEG and NOT. */
3528 if (code
== NEG
|| code
== NOT
)
3537 /* Return 1 iff it is necessary to swap operands of commutative operation
3538 in order to canonicalize expression. */
3541 swap_commutative_operands_p (rtx x
, rtx y
)
3543 return (commutative_operand_precedence (x
)
3544 < commutative_operand_precedence (y
));
3547 /* Return 1 if X is an autoincrement side effect and the register is
3548 not the stack pointer. */
3550 auto_inc_p (const_rtx x
)
3552 switch (GET_CODE (x
))
3560 /* There are no REG_INC notes for SP. */
3561 if (XEXP (x
, 0) != stack_pointer_rtx
)
3569 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3571 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3580 code
= GET_CODE (in
);
3581 fmt
= GET_RTX_FORMAT (code
);
3582 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3586 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3589 else if (fmt
[i
] == 'E')
3590 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3591 if (loc
== &XVECEXP (in
, i
, j
)
3592 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3598 /* Reinterpret a subreg as a bit extraction from an integer and return
3599 the position of the least significant bit of the extracted value.
3600 In other words, if the extraction were performed as a shift right
3601 and mask, return the number of bits to shift right.
3603 The outer value of the subreg has OUTER_BYTES bytes and starts at
3604 byte offset SUBREG_BYTE within an inner value of INNER_BYTES bytes. */
3607 subreg_size_lsb (poly_uint64 outer_bytes
,
3608 poly_uint64 inner_bytes
,
3609 poly_uint64 subreg_byte
)
3611 poly_uint64 subreg_end
, trailing_bytes
, byte_pos
;
3613 /* A paradoxical subreg begins at bit position 0. */
3614 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3615 if (maybe_gt (outer_bytes
, inner_bytes
))
3617 gcc_checking_assert (known_eq (subreg_byte
, 0U));
3621 subreg_end
= subreg_byte
+ outer_bytes
;
3622 trailing_bytes
= inner_bytes
- subreg_end
;
3623 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3624 byte_pos
= trailing_bytes
;
3625 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3626 byte_pos
= subreg_byte
;
3629 /* When bytes and words have opposite endianness, we must be able
3630 to split offsets into words and bytes at compile time. */
3631 poly_uint64 leading_word_part
3632 = force_align_down (subreg_byte
, UNITS_PER_WORD
);
3633 poly_uint64 trailing_word_part
3634 = force_align_down (trailing_bytes
, UNITS_PER_WORD
);
3635 /* If the subreg crosses a word boundary ensure that
3636 it also begins and ends on a word boundary. */
3637 gcc_assert (known_le (subreg_end
- leading_word_part
,
3638 (unsigned int) UNITS_PER_WORD
)
3639 || (known_eq (leading_word_part
, subreg_byte
)
3640 && known_eq (trailing_word_part
, trailing_bytes
)));
3641 if (WORDS_BIG_ENDIAN
)
3642 byte_pos
= trailing_word_part
+ (subreg_byte
- leading_word_part
);
3644 byte_pos
= leading_word_part
+ (trailing_bytes
- trailing_word_part
);
3647 return byte_pos
* BITS_PER_UNIT
;
3650 /* Given a subreg X, return the bit offset where the subreg begins
3651 (counting from the least significant bit of the reg). */
3654 subreg_lsb (const_rtx x
)
3656 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3660 /* Return the subreg byte offset for a subreg whose outer value has
3661 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3662 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3663 lsb of the inner value. This is the inverse of the calculation
3664 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3667 subreg_size_offset_from_lsb (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
,
3668 poly_uint64 lsb_shift
)
3670 /* A paradoxical subreg begins at bit position 0. */
3671 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3672 if (maybe_gt (outer_bytes
, inner_bytes
))
3674 gcc_checking_assert (known_eq (lsb_shift
, 0U));
3678 poly_uint64 lower_bytes
= exact_div (lsb_shift
, BITS_PER_UNIT
);
3679 poly_uint64 upper_bytes
= inner_bytes
- (lower_bytes
+ outer_bytes
);
3680 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3682 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3686 /* When bytes and words have opposite endianness, we must be able
3687 to split offsets into words and bytes at compile time. */
3688 poly_uint64 lower_word_part
= force_align_down (lower_bytes
,
3690 poly_uint64 upper_word_part
= force_align_down (upper_bytes
,
3692 if (WORDS_BIG_ENDIAN
)
3693 return upper_word_part
+ (lower_bytes
- lower_word_part
);
3695 return lower_word_part
+ (upper_bytes
- upper_word_part
);
3699 /* Fill in information about a subreg of a hard register.
3700 xregno - A regno of an inner hard subreg_reg (or what will become one).
3701 xmode - The mode of xregno.
3702 offset - The byte offset.
3703 ymode - The mode of a top level SUBREG (or what may become one).
3704 info - Pointer to structure to fill in.
3706 Rather than considering one particular inner register (and thus one
3707 particular "outer" register) in isolation, this function really uses
3708 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3709 function does not check whether adding INFO->offset to XREGNO gives
3710 a valid hard register; even if INFO->offset + XREGNO is out of range,
3711 there might be another register of the same type that is in range.
3712 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
3713 the new register, since that can depend on things like whether the final
3714 register number is even or odd. Callers that want to check whether
3715 this particular subreg can be replaced by a simple (reg ...) should
3716 use simplify_subreg_regno. */
3719 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3720 poly_uint64 offset
, machine_mode ymode
,
3721 struct subreg_info
*info
)
3723 unsigned int nregs_xmode
, nregs_ymode
;
3725 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3727 poly_uint64 xsize
= GET_MODE_SIZE (xmode
);
3728 poly_uint64 ysize
= GET_MODE_SIZE (ymode
);
3730 bool rknown
= false;
3732 /* If the register representation of a non-scalar mode has holes in it,
3733 we expect the scalar units to be concatenated together, with the holes
3734 distributed evenly among the scalar units. Each scalar unit must occupy
3735 at least one register. */
3736 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3738 /* As a consequence, we must be dealing with a constant number of
3739 scalars, and thus a constant offset and number of units. */
3740 HOST_WIDE_INT coffset
= offset
.to_constant ();
3741 HOST_WIDE_INT cysize
= ysize
.to_constant ();
3742 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3743 unsigned int nunits
= GET_MODE_NUNITS (xmode
).to_constant ();
3744 scalar_mode xmode_unit
= GET_MODE_INNER (xmode
);
3745 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3746 gcc_assert (nregs_xmode
3748 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3749 gcc_assert (hard_regno_nregs (xregno
, xmode
)
3750 == hard_regno_nregs (xregno
, xmode_unit
) * nunits
);
3752 /* You can only ask for a SUBREG of a value with holes in the middle
3753 if you don't cross the holes. (Such a SUBREG should be done by
3754 picking a different register class, or doing it in memory if
3755 necessary.) An example of a value with holes is XCmode on 32-bit
3756 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3757 3 for each part, but in memory it's two 128-bit parts.
3758 Padding is assumed to be at the end (not necessarily the 'high part')
3760 if ((coffset
/ GET_MODE_SIZE (xmode_unit
) + 1 < nunits
)
3761 && (coffset
/ GET_MODE_SIZE (xmode_unit
)
3762 != ((coffset
+ cysize
- 1) / GET_MODE_SIZE (xmode_unit
))))
3764 info
->representable_p
= false;
3769 nregs_xmode
= hard_regno_nregs (xregno
, xmode
);
3771 nregs_ymode
= hard_regno_nregs (xregno
, ymode
);
3773 /* Subreg sizes must be ordered, so that we can tell whether they are
3774 partial, paradoxical or complete. */
3775 gcc_checking_assert (ordered_p (xsize
, ysize
));
3777 /* Paradoxical subregs are otherwise valid. */
3778 if (!rknown
&& known_eq (offset
, 0U) && maybe_gt (ysize
, xsize
))
3780 info
->representable_p
= true;
3781 /* If this is a big endian paradoxical subreg, which uses more
3782 actual hard registers than the original register, we must
3783 return a negative offset so that we find the proper highpart
3786 We assume that the ordering of registers within a multi-register
3787 value has a consistent endianness: if bytes and register words
3788 have different endianness, the hard registers that make up a
3789 multi-register value must be at least word-sized. */
3790 if (REG_WORDS_BIG_ENDIAN
)
3791 info
->offset
= (int) nregs_xmode
- (int) nregs_ymode
;
3794 info
->nregs
= nregs_ymode
;
3798 /* If registers store different numbers of bits in the different
3799 modes, we cannot generally form this subreg. */
3800 poly_uint64 regsize_xmode
, regsize_ymode
;
3801 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3802 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3803 && multiple_p (xsize
, nregs_xmode
, ®size_xmode
)
3804 && multiple_p (ysize
, nregs_ymode
, ®size_ymode
))
3807 && ((nregs_ymode
> 1 && maybe_gt (regsize_xmode
, regsize_ymode
))
3808 || (nregs_xmode
> 1 && maybe_gt (regsize_ymode
, regsize_xmode
))))
3810 info
->representable_p
= false;
3811 if (!can_div_away_from_zero_p (ysize
, regsize_xmode
, &info
->nregs
)
3812 || !can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3813 /* Checked by validate_subreg. We must know at compile time
3814 which inner registers are being accessed. */
3818 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3819 would go outside of XMODE. */
3820 if (!rknown
&& maybe_gt (ysize
+ offset
, xsize
))
3822 info
->representable_p
= false;
3823 info
->nregs
= nregs_ymode
;
3824 if (!can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3825 /* Checked by validate_subreg. We must know at compile time
3826 which inner registers are being accessed. */
3830 /* Quick exit for the simple and common case of extracting whole
3831 subregisters from a multiregister value. */
3832 /* ??? It would be better to integrate this into the code below,
3833 if we can generalize the concept enough and figure out how
3834 odd-sized modes can coexist with the other weird cases we support. */
3835 HOST_WIDE_INT count
;
3837 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3838 && known_eq (regsize_xmode
, regsize_ymode
)
3839 && constant_multiple_p (offset
, regsize_ymode
, &count
))
3841 info
->representable_p
= true;
3842 info
->nregs
= nregs_ymode
;
3843 info
->offset
= count
;
3844 gcc_assert (info
->offset
+ info
->nregs
<= (int) nregs_xmode
);
3849 /* Lowpart subregs are otherwise valid. */
3850 if (!rknown
&& known_eq (offset
, subreg_lowpart_offset (ymode
, xmode
)))
3852 info
->representable_p
= true;
3855 if (known_eq (offset
, 0U) || nregs_xmode
== nregs_ymode
)
3858 info
->nregs
= nregs_ymode
;
3863 /* Set NUM_BLOCKS to the number of independently-representable YMODE
3864 values there are in (reg:XMODE XREGNO). We can view the register
3865 as consisting of this number of independent "blocks", where each
3866 block occupies NREGS_YMODE registers and contains exactly one
3867 representable YMODE value. */
3868 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3869 unsigned int num_blocks
= nregs_xmode
/ nregs_ymode
;
3871 /* Calculate the number of bytes in each block. This must always
3872 be exact, otherwise we don't know how to verify the constraint.
3873 These conditions may be relaxed but subreg_regno_offset would
3874 need to be redesigned. */
3875 poly_uint64 bytes_per_block
= exact_div (xsize
, num_blocks
);
3877 /* Get the number of the first block that contains the subreg and the byte
3878 offset of the subreg from the start of that block. */
3879 unsigned int block_number
;
3880 poly_uint64 subblock_offset
;
3881 if (!can_div_trunc_p (offset
, bytes_per_block
, &block_number
,
3883 /* Checked by validate_subreg. We must know at compile time which
3884 inner registers are being accessed. */
3889 /* Only the lowpart of each block is representable. */
3890 info
->representable_p
3891 = known_eq (subblock_offset
,
3892 subreg_size_lowpart_offset (ysize
, bytes_per_block
));
3896 /* We assume that the ordering of registers within a multi-register
3897 value has a consistent endianness: if bytes and register words
3898 have different endianness, the hard registers that make up a
3899 multi-register value must be at least word-sized. */
3900 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
)
3901 /* The block number we calculated above followed memory endianness.
3902 Convert it to register endianness by counting back from the end.
3903 (Note that, because of the assumption above, each block must be
3904 at least word-sized.) */
3905 info
->offset
= (num_blocks
- block_number
- 1) * nregs_ymode
;
3907 info
->offset
= block_number
* nregs_ymode
;
3908 info
->nregs
= nregs_ymode
;
3911 /* This function returns the regno offset of a subreg expression.
3912 xregno - A regno of an inner hard subreg_reg (or what will become one).
3913 xmode - The mode of xregno.
3914 offset - The byte offset.
3915 ymode - The mode of a top level SUBREG (or what may become one).
3916 RETURN - The regno offset which would be used. */
3918 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3919 poly_uint64 offset
, machine_mode ymode
)
3921 struct subreg_info info
;
3922 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3926 /* This function returns true when the offset is representable via
3927 subreg_offset in the given regno.
3928 xregno - A regno of an inner hard subreg_reg (or what will become one).
3929 xmode - The mode of xregno.
3930 offset - The byte offset.
3931 ymode - The mode of a top level SUBREG (or what may become one).
3932 RETURN - Whether the offset is representable. */
3934 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3935 poly_uint64 offset
, machine_mode ymode
)
3937 struct subreg_info info
;
3938 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3939 return info
.representable_p
;
3942 /* Return the number of a YMODE register to which
3944 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3946 can be simplified. Return -1 if the subreg can't be simplified.
3948 XREGNO is a hard register number. */
3951 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3952 poly_uint64 offset
, machine_mode ymode
)
3954 struct subreg_info info
;
3955 unsigned int yregno
;
3957 /* Give the backend a chance to disallow the mode change. */
3958 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3959 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3960 && !REG_CAN_CHANGE_MODE_P (xregno
, xmode
, ymode
))
3963 /* We shouldn't simplify stack-related registers. */
3964 if ((!reload_completed
|| frame_pointer_needed
)
3965 && xregno
== FRAME_POINTER_REGNUM
)
3968 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3969 && xregno
== ARG_POINTER_REGNUM
)
3972 if (xregno
== STACK_POINTER_REGNUM
3973 /* We should convert hard stack register in LRA if it is
3975 && ! lra_in_progress
)
3978 /* Try to get the register offset. */
3979 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3980 if (!info
.representable_p
)
3983 /* Make sure that the offsetted register value is in range. */
3984 yregno
= xregno
+ info
.offset
;
3985 if (!HARD_REGISTER_NUM_P (yregno
))
3988 /* See whether (reg:YMODE YREGNO) is valid.
3990 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3991 This is a kludge to work around how complex FP arguments are passed
3992 on IA-64 and should be fixed. See PR target/49226. */
3993 if (!targetm
.hard_regno_mode_ok (yregno
, ymode
)
3994 && targetm
.hard_regno_mode_ok (xregno
, xmode
))
3997 return (int) yregno
;
4000 /* Return the final regno that a subreg expression refers to. */
4002 subreg_regno (const_rtx x
)
4005 rtx subreg
= SUBREG_REG (x
);
4006 int regno
= REGNO (subreg
);
4008 ret
= regno
+ subreg_regno_offset (regno
,
4016 /* Return the number of registers that a subreg expression refers
4019 subreg_nregs (const_rtx x
)
4021 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
4024 /* Return the number of registers that a subreg REG with REGNO
4025 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
4026 changed so that the regno can be passed in. */
4029 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
4031 struct subreg_info info
;
4032 rtx subreg
= SUBREG_REG (x
);
4034 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
4039 struct parms_set_data
4045 /* Helper function for noticing stores to parameter registers. */
4047 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
4049 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
4050 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
4051 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
4053 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
4058 /* Look backward for first parameter to be loaded.
4059 Note that loads of all parameters will not necessarily be
4060 found if CSE has eliminated some of them (e.g., an argument
4061 to the outer function is passed down as a parameter).
4062 Do not skip BOUNDARY. */
4064 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
4066 struct parms_set_data parm
;
4068 rtx_insn
*before
, *first_set
;
4070 /* Since different machines initialize their parameter registers
4071 in different orders, assume nothing. Collect the set of all
4072 parameter registers. */
4073 CLEAR_HARD_REG_SET (parm
.regs
);
4075 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
4076 if (GET_CODE (XEXP (p
, 0)) == USE
4077 && REG_P (XEXP (XEXP (p
, 0), 0))
4078 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
4080 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
4082 /* We only care about registers which can hold function
4084 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
4087 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
4091 first_set
= call_insn
;
4093 /* Search backward for the first set of a register in this set. */
4094 while (parm
.nregs
&& before
!= boundary
)
4096 before
= PREV_INSN (before
);
4098 /* It is possible that some loads got CSEed from one call to
4099 another. Stop in that case. */
4100 if (CALL_P (before
))
4103 /* Our caller needs either ensure that we will find all sets
4104 (in case code has not been optimized yet), or take care
4105 for possible labels in a way by setting boundary to preceding
4107 if (LABEL_P (before
))
4109 gcc_assert (before
== boundary
);
4113 if (INSN_P (before
))
4115 int nregs_old
= parm
.nregs
;
4116 note_stores (before
, parms_set
, &parm
);
4117 /* If we found something that did not set a parameter reg,
4118 we're done. Do not keep going, as that might result
4119 in hoisting an insn before the setting of a pseudo
4120 that is used by the hoisted insn. */
4121 if (nregs_old
!= parm
.nregs
)
4130 /* Return true if we should avoid inserting code between INSN and preceding
4131 call instruction. */
4134 keep_with_call_p (const rtx_insn
*insn
)
4138 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
4140 if (REG_P (SET_DEST (set
))
4141 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
4142 && fixed_regs
[REGNO (SET_DEST (set
))]
4143 && general_operand (SET_SRC (set
), VOIDmode
))
4145 if (REG_P (SET_SRC (set
))
4146 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
4147 && REG_P (SET_DEST (set
))
4148 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
4150 /* There may be a stack pop just after the call and before the store
4151 of the return register. Search for the actual store when deciding
4152 if we can break or not. */
4153 if (SET_DEST (set
) == stack_pointer_rtx
)
4155 /* This CONST_CAST is okay because next_nonnote_insn just
4156 returns its argument and we assign it to a const_rtx
4159 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
4160 if (i2
&& keep_with_call_p (i2
))
4167 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4168 to non-complex jumps. That is, direct unconditional, conditional,
4169 and tablejumps, but not computed jumps or returns. It also does
4170 not apply to the fallthru case of a conditional jump. */
4173 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4175 rtx tmp
= JUMP_LABEL (jump_insn
);
4176 rtx_jump_table_data
*table
;
4181 if (tablejump_p (jump_insn
, NULL
, &table
))
4183 rtvec vec
= table
->get_labels ();
4184 int i
, veclen
= GET_NUM_ELEM (vec
);
4186 for (i
= 0; i
< veclen
; ++i
)
4187 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4191 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4198 /* Return an estimate of the cost of computing rtx X.
4199 One use is in cse, to decide which expression to keep in the hash table.
4200 Another is in rtl generation, to pick the cheapest way to multiply.
4201 Other uses like the latter are expected in the future.
4203 X appears as operand OPNO in an expression with code OUTER_CODE.
4204 SPEED specifies whether costs optimized for speed or size should
4208 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4209 int opno
, bool speed
)
4221 if (GET_CODE (x
) == SET
)
4222 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4223 the mode for the factor. */
4224 mode
= GET_MODE (SET_DEST (x
));
4225 else if (GET_MODE (x
) != VOIDmode
)
4226 mode
= GET_MODE (x
);
4228 mode_size
= estimated_poly_value (GET_MODE_SIZE (mode
));
4230 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4231 many insns, taking N times as long. */
4232 factor
= mode_size
> UNITS_PER_WORD
? mode_size
/ UNITS_PER_WORD
: 1;
4234 /* Compute the default costs of certain things.
4235 Note that targetm.rtx_costs can override the defaults. */
4237 code
= GET_CODE (x
);
4241 /* Multiplication has time-complexity O(N*N), where N is the
4242 number of units (translated from digits) when using
4243 schoolbook long multiplication. */
4244 total
= factor
* factor
* COSTS_N_INSNS (5);
4250 /* Similarly, complexity for schoolbook long division. */
4251 total
= factor
* factor
* COSTS_N_INSNS (7);
4254 /* Used in combine.c as a marker. */
4258 total
= factor
* COSTS_N_INSNS (1);
4268 /* If we can't tie these modes, make this expensive. The larger
4269 the mode, the more expensive it is. */
4270 if (!targetm
.modes_tieable_p (mode
, GET_MODE (SUBREG_REG (x
))))
4271 return COSTS_N_INSNS (2 + factor
);
4275 if (targetm
.modes_tieable_p (mode
, GET_MODE (XEXP (x
, 0))))
4282 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4287 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4288 which is already in total. */
4290 fmt
= GET_RTX_FORMAT (code
);
4291 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4293 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4294 else if (fmt
[i
] == 'E')
4295 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4296 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4301 /* Fill in the structure C with information about both speed and size rtx
4302 costs for X, which is operand OPNO in an expression with code OUTER. */
4305 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4306 struct full_rtx_costs
*c
)
4308 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4309 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4313 /* Return cost of address expression X.
4314 Expect that X is properly formed address reference.
4316 SPEED parameter specify whether costs optimized for speed or size should
4320 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4322 /* We may be asked for cost of various unusual addresses, such as operands
4323 of push instruction. It is not worthwhile to complicate writing
4324 of the target hook by such cases. */
4326 if (!memory_address_addr_space_p (mode
, x
, as
))
4329 return targetm
.address_cost (x
, mode
, as
, speed
);
4332 /* If the target doesn't override, compute the cost as with arithmetic. */
4335 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4337 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4341 unsigned HOST_WIDE_INT
4342 nonzero_bits (const_rtx x
, machine_mode mode
)
4344 if (mode
== VOIDmode
)
4345 mode
= GET_MODE (x
);
4346 scalar_int_mode int_mode
;
4347 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4348 return GET_MODE_MASK (mode
);
4349 return cached_nonzero_bits (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4353 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4355 if (mode
== VOIDmode
)
4356 mode
= GET_MODE (x
);
4357 scalar_int_mode int_mode
;
4358 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4360 return cached_num_sign_bit_copies (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4363 /* Return true if nonzero_bits1 might recurse into both operands
4367 nonzero_bits_binary_arith_p (const_rtx x
)
4369 if (!ARITHMETIC_P (x
))
4371 switch (GET_CODE (x
))
4393 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4394 It avoids exponential behavior in nonzero_bits1 when X has
4395 identical subexpressions on the first or the second level. */
4397 static unsigned HOST_WIDE_INT
4398 cached_nonzero_bits (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4399 machine_mode known_mode
,
4400 unsigned HOST_WIDE_INT known_ret
)
4402 if (x
== known_x
&& mode
== known_mode
)
4405 /* Try to find identical subexpressions. If found call
4406 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4407 precomputed value for the subexpression as KNOWN_RET. */
4409 if (nonzero_bits_binary_arith_p (x
))
4411 rtx x0
= XEXP (x
, 0);
4412 rtx x1
= XEXP (x
, 1);
4414 /* Check the first level. */
4416 return nonzero_bits1 (x
, mode
, x0
, mode
,
4417 cached_nonzero_bits (x0
, mode
, known_x
,
4418 known_mode
, known_ret
));
4420 /* Check the second level. */
4421 if (nonzero_bits_binary_arith_p (x0
)
4422 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4423 return nonzero_bits1 (x
, mode
, x1
, mode
,
4424 cached_nonzero_bits (x1
, mode
, known_x
,
4425 known_mode
, known_ret
));
4427 if (nonzero_bits_binary_arith_p (x1
)
4428 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4429 return nonzero_bits1 (x
, mode
, x0
, mode
,
4430 cached_nonzero_bits (x0
, mode
, known_x
,
4431 known_mode
, known_ret
));
4434 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4437 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4438 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4439 is less useful. We can't allow both, because that results in exponential
4440 run time recursion. There is a nullstone testcase that triggered
4441 this. This macro avoids accidental uses of num_sign_bit_copies. */
4442 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4444 /* Given an expression, X, compute which bits in X can be nonzero.
4445 We don't care about bits outside of those defined in MODE.
4447 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4448 an arithmetic operation, we can do better. */
4450 static unsigned HOST_WIDE_INT
4451 nonzero_bits1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4452 machine_mode known_mode
,
4453 unsigned HOST_WIDE_INT known_ret
)
4455 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4456 unsigned HOST_WIDE_INT inner_nz
;
4457 enum rtx_code code
= GET_CODE (x
);
4458 machine_mode inner_mode
;
4459 unsigned int inner_width
;
4460 scalar_int_mode xmode
;
4462 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4464 if (CONST_INT_P (x
))
4466 if (SHORT_IMMEDIATES_SIGN_EXTEND
4468 && mode_width
< BITS_PER_WORD
4469 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1))) != 0)
4470 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4475 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
4477 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
4479 /* If X is wider than MODE, use its mode instead. */
4480 if (xmode_width
> mode_width
)
4483 nonzero
= GET_MODE_MASK (mode
);
4484 mode_width
= xmode_width
;
4487 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4488 /* Our only callers in this case look for single bit values. So
4489 just return the mode mask. Those tests will then be false. */
4492 /* If MODE is wider than X, but both are a single word for both the host
4493 and target machines, we can compute this from which bits of the object
4494 might be nonzero in its own mode, taking into account the fact that, on
4495 CISC machines, accessing an object in a wider mode generally causes the
4496 high-order bits to become undefined, so they are not known to be zero.
4497 We extend this reasoning to RISC machines for operations that might not
4498 operate on the full registers. */
4499 if (mode_width
> xmode_width
4500 && xmode_width
<= BITS_PER_WORD
4501 && xmode_width
<= HOST_BITS_PER_WIDE_INT
4502 && !(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
4504 nonzero
&= cached_nonzero_bits (x
, xmode
,
4505 known_x
, known_mode
, known_ret
);
4506 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
);
4510 /* Please keep nonzero_bits_binary_arith_p above in sync with
4511 the code in the switch below. */
4515 #if defined(POINTERS_EXTEND_UNSIGNED)
4516 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4517 all the bits above ptr_mode are known to be zero. */
4518 /* As we do not know which address space the pointer is referring to,
4519 we can do this only if the target does not support different pointer
4520 or address modes depending on the address space. */
4521 if (target_default_pointer_address_modes_p ()
4522 && POINTERS_EXTEND_UNSIGNED
4525 && !targetm
.have_ptr_extend ())
4526 nonzero
&= GET_MODE_MASK (ptr_mode
);
4529 /* Include declared information about alignment of pointers. */
4530 /* ??? We don't properly preserve REG_POINTER changes across
4531 pointer-to-integer casts, so we can't trust it except for
4532 things that we know must be pointers. See execute/960116-1.c. */
4533 if ((x
== stack_pointer_rtx
4534 || x
== frame_pointer_rtx
4535 || x
== arg_pointer_rtx
)
4536 && REGNO_POINTER_ALIGN (REGNO (x
)))
4538 unsigned HOST_WIDE_INT alignment
4539 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4541 #ifdef PUSH_ROUNDING
4542 /* If PUSH_ROUNDING is defined, it is possible for the
4543 stack to be momentarily aligned only to that amount,
4544 so we pick the least alignment. */
4545 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4547 poly_uint64 rounded_1
= PUSH_ROUNDING (poly_int64 (1));
4548 alignment
= MIN (known_alignment (rounded_1
), alignment
);
4552 nonzero
&= ~(alignment
- 1);
4556 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4557 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, xmode
, mode
,
4561 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4562 known_mode
, known_ret
);
4564 return nonzero_for_hook
;
4568 /* In many, if not most, RISC machines, reading a byte from memory
4569 zeros the rest of the register. Noticing that fact saves a lot
4570 of extra zero-extends. */
4571 if (load_extend_op (xmode
) == ZERO_EXTEND
)
4572 nonzero
&= GET_MODE_MASK (xmode
);
4576 case UNEQ
: case LTGT
:
4577 case GT
: case GTU
: case UNGT
:
4578 case LT
: case LTU
: case UNLT
:
4579 case GE
: case GEU
: case UNGE
:
4580 case LE
: case LEU
: case UNLE
:
4581 case UNORDERED
: case ORDERED
:
4582 /* If this produces an integer result, we know which bits are set.
4583 Code here used to clear bits outside the mode of X, but that is
4585 /* Mind that MODE is the mode the caller wants to look at this
4586 operation in, and not the actual operation mode. We can wind
4587 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4588 that describes the results of a vector compare. */
4589 if (GET_MODE_CLASS (xmode
) == MODE_INT
4590 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4591 nonzero
= STORE_FLAG_VALUE
;
4596 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4597 and num_sign_bit_copies. */
4598 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4602 if (xmode_width
< mode_width
)
4603 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
));
4608 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4609 and num_sign_bit_copies. */
4610 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4616 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4617 known_x
, known_mode
, known_ret
)
4618 & GET_MODE_MASK (mode
));
4622 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4623 known_x
, known_mode
, known_ret
);
4624 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4625 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4629 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4630 Otherwise, show all the bits in the outer mode but not the inner
4632 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4633 known_x
, known_mode
, known_ret
);
4634 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4636 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4637 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4638 inner_nz
|= (GET_MODE_MASK (mode
)
4639 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4642 nonzero
&= inner_nz
;
4646 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4647 known_x
, known_mode
, known_ret
)
4648 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4649 known_x
, known_mode
, known_ret
);
4653 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4655 unsigned HOST_WIDE_INT nonzero0
4656 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4657 known_x
, known_mode
, known_ret
);
4659 /* Don't call nonzero_bits for the second time if it cannot change
4661 if ((nonzero
& nonzero0
) != nonzero
)
4663 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4664 known_x
, known_mode
, known_ret
);
4668 case PLUS
: case MINUS
:
4670 case DIV
: case UDIV
:
4671 case MOD
: case UMOD
:
4672 /* We can apply the rules of arithmetic to compute the number of
4673 high- and low-order zero bits of these operations. We start by
4674 computing the width (position of the highest-order nonzero bit)
4675 and the number of low-order zero bits for each value. */
4677 unsigned HOST_WIDE_INT nz0
4678 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4679 known_x
, known_mode
, known_ret
);
4680 unsigned HOST_WIDE_INT nz1
4681 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4682 known_x
, known_mode
, known_ret
);
4683 int sign_index
= xmode_width
- 1;
4684 int width0
= floor_log2 (nz0
) + 1;
4685 int width1
= floor_log2 (nz1
) + 1;
4686 int low0
= ctz_or_zero (nz0
);
4687 int low1
= ctz_or_zero (nz1
);
4688 unsigned HOST_WIDE_INT op0_maybe_minusp
4689 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4690 unsigned HOST_WIDE_INT op1_maybe_minusp
4691 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4692 unsigned int result_width
= mode_width
;
4698 result_width
= MAX (width0
, width1
) + 1;
4699 result_low
= MIN (low0
, low1
);
4702 result_low
= MIN (low0
, low1
);
4705 result_width
= width0
+ width1
;
4706 result_low
= low0
+ low1
;
4711 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4712 result_width
= width0
;
4717 result_width
= width0
;
4722 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4723 result_width
= MIN (width0
, width1
);
4724 result_low
= MIN (low0
, low1
);
4729 result_width
= MIN (width0
, width1
);
4730 result_low
= MIN (low0
, low1
);
4736 if (result_width
< mode_width
)
4737 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4740 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4745 if (CONST_INT_P (XEXP (x
, 1))
4746 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4747 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4751 /* If this is a SUBREG formed for a promoted variable that has
4752 been zero-extended, we know that at least the high-order bits
4753 are zero, though others might be too. */
4754 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4755 nonzero
= GET_MODE_MASK (xmode
)
4756 & cached_nonzero_bits (SUBREG_REG (x
), xmode
,
4757 known_x
, known_mode
, known_ret
);
4759 /* If the inner mode is a single word for both the host and target
4760 machines, we can compute this from which bits of the inner
4761 object might be nonzero. */
4762 inner_mode
= GET_MODE (SUBREG_REG (x
));
4763 if (GET_MODE_PRECISION (inner_mode
).is_constant (&inner_width
)
4764 && inner_width
<= BITS_PER_WORD
4765 && inner_width
<= HOST_BITS_PER_WIDE_INT
)
4767 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4768 known_x
, known_mode
, known_ret
);
4770 /* On a typical CISC machine, accessing an object in a wider mode
4771 causes the high-order bits to become undefined. So they are
4772 not known to be zero.
4774 On a typical RISC machine, we only have to worry about the way
4775 loads are extended. Otherwise, if we get a reload for the inner
4776 part, it may be loaded from the stack, and then we may lose all
4777 the zero bits that existed before the store to the stack. */
4779 if ((!WORD_REGISTER_OPERATIONS
4780 || ((extend_op
= load_extend_op (inner_mode
)) == SIGN_EXTEND
4781 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4782 : extend_op
!= ZERO_EXTEND
)
4783 || !MEM_P (SUBREG_REG (x
)))
4784 && xmode_width
> inner_width
)
4786 |= (GET_MODE_MASK (GET_MODE (x
)) & ~GET_MODE_MASK (inner_mode
));
4795 /* The nonzero bits are in two classes: any bits within MODE
4796 that aren't in xmode are always significant. The rest of the
4797 nonzero bits are those that are significant in the operand of
4798 the shift when shifted the appropriate number of bits. This
4799 shows that high-order bits are cleared by the right shift and
4800 low-order bits by left shifts. */
4801 if (CONST_INT_P (XEXP (x
, 1))
4802 && INTVAL (XEXP (x
, 1)) >= 0
4803 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4804 && INTVAL (XEXP (x
, 1)) < xmode_width
)
4806 int count
= INTVAL (XEXP (x
, 1));
4807 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (xmode
);
4808 unsigned HOST_WIDE_INT op_nonzero
4809 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4810 known_x
, known_mode
, known_ret
);
4811 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4812 unsigned HOST_WIDE_INT outer
= 0;
4814 if (mode_width
> xmode_width
)
4815 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4830 /* If the sign bit may have been nonzero before the shift, we
4831 need to mark all the places it could have been copied to
4832 by the shift as possibly nonzero. */
4833 if (inner
& (HOST_WIDE_INT_1U
<< (xmode_width
- 1 - count
)))
4834 inner
|= (((HOST_WIDE_INT_1U
<< count
) - 1)
4835 << (xmode_width
- count
));
4839 inner
= (inner
<< (count
% xmode_width
)
4840 | (inner
>> (xmode_width
- (count
% xmode_width
))))
4845 inner
= (inner
>> (count
% xmode_width
)
4846 | (inner
<< (xmode_width
- (count
% xmode_width
))))
4854 nonzero
&= (outer
| inner
);
4860 /* This is at most the number of bits in the mode. */
4861 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4865 /* If CLZ has a known value at zero, then the nonzero bits are
4866 that value, plus the number of bits in the mode minus one. */
4867 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4869 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4875 /* If CTZ has a known value at zero, then the nonzero bits are
4876 that value, plus the number of bits in the mode minus one. */
4877 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4879 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4885 /* This is at most the number of bits in the mode minus 1. */
4886 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4895 unsigned HOST_WIDE_INT nonzero_true
4896 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4897 known_x
, known_mode
, known_ret
);
4899 /* Don't call nonzero_bits for the second time if it cannot change
4901 if ((nonzero
& nonzero_true
) != nonzero
)
4902 nonzero
&= nonzero_true
4903 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4904 known_x
, known_mode
, known_ret
);
4915 /* See the macro definition above. */
4916 #undef cached_num_sign_bit_copies
4919 /* Return true if num_sign_bit_copies1 might recurse into both operands
4923 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4925 if (!ARITHMETIC_P (x
))
4927 switch (GET_CODE (x
))
4945 /* The function cached_num_sign_bit_copies is a wrapper around
4946 num_sign_bit_copies1. It avoids exponential behavior in
4947 num_sign_bit_copies1 when X has identical subexpressions on the
4948 first or the second level. */
4951 cached_num_sign_bit_copies (const_rtx x
, scalar_int_mode mode
,
4952 const_rtx known_x
, machine_mode known_mode
,
4953 unsigned int known_ret
)
4955 if (x
== known_x
&& mode
== known_mode
)
4958 /* Try to find identical subexpressions. If found call
4959 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4960 the precomputed value for the subexpression as KNOWN_RET. */
4962 if (num_sign_bit_copies_binary_arith_p (x
))
4964 rtx x0
= XEXP (x
, 0);
4965 rtx x1
= XEXP (x
, 1);
4967 /* Check the first level. */
4970 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4971 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4975 /* Check the second level. */
4976 if (num_sign_bit_copies_binary_arith_p (x0
)
4977 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4979 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4980 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4984 if (num_sign_bit_copies_binary_arith_p (x1
)
4985 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4987 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4988 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4993 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4996 /* Return the number of bits at the high-order end of X that are known to
4997 be equal to the sign bit. X will be used in mode MODE. The returned
4998 value will always be between 1 and the number of bits in MODE. */
5001 num_sign_bit_copies1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
5002 machine_mode known_mode
,
5003 unsigned int known_ret
)
5005 enum rtx_code code
= GET_CODE (x
);
5006 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
5007 int num0
, num1
, result
;
5008 unsigned HOST_WIDE_INT nonzero
;
5010 if (CONST_INT_P (x
))
5012 /* If the constant is negative, take its 1's complement and remask.
5013 Then see how many zero bits we have. */
5014 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
5015 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5016 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5017 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5019 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5022 scalar_int_mode xmode
, inner_mode
;
5023 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
5026 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
5028 /* For a smaller mode, just ignore the high bits. */
5029 if (bitwidth
< xmode_width
)
5031 num0
= cached_num_sign_bit_copies (x
, xmode
,
5032 known_x
, known_mode
, known_ret
);
5033 return MAX (1, num0
- (int) (xmode_width
- bitwidth
));
5036 if (bitwidth
> xmode_width
)
5038 /* If this machine does not do all register operations on the entire
5039 register and MODE is wider than the mode of X, we can say nothing
5040 at all about the high-order bits. We extend this reasoning to RISC
5041 machines for operations that might not operate on full registers. */
5042 if (!(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
5045 /* Likewise on machines that do, if the mode of the object is smaller
5046 than a word and loads of that size don't sign extend, we can say
5047 nothing about the high order bits. */
5048 if (xmode_width
< BITS_PER_WORD
5049 && load_extend_op (xmode
) != SIGN_EXTEND
)
5053 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
5054 the code in the switch below. */
5059 #if defined(POINTERS_EXTEND_UNSIGNED)
5060 /* If pointers extend signed and this is a pointer in Pmode, say that
5061 all the bits above ptr_mode are known to be sign bit copies. */
5062 /* As we do not know which address space the pointer is referring to,
5063 we can do this only if the target does not support different pointer
5064 or address modes depending on the address space. */
5065 if (target_default_pointer_address_modes_p ()
5066 && ! POINTERS_EXTEND_UNSIGNED
&& xmode
== Pmode
5067 && mode
== Pmode
&& REG_POINTER (x
)
5068 && !targetm
.have_ptr_extend ())
5069 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
5073 unsigned int copies_for_hook
= 1, copies
= 1;
5074 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, xmode
, mode
,
5078 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
5079 known_mode
, known_ret
);
5081 if (copies
> 1 || copies_for_hook
> 1)
5082 return MAX (copies
, copies_for_hook
);
5084 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
5089 /* Some RISC machines sign-extend all loads of smaller than a word. */
5090 if (load_extend_op (xmode
) == SIGN_EXTEND
)
5091 return MAX (1, ((int) bitwidth
- (int) xmode_width
+ 1));
5095 /* If this is a SUBREG for a promoted object that is sign-extended
5096 and we are looking at it in a wider mode, we know that at least the
5097 high-order bits are known to be sign bit copies. */
5099 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
5101 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5102 known_x
, known_mode
, known_ret
);
5103 return MAX ((int) bitwidth
- (int) xmode_width
+ 1, num0
);
5106 if (is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (x
)), &inner_mode
))
5108 /* For a smaller object, just ignore the high bits. */
5109 if (bitwidth
<= GET_MODE_PRECISION (inner_mode
))
5111 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), inner_mode
,
5112 known_x
, known_mode
,
5114 return MAX (1, num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5118 /* For paradoxical SUBREGs on machines where all register operations
5119 affect the entire register, just look inside. Note that we are
5120 passing MODE to the recursive call, so the number of sign bit
5121 copies will remain relative to that mode, not the inner mode.
5123 This works only if loads sign extend. Otherwise, if we get a
5124 reload for the inner part, it may be loaded from the stack, and
5125 then we lose all sign bit copies that existed before the store
5127 if (WORD_REGISTER_OPERATIONS
5128 && load_extend_op (inner_mode
) == SIGN_EXTEND
5129 && paradoxical_subreg_p (x
)
5130 && MEM_P (SUBREG_REG (x
)))
5131 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5132 known_x
, known_mode
, known_ret
);
5137 if (CONST_INT_P (XEXP (x
, 1)))
5138 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
5142 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
5143 return (bitwidth
- GET_MODE_PRECISION (inner_mode
)
5144 + cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5145 known_x
, known_mode
, known_ret
));
5149 /* For a smaller object, just ignore the high bits. */
5150 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
5151 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5152 known_x
, known_mode
, known_ret
);
5153 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5157 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5158 known_x
, known_mode
, known_ret
);
5160 case ROTATE
: case ROTATERT
:
5161 /* If we are rotating left by a number of bits less than the number
5162 of sign bit copies, we can just subtract that amount from the
5164 if (CONST_INT_P (XEXP (x
, 1))
5165 && INTVAL (XEXP (x
, 1)) >= 0
5166 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
5168 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5169 known_x
, known_mode
, known_ret
);
5170 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
5171 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
5176 /* In general, this subtracts one sign bit copy. But if the value
5177 is known to be positive, the number of sign bit copies is the
5178 same as that of the input. Finally, if the input has just one bit
5179 that might be nonzero, all the bits are copies of the sign bit. */
5180 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5181 known_x
, known_mode
, known_ret
);
5182 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5183 return num0
> 1 ? num0
- 1 : 1;
5185 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5190 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
5195 case IOR
: case AND
: case XOR
:
5196 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5197 /* Logical operations will preserve the number of sign-bit copies.
5198 MIN and MAX operations always return one of the operands. */
5199 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5200 known_x
, known_mode
, known_ret
);
5201 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5202 known_x
, known_mode
, known_ret
);
5204 /* If num1 is clearing some of the top bits then regardless of
5205 the other term, we are guaranteed to have at least that many
5206 high-order zero bits. */
5209 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5210 && CONST_INT_P (XEXP (x
, 1))
5211 && (UINTVAL (XEXP (x
, 1))
5212 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5215 /* Similarly for IOR when setting high-order bits. */
5218 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5219 && CONST_INT_P (XEXP (x
, 1))
5220 && (UINTVAL (XEXP (x
, 1))
5221 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5224 return MIN (num0
, num1
);
5226 case PLUS
: case MINUS
:
5227 /* For addition and subtraction, we can have a 1-bit carry. However,
5228 if we are subtracting 1 from a positive number, there will not
5229 be such a carry. Furthermore, if the positive number is known to
5230 be 0 or 1, we know the result is either -1 or 0. */
5232 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5233 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5235 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5236 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5237 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5238 : bitwidth
- floor_log2 (nonzero
) - 1);
5241 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5242 known_x
, known_mode
, known_ret
);
5243 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5244 known_x
, known_mode
, known_ret
);
5245 result
= MAX (1, MIN (num0
, num1
) - 1);
5250 /* The number of bits of the product is the sum of the number of
5251 bits of both terms. However, unless one of the terms if known
5252 to be positive, we must allow for an additional bit since negating
5253 a negative number can remove one sign bit copy. */
5255 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5256 known_x
, known_mode
, known_ret
);
5257 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5258 known_x
, known_mode
, known_ret
);
5260 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5262 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5263 || (((nonzero_bits (XEXP (x
, 0), mode
)
5264 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5265 && ((nonzero_bits (XEXP (x
, 1), mode
)
5266 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5270 return MAX (1, result
);
5273 /* The result must be <= the first operand. If the first operand
5274 has the high bit set, we know nothing about the number of sign
5276 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5278 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5279 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5282 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5283 known_x
, known_mode
, known_ret
);
5286 /* The result must be <= the second operand. If the second operand
5287 has (or just might have) the high bit set, we know nothing about
5288 the number of sign bit copies. */
5289 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5291 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5292 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5295 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5296 known_x
, known_mode
, known_ret
);
5299 /* Similar to unsigned division, except that we have to worry about
5300 the case where the divisor is negative, in which case we have
5302 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5303 known_x
, known_mode
, known_ret
);
5305 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5306 || (nonzero_bits (XEXP (x
, 1), mode
)
5307 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5313 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5314 known_x
, known_mode
, known_ret
);
5316 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5317 || (nonzero_bits (XEXP (x
, 1), mode
)
5318 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5324 /* Shifts by a constant add to the number of bits equal to the
5326 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5327 known_x
, known_mode
, known_ret
);
5328 if (CONST_INT_P (XEXP (x
, 1))
5329 && INTVAL (XEXP (x
, 1)) > 0
5330 && INTVAL (XEXP (x
, 1)) < xmode_width
)
5331 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5336 /* Left shifts destroy copies. */
5337 if (!CONST_INT_P (XEXP (x
, 1))
5338 || INTVAL (XEXP (x
, 1)) < 0
5339 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5340 || INTVAL (XEXP (x
, 1)) >= xmode_width
)
5343 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5344 known_x
, known_mode
, known_ret
);
5345 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5348 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5349 known_x
, known_mode
, known_ret
);
5350 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5351 known_x
, known_mode
, known_ret
);
5352 return MIN (num0
, num1
);
5354 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5355 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5356 case GEU
: case GTU
: case LEU
: case LTU
:
5357 case UNORDERED
: case ORDERED
:
5358 /* If the constant is negative, take its 1's complement and remask.
5359 Then see how many zero bits we have. */
5360 nonzero
= STORE_FLAG_VALUE
;
5361 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5362 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5363 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5365 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5371 /* If we haven't been able to figure it out by one of the above rules,
5372 see if some of the high-order bits are known to be zero. If so,
5373 count those bits and return one less than that amount. If we can't
5374 safely compute the mask for this mode, always return BITWIDTH. */
5376 bitwidth
= GET_MODE_PRECISION (mode
);
5377 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5380 nonzero
= nonzero_bits (x
, mode
);
5381 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5382 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5385 /* Calculate the rtx_cost of a single instruction pattern. A return value of
5386 zero indicates an instruction pattern without a known cost. */
5389 pattern_cost (rtx pat
, bool speed
)
5394 /* Extract the single set rtx from the instruction pattern. We
5395 can't use single_set since we only have the pattern. We also
5396 consider PARALLELs of a normal set and a single comparison. In
5397 that case we use the cost of the non-comparison SET operation,
5398 which is most-likely to be the real cost of this operation. */
5399 if (GET_CODE (pat
) == SET
)
5401 else if (GET_CODE (pat
) == PARALLEL
)
5404 rtx comparison
= NULL_RTX
;
5406 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5408 rtx x
= XVECEXP (pat
, 0, i
);
5409 if (GET_CODE (x
) == SET
)
5411 if (GET_CODE (SET_SRC (x
)) == COMPARE
)
5426 if (!set
&& comparison
)
5435 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5436 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5439 /* Calculate the cost of a single instruction. A return value of zero
5440 indicates an instruction pattern without a known cost. */
5443 insn_cost (rtx_insn
*insn
, bool speed
)
5445 if (targetm
.insn_cost
)
5446 return targetm
.insn_cost (insn
, speed
);
5448 return pattern_cost (PATTERN (insn
), speed
);
5451 /* Returns estimate on cost of computing SEQ. */
5454 seq_cost (const rtx_insn
*seq
, bool speed
)
5459 for (; seq
; seq
= NEXT_INSN (seq
))
5461 set
= single_set (seq
);
5463 cost
+= set_rtx_cost (set
, speed
);
5464 else if (NONDEBUG_INSN_P (seq
))
5466 int this_cost
= insn_cost (CONST_CAST_RTX_INSN (seq
), speed
);
5477 /* Given an insn INSN and condition COND, return the condition in a
5478 canonical form to simplify testing by callers. Specifically:
5480 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5481 (2) Both operands will be machine operands; (cc0) will have been replaced.
5482 (3) If an operand is a constant, it will be the second operand.
5483 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5484 for GE, GEU, and LEU.
5486 If the condition cannot be understood, or is an inequality floating-point
5487 comparison which needs to be reversed, 0 will be returned.
5489 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5491 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5492 insn used in locating the condition was found. If a replacement test
5493 of the condition is desired, it should be placed in front of that
5494 insn and we will be sure that the inputs are still valid.
5496 If WANT_REG is nonzero, we wish the condition to be relative to that
5497 register, if possible. Therefore, do not canonicalize the condition
5498 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5499 to be a compare to a CC mode register.
5501 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5505 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5506 rtx_insn
**earliest
,
5507 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5510 rtx_insn
*prev
= insn
;
5514 int reverse_code
= 0;
5516 basic_block bb
= BLOCK_FOR_INSN (insn
);
5518 code
= GET_CODE (cond
);
5519 mode
= GET_MODE (cond
);
5520 op0
= XEXP (cond
, 0);
5521 op1
= XEXP (cond
, 1);
5524 code
= reversed_comparison_code (cond
, insn
);
5525 if (code
== UNKNOWN
)
5531 /* If we are comparing a register with zero, see if the register is set
5532 in the previous insn to a COMPARE or a comparison operation. Perform
5533 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5536 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5537 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5538 && op1
== CONST0_RTX (GET_MODE (op0
))
5541 /* Set nonzero when we find something of interest. */
5544 /* If comparison with cc0, import actual comparison from compare
5548 if ((prev
= prev_nonnote_insn (prev
)) == 0
5549 || !NONJUMP_INSN_P (prev
)
5550 || (set
= single_set (prev
)) == 0
5551 || SET_DEST (set
) != cc0_rtx
)
5554 op0
= SET_SRC (set
);
5555 op1
= CONST0_RTX (GET_MODE (op0
));
5560 /* If this is a COMPARE, pick up the two things being compared. */
5561 if (GET_CODE (op0
) == COMPARE
)
5563 op1
= XEXP (op0
, 1);
5564 op0
= XEXP (op0
, 0);
5567 else if (!REG_P (op0
))
5570 /* Go back to the previous insn. Stop if it is not an INSN. We also
5571 stop if it isn't a single set or if it has a REG_INC note because
5572 we don't want to bother dealing with it. */
5574 prev
= prev_nonnote_nondebug_insn (prev
);
5577 || !NONJUMP_INSN_P (prev
)
5578 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5579 /* In cfglayout mode, there do not have to be labels at the
5580 beginning of a block, or jumps at the end, so the previous
5581 conditions would not stop us when we reach bb boundary. */
5582 || BLOCK_FOR_INSN (prev
) != bb
)
5585 set
= set_of (op0
, prev
);
5588 && (GET_CODE (set
) != SET
5589 || !rtx_equal_p (SET_DEST (set
), op0
)))
5592 /* If this is setting OP0, get what it sets it to if it looks
5596 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5597 #ifdef FLOAT_STORE_FLAG_VALUE
5598 REAL_VALUE_TYPE fsfv
;
5601 /* ??? We may not combine comparisons done in a CCmode with
5602 comparisons not done in a CCmode. This is to aid targets
5603 like Alpha that have an IEEE compliant EQ instruction, and
5604 a non-IEEE compliant BEQ instruction. The use of CCmode is
5605 actually artificial, simply to prevent the combination, but
5606 should not affect other platforms.
5608 However, we must allow VOIDmode comparisons to match either
5609 CCmode or non-CCmode comparison, because some ports have
5610 modeless comparisons inside branch patterns.
5612 ??? This mode check should perhaps look more like the mode check
5613 in simplify_comparison in combine. */
5614 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5615 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5617 && inner_mode
!= VOIDmode
)
5619 if (GET_CODE (SET_SRC (set
)) == COMPARE
5622 && val_signbit_known_set_p (inner_mode
,
5624 #ifdef FLOAT_STORE_FLAG_VALUE
5626 && SCALAR_FLOAT_MODE_P (inner_mode
)
5627 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5628 REAL_VALUE_NEGATIVE (fsfv
)))
5631 && COMPARISON_P (SET_SRC (set
))))
5633 else if (((code
== EQ
5635 && val_signbit_known_set_p (inner_mode
,
5637 #ifdef FLOAT_STORE_FLAG_VALUE
5639 && SCALAR_FLOAT_MODE_P (inner_mode
)
5640 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5641 REAL_VALUE_NEGATIVE (fsfv
)))
5644 && COMPARISON_P (SET_SRC (set
)))
5649 else if ((code
== EQ
|| code
== NE
)
5650 && GET_CODE (SET_SRC (set
)) == XOR
)
5651 /* Handle sequences like:
5654 ...(eq|ne op0 (const_int 0))...
5658 (eq op0 (const_int 0)) reduces to (eq X Y)
5659 (ne op0 (const_int 0)) reduces to (ne X Y)
5661 This is the form used by MIPS16, for example. */
5667 else if (reg_set_p (op0
, prev
))
5668 /* If this sets OP0, but not directly, we have to give up. */
5673 /* If the caller is expecting the condition to be valid at INSN,
5674 make sure X doesn't change before INSN. */
5675 if (valid_at_insn_p
)
5676 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5678 if (COMPARISON_P (x
))
5679 code
= GET_CODE (x
);
5682 code
= reversed_comparison_code (x
, prev
);
5683 if (code
== UNKNOWN
)
5688 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5694 /* If constant is first, put it last. */
5695 if (CONSTANT_P (op0
))
5696 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5698 /* If OP0 is the result of a comparison, we weren't able to find what
5699 was really being compared, so fail. */
5701 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5704 /* Canonicalize any ordered comparison with integers involving equality
5705 if we can do computations in the relevant mode and we do not
5708 scalar_int_mode op0_mode
;
5709 if (CONST_INT_P (op1
)
5710 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &op0_mode
)
5711 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
)
5713 HOST_WIDE_INT const_val
= INTVAL (op1
);
5714 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5715 unsigned HOST_WIDE_INT max_val
5716 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (op0_mode
);
5721 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5722 code
= LT
, op1
= gen_int_mode (const_val
+ 1, op0_mode
);
5725 /* When cross-compiling, const_val might be sign-extended from
5726 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5728 if ((const_val
& max_val
)
5729 != (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (op0_mode
) - 1)))
5730 code
= GT
, op1
= gen_int_mode (const_val
- 1, op0_mode
);
5734 if (uconst_val
< max_val
)
5735 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, op0_mode
);
5739 if (uconst_val
!= 0)
5740 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, op0_mode
);
5748 /* Never return CC0; return zero instead. */
5752 /* We promised to return a comparison. */
5753 rtx ret
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5754 if (COMPARISON_P (ret
))
5759 /* Given a jump insn JUMP, return the condition that will cause it to branch
5760 to its JUMP_LABEL. If the condition cannot be understood, or is an
5761 inequality floating-point comparison which needs to be reversed, 0 will
5764 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5765 insn used in locating the condition was found. If a replacement test
5766 of the condition is desired, it should be placed in front of that
5767 insn and we will be sure that the inputs are still valid. If EARLIEST
5768 is null, the returned condition will be valid at INSN.
5770 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5771 compare CC mode register.
5773 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5776 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5777 int valid_at_insn_p
)
5783 /* If this is not a standard conditional jump, we can't parse it. */
5785 || ! any_condjump_p (jump
))
5787 set
= pc_set (jump
);
5789 cond
= XEXP (SET_SRC (set
), 0);
5791 /* If this branches to JUMP_LABEL when the condition is false, reverse
5794 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5795 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5797 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5798 allow_cc_mode
, valid_at_insn_p
);
5801 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5802 TARGET_MODE_REP_EXTENDED.
5804 Note that we assume that the property of
5805 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5806 narrower than mode B. I.e., if A is a mode narrower than B then in
5807 order to be able to operate on it in mode B, mode A needs to
5808 satisfy the requirements set by the representation of mode B. */
5811 init_num_sign_bit_copies_in_rep (void)
5813 opt_scalar_int_mode in_mode_iter
;
5814 scalar_int_mode mode
;
5816 FOR_EACH_MODE_IN_CLASS (in_mode_iter
, MODE_INT
)
5817 FOR_EACH_MODE_UNTIL (mode
, in_mode_iter
.require ())
5819 scalar_int_mode in_mode
= in_mode_iter
.require ();
5822 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5823 extends to the next widest mode. */
5824 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5825 || GET_MODE_WIDER_MODE (mode
).require () == in_mode
);
5827 /* We are in in_mode. Count how many bits outside of mode
5828 have to be copies of the sign-bit. */
5829 FOR_EACH_MODE (i
, mode
, in_mode
)
5831 /* This must always exist (for the last iteration it will be
5833 scalar_int_mode wider
= GET_MODE_WIDER_MODE (i
).require ();
5835 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5836 /* We can only check sign-bit copies starting from the
5837 top-bit. In order to be able to check the bits we
5838 have already seen we pretend that subsequent bits
5839 have to be sign-bit copies too. */
5840 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5841 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5842 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5847 /* Suppose that truncation from the machine mode of X to MODE is not a
5848 no-op. See if there is anything special about X so that we can
5849 assume it already contains a truncated value of MODE. */
5852 truncated_to_mode (machine_mode mode
, const_rtx x
)
5854 /* This register has already been used in MODE without explicit
5856 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5859 /* See if we already satisfy the requirements of MODE. If yes we
5860 can just switch to MODE. */
5861 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5862 && (num_sign_bit_copies (x
, GET_MODE (x
))
5863 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5869 /* Return true if RTX code CODE has a single sequence of zero or more
5870 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5871 entry in that case. */
5874 setup_reg_subrtx_bounds (unsigned int code
)
5876 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5878 for (; format
[i
] != 'e'; ++i
)
5881 /* No subrtxes. Leave start and count as 0. */
5883 if (format
[i
] == 'E' || format
[i
] == 'V')
5887 /* Record the sequence of 'e's. */
5888 rtx_all_subrtx_bounds
[code
].start
= i
;
5891 while (format
[i
] == 'e');
5892 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5893 /* rtl-iter.h relies on this. */
5894 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5896 for (; format
[i
]; ++i
)
5897 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5903 /* Initialize rtx_all_subrtx_bounds. */
5908 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5910 if (!setup_reg_subrtx_bounds (i
))
5911 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5912 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5913 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5916 init_num_sign_bit_copies_in_rep ();
5919 /* Check whether this is a constant pool constant. */
5921 constant_pool_constant_p (rtx x
)
5923 x
= avoid_constant_pool_reference (x
);
5924 return CONST_DOUBLE_P (x
);
5927 /* If M is a bitmask that selects a field of low-order bits within an item but
5928 not the entire word, return the length of the field. Return -1 otherwise.
5929 M is used in machine mode MODE. */
5932 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5934 if (mode
!= VOIDmode
)
5936 if (!HWI_COMPUTABLE_MODE_P (mode
))
5938 m
&= GET_MODE_MASK (mode
);
5941 return exact_log2 (m
+ 1);
5944 /* Return the mode of MEM's address. */
5947 get_address_mode (rtx mem
)
5951 gcc_assert (MEM_P (mem
));
5952 mode
= GET_MODE (XEXP (mem
, 0));
5953 if (mode
!= VOIDmode
)
5954 return as_a
<scalar_int_mode
> (mode
);
5955 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5958 /* Split up a CONST_DOUBLE or integer constant rtx
5959 into two rtx's for single words,
5960 storing in *FIRST the word that comes first in memory in the target
5961 and in *SECOND the other.
5963 TODO: This function needs to be rewritten to work on any size
5967 split_double (rtx value
, rtx
*first
, rtx
*second
)
5969 if (CONST_INT_P (value
))
5971 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5973 /* In this case the CONST_INT holds both target words.
5974 Extract the bits from it into two word-sized pieces.
5975 Sign extend each half to HOST_WIDE_INT. */
5976 unsigned HOST_WIDE_INT low
, high
;
5977 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5978 unsigned bits_per_word
= BITS_PER_WORD
;
5980 /* Set sign_bit to the most significant bit of a word. */
5982 sign_bit
<<= bits_per_word
- 1;
5984 /* Set mask so that all bits of the word are set. We could
5985 have used 1 << BITS_PER_WORD instead of basing the
5986 calculation on sign_bit. However, on machines where
5987 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5988 compiler warning, even though the code would never be
5990 mask
= sign_bit
<< 1;
5993 /* Set sign_extend as any remaining bits. */
5994 sign_extend
= ~mask
;
5996 /* Pick the lower word and sign-extend it. */
5997 low
= INTVAL (value
);
6002 /* Pick the higher word, shifted to the least significant
6003 bits, and sign-extend it. */
6004 high
= INTVAL (value
);
6005 high
>>= bits_per_word
- 1;
6008 if (high
& sign_bit
)
6009 high
|= sign_extend
;
6011 /* Store the words in the target machine order. */
6012 if (WORDS_BIG_ENDIAN
)
6014 *first
= GEN_INT (high
);
6015 *second
= GEN_INT (low
);
6019 *first
= GEN_INT (low
);
6020 *second
= GEN_INT (high
);
6025 /* The rule for using CONST_INT for a wider mode
6026 is that we regard the value as signed.
6027 So sign-extend it. */
6028 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
6029 if (WORDS_BIG_ENDIAN
)
6041 else if (GET_CODE (value
) == CONST_WIDE_INT
)
6043 /* All of this is scary code and needs to be converted to
6044 properly work with any size integer. */
6045 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
6046 if (WORDS_BIG_ENDIAN
)
6048 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6049 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6053 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6054 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6057 else if (!CONST_DOUBLE_P (value
))
6059 if (WORDS_BIG_ENDIAN
)
6061 *first
= const0_rtx
;
6067 *second
= const0_rtx
;
6070 else if (GET_MODE (value
) == VOIDmode
6071 /* This is the old way we did CONST_DOUBLE integers. */
6072 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
6074 /* In an integer, the words are defined as most and least significant.
6075 So order them by the target's convention. */
6076 if (WORDS_BIG_ENDIAN
)
6078 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6079 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
6083 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
6084 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6091 /* Note, this converts the REAL_VALUE_TYPE to the target's
6092 format, splits up the floating point double and outputs
6093 exactly 32 bits of it into each of l[0] and l[1] --
6094 not necessarily BITS_PER_WORD bits. */
6095 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
6097 /* If 32 bits is an entire word for the target, but not for the host,
6098 then sign-extend on the host so that the number will look the same
6099 way on the host that it would on the target. See for instance
6100 simplify_unary_operation. The #if is needed to avoid compiler
6103 #if HOST_BITS_PER_LONG > 32
6104 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
6106 if (l
[0] & ((long) 1 << 31))
6107 l
[0] |= ((unsigned long) (-1) << 32);
6108 if (l
[1] & ((long) 1 << 31))
6109 l
[1] |= ((unsigned long) (-1) << 32);
6113 *first
= GEN_INT (l
[0]);
6114 *second
= GEN_INT (l
[1]);
6118 /* Return true if X is a sign_extract or zero_extract from the least
6122 lsb_bitfield_op_p (rtx x
)
6124 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
6126 machine_mode mode
= GET_MODE (XEXP (x
, 0));
6127 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
6128 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
6129 poly_int64 remaining_bits
= GET_MODE_PRECISION (mode
) - len
;
6131 return known_eq (pos
, BITS_BIG_ENDIAN
? remaining_bits
: 0);
6136 /* Strip outer address "mutations" from LOC and return a pointer to the
6137 inner value. If OUTER_CODE is nonnull, store the code of the innermost
6138 stripped expression there.
6140 "Mutations" either convert between modes or apply some kind of
6141 extension, truncation or alignment. */
6144 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
6148 enum rtx_code code
= GET_CODE (*loc
);
6149 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
6150 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
6151 used to convert between pointer sizes. */
6152 loc
= &XEXP (*loc
, 0);
6153 else if (lsb_bitfield_op_p (*loc
))
6154 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
6155 acts as a combined truncation and extension. */
6156 loc
= &XEXP (*loc
, 0);
6157 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
6158 /* (and ... (const_int -X)) is used to align to X bytes. */
6159 loc
= &XEXP (*loc
, 0);
6160 else if (code
== SUBREG
6161 && !OBJECT_P (SUBREG_REG (*loc
))
6162 && subreg_lowpart_p (*loc
))
6163 /* (subreg (operator ...) ...) inside and is used for mode
6165 loc
= &SUBREG_REG (*loc
);
6173 /* Return true if CODE applies some kind of scale. The scaled value is
6174 is the first operand and the scale is the second. */
6177 binary_scale_code_p (enum rtx_code code
)
6179 return (code
== MULT
6181 /* Needed by ARM targets. */
6185 || code
== ROTATERT
);
6188 /* If *INNER can be interpreted as a base, return a pointer to the inner term
6189 (see address_info). Return null otherwise. */
6192 get_base_term (rtx
*inner
)
6194 if (GET_CODE (*inner
) == LO_SUM
)
6195 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6198 || GET_CODE (*inner
) == SUBREG
6199 || GET_CODE (*inner
) == SCRATCH
)
6204 /* If *INNER can be interpreted as an index, return a pointer to the inner term
6205 (see address_info). Return null otherwise. */
6208 get_index_term (rtx
*inner
)
6210 /* At present, only constant scales are allowed. */
6211 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
6212 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6215 || GET_CODE (*inner
) == SUBREG
6216 || GET_CODE (*inner
) == SCRATCH
)
6221 /* Set the segment part of address INFO to LOC, given that INNER is the
6225 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6227 gcc_assert (!info
->segment
);
6228 info
->segment
= loc
;
6229 info
->segment_term
= inner
;
6232 /* Set the base part of address INFO to LOC, given that INNER is the
6236 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6238 gcc_assert (!info
->base
);
6240 info
->base_term
= inner
;
6243 /* Set the index part of address INFO to LOC, given that INNER is the
6247 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6249 gcc_assert (!info
->index
);
6251 info
->index_term
= inner
;
6254 /* Set the displacement part of address INFO to LOC, given that INNER
6255 is the constant term. */
6258 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6260 gcc_assert (!info
->disp
);
6262 info
->disp_term
= inner
;
6265 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6266 rest of INFO accordingly. */
6269 decompose_incdec_address (struct address_info
*info
)
6271 info
->autoinc_p
= true;
6273 rtx
*base
= &XEXP (*info
->inner
, 0);
6274 set_address_base (info
, base
, base
);
6275 gcc_checking_assert (info
->base
== info
->base_term
);
6277 /* These addresses are only valid when the size of the addressed
6279 gcc_checking_assert (info
->mode
!= VOIDmode
);
6282 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6283 of INFO accordingly. */
6286 decompose_automod_address (struct address_info
*info
)
6288 info
->autoinc_p
= true;
6290 rtx
*base
= &XEXP (*info
->inner
, 0);
6291 set_address_base (info
, base
, base
);
6292 gcc_checking_assert (info
->base
== info
->base_term
);
6294 rtx plus
= XEXP (*info
->inner
, 1);
6295 gcc_assert (GET_CODE (plus
) == PLUS
);
6297 info
->base_term2
= &XEXP (plus
, 0);
6298 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6300 rtx
*step
= &XEXP (plus
, 1);
6301 rtx
*inner_step
= strip_address_mutations (step
);
6302 if (CONSTANT_P (*inner_step
))
6303 set_address_disp (info
, step
, inner_step
);
6305 set_address_index (info
, step
, inner_step
);
6308 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6309 values in [PTR, END). Return a pointer to the end of the used array. */
6312 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6315 if (GET_CODE (x
) == PLUS
)
6317 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6318 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6322 gcc_assert (ptr
!= end
);
6328 /* Evaluate the likelihood of X being a base or index value, returning
6329 positive if it is likely to be a base, negative if it is likely to be
6330 an index, and 0 if we can't tell. Make the magnitude of the return
6331 value reflect the amount of confidence we have in the answer.
6333 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6336 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6337 enum rtx_code outer_code
, enum rtx_code index_code
)
6339 /* Believe *_POINTER unless the address shape requires otherwise. */
6340 if (REG_P (x
) && REG_POINTER (x
))
6342 if (MEM_P (x
) && MEM_POINTER (x
))
6345 if (REG_P (x
) && HARD_REGISTER_P (x
))
6347 /* X is a hard register. If it only fits one of the base
6348 or index classes, choose that interpretation. */
6349 int regno
= REGNO (x
);
6350 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6351 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6352 if (base_p
!= index_p
)
6353 return base_p
? 1 : -1;
6358 /* INFO->INNER describes a normal, non-automodified address.
6359 Fill in the rest of INFO accordingly. */
6362 decompose_normal_address (struct address_info
*info
)
6364 /* Treat the address as the sum of up to four values. */
6366 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6367 ops
+ ARRAY_SIZE (ops
)) - ops
;
6369 /* If there is more than one component, any base component is in a PLUS. */
6371 info
->base_outer_code
= PLUS
;
6373 /* Try to classify each sum operand now. Leave those that could be
6374 either a base or an index in OPS. */
6377 for (size_t in
= 0; in
< n_ops
; ++in
)
6380 rtx
*inner
= strip_address_mutations (loc
);
6381 if (CONSTANT_P (*inner
))
6382 set_address_disp (info
, loc
, inner
);
6383 else if (GET_CODE (*inner
) == UNSPEC
)
6384 set_address_segment (info
, loc
, inner
);
6387 /* The only other possibilities are a base or an index. */
6388 rtx
*base_term
= get_base_term (inner
);
6389 rtx
*index_term
= get_index_term (inner
);
6390 gcc_assert (base_term
|| index_term
);
6392 set_address_index (info
, loc
, index_term
);
6393 else if (!index_term
)
6394 set_address_base (info
, loc
, base_term
);
6397 gcc_assert (base_term
== index_term
);
6399 inner_ops
[out
] = base_term
;
6405 /* Classify the remaining OPS members as bases and indexes. */
6408 /* If we haven't seen a base or an index yet, assume that this is
6409 the base. If we were confident that another term was the base
6410 or index, treat the remaining operand as the other kind. */
6412 set_address_base (info
, ops
[0], inner_ops
[0]);
6414 set_address_index (info
, ops
[0], inner_ops
[0]);
6418 /* In the event of a tie, assume the base comes first. */
6419 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6421 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6422 GET_CODE (*ops
[0])))
6424 set_address_base (info
, ops
[0], inner_ops
[0]);
6425 set_address_index (info
, ops
[1], inner_ops
[1]);
6429 set_address_base (info
, ops
[1], inner_ops
[1]);
6430 set_address_index (info
, ops
[0], inner_ops
[0]);
6434 gcc_assert (out
== 0);
6437 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6438 or VOIDmode if not known. AS is the address space associated with LOC.
6439 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6442 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6443 addr_space_t as
, enum rtx_code outer_code
)
6445 memset (info
, 0, sizeof (*info
));
6448 info
->addr_outer_code
= outer_code
;
6450 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6451 info
->base_outer_code
= outer_code
;
6452 switch (GET_CODE (*info
->inner
))
6458 decompose_incdec_address (info
);
6463 decompose_automod_address (info
);
6467 decompose_normal_address (info
);
6472 /* Describe address operand LOC in INFO. */
6475 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6477 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6480 /* Describe the address of MEM X in INFO. */
6483 decompose_mem_address (struct address_info
*info
, rtx x
)
6485 gcc_assert (MEM_P (x
));
6486 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6487 MEM_ADDR_SPACE (x
), MEM
);
6490 /* Update INFO after a change to the address it describes. */
6493 update_address (struct address_info
*info
)
6495 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6496 info
->addr_outer_code
);
6499 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6500 more complicated than that. */
6503 get_index_scale (const struct address_info
*info
)
6505 rtx index
= *info
->index
;
6506 if (GET_CODE (index
) == MULT
6507 && CONST_INT_P (XEXP (index
, 1))
6508 && info
->index_term
== &XEXP (index
, 0))
6509 return INTVAL (XEXP (index
, 1));
6511 if (GET_CODE (index
) == ASHIFT
6512 && CONST_INT_P (XEXP (index
, 1))
6513 && info
->index_term
== &XEXP (index
, 0))
6514 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6516 if (info
->index
== info
->index_term
)
6522 /* Return the "index code" of INFO, in the form required by
6526 get_index_code (const struct address_info
*info
)
6529 return GET_CODE (*info
->index
);
6532 return GET_CODE (*info
->disp
);
6537 /* Return true if RTL X contains a SYMBOL_REF. */
6540 contains_symbol_ref_p (const_rtx x
)
6542 subrtx_iterator::array_type array
;
6543 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6544 if (SYMBOL_REF_P (*iter
))
6550 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6553 contains_symbolic_reference_p (const_rtx x
)
6555 subrtx_iterator::array_type array
;
6556 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6557 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6563 /* Return true if RTL X contains a constant pool address. */
6566 contains_constant_pool_address_p (const_rtx x
)
6568 subrtx_iterator::array_type array
;
6569 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6570 if (SYMBOL_REF_P (*iter
) && CONSTANT_POOL_ADDRESS_P (*iter
))
6577 /* Return true if X contains a thread-local symbol. */
6580 tls_referenced_p (const_rtx x
)
6582 if (!targetm
.have_tls
)
6585 subrtx_iterator::array_type array
;
6586 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6587 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)