| blob | 3ad050fecf1a76bce932f32c91e52ad25c8480b6 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* And similarly, for notes. */
309 /* Basic block in which we are performing combines. */
313 \f
314 /* Length of the currently allocated uid_insn_cost array. */
318 /* The following array records the insn_cost for every insn
319 in the instruction stream. */
323 /* The following array records the LOG_LINKS for every insn in the
324 instruction stream as struct insn_link pointers. */
330 };
336 {
340 }
342 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
343 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
345 #define FOR_EACH_LOG_LINK(L, INSN) \
346 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348 /* Links for LOG_LINKS are allocated from this obstack. */
352 /* Allocate a link. */
356 {
364 }
366 /* Incremented for each basic block. */
370 /* Reset to label_tick for each extended basic block in scanning order. */
374 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
375 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
379 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
380 be safely used. It is zero while computing them and after combine has
381 completed. This former test prevents propagating values based on
382 previously set values, which can be incorrect if a variable is modified
383 in a loop. */
387 \f
388 /* Record one modification to rtl structure
389 to be undone by storing old_contents into *where. */
393 struct undo
394 {
399 };
401 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
402 num_undo says how many are currently recorded.
404 other_insn is nonzero if we have modified some other insn in the process
405 of working on subst_insn. It must be verified too. */
407 struct undobuf
408 {
412 };
416 /* Number of times the pseudo being substituted for
417 was found and replaced. */
422 scalar_int_mode,
425 scalar_int_mode,
497 \f
499 /* It is not safe to use ordinary gen_lowpart in combine.
500 See comments in gen_lowpart_for_combine. */
501 #undef RTL_HOOKS_GEN_LOWPART
502 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
504 /* Our implementation of gen_lowpart never emits a new pseudo. */
505 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
506 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
508 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
509 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
511 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
512 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
514 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
515 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
519 \f
520 /* Convenience wrapper for the canonicalize_comparison target hook.
521 Target hooks cannot use enum rtx_code. */
525 {
529 }
531 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
532 PATTERN can not be split. Otherwise, it returns an insn sequence.
533 This is a wrapper around split_insns which ensures that the
534 reg_stat vector is made larger if the splitter creates a new
535 register. */
539 {
548 }
550 /* This is used by find_single_use to locate an rtx in LOC that
551 contains exactly one use of DEST, which is typically either a REG
552 or CC0. It returns a pointer to the innermost rtx expression
553 containing DEST. Appearances of DEST that are being used to
554 totally replace it are not counted. */
558 {
567 {
571 CASE_CONST_ANY:
576 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
577 of a REG that occupies all of the REG, the insn uses DEST if
578 it is mentioned in the destination or the source. Otherwise, we
579 need just check the source. */
596 }
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
603 {
605 {
610 else
616 /* Duplicate usage. */
618 }
620 {
624 {
630 else
637 }
638 }
639 }
642 }
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
661 {
662 basic_block bb;
668 {
678 }
688 {
694 {
699 }
700 }
703 }
704 \f
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
713 {
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
727 {
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
743 }
747 else
756 }
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
766 {
775 else
784 }
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
795 {
804 else
813 }
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
821 {
830 else
839 }
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
842 \f
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
854 {
859 /* Lookup the original insn_costs. */
864 {
867 {
871 }
872 else
873 {
877 }
878 }
879 else
880 {
883 }
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
891 /* Calculate the replacement insn_costs. */
900 {
910 }
911 else
912 {
915 }
918 {
927 optimize_this_for_speed_p);
931 {
934 }
935 else
937 }
939 /* Disallow this combination if both new_cost and old_cost are greater than
940 zero, and new_cost is greater than old cost. */
944 {
963 else
965 }
970 /* Update the uid_insn_cost array with the replacement costs. */
974 {
978 }
981 }
984 /* Delete any insns that copy a register to itself. */
986 static void
988 {
990 basic_block bb;
993 {
995 {
998 {
1003 }
1004 }
1005 }
1006 }
1008 \f
1009 /* Return false if we do not want to (or cannot) combine DEF. */
1010 static bool
1012 {
1013 /* Do not consider if it is pre/post modification in MEM. */
1019 /* Do not combine frame pointer adjustments. */
1022 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1030 }
1032 /* Return false if we do not want to (or cannot) combine USE. */
1033 static bool
1035 {
1036 /* Do not consider the usage of the stack pointer by function call. */
1041 }
1043 /* Fill in log links field for all insns. */
1045 static void
1047 {
1048 basic_block bb;
1055 /* Pass through each block from the end, recording the uses of each
1056 register and establishing log links when def is encountered.
1057 Note that we do not clear next_use array in order to save time,
1058 so we have to test whether the use is in the same basic block as def.
1060 There are a few cases below when we do not consider the definition or
1061 usage -- these are taken from original flow.c did. Don't ask me why it is
1062 done this way; I don't know and if it works, I don't want to know. */
1065 {
1067 {
1071 /* Log links are created only once. */
1075 {
1091 /* flow.c claimed:
1093 We don't build a LOG_LINK for hard registers contained
1094 in ASM_OPERANDs. If these registers get replaced,
1095 we might wind up changing the semantics of the insn,
1096 even if reload can make what appear to be valid
1097 assignments later. */
1102 /* Don't add duplicate links between instructions. */
1111 }
1116 }
1117 }
1120 }
1122 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1123 true if we found a LOG_LINK that proves that A feeds B. This only works
1124 if there are no instructions between A and B which could have a link
1125 depending on A, since in that case we would not record a link for B.
1126 We also check the implicit dependency created by a cc0 setter/user
1127 pair. */
1129 static bool
1131 {
1139 }
1140 \f
1141 /* Main entry point for combiner. F is the first insn of the function.
1142 NREGS is the first unused pseudo-reg number.
1144 Return nonzero if the combiner has turned an indirect jump
1145 instruction into a direct jump. */
1146 static int
1148 {
1153 basic_block last_bb;
1173 /* Allocate array for insn info. */
1181 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1182 problems when, for example, we have j <<= 1 in a loop. */
1187 /* Scan all SETs and see if we can deduce anything about what
1188 bits are known to be zero for some registers and how many copies
1189 of the sign bit are known to exist for those registers.
1191 Also set any known values so that we can use it while searching
1192 for what bits are known to be set. */
1195 /* Allow the entry block and the first block to fall into the same EBB.
1196 Conceptually the incoming promotions are assigned to the entry block. */
1201 {
1206 label_tick++;
1214 {
1215 rtx links;
1221 insn);
1228 insn);
1230 /* Record the current insn_cost of this instruction. */
1234 {
1237 }
1238 }
1239 }
1243 /* Now scan all the insns in forward order. */
1251 {
1254 /* Ignore instruction combination in basic blocks that are going to
1255 be removed as unreachable anyway. See PR82386. */
1263 label_tick++;
1273 {
1287 /* See if we know about function return values before this
1288 insn based upon SUBREG flags. */
1291 /* See if we can find hardregs and subreg of pseudos in
1292 narrower modes. This could help turning TRUNCATEs
1293 into SUBREGs. */
1296 /* Try this insn with each insn it links back to. */
1302 {
1305 }
1307 /* Try each sequence of three linked insns ending with this one. */
1311 {
1314 /* If the linked insn has been replaced by a note, then there
1315 is no point in pursuing this chain any further. */
1323 {
1326 }
1327 }
1329 /* Try to combine a jump insn that uses CC0
1330 with a preceding insn that sets CC0, and maybe with its
1331 logical predecessor as well.
1332 This is how we make decrement-and-branch insns.
1333 We need this special code because data flow connections
1334 via CC0 do not get entered in LOG_LINKS. */
1341 {
1352 }
1354 /* Do the same for an insn that explicitly references CC0. */
1361 {
1372 }
1374 /* Finally, see if any of the insns that this insn links to
1375 explicitly references CC0. If so, try this insn, that insn,
1376 and its predecessor if it sets CC0. */
1378 {
1390 }
1392 /* Try combining an insn with two different insns whose results it
1393 uses. */
1403 {
1406 }
1408 /* Try four-instruction combinations. */
1411 {
1415 /* If the linked insn has been replaced by a note, then there
1416 is no point in pursuing this chain any further. */
1421 {
1425 /* I0 -> I1 -> I2 -> I3. */
1431 {
1434 }
1435 /* I0, I1 -> I2, I2 -> I3. */
1442 {
1445 }
1446 }
1449 {
1453 /* I0 -> I2; I1, I2 -> I3. */
1459 {
1462 }
1463 /* I0 -> I1; I1, I2 -> I3. */
1469 {
1472 }
1473 }
1474 }
1476 /* Try this insn with each REG_EQUAL note it links back to. */
1478 {
1484 /* Avoid using a register that may already been marked
1485 dead by an earlier instruction. */
1493 {
1494 /* Temporarily replace the set's source with the
1495 contents of the REG_EQUAL note. The insn will
1496 be deleted or recognized by try_combine. */
1507 last_combined_insn);
1510 {
1513 }
1516 }
1517 }
1522 retry:
1523 ;
1524 }
1525 }
1532 /* Clean up. */
1538 {
1541 {
1544 }
1546 }
1556 /* Make recognizer allow volatile MEMs again. */
1560 }
1562 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1564 static void
1566 {
1572 }
1573 \f
1574 /* Set up any promoted values for incoming argument registers. */
1576 static void
1578 {
1579 tree arg;
1584 {
1589 /* Only continue if the incoming argument is in a register. */
1593 /* Determine, if possible, whether all call sites of the current
1594 function lie within the current compilation unit. (This does
1595 take into account the exporting of a function via taking its
1596 address, and so forth.) */
1599 /* The mode and signedness of the argument before any promotions happen
1600 (equal to the mode of the pseudo holding it at that stage). */
1604 /* The mode and signedness of the argument after any source language and
1605 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1609 /* The mode and signedness of the argument as it is actually passed,
1610 see assign_parm_setup_reg in function.c. */
1614 /* The mode of the register in which the argument is being passed. */
1617 /* Eliminate sign extensions in the callee when:
1618 (a) A mode promotion has occurred; */
1621 /* (b) The mode of the register is the same as the mode of
1622 the argument as it is passed; */
1625 /* (c) There's no language level extension; */
1627 ;
1628 /* (c.1) All callers are from the current compilation unit. If that's
1629 the case we don't have to rely on an ABI, we only have to know
1630 what we're generating right now, and we know that we will do the
1631 mode1 to mode2 promotion with the given sign. */
1634 /* (c.2) The combination of the two promotions is useful. This is
1635 true when the signs match, or if the first promotion is unsigned.
1636 In the later case, (sign_extend (zero_extend x)) is the same as
1637 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1643 /* Record that the value was promoted from mode1 to mode3,
1644 so that any sign extension at the head of the current
1645 function may be eliminated. */
1649 }
1650 }
1652 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1653 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1654 because some machines (maybe most) will actually do the sign-extension and
1655 this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1658 kludge. */
1660 static rtx
1662 {
1663 scalar_int_mode int_mode;
1672 }
1674 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1675 and SET. */
1677 static void
1679 rtx x)
1680 {
1690 {
1694 }
1696 /* Don't call nonzero_bits if it cannot change anything. */
1698 {
1703 }
1705 /* Don't call num_sign_bit_copies if it cannot change anything. */
1707 {
1710 {
1714 }
1717 }
1718 }
1720 /* Called via note_stores. If X is a pseudo that is narrower than
1721 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1723 If we are setting only a portion of X and we can't figure out what
1724 portion, assume all bits will be used since we don't know what will
1725 be happening.
1727 Similarly, set how many bits of X are known to be copies of the sign bit
1728 at all locations in the function. This is the smallest number implied
1729 by any set of X. */
1731 static void
1733 {
1735 scalar_int_mode mode;
1739 /* If this register is undefined at the start of the file, we can't
1740 say what its contents were. */
1741 && ! REGNO_REG_SET_P
1745 {
1749 {
1753 }
1755 /* If this register is being initialized using itself, and the
1756 register is uninitialized in this basic block, and there are
1757 no LOG_LINKS which set the register, then part of the
1758 register is uninitialized. In that case we can't assume
1759 anything about the number of nonzero bits.
1761 ??? We could do better if we checked this in
1762 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1763 could avoid making assumptions about the insn which initially
1764 sets the register, while still using the information in other
1765 insns. We would have to be careful to check every insn
1766 involved in the combination. */
1772 {
1779 {
1783 }
1784 }
1786 /* If this is a complex assignment, see if we can convert it into a
1787 simple assignment. */
1790 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1791 set what we know about X. */
1797 else
1798 {
1801 }
1802 }
1803 }
1804 \f
1805 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1806 optionally insns that were previously combined into I3 or that will be
1807 combined into the merger of INSN and I3. The order is PRED, PRED2,
1808 INSN, SUCC, SUCC2, I3.
1810 Return 0 if the combination is not allowed for any reason.
1812 If the combination is allowed, *PDEST will be set to the single
1813 destination of INSN and *PSRC to the single source, and this function
1814 will return 1. */
1816 static int
1820 {
1825 rtx link;
1830 {
1832 {
1837 }
1842 }
1846 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1847 or a PARALLEL consisting of such a SET and CLOBBERs.
1849 If INSN has CLOBBER parallel parts, ignore them for our processing.
1850 By definition, these happen during the execution of the insn. When it
1851 is merged with another insn, all bets are off. If they are, in fact,
1852 needed and aren't also supplied in I3, they may be added by
1853 recog_for_combine. Otherwise, it won't match.
1855 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1856 note.
1858 Get the source and destination of INSN. If more than one, can't
1859 combine. */
1865 {
1867 {
1871 {
1872 /* This is important to combine floating point insns
1873 for the SH4 port. */
1875 /* Combining an isolated USE doesn't make sense.
1876 We depend here on combinable_i3pat to reject them. */
1877 /* The code below this loop only verifies that the inputs of
1878 the SET in INSN do not change. We call reg_set_between_p
1879 to verify that the REG in the USE does not change between
1880 I3 and INSN.
1881 If the USE in INSN was for a pseudo register, the matching
1882 insn pattern will likely match any register; combining this
1883 with any other USE would only be safe if we knew that the
1884 used registers have identical values, or if there was
1885 something to tell them apart, e.g. different modes. For
1886 now, we forgo such complicated tests and simply disallow
1887 combining of USES of pseudo registers with any other USE. */
1890 {
1895 do
1896 {
1906 }
1908 }
1911 /* We can ignore CLOBBERs. */
1916 /* Ignore SETs whose result isn't used but not those that
1917 have side-effects. */
1923 /* If we have already found a SET, this is a second one and
1924 so we cannot combine with this insn. */
1932 /* Anything else means we can't combine. */
1934 }
1935 }
1938 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1939 so don't do anything with it. */
1942 }
1943 else
1949 /* The simplification in expand_field_assignment may call back to
1950 get_last_value, so set safe guard here. */
1956 /* Do not eliminate user-specified register if it is in an
1957 asm input because we may break the register asm usage defined
1958 in GCC manual if allow to do so.
1959 Be aware that this may cover more cases than we expect but this
1960 should be harmless. */
1965 /* Don't eliminate a store in the stack pointer. */
1967 /* Don't combine with an insn that sets a register to itself if it has
1968 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1970 /* Can't merge an ASM_OPERANDS. */
1972 /* Can't merge a function call. */
1974 /* Don't eliminate a function call argument. */
1980 /* Don't substitute into an incremented register. */
1984 /* Don't substitute into a non-local goto, this confuses CFG. */
1986 /* Make sure that DEST is not used after INSN but before SUCC, or
1987 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1988 || (!all_adjacent
1989 && ((succ2
1994 || (succ
1995 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1996 that case SUCC is not in the insn stream, so use SUCC2
1997 instead for this test. */
1999 succ2
2002 /* Make sure that the value that is to be substituted for the register
2003 does not use any registers whose values alter in between. However,
2004 If the insns are adjacent, a use can't cross a set even though we
2005 think it might (this can happen for a sequence of insns each setting
2006 the same destination; last_set of that register might point to
2007 a NOTE). If INSN has a REG_EQUIV note, the register is always
2008 equivalent to the memory so the substitution is valid even if there
2009 are intervening stores. Also, don't move a volatile asm or
2010 UNSPEC_VOLATILE across any other insns. */
2011 || (! all_adjacent
2017 /* Don't combine across a CALL_INSN, because that would possibly
2018 change whether the life span of some REGs crosses calls or not,
2019 and it is a pain to update that information.
2020 Exception: if source is a constant, moving it later can't hurt.
2021 Accept that as a special case. */
2025 /* DEST must either be a REG or CC0. */
2027 {
2028 /* If register alignment is being enforced for multi-word items in all
2029 cases except for parameters, it is possible to have a register copy
2030 insn referencing a hard register that is not allowed to contain the
2031 mode being copied and which would not be valid as an operand of most
2032 insns. Eliminate this problem by not combining with such an insn.
2034 Also, on some machines we don't want to extend the life of a hard
2035 register. */
2040 /* Don't extend the life of a hard register unless it is
2041 user variable (if we have few registers) or it can't
2042 fit into the desired register (meaning something special
2043 is going on).
2044 Also avoid substituting a return register into I3, because
2045 reload can't handle a conflict with constraints of other
2046 inputs. */
2051 }
2059 {
2062 /* If the clobber represents an earlyclobber operand, we must not
2063 substitute an expression containing the clobbered register.
2064 As we do not analyze the constraint strings here, we have to
2065 make the conservative assumption. However, if the register is
2066 a fixed hard reg, the clobber cannot represent any operand;
2067 we leave it up to the machine description to either accept or
2068 reject use-and-clobber patterns. */
2074 }
2076 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2077 or not), reject, unless nothing volatile comes between it and I3 */
2080 {
2081 /* Make sure neither succ nor succ2 contains a volatile reference. */
2086 /* We'll check insns between INSN and I3 below. */
2087 }
2089 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2090 to be an explicit register variable, and was chosen for a reason. */
2096 /* If INSN contains volatile references (specifically volatile MEMs),
2097 we cannot combine across any other volatile references.
2098 Even if INSN doesn't contain volatile references, any intervening
2099 volatile insn might affect machine state. */
2102 ? volatile_refs_p
2109 /* If INSN contains an autoincrement or autodecrement, make sure that
2110 register is not used between there and I3, and not already used in
2111 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2112 Also insist that I3 not be a jump; if it were one
2113 and the incremented register were spilled, we would lose. */
2131 /* Don't combine an insn that follows a CC0-setting insn.
2132 An insn that uses CC0 must not be separated from the one that sets it.
2133 We do, however, allow I2 to follow a CC0-setting insn if that insn
2134 is passed as I1; in that case it will be deleted also.
2135 We also allow combining in this case if all the insns are adjacent
2136 because that would leave the two CC0 insns adjacent as well.
2137 It would be more logical to test whether CC0 occurs inside I1 or I2,
2138 but that would be much slower, and this ought to be equivalent. */
2141 {
2146 }
2148 /* If we get here, we have passed all the tests and the combination is
2149 to be allowed. */
2155 }
2156 \f
2157 /* LOC is the location within I3 that contains its pattern or the component
2158 of a PARALLEL of the pattern. We validate that it is valid for combining.
2160 One problem is if I3 modifies its output, as opposed to replacing it
2161 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2162 doing so would produce an insn that is not equivalent to the original insns.
2164 Consider:
2166 (set (reg:DI 101) (reg:DI 100))
2167 (set (subreg:SI (reg:DI 101) 0) <foo>)
2169 This is NOT equivalent to:
2171 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2172 (set (reg:DI 101) (reg:DI 100))])
2174 Not only does this modify 100 (in which case it might still be valid
2175 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2177 We can also run into a problem if I2 sets a register that I1
2178 uses and I1 gets directly substituted into I3 (not via I2). In that
2179 case, we would be getting the wrong value of I2DEST into I3, so we
2180 must reject the combination. This case occurs when I2 and I1 both
2181 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2182 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2183 of a SET must prevent combination from occurring. The same situation
2184 can occur for I0, in which case I0_NOT_IN_SRC is set.
2186 Before doing the above check, we first try to expand a field assignment
2187 into a set of logical operations.
2189 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2190 we place a register that is both set and used within I3. If more than one
2191 such register is detected, we fail.
2193 Return 1 if the combination is valid, zero otherwise. */
2195 static int
2198 {
2202 {
2207 rtx subdest;
2214 /* Check for the case where I3 modifies its output, as discussed
2215 above. We don't want to prevent pseudos from being combined
2216 into the address of a MEM, so only prevent the combination if
2217 i1 or i2 set the same MEM. */
2227 /* This is the same test done in can_combine_p except we can't test
2228 all_adjacent; we don't have to, since this instruction will stay
2229 in place, thus we are not considering increasing the lifetime of
2230 INNER_DEST.
2232 Also, if this insn sets a function argument, combining it with
2233 something that might need a spill could clobber a previous
2234 function argument; the all_adjacent test in can_combine_p also
2235 checks this; here, we do a more specific test for this case. */
2245 /* If DEST is used in I3, it is being killed in this insn, so
2246 record that for later. We have to consider paradoxical
2247 subregs here, since they kill the whole register, but we
2248 ignore partial subregs, STRICT_LOW_PART, etc.
2249 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2250 STACK_POINTER_REGNUM, since these are always considered to be
2251 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2259 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2265 {
2270 }
2271 }
2274 {
2281 }
2284 }
2285 \f
2286 /* Return 1 if X is an arithmetic expression that contains a multiplication
2287 and division. We don't count multiplications by powers of two here. */
2289 static int
2291 {
2293 {
2309 }
2310 }
2311 \f
2312 /* Determine whether INSN can be used in a combination. Return nonzero if
2313 not. This is used in try_combine to detect early some cases where we
2314 can't perform combinations. */
2316 static int
2318 {
2319 rtx set;
2322 /* If this isn't really an insn, we can't do anything.
2323 This can occur when flow deletes an insn that it has merged into an
2324 auto-increment address. */
2328 /* Never combine loads and stores involving hard regs that are likely
2329 to be spilled. The register allocator can usually handle such
2330 reg-reg moves by tying. If we allow the combiner to make
2331 substitutions of likely-spilled regs, reload might die.
2332 As an exception, we allow combinations involving fixed regs; these are
2333 not available to the register allocator so there's no risk involved. */
2354 }
2356 struct likely_spilled_retval_info
2357 {
2360 };
2362 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2363 hard registers that are known to be written to / clobbered in full. */
2364 static void
2366 {
2383 else
2386 }
2388 /* Return nonzero iff part of the return value is live during INSN, and
2389 it is likely spilled. This can happen when more than one insn is needed
2390 to copy the return value, e.g. when we consider to combine into the
2391 second copy insn for a complex value. */
2393 static int
2395 {
2397 rtx reg;
2400 /* We assume here that no machine mode needs more than
2401 32 hard registers when the value overlaps with a register
2402 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2417 /* Disregard parts of the return value that are set later. */
2426 /* Check if any of the (probably) live return value registers is
2427 likely spilled. */
2428 nregs --;
2429 do
2430 {
2436 }
2438 /* Adjust INSN after we made a change to its destination.
2440 Changing the destination can invalidate notes that say something about
2441 the results of the insn and a LOG_LINK pointing to the insn. */
2443 static void
2445 {
2446 /* For notes, be conservative and simply remove them. */
2449 /* The new insn will have a destination that was previously the destination
2450 of an insn just above it. Call distribute_links to make a LOG_LINK from
2451 the next use of that destination. */
2467 }
2469 /* Return TRUE if combine can reuse reg X in mode MODE.
2470 ADDED_SETS is nonzero if the original set is still required. */
2471 static bool
2473 {
2479 /* Don't change between modes with different underlying register sizes,
2480 since this could lead to invalid subregs. */
2486 /* Allow hard registers if the new mode is legal, and occupies no more
2487 registers than the old mode. */
2492 /* Or a pseudo that is only used once. */
2495 && !added_sets
2497 }
2500 /* Check whether X, the destination of a set, refers to part of
2501 the register specified by REG. */
2503 static bool
2505 {
2506 /* Check that reg is an integer mode register. */
2517 }
2519 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2520 Note that the INSN should be deleted *after* removing dead edges, so
2521 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2522 but not for a (set (pc) (label_ref FOO)). */
2524 static void
2526 {
2534 {
2539 /* Remove barriers from the footer if there are any. */
2542 {
2545 else
2549 }
2552 }
2553 }
2555 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2556 by an arbitrary number of CLOBBERs. */
2557 static bool
2559 {
2578 }
2580 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2581 CLOBBERs), can be split into individual SETs in that order, without
2582 changing semantics. */
2583 static bool
2585 {
2593 {
2602 }
2605 }
2607 /* Try to combine the insns I0, I1 and I2 into I3.
2608 Here I0, I1 and I2 appear earlier than I3.
2609 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2610 I3.
2612 If we are combining more than two insns and the resulting insn is not
2613 recognized, try splitting it into two insns. If that happens, I2 and I3
2614 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2615 Otherwise, I0, I1 and I2 are pseudo-deleted.
2617 Return 0 if the combination does not work. Then nothing is changed.
2618 If we did the combination, return the insn at which combine should
2619 resume scanning.
2621 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2622 new direct jump instruction.
2624 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2625 been I3 passed to an earlier try_combine within the same basic
2626 block. */
2631 {
2632 /* New patterns for I3 and I2, respectively. */
2636 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2637 dead. */
2639 /* Total number of SETs to put into I3. */
2641 /* Nonzero if I2's or I1's body now appears in I3. */
2643 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2645 /* Contains I3 if the destination of I3 is used in its source, which means
2646 that the old life of I3 is being killed. If that usage is placed into
2647 I2 and not in I3, a REG_DEAD note must be made. */
2649 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2651 /* Copy of SET_SRC of I1 and I0, if needed. */
2653 /* Set if I2DEST was reused as a scratch register. */
2655 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2657 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2662 /* Notes that must be added to REG_NOTES in I3 and I2. */
2664 /* Notes that we substituted I3 into I2 instead of the normal case. */
2666 /* Notes that I1, I2 or I3 is a MULT operation. */
2674 rtx temp_expr;
2677 rtx new_other_notes;
2681 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2682 never be). */
2686 /* Only try four-insn combinations when there's high likelihood of
2687 success. Look for simple insns, such as loads of constants or
2688 binary operations involving a constant. */
2690 {
2700 {
2703 rtx src;
2708 {
2711 }
2713 ngood++;
2716 nshift++;
2717 }
2719 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2720 are likely manipulating its value. Ideally we'll be able to combine
2721 all four insns into a bitfield insertion of some kind.
2723 Note the source in I0 might be inside a sign/zero extension and the
2724 memory modes in I0 and I3 might be different. So extract the address
2725 from the destination of I3 and search for it in the source of I0.
2727 In the event that there's a match but the source/dest do not actually
2728 refer to the same memory, the worst that happens is we try some
2729 combinations that we wouldn't have otherwise. */
2731 /* Ensure the source of SET0 is a MEM, possibly buried inside
2732 an extension. */
2738 /* Ensure the destination of SET3 is a MEM. */
2740 /* Would it be better to extract the base address for the MEM
2741 in SET3 and look for that? I don't have cases where it matters
2742 but I could envision such cases. */
2748 }
2750 /* Exit early if one of the insns involved can't be used for
2751 combinations. */
2762 combine_attempts++;
2765 /* Reset the hard register usage information. */
2769 {
2776 else
2786 }
2788 /* If multiple insns feed into one of I2 or I3, they can be in any
2789 order. To simplify the code below, reorder them in sequence. */
2800 /* First check for one important special case that the code below will
2801 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2802 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2803 we may be able to replace that destination with the destination of I3.
2804 This occurs in the common code where we compute both a quotient and
2805 remainder into a structure, in which case we want to do the computation
2806 directly into the structure to avoid register-register copies.
2808 Note that this case handles both multiple sets in I2 and also cases
2809 where I2 has a number of CLOBBERs inside the PARALLEL.
2811 We make very conservative checks below and only try to handle the
2812 most common cases of this. For example, we only handle the case
2813 where I2 and I3 are adjacent to avoid making difficult register
2814 usage tests. */
2822 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2823 below would need to check what is inside (and reg_overlap_mentioned_p
2824 doesn't support those codes anyway). Don't allow those destinations;
2825 the resulting insn isn't likely to be recognized anyway. */
2831 {
2834 /* Make sure that the destination of I3,
2835 which we are going to substitute into one output of I2,
2836 is not used within another output of I2. We must avoid making this:
2837 (parallel [(set (mem (reg 69)) ...)
2838 (set (reg 69) ...)])
2839 which is not well-defined as to order of actions.
2840 (Besides, reload can't handle output reloads for this.)
2842 The problem can also happen if the dest of I3 is a memory ref,
2843 if another dest in I2 is an indirect memory ref.
2845 Neither can this PARALLEL be an asm. We do not allow combining
2846 that usually (see can_combine_p), so do not here either. */
2849 {
2858 }
2864 {
2865 combine_merges++;
2875 /* Replace the dest in I2 with our dest and make the resulting
2876 insn the new pattern for I3. Then skip to where we validate
2877 the pattern. Everything was set up above. */
2882 }
2883 }
2885 /* If I2 is setting a pseudo to a constant and I3 is setting some
2886 sub-part of it to another constant, merge them by making a new
2887 constant. */
2895 {
2902 {
2907 {
2913 }
2914 }
2915 else
2916 {
2920 {
2923 }
2924 }
2927 {
2928 /* If this is the low part, we're done. */
2930 ;
2931 /* Handle the case where inner is twice the size of outer. */
2935 /* Otherwise give up for now. */
2936 else
2938 }
2941 {
2949 combine_merges++;
2956 /* Replace the source in I2 with the new constant and make the
2957 resulting insn the new pattern for I3. Then skip to where we
2958 validate the pattern. Everything was set up above. */
2964 /* The dest of I3 has been replaced with the dest of I2. */
2967 }
2968 }
2970 /* If we have no I1 and I2 looks like:
2971 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2972 (set Y OP)])
2973 make up a dummy I1 that is
2974 (set Y OP)
2975 and change I2 to be
2976 (set (reg:CC X) (compare:CC Y (const_int 0)))
2978 (We can ignore any trailing CLOBBERs.)
2980 This undoes a previous combination and allows us to match a branch-and-
2981 decrement insn. */
2993 {
2994 /* We make I1 with the same INSN_UID as I2. This gives it
2995 the same DF_INSN_LUID for value tracking. Our fake I1 will
2996 never appear in the insn stream so giving it the same INSN_UID
2997 as I2 will not cause a problem. */
3010 }
3012 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3013 make those two SETs separate I1 and I2 insns, and make an I0 that is
3014 the original I1. */
3022 {
3023 /* If there is no I1, there is no I0 either. */
3026 /* We make I1 with the same INSN_UID as I2. This gives it
3027 the same DF_INSN_LUID for value tracking. Our fake I1 will
3028 never appear in the insn stream so giving it the same INSN_UID
3029 as I2 will not cause a problem. */
3037 }
3039 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3041 {
3046 }
3048 {
3053 }
3055 {
3060 }
3062 /* Record whether I2DEST is used in I2SRC and similarly for the other
3063 cases. Knowing this will help in register status updating below. */
3074 /* For the earlier insns, determine which of the subsequent ones they
3075 feed. */
3082 /* Ensure that I3's pattern can be the destination of combines. */
3088 {
3091 }
3093 /* See if any of the insns is a MULT operation. Unless one is, we will
3094 reject a combination that is, since it must be slower. Be conservative
3095 here. */
3103 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3104 We used to do this EXCEPT in one case: I3 has a post-inc in an
3105 output operand. However, that exception can give rise to insns like
3106 mov r3,(r3)+
3107 which is a famous insn on the PDP-11 where the value of r3 used as the
3108 source was model-dependent. Avoid this sort of thing. */
3110 #if 0
3116 /* It's not the exception. */
3117 #endif
3119 {
3120 rtx link;
3126 {
3129 }
3130 }
3132 /* See if the SETs in I1 or I2 need to be kept around in the merged
3133 instruction: whenever the value set there is still needed past I3.
3134 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3136 For the SET in I1, we have two cases: if I1 and I2 independently feed
3137 into I3, the set in I1 needs to be kept around unless I1DEST dies
3138 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3139 in I1 needs to be kept around unless I1DEST dies or is set in either
3140 I2 or I3. The same considerations apply to I0. */
3147 else
3155 else
3158 /* We are about to copy insns for the case where they need to be kept
3159 around. Check that they can be copied in the merged instruction. */
3165 {
3168 }
3170 /* If the set in I2 needs to be kept around, we must make a copy of
3171 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3172 PATTERN (I2), we are only substituting for the original I1DEST, not into
3173 an already-substituted copy. This also prevents making self-referential
3174 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3175 I2DEST. */
3178 {
3181 else
3183 }
3186 {
3189 else
3191 }
3194 {
3197 else
3199 }
3201 combine_merges++;
3203 /* Substitute in the latest insn for the regs set by the earlier ones. */
3209 /* Many machines that don't use CC0 have insns that can both perform an
3210 arithmetic operation and set the condition code. These operations will
3211 be represented as a PARALLEL with the first element of the vector
3212 being a COMPARE of an arithmetic operation with the constant zero.
3213 The second element of the vector will set some pseudo to the result
3214 of the same arithmetic operation. If we simplify the COMPARE, we won't
3215 match such a pattern and so will generate an extra insn. Here we test
3216 for this case, where both the comparison and the operation result are
3217 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3218 I2SRC. Later we will make the PARALLEL that contains I2. */
3224 {
3225 rtx newpat_dest;
3231 scalar_int_mode mode;
3240 {
3246 }
3248 /* Do the rest only if op1 is const0_rtx, which may be the
3249 result of simplification. */
3251 {
3252 /* If a single use of the CC is found, prepare to modify it
3253 when SELECT_CC_MODE returns a new CC-class mode, or when
3254 the above simplify_compare_const() returned a new comparison
3255 operator. undobuf.other_insn is assigned the CC use insn
3256 when modifying it. */
3258 {
3259 #ifdef SELECT_CC_MODE
3260 machine_mode new_mode
3265 {
3270 else
3271 {
3274 }
3275 }
3276 #endif
3277 /* Cases for modifying the CC-using comparison. */
3279 /* ??? Do we need to verify the zero rtx? */
3281 {
3282 /* Replace cc_use_loc with entire new RTX. */
3287 }
3289 {
3290 /* Just replace the CC reg with a new mode. */
3293 }
3294 }
3296 /* Now we modify the current newpat:
3297 First, SET_DEST(newpat) is updated if the CC mode has been
3298 altered. For targets without SELECT_CC_MODE, this should be
3299 optimized away. */
3302 /* This is always done to propagate i2src into newpat. */
3305 /* Create new version of i2pat if needed; the below PARALLEL
3306 creation needs this to work correctly. */
3310 }
3311 }
3314 {
3315 /* It is possible that the source of I2 or I1 may be performing
3316 an unneeded operation, such as a ZERO_EXTEND of something
3317 that is known to have the high part zero. Handle that case
3318 by letting subst look at the inner insns.
3320 Another way to do this would be to have a function that tries
3321 to simplify a single insn instead of merging two or more
3322 insns. We don't do this because of the potential of infinite
3323 loops and because of the potential extra memory required.
3324 However, doing it the way we are is a bit of a kludge and
3325 doesn't catch all cases.
3327 But only do this if -fexpensive-optimizations since it slows
3328 things down and doesn't usually win.
3330 This is not done in the COMPARE case above because the
3331 unmodified I2PAT is used in the PARALLEL and so a pattern
3332 with a modified I2SRC would not match. */
3335 {
3336 /* Pass pc_rtx so no substitutions are done, just
3337 simplifications. */
3339 {
3342 }
3346 }
3351 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3352 copy of I2SRC each time we substitute it, in order to avoid creating
3353 self-referential RTL when we will be substituting I1SRC for I1DEST
3354 later. Likewise if I0 feeds into I2, either directly or indirectly
3355 through I1, and I0DEST is in I0SRC. */
3362 /* Record whether I2's body now appears within I3's body. */
3364 }
3366 /* If we already got a failure, don't try to do more. Otherwise, try to
3367 substitute I1 if we have it. */
3370 {
3371 /* Check that an autoincrement side-effect on I1 has not been lost.
3372 This happens if I1DEST is mentioned in I2 and dies there, and
3373 has disappeared from the new pattern. */
3375 && i1_feeds_i2_n
3378 /* Before we can do this substitution, we must redo the test done
3379 above (see detailed comments there) that ensures I1DEST isn't
3380 mentioned in any SETs in NEWPAT that are field assignments. */
3383 {
3386 }
3391 /* If the following substitution will modify I1SRC, make a copy of it
3392 for the case where it is substituted for I1DEST in I2PAT later. */
3396 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3397 copy of I1SRC each time we substitute it, in order to avoid creating
3398 self-referential RTL when we will be substituting I0SRC for I0DEST
3399 later. */
3404 /* Record whether I1's body now appears within I3's body. */
3406 }
3408 /* Likewise for I0 if we have it. */
3411 {
3418 {
3421 }
3423 /* If the following substitution will modify I0SRC, make a copy of it
3424 for the case where it is substituted for I0DEST in I1PAT later. */
3427 /* And a copy for I0DEST in I2PAT substitution. */
3436 }
3438 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3439 to count all the ways that I2SRC and I1SRC can be used. */
3450 /* Fail if we tried to make a new register. */
3452 /* Fail if we couldn't do something and have a CLOBBER. */
3454 /* Fail if this new pattern is a MULT and we didn't have one before
3455 at the outer level. */
3458 {
3461 }
3463 /* If the actions of the earlier insns must be kept
3464 in addition to substituting them into the latest one,
3465 we must make a new PARALLEL for the latest insn
3466 to hold additional the SETs. */
3469 {
3471 combine_extras++;
3474 {
3480 }
3481 else
3482 {
3487 }
3493 {
3499 }
3501 {
3510 }
3511 }
3513 validate_replacement:
3515 /* Note which hard regs this insn has as inputs. */
3518 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3519 consider splitting this pattern, we might need these clobbers. */
3522 {
3528 }
3530 /* We have recognized nothing yet. */
3533 /* See if this is a PARALLEL of two SETs where one SET's destination is
3534 a register that is unused and this isn't marked as an instruction that
3535 might trap in an EH region. In that case, we just need the other SET.
3536 We prefer this over the PARALLEL.
3538 This can occur when simplifying a divmod insn. We *must* test for this
3539 case here because the code below that splits two independent SETs doesn't
3540 handle this case correctly when it updates the register status.
3542 It's pointless doing this if we originally had two sets, one from
3543 i3, and one from i2. Combining then splitting the parallel results
3544 in the original i2 again plus an invalid insn (which we delete).
3545 The net effect is only to move instructions around, which makes
3546 debug info less accurate.
3548 If the remaining SET came from I2 its destination should not be used
3549 between I2 and I3. See PR82024. */
3554 {
3565 {
3568 }
3577 {
3582 {
3588 }
3589 }
3593 }
3595 /* Is the result of combination a valid instruction? */
3599 /* If we were combining three insns and the result is a simple SET
3600 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3601 insns. There are two ways to do this. It can be split using a
3602 machine-specific method (like when you have an addition of a large
3603 constant) or by combine in the function find_split_point. */
3607 {
3611 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3612 use I2DEST as a scratch register will help. In the latter case,
3613 convert I2DEST to the mode of the source of NEWPAT if we can. */
3617 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3618 inputs of NEWPAT. */
3620 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3621 possible to try that as a scratch reg. This would require adding
3622 more code to make it work though. */
3625 {
3628 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3629 (temporarily, until we are committed to this instruction
3630 combination) does not work: for example, any call to nonzero_bits
3631 on the register (from a splitter in the MD file, for example)
3632 will get the old information, which is invalid.
3634 Since nowadays we can create registers during combine just fine,
3635 we should just create a new one here, not reuse i2dest. */
3637 /* First try to split using the original register as a
3638 scratch register. */
3642 i2dest)));
3645 /* If that didn't work, try changing the mode of I2DEST if
3646 we can. */
3651 {
3653 rtx ni2dest;
3657 else
3658 {
3661 }
3663 parallel = (gen_rtx_PARALLEL
3667 ni2dest))));
3672 {
3680 }
3681 }
3684 }
3686 /* If recog_for_combine has discarded clobbers, try to use them
3687 again for the split. */
3689 {
3692 }
3695 {
3700 }
3704 {
3714 /* If I2 or I3 has multiple SETs, we won't know how to track
3715 register status, so don't use these insns. If I2's destination
3716 is used between I2 and I3, we also can't use these insns. */
3726 /* It is possible that both insns now set the destination of I3.
3727 If so, we must show an extra use of it. */
3730 {
3749 }
3750 }
3752 /* If we can split it and use I2DEST, go ahead and see if that
3753 helps things be recognized. Verify that none of the registers
3754 are set between I2 and I3. */
3758 /* We need I2DEST in the proper mode. If it is a hard register
3759 or the only use of a pseudo, we can change its mode.
3760 Make sure we don't change a hard register to have a mode that
3761 isn't valid for it, or change the number of registers. */
3768 /* We can't overwrite I2DEST if its value is still used by
3769 NEWPAT. */
3771 {
3780 /* *SPLIT may be part of I2SRC, so make sure we have the
3781 original expression around for later debug processing.
3782 We should not need I2SRC any more in other cases. */
3785 else
3788 /* Get NEWDEST as a register in the proper mode. We have already
3789 validated that we can do this. */
3791 {
3794 else
3795 {
3798 }
3799 }
3801 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3802 an ASHIFT. This can occur if it was inside a PLUS and hence
3803 appeared to be a memory address. This is a kludge. */
3808 {
3812 /* Update split_code because we may not have a multiply
3813 anymore. */
3815 }
3817 /* Similarly for (plus (mult FOO (const_int pow2))). */
3823 {
3828 i_rtx));
3829 /* Update split_code because we may not have a multiply
3830 anymore. */
3832 }
3834 #ifdef INSN_SCHEDULING
3835 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3836 be written as a ZERO_EXTEND. */
3838 {
3839 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3840 what it really is. */
3845 else
3848 }
3849 #endif
3851 /* Attempt to split binary operators using arithmetic identities. */
3855 {
3862 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3864 {
3869 }
3870 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3877 {
3883 /* Split both "((X op Y) op X) op Y" and
3884 "((X op Y) op Y) op X" as "T op T" where T is
3885 "X op Y". */
3888 {
3893 }
3894 /* Split "((X op X) op Y) op Y)" as "T op T" where
3895 T is "X op Y". */
3897 {
3903 }
3904 }
3905 }
3908 {
3911 }
3915 /* recog_for_combine might have added CLOBBERs to newi2pat.
3916 Make sure NEWPAT does not depend on the clobbered regs. */
3920 {
3923 {
3926 }
3927 }
3929 /* If the split point was a MULT and we didn't have one before,
3930 don't use one now. */
3933 }
3934 }
3936 /* Check for a case where we loaded from memory in a narrow mode and
3937 then sign extended it, but we need both registers. In that case,
3938 we have a PARALLEL with both loads from the same memory location.
3939 We can split this into a load from memory followed by a register-register
3940 copy. This saves at least one insn, more if register allocation can
3941 eliminate the copy.
3943 We cannot do this if the destination of the first assignment is a
3944 condition code register or cc0. We eliminate this case by making sure
3945 the SET_DEST and SET_SRC have the same mode.
3947 We cannot do this if the destination of the second assignment is
3948 a register that we have already assumed is zero-extended. Similarly
3949 for a SUBREG of such a register. */
3968 BITS_PER_WORD)
3970 HOST_BITS_PER_INT)
3978 BITS_PER_WORD)
3980 HOST_BITS_PER_INT)
3987 {
3988 rtx ni2dest;
4002 }
4004 /* Similarly, check for a case where we have a PARALLEL of two independent
4005 SETs but we started with three insns. In this case, we can do the sets
4006 as two separate insns. This case occurs when some SET allows two
4007 other insns to combine, but the destination of that SET is still live.
4009 Also do this if we started with two insns and (at least) one of the
4010 resulting sets is a noop; this noop will be deleted later. */
4029 {
4033 /* Normally, it doesn't matter which of the two is done first,
4034 but the one that references cc0 can't be the second, and
4035 one which uses any regs/memory set in between i2 and i3 can't
4036 be first. The PARALLEL might also have been pre-existing in i3,
4037 so we need to make sure that we won't wrongly hoist a SET to i2
4038 that would conflict with a death note present in there. */
4046 /* If I3 is a jump, ensure that set0 is a jump so that
4047 we do not create invalid RTL. */
4049 )
4050 {
4053 }
4061 /* If I3 is a jump, ensure that set1 is a jump so that
4062 we do not create invalid RTL. */
4064 )
4065 {
4068 }
4069 else
4070 {
4073 }
4078 {
4079 /* recog_for_combine might have added CLOBBERs to newi2pat.
4080 Make sure NEWPAT does not depend on the clobbered regs. */
4082 {
4085 {
4088 {
4091 }
4092 }
4093 }
4099 }
4100 }
4102 /* If it still isn't recognized, fail and change things back the way they
4103 were. */
4105 /* Is the result a reasonable ASM_OPERANDS? */
4107 {
4110 }
4112 /* If we had to change another insn, make sure it is valid also. */
4114 {
4122 {
4125 }
4126 }
4128 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4129 they are adjacent to each other or not. */
4131 {
4135 {
4138 }
4139 }
4141 /* Only allow this combination if insn_cost reports that the
4142 replacement instructions are cheaper than the originals. */
4144 {
4147 }
4150 {
4155 {
4160 /* Temporarily revert mode back. */
4164 {
4165 /* If we used i2dest as a scratch register with a
4166 different mode, substitute it for the original
4167 i2src while its original mode is temporarily
4168 restored, and then clear i2scratch so that we don't
4169 do it again later. */
4171 this_basic_block);
4173 /* Put back the new mode. */
4175 }
4176 else
4177 {
4182 {
4185 }
4186 else
4187 {
4194 }
4196 /* We're dealing with a reg that changed mode but not
4197 meaning, so we want to turn it into a subreg for
4198 the new mode. However, because of REG sharing and
4199 because its mode had already changed, we have to do
4200 it in two steps. First, replace any debug uses of
4201 reg, with its original mode temporarily restored,
4202 with this copy we have created; then, replace the
4203 copy with the SUBREG of the original shared reg,
4204 once again changed to the new mode. */
4206 this_basic_block);
4210 this_basic_block);
4211 }
4212 }
4213 }
4215 /* If we will be able to accept this, we have made a
4216 change to the destination of I3. This requires us to
4217 do a few adjustments. */
4220 {
4223 }
4225 /* We now know that we can do this combination. Merge the insns and
4226 update the status of registers and LOG_LINKS. */
4229 {
4234 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4235 ensure that they are still valid. Then add any non-duplicate
4236 notes added by recog_for_combine. */
4238 {
4247 /* Simply drop equal note since it may be no longer valid
4248 for other_insn. It may be possible to record that CC
4249 register is changed and only discard those notes, but
4250 in practice it's unnecessary complication and doesn't
4251 give any meaningful improvement.
4253 See PR78559. */
4257 }
4261 NULL_RTX);
4262 }
4265 {
4266 /* I3 now uses what used to be its destination and which is now
4267 I2's destination. This requires us to do a few adjustments. */
4270 }
4273 {
4274 /* We might need a LOG_LINK from I3 to I2. But then we used to
4275 have one, so we still will.
4277 However, some later insn might be using I2's dest and have
4278 a LOG_LINK pointing at I3. We should change it to point at
4279 I2 instead. */
4281 /* newi2pat is usually a SET here; however, recog_for_combine might
4282 have added some clobbers. */
4287 /* It can only be a SET of a REG or of a SUBREG of a REG. */
4292 !done
4293 && insn
4297 {
4301 {
4305 }
4306 }
4307 }
4309 {
4314 /* Compute which registers we expect to eliminate. newi2pat may be setting
4315 either i3dest or i2dest, so we must check it. */
4318 || !i2dest_killed
4320 /* For i1, we need to compute both local elimination and global
4321 elimination information with respect to newi2pat because i1dest
4322 may be the same as i3dest, in which case newi2pat may be setting
4323 i1dest. Global information is used when distributing REG_DEAD
4324 note for i2 and i3, in which case it does matter if newi2pat sets
4325 i1dest or not.
4327 Local information is used when distributing REG_DEAD note for i1,
4328 in which case it doesn't matter if newi2pat sets i1dest or not.
4329 See PR62151, if we have four insns combination:
4330 i0: r0 <- i0src
4331 i1: r1 <- i1src (using r0)
4332 REG_DEAD (r0)
4333 i2: r0 <- i2src (using r1)
4334 i3: r3 <- i3src (using r0)
4335 ix: using r0
4336 From i1's point of view, r0 is eliminated, no matter if it is set
4337 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4338 should be discarded.
4340 Note local information only affects cases in forms like "I1->I2->I3",
4341 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4342 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4343 i0dest anyway. */
4345 || !i1dest_killed
4350 /* Same case as i1. */
4357 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4358 clear them. */
4366 /* Ensure that we do not have something that should not be shared but
4367 occurs multiple times in the new insns. Check this by first
4368 resetting all the `used' flags and then copying anything is shared. */
4392 {
4395 {
4397 {
4398 /* I2SRC must still be meaningful at this point. Some
4399 splitting operations can invalidate I2SRC, but those
4400 operations do not apply to calls. */
4404 }
4411 }
4412 }
4417 /* We had one special case above where I2 had more than one set and
4418 we replaced a destination of one of those sets with the destination
4419 of I3. In that case, we have to update LOG_LINKS of insns later
4420 in this basic block. Note that this (expensive) case is rare.
4422 Also, in this case, we must pretend that all REG_NOTEs for I2
4423 actually came from I3, so that REG_UNUSED notes from I2 will be
4424 properly handled. */
4427 {
4436 temp_insn
4446 {
4451 }
4452 else
4455 }
4463 {
4466 this_basic_block);
4469 }
4470 else
4471 {
4474 this_basic_block);
4476 }
4479 {
4484 this_basic_block);
4486 }
4489 {
4494 this_basic_block);
4496 }
4498 /* Get death notes for everything that is now used in either I3 or
4499 I2 and used to die in a previous insn. If we built two new
4500 patterns, move from I1 to I2 then I2 to I3 so that we get the
4501 proper movement on registers that I2 modifies. */
4507 else
4513 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4530 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4531 know these are REG_UNUSED and want them to go to the desired insn,
4532 so we always pass it as i3. */
4536 NULL_RTX);
4540 NULL_RTX);
4542 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4543 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4544 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4545 in that case, it might delete I2. Similarly for I2 and I1.
4546 Show an additional death due to the REG_DEAD note we make here. If
4547 we discard it in distribute_notes, we will decrement it again. */
4550 {
4555 else
4558 }
4561 {
4566 else
4569 }
4572 {
4577 else
4580 }
4583 {
4588 else
4591 }
4599 {
4604 /* The insn that used to set this register doesn't exist, and
4605 this life of the register may not exist either. See if one of
4606 I3's links points to an insn that sets I2DEST. If it does,
4607 that is now the last known value for I2DEST. If we don't update
4608 this and I2 set the register to a value that depended on its old
4609 contents, we will get confused. If this insn is used, thing
4610 will be set correctly in combine_instructions. */
4618 /* If the reg formerly set in I2 died only once and that was in I3,
4619 zero its use count so it won't make `reload' do any work. */
4622 && ! i2dest_in_i2src
4625 }
4628 {
4641 && ! i1dest_in_i1src
4644 }
4647 {
4660 && ! i0dest_in_i0src
4663 }
4665 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4666 been made to this insn. The order is important, because newi2pat
4667 can affect nonzero_bits of newpat. */
4671 }
4674 {
4676 {
4679 }
4681 }
4684 {
4686 {
4689 }
4691 }
4694 {
4696 {
4699 }
4701 }
4704 {
4706 {
4709 }
4711 }
4714 {
4716 {
4719 }
4721 }
4723 /* Set new_direct_jump_p if a new return or simple jump instruction
4724 has been created. Adjust the CFG accordingly. */
4726 {
4730 }
4735 {
4738 }
4742 {
4748 }
4753 {
4759 }
4761 /* A noop might also need cleaning up of CFG, if it comes from the
4762 simplification of a jump. */
4767 {
4770 }
4777 {
4780 }
4782 combine_successes++;
4792 }
4793 \f
4794 /* Get a marker for undoing to the current state. */
4798 {
4800 }
4802 /* Undo the modifications up to the marker. */
4804 static void
4806 {
4810 {
4815 {
4830 }
4834 }
4837 }
4839 /* Undo all the modifications recorded in undobuf. */
4841 static void
4843 {
4845 }
4847 /* We've committed to accepting the changes we made. Move all
4848 of the undos to the free list. */
4850 static void
4852 {
4856 {
4860 }
4862 }
4863 \f
4864 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4865 where we have an arithmetic expression and return that point. LOC will
4866 be inside INSN.
4868 try_combine will call this function to see if an insn can be split into
4869 two insns. */
4873 {
4883 /* First special-case some codes. */
4885 {
4887 #ifdef INSN_SCHEDULING
4888 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4889 point. */
4892 #endif
4896 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4897 using LO_SUM and HIGH. */
4900 {
4908 }
4910 /* If we have a PLUS whose second operand is a constant and the
4911 address is not valid, perhaps will can split it up using
4912 the machine-specific way to split large constants. We use
4913 the first pseudo-reg (one of the virtual regs) as a placeholder;
4914 it will not remain in the result. */
4919 {
4922 subst_insn);
4924 /* This should have produced two insns, each of which sets our
4925 placeholder. If the source of the second is a valid address,
4926 we can make put both sources together and make a split point
4927 in the middle. */
4940 && memory_address_addr_space_p
4943 {
4947 /* Replace the placeholder in SRC2 with SRC1. If we can
4948 find where in SRC2 it was placed, that can become our
4949 split point and we can replace this address with SRC2.
4950 Just try two obvious places. */
4961 {
4964 }
4965 }
4967 /* If that didn't work, perhaps the first operand is complex and
4968 needs to be computed separately, so make a split point there.
4969 This will occur on machines that just support REG + CONST
4970 and have a constant moved through some previous computation. */
4976 }
4978 /* If we have a PLUS whose first operand is complex, try computing it
4979 separately by making a split there. */
4990 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4991 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4992 we need to put the operand into a register. So split at that
4993 point. */
5003 /* See if we can split SET_SRC as it stands. */
5008 /* See if we can split SET_DEST as it stands. */
5013 /* See if this is a bitfield assignment with everything constant. If
5014 so, this is an IOR of an AND, so split it into that. */
5026 {
5031 unsigned HOST_WIDE_INT mask
5033 rtx or_mask;
5042 else
5043 {
5049 or_mask));
5050 }
5057 }
5059 /* Otherwise, see if this is an operation that we can split into two.
5060 If so, try to split that. */
5064 {
5066 /* If we are AND'ing with a large constant that is only a single
5067 bit and the result is only being used in a context where we
5068 need to know if it is zero or nonzero, replace it with a bit
5069 extraction. This will avoid the large constant, which might
5070 have taken more than one insn to make. If the constant were
5071 not a valid argument to the AND but took only one insn to make,
5072 this is no worse, but if it took more than one insn, it will
5073 be better. */
5083 {
5088 {
5091 }
5092 }
5096 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5097 is known to be on, this can be converted into a NEG of a shift. */
5103 {
5110 pos_rtx)));
5115 }
5121 /* We can't optimize if either mode is a partial integer
5122 mode as we don't know how many bits are significant
5123 in those modes. */
5139 {
5147 }
5152 }
5158 {
5159 /* For unsigned, we have a choice of a shift followed by an
5160 AND or two shifts. Use two shifts for field sizes where the
5161 constant might be too large. We assume here that we can
5162 always at least get 8-bit constants in an AND insn, which is
5163 true for every current RISC. */
5166 {
5167 unsigned HOST_WIDE_INT mask
5172 gen_rtx_LSHIFTRT
5179 }
5180 else
5181 {
5185 gen_rtx_fmt_ee
5195 }
5196 }
5198 /* See if this is a simple operation with a constant as the second
5199 operand. It might be that this constant is out of range and hence
5200 could be used as a split point. */
5208 /* Finally, see if this is a simple operation with its first operand
5209 not in a register. The operation might require this operand in a
5210 register, so return it as a split point. We can always do this
5211 because if the first operand were another operation, we would have
5212 already found it as a split point. */
5221 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5222 it is better to write this as (not (ior A B)) so we can split it.
5223 Similarly for IOR. */
5225 {
5233 }
5235 /* Many RISC machines have a large set of logical insns. If the
5236 second operand is a NOT, put it first so we will try to split the
5237 other operand first. */
5239 {
5243 }
5248 /* Canonicalization can produce (minus A (mult B C)), where C is a
5249 constant. It may be better to try splitting (plus (mult B -C) A)
5250 instead if this isn't a multiply by a power of two. */
5254 {
5262 mode)),
5265 }
5267 /* Split at a multiply-accumulate instruction. However if this is
5268 the SET_SRC, we likely do not have such an instruction and it's
5269 worthless to try this split. */
5278 }
5280 /* Otherwise, select our actions depending on our rtx class. */
5282 {
5288 /* fall through */
5296 /* fall through */
5298 /* Some machines have (and (shift ...) ...) insns. If X is not
5299 an AND, but XEXP (X, 0) is, use it as our split point. */
5309 /* Otherwise, we don't have a split point. */
5311 }
5312 }
5313 \f
5314 /* Throughout X, replace FROM with TO, and return the result.
5315 The result is TO if X is FROM;
5316 otherwise the result is X, but its contents may have been modified.
5317 If they were modified, a record was made in undobuf so that
5318 undo_all will (among other things) return X to its original state.
5320 If the number of changes necessary is too much to record to undo,
5321 the excess changes are not made, so the result is invalid.
5322 The changes already made can still be undone.
5323 undobuf.num_undo is incremented for such changes, so by testing that
5324 the caller can tell whether the result is valid.
5326 `n_occurrences' is incremented each time FROM is replaced.
5328 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5330 IN_COND is nonzero if we are at the top level of a condition.
5332 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5333 by copying if `n_occurrences' is nonzero. */
5335 static rtx
5337 {
5342 rtx new_rtx;
5344 /* Two expressions are equal if they are identical copies of a shared
5345 RTX or if they are both registers with the same register number
5346 and mode. */
5348 #define COMBINE_RTX_EQUAL_P(X,Y) \
5349 ((X) == (Y) \
5350 || (REG_P (X) && REG_P (Y) \
5351 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5353 /* Do not substitute into clobbers of regs -- this will never result in
5354 valid RTL. */
5359 {
5360 n_occurrences++;
5362 }
5364 /* If X and FROM are the same register but different modes, they
5365 will not have been seen as equal above. However, the log links code
5366 will make a LOG_LINKS entry for that case. If we do nothing, we
5367 will try to rerecognize our original insn and, when it succeeds,
5368 we will delete the feeding insn, which is incorrect.
5370 So force this insn not to match in this (rare) case. */
5375 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5376 of which may contain things that can be combined. */
5380 /* It is possible to have a subexpression appear twice in the insn.
5381 Suppose that FROM is a register that appears within TO.
5382 Then, after that subexpression has been scanned once by `subst',
5383 the second time it is scanned, TO may be found. If we were
5384 to scan TO here, we would find FROM within it and create a
5385 self-referent rtl structure which is completely wrong. */
5389 /* Parallel asm_operands need special attention because all of the
5390 inputs are shared across the arms. Furthermore, unsharing the
5391 rtl results in recognition failures. Failure to handle this case
5392 specially can result in circular rtl.
5394 Solve this by doing a normal pass across the first entry of the
5395 parallel, and only processing the SET_DESTs of the subsequent
5396 entries. Ug. */
5401 {
5404 /* If this substitution failed, this whole thing fails. */
5412 {
5418 {
5421 /* If this substitution failed, this whole thing fails. */
5427 }
5428 }
5429 }
5430 else
5431 {
5435 /* We don't need to process a SET_DEST that is a register, CC0,
5436 or PC, so set up to skip this common case. All other cases
5437 where we want to suppress replacing something inside a
5438 SET_SRC are handled via the IN_DEST operand. */
5445 /* Trying to simplify the operands of a widening MULT is not likely
5446 to create RTL matching a machine insn. */
5458 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5459 constant. */
5464 {
5466 {
5469 {
5471 {
5474 n_occurrences++;
5475 }
5476 else
5477 {
5479 unique_copy);
5481 /* If this substitution failed, this whole thing
5482 fails. */
5486 }
5489 }
5490 }
5492 {
5493 /* If this is a register being set, ignore it. */
5500 ;
5503 {
5504 /* In general, don't install a subreg involving two
5505 modes not tieable. It can worsen register
5506 allocation, and can even make invalid reload
5507 insns, since the reg inside may need to be copied
5508 from in the outside mode, and that may be invalid
5509 if it is an fp reg copied in integer mode.
5511 We allow two exceptions to this: It is valid if
5512 it is inside another SUBREG and the mode of that
5513 SUBREG and the mode of the inside of TO is
5514 tieable and it is valid if X is a SET that copies
5515 FROM to CC0. */
5523 && (!HAVE_cc0
5538 n_occurrences++;
5539 }
5540 else
5541 /* If we are in a SET_DEST, suppress most cases unless we
5542 have gone inside a MEM, in which case we want to
5543 simplify the address. We assume here that things that
5544 are actually part of the destination have their inner
5545 parts in the first expression. This is true for SUBREG,
5546 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5547 things aside from REG and MEM that should appear in a
5548 SET_DEST. */
5550 (((in_dest
5556 unique_copy);
5558 /* If we found that we will have to reject this combination,
5559 indicate that by returning the CLOBBER ourselves, rather than
5560 an expression containing it. This will speed things up as
5561 well as prevent accidents where two CLOBBERs are considered
5562 to be equal, thus producing an incorrect simplification. */
5568 {
5576 }
5581 {
5583 new_rtx,
5587 }
5588 else
5590 }
5591 }
5592 }
5594 /* Check if we are loading something from the constant pool via float
5595 extension; in this case we would undo compress_float_constant
5596 optimization and degenerate constant load to an immediate value. */
5600 {
5604 }
5606 /* Try to simplify X. If the simplification changed the code, it is likely
5607 that further simplification will help, so loop, but limit the number
5608 of repetitions that will be performed. */
5611 {
5612 /* If X is sufficiently simple, don't bother trying to do anything
5613 with it. */
5622 /* We no longer know the original mode of operand 0 since we
5623 have changed the form of X) */
5625 }
5628 }
5629 \f
5630 /* If X is a commutative operation whose operands are not in the canonical
5631 order, use substitutions to swap them. */
5633 static void
5635 {
5638 {
5642 }
5643 }
5645 /* Simplify X, a piece of RTL. We just operate on the expression at the
5646 outer level; call `subst' to simplify recursively. Return the new
5647 expression.
5649 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5650 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5651 of a condition. */
5653 static rtx
5656 {
5659 scalar_int_mode int_mode;
5660 rtx temp;
5663 /* If this is a commutative operation, put a constant last and a complex
5664 expression first. We don't need to do this for comparisons here. */
5667 /* Try to fold this expression in case we have constants that weren't
5668 present before. */
5671 {
5679 {
5682 {
5686 }
5689 }
5702 }
5705 {
5710 }
5712 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5713 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5714 things. Check for cases where both arms are testing the same
5715 condition.
5717 Don't do anything if all operands are very simple. */
5730 {
5735 /* If everything is a comparison, what we have is highly unlikely
5736 to be simpler, so don't use it. */
5739 /* Similarly, if we end up with one of the expressions the same
5740 as the original, it is certainly not simpler. */
5743 {
5750 /* Simplify the alternative arms; this may collapse the true and
5751 false arms to store-flag values. Be careful to use copy_rtx
5752 here since true_rtx or false_rtx might share RTL with x as a
5753 result of the if_then_else_cond call above. */
5757 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5758 is unlikely to be simpler. */
5761 {
5764 /* Restarting if we generate a store-flag expression will cause
5765 us to loop. Just drop through in this case. */
5767 /* If the result values are STORE_FLAG_VALUE and zero, we can
5768 just make the comparison operation. */
5779 /* Likewise, we can make the negate of a comparison operation
5780 if the result values are - STORE_FLAG_VALUE and zero. */
5788 mode);
5799 mode);
5800 else
5803 mode,
5804 VOIDmode,
5805 cond,
5806 cop1),
5811 }
5812 }
5813 }
5815 /* First see if we can apply the inverse distributive law. */
5818 {
5822 }
5824 /* If CODE is an associative operation not otherwise handled, see if we
5825 can associate some operands. This can win if they are constants or
5826 if they are logically related (i.e. (a & b) & a). */
5832 {
5834 {
5838 rtx inner;
5840 /* Make sure we pass the constant operand if any as the second
5841 one if this is a commutative operation. */
5849 /* For commutative operations, try the other pair if that one
5850 didn't simplify. */
5852 {
5857 }
5861 }
5862 }
5864 /* A little bit of algebraic simplification here. */
5866 {
5868 /* Ensure that our address has any ASHIFTs converted to MULT in case
5869 address-recognizing predicates are called later. */
5878 /* See if this can be moved to simplify_subreg. */
5881 /* Don't call gen_lowpart if the inner mode
5882 is VOIDmode and we cannot simplify it, as SUBREG without
5883 inner mode is invalid. */
5890 {
5891 rtx temp;
5897 /* If op is known to have all lower bits zero, the result is zero. */
5910 }
5912 /* Don't change the mode of the MEM if that would change the meaning
5913 of the address. */
5920 /* Note that we cannot do any narrowing for non-constants since
5921 we might have been counting on using the fact that some bits were
5922 zero. We now do this in the SET. */
5929 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5930 replaced by (lshiftrt X C). This will convert
5931 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5939 /* If X has only a single bit that might be nonzero, say, bit I, convert
5940 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5941 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5942 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5943 or a SUBREG of one since we'd be making the expression more
5944 complex if it was just a register. */
5951 {
5952 rtx temp1 = simplify_shift_const
5958 /* If all we did was surround TEMP with the two shifts, we
5959 haven't improved anything, so don't use it. Otherwise,
5960 we are better off with TEMP1. */
5965 }
5969 /* We can't handle truncation to a partial integer mode here
5970 because we don't know the real bitsize of the partial
5971 integer mode. */
5980 /* We can truncate a constant value and return it. */
5984 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5985 whose value is a comparison can be replaced with a subreg if
5986 STORE_FLAG_VALUE permits. */
5995 /* (const (const X)) can become (const X). Do it this way rather than
5996 returning the inner CONST since CONST can be shared with a
5997 REG_EQUAL note. */
6003 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6004 can add in an offset. find_split_point will split this address up
6005 again if it doesn't match. */
6012 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6013 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6014 bit-field and can be replaced by either a sign_extend or a
6015 sign_extract. The `and' may be a zero_extend and the two
6016 <c>, -<c> constants may be reversed. */
6033 return simplify_shift_const
6040 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6041 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6042 the bitsize of the mode - 1. This allows simplification of
6043 "a = (b & 8) == 0;" */
6050 return simplify_shift_const
6054 const1_rtx),
6058 /* If we are adding two things that have no bits in common, convert
6059 the addition into an IOR. This will often be further simplified,
6060 for example in cases like ((a & 1) + (a & 2)), which can
6061 become a & 3. */
6066 {
6067 /* Try to simplify the expression further. */
6071 /* If we could, great. If not, do not go ahead with the IOR
6072 replacement, since PLUS appears in many special purpose
6073 address arithmetic instructions. */
6081 }
6083 /* Canonicalize x + x into x << 1. */
6092 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6093 (and <foo> (const_int pow2-1)) */
6104 /* If we have (mult (plus A B) C), apply the distributive law and then
6105 the inverse distributive law to see if things simplify. This
6106 occurs mostly in addresses, often when unrolling loops. */
6109 {
6113 }
6115 /* Try simplify a*(b/c) as (a*b)/c. */
6118 {
6124 }
6128 /* If this is a divide by a power of two, treat it as a shift if
6129 its first operand is a shift. */
6149 /* If the first operand is a condition code, we can't do anything
6150 with it. */
6154 {
6162 /* Simplify our comparison, if possible. */
6165 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6166 if only the low-order bit is possibly nonzero in X (such as when
6167 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6168 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6169 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6170 (plus X 1).
6172 Remove any ZERO_EXTRACT we made when thinking this was a
6173 comparison. It may now be simpler to use, e.g., an AND. If a
6174 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6175 the call to make_compound_operation in the SET case.
6177 Don't apply these optimizations if the caller would
6178 prefer a comparison rather than a value.
6179 E.g., for the condition in an IF_THEN_ELSE most targets need
6180 an explicit comparison. */
6183 ;
6201 {
6205 int_mode);
6206 }
6214 {
6218 const1_rtx);
6219 }
6228 {
6231 }
6233 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6234 those above. */
6236 ;
6253 {
6257 int_mode);
6258 }
6267 {
6271 int_mode);
6272 }
6274 /* If X is 0/1, (eq X 0) is X-1. */
6281 {
6284 }
6286 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6287 one bit that might be nonzero, we can convert (ne x 0) to
6288 (ashift x c) where C puts the bit in the sign bit. Remove any
6289 AND with STORE_FLAG_VALUE when we are done, since we are only
6290 going to test the sign bit. */
6298 {
6304 else
6306 }
6308 /* If the code changed, return a whole new comparison.
6309 We also need to avoid using SUBST in cases where
6310 simplify_comparison has widened a comparison with a CONST_INT,
6311 since in that case the wider CONST_INT may fail the sanity
6312 checks in do_SUBST. */
6319 /* Otherwise, keep this operation, but maybe change its operands.
6320 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6323 }
6333 /* If we are processing SET_DEST, we are done. */
6351 /* If this is a shift by a constant amount, simplify it. */
6359 (HOST_WIDE_INT_1U
6368 }
6371 }
6372 \f
6373 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6375 static rtx
6377 {
6384 rtx temp;
6387 rtx reversed;
6390 /* Simplify storing of the truth value. */
6395 /* Also when the truth value has to be reversed. */
6401 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6402 in it is being compared against certain values. Get the true and false
6403 comparisons and see if that says anything about the value of each arm. */
6409 {
6410 HOST_WIDE_INT nzb;
6416 /* If FALSE_CODE is EQ, swap the codes and arms. */
6419 {
6422 }
6424 scalar_int_mode from_mode;
6426 {
6427 /* If we are comparing against zero and the expression being
6428 tested has only a single bit that might be nonzero, that is
6429 its value when it is not equal to zero. Similarly if it is
6430 known to be -1 or 0. */
6434 {
6437 }
6442 {
6445 }
6446 }
6448 /* Now simplify an arm if we know the value of the register in the
6449 branch and it is used in the arm. Be careful due to the potential
6450 of locally-shared RTL. */
6467 }
6469 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6470 reversed, do so to avoid needing two sets of patterns for
6471 subtract-and-branch insns. Similarly if we have a constant in the true
6472 arm, the false arm is the same as the first operand of the comparison, or
6473 the false arm is more complicated than the true arm. */
6486 {
6495 /* It is possible that the conditional has been simplified out. */
6498 }
6500 /* If the two arms are identical, we don't need the comparison. */
6505 /* Convert a == b ? b : a to "a". */
6517 /* Look for cases where we have (abs x) or (neg (abs X)). */
6520 && comparison_p
6527 {
6533 return
6536 mode);
6539 }
6541 /* Look for MIN or MAX. */
6544 && comparison_p
6549 {
6564 }
6566 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6567 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6568 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6569 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6570 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6571 neither 1 or -1, but it isn't worth checking for. */
6574 && comparison_p
6577 {
6593 /* If an identity-zero op is commutative, check whether there
6594 would be a match if we swapped the operands. */
6615 {
6619 }
6632 {
6636 }
6653 {
6657 }
6670 {
6674 }
6677 {
6687 const_true_rtx));
6695 }
6696 }
6698 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6699 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6700 negation of a single bit, we can convert this operation to a shift. We
6701 can actually do this more generally, but it doesn't seem worth it. */
6713 return
6717 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6718 non-zero bit in A is C1. */
6726 {
6732 }
6735 }
6736 \f
6737 /* Simplify X, a SET expression. Return the new expression. */
6739 static rtx
6741 {
6744 machine_mode mode
6748 scalar_int_mode int_mode;
6750 /* (set (pc) (return)) gets written as (return). */
6754 /* Now that we know for sure which bits of SRC we are using, see if we can
6755 simplify the expression for the object knowing that we only need the
6756 low-order bits. */
6759 {
6762 }
6764 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6765 the comparison result and try to simplify it unless we already have used
6766 undobuf.other_insn. */
6774 {
6783 {
6786 {
6789 }
6790 }
6791 else
6799 {
6803 }
6804 else
6805 {
6810 /* Attempt to simplify CC user. */
6812 {
6816 }
6818 /* Convert X into a no-op move. */
6822 }
6824 /* Simplify our comparison, if possible. */
6827 #ifdef SELECT_CC_MODE
6828 /* If this machine has CC modes other than CCmode, check to see if we
6829 need to use a different CC mode here. */
6838 else
6841 /* If the mode changed, we have to change SET_DEST, the mode in the
6842 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6843 a hard register, just build new versions with the proper mode. If it
6844 is a pseudo, we lose unless it is only time we set the pseudo, in
6845 which case we can safely change its mode. */
6847 {
6849 {
6851 rtx new_dest;
6855 else
6856 {
6859 }
6866 }
6867 }
6870 /* If the code changed, we have to build a new comparison in
6871 undobuf.other_insn. */
6873 {
6882 /* If the only change we made was to change an EQ into an NE or
6883 vice versa, OP0 has only one bit that might be nonzero, and OP1
6884 is zero, check if changing the user of the condition code will
6885 produce a valid insn. If it won't, we can keep the original code
6886 in that insn by surrounding our operation with an XOR. */
6893 {
6898 {
6905 }
6906 }
6907 }
6912 /* Don't generate a compare of a CC with 0, just use that CC. */
6914 {
6917 }
6918 /* Otherwise, if we didn't previously have the same COMPARE we
6919 want, create it from scratch. */
6922 {
6925 }
6926 }
6927 else
6928 {
6929 /* Get SET_SRC in a form where we have placed back any
6930 compound expressions. Then do the checks below. */
6933 }
6935 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6936 and X being a REG or (subreg (reg)), we may be able to convert this to
6937 (set (subreg:m2 x) (op)).
6939 We can always do this if M1 is narrower than M2 because that means that
6940 we only care about the low bits of the result.
6942 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6943 perform a narrower operation than requested since the high-order bits will
6944 be undefined. On machine where it is defined, this transformation is safe
6945 as long as M1 and M2 have the same number of words. */
6949 && (known_equal_after_align_up
6952 UNITS_PER_WORD))
6961 {
6964 dest));
6968 }
6970 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6971 in SRC. */
6975 {
6979 /* Here we make sure that we don't have a sign bit on. */
6982 {
6985 }
6986 }
6988 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6989 would require a paradoxical subreg. Replace the subreg with a
6990 zero_extend to avoid the reload that would otherwise be required.
6991 Don't do this unless we have a scalar integer mode, otherwise the
6992 transformation is incorrect. */
6999 {
7004 }
7006 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7007 are comparing an item known to be 0 or -1 against 0, use a logical
7008 operation instead. Check for one of the arms being an IOR of the other
7009 arm with some value. We compute three terms to be IOR'ed together. In
7010 practice, at most two will be nonzero. Then we do the IOR's. */
7018 && (!HAVE_conditional_move
7023 {
7048 int_mode),
7049 false_rtx);
7055 term3));
7058 }
7060 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7061 whole thing fail. */
7066 else
7067 /* Convert this into a field assignment operation, if possible. */
7069 }
7070 \f
7071 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7072 result. */
7074 static rtx
7076 {
7079 scalar_int_mode mode;
7082 {
7084 /* We can call simplify_and_const_int only if we don't lose
7085 any (sign) bits when converting INTVAL (op1) to
7086 "unsigned HOST_WIDE_INT". */
7091 {
7098 }
7100 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7101 apply the distributive law and then the inverse distributive
7102 law to see if things simplify. */
7104 {
7108 }
7110 {
7114 }
7118 /* If we have (ior (and A B) C), apply the distributive law and then
7119 the inverse distributive law to see if things simplify. */
7122 {
7126 }
7129 {
7133 }
7138 }
7141 }
7142 \f
7143 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7144 operations" because they can be replaced with two more basic operations.
7145 ZERO_EXTEND is also considered "compound" because it can be replaced with
7146 an AND operation, which is simpler, though only one operation.
7148 The function expand_compound_operation is called with an rtx expression
7149 and will convert it to the appropriate shifts and AND operations,
7150 simplifying at each stage.
7152 The function make_compound_operation is called to convert an expression
7153 consisting of shifts and ANDs into the equivalent compound expression.
7154 It is the inverse of this function, loosely speaking. */
7156 static rtx
7158 {
7162 rtx tem;
7163 scalar_int_mode inner_mode;
7166 {
7169 /* FALLTHRU */
7171 /* We can't necessarily use a const_int for a multiword mode;
7172 it depends on implicitly extending the value.
7173 Since we don't know the right way to extend it,
7174 we can't tell whether the implicit way is right.
7176 Even for a mode that is no wider than a const_int,
7177 we can't win, because we need to sign extend one of its bits through
7178 the rest of it, and we don't know which bit. */
7182 /* Reject modes that aren't scalar integers because turning vector
7183 or complex modes into shifts causes problems. */
7187 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7188 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7189 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7190 reloaded. If not for that, MEM's would very rarely be safe.
7192 Reject modes bigger than a word, because we might not be able
7193 to reference a two-register group starting with an arbitrary register
7194 (and currently gen_lowpart might crash for a SUBREG). */
7200 /* If the inner object has VOIDmode (the only way this can happen
7201 is if it is an ASM_OPERANDS), we can't do anything since we don't
7202 know how much masking to do. */
7211 /* fall through */
7214 /* If the operand is a CLOBBER, just return it. */
7222 /* Reject modes that aren't scalar integers because turning vector
7223 or complex modes into shifts causes problems. */
7230 /* This should stay within the object being extracted, fail otherwise. */
7241 }
7243 /* We've rejected non-scalar operations by now. */
7246 /* Convert sign extension to zero extension, if we know that the high
7247 bit is not set, as this is easier to optimize. It will be converted
7248 back to cheaper alternative in make_extraction. */
7254 {
7258 /* Make sure this is a profitable operation. */
7265 else
7267 }
7269 /* We can optimize some special cases of ZERO_EXTEND. */
7271 {
7272 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7273 know that the last value didn't have any inappropriate bits
7274 set. */
7282 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7291 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7292 is a comparison and STORE_FLAG_VALUE permits. This is like
7293 the first case, but it works even when MODE is larger
7294 than HOST_WIDE_INT. */
7302 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7311 }
7313 /* If we reach here, we want to return a pair of shifts. The inner
7314 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7315 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7316 logical depending on the value of UNSIGNEDP.
7318 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7319 converted into an AND of a shift.
7321 We must check for the case where the left shift would have a negative
7322 count. This can happen in a case like (x >> 31) & 255 on machines
7323 that can't shift by a constant. On those machines, we would first
7324 combine the shift with the AND to produce a variable-position
7325 extraction. Then the constant of 31 would be substituted in
7326 to produce such a position. */
7330 {
7338 }
7343 pos),
7345 else
7346 /* Any other cases we can't handle. */
7349 /* If we couldn't do this for some reason, return the original
7350 expression. */
7355 }
7356 \f
7357 /* X is a SET which contains an assignment of one object into
7358 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7359 or certain SUBREGS). If possible, convert it into a series of
7360 logical operations.
7362 We half-heartedly support variable positions, but do not at all
7363 support variable lengths. */
7365 static const_rtx
7367 {
7368 rtx inner;
7372 scalar_int_mode compute_mode;
7374 /* Loop until we find something we can't simplify. */
7376 {
7379 {
7385 MAX_MODE_INT);
7386 }
7389 {
7397 /* A constant position should stay within the width of INNER. */
7402 {
7408 /* If position is ADJUST - X, new position is X. */
7410 else
7414 pos);
7415 }
7416 }
7418 /* If the destination is a subreg that overwrites the whole of the inner
7419 register, we can move the subreg to the source. */
7421 /* We need SUBREGs to compute nonzero_bits properly. */
7422 && nonzero_sign_valid
7424 {
7426 gen_lowpart
7430 }
7431 else
7437 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7439 {
7440 /* Don't do anything for vector or complex integral types. */
7444 /* Try to find an integral mode to pun with. */
7450 }
7452 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7456 /* Don't try to compute in too wide unsupported modes. */
7460 /* Now compute the equivalent expression. Make a copy of INNER
7461 for the SET_DEST in case it is a MEM into which we will substitute;
7462 we don't want shared RTL in that case. */
7464 compute_mode);
7468 compute_mode,
7470 compute_mode),
7471 inner);
7476 mask),
7477 pos);
7482 }
7485 }
7486 \f
7487 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7488 it is an RTX that represents the (variable) starting position; otherwise,
7489 POS is the (constant) starting bit position. Both are counted from the LSB.
7491 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7493 IN_DEST is nonzero if this is a reference in the destination of a SET.
7494 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7495 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7496 be used.
7498 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7499 ZERO_EXTRACT should be built even for bits starting at bit 0.
7501 MODE is the desired mode of the result (if IN_DEST == 0).
7503 The result is an RTX for the extraction or NULL_RTX if the target
7504 can't handle it. */
7506 static rtx
7510 {
7511 /* This mode describes the size of the storage area
7512 to fetch the overall value from. Within that, we
7513 ignore the POS lowest bits, etc. */
7515 machine_mode inner_mode;
7516 scalar_int_mode wanted_inner_mode;
7522 HOST_WIDE_INT orig_pos;
7530 /* If trying or potentionally trying to extract
7531 bits outside of is_mode, don't look through
7532 non-paradoxical SUBREGs. See PR82192. */
7535 {
7536 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7537 consider just the QI as the memory to extract from.
7538 The subreg adds or removes high bits; its mode is
7539 irrelevant to the meaning of this extraction,
7540 since POS and LEN count from the lsb. */
7544 }
7549 {
7550 /* We're extracting the least significant bits of an rtx
7551 (ashift X (const_int C)), where LEN > C. Extract the
7552 least significant (LEN - C) bits of X, giving an rtx
7553 whose mode is MODE, then shift it left C times. */
7559 }
7561 /* If trying or potentionally trying to extract
7562 bits outside of is_mode, don't look through
7563 TRUNCATE. See PR82192. */
7570 /* See if this can be done without an extraction. We never can if the
7571 width of the field is not the same as that of some integer mode. For
7572 registers, we can only avoid the extraction if the position is at the
7573 low-order bit and this is either not in the destination or we have the
7574 appropriate STRICT_LOW_PART operation available.
7576 For MEM, we can avoid an extract if the field starts on an appropriate
7577 boundary and we can change the mode of the memory reference. */
7579 scalar_int_mode tmode;
7588 && (! in_dest
7592 && (pos
7595 /* We can't do this if we are widening INNER_MODE (it
7596 may not be aligned, for one thing). */
7602 {
7603 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7604 field. If the original and current mode are the same, we need not
7605 adjust the offset. Otherwise, we do if bytes big endian.
7607 If INNER is not a MEM, get a piece consisting of just the field
7608 of interest (in this case POS % BITS_PER_WORD must be 0). */
7611 {
7612 poly_int64 offset;
7614 /* POS counts from lsb, but make OFFSET count in memory order. */
7618 else
7622 }
7624 {
7626 {
7627 /* We can't call gen_lowpart in a DEST since we
7628 always want a SUBREG (see below) and it would sometimes
7629 return a new hard register. */
7631 {
7632 poly_uint64 offset
7635 /* Avoid creating invalid subregs, for example when
7636 simplifying (x>>32)&255. */
7641 }
7642 else
7644 }
7645 else
7647 }
7648 else
7650 len >= HOST_BITS_PER_WIDE_INT
7651 ? HOST_WIDE_INT_M1U
7654 /* If this extraction is going into the destination of a SET,
7655 make a STRICT_LOW_PART unless we made a MEM. */
7670 /* If we know that no extraneous bits are set, and that the high
7671 bit is not set, convert the extraction to the cheaper of
7672 sign and zero extension, that are equivalent in these cases. */
7678 {
7682 /* Prefer ZERO_EXTENSION, since it gives more information to
7683 backends. */
7688 }
7690 /* Otherwise, sign- or zero-extend unless we already are in the
7691 proper mode. */
7695 }
7697 /* Unless this is a COMPARE or we have a funny memory reference,
7698 don't do anything with zero-extending field extracts starting at
7699 the low-order bit since they are simple AND operations. */
7704 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7705 if the position is not a constant and the length is not 1. In all
7706 other cases, we would only be going outside our object in cases when
7707 an original shift would have been undefined. */
7716 /* If INNER is not from memory, we want it to have the mode of a register
7717 extraction pattern's structure operand, or word_mode if there is no
7718 such pattern. The same applies to extraction_mode and pos_mode
7719 and their respective operands.
7721 For memory, assume that the desired extraction_mode and pos_mode
7722 are the same as for a register operation, since at present we don't
7723 have named patterns for aligned memory structures. */
7728 {
7732 }
7734 /* Never narrow an object, since that might not be safe. */
7742 else
7743 {
7744 /* Be careful not to go beyond the extracted object and maintain the
7745 natural alignment of the memory. */
7750 }
7755 {
7756 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7757 BITS_BIG_ENDIAN style. If position is constant, compute new
7758 position. Otherwise, build subtraction.
7759 Note that POS is relative to the mode of the original argument.
7760 If it's a MEM we need to recompute POS relative to that.
7761 However, if we're extracting from (or inserting into) a register,
7762 we want to recompute POS relative to wanted_inner_mode. */
7771 else
7772 pos_rtx
7775 pos_rtx);
7776 /* POS may be less than 0 now, but we check for that below.
7777 Note that it can only be less than 0 if !MEM_P (inner). */
7778 }
7780 /* If INNER has a wider mode, and this is a constant extraction, try to
7781 make it smaller and adjust the byte to point to the byte containing
7782 the value. */
7785 && ! pos_rtx
7790 {
7793 /* The computations below will be correct if the machine is big
7794 endian in both bits and bytes or little endian in bits and bytes.
7795 If it is mixed, we must adjust. */
7797 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7798 adjust OFFSET to compensate. */
7803 /* We can now move to the desired byte. */
7814 }
7816 /* If INNER is not memory, get it into the proper mode. If we are changing
7817 its mode, POS must be a constant and smaller than the size of the new
7818 mode. */
7820 {
7821 /* On the LHS, don't create paradoxical subregs implicitely truncating
7822 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7825 wanted_inner_mode))
7837 pos_rtx
7839 ? HOST_WIDE_INT_M1U
7843 }
7845 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7846 have to zero extend. Otherwise, we can just use a SUBREG.
7848 We dealt with constant rtxes earlier, so pos_rtx cannot
7849 have VOIDmode at this point. */
7853 {
7857 /* If we know that no extraneous bits are set, and that the high
7858 bit is not set, convert extraction to cheaper one - either
7859 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7860 cases. */
7868 {
7872 /* Prefer ZERO_EXTENSION, since it gives more information to
7873 backends. */
7877 }
7879 }
7881 /* Make POS_RTX unless we already have it and it is correct. If we don't
7882 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7883 be a CONST_INT. */
7890 /* Make the required operation. See if we can use existing rtx. */
7897 }
7898 \f
7899 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7900 can be commuted with any other operations in X. Return X without
7901 that shift if so. */
7903 static rtx
7905 {
7907 rtx tem;
7910 {
7912 /* This is the shift itself. If it is wide enough, we will return
7913 either the value being shifted if the shift count is equal to
7914 COUNT or a shift for the difference. */
7928 /* If we can safely shift this constant and we find the inner shift,
7929 make a new operation. */
7934 {
7938 }
7943 }
7946 }
7947 \f
7948 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7949 level of the expression and MODE is its mode. IN_CODE is as for
7950 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7951 that should be used when recursing on operands of *X_PTR.
7953 There are two possible actions:
7955 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7956 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7958 - Return a new rtx, which the caller returns directly. */
7960 static rtx
7964 {
7972 rtx tem;
7973 scalar_int_mode inner_mode;
7977 {
7980 }
7982 /* Process depending on the code of this operation. If NEW is set
7983 nonzero, it will be returned. */
7986 {
7988 /* Convert shifts by constants into multiplications if inside
7989 an address. */
7993 {
7999 {
8002 }
8005 }
8014 {
8018 }
8021 {
8025 mode));
8027 }
8028 else
8029 {
8032 }
8042 {
8046 }
8049 {
8053 mode));
8055 }
8056 else
8057 {
8061 }
8064 /* If the second operand is not a constant, we can't do anything
8065 with it. */
8069 /* If the constant is a power of two minus one and the first operand
8070 is a logical right shift, make an extraction. */
8073 {
8077 }
8079 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8086 {
8093 /* If we narrowed the mode when dropping the subreg, then we lose. */
8097 /* If that didn't give anything, see if the AND simplifies on
8098 its own. */
8100 {
8104 }
8105 }
8106 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8112 {
8113 /* Apply the distributive law, and then try to make extractions. */
8120 }
8122 /* If we are have (and (rotate X C) M) and C is larger than the number
8123 of bits in M, this is an extraction. */
8129 {
8135 }
8137 /* On machines without logical shifts, if the operand of the AND is
8138 a logical shift and our mask turns off all the propagated sign
8139 bits, we can replace the logical shift with an arithmetic shift. */
8147 {
8157 next_code),
8159 }
8161 /* If the constant is one less than a power of two, this might be
8162 representable by an extraction even if no shift is present.
8163 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8164 we are in a COMPARE. */
8168 next_code),
8171 /* If we are in a comparison and this is an AND with a power of two,
8172 convert this into the appropriate bit extract. */
8178 next_code),
8181 /* If the one operand is a paradoxical subreg of a register or memory and
8182 the constant (limited to the smaller mode) has only zero bits where
8183 the sub expression has known zero bits, this can be expressed as
8184 a zero_extend. */
8186 {
8187 rtx sub;
8195 {
8199 /* original AND constant with all the known zero bits set */
8202 {
8206 }
8207 }
8208 }
8213 /* If the sign bit is known to be zero, replace this with an
8214 arithmetic shift. */
8219 {
8222 next_code),
8225 }
8227 /* fall through */
8233 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8234 this is a SIGN_EXTRACT. */
8241 {
8248 }
8250 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8251 If so, try to merge the shifts into a SIGN_EXTEND. We could
8252 also do this for some cases of SIGN_EXTRACT, but it doesn't
8253 seem worth the effort; the case checked for occurs on Alpha. */
8264 next_code),
8271 /* Call ourselves recursively on the inner expression. If we are
8272 narrowing the object and it has a different RTL code from
8273 what it originally did, do this SUBREG as a force_to_mode. */
8274 {
8278 /* If the SUBREG is masking of a logical right shift,
8279 make an extraction. */
8286 {
8295 }
8297 /* If in_code is COMPARE, it isn't always safe to pass it through
8298 to the recursive make_compound_operation call. */
8302 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8303 is (const_int 0), rather than
8304 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8305 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8306 for non-equality comparisons against 0 is not equivalent
8307 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8317 simplified
8325 {
8326 rtx newer
8329 /* If we have something other than a SUBREG, we might have
8330 done an expansion, so rerun ourselves. */
8334 /* force_to_mode can expand compounds. If it just re-expanded
8335 the compound, use gen_lowpart to convert to the desired
8336 mode. */
8338 /* Likewise if it re-expanded the compound only partially.
8339 This happens for SUBREG of ZERO_EXTRACT if they extract
8340 the same number of bits. */
8349 }
8353 }
8358 }
8364 }
8366 /* Look at the expression rooted at X. Look for expressions
8367 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8368 Form these expressions.
8370 Return the new rtx, usually just X.
8372 Also, for machines like the VAX that don't have logical shift insns,
8373 try to convert logical to arithmetic shift operations in cases where
8374 they are equivalent. This undoes the canonicalizations to logical
8375 shifts done elsewhere.
8377 We try, as much as possible, to re-use rtl expressions to save memory.
8379 IN_CODE says what kind of expression we are processing. Normally, it is
8380 SET. In a memory address it is MEM. When processing the arguments of
8381 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8382 precisely it is an equality comparison against zero. */
8384 rtx
8386 {
8393 /* Select the code to be used in recursive calls. Once we are inside an
8394 address, we stay there. If we have a comparison, set to COMPARE,
8395 but once inside, go back to our default of SET. */
8402 scalar_int_mode mode;
8404 {
8410 }
8412 /* Now recursively process each operand of this operation. We need to
8413 handle ZERO_EXTEND specially so that we don't lose track of the
8414 inner mode. */
8416 {
8424 }
8429 {
8432 }
8435 {
8438 }
8442 }
8443 \f
8444 /* Given M see if it is a value that would select a field of bits
8445 within an item, but not the entire word. Return -1 if not.
8446 Otherwise, return the starting position of the field, where 0 is the
8447 low-order bit.
8449 *PLEN is set to the length of the field. */
8451 static int
8453 {
8454 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8459 /* Now shift off the low-order zero bits and see if we have a
8460 power of two minus 1. */
8468 }
8469 \f
8470 /* If X refers to a register that equals REG in value, replace these
8471 references with REG. */
8472 static rtx
8474 {
8482 {
8515 /* FALLTHRU */
8519 {
8523 else
8525 }
8527 /* fall through */
8534 {
8537 {
8539 {
8542 }
8544 }
8545 }
8547 {
8550 {
8553 {
8555 {
8558 }
8560 }
8561 }
8562 }
8565 }
8568 }
8570 /* Return X converted to MODE. If the value is already truncated to
8571 MODE we can just return a subreg even though in the general case we
8572 would need an explicit truncation. */
8574 static rtx
8576 {
8581 {
8582 /* Bit-cast X into an integer mode. */
8587 }
8590 }
8592 /* See if X can be simplified knowing that we will only refer to it in
8593 MODE and will only refer to those bits that are nonzero in MASK.
8594 If other bits are being computed or if masking operations are done
8595 that select a superset of the bits in MASK, they can sometimes be
8596 ignored.
8598 Return a possibly simplified expression, but always convert X to
8599 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8601 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8602 are all off in X. This is used when X will be complemented, by either
8603 NOT, NEG, or XOR. */
8605 static rtx
8608 {
8611 machine_mode op_mode;
8614 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8615 code below will do the wrong thing since the mode of such an
8616 expression is VOIDmode.
8618 Also do nothing if X is a CLOBBER; this can happen if X was
8619 the return value from a call to gen_lowpart. */
8623 /* We want to perform the operation in its present mode unless we know
8624 that the operation is valid in MODE, in which case we do the operation
8625 in MODE. */
8630 /* It is not valid to do a right-shift in a narrower mode
8631 than the one it came in with. */
8636 /* Truncate MASK to fit OP_MODE. */
8640 /* Determine what bits of X are guaranteed to be (non)zero. */
8643 /* If none of the bits in X are needed, return a zero. */
8647 /* If X is a CONST_INT, return a new one. Do this here since the
8648 test below will fail. */
8650 {
8653 else
8654 {
8657 }
8658 }
8660 /* If X is narrower than MODE and we want all the bits in X's mode, just
8661 get X in the proper mode. */
8666 /* We can ignore the effect of a SUBREG if it narrows the mode or
8667 if the constant masks to zero all the bits the mode doesn't have. */
8671 || (mask
8679 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8680 integer too. */
8686 }
8688 /* Subroutine of force_to_mode that handles cases in which both X and
8689 the result are scalar integers. MODE is the mode of the result,
8690 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8691 is preferred for simplified versions of X. The other arguments
8692 are as for force_to_mode. */
8694 static rtx
8698 {
8704 /* When we have an arithmetic operation, or a shift whose count we
8705 do not know, we need to assume that all bits up to the highest-order
8706 bit in MASK will be needed. This is how we form such a mask. */
8709 else
8714 {
8716 /* If X is a (clobber (const_int)), return it since we know we are
8717 generating something that won't match. */
8730 /* Similarly for a truncate. */
8734 /* If this is an AND with a constant, convert it into an AND
8735 whose constant is the AND of that constant with MASK. If it
8736 remains an AND of MASK, delete it since it is redundant. */
8739 {
8744 /* If X is still an AND, see if it is an AND with a mask that
8745 is just some low-order bits. If so, and it is MASK, we don't
8746 need it. */
8752 /* If it remains an AND, try making another AND with the bits
8753 in the mode mask that aren't in MASK turned on. If the
8754 constant in the AND is wide enough, this might make a
8755 cheaper constant. */
8760 {
8761 unsigned HOST_WIDE_INT cval
8763 rtx y;
8770 }
8773 }
8778 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8779 low-order bits (as in an alignment operation) and FOO is already
8780 aligned to that boundary, mask C1 to that boundary as well.
8781 This may eliminate that PLUS and, later, the AND. */
8783 {
8787 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8788 number, sign extend it. */
8801 }
8803 /* fall through */
8806 /* Substituting into the operands of a widening MULT is not likely to
8807 create RTL matching a machine insn. */
8817 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8818 most significant bit in MASK since carries from those bits will
8819 affect the bits we are interested in. */
8824 /* If X is (minus C Y) where C's least set bit is larger than any bit
8825 in the mask, then we may replace with (neg Y). */
8828 {
8831 }
8833 /* Similarly, if C contains every bit in the fuller_mask, then we may
8834 replace with (not Y). */
8837 {
8840 }
8847 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8848 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8849 operation which may be a bitfield extraction. Ensure that the
8850 constant we form is not wider than the mode of X. */
8862 {
8865 xmode);
8871 }
8873 binop:
8874 /* For most binary operations, just propagate into the operation and
8875 change the mode if we have an operation of that mode. */
8880 /* If we ended up truncating both operands, truncate the result of the
8881 operation instead. */
8884 {
8887 }
8893 {
8896 }
8900 /* For left shifts, do the same, but just for the first operand.
8901 However, we cannot do anything with shifts where we cannot
8902 guarantee that the counts are smaller than the size of the mode
8903 because such a count will have a different meaning in a
8904 wider mode. */
8914 /* If the shift count is a constant and we can do arithmetic in
8915 the mode of the shift, refine which bits we need. Otherwise, use the
8916 conservative form of the mask. */
8922 else
8930 {
8933 }
8937 /* Here we can only do something if the shift count is a constant,
8938 this shift constant is valid for the host, and we can do arithmetic
8939 in OP_MODE. */
8945 {
8949 /* Select the mask of the bits we need for the shift operand. */
8952 /* We can only change the mode of the shift if we can do arithmetic
8953 in the mode of the shift and INNER_MASK is no wider than the
8954 width of X's mode. */
8961 {
8964 }
8965 }
8967 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8968 shift and AND produces only copies of the sign bit (C2 is one less
8969 than a power of two), we can do this with just a shift. */
8973 /* The shift puts one of the sign bit copies in the least significant
8974 bit. */
8979 /* Number of bits left after the shift must be more than the mask
8980 needs. */
8983 /* Must be more sign bit copies than the mask needs. */
8986 {
8990 }
8994 /* If we are just looking for the sign bit, we don't need this shift at
8995 all, even if it has a variable count. */
8999 /* If this is a shift by a constant, get a mask that contains those bits
9000 that are not copies of the sign bit. We then have two cases: If
9001 MASK only includes those bits, this can be a logical shift, which may
9002 allow simplifications. If MASK is a single-bit field not within
9003 those bits, we are requesting a copy of the sign bit and hence can
9004 shift the sign bit to the appropriate location. */
9008 {
9012 /* If the considered data is wider than HOST_WIDE_INT, we can't
9013 represent a mask for all its bits in a single scalar.
9014 But we only care about the lower bits, so calculate these. */
9017 {
9020 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9021 is the number of bits a full-width mask would have set.
9022 We need only shift if these are fewer than nonzero can
9023 hold. If not, we must keep all bits set in nonzero. */
9028 + HOST_BITS_PER_WIDE_INT
9030 }
9031 else
9032 {
9035 }
9038 {
9043 }
9046 {
9047 x = simplify_shift_const
9053 }
9054 }
9056 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9057 even if the shift count isn't a constant. */
9061 shiftrt:
9063 /* If this is a zero- or sign-extension operation that just affects bits
9064 we don't care about, remove it. Be sure the call above returned
9065 something that is still a shift. */
9075 next_select);
9081 /* If the shift count is constant and we can do computations
9082 in the mode of X, compute where the bits we care about are.
9083 Otherwise, we can't do anything. Don't change the mode of
9084 the shift or propagate MODE into the shift, though. */
9087 {
9096 }
9100 /* If we just want the low-order bit, the NEG isn't needed since it
9101 won't change the low-order bit. */
9105 /* We need any bits less significant than the most significant bit in
9106 MASK since carries from those bits will affect the bits we are
9107 interested in. */
9112 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9113 same as the XOR case above. Ensure that the constant we form is not
9114 wider than the mode of X. */
9122 {
9129 }
9131 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9132 use the full mask inside the NOT. */
9135 unop:
9138 next_select));
9140 {
9143 }
9147 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9148 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9149 which is equal to STORE_FLAG_VALUE. */
9161 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9162 written in a narrower mode. We play it safe and do not do so. */
9178 }
9180 /* Ensure we return a value of the proper mode. */
9182 }
9183 \f
9184 /* Return nonzero if X is an expression that has one of two values depending on
9185 whether some other value is zero or nonzero. In that case, we return the
9186 value that is being tested, *PTRUE is set to the value if the rtx being
9187 returned has a nonzero value, and *PFALSE is set to the other alternative.
9189 If we return zero, we set *PTRUE and *PFALSE to X. */
9191 static rtx
9193 {
9198 scalar_int_mode int_mode;
9200 /* If we are comparing a value against zero, we are done. */
9203 {
9207 }
9209 /* If this is a unary operation whose operand has one of two values, apply
9210 our opcode to compute those values. */
9213 {
9218 }
9220 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9221 make can't possibly match and would suppress other optimizations. */
9223 ;
9225 /* If this is a binary operation, see if either side has only one of two
9226 values. If either one does or if both do and they are conditional on
9227 the same value, compute the new true and false values. */
9229 {
9237 {
9238 /* Try to enable a simplification by undoing work done by
9239 if_then_else_cond if it converted a REG into something more
9240 complex. */
9242 {
9245 }
9246 else
9247 {
9250 }
9251 }
9255 {
9256 /* If if_then_else_cond returned zero, then true/false are the
9257 same rtl. We must copy one of them to prevent invalid rtl
9258 sharing. */
9265 {
9270 }
9271 else
9272 {
9275 }
9278 }
9280 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9281 operands is zero when the other is nonzero, and vice-versa,
9282 and STORE_FLAG_VALUE is 1 or -1. */
9288 {
9305 {
9312 const_true_rtx);
9314 }
9315 }
9317 /* Similarly for MULT, AND and UMIN, except that for these the result
9318 is always zero. */
9322 {
9336 {
9339 }
9340 }
9341 }
9344 {
9345 /* If we have IF_THEN_ELSE already, extract the condition and
9346 canonicalize it if it is NE or EQ. */
9352 {
9355 }
9356 else
9358 }
9360 /* If X is a SUBREG, we can narrow both the true and false values
9361 if the inner expression, if there is a condition. */
9365 {
9371 {
9375 }
9376 }
9378 /* If X is a constant, this isn't special and will cause confusions
9379 if we treat it as such. Likewise if it is equivalent to a constant. */
9382 ;
9384 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9385 will be least confusing to the rest of the compiler. */
9387 {
9390 }
9392 /* If X is known to be either 0 or -1, those are the true and
9393 false values when testing X. */
9398 {
9401 }
9403 /* Likewise for 0 or a single bit. */
9406 {
9409 }
9411 /* Otherwise fail; show no condition with true and false values the same. */
9414 }
9415 \f
9416 /* Return the value of expression X given the fact that condition COND
9417 is known to be true when applied to REG as its first operand and VAL
9418 as its second. X is known to not be shared and so can be modified in
9419 place.
9421 We only handle the simplest cases, and specifically those cases that
9422 arise with IF_THEN_ELSE expressions. */
9424 static rtx
9426 {
9434 /* If either operand of the condition is a floating point value,
9435 then we have to avoid collapsing an EQ comparison. */
9445 /* If X is (abs REG) and we know something about REG's relationship
9446 with zero, we may be able to simplify this. */
9450 {
9459 }
9461 /* The only other cases we handle are MIN, MAX, and comparisons if the
9462 operands are the same as REG and VAL. */
9465 {
9467 {
9470 }
9473 {
9475 {
9483 else
9485 }
9488 {
9491 /* Do not reverse the condition when it is NE or EQ.
9492 This is because we cannot conclude anything about
9493 the value of 'SMAX (x, y)' when x is not equal to y,
9494 but we can when x equals y. */
9500 {
9511 }
9512 }
9513 }
9514 }
9516 {
9521 {
9522 /* We must simplify subreg here, before we lose track of the
9523 original inner_mode. */
9528 else
9530 }
9533 }
9534 /* We don't have to handle SIGN_EXTEND here, because even in the
9535 case of replacing something with a modeless CONST_INT, a
9536 CONST_INT is already (supposed to be) a valid sign extension for
9537 its narrower mode, which implies it's already properly
9538 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9539 story is different. */
9541 {
9546 {
9547 /* We must simplify the zero_extend here, before we lose
9548 track of the original inner_mode. */
9553 else
9555 }
9558 }
9562 {
9569 }
9572 }
9573 \f
9574 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9575 assignment as a field assignment. */
9577 static int
9579 {
9581 {
9589 }
9597 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9598 Note that all SUBREGs of MEM are paradoxical; otherwise they
9599 would have been rewritten. */
9612 /* We used to see if get_last_value of X and Y were the same but that's
9613 not correct. In one direction, we'll cause the assignment to have
9614 the wrong destination and in the case, we'll import a register into this
9615 insn that might have already have been dead. So fail if none of the
9616 above cases are true. */
9618 }
9619 \f
9620 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9621 Return that assignment if so.
9623 We only handle the most common cases. */
9625 static rtx
9627 {
9630 rtx assign;
9632 HOST_WIDE_INT c1;
9633 HOST_WIDE_INT pos;
9635 rtx other;
9637 /* All the rules in this function are specific to scalar integers. */
9638 scalar_int_mode mode;
9642 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9643 a clear of a one-bit field. We will have changed it to
9644 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9645 for a SUBREG. */
9651 {
9657 }
9666 {
9673 }
9675 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9676 one-bit field. */
9680 {
9686 }
9688 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9689 SRC is an AND with all bits of that field set, then we can discard
9690 the AND. */
9695 {
9702 else
9705 /* Complete overlap. We can remove the source AND. */
9709 /* Partial overlap. We can reduce the source AND. */
9711 {
9715 }
9716 }
9718 /* The other case we handle is assignments into a constant-position
9719 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9720 a mask that has all one bits except for a group of zero bits and
9721 OTHER is known to have zeros where C1 has ones, this is such an
9722 assignment. Compute the position and length from C1. Shift OTHER
9723 to the appropriate position, force it to the required mode, and
9724 make the extraction. Check for the AND in both operands. */
9726 /* One or more SUBREGs might obscure the constant-position field
9727 assignment. The first one we are likely to encounter is an outer
9728 narrowing SUBREG, which we can just strip for the purposes of
9729 identifying the constant-field assignment. */
9746 /* The second SUBREG that might get in the way is a paradoxical
9747 SUBREG around the first operand of the AND. We want to
9748 pretend the operand is as wide as the destination here. We
9749 do this by adjusting the MEM to wider mode for the sole
9750 purpose of the call to rtx_equal_for_field_assignment_p. Also
9751 note this trick only works for MEMs. */
9763 /* The second SUBREG that might get in the way is a paradoxical
9764 SUBREG around the first operand of the AND. We want to
9765 pretend the operand is as wide as the destination here. We
9766 do this by adjusting the MEM to wider mode for the sole
9767 purpose of the call to rtx_equal_for_field_assignment_p. Also
9768 note this trick only works for MEMs. */
9776 else
9790 /* The mode to use for the source is the mode of the assignment, or of
9791 what is inside a possible STRICT_LOW_PART. */
9795 /* Shift OTHER right POS places and make it the source, restricting it
9796 to the proper length and mode. */
9800 dest);
9802 len >= HOST_BITS_PER_WIDE_INT
9803 ? HOST_WIDE_INT_M1U
9807 /* If SRC is masked by an AND that does not make a difference in
9808 the value being stored, strip it. */
9819 }
9820 \f
9821 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9822 if so. */
9824 static rtx
9826 {
9830 rtx tem;
9832 /* Distributivity is not true for floating point as it can change the
9833 value. So we don't do it unless -funsafe-math-optimizations. */
9838 /* The outer operation can only be one of the following: */
9846 /* If either operand is a primitive we can't do anything, so get out
9847 fast. */
9857 /* See if the inner and outer operations distribute. */
9859 {
9864 /* These all distribute except over PLUS. */
9875 /* This is also a multiply, so it distributes over everything. */
9878 /* This used to handle SUBREG, but this turned out to be counter-
9879 productive, since (subreg (op ...)) usually is not handled by
9880 insn patterns, and this "optimization" therefore transformed
9881 recognizable patterns into unrecognizable ones. Therefore the
9882 SUBREG case was removed from here.
9884 It is possible that distributing SUBREG over arithmetic operations
9885 leads to an intermediate result than can then be optimized further,
9886 e.g. by moving the outer SUBREG to the other side of a SET as done
9887 in simplify_set. This seems to have been the original intent of
9888 handling SUBREGs here.
9890 However, with current GCC this does not appear to actually happen,
9891 at least on major platforms. If some case is found where removing
9892 the SUBREG case here prevents follow-on optimizations, distributing
9893 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9897 }
9899 /* Set LHS and RHS to the inner operands (A and B in the example
9900 above) and set OTHER to the common operand (C in the example).
9901 There is only one way to do this unless the inner operation is
9902 commutative. */
9914 else
9917 /* Form the new inner operation, seeing if it simplifies first. */
9920 /* There is one exception to the general way of distributing:
9921 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9923 {
9926 }
9928 /* We may be able to continuing distributing the result, so call
9929 ourselves recursively on the inner operation before forming the
9930 outer operation, which we return. */
9933 }
9935 /* See if X is of the form (* (+ A B) C), and if so convert to
9936 (+ (* A C) (* B C)) and try to simplify.
9938 Most of the time, this results in no change. However, if some of
9939 the operands are the same or inverses of each other, simplifications
9940 will result.
9942 For example, (and (ior A B) (not B)) can occur as the result of
9943 expanding a bit field assignment. When we apply the distributive
9944 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9945 which then simplifies to (and (A (not B))).
9947 Note that no checks happen on the validity of applying the inverse
9948 distributive law. This is pointless since we can do it in the
9949 few places where this routine is called.
9951 N is the index of the term that is decomposed (the arithmetic operation,
9952 i.e. (+ A B) in the first example above). !N is the index of the term that
9953 is distributed, i.e. of C in the first example above. */
9954 static rtx
9956 {
9957 machine_mode mode;
9961 /* Distributivity is not true for floating point as it can change the
9962 value. So we don't do it unless -funsafe-math-optimizations. */
9979 /* Special case (and (xor B C) (not A)), which is equivalent to
9980 (xor (ior A B) (ior A C)) */
9982 {
9985 }
9988 {
9989 /* Distribute the second term. */
9992 }
9993 else
9994 {
9995 /* Distribute the first term. */
9998 }
10008 }
10009 \f
10010 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10011 in MODE. Return an equivalent form, if different from (and VAROP
10012 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10014 static rtx
10017 {
10020 rtx orig_varop;
10028 /* Simplify VAROP knowing that we will be only looking at some of the
10029 bits in it.
10031 Note by passing in CONSTOP, we guarantee that the bits not set in
10032 CONSTOP are not significant and will never be examined. We must
10033 ensure that is the case by explicitly masking out those bits
10034 before returning. */
10037 /* If VAROP is a CLOBBER, we will fail so return it. */
10041 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10042 to VAROP and return the new constant. */
10046 /* See what bits may be nonzero in VAROP. Unlike the general case of
10047 a call to nonzero_bits, here we don't care about bits outside
10048 MODE. */
10052 /* Turn off all bits in the constant that are known to already be zero.
10053 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10054 which is tested below. */
10058 /* If we don't have any bits left, return zero. */
10062 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10063 a power of two, we can replace this with an ASHIFT. */
10068 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10069 or XOR, then try to apply the distributive law. This may eliminate
10070 operations if either branch can be simplified because of the AND.
10071 It may also make some cases more complex, but those cases probably
10072 won't match a pattern either with or without this. */
10075 {
10077 return
10078 gen_lowpart
10080 apply_distributive_law
10084 constop),
10087 constop))));
10088 }
10090 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10091 the AND and see if one of the operands simplifies to zero. If so, we
10092 may eliminate it. */
10096 {
10105 }
10107 /* Make a SUBREG if necessary. If we can't make it, fail. */
10112 /* If we are only masking insignificant bits, return VAROP. */
10119 /* Otherwise, return an AND. */
10121 }
10124 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10125 in MODE.
10127 Return an equivalent form, if different from X. Otherwise, return X. If
10128 X is zero, we are to always construct the equivalent form. */
10130 static rtx
10133 {
10144 }
10145 \f
10146 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10147 We don't care about bits outside of those defined in MODE.
10149 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10150 a shift, AND, or zero_extract, we can do better. */
10152 static rtx
10154 scalar_int_mode mode,
10156 {
10157 rtx tem;
10160 /* If X is a register whose nonzero bits value is current, use it.
10161 Otherwise, if X is a register whose value we can find, use that
10162 value. Otherwise, use the previously-computed global nonzero bits
10163 for this register. */
10177 && !REGNO_REG_SET_P
10180 {
10181 /* Note that, even if the precision of last_set_mode is lower than that
10182 of mode, record_value_for_reg invoked nonzero_bits on the register
10183 with nonzero_bits_mode (because last_set_mode is necessarily integral
10184 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10185 are all valid, hence in mode too since nonzero_bits_mode is defined
10186 to the largest HWI_COMPUTABLE_MODE_P mode. */
10189 }
10193 {
10198 }
10201 {
10205 /* We don't know anything about the upper bits. */
10209 }
10212 }
10214 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10215 end of X that are known to be equal to the sign bit. X will be used
10216 in mode MODE; the returned value will always be between 1 and the
10217 number of bits in MODE. */
10219 static rtx
10221 scalar_int_mode mode,
10223 {
10224 rtx tem;
10237 && !REGNO_REG_SET_P
10240 {
10243 }
10254 }
10255 \f
10256 /* Return the number of "extended" bits there are in X, when interpreted
10257 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10258 unsigned quantities, this is the number of high-order zero bits.
10259 For signed quantities, this is the number of copies of the sign bit
10260 minus 1. In both case, this function returns the number of "spare"
10261 bits. For example, if two quantities for which this function returns
10262 at least 1 are added, the addition is known not to overflow.
10264 This function will always return 0 unless called during combine, which
10265 implies that it must be called from a define_split. */
10267 unsigned int
10269 {
10273 scalar_int_mode int_mode;
10281 }
10283 /* This function is called from `simplify_shift_const' to merge two
10284 outer operations. Specifically, we have already found that we need
10285 to perform operation *POP0 with constant *PCONST0 at the outermost
10286 position. We would now like to also perform OP1 with constant CONST1
10287 (with *POP0 being done last).
10289 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10290 the resulting operation. *PCOMP_P is set to 1 if we would need to
10291 complement the innermost operand, otherwise it is unchanged.
10293 MODE is the mode in which the operation will be done. No bits outside
10294 the width of this mode matter. It is assumed that the width of this mode
10295 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10297 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10298 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10299 result is simply *PCONST0.
10301 If the resulting operation cannot be expressed as one operation, we
10302 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10304 static int
10305 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10306 {
10313 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10317 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10318 if OP0 is SET. */
10327 {
10329 {
10347 }
10348 }
10350 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10354 /* If the two constants aren't the same, we can't do anything. The
10355 remaining six cases can all be done. */
10359 else
10361 {
10364 /* (a & b) | b == b */
10367 /* (a ^ b) | b == a | b */
10368 {;}
10373 /* (a & b) ^ b == (~a) & b */
10376 /* (a | b) ^ b == a & ~b */
10382 /* (a | b) & b == b */
10385 /* (a ^ b) & b) == (~a) & b */
10390 }
10392 /* Check for NO-OP cases. */
10405 /* ??? Slightly redundant with the above mask, but not entirely.
10406 Moving this above means we'd have to sign-extend the mode mask
10407 for the final test. */
10412 }
10413 \f
10414 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10415 the shift in. The original shift operation CODE is performed on OP in
10416 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10417 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10418 result of the shift is subject to operation OUTER_CODE with operand
10419 OUTER_CONST. */
10421 static scalar_int_mode
10425 {
10428 /* In general we can't perform in wider mode for right shift and rotate. */
10430 {
10432 /* We can still widen if the bits brought in from the left are identical
10433 to the sign bit of ORIG_MODE. */
10441 /* Similarly here but with zero bits. */
10446 /* We can also widen if the bits brought in will be masked off. This
10447 operation is performed in ORIG_MODE. */
10449 {
10455 }
10456 /* fall through */
10466 }
10467 }
10469 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10470 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10471 if we cannot simplify it. Otherwise, return a simplified value.
10473 The shift is normally computed in the widest mode we find in VAROP, as
10474 long as it isn't a different number of words than RESULT_MODE. Exceptions
10475 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10477 static rtx
10480 {
10485 machine_mode shift_mode;
10487 /* We form (outer_op (code varop count) (outer_const)). */
10493 /* Make sure and truncate the "natural" shift on the way in. We don't
10494 want to do this inside the loop as it makes it more difficult to
10495 combine shifts. */
10499 /* If we were given an invalid count, don't do anything except exactly
10500 what was requested. */
10507 /* Unless one of the branches of the `if' in this loop does a `continue',
10508 we will `break' the loop after the `if'. */
10511 {
10512 /* If we have an operand of (clobber (const_int 0)), fail. */
10516 /* Convert ROTATERT to ROTATE. */
10518 {
10522 }
10526 {
10527 /* We only change the modes of scalar shifts. */
10533 }
10535 scalar_int_mode shift_unit_mode
10538 /* Handle cases where the count is greater than the size of the mode
10539 minus 1. For ASHIFT, use the size minus one as the count (this can
10540 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10541 take the count modulo the size. For other shifts, the result is
10542 zero.
10544 Since these shifts are being produced by the compiler by combining
10545 multiple operations, each of which are defined, we know what the
10546 result is supposed to be. */
10549 {
10554 else
10555 {
10556 /* We can't simply return zero because there may be an
10557 outer op. */
10561 }
10562 }
10564 /* If we discovered we had to complement VAROP, leave. Making a NOT
10565 here would cause an infinite loop. */
10570 {
10571 /* An arithmetic right shift of a quantity known to be -1 or 0
10572 is a no-op. */
10576 {
10579 }
10581 /* If we are doing an arithmetic right shift and discarding all but
10582 the sign bit copies, this is equivalent to doing a shift by the
10583 bitsize minus one. Convert it into that shift because it will
10584 often allow other simplifications. */
10591 /* We simplify the tests below and elsewhere by converting
10592 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10593 `make_compound_operation' will convert it to an ASHIFTRT for
10594 those machines (such as VAX) that don't have an LSHIFTRT. */
10599 shift_unit_mode)))
10611 }
10614 {
10621 {
10624 }
10628 /* The following rules apply only to scalars. */
10633 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10634 minus the width of a smaller mode, we can do this with a
10635 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10642 {
10651 }
10655 /* The following rules apply only to scalars. */
10661 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10662 the same number of words as what we've seen so far. Then store
10663 the widest mode in MODE. */
10670 {
10675 }
10679 /* Some machines use MULT instead of ASHIFT because MULT
10680 is cheaper. But it is still better on those machines to
10681 merge two shifts into one. */
10684 {
10689 }
10693 /* Similar, for when divides are cheaper. */
10696 {
10701 }
10705 /* If we are extracting just the sign bit of an arithmetic
10706 right shift, that shift is not needed. However, the sign
10707 bit of a wider mode may be different from what would be
10708 interpreted as the sign bit in a narrower mode, so, if
10709 the result is narrower, don't discard the shift. */
10714 {
10717 }
10719 /* fall through */
10724 /* The following rules apply only to scalars. */
10731 /* Here we have two nested shifts. The result is usually the
10732 AND of a new shift with a mask. We compute the result below. */
10738 {
10742 rtx mask_rtx;
10744 /* We have one common special case. We can't do any merging if
10745 the inner code is an ASHIFTRT of a smaller mode. However, if
10746 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10747 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10748 we can convert it to
10749 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10750 This simplifies certain SIGN_EXTEND operations. */
10754 {
10755 /* C3 has the low-order C1 bits zero. */
10767 }
10769 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10770 than C1 high-order bits equal to the sign bit, we can convert
10771 this to either an ASHIFT or an ASHIFTRT depending on the
10772 two counts.
10774 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10780 {
10784 {
10787 }
10790 }
10792 /* There are some cases we can't do. If CODE is ASHIFTRT,
10793 we can only do this if FIRST_CODE is also ASHIFTRT.
10795 We can't do the case when CODE is ROTATE and FIRST_CODE is
10796 ASHIFTRT.
10798 If the mode of this shift is not the mode of the outer shift,
10799 we can't do this if either shift is a right shift or ROTATE.
10801 Finally, we can't do any of these if the mode is too wide
10802 unless the codes are the same.
10804 Handle the case where the shift codes are the same
10805 first. */
10808 {
10817 }
10828 /* To compute the mask to apply after the shift, shift the
10829 nonzero bits of the inner shift the same way the
10830 outer shift will. */
10833 int_result_mode);
10835 mask_rtx
10839 /* Give up if we can't compute an outer operation to use. */
10847 /* If the shifts are in the same direction, we add the
10848 counts. Otherwise, we subtract them. */
10852 else
10855 /* If COUNT is positive, the new shift is usually CODE,
10856 except for the two exceptions below, in which case it is
10857 FIRST_CODE. If the count is negative, FIRST_CODE should
10858 always be used */
10868 }
10870 /* If we have (A << B << C) for any shift, we can convert this to
10871 (A << C << B). This wins if A is a constant. Only try this if
10872 B is not a constant. */
10877 {
10878 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10879 sure the result will be masked. See PR70222. */
10887 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10888 up outer sign extension (often left and right shift) is
10889 hardly more efficient than the original. See PR70429. */
10896 count_rtx);
10900 }
10904 /* The following rules apply only to scalars. */
10908 /* Make this fit the case below. */
10915 /* The following rules apply only to scalars. */
10921 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10922 with C the size of VAROP - 1 and the shift is logical if
10923 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10924 we have an (le X 0) operation. If we have an arithmetic shift
10925 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10926 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10934 {
10937 const0_rtx);
10943 }
10945 /* If we have (shift (logical)), move the logical to the outside
10946 to allow it to possibly combine with another logical and the
10947 shift to combine with another shift. This also canonicalizes to
10948 what a ZERO_EXTRACT looks like. Also, some machines have
10949 (and (shift)) insns. */
10952 /* We can't do this if we have (ashiftrt (xor)) and the
10953 constant has its sign bit set in shift_unit_mode with
10954 shift_unit_mode wider than result_mode. */
10967 {
10970 }
10972 /* If we can't do that, try to simplify the shift in each arm of the
10973 logical expression, make a new logical expression, and apply
10974 the inverse distributive law. This also can't be done for
10975 (ashiftrt (xor)) where we've widened the shift and the constant
10976 changes the sign bit. */
10982 {
10994 }
10998 /* The following rules apply only to scalars. */
11003 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11004 says that the sign bit can be tested, FOO has mode MODE, C is
11005 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11006 that may be nonzero. */
11016 {
11020 }
11024 /* The following rules apply only to scalars. */
11029 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11030 than the number of bits in the mode is equivalent to A. */
11034 {
11038 }
11040 /* NEG commutes with ASHIFT since it is multiplication. Move the
11041 NEG outside to allow shifts to combine. */
11045 {
11048 }
11052 /* The following rules apply only to scalars. */
11057 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11058 is one less than the number of bits in the mode is
11059 equivalent to (xor A 1). */
11066 {
11070 }
11072 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11073 that might be nonzero in BAR are those being shifted out and those
11074 bits are known zero in FOO, we can replace the PLUS with FOO.
11075 Similarly in the other operand order. This code occurs when
11076 we are computing the size of a variable-size array. */
11083 {
11086 }
11094 {
11097 }
11099 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11110 {
11113 }
11115 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11116 signbit', and attempt to change the PLUS to an XOR and move it to
11117 the outer operation as is done above in the AND/IOR/XOR case
11118 leg for shift(logical). See details in logical handling above
11119 for reasoning in doing so. */
11131 {
11134 }
11139 /* The following rules apply only to scalars. */
11144 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11145 with C the size of VAROP - 1 and the shift is logical if
11146 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11147 we have a (gt X 0) operation. If the shift is arithmetic with
11148 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11149 we have a (neg (gt X 0)) operation. */
11158 {
11161 const0_rtx);
11167 }
11171 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11172 if the truncate does not affect the value. */
11179 {
11183 new_count);
11186 new_count_rtx);
11190 }
11195 }
11198 }
11202 {
11203 /* We only change the modes of scalar shifts. */
11208 }
11210 /* We have now finished analyzing the shift. The result should be
11211 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11212 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11213 to the result of the shift. OUTER_CONST is the relevant constant,
11214 but we must turn off all bits turned off in the shift. */
11222 /* Make a SUBREG if necessary. If we can't make it, fail. */
11227 /* If we have an outer operation and we just made a shift, it is
11228 possible that we could have simplified the shift were it not
11229 for the outer operation. So try to do the simplification
11230 recursively. */
11234 else
11241 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11242 turn off all the bits that the shift would have turned off. */
11244 /* We only change the modes of scalar shifts. */
11248 /* Do the remainder of the processing in RESULT_MODE. */
11251 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11252 operation. */
11257 {
11267 {
11268 /* This means that we have determined that the result is
11269 equivalent to a constant. This should be rare. */
11272 }
11275 else
11278 }
11281 }
11283 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11284 The result of the shift is RESULT_MODE. If we cannot simplify it,
11285 return X or, if it is NULL, synthesize the expression with
11286 simplify_gen_binary. Otherwise, return a simplified value.
11288 The shift is normally computed in the widest mode we find in VAROP, as
11289 long as it isn't a different number of words than RESULT_MODE. Exceptions
11290 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11292 static rtx
11295 {
11306 }
11308 \f
11309 /* A subroutine of recog_for_combine. See there for arguments and
11310 return value. */
11312 static int
11314 {
11316 rtx pat_without_clobbers;
11324 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11325 we use to indicate that something didn't match. If we find such a
11326 thing, force rejection. */
11340 {
11343 else
11346 }
11348 /* If it isn't, there is the possibility that we previously had an insn
11349 that clobbered some register as a side effect, but the combined
11350 insn doesn't need to do that. So try once more without the clobbers
11351 unless this represents an ASM insn. */
11355 {
11360 {
11363 pos++;
11364 }
11374 {
11377 else
11380 }
11381 }
11388 /* Recognize all noop sets, these will be killed by followup pass. */
11392 /* If we had any clobbers to add, make a new pattern than contains
11393 them. Then check to make sure that all of them are dead. */
11395 {
11405 else
11412 {
11417 {
11421 }
11422 }
11424 }
11428 {
11436 /* Allow targets to reject combined insn. */
11438 {
11441 dump_file);
11443 /* Callers expect recog_for_combine to strip
11444 clobbers from the pattern on failure. */
11449 }
11454 }
11460 }
11462 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11463 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11464 Return whether anything was so changed. */
11466 static bool
11468 {
11474 {
11486 {
11496 else
11500 {
11506 }
11507 }
11513 {
11518 {
11524 }
11525 }
11530 {
11534 }
11535 else
11541 {
11544 }
11548 }
11555 scalar_int_mode mode;
11561 {
11575 else
11583 }
11586 }
11588 /* Like recog, but we receive the address of a pointer to a new pattern.
11589 We try to match the rtx that the pointer points to.
11590 If that fails, we may try to modify or replace the pattern,
11591 storing the replacement into the same pointer object.
11593 Modifications include deletion or addition of CLOBBERs. If the
11594 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11595 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11596 (and undo if that fails).
11598 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11599 the CLOBBERs are placed.
11601 The value is the final insn code from the pattern ultimately matched,
11602 or -1. */
11604 static int
11606 {
11618 {
11621 {
11625 }
11626 }
11629 {
11634 }
11637 }
11638 \f
11639 /* Like gen_lowpart_general but for use by combine. In combine it
11640 is not possible to create any new pseudoregs. However, it is
11641 safe to create invalid memory addresses, because combine will
11642 try to recognize them and all they will do is make the combine
11643 attempt fail.
11645 If for some reason this cannot do its job, an rtx
11646 (clobber (const_int 0)) is returned.
11647 An insn containing that will not be recognized. */
11649 static rtx
11651 {
11653 rtx result;
11658 /* We can only support MODE being wider than a word if X is a
11659 constant integer or has a mode the same size. */
11665 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11666 won't know what to do. So we will strip off the SUBREG here and
11667 process normally. */
11669 {
11672 /* For use in case we fall down into the address adjustments
11673 further below, we need to adjust the known mode and size of
11674 x; imode and isize, since we just adjusted x. */
11679 }
11687 {
11688 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11689 address. */
11694 /* If we want to refer to something bigger than the original memref,
11695 generate a paradoxical subreg instead. That will force a reload
11696 of the original memref X. */
11702 }
11704 /* If X is a comparison operator, rewrite it in a new mode. This
11705 probably won't match, but may allow further simplifications. */
11709 /* If we couldn't simplify X any other way, just enclose it in a
11710 SUBREG. Normally, this SUBREG won't match, but some patterns may
11711 include an explicit SUBREG or we may simplify it further in combine. */
11712 else
11713 {
11714 rtx res;
11717 {
11722 }
11726 }
11728 fail:
11730 }
11731 \f
11732 /* Try to simplify a comparison between OP0 and a constant OP1,
11733 where CODE is the comparison code that will be tested, into a
11734 (CODE OP0 const0_rtx) form.
11736 The result is a possibly different comparison code to use.
11737 *POP1 may be updated. */
11739 static enum rtx_code
11742 {
11743 scalar_int_mode int_mode;
11746 /* Get the constant we are comparing against and turn off all bits
11747 not on in our mode. */
11751 /* If we are comparing against a constant power of two and the value
11752 being compared can only have that single bit nonzero (e.g., it was
11753 `and'ed with that bit), we can replace this with a comparison
11754 with zero. */
11763 {
11766 }
11768 /* Similarly, if we are comparing a value known to be either -1 or
11769 0 with -1, change it to the opposite comparison against zero. */
11775 {
11778 }
11780 /* Do some canonicalizations based on the comparison code. We prefer
11781 comparisons against zero and then prefer equality comparisons.
11782 If we can reduce the size of a constant, we will do that too. */
11784 {
11786 /* < C is equivalent to <= (C - 1) */
11788 {
11791 /* ... fall through to LE case below. */
11793 }
11794 else
11798 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11800 {
11803 }
11805 /* If we are doing a <= 0 comparison on a value known to have
11806 a zero sign bit, we can replace this with == 0. */
11817 /* >= C is equivalent to > (C - 1). */
11819 {
11822 /* ... fall through to GT below. */
11824 }
11825 else
11829 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11831 {
11834 }
11836 /* If we are doing a > 0 comparison on a value known to have
11837 a zero sign bit, we can replace this with != 0. */
11848 /* < C is equivalent to <= (C - 1). */
11850 {
11853 /* ... fall through ... */
11855 }
11856 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11861 {
11865 }
11866 else
11870 /* unsigned <= 0 is equivalent to == 0 */
11873 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11877 == ((HOST_WIDE_INT_1U
11879 {
11882 }
11886 /* >= C is equivalent to > (C - 1). */
11888 {
11891 /* ... fall through ... */
11893 }
11895 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11900 {
11904 }
11905 else
11909 /* unsigned > 0 is equivalent to != 0 */
11912 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11916 == (HOST_WIDE_INT_1U
11918 {
11921 }
11926 }
11930 }
11931 \f
11932 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11933 comparison code that will be tested.
11935 The result is a possibly different comparison code to use. *POP0 and
11936 *POP1 may be updated.
11938 It is possible that we might detect that a comparison is either always
11939 true or always false. However, we do not perform general constant
11940 folding in combine, so this knowledge isn't useful. Such tautologies
11941 should have been detected earlier. Hence we ignore all such cases. */
11943 static enum rtx_code
11945 {
11951 opt_scalar_int_mode tmode_iter;
11953 /* Try a few ways of applying the same transformation to both operands. */
11955 {
11956 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11957 so check specially. */
11976 {
11979 }
11981 /* If both operands are the same constant shift, see if we can ignore the
11982 shift. We can if the shift is a rotate or if the bits shifted out of
11983 this shift are known to be zero for both inputs and if the type of
11984 comparison is compatible with the shift. */
11997 {
12010 else
12012 }
12014 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12015 SUBREGs are of the same mode, and, in both cases, the AND would
12016 be redundant if the comparison was done in the narrower mode,
12017 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12018 and the operand's possibly nonzero bits are 0xffffff01; in that case
12019 if we only care about QImode, we don't need the AND). This case
12020 occurs if the output mode of an scc insn is not SImode and
12021 STORE_FLAG_VALUE == 1 (e.g., the 386).
12023 Similarly, check for a case where the AND's are ZERO_EXTEND
12024 operations from some narrower mode even though a SUBREG is not
12025 present. */
12030 {
12046 {
12050 /* The resulting comparison is always unsigned since we masked
12051 off the original sign bit. */
12055 }
12061 {
12067 }
12071 }
12073 /* If both operands are NOT, we can strip off the outer operation
12074 and adjust the comparison code for swapped operands; similarly for
12075 NEG, except that this must be an equality comparison. */
12081 else
12083 }
12085 /* If the first operand is a constant, swap the operands and adjust the
12086 comparison code appropriately, but don't do this if the second operand
12087 is already a constant integer. */
12089 {
12092 }
12094 /* We now enter a loop during which we will try to simplify the comparison.
12095 For the most part, we only are concerned with comparisons with zero,
12096 but some things may really be comparisons with zero but not start
12097 out looking that way. */
12100 {
12102 scalar_int_mode int_mode;
12106 HOST_WIDE_INT const_op;
12108 /* We only want to handle integral modes. This catches VOIDmode,
12109 CCmode, and the floating-point modes. An exception is that we
12110 can handle VOIDmode if OP0 is a COMPARE or a comparison
12111 operation. */
12118 /* Try to simplify the compare to constant, possibly changing the
12119 comparison op, and/or changing op1 to zero. */
12123 /* Compute some predicates to simplify code below. */
12130 /* If this is a sign bit comparison and we can do arithmetic in
12131 MODE, say that we will only be needing the sign bit of OP0. */
12136 HOST_WIDE_INT_1U
12141 {
12142 /* We can't do anything if OP0 is a condition code value, rather
12143 than an actual data value. */
12149 /* Get the two operands being compared. */
12152 else
12155 /* Check for the cases where we simply want the result of the
12156 earlier test or the opposite of that result. */
12160 {
12164 else
12168 {
12173 }
12174 }
12176 }
12182 /* Now try cases based on the opcode of OP0. If none of the cases
12183 does a "continue", we exit this loop immediately after the
12184 switch. */
12189 {
12191 /* If we are extracting a single bit from a variable position in
12192 a constant that has only a single bit set and are comparing it
12193 with zero, we can convert this into an equality comparison
12194 between the position and the location of the single bit. */
12195 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12196 have already reduced the shift count modulo the word size. */
12202 {
12210 /* Result is nonzero iff shift count is equal to I. */
12213 }
12215 /* fall through */
12220 {
12223 }
12227 /* If testing for equality, we can take the NOT of the constant. */
12230 {
12234 }
12236 /* If just looking at the sign bit, reverse the sense of the
12237 comparison. */
12239 {
12243 }
12247 /* If testing for equality, we can take the NEG of the constant. */
12250 {
12254 }
12256 /* The remaining cases only apply to comparisons with zero. */
12260 /* When X is ABS or is known positive,
12261 (neg X) is < 0 if and only if X != 0. */
12269 {
12273 }
12275 /* If we have NEG of something whose two high-order bits are the
12276 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12278 {
12282 }
12286 /* If we are testing equality and our count is a constant, we
12287 can perform the inverse operation on our RHS. */
12291 {
12295 }
12297 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12298 a particular bit. Convert it to an AND of a constant of that
12299 bit. This will be converted into a ZERO_EXTRACT. */
12303 {
12305 (HOST_WIDE_INT_1U
12310 }
12312 /* Fall through. */
12315 /* ABS is ignorable inside an equality comparison with zero. */
12317 {
12320 }
12324 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12325 (compare FOO CONST) if CONST fits in FOO's mode and we
12326 are either testing inequality or have an unsigned
12327 comparison with ZERO_EXTEND or a signed comparison with
12328 SIGN_EXTEND. But don't do it if we don't have a compare
12329 insn of the given mode, since we'd have to revert it
12330 later on, and then we wouldn't know whether to sign- or
12331 zero-extend. */
12333 && ! unsigned_comparison_p
12337 {
12340 }
12344 /* Check for the case where we are comparing A - C1 with C2, that is
12346 (subreg:MODE (plus (A) (-C1))) op (C2)
12348 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12349 comparison in the wider mode. One of the following two conditions
12350 must be true in order for this to be valid:
12352 1. The mode extension results in the same bit pattern being added
12353 on both sides and the comparison is equality or unsigned. As
12354 C2 has been truncated to fit in MODE, the pattern can only be
12355 all 0s or all 1s.
12357 2. The mode extension results in the sign bit being copied on
12358 each side.
12360 The difficulty here is that we have predicates for A but not for
12361 (A - C1) so we need to check that C1 is within proper bounds so
12362 as to perturbate A as little as possible. */
12371 {
12379 /* (A - C1) zero-extends if it is positive and sign-extends
12380 if it is negative, C2 both zero- and sign-extends. */
12384 /* (A - C1) sign-extends if it is positive and 1-extends
12385 if it is negative, C2 both sign- and 1-extends. */
12392 /* (A - C1) always sign-extends, like C2. */
12396 {
12399 }
12400 }
12402 /* If the inner mode is narrower and we are extracting the low part,
12403 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12405 ;
12414 {
12415 /* Remove outer subregs that don't do anything. */
12420 {
12424 }
12426 }
12427 else
12430 /* FALLTHROUGH */
12439 {
12442 }
12446 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12447 this for equality comparisons due to pathological cases involving
12448 overflows. */
12452 {
12456 }
12458 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12461 {
12465 }
12469 /* We used to optimize signed comparisons against zero, but that
12470 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12471 arrive here as equality comparisons, or (GEU, LTU) are
12472 optimized away. No need to special-case them. */
12474 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12475 (eq B (minus A C)), whichever simplifies. We can only do
12476 this for equality comparisons due to pathological cases involving
12477 overflows. */
12481 {
12485 }
12490 {
12494 }
12496 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12497 of bits in X minus 1, is one iff X > 0. */
12502 {
12506 }
12510 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12511 if C is zero or B is a constant. */
12515 {
12519 }
12524 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12525 iff X <= 0. */
12529 {
12533 }
12537 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12538 will be converted to a ZERO_EXTRACT later. */
12542 {
12547 }
12549 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12550 zero and X is a comparison and C1 and C2 describe only bits set
12551 in STORE_FLAG_VALUE, we can compare with X. */
12559 {
12566 {
12569 }
12570 }
12572 /* If we are doing an equality comparison of an AND of a bit equal
12573 to the sign bit, replace this with a LT or GE comparison of
12574 the underlying value. */
12581 {
12585 }
12587 /* If this AND operation is really a ZERO_EXTEND from a narrower
12588 mode, the constant fits within that mode, and this is either an
12589 equality or unsigned comparison, try to do this comparison in
12590 the narrower mode.
12592 Note that in:
12594 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12595 -> (ne:DI (reg:SI 4) (const_int 0))
12597 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12598 known to hold a value of the required mode the
12599 transformation is invalid. */
12607 {
12610 }
12612 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12613 fits in both M1 and M2 and the SUBREG is either paradoxical
12614 or represents the low part, permute the SUBREG and the AND
12615 and try again. */
12618 {
12620 /* Require an integral mode, to avoid creating something like
12621 (AND:SF ...). */
12624 /* It is unsafe to commute the AND into the SUBREG if the
12625 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12626 not defined. As originally written the upper bits
12627 have a defined value due to the AND operation.
12628 However, if we commute the AND inside the SUBREG then
12629 they no longer have defined values and the meaning of
12630 the code has been changed.
12631 Also C1 should not change value in the smaller mode,
12632 see PR67028 (a positive C1 can become negative in the
12633 smaller mode, so that the AND does no longer mask the
12634 upper bits). */
12635 && ((WORD_REGISTER_OPERATIONS
12647 {
12653 }
12654 }
12656 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12660 {
12665 }
12667 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12668 (eq (and (lshiftrt X) 1) 0).
12669 Also handle the case where (not X) is expressed using xor. */
12673 {
12683 == HOST_WIDE_INT_1U
12685 {
12686 op0
12691 }
12692 }
12696 /* If we have (compare (ashift FOO N) (const_int C)) and
12697 the high order N bits of FOO (N+1 if an inequality comparison)
12698 are known to be zero, we can do this by comparing FOO with C
12699 shifted right N bits so long as the low-order N bits of C are
12700 zero. */
12712 {
12713 /* We must perform a logical shift, not an arithmetic one,
12714 as we want the top N bits of C to be zero. */
12721 }
12723 /* If we are doing a sign bit comparison, it means we are testing
12724 a particular bit. Convert it to the appropriate AND. */
12727 {
12729 (HOST_WIDE_INT_1U
12734 }
12736 /* If this an equality comparison with zero and we are shifting
12737 the low bit to the sign bit, we can convert this to an AND of the
12738 low-order bit. */
12742 {
12745 }
12749 /* If this is an equality comparison with zero, we can do this
12750 as a logical shift, which might be much simpler. */
12753 {
12758 }
12760 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12761 do the comparison in a narrower mode. */
12771 {
12774 }
12776 /* Likewise if OP0 is a PLUS of a sign extension with a
12777 constant, which is usually represented with the PLUS
12778 between the shifts. */
12790 {
12798 new_const);
12800 }
12802 /* FALLTHROUGH */
12804 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12805 the low order N bits of FOO are known to be zero, we can do this
12806 by comparing FOO with C shifted left N bits so long as no
12807 overflow occurs. Even if the low order N bits of FOO aren't known
12808 to be zero, if the comparison is >= or < we can use the same
12809 optimization and for > or <= by setting all the low
12810 order N bits in the comparison constant. */
12821 {
12822 unsigned HOST_WIDE_INT low_bits
12824 & ((HOST_WIDE_INT_1U
12827 {
12828 /* If the shift was logical, then we must make the condition
12829 unsigned. */
12838 const_op
12843 }
12844 }
12846 /* If we are using this shift to extract just the sign bit, we
12847 can replace this with an LT or GE comparison. */
12852 {
12856 }
12861 }
12864 }
12866 /* Now make any compound operations involved in this comparison. Then,
12867 check for an outmost SUBREG on OP0 that is not doing anything or is
12868 paradoxical. The latter transformation must only be performed when
12869 it is known that the "extra" bits will be the same in op0 and op1 or
12870 that they don't matter. There are three cases to consider:
12872 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12873 care bits and we can assume they have any convenient value. So
12874 making the transformation is safe.
12876 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12877 In this case the upper bits of op0 are undefined. We should not make
12878 the simplification in that case as we do not know the contents of
12879 those bits.
12881 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12882 In that case we know those bits are zeros or ones. We must also be
12883 sure that they are the same as the upper bits of op1.
12885 We can never remove a SUBREG for a non-equality comparison because
12886 the sign bit is in a different place in the underlying object. */
12899 {
12901 {
12902 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12903 implemented. */
12905 {
12908 }
12909 }
12913 {
12918 }
12919 }
12921 /* We now do the opposite procedure: Some machines don't have compare
12922 insns in all modes. If OP0's mode is an integer mode smaller than a
12923 word and we can't do a compare in that mode, see if there is a larger
12924 mode for which we can do the compare. There are a number of cases in
12925 which we can use the wider mode. */
12931 {
12936 {
12939 /* If this is a test for negative, we can make an explicit
12940 test of the sign bit. Test this first so we can use
12941 a paradoxical subreg to extend OP0. */
12945 {
12946 unsigned HOST_WIDE_INT sign
12953 }
12955 /* If the only nonzero bits in OP0 and OP1 are those in the
12956 narrower mode and this is an equality or unsigned comparison,
12957 we can use the wider mode. Similarly for sign-extended
12958 values, in which case it is true for all comparisons. */
12975 {
12976 /* If OP0 is an AND and we don't have an AND in MODE either,
12977 make a new AND in the proper mode. */
12985 else
12986 {
12988 {
12993 }
12994 else
12995 {
13000 }
13002 }
13003 }
13004 }
13005 }
13007 /* We may have changed the comparison operands. Re-canonicalize. */
13009 {
13012 }
13014 /* If this machine only supports a subset of valid comparisons, see if we
13015 can convert an unsupported one into a supported one. */
13022 }
13023 \f
13024 /* Utility function for record_value_for_reg. Count number of
13025 rtxs in X. */
13026 static int
13028 {
13035 {
13055 }
13066 }
13067 \f
13068 /* Utility function for following routine. Called when X is part of a value
13069 being stored into last_set_value. Sets last_set_table_tick
13070 for each register mentioned. Similar to mention_regs in cse.c */
13072 static void
13074 {
13080 {
13086 {
13089 }
13092 }
13096 {
13097 /* Check for identical subexpressions. If x contains
13098 identical subexpression we only have to traverse one of
13099 them. */
13101 {
13102 /* Note that at this point x1 has already been
13103 processed. */
13107 /* If x0 and x1 are identical then there is no need to
13108 process x0. */
13112 /* If x0 is identical to a subexpression of x1 then while
13113 processing x1, x0 has already been processed. Thus we
13114 are done with x. */
13119 /* If x1 is identical to a subexpression of x0 then we
13120 still have to process the rest of x0. */
13123 {
13126 }
13127 }
13130 }
13134 }
13136 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13137 are saying that the register is clobbered and we no longer know its
13138 value. If INSN is zero, don't update reg_stat[].last_set; this is
13139 only permitted with VALUE also zero and is used to invalidate the
13140 register. */
13142 static void
13144 {
13150 /* If VALUE contains REG and we have a previous value for REG, substitute
13151 the previous value. */
13153 {
13154 rtx tem;
13156 /* Set things up so get_last_value is allowed to see anything set up to
13157 our insn. */
13161 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13162 it isn't going to be useful and will take a lot of time to process,
13163 so just use the CLOBBER. */
13166 {
13172 {
13173 /* If there are two or more occurrences of REG in VALUE,
13174 prevent the value from growing too much. */
13177 }
13180 }
13181 }
13183 /* For each register modified, show we don't know its value, that
13184 we don't know about its bitwise content, that its value has been
13185 updated, and that we don't know the location of the death of the
13186 register. */
13188 {
13200 }
13202 /* Mark registers that are being referenced in this value. */
13206 /* Now update the status of each register being set.
13207 If someone is using this register in this block, set this register
13208 to invalid since we will get confused between the two lives in this
13209 basic block. This makes using this register always invalid. In cse, we
13210 scan the table to invalidate all entries using this register, but this
13211 is too much work for us. */
13214 {
13220 else
13222 }
13224 /* The value being assigned might refer to X (like in "x++;"). In that
13225 case, we must replace it with (clobber (const_int 0)) to prevent
13226 infinite loops. */
13229 {
13233 }
13235 /* For the main register being modified, update the value, the mode, the
13236 nonzero bits, and the number of sign bit copies. */
13241 {
13249 rsp->last_set_sign_bit_copies
13251 }
13252 }
13254 /* Called via note_stores from record_dead_and_set_regs to handle one
13255 SET or CLOBBER in an insn. DATA is the instruction in which the
13256 set is occurring. */
13258 static void
13260 {
13267 {
13271 }
13274 {
13275 /* If we are setting the whole register, we know its value. Otherwise
13276 show that we don't know the value. We can handle a SUBREG if it's
13277 the low part, but we must be careful with paradoxical SUBREGs on
13278 RISC architectures because we cannot strip e.g. an extension around
13279 a load and record the naked load since the RTL middle-end considers
13280 that the upper bits are defined according to LOAD_EXTEND_OP. */
13287 BITS_PER_WORD)
13290 WORD_REGISTER_OPERATIONS
13295 else
13297 }
13299 /* Ignore pushes, they clobber nothing. */
13302 }
13304 /* Update the records of when each REG was most recently set or killed
13305 for the things done by INSN. This is the last thing done in processing
13306 INSN in the combiner loop.
13308 We update reg_stat[], in particular fields last_set, last_set_value,
13309 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13310 last_death, and also the similar information mem_last_set (which insn
13311 most recently modified memory) and last_call_luid (which insn was the
13312 most recent subroutine call). */
13314 static void
13316 {
13317 rtx link;
13321 {
13324 {
13329 {
13334 }
13335 }
13338 }
13341 {
13342 hard_reg_set_iterator hrsi;
13344 {
13356 }
13360 /* We can't combine into a call pattern. Remember, though, that
13361 the return value register is set at this LUID. We could
13362 still replace a register with the return value from the
13363 wrong subroutine call! */
13365 }
13366 else
13368 }
13370 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13371 register present in the SUBREG, so for each such SUBREG go back and
13372 adjust nonzero and sign bit information of the registers that are
13373 known to have some zero/sign bits set.
13375 This is needed because when combine blows the SUBREGs away, the
13376 information on zero/sign bits is lost and further combines can be
13377 missed because of that. */
13379 static void
13381 {
13383 rtx set;
13391 {
13400 {
13403 }
13407 {
13410 }
13413 {
13416 }
13417 else
13419 }
13420 }
13422 /* Check if X, a register, is known to contain a value already
13423 truncated to MODE. In this case we can use a subreg to refer to
13424 the truncated value even though in the generic case we would need
13425 an explicit truncation. */
13427 static bool
13429 {
13441 }
13443 /* If X is a hard reg or a subreg record the mode that the register is
13444 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13445 able to turn a truncate into a subreg using this information. Return true
13446 if traversing X is complete. */
13448 static bool
13450 {
13451 machine_mode truncated_mode;
13455 {
13467 }
13468 /* ??? For hard-regs we now record everything. We might be able to
13469 optimize this using last_set_mode. */
13472 else
13479 {
13482 }
13485 }
13487 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13488 the modes they are used in. This can help truning TRUNCATEs into
13489 SUBREGs. */
13491 static void
13493 {
13498 }
13500 /* Scan X for promoted SUBREGs. For each one found,
13501 note what it implies to the registers used in it. */
13503 static void
13505 {
13510 else
13511 {
13517 {
13527 }
13528 }
13529 }
13530 \f
13531 /* Verify that all the registers and memory references mentioned in *LOC are
13532 still valid. *LOC was part of a value set in INSN when label_tick was
13533 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13534 the invalid references with (clobber (const_int 0)) and return 1. This
13535 replacement is useful because we often can get useful information about
13536 the form of a value (e.g., if it was produced by a shift that always
13537 produces -1 or 0) even though we don't know exactly what registers it
13538 was produced from. */
13540 static int
13542 {
13549 {
13555 {
13558 /* If this is a pseudo-register that was only set once and not
13559 live at the beginning of the function, it is always valid. */
13563 && (!REGNO_REG_SET_P
13565 regno)))
13567 {
13571 }
13572 }
13575 }
13576 /* If this is a memory reference, make sure that there were no stores after
13577 it that might have clobbered the value. We don't have alias info, so we
13578 assume any store invalidates it. Moreover, we only have local UIDs, so
13579 we also assume that there were stores in the intervening basic blocks. */
13582 {
13586 }
13589 {
13591 {
13592 /* Check for identical subexpressions. If x contains
13593 identical subexpression we only have to traverse one of
13594 them. */
13596 {
13597 /* Note that at this point x0 has already been checked
13598 and found valid. */
13602 /* If x0 and x1 are identical then x is also valid. */
13606 /* If x1 is identical to a subexpression of x0 then
13607 while checking x0, x1 has already been checked. Thus
13608 it is valid and so as x. */
13613 /* If x0 is identical to a subexpression of x1 then x is
13614 valid iff the rest of x1 is valid. */
13617 return
13621 }
13626 }
13632 }
13634 /* If we haven't found a reason for it to be invalid, it is valid. */
13636 }
13638 /* Get the last value assigned to X, if known. Some registers
13639 in the value may be replaced with (clobber (const_int 0)) if their value
13640 is known longer known reliably. */
13642 static rtx
13644 {
13646 rtx value;
13649 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13650 then convert it to the desired mode. If this is a paradoxical SUBREG,
13651 we cannot predict what values the "extra" bits might have. */
13665 /* If we don't have a value, or if it isn't for this basic block and
13666 it's either a hard register, set more than once, or it's a live
13667 at the beginning of the function, return 0.
13669 Because if it's not live at the beginning of the function then the reg
13670 is always set before being used (is never used without being set).
13671 And, if it's set only once, and it's always set before use, then all
13672 uses must have the same last value, even if it's not from this basic
13673 block. */
13680 || REGNO_REG_SET_P
13684 /* If the value was set in a later insn than the ones we are processing,
13685 we can't use it even if the register was only set once. */
13690 /* If fewer bits were set than what we are asked for now, we cannot use
13691 the value. */
13696 /* If the value has all its registers valid, return it. */
13700 /* Otherwise, make a copy and replace any invalid register with
13701 (clobber (const_int 0)). If that fails for some reason, return 0. */
13708 }
13709 \f
13710 /* Define three variables used for communication between the following
13711 routines. */
13716 /* Function called via note_stores from reg_dead_at_p.
13718 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13719 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13721 static void
13723 {
13733 }
13735 /* Return nonzero if REG is known to be dead at INSN.
13737 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13738 referencing REG, it is dead. If we hit a SET referencing REG, it is
13739 live. Otherwise, see if it is live or dead at the start of the basic
13740 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13741 must be assumed to be always live. */
13743 static int
13745 {
13746 basic_block block;
13749 /* Set variables for reg_dead_at_p_1. */
13755 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13756 we allow the machine description to decide whether use-and-clobber
13757 patterns are OK. */
13759 {
13763 }
13765 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13766 beginning of basic block. */
13769 {
13771 {
13781 }
13787 }
13789 /* Look at live-in sets for the basic block that we were in. */
13795 }
13796 \f
13797 /* Note hard registers in X that are used. */
13799 static void
13801 {
13807 {
13811 CASE_CONST_ANY:
13816 /* CC0 must die in the insn after it is set, so we don't need to take
13817 special note of it here. */
13822 /* If we are clobbering a MEM, mark any hard registers inside the
13823 address as used. */
13830 /* A hard reg in a wide mode may really be multiple registers.
13831 If so, mark all of them just like the first. */
13833 {
13834 /* None of this applies to the stack, frame or arg pointers. */
13836 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13844 }
13848 {
13849 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13850 the address. */
13862 }
13867 }
13869 /* Recursively scan the operands of this expression. */
13871 {
13875 {
13879 {
13884 }
13885 }
13886 }
13887 }
13888 \f
13889 /* Remove register number REGNO from the dead registers list of INSN.
13891 Return the note used to record the death, if there was one. */
13893 rtx
13895 {
13902 }
13904 /* For each register (hardware or pseudo) used within expression X, if its
13905 death is in an instruction with luid between FROM_LUID (inclusive) and
13906 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13907 list headed by PNOTES.
13909 That said, don't move registers killed by maybe_kill_insn.
13911 This is done when X is being merged by combination into TO_INSN. These
13912 notes will then be distributed as needed. */
13914 static void
13917 {
13923 {
13927 /* If we do not know where the register died, it may still die between
13928 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
13930 {
13935 {
13937 {
13941 }
13944 }
13945 }
13947 /* Don't move the register if it gets killed in between from and to. */
13956 {
13959 /* It is possible for the call above to return 0. This can occur
13960 when last_death points to I2 or I1 that we combined with.
13961 In that case make a new note.
13963 We must also check for the case where X is a hard register
13964 and NOTE is a death note for a range of hard registers
13965 including X. In that case, we must put REG_DEAD notes for
13966 the remaining registers in place of NOTE. */
13970 {
13979 }
13981 /* If we didn't find any note, or if we found a REG_DEAD note that
13982 covers only part of the given reg, and we have a multi-reg hard
13983 register, then to be safe we must check for REG_DEAD notes
13984 for each register other than the first. They could have
13985 their own REG_DEAD notes lying around. */
13992 {
13999 else
14005 }
14008 {
14011 }
14012 else
14014 }
14017 }
14020 {
14025 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14026 that accesses one word of a multi-word item, some
14027 piece of everything register in the expression is used by
14028 this insn, so remove any old death. */
14029 /* ??? So why do we test for equality of the sizes? */
14035 {
14038 }
14040 /* If this is some other SUBREG, we know it replaces the entire
14041 value, so use that as the destination. */
14045 /* If this is a MEM, adjust deaths of anything used in the address.
14046 For a REG (the only other possibility), the entire value is
14047 being replaced so the old value is not used in this insn. */
14053 }
14062 {
14064 {
14069 }
14072 }
14073 }
14074 \f
14075 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14076 pattern of an insn. X must be a REG. */
14078 static int
14080 {
14084 {
14086 rtx target;
14093 else
14110 }
14118 }
14119 \f
14120 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14121 as appropriate. I3 and I2 are the insns resulting from the combination
14122 insns including FROM (I2 may be zero).
14124 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14125 not need REG_DEAD notes because they are being substituted for. This
14126 saves searching in the most common cases.
14128 Each note in the list is either ignored or placed on some insns, depending
14129 on the type of note. */
14131 static void
14134 {
14136 rtx tem_note;
14140 {
14145 {
14148 /* Doesn't matter much where we put this, as long as it's somewhere.
14149 It is preferable to keep these notes on branches, which is most
14150 likely to be i3. */
14157 else
14158 {
14161 }
14165 /* These notes must remain with the call or trapping instruction. */
14170 else
14171 {
14177 /* ??? Otherwise assume we've combined things such that we
14178 can now prove that the instructions can't trap. Drop the
14179 note in this case. */
14180 }
14184 /* ??? How to distribute between i3-i1. Assume i3 contains the
14185 entire adjustment. Assert i3 contains at least some adjust. */
14187 {
14189 /* fixup_args_size_notes looks at REG_NORETURN note,
14190 so ensure the note is placed there first. */
14192 {
14196 {
14202 }
14203 }
14205 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14206 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14209 && !ACCUMULATE_OUTGOING_ARGS
14211 }
14219 /* These notes must remain with the call. It should not be
14220 possible for both I2 and I3 to be a call. */
14223 else
14224 {
14227 }
14231 /* Any clobbers for i3 may still exist, and so we must process
14232 REG_UNUSED notes from that insn.
14234 Any clobbers from i2 or i1 can only exist if they were added by
14235 recog_for_combine. In that case, recog_for_combine created the
14236 necessary REG_UNUSED notes. Trying to keep any original
14237 REG_UNUSED notes from these insns can cause incorrect output
14238 if it is for the same register as the original i3 dest.
14239 In that case, we will notice that the register is set in i3,
14240 and then add a REG_UNUSED note for the destination of i3, which
14241 is wrong. However, it is possible to have REG_UNUSED notes from
14242 i2 or i1 for register which were both used and clobbered, so
14243 we keep notes from i2 or i1 if they will turn into REG_DEAD
14244 notes. */
14246 /* If this register is set or clobbered in I3, put the note there
14247 unless there is one already. */
14249 {
14257 }
14258 /* Otherwise, if this register is used by I3, then this register
14259 now dies here, so we must put a REG_DEAD note here unless there
14260 is one already. */
14266 {
14269 }
14271 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14272 but we can't tell which at this point. We must reset any
14273 expectations we had about the value that was previously
14274 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14275 and, if appropriate, restore its previous value, but we
14276 don't have enough information for that at this point. */
14277 else
14278 {
14281 /* Otherwise, if this register is now referenced in i2
14282 then the register used to be modified in one of the
14283 original insns. If it was i3 (say, in an unused
14284 parallel), it's now completely gone, so the note can
14285 be discarded. But if it was modified in i2, i1 or i0
14286 and we still reference it in i2, then we're
14287 referencing the previous value, and since the
14288 register was modified and REG_UNUSED, we know that
14289 the previous value is now dead. So, if we only
14290 reference the register in i2, we change the note to
14291 REG_DEAD, to reflect the previous value. However, if
14292 we're also setting or clobbering the register as
14293 scratch, we know (because the register was not
14294 referenced in i3) that it's unused, just as it was
14295 unused before, and we place the note in i2. */
14298 {
14307 }
14308 }
14315 /* These notes say something about results of an insn. We can
14316 only support them if they used to be on I3 in which case they
14317 remain on I3. Otherwise they are ignored.
14319 If the note refers to an expression that is not a constant, we
14320 must also ignore the note since we cannot tell whether the
14321 equivalence is still true. It might be possible to do
14322 slightly better than this (we only have a problem if I2DEST
14323 or I1DEST is present in the expression), but it doesn't
14324 seem worth the trouble. */
14332 /* These notes say something about how a register is used. They must
14333 be present on any use of the register in I2 or I3. */
14338 {
14341 else
14343 }
14348 /* This can show up in several ways -- either directly in the
14349 pattern, or hidden off in the constant pool with (or without?)
14350 a REG_EQUAL note. */
14351 /* ??? Ignore the without-reg_equal-note problem for now. */
14363 {
14366 else
14368 }
14370 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14371 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14372 there. */
14377 {
14384 }
14390 {
14398 }
14402 /* This note says something about the value of a register prior
14403 to the execution of an insn. It is too much trouble to see
14404 if the note is still correct in all situations. It is better
14405 to simply delete it. */
14409 /* If we replaced the right hand side of FROM_INSN with a
14410 REG_EQUAL note, the original use of the dying register
14411 will not have been combined into I3 and I2. In such cases,
14412 FROM_INSN is guaranteed to be the first of the combined
14413 instructions, so we simply need to search back before
14414 FROM_INSN for the previous use or set of this register,
14415 then alter the notes there appropriately.
14417 If the register is used as an input in I3, it dies there.
14418 Similarly for I2, if it is nonzero and adjacent to I3.
14420 If the register is not used as an input in either I3 or I2
14421 and it is not one of the registers we were supposed to eliminate,
14422 there are two possibilities. We might have a non-adjacent I2
14423 or we might have somehow eliminated an additional register
14424 from a computation. For example, we might have had A & B where
14425 we discover that B will always be zero. In this case we will
14426 eliminate the reference to A.
14428 In both cases, we must search to see if we can find a previous
14429 use of A and put the death note there. */
14435 else
14436 {
14442 {
14443 /* If the new I2 sets the same register that is marked
14444 dead in the note, we do not in general know where to
14445 put the note. One important case we _can_ handle is
14446 when the note comes from I3. */
14449 else
14451 }
14458 && !(i2mod
14460 i2mod_old_rhs)))
14465 }
14468 {
14472 {
14474 {
14478 }
14480 /* If the register is being set at TEM_INSN, see if that is all
14481 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14482 into a REG_UNUSED note instead. Don't delete sets to
14483 global register vars. */
14487 {
14498 ;
14500 /* Verify that it was the set, and not a clobber that
14501 modified the register.
14503 CC0 targets must be careful to maintain setter/user
14504 pairs. If we cannot delete the setter due to side
14505 effects, mark the user with an UNUSED note instead
14506 of deleting it. */
14510 && (!HAVE_cc0
14514 {
14515 /* Move the notes and links of TEM_INSN elsewhere.
14516 This might delete other dead insns recursively.
14517 First set the pattern to something that won't use
14518 any register. */
14537 /* Delete the setter too. */
14539 {
14552 }
14553 }
14554 else
14555 {
14558 /* If there isn't already a REG_UNUSED note, put one
14559 here. Do not place a REG_DEAD note, even if
14560 the register is also used here; that would not
14561 match the algorithm used in lifetime analysis
14562 and can cause the consistency check in the
14563 scheduler to fail. */
14568 }
14569 }
14573 {
14576 /* If we are doing a 3->2 combination, and we have a
14577 register which formerly died in i3 and was not used
14578 by i2, which now no longer dies in i3 and is used in
14579 i2 but does not die in i2, and place is between i2
14580 and i3, then we may need to move a link from place to
14581 i2. */
14583 && from_insn
14586 {
14590 }
14592 }
14596 }
14598 }
14600 /* If the register is set or already dead at PLACE, we needn't do
14601 anything with this note if it is still a REG_DEAD note.
14602 We check here if it is set at all, not if is it totally replaced,
14603 which is what `dead_or_set_p' checks, so also check for it being
14604 set partially. */
14607 {
14613 {
14614 /* Unless the register previously died in PLACE, clear
14615 last_death. [I no longer understand why this is
14616 being done.] */
14620 }
14621 else
14624 /* If this is a death note for a hard reg that is occupying
14625 multiple registers, ensure that we are still using all
14626 parts of the object. If we find a piece of the object
14627 that is unused, we must arrange for an appropriate REG_DEAD
14628 note to be added for it. However, we can't just emit a USE
14629 and tag the note to it, since the register might actually
14630 be dead; so we recourse, and the recursive call then finds
14631 the previous insn that used this register. */
14634 {
14643 {
14646 }
14649 {
14650 /* Put only REG_DEAD notes for pieces that are
14651 not already dead or set. */
14655 {
14662 {
14664 NULL_RTX);
14668 NULL_RTX);
14669 }
14674 {
14676 {
14680 }
14684 {
14687 }
14688 }
14689 }
14692 }
14693 }
14694 }
14698 /* Any other notes should not be present at this point in the
14699 compilation. */
14701 }
14704 {
14708 /* Set added_notes_insn to the earliest insn we added a note to. */
14712 }
14715 {
14718 /* Set added_notes_insn to the earliest insn we added a note to. */
14722 }
14723 }
14724 }
14725 \f
14726 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14727 I3, I2, and I1 to new locations. This is also called to add a link
14728 pointing at I3 when I3's destination is changed. */
14730 static void
14732 {
14736 {
14743 /* If the insn that this link points to is a NOTE, ignore it. */
14752 {
14755 {
14771 }
14774 }
14775 else
14788 /* A LOG_LINK is defined as being placed on the first insn that uses
14789 a register and points to the insn that sets the register. Start
14790 searching at the next insn after the target of the link and stop
14791 when we reach a set of the register or the end of the basic block.
14793 Note that this correctly handles the link that used to point from
14794 I3 to I2. Also note that not much searching is typically done here
14795 since most links don't point very far away. */
14804 {
14808 }
14811 {
14814 }
14818 /* If we found a place to put the link, place it there unless there
14819 is already a link to the same insn as LINK at that point. */
14822 {
14830 {
14834 /* Set added_links_insn to the earliest insn we added a
14835 link to. */
14839 }
14840 }
14841 }
14842 }
14843 \f
14844 /* Check for any register or memory mentioned in EQUIV that is not
14845 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14846 of EXPR where some registers may have been replaced by constants. */
14848 static bool
14850 {
14853 {
14858 }
14860 }
14861 \f
14862 DEBUG_FUNCTION void
14864 {
14865 fprintf
14867 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14869 }
14871 void
14873 {
14874 fprintf
14876 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14878 }
14879 \f
14880 /* Try combining insns through substitution. */
14881 static unsigned int
14883 {
14893 rebuild_jump_labels_after_combine
14896 /* Combining insns may have turned an indirect jump into a
14897 direct jump. Rebuild the JUMP_LABEL fields of jumping
14898 instructions. */
14900 {
14907 }
14911 }
14916 {
14926 };
14929 {
14933 {}
14935 /* opt_pass methods: */
14938 {
14940 }
14946 rtl_opt_pass *
14948 {
14950 }