1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
30 /* Include insn-config.h before expr.h so that HAVE_conditional_move
31 is properly defined. */
32 #include "insn-config.h"
46 #include "basic-block.h"
49 /* Each optab contains info on how this target machine
50 can perform a particular operation
51 for all sizes and kinds of operands.
53 The operation to be performed is often specified
54 by passing one of these optabs as an argument.
56 See expr.h for documentation of these optabs. */
58 optab optab_table
[OTI_MAX
];
60 rtx libfunc_table
[LTI_MAX
];
62 /* Tables of patterns for converting one mode to another. */
63 convert_optab convert_optab_table
[COI_MAX
];
65 /* Contains the optab used for each rtx code. */
66 optab code_to_optab
[NUM_RTX_CODE
+ 1];
68 /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...)
69 gives the gen_function to make a branch to test that condition. */
71 rtxfun bcc_gen_fctn
[NUM_RTX_CODE
];
73 /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...)
74 gives the insn code to make a store-condition insn
75 to test that condition. */
77 enum insn_code setcc_gen_code
[NUM_RTX_CODE
];
79 #ifdef HAVE_conditional_move
80 /* Indexed by the machine mode, gives the insn code to make a conditional
81 move insn. This is not indexed by the rtx-code like bcc_gen_fctn and
82 setcc_gen_code to cut down on the number of named patterns. Consider a day
83 when a lot more rtx codes are conditional (eg: for the ARM). */
85 enum insn_code movcc_gen_code
[NUM_MACHINE_MODES
];
88 /* Indexed by the machine mode, gives the insn code for vector conditional
91 enum insn_code vcond_gen_code
[NUM_MACHINE_MODES
];
92 enum insn_code vcondu_gen_code
[NUM_MACHINE_MODES
];
94 /* The insn generating function can not take an rtx_code argument.
95 TRAP_RTX is used as an rtx argument. Its code is replaced with
96 the code to be used in the trap insn and all other fields are ignored. */
97 static GTY(()) rtx trap_rtx
;
99 static int add_equal_note (rtx
, rtx
, enum rtx_code
, rtx
, rtx
);
100 static rtx
widen_operand (rtx
, enum machine_mode
, enum machine_mode
, int,
102 static void prepare_cmp_insn (rtx
*, rtx
*, enum rtx_code
*, rtx
,
103 enum machine_mode
*, int *,
104 enum can_compare_purpose
);
105 static enum insn_code
can_fix_p (enum machine_mode
, enum machine_mode
, int,
107 static enum insn_code
can_float_p (enum machine_mode
, enum machine_mode
, int);
108 static optab
new_optab (void);
109 static convert_optab
new_convert_optab (void);
110 static inline optab
init_optab (enum rtx_code
);
111 static inline optab
init_optabv (enum rtx_code
);
112 static inline convert_optab
init_convert_optab (enum rtx_code
);
113 static void init_libfuncs (optab
, int, int, const char *, int);
114 static void init_integral_libfuncs (optab
, const char *, int);
115 static void init_floating_libfuncs (optab
, const char *, int);
116 static void init_interclass_conv_libfuncs (convert_optab
, const char *,
117 enum mode_class
, enum mode_class
);
118 static void init_intraclass_conv_libfuncs (convert_optab
, const char *,
119 enum mode_class
, bool);
120 static void emit_cmp_and_jump_insn_1 (rtx
, rtx
, enum machine_mode
,
121 enum rtx_code
, int, rtx
);
122 static void prepare_float_lib_cmp (rtx
*, rtx
*, enum rtx_code
*,
123 enum machine_mode
*, int *);
124 static rtx
widen_clz (enum machine_mode
, rtx
, rtx
);
125 static rtx
expand_parity (enum machine_mode
, rtx
, rtx
);
126 static enum rtx_code
get_rtx_code (enum tree_code
, bool);
127 static rtx
vector_compare_rtx (tree
, bool, enum insn_code
);
129 #ifndef HAVE_conditional_trap
130 #define HAVE_conditional_trap 0
131 #define gen_conditional_trap(a,b) (gcc_unreachable (), NULL_RTX)
134 /* Prefixes for the current version of decimal floating point (BID vs. DPD) */
135 #if ENABLE_DECIMAL_BID_FORMAT
136 #define DECIMAL_PREFIX "bid_"
138 #define DECIMAL_PREFIX "dpd_"
142 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
143 the result of operation CODE applied to OP0 (and OP1 if it is a binary
146 If the last insn does not set TARGET, don't do anything, but return 1.
148 If a previous insn sets TARGET and TARGET is one of OP0 or OP1,
149 don't add the REG_EQUAL note but return 0. Our caller can then try
150 again, ensuring that TARGET is not one of the operands. */
153 add_equal_note (rtx insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
155 rtx last_insn
, insn
, set
;
158 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
160 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
161 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
162 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
163 && GET_RTX_CLASS (code
) != RTX_COMPARE
164 && GET_RTX_CLASS (code
) != RTX_UNARY
)
167 if (GET_CODE (target
) == ZERO_EXTRACT
)
170 for (last_insn
= insns
;
171 NEXT_INSN (last_insn
) != NULL_RTX
;
172 last_insn
= NEXT_INSN (last_insn
))
175 set
= single_set (last_insn
);
179 if (! rtx_equal_p (SET_DEST (set
), target
)
180 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
181 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
182 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
185 /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET
186 besides the last insn. */
187 if (reg_overlap_mentioned_p (target
, op0
)
188 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
190 insn
= PREV_INSN (last_insn
);
191 while (insn
!= NULL_RTX
)
193 if (reg_set_p (target
, insn
))
196 insn
= PREV_INSN (insn
);
200 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
201 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
203 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
205 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
210 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
211 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
212 not actually do a sign-extend or zero-extend, but can leave the
213 higher-order bits of the result rtx undefined, for example, in the case
214 of logical operations, but not right shifts. */
217 widen_operand (rtx op
, enum machine_mode mode
, enum machine_mode oldmode
,
218 int unsignedp
, int no_extend
)
222 /* If we don't have to extend and this is a constant, return it. */
223 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
226 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
227 extend since it will be more efficient to do so unless the signedness of
228 a promoted object differs from our extension. */
230 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
231 && SUBREG_PROMOTED_UNSIGNED_P (op
) == unsignedp
))
232 return convert_modes (mode
, oldmode
, op
, unsignedp
);
234 /* If MODE is no wider than a single word, we return a paradoxical
236 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
237 return gen_rtx_SUBREG (mode
, force_reg (GET_MODE (op
), op
), 0);
239 /* Otherwise, get an object of MODE, clobber it, and set the low-order
242 result
= gen_reg_rtx (mode
);
243 emit_insn (gen_rtx_CLOBBER (VOIDmode
, result
));
244 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
248 /* Return the optab used for computing the operation given by
249 the tree code, CODE. This function is not always usable (for
250 example, it cannot give complete results for multiplication
251 or division) but probably ought to be relied on more widely
252 throughout the expander. */
254 optab_for_tree_code (enum tree_code code
, tree type
)
266 return one_cmpl_optab
;
275 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
283 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
289 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
298 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
301 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
303 case REALIGN_LOAD_EXPR
:
304 return vec_realign_load_optab
;
307 return TYPE_UNSIGNED (type
) ? usum_widen_optab
: ssum_widen_optab
;
310 return TYPE_UNSIGNED (type
) ? udot_prod_optab
: sdot_prod_optab
;
313 return TYPE_UNSIGNED (type
) ? reduc_umax_optab
: reduc_smax_optab
;
316 return TYPE_UNSIGNED (type
) ? reduc_umin_optab
: reduc_smin_optab
;
318 case REDUC_PLUS_EXPR
:
319 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
321 case VEC_LSHIFT_EXPR
:
322 return vec_shl_optab
;
324 case VEC_RSHIFT_EXPR
:
325 return vec_shr_optab
;
327 case VEC_WIDEN_MULT_HI_EXPR
:
328 return TYPE_UNSIGNED (type
) ?
329 vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
331 case VEC_WIDEN_MULT_LO_EXPR
:
332 return TYPE_UNSIGNED (type
) ?
333 vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
335 case VEC_UNPACK_HI_EXPR
:
336 return TYPE_UNSIGNED (type
) ?
337 vec_unpacku_hi_optab
: vec_unpacks_hi_optab
;
339 case VEC_UNPACK_LO_EXPR
:
340 return TYPE_UNSIGNED (type
) ?
341 vec_unpacku_lo_optab
: vec_unpacks_lo_optab
;
343 case VEC_PACK_TRUNC_EXPR
:
344 return vec_pack_trunc_optab
;
346 case VEC_PACK_SAT_EXPR
:
347 return TYPE_UNSIGNED (type
) ? vec_pack_usat_optab
: vec_pack_ssat_optab
;
353 trapv
= INTEGRAL_TYPE_P (type
) && TYPE_OVERFLOW_TRAPS (type
);
357 return trapv
? addv_optab
: add_optab
;
360 return trapv
? subv_optab
: sub_optab
;
363 return trapv
? smulv_optab
: smul_optab
;
366 return trapv
? negv_optab
: neg_optab
;
369 return trapv
? absv_optab
: abs_optab
;
371 case VEC_EXTRACT_EVEN_EXPR
:
372 return vec_extract_even_optab
;
374 case VEC_EXTRACT_ODD_EXPR
:
375 return vec_extract_odd_optab
;
377 case VEC_INTERLEAVE_HIGH_EXPR
:
378 return vec_interleave_high_optab
;
380 case VEC_INTERLEAVE_LOW_EXPR
:
381 return vec_interleave_low_optab
;
389 /* Expand vector widening operations.
391 There are two different classes of operations handled here:
392 1) Operations whose result is wider than all the arguments to the operation.
393 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
394 In this case OP0 and optionally OP1 would be initialized,
395 but WIDE_OP wouldn't (not relevant for this case).
396 2) Operations whose result is of the same size as the last argument to the
397 operation, but wider than all the other arguments to the operation.
398 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
399 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
401 E.g, when called to expand the following operations, this is how
402 the arguments will be initialized:
404 widening-sum 2 oprnd0 - oprnd1
405 widening-dot-product 3 oprnd0 oprnd1 oprnd2
406 widening-mult 2 oprnd0 oprnd1 -
407 type-promotion (vec-unpack) 1 oprnd0 - - */
410 expand_widen_pattern_expr (tree exp
, rtx op0
, rtx op1
, rtx wide_op
, rtx target
,
413 tree oprnd0
, oprnd1
, oprnd2
;
414 enum machine_mode wmode
= 0, tmode0
, tmode1
= 0;
415 optab widen_pattern_optab
;
417 enum machine_mode xmode0
, xmode1
= 0, wxmode
= 0;
420 rtx xop0
, xop1
, wxop
;
421 int nops
= TREE_OPERAND_LENGTH (exp
);
423 oprnd0
= TREE_OPERAND (exp
, 0);
424 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
425 widen_pattern_optab
=
426 optab_for_tree_code (TREE_CODE (exp
), TREE_TYPE (oprnd0
));
427 icode
= (int) widen_pattern_optab
->handlers
[(int) tmode0
].insn_code
;
428 gcc_assert (icode
!= CODE_FOR_nothing
);
429 xmode0
= insn_data
[icode
].operand
[1].mode
;
433 oprnd1
= TREE_OPERAND (exp
, 1);
434 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
435 xmode1
= insn_data
[icode
].operand
[2].mode
;
438 /* The last operand is of a wider mode than the rest of the operands. */
446 gcc_assert (tmode1
== tmode0
);
448 oprnd2
= TREE_OPERAND (exp
, 2);
449 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
450 wxmode
= insn_data
[icode
].operand
[3].mode
;
454 wmode
= wxmode
= insn_data
[icode
].operand
[0].mode
;
457 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, wmode
))
458 temp
= gen_reg_rtx (wmode
);
466 /* In case the insn wants input operands in modes different from
467 those of the actual operands, convert the operands. It would
468 seem that we don't need to convert CONST_INTs, but we do, so
469 that they're properly zero-extended, sign-extended or truncated
472 if (GET_MODE (op0
) != xmode0
&& xmode0
!= VOIDmode
)
473 xop0
= convert_modes (xmode0
,
474 GET_MODE (op0
) != VOIDmode
480 if (GET_MODE (op1
) != xmode1
&& xmode1
!= VOIDmode
)
481 xop1
= convert_modes (xmode1
,
482 GET_MODE (op1
) != VOIDmode
488 if (GET_MODE (wide_op
) != wxmode
&& wxmode
!= VOIDmode
)
489 wxop
= convert_modes (wxmode
,
490 GET_MODE (wide_op
) != VOIDmode
495 /* Now, if insn's predicates don't allow our operands, put them into
498 if (! (*insn_data
[icode
].operand
[1].predicate
) (xop0
, xmode0
)
499 && xmode0
!= VOIDmode
)
500 xop0
= copy_to_mode_reg (xmode0
, xop0
);
504 if (! (*insn_data
[icode
].operand
[2].predicate
) (xop1
, xmode1
)
505 && xmode1
!= VOIDmode
)
506 xop1
= copy_to_mode_reg (xmode1
, xop1
);
510 if (! (*insn_data
[icode
].operand
[3].predicate
) (wxop
, wxmode
)
511 && wxmode
!= VOIDmode
)
512 wxop
= copy_to_mode_reg (wxmode
, wxop
);
514 pat
= GEN_FCN (icode
) (temp
, xop0
, xop1
, wxop
);
517 pat
= GEN_FCN (icode
) (temp
, xop0
, xop1
);
523 if (! (*insn_data
[icode
].operand
[2].predicate
) (wxop
, wxmode
)
524 && wxmode
!= VOIDmode
)
525 wxop
= copy_to_mode_reg (wxmode
, wxop
);
527 pat
= GEN_FCN (icode
) (temp
, xop0
, wxop
);
530 pat
= GEN_FCN (icode
) (temp
, xop0
);
537 /* Generate code to perform an operation specified by TERNARY_OPTAB
538 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
540 UNSIGNEDP is for the case where we have to widen the operands
541 to perform the operation. It says to use zero-extension.
543 If TARGET is nonzero, the value
544 is generated there, if it is convenient to do so.
545 In all cases an rtx is returned for the locus of the value;
546 this may or may not be TARGET. */
549 expand_ternary_op (enum machine_mode mode
, optab ternary_optab
, rtx op0
,
550 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
552 int icode
= (int) ternary_optab
->handlers
[(int) mode
].insn_code
;
553 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
554 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
555 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
558 rtx xop0
= op0
, xop1
= op1
, xop2
= op2
;
560 gcc_assert (ternary_optab
->handlers
[(int) mode
].insn_code
561 != CODE_FOR_nothing
);
563 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
564 temp
= gen_reg_rtx (mode
);
568 /* In case the insn wants input operands in modes different from
569 those of the actual operands, convert the operands. It would
570 seem that we don't need to convert CONST_INTs, but we do, so
571 that they're properly zero-extended, sign-extended or truncated
574 if (GET_MODE (op0
) != mode0
&& mode0
!= VOIDmode
)
575 xop0
= convert_modes (mode0
,
576 GET_MODE (op0
) != VOIDmode
581 if (GET_MODE (op1
) != mode1
&& mode1
!= VOIDmode
)
582 xop1
= convert_modes (mode1
,
583 GET_MODE (op1
) != VOIDmode
588 if (GET_MODE (op2
) != mode2
&& mode2
!= VOIDmode
)
589 xop2
= convert_modes (mode2
,
590 GET_MODE (op2
) != VOIDmode
595 /* Now, if insn's predicates don't allow our operands, put them into
598 if (!insn_data
[icode
].operand
[1].predicate (xop0
, mode0
)
599 && mode0
!= VOIDmode
)
600 xop0
= copy_to_mode_reg (mode0
, xop0
);
602 if (!insn_data
[icode
].operand
[2].predicate (xop1
, mode1
)
603 && mode1
!= VOIDmode
)
604 xop1
= copy_to_mode_reg (mode1
, xop1
);
606 if (!insn_data
[icode
].operand
[3].predicate (xop2
, mode2
)
607 && mode2
!= VOIDmode
)
608 xop2
= copy_to_mode_reg (mode2
, xop2
);
610 pat
= GEN_FCN (icode
) (temp
, xop0
, xop1
, xop2
);
617 /* Like expand_binop, but return a constant rtx if the result can be
618 calculated at compile time. The arguments and return value are
619 otherwise the same as for expand_binop. */
622 simplify_expand_binop (enum machine_mode mode
, optab binoptab
,
623 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
624 enum optab_methods methods
)
626 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
628 rtx x
= simplify_binary_operation (binoptab
->code
, mode
, op0
, op1
);
634 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
637 /* Like simplify_expand_binop, but always put the result in TARGET.
638 Return true if the expansion succeeded. */
641 force_expand_binop (enum machine_mode mode
, optab binoptab
,
642 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
643 enum optab_methods methods
)
645 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
646 target
, unsignedp
, methods
);
650 emit_move_insn (target
, x
);
654 /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */
657 expand_vec_shift_expr (tree vec_shift_expr
, rtx target
)
659 enum insn_code icode
;
660 rtx rtx_op1
, rtx_op2
;
661 enum machine_mode mode1
;
662 enum machine_mode mode2
;
663 enum machine_mode mode
= TYPE_MODE (TREE_TYPE (vec_shift_expr
));
664 tree vec_oprnd
= TREE_OPERAND (vec_shift_expr
, 0);
665 tree shift_oprnd
= TREE_OPERAND (vec_shift_expr
, 1);
669 switch (TREE_CODE (vec_shift_expr
))
671 case VEC_RSHIFT_EXPR
:
672 shift_optab
= vec_shr_optab
;
674 case VEC_LSHIFT_EXPR
:
675 shift_optab
= vec_shl_optab
;
681 icode
= (int) shift_optab
->handlers
[(int) mode
].insn_code
;
682 gcc_assert (icode
!= CODE_FOR_nothing
);
684 mode1
= insn_data
[icode
].operand
[1].mode
;
685 mode2
= insn_data
[icode
].operand
[2].mode
;
687 rtx_op1
= expand_expr (vec_oprnd
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
688 if (!(*insn_data
[icode
].operand
[1].predicate
) (rtx_op1
, mode1
)
689 && mode1
!= VOIDmode
)
690 rtx_op1
= force_reg (mode1
, rtx_op1
);
692 rtx_op2
= expand_expr (shift_oprnd
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
693 if (!(*insn_data
[icode
].operand
[2].predicate
) (rtx_op2
, mode2
)
694 && mode2
!= VOIDmode
)
695 rtx_op2
= force_reg (mode2
, rtx_op2
);
698 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
699 target
= gen_reg_rtx (mode
);
701 /* Emit instruction */
702 pat
= GEN_FCN (icode
) (target
, rtx_op1
, rtx_op2
);
709 /* This subroutine of expand_doubleword_shift handles the cases in which
710 the effective shift value is >= BITS_PER_WORD. The arguments and return
711 value are the same as for the parent routine, except that SUPERWORD_OP1
712 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
713 INTO_TARGET may be null if the caller has decided to calculate it. */
716 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
717 rtx outof_target
, rtx into_target
,
718 int unsignedp
, enum optab_methods methods
)
720 if (into_target
!= 0)
721 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
722 into_target
, unsignedp
, methods
))
725 if (outof_target
!= 0)
727 /* For a signed right shift, we must fill OUTOF_TARGET with copies
728 of the sign bit, otherwise we must fill it with zeros. */
729 if (binoptab
!= ashr_optab
)
730 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
732 if (!force_expand_binop (word_mode
, binoptab
,
733 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
734 outof_target
, unsignedp
, methods
))
740 /* This subroutine of expand_doubleword_shift handles the cases in which
741 the effective shift value is < BITS_PER_WORD. The arguments and return
742 value are the same as for the parent routine. */
745 expand_subword_shift (enum machine_mode op1_mode
, optab binoptab
,
746 rtx outof_input
, rtx into_input
, rtx op1
,
747 rtx outof_target
, rtx into_target
,
748 int unsignedp
, enum optab_methods methods
,
749 unsigned HOST_WIDE_INT shift_mask
)
751 optab reverse_unsigned_shift
, unsigned_shift
;
754 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
755 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
757 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
758 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
759 the opposite direction to BINOPTAB. */
760 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
762 carries
= outof_input
;
763 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
764 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
769 /* We must avoid shifting by BITS_PER_WORD bits since that is either
770 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
771 has unknown behavior. Do a single shift first, then shift by the
772 remainder. It's OK to use ~OP1 as the remainder if shift counts
773 are truncated to the mode size. */
774 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
775 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
776 if (shift_mask
== BITS_PER_WORD
- 1)
778 tmp
= immed_double_const (-1, -1, op1_mode
);
779 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
784 tmp
= immed_double_const (BITS_PER_WORD
- 1, 0, op1_mode
);
785 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
789 if (tmp
== 0 || carries
== 0)
791 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
792 carries
, tmp
, 0, unsignedp
, methods
);
796 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
797 so the result can go directly into INTO_TARGET if convenient. */
798 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
799 into_target
, unsignedp
, methods
);
803 /* Now OR in the bits carried over from OUTOF_INPUT. */
804 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
805 into_target
, unsignedp
, methods
))
808 /* Use a standard word_mode shift for the out-of half. */
809 if (outof_target
!= 0)
810 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
811 outof_target
, unsignedp
, methods
))
818 #ifdef HAVE_conditional_move
819 /* Try implementing expand_doubleword_shift using conditional moves.
820 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
821 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
822 are the shift counts to use in the former and latter case. All other
823 arguments are the same as the parent routine. */
826 expand_doubleword_shift_condmove (enum machine_mode op1_mode
, optab binoptab
,
827 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
828 rtx outof_input
, rtx into_input
,
829 rtx subword_op1
, rtx superword_op1
,
830 rtx outof_target
, rtx into_target
,
831 int unsignedp
, enum optab_methods methods
,
832 unsigned HOST_WIDE_INT shift_mask
)
834 rtx outof_superword
, into_superword
;
836 /* Put the superword version of the output into OUTOF_SUPERWORD and
838 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
839 if (outof_target
!= 0 && subword_op1
== superword_op1
)
841 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
842 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
843 into_superword
= outof_target
;
844 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
845 outof_superword
, 0, unsignedp
, methods
))
850 into_superword
= gen_reg_rtx (word_mode
);
851 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
852 outof_superword
, into_superword
,
857 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
858 if (!expand_subword_shift (op1_mode
, binoptab
,
859 outof_input
, into_input
, subword_op1
,
860 outof_target
, into_target
,
861 unsignedp
, methods
, shift_mask
))
864 /* Select between them. Do the INTO half first because INTO_SUPERWORD
865 might be the current value of OUTOF_TARGET. */
866 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
867 into_target
, into_superword
, word_mode
, false))
870 if (outof_target
!= 0)
871 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
872 outof_target
, outof_superword
,
880 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
881 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
882 input operand; the shift moves bits in the direction OUTOF_INPUT->
883 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
884 of the target. OP1 is the shift count and OP1_MODE is its mode.
885 If OP1 is constant, it will have been truncated as appropriate
886 and is known to be nonzero.
888 If SHIFT_MASK is zero, the result of word shifts is undefined when the
889 shift count is outside the range [0, BITS_PER_WORD). This routine must
890 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
892 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
893 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
894 fill with zeros or sign bits as appropriate.
896 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
897 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
898 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
899 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
902 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
903 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
904 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
905 function wants to calculate it itself.
907 Return true if the shift could be successfully synthesized. */
910 expand_doubleword_shift (enum machine_mode op1_mode
, optab binoptab
,
911 rtx outof_input
, rtx into_input
, rtx op1
,
912 rtx outof_target
, rtx into_target
,
913 int unsignedp
, enum optab_methods methods
,
914 unsigned HOST_WIDE_INT shift_mask
)
916 rtx superword_op1
, tmp
, cmp1
, cmp2
;
917 rtx subword_label
, done_label
;
918 enum rtx_code cmp_code
;
920 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
921 fill the result with sign or zero bits as appropriate. If so, the value
922 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
923 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
924 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
926 This isn't worthwhile for constant shifts since the optimizers will
927 cope better with in-range shift counts. */
928 if (shift_mask
>= BITS_PER_WORD
930 && !CONSTANT_P (op1
))
932 if (!expand_doubleword_shift (op1_mode
, binoptab
,
933 outof_input
, into_input
, op1
,
935 unsignedp
, methods
, shift_mask
))
937 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
938 outof_target
, unsignedp
, methods
))
943 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
944 is true when the effective shift value is less than BITS_PER_WORD.
945 Set SUPERWORD_OP1 to the shift count that should be used to shift
946 OUTOF_INPUT into INTO_TARGET when the condition is false. */
947 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
948 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
950 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
951 is a subword shift count. */
952 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
954 cmp2
= CONST0_RTX (op1_mode
);
960 /* Set CMP1 to OP1 - BITS_PER_WORD. */
961 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
963 cmp2
= CONST0_RTX (op1_mode
);
965 superword_op1
= cmp1
;
970 /* If we can compute the condition at compile time, pick the
971 appropriate subroutine. */
972 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
973 if (tmp
!= 0 && GET_CODE (tmp
) == CONST_INT
)
975 if (tmp
== const0_rtx
)
976 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
977 outof_target
, into_target
,
980 return expand_subword_shift (op1_mode
, binoptab
,
981 outof_input
, into_input
, op1
,
982 outof_target
, into_target
,
983 unsignedp
, methods
, shift_mask
);
986 #ifdef HAVE_conditional_move
987 /* Try using conditional moves to generate straight-line code. */
989 rtx start
= get_last_insn ();
990 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
991 cmp_code
, cmp1
, cmp2
,
992 outof_input
, into_input
,
994 outof_target
, into_target
,
995 unsignedp
, methods
, shift_mask
))
997 delete_insns_since (start
);
1001 /* As a last resort, use branches to select the correct alternative. */
1002 subword_label
= gen_label_rtx ();
1003 done_label
= gen_label_rtx ();
1006 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
1007 0, 0, subword_label
);
1010 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1011 outof_target
, into_target
,
1012 unsignedp
, methods
))
1015 emit_jump_insn (gen_jump (done_label
));
1017 emit_label (subword_label
);
1019 if (!expand_subword_shift (op1_mode
, binoptab
,
1020 outof_input
, into_input
, op1
,
1021 outof_target
, into_target
,
1022 unsignedp
, methods
, shift_mask
))
1025 emit_label (done_label
);
1029 /* Subroutine of expand_binop. Perform a double word multiplication of
1030 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
1031 as the target's word_mode. This function return NULL_RTX if anything
1032 goes wrong, in which case it may have already emitted instructions
1033 which need to be deleted.
1035 If we want to multiply two two-word values and have normal and widening
1036 multiplies of single-word values, we can do this with three smaller
1037 multiplications. Note that we do not make a REG_NO_CONFLICT block here
1038 because we are not operating on one word at a time.
1040 The multiplication proceeds as follows:
1041 _______________________
1042 [__op0_high_|__op0_low__]
1043 _______________________
1044 * [__op1_high_|__op1_low__]
1045 _______________________________________________
1046 _______________________
1047 (1) [__op0_low__*__op1_low__]
1048 _______________________
1049 (2a) [__op0_low__*__op1_high_]
1050 _______________________
1051 (2b) [__op0_high_*__op1_low__]
1052 _______________________
1053 (3) [__op0_high_*__op1_high_]
1056 This gives a 4-word result. Since we are only interested in the
1057 lower 2 words, partial result (3) and the upper words of (2a) and
1058 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1059 calculated using non-widening multiplication.
1061 (1), however, needs to be calculated with an unsigned widening
1062 multiplication. If this operation is not directly supported we
1063 try using a signed widening multiplication and adjust the result.
1064 This adjustment works as follows:
1066 If both operands are positive then no adjustment is needed.
1068 If the operands have different signs, for example op0_low < 0 and
1069 op1_low >= 0, the instruction treats the most significant bit of
1070 op0_low as a sign bit instead of a bit with significance
1071 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1072 with 2**BITS_PER_WORD - op0_low, and two's complements the
1073 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1076 Similarly, if both operands are negative, we need to add
1077 (op0_low + op1_low) * 2**BITS_PER_WORD.
1079 We use a trick to adjust quickly. We logically shift op0_low right
1080 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1081 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1082 logical shift exists, we do an arithmetic right shift and subtract
1086 expand_doubleword_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
1087 bool umulp
, enum optab_methods methods
)
1089 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1090 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1091 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
1092 rtx product
, adjust
, product_high
, temp
;
1094 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1095 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1096 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1097 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1099 /* If we're using an unsigned multiply to directly compute the product
1100 of the low-order words of the operands and perform any required
1101 adjustments of the operands, we begin by trying two more multiplications
1102 and then computing the appropriate sum.
1104 We have checked above that the required addition is provided.
1105 Full-word addition will normally always succeed, especially if
1106 it is provided at all, so we don't worry about its failure. The
1107 multiplication may well fail, however, so we do handle that. */
1111 /* ??? This could be done with emit_store_flag where available. */
1112 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1113 NULL_RTX
, 1, methods
);
1115 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
1116 NULL_RTX
, 0, OPTAB_DIRECT
);
1119 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1120 NULL_RTX
, 0, methods
);
1123 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
1124 NULL_RTX
, 0, OPTAB_DIRECT
);
1131 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
1132 NULL_RTX
, 0, OPTAB_DIRECT
);
1136 /* OP0_HIGH should now be dead. */
1140 /* ??? This could be done with emit_store_flag where available. */
1141 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1142 NULL_RTX
, 1, methods
);
1144 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
1145 NULL_RTX
, 0, OPTAB_DIRECT
);
1148 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1149 NULL_RTX
, 0, methods
);
1152 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
1153 NULL_RTX
, 0, OPTAB_DIRECT
);
1160 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
1161 NULL_RTX
, 0, OPTAB_DIRECT
);
1165 /* OP1_HIGH should now be dead. */
1167 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
1168 adjust
, 0, OPTAB_DIRECT
);
1170 if (target
&& !REG_P (target
))
1174 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1175 target
, 1, OPTAB_DIRECT
);
1177 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1178 target
, 1, OPTAB_DIRECT
);
1183 product_high
= operand_subword (product
, high
, 1, mode
);
1184 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
1185 REG_P (product_high
) ? product_high
: adjust
,
1187 emit_move_insn (product_high
, adjust
);
1191 /* Wrapper around expand_binop which takes an rtx code to specify
1192 the operation to perform, not an optab pointer. All other
1193 arguments are the same. */
1195 expand_simple_binop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
1196 rtx op1
, rtx target
, int unsignedp
,
1197 enum optab_methods methods
)
1199 optab binop
= code_to_optab
[(int) code
];
1202 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1205 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1206 binop. Order them according to commutative_operand_precedence and, if
1207 possible, try to put TARGET or a pseudo first. */
1209 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
1211 int op0_prec
= commutative_operand_precedence (op0
);
1212 int op1_prec
= commutative_operand_precedence (op1
);
1214 if (op0_prec
< op1_prec
)
1217 if (op0_prec
> op1_prec
)
1220 /* With equal precedence, both orders are ok, but it is better if the
1221 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1222 if (target
== 0 || REG_P (target
))
1223 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
1225 return rtx_equal_p (op1
, target
);
1229 /* Generate code to perform an operation specified by BINOPTAB
1230 on operands OP0 and OP1, with result having machine-mode MODE.
1232 UNSIGNEDP is for the case where we have to widen the operands
1233 to perform the operation. It says to use zero-extension.
1235 If TARGET is nonzero, the value
1236 is generated there, if it is convenient to do so.
1237 In all cases an rtx is returned for the locus of the value;
1238 this may or may not be TARGET. */
1241 expand_binop (enum machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1242 rtx target
, int unsignedp
, enum optab_methods methods
)
1244 enum optab_methods next_methods
1245 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1246 ? OPTAB_WIDEN
: methods
);
1247 enum mode_class
class;
1248 enum machine_mode wider_mode
;
1250 int commutative_op
= 0;
1251 int shift_op
= (binoptab
->code
== ASHIFT
1252 || binoptab
->code
== ASHIFTRT
1253 || binoptab
->code
== LSHIFTRT
1254 || binoptab
->code
== ROTATE
1255 || binoptab
->code
== ROTATERT
);
1256 rtx entry_last
= get_last_insn ();
1258 bool first_pass_p
= true;
1260 class = GET_MODE_CLASS (mode
);
1262 /* If subtracting an integer constant, convert this into an addition of
1263 the negated constant. */
1265 if (binoptab
== sub_optab
&& GET_CODE (op1
) == CONST_INT
)
1267 op1
= negate_rtx (mode
, op1
);
1268 binoptab
= add_optab
;
1271 /* If we are inside an appropriately-short loop and we are optimizing,
1272 force expensive constants into a register. */
1273 if (CONSTANT_P (op0
) && optimize
1274 && rtx_cost (op0
, binoptab
->code
) > COSTS_N_INSNS (1))
1276 if (GET_MODE (op0
) != VOIDmode
)
1277 op0
= convert_modes (mode
, VOIDmode
, op0
, unsignedp
);
1278 op0
= force_reg (mode
, op0
);
1281 if (CONSTANT_P (op1
) && optimize
1282 && ! shift_op
&& rtx_cost (op1
, binoptab
->code
) > COSTS_N_INSNS (1))
1284 if (GET_MODE (op1
) != VOIDmode
)
1285 op1
= convert_modes (mode
, VOIDmode
, op1
, unsignedp
);
1286 op1
= force_reg (mode
, op1
);
1289 /* Record where to delete back to if we backtrack. */
1290 last
= get_last_insn ();
1292 /* If operation is commutative,
1293 try to make the first operand a register.
1294 Even better, try to make it the same as the target.
1295 Also try to make the last operand a constant. */
1296 if (GET_RTX_CLASS (binoptab
->code
) == RTX_COMM_ARITH
1297 || binoptab
== smul_widen_optab
1298 || binoptab
== umul_widen_optab
1299 || binoptab
== smul_highpart_optab
1300 || binoptab
== umul_highpart_optab
)
1304 if (swap_commutative_operands_with_target (target
, op0
, op1
))
1314 /* If we can do it with a three-operand insn, do so. */
1316 if (methods
!= OPTAB_MUST_WIDEN
1317 && binoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1319 int icode
= (int) binoptab
->handlers
[(int) mode
].insn_code
;
1320 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
1321 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
1322 enum machine_mode tmp_mode
;
1324 rtx xop0
= op0
, xop1
= op1
;
1329 temp
= gen_reg_rtx (mode
);
1331 /* If it is a commutative operator and the modes would match
1332 if we would swap the operands, we can save the conversions. */
1335 if (GET_MODE (op0
) != mode0
&& GET_MODE (op1
) != mode1
1336 && GET_MODE (op0
) == mode1
&& GET_MODE (op1
) == mode0
)
1340 tmp
= op0
; op0
= op1
; op1
= tmp
;
1341 tmp
= xop0
; xop0
= xop1
; xop1
= tmp
;
1345 /* In case the insn wants input operands in modes different from
1346 those of the actual operands, convert the operands. It would
1347 seem that we don't need to convert CONST_INTs, but we do, so
1348 that they're properly zero-extended, sign-extended or truncated
1351 if (GET_MODE (op0
) != mode0
&& mode0
!= VOIDmode
)
1352 xop0
= convert_modes (mode0
,
1353 GET_MODE (op0
) != VOIDmode
1358 if (GET_MODE (op1
) != mode1
&& mode1
!= VOIDmode
)
1359 xop1
= convert_modes (mode1
,
1360 GET_MODE (op1
) != VOIDmode
1365 /* Now, if insn's predicates don't allow our operands, put them into
1368 if (!insn_data
[icode
].operand
[1].predicate (xop0
, mode0
)
1369 && mode0
!= VOIDmode
)
1370 xop0
= copy_to_mode_reg (mode0
, xop0
);
1372 if (!insn_data
[icode
].operand
[2].predicate (xop1
, mode1
)
1373 && mode1
!= VOIDmode
)
1374 xop1
= copy_to_mode_reg (mode1
, xop1
);
1376 if (binoptab
== vec_pack_trunc_optab
1377 || binoptab
== vec_pack_usat_optab
1378 || binoptab
== vec_pack_ssat_optab
)
1380 /* The mode of the result is different then the mode of the
1382 tmp_mode
= insn_data
[icode
].operand
[0].mode
;
1383 if (GET_MODE_NUNITS (tmp_mode
) != 2 * GET_MODE_NUNITS (mode
))
1389 if (!insn_data
[icode
].operand
[0].predicate (temp
, tmp_mode
))
1390 temp
= gen_reg_rtx (tmp_mode
);
1392 pat
= GEN_FCN (icode
) (temp
, xop0
, xop1
);
1395 /* If PAT is composed of more than one insn, try to add an appropriate
1396 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1397 operand, call ourselves again, this time without a target. */
1398 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1399 && ! add_equal_note (pat
, temp
, binoptab
->code
, xop0
, xop1
))
1401 delete_insns_since (last
);
1402 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1403 unsignedp
, methods
);
1410 delete_insns_since (last
);
1413 /* If we were trying to rotate by a constant value, and that didn't
1414 work, try rotating the other direction before falling back to
1415 shifts and bitwise-or. */
1417 && (binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1418 && class == MODE_INT
1419 && GET_CODE (op1
) == CONST_INT
1421 && (unsigned int) INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
1423 first_pass_p
= false;
1424 op1
= GEN_INT (GET_MODE_BITSIZE (mode
) - INTVAL (op1
));
1425 binoptab
= binoptab
== rotl_optab
? rotr_optab
: rotl_optab
;
1429 /* If this is a multiply, see if we can do a widening operation that
1430 takes operands of this mode and makes a wider mode. */
1432 if (binoptab
== smul_optab
1433 && GET_MODE_WIDER_MODE (mode
) != VOIDmode
1434 && (((unsignedp
? umul_widen_optab
: smul_widen_optab
)
1435 ->handlers
[(int) GET_MODE_WIDER_MODE (mode
)].insn_code
)
1436 != CODE_FOR_nothing
))
1438 temp
= expand_binop (GET_MODE_WIDER_MODE (mode
),
1439 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1440 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1444 if (GET_MODE_CLASS (mode
) == MODE_INT
1445 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1446 GET_MODE_BITSIZE (GET_MODE (temp
))))
1447 return gen_lowpart (mode
, temp
);
1449 return convert_to_mode (mode
, temp
, unsignedp
);
1453 /* Look for a wider mode of the same class for which we think we
1454 can open-code the operation. Check for a widening multiply at the
1455 wider mode as well. */
1457 if (CLASS_HAS_WIDER_MODES_P (class)
1458 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1459 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1460 wider_mode
!= VOIDmode
;
1461 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1463 if (binoptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
1464 || (binoptab
== smul_optab
1465 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1466 && (((unsignedp
? umul_widen_optab
: smul_widen_optab
)
1467 ->handlers
[(int) GET_MODE_WIDER_MODE (wider_mode
)].insn_code
)
1468 != CODE_FOR_nothing
)))
1470 rtx xop0
= op0
, xop1
= op1
;
1473 /* For certain integer operations, we need not actually extend
1474 the narrow operands, as long as we will truncate
1475 the results to the same narrowness. */
1477 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1478 || binoptab
== xor_optab
1479 || binoptab
== add_optab
|| binoptab
== sub_optab
1480 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1481 && class == MODE_INT
)
1484 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1486 /* The second operand of a shift must always be extended. */
1487 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1488 no_extend
&& binoptab
!= ashl_optab
);
1490 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1491 unsignedp
, OPTAB_DIRECT
);
1494 if (class != MODE_INT
1495 || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1496 GET_MODE_BITSIZE (wider_mode
)))
1499 target
= gen_reg_rtx (mode
);
1500 convert_move (target
, temp
, 0);
1504 return gen_lowpart (mode
, temp
);
1507 delete_insns_since (last
);
1511 /* These can be done a word at a time. */
1512 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1513 && class == MODE_INT
1514 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1515 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1521 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1522 won't be accurate, so use a new target. */
1523 if (target
== 0 || target
== op0
|| target
== op1
)
1524 target
= gen_reg_rtx (mode
);
1528 /* Do the actual arithmetic. */
1529 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1531 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1532 rtx x
= expand_binop (word_mode
, binoptab
,
1533 operand_subword_force (op0
, i
, mode
),
1534 operand_subword_force (op1
, i
, mode
),
1535 target_piece
, unsignedp
, next_methods
);
1540 if (target_piece
!= x
)
1541 emit_move_insn (target_piece
, x
);
1544 insns
= get_insns ();
1547 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1549 if (binoptab
->code
!= UNKNOWN
)
1551 = gen_rtx_fmt_ee (binoptab
->code
, mode
,
1552 copy_rtx (op0
), copy_rtx (op1
));
1556 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv_value
);
1561 /* Synthesize double word shifts from single word shifts. */
1562 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1563 || binoptab
== ashr_optab
)
1564 && class == MODE_INT
1565 && (GET_CODE (op1
) == CONST_INT
|| !optimize_size
)
1566 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1567 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1568 && ashl_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1569 && lshr_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1571 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1572 enum machine_mode op1_mode
;
1574 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1575 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1576 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1578 /* Apply the truncation to constant shifts. */
1579 if (double_shift_mask
> 0 && GET_CODE (op1
) == CONST_INT
)
1580 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1582 if (op1
== CONST0_RTX (op1_mode
))
1585 /* Make sure that this is a combination that expand_doubleword_shift
1586 can handle. See the comments there for details. */
1587 if (double_shift_mask
== 0
1588 || (shift_mask
== BITS_PER_WORD
- 1
1589 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1591 rtx insns
, equiv_value
;
1592 rtx into_target
, outof_target
;
1593 rtx into_input
, outof_input
;
1594 int left_shift
, outof_word
;
1596 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1597 won't be accurate, so use a new target. */
1598 if (target
== 0 || target
== op0
|| target
== op1
)
1599 target
= gen_reg_rtx (mode
);
1603 /* OUTOF_* is the word we are shifting bits away from, and
1604 INTO_* is the word that we are shifting bits towards, thus
1605 they differ depending on the direction of the shift and
1606 WORDS_BIG_ENDIAN. */
1608 left_shift
= binoptab
== ashl_optab
;
1609 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1611 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1612 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1614 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1615 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1617 if (expand_doubleword_shift (op1_mode
, binoptab
,
1618 outof_input
, into_input
, op1
,
1619 outof_target
, into_target
,
1620 unsignedp
, next_methods
, shift_mask
))
1622 insns
= get_insns ();
1625 equiv_value
= gen_rtx_fmt_ee (binoptab
->code
, mode
, op0
, op1
);
1626 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv_value
);
1633 /* Synthesize double word rotates from single word shifts. */
1634 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1635 && class == MODE_INT
1636 && GET_CODE (op1
) == CONST_INT
1637 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1638 && ashl_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1639 && lshr_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1642 rtx into_target
, outof_target
;
1643 rtx into_input
, outof_input
;
1645 int shift_count
, left_shift
, outof_word
;
1647 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1648 won't be accurate, so use a new target. Do this also if target is not
1649 a REG, first because having a register instead may open optimization
1650 opportunities, and second because if target and op0 happen to be MEMs
1651 designating the same location, we would risk clobbering it too early
1652 in the code sequence we generate below. */
1653 if (target
== 0 || target
== op0
|| target
== op1
|| ! REG_P (target
))
1654 target
= gen_reg_rtx (mode
);
1658 shift_count
= INTVAL (op1
);
1660 /* OUTOF_* is the word we are shifting bits away from, and
1661 INTO_* is the word that we are shifting bits towards, thus
1662 they differ depending on the direction of the shift and
1663 WORDS_BIG_ENDIAN. */
1665 left_shift
= (binoptab
== rotl_optab
);
1666 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1668 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1669 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1671 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1672 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1674 if (shift_count
== BITS_PER_WORD
)
1676 /* This is just a word swap. */
1677 emit_move_insn (outof_target
, into_input
);
1678 emit_move_insn (into_target
, outof_input
);
1683 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1684 rtx first_shift_count
, second_shift_count
;
1685 optab reverse_unsigned_shift
, unsigned_shift
;
1687 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1688 ? lshr_optab
: ashl_optab
);
1690 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1691 ? ashl_optab
: lshr_optab
);
1693 if (shift_count
> BITS_PER_WORD
)
1695 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1696 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1700 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1701 second_shift_count
= GEN_INT (shift_count
);
1704 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1705 outof_input
, first_shift_count
,
1706 NULL_RTX
, unsignedp
, next_methods
);
1707 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1708 into_input
, second_shift_count
,
1709 NULL_RTX
, unsignedp
, next_methods
);
1711 if (into_temp1
!= 0 && into_temp2
!= 0)
1712 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1713 into_target
, unsignedp
, next_methods
);
1717 if (inter
!= 0 && inter
!= into_target
)
1718 emit_move_insn (into_target
, inter
);
1720 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1721 into_input
, first_shift_count
,
1722 NULL_RTX
, unsignedp
, next_methods
);
1723 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1724 outof_input
, second_shift_count
,
1725 NULL_RTX
, unsignedp
, next_methods
);
1727 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1728 inter
= expand_binop (word_mode
, ior_optab
,
1729 outof_temp1
, outof_temp2
,
1730 outof_target
, unsignedp
, next_methods
);
1732 if (inter
!= 0 && inter
!= outof_target
)
1733 emit_move_insn (outof_target
, inter
);
1736 insns
= get_insns ();
1741 /* One may be tempted to wrap the insns in a REG_NO_CONFLICT
1742 block to help the register allocator a bit. But a multi-word
1743 rotate will need all the input bits when setting the output
1744 bits, so there clearly is a conflict between the input and
1745 output registers. So we can't use a no-conflict block here. */
1751 /* These can be done a word at a time by propagating carries. */
1752 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1753 && class == MODE_INT
1754 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1755 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1758 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1759 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1760 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1761 rtx xop0
, xop1
, xtarget
;
1763 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1764 value is one of those, use it. Otherwise, use 1 since it is the
1765 one easiest to get. */
1766 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1767 int normalizep
= STORE_FLAG_VALUE
;
1772 /* Prepare the operands. */
1773 xop0
= force_reg (mode
, op0
);
1774 xop1
= force_reg (mode
, op1
);
1776 xtarget
= gen_reg_rtx (mode
);
1778 if (target
== 0 || !REG_P (target
))
1781 /* Indicate for flow that the entire target reg is being set. */
1783 emit_insn (gen_rtx_CLOBBER (VOIDmode
, xtarget
));
1785 /* Do the actual arithmetic. */
1786 for (i
= 0; i
< nwords
; i
++)
1788 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
1789 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
1790 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
1791 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
1794 /* Main add/subtract of the input operands. */
1795 x
= expand_binop (word_mode
, binoptab
,
1796 op0_piece
, op1_piece
,
1797 target_piece
, unsignedp
, next_methods
);
1803 /* Store carry from main add/subtract. */
1804 carry_out
= gen_reg_rtx (word_mode
);
1805 carry_out
= emit_store_flag_force (carry_out
,
1806 (binoptab
== add_optab
1809 word_mode
, 1, normalizep
);
1816 /* Add/subtract previous carry to main result. */
1817 newx
= expand_binop (word_mode
,
1818 normalizep
== 1 ? binoptab
: otheroptab
,
1820 NULL_RTX
, 1, next_methods
);
1824 /* Get out carry from adding/subtracting carry in. */
1825 rtx carry_tmp
= gen_reg_rtx (word_mode
);
1826 carry_tmp
= emit_store_flag_force (carry_tmp
,
1827 (binoptab
== add_optab
1830 word_mode
, 1, normalizep
);
1832 /* Logical-ior the two poss. carry together. */
1833 carry_out
= expand_binop (word_mode
, ior_optab
,
1834 carry_out
, carry_tmp
,
1835 carry_out
, 0, next_methods
);
1839 emit_move_insn (target_piece
, newx
);
1843 if (x
!= target_piece
)
1844 emit_move_insn (target_piece
, x
);
1847 carry_in
= carry_out
;
1850 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
1852 if (mov_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
1853 || ! rtx_equal_p (target
, xtarget
))
1855 rtx temp
= emit_move_insn (target
, xtarget
);
1857 set_unique_reg_note (temp
,
1859 gen_rtx_fmt_ee (binoptab
->code
, mode
,
1870 delete_insns_since (last
);
1873 /* Attempt to synthesize double word multiplies using a sequence of word
1874 mode multiplications. We first attempt to generate a sequence using a
1875 more efficient unsigned widening multiply, and if that fails we then
1876 try using a signed widening multiply. */
1878 if (binoptab
== smul_optab
1879 && class == MODE_INT
1880 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1881 && smul_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1882 && add_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1884 rtx product
= NULL_RTX
;
1886 if (umul_widen_optab
->handlers
[(int) mode
].insn_code
1887 != CODE_FOR_nothing
)
1889 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
1892 delete_insns_since (last
);
1895 if (product
== NULL_RTX
1896 && smul_widen_optab
->handlers
[(int) mode
].insn_code
1897 != CODE_FOR_nothing
)
1899 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
1902 delete_insns_since (last
);
1905 if (product
!= NULL_RTX
)
1907 if (mov_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1909 temp
= emit_move_insn (target
? target
: product
, product
);
1910 set_unique_reg_note (temp
,
1912 gen_rtx_fmt_ee (MULT
, mode
,
1920 /* It can't be open-coded in this mode.
1921 Use a library call if one is available and caller says that's ok. */
1923 if (binoptab
->handlers
[(int) mode
].libfunc
1924 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
1928 enum machine_mode op1_mode
= mode
;
1935 op1_mode
= word_mode
;
1936 /* Specify unsigned here,
1937 since negative shift counts are meaningless. */
1938 op1x
= convert_to_mode (word_mode
, op1
, 1);
1941 if (GET_MODE (op0
) != VOIDmode
1942 && GET_MODE (op0
) != mode
)
1943 op0
= convert_to_mode (mode
, op0
, unsignedp
);
1945 /* Pass 1 for NO_QUEUE so we don't lose any increments
1946 if the libcall is cse'd or moved. */
1947 value
= emit_library_call_value (binoptab
->handlers
[(int) mode
].libfunc
,
1948 NULL_RTX
, LCT_CONST
, mode
, 2,
1949 op0
, mode
, op1x
, op1_mode
);
1951 insns
= get_insns ();
1954 target
= gen_reg_rtx (mode
);
1955 emit_libcall_block (insns
, target
, value
,
1956 gen_rtx_fmt_ee (binoptab
->code
, mode
, op0
, op1
));
1961 delete_insns_since (last
);
1963 /* It can't be done in this mode. Can we do it in a wider mode? */
1965 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
1966 || methods
== OPTAB_MUST_WIDEN
))
1968 /* Caller says, don't even try. */
1969 delete_insns_since (entry_last
);
1973 /* Compute the value of METHODS to pass to recursive calls.
1974 Don't allow widening to be tried recursively. */
1976 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
1978 /* Look for a wider mode of the same class for which it appears we can do
1981 if (CLASS_HAS_WIDER_MODES_P (class))
1983 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1984 wider_mode
!= VOIDmode
;
1985 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1987 if ((binoptab
->handlers
[(int) wider_mode
].insn_code
1988 != CODE_FOR_nothing
)
1989 || (methods
== OPTAB_LIB
1990 && binoptab
->handlers
[(int) wider_mode
].libfunc
))
1992 rtx xop0
= op0
, xop1
= op1
;
1995 /* For certain integer operations, we need not actually extend
1996 the narrow operands, as long as we will truncate
1997 the results to the same narrowness. */
1999 if ((binoptab
== ior_optab
|| binoptab
== and_optab
2000 || binoptab
== xor_optab
2001 || binoptab
== add_optab
|| binoptab
== sub_optab
2002 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
2003 && class == MODE_INT
)
2006 xop0
= widen_operand (xop0
, wider_mode
, mode
,
2007 unsignedp
, no_extend
);
2009 /* The second operand of a shift must always be extended. */
2010 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
2011 no_extend
&& binoptab
!= ashl_optab
);
2013 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
2014 unsignedp
, methods
);
2017 if (class != MODE_INT
2018 || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
2019 GET_MODE_BITSIZE (wider_mode
)))
2022 target
= gen_reg_rtx (mode
);
2023 convert_move (target
, temp
, 0);
2027 return gen_lowpart (mode
, temp
);
2030 delete_insns_since (last
);
2035 delete_insns_since (entry_last
);
2039 /* Expand a binary operator which has both signed and unsigned forms.
2040 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2043 If we widen unsigned operands, we may use a signed wider operation instead
2044 of an unsigned wider operation, since the result would be the same. */
2047 sign_expand_binop (enum machine_mode mode
, optab uoptab
, optab soptab
,
2048 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
2049 enum optab_methods methods
)
2052 optab direct_optab
= unsignedp
? uoptab
: soptab
;
2053 struct optab wide_soptab
;
2055 /* Do it without widening, if possible. */
2056 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2057 unsignedp
, OPTAB_DIRECT
);
2058 if (temp
|| methods
== OPTAB_DIRECT
)
2061 /* Try widening to a signed int. Make a fake signed optab that
2062 hides any signed insn for direct use. */
2063 wide_soptab
= *soptab
;
2064 wide_soptab
.handlers
[(int) mode
].insn_code
= CODE_FOR_nothing
;
2065 wide_soptab
.handlers
[(int) mode
].libfunc
= 0;
2067 temp
= expand_binop (mode
, &wide_soptab
, op0
, op1
, target
,
2068 unsignedp
, OPTAB_WIDEN
);
2070 /* For unsigned operands, try widening to an unsigned int. */
2071 if (temp
== 0 && unsignedp
)
2072 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2073 unsignedp
, OPTAB_WIDEN
);
2074 if (temp
|| methods
== OPTAB_WIDEN
)
2077 /* Use the right width lib call if that exists. */
2078 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
, unsignedp
, OPTAB_LIB
);
2079 if (temp
|| methods
== OPTAB_LIB
)
2082 /* Must widen and use a lib call, use either signed or unsigned. */
2083 temp
= expand_binop (mode
, &wide_soptab
, op0
, op1
, target
,
2084 unsignedp
, methods
);
2088 return expand_binop (mode
, uoptab
, op0
, op1
, target
,
2089 unsignedp
, methods
);
2093 /* Generate code to perform an operation specified by UNOPPTAB
2094 on operand OP0, with two results to TARG0 and TARG1.
2095 We assume that the order of the operands for the instruction
2096 is TARG0, TARG1, OP0.
2098 Either TARG0 or TARG1 may be zero, but what that means is that
2099 the result is not actually wanted. We will generate it into
2100 a dummy pseudo-reg and discard it. They may not both be zero.
2102 Returns 1 if this operation can be performed; 0 if not. */
2105 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
2108 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2109 enum mode_class
class;
2110 enum machine_mode wider_mode
;
2111 rtx entry_last
= get_last_insn ();
2114 class = GET_MODE_CLASS (mode
);
2117 targ0
= gen_reg_rtx (mode
);
2119 targ1
= gen_reg_rtx (mode
);
2121 /* Record where to go back to if we fail. */
2122 last
= get_last_insn ();
2124 if (unoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
2126 int icode
= (int) unoptab
->handlers
[(int) mode
].insn_code
;
2127 enum machine_mode mode0
= insn_data
[icode
].operand
[2].mode
;
2131 if (GET_MODE (xop0
) != VOIDmode
2132 && GET_MODE (xop0
) != mode0
)
2133 xop0
= convert_to_mode (mode0
, xop0
, unsignedp
);
2135 /* Now, if insn doesn't accept these operands, put them into pseudos. */
2136 if (!insn_data
[icode
].operand
[2].predicate (xop0
, mode0
))
2137 xop0
= copy_to_mode_reg (mode0
, xop0
);
2139 /* We could handle this, but we should always be called with a pseudo
2140 for our targets and all insns should take them as outputs. */
2141 gcc_assert (insn_data
[icode
].operand
[0].predicate (targ0
, mode
));
2142 gcc_assert (insn_data
[icode
].operand
[1].predicate (targ1
, mode
));
2144 pat
= GEN_FCN (icode
) (targ0
, targ1
, xop0
);
2151 delete_insns_since (last
);
2154 /* It can't be done in this mode. Can we do it in a wider mode? */
2156 if (CLASS_HAS_WIDER_MODES_P (class))
2158 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2159 wider_mode
!= VOIDmode
;
2160 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2162 if (unoptab
->handlers
[(int) wider_mode
].insn_code
2163 != CODE_FOR_nothing
)
2165 rtx t0
= gen_reg_rtx (wider_mode
);
2166 rtx t1
= gen_reg_rtx (wider_mode
);
2167 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2169 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2171 convert_move (targ0
, t0
, unsignedp
);
2172 convert_move (targ1
, t1
, unsignedp
);
2176 delete_insns_since (last
);
2181 delete_insns_since (entry_last
);
2185 /* Generate code to perform an operation specified by BINOPTAB
2186 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2187 We assume that the order of the operands for the instruction
2188 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2189 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2191 Either TARG0 or TARG1 may be zero, but what that means is that
2192 the result is not actually wanted. We will generate it into
2193 a dummy pseudo-reg and discard it. They may not both be zero.
2195 Returns 1 if this operation can be performed; 0 if not. */
2198 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2201 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2202 enum mode_class
class;
2203 enum machine_mode wider_mode
;
2204 rtx entry_last
= get_last_insn ();
2207 class = GET_MODE_CLASS (mode
);
2209 /* If we are inside an appropriately-short loop and we are optimizing,
2210 force expensive constants into a register. */
2211 if (CONSTANT_P (op0
) && optimize
2212 && rtx_cost (op0
, binoptab
->code
) > COSTS_N_INSNS (1))
2213 op0
= force_reg (mode
, op0
);
2215 if (CONSTANT_P (op1
) && optimize
2216 && rtx_cost (op1
, binoptab
->code
) > COSTS_N_INSNS (1))
2217 op1
= force_reg (mode
, op1
);
2220 targ0
= gen_reg_rtx (mode
);
2222 targ1
= gen_reg_rtx (mode
);
2224 /* Record where to go back to if we fail. */
2225 last
= get_last_insn ();
2227 if (binoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
2229 int icode
= (int) binoptab
->handlers
[(int) mode
].insn_code
;
2230 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2231 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2233 rtx xop0
= op0
, xop1
= op1
;
2235 /* In case the insn wants input operands in modes different from
2236 those of the actual operands, convert the operands. It would
2237 seem that we don't need to convert CONST_INTs, but we do, so
2238 that they're properly zero-extended, sign-extended or truncated
2241 if (GET_MODE (op0
) != mode0
&& mode0
!= VOIDmode
)
2242 xop0
= convert_modes (mode0
,
2243 GET_MODE (op0
) != VOIDmode
2248 if (GET_MODE (op1
) != mode1
&& mode1
!= VOIDmode
)
2249 xop1
= convert_modes (mode1
,
2250 GET_MODE (op1
) != VOIDmode
2255 /* Now, if insn doesn't accept these operands, put them into pseudos. */
2256 if (!insn_data
[icode
].operand
[1].predicate (xop0
, mode0
))
2257 xop0
= copy_to_mode_reg (mode0
, xop0
);
2259 if (!insn_data
[icode
].operand
[2].predicate (xop1
, mode1
))
2260 xop1
= copy_to_mode_reg (mode1
, xop1
);
2262 /* We could handle this, but we should always be called with a pseudo
2263 for our targets and all insns should take them as outputs. */
2264 gcc_assert (insn_data
[icode
].operand
[0].predicate (targ0
, mode
));
2265 gcc_assert (insn_data
[icode
].operand
[3].predicate (targ1
, mode
));
2267 pat
= GEN_FCN (icode
) (targ0
, xop0
, xop1
, targ1
);
2274 delete_insns_since (last
);
2277 /* It can't be done in this mode. Can we do it in a wider mode? */
2279 if (CLASS_HAS_WIDER_MODES_P (class))
2281 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2282 wider_mode
!= VOIDmode
;
2283 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2285 if (binoptab
->handlers
[(int) wider_mode
].insn_code
2286 != CODE_FOR_nothing
)
2288 rtx t0
= gen_reg_rtx (wider_mode
);
2289 rtx t1
= gen_reg_rtx (wider_mode
);
2290 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2291 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2293 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2296 convert_move (targ0
, t0
, unsignedp
);
2297 convert_move (targ1
, t1
, unsignedp
);
2301 delete_insns_since (last
);
2306 delete_insns_since (entry_last
);
2310 /* Expand the two-valued library call indicated by BINOPTAB, but
2311 preserve only one of the values. If TARG0 is non-NULL, the first
2312 value is placed into TARG0; otherwise the second value is placed
2313 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2314 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2315 This routine assumes that the value returned by the library call is
2316 as if the return value was of an integral mode twice as wide as the
2317 mode of OP0. Returns 1 if the call was successful. */
2320 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2321 rtx targ0
, rtx targ1
, enum rtx_code code
)
2323 enum machine_mode mode
;
2324 enum machine_mode libval_mode
;
2328 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2329 gcc_assert (!targ0
!= !targ1
);
2331 mode
= GET_MODE (op0
);
2332 if (!binoptab
->handlers
[(int) mode
].libfunc
)
2335 /* The value returned by the library function will have twice as
2336 many bits as the nominal MODE. */
2337 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2340 libval
= emit_library_call_value (binoptab
->handlers
[(int) mode
].libfunc
,
2341 NULL_RTX
, LCT_CONST
,
2345 /* Get the part of VAL containing the value that we want. */
2346 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2347 targ0
? 0 : GET_MODE_SIZE (mode
));
2348 insns
= get_insns ();
2350 /* Move the into the desired location. */
2351 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2352 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2358 /* Wrapper around expand_unop which takes an rtx code to specify
2359 the operation to perform, not an optab pointer. All other
2360 arguments are the same. */
2362 expand_simple_unop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
2363 rtx target
, int unsignedp
)
2365 optab unop
= code_to_optab
[(int) code
];
2368 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2374 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). */
2376 widen_clz (enum machine_mode mode
, rtx op0
, rtx target
)
2378 enum mode_class
class = GET_MODE_CLASS (mode
);
2379 if (CLASS_HAS_WIDER_MODES_P (class))
2381 enum machine_mode wider_mode
;
2382 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2383 wider_mode
!= VOIDmode
;
2384 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2386 if (clz_optab
->handlers
[(int) wider_mode
].insn_code
2387 != CODE_FOR_nothing
)
2389 rtx xop0
, temp
, last
;
2391 last
= get_last_insn ();
2394 target
= gen_reg_rtx (mode
);
2395 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2396 temp
= expand_unop (wider_mode
, clz_optab
, xop0
, NULL_RTX
, true);
2398 temp
= expand_binop (wider_mode
, sub_optab
, temp
,
2399 GEN_INT (GET_MODE_BITSIZE (wider_mode
)
2400 - GET_MODE_BITSIZE (mode
)),
2401 target
, true, OPTAB_DIRECT
);
2403 delete_insns_since (last
);
2415 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2417 widen_bswap (enum machine_mode mode
, rtx op0
, rtx target
)
2419 enum mode_class
class = GET_MODE_CLASS (mode
);
2420 enum machine_mode wider_mode
;
2423 if (!CLASS_HAS_WIDER_MODES_P (class))
2426 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2427 wider_mode
!= VOIDmode
;
2428 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2429 if (bswap_optab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
)
2434 last
= get_last_insn ();
2436 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2437 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2440 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2441 size_int (GET_MODE_BITSIZE (wider_mode
)
2442 - GET_MODE_BITSIZE (mode
)),
2448 target
= gen_reg_rtx (mode
);
2449 emit_move_insn (target
, gen_lowpart (mode
, x
));
2452 delete_insns_since (last
);
2457 /* Try calculating bswap as two bswaps of two word-sized operands. */
2460 expand_doubleword_bswap (enum machine_mode mode
, rtx op
, rtx target
)
2464 t1
= expand_unop (word_mode
, bswap_optab
,
2465 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2466 t0
= expand_unop (word_mode
, bswap_optab
,
2467 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2470 target
= gen_reg_rtx (mode
);
2472 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
2473 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2474 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2479 /* Try calculating (parity x) as (and (popcount x) 1), where
2480 popcount can also be done in a wider mode. */
2482 expand_parity (enum machine_mode mode
, rtx op0
, rtx target
)
2484 enum mode_class
class = GET_MODE_CLASS (mode
);
2485 if (CLASS_HAS_WIDER_MODES_P (class))
2487 enum machine_mode wider_mode
;
2488 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2489 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2491 if (popcount_optab
->handlers
[(int) wider_mode
].insn_code
2492 != CODE_FOR_nothing
)
2494 rtx xop0
, temp
, last
;
2496 last
= get_last_insn ();
2499 target
= gen_reg_rtx (mode
);
2500 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2501 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2504 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2505 target
, true, OPTAB_DIRECT
);
2507 delete_insns_since (last
);
2516 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2517 conditions, VAL may already be a SUBREG against which we cannot generate
2518 a further SUBREG. In this case, we expect forcing the value into a
2519 register will work around the situation. */
2522 lowpart_subreg_maybe_copy (enum machine_mode omode
, rtx val
,
2523 enum machine_mode imode
)
2526 ret
= lowpart_subreg (omode
, val
, imode
);
2529 val
= force_reg (imode
, val
);
2530 ret
= lowpart_subreg (omode
, val
, imode
);
2531 gcc_assert (ret
!= NULL
);
2536 /* Expand a floating point absolute value or negation operation via a
2537 logical operation on the sign bit. */
2540 expand_absneg_bit (enum rtx_code code
, enum machine_mode mode
,
2541 rtx op0
, rtx target
)
2543 const struct real_format
*fmt
;
2544 int bitpos
, word
, nwords
, i
;
2545 enum machine_mode imode
;
2546 HOST_WIDE_INT hi
, lo
;
2549 /* The format has to have a simple sign bit. */
2550 fmt
= REAL_MODE_FORMAT (mode
);
2554 bitpos
= fmt
->signbit_rw
;
2558 /* Don't create negative zeros if the format doesn't support them. */
2559 if (code
== NEG
&& !fmt
->has_signed_zero
)
2562 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2564 imode
= int_mode_for_mode (mode
);
2565 if (imode
== BLKmode
)
2574 if (FLOAT_WORDS_BIG_ENDIAN
)
2575 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2577 word
= bitpos
/ BITS_PER_WORD
;
2578 bitpos
= bitpos
% BITS_PER_WORD
;
2579 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2582 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
2585 lo
= (HOST_WIDE_INT
) 1 << bitpos
;
2589 hi
= (HOST_WIDE_INT
) 1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
2595 if (target
== 0 || target
== op0
)
2596 target
= gen_reg_rtx (mode
);
2602 for (i
= 0; i
< nwords
; ++i
)
2604 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2605 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2609 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2611 immed_double_const (lo
, hi
, imode
),
2612 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2613 if (temp
!= targ_piece
)
2614 emit_move_insn (targ_piece
, temp
);
2617 emit_move_insn (targ_piece
, op0_piece
);
2620 insns
= get_insns ();
2623 temp
= gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
));
2624 emit_no_conflict_block (insns
, target
, op0
, NULL_RTX
, temp
);
2628 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2629 gen_lowpart (imode
, op0
),
2630 immed_double_const (lo
, hi
, imode
),
2631 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2632 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2634 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
2635 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)));
2641 /* Generate code to perform an operation specified by UNOPTAB
2642 on operand OP0, with result having machine-mode MODE.
2644 UNSIGNEDP is for the case where we have to widen the operands
2645 to perform the operation. It says to use zero-extension.
2647 If TARGET is nonzero, the value
2648 is generated there, if it is convenient to do so.
2649 In all cases an rtx is returned for the locus of the value;
2650 this may or may not be TARGET. */
2653 expand_unop (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2656 enum mode_class
class;
2657 enum machine_mode wider_mode
;
2659 rtx last
= get_last_insn ();
2662 class = GET_MODE_CLASS (mode
);
2664 if (unoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
2666 int icode
= (int) unoptab
->handlers
[(int) mode
].insn_code
;
2667 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2673 temp
= gen_reg_rtx (mode
);
2675 if (GET_MODE (xop0
) != VOIDmode
2676 && GET_MODE (xop0
) != mode0
)
2677 xop0
= convert_to_mode (mode0
, xop0
, unsignedp
);
2679 /* Now, if insn doesn't accept our operand, put it into a pseudo. */
2681 if (!insn_data
[icode
].operand
[1].predicate (xop0
, mode0
))
2682 xop0
= copy_to_mode_reg (mode0
, xop0
);
2684 if (!insn_data
[icode
].operand
[0].predicate (temp
, mode
))
2685 temp
= gen_reg_rtx (mode
);
2687 pat
= GEN_FCN (icode
) (temp
, xop0
);
2690 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
2691 && ! add_equal_note (pat
, temp
, unoptab
->code
, xop0
, NULL_RTX
))
2693 delete_insns_since (last
);
2694 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
2702 delete_insns_since (last
);
2705 /* It can't be done in this mode. Can we open-code it in a wider mode? */
2707 /* Widening clz needs special treatment. */
2708 if (unoptab
== clz_optab
)
2710 temp
= widen_clz (mode
, op0
, target
);
2717 /* Widening (or narrowing) bswap needs special treatment. */
2718 if (unoptab
== bswap_optab
)
2720 temp
= widen_bswap (mode
, op0
, target
);
2724 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
2725 && unoptab
->handlers
[word_mode
].insn_code
!= CODE_FOR_nothing
)
2727 temp
= expand_doubleword_bswap (mode
, op0
, target
);
2735 if (CLASS_HAS_WIDER_MODES_P (class))
2736 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2737 wider_mode
!= VOIDmode
;
2738 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2740 if (unoptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
)
2744 /* For certain operations, we need not actually extend
2745 the narrow operand, as long as we will truncate the
2746 results to the same narrowness. */
2748 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
2749 (unoptab
== neg_optab
2750 || unoptab
== one_cmpl_optab
)
2751 && class == MODE_INT
);
2753 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2758 if (class != MODE_INT
2759 || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
2760 GET_MODE_BITSIZE (wider_mode
)))
2763 target
= gen_reg_rtx (mode
);
2764 convert_move (target
, temp
, 0);
2768 return gen_lowpart (mode
, temp
);
2771 delete_insns_since (last
);
2775 /* These can be done a word at a time. */
2776 if (unoptab
== one_cmpl_optab
2777 && class == MODE_INT
2778 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2779 && unoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
2784 if (target
== 0 || target
== op0
)
2785 target
= gen_reg_rtx (mode
);
2789 /* Do the actual arithmetic. */
2790 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
2792 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
2793 rtx x
= expand_unop (word_mode
, unoptab
,
2794 operand_subword_force (op0
, i
, mode
),
2795 target_piece
, unsignedp
);
2797 if (target_piece
!= x
)
2798 emit_move_insn (target_piece
, x
);
2801 insns
= get_insns ();
2804 emit_no_conflict_block (insns
, target
, op0
, NULL_RTX
,
2805 gen_rtx_fmt_e (unoptab
->code
, mode
,
2810 if (unoptab
->code
== NEG
)
2812 /* Try negating floating point values by flipping the sign bit. */
2813 if (SCALAR_FLOAT_MODE_P (mode
))
2815 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
2820 /* If there is no negation pattern, and we have no negative zero,
2821 try subtracting from zero. */
2822 if (!HONOR_SIGNED_ZEROS (mode
))
2824 temp
= expand_binop (mode
, (unoptab
== negv_optab
2825 ? subv_optab
: sub_optab
),
2826 CONST0_RTX (mode
), op0
, target
,
2827 unsignedp
, OPTAB_DIRECT
);
2833 /* Try calculating parity (x) as popcount (x) % 2. */
2834 if (unoptab
== parity_optab
)
2836 temp
= expand_parity (mode
, op0
, target
);
2842 /* Now try a library call in this mode. */
2843 if (unoptab
->handlers
[(int) mode
].libfunc
)
2847 enum machine_mode outmode
= mode
;
2849 /* All of these functions return small values. Thus we choose to
2850 have them return something that isn't a double-word. */
2851 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
2852 || unoptab
== popcount_optab
|| unoptab
== parity_optab
)
2854 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
)));
2858 /* Pass 1 for NO_QUEUE so we don't lose any increments
2859 if the libcall is cse'd or moved. */
2860 value
= emit_library_call_value (unoptab
->handlers
[(int) mode
].libfunc
,
2861 NULL_RTX
, LCT_CONST
, outmode
,
2863 insns
= get_insns ();
2866 target
= gen_reg_rtx (outmode
);
2867 emit_libcall_block (insns
, target
, value
,
2868 gen_rtx_fmt_e (unoptab
->code
, outmode
, op0
));
2873 /* It can't be done in this mode. Can we do it in a wider mode? */
2875 if (CLASS_HAS_WIDER_MODES_P (class))
2877 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2878 wider_mode
!= VOIDmode
;
2879 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2881 if ((unoptab
->handlers
[(int) wider_mode
].insn_code
2882 != CODE_FOR_nothing
)
2883 || unoptab
->handlers
[(int) wider_mode
].libfunc
)
2887 /* For certain operations, we need not actually extend
2888 the narrow operand, as long as we will truncate the
2889 results to the same narrowness. */
2891 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
2892 (unoptab
== neg_optab
2893 || unoptab
== one_cmpl_optab
)
2894 && class == MODE_INT
);
2896 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2899 /* If we are generating clz using wider mode, adjust the
2901 if (unoptab
== clz_optab
&& temp
!= 0)
2902 temp
= expand_binop (wider_mode
, sub_optab
, temp
,
2903 GEN_INT (GET_MODE_BITSIZE (wider_mode
)
2904 - GET_MODE_BITSIZE (mode
)),
2905 target
, true, OPTAB_DIRECT
);
2909 if (class != MODE_INT
)
2912 target
= gen_reg_rtx (mode
);
2913 convert_move (target
, temp
, 0);
2917 return gen_lowpart (mode
, temp
);
2920 delete_insns_since (last
);
2925 /* One final attempt at implementing negation via subtraction,
2926 this time allowing widening of the operand. */
2927 if (unoptab
->code
== NEG
&& !HONOR_SIGNED_ZEROS (mode
))
2930 temp
= expand_binop (mode
,
2931 unoptab
== negv_optab
? subv_optab
: sub_optab
,
2932 CONST0_RTX (mode
), op0
,
2933 target
, unsignedp
, OPTAB_LIB_WIDEN
);
2941 /* Emit code to compute the absolute value of OP0, with result to
2942 TARGET if convenient. (TARGET may be 0.) The return value says
2943 where the result actually is to be found.
2945 MODE is the mode of the operand; the mode of the result is
2946 different but can be deduced from MODE.
2951 expand_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
,
2952 int result_unsignedp
)
2957 result_unsignedp
= 1;
2959 /* First try to do it with a special abs instruction. */
2960 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
2965 /* For floating point modes, try clearing the sign bit. */
2966 if (SCALAR_FLOAT_MODE_P (mode
))
2968 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
2973 /* If we have a MAX insn, we can do this as MAX (x, -x). */
2974 if (smax_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
2975 && !HONOR_SIGNED_ZEROS (mode
))
2977 rtx last
= get_last_insn ();
2979 temp
= expand_unop (mode
, neg_optab
, op0
, NULL_RTX
, 0);
2981 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
2987 delete_insns_since (last
);
2990 /* If this machine has expensive jumps, we can do integer absolute
2991 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
2992 where W is the width of MODE. */
2994 if (GET_MODE_CLASS (mode
) == MODE_INT
&& BRANCH_COST
>= 2)
2996 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2997 size_int (GET_MODE_BITSIZE (mode
) - 1),
3000 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3003 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
3004 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3014 expand_abs (enum machine_mode mode
, rtx op0
, rtx target
,
3015 int result_unsignedp
, int safe
)
3020 result_unsignedp
= 1;
3022 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3026 /* If that does not win, use conditional jump and negate. */
3028 /* It is safe to use the target if it is the same
3029 as the source if this is also a pseudo register */
3030 if (op0
== target
&& REG_P (op0
)
3031 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3034 op1
= gen_label_rtx ();
3035 if (target
== 0 || ! safe
3036 || GET_MODE (target
) != mode
3037 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3039 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3040 target
= gen_reg_rtx (mode
);
3042 emit_move_insn (target
, op0
);
3045 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3046 NULL_RTX
, NULL_RTX
, op1
);
3048 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3051 emit_move_insn (target
, op0
);
3057 /* A subroutine of expand_copysign, perform the copysign operation using the
3058 abs and neg primitives advertised to exist on the target. The assumption
3059 is that we have a split register file, and leaving op0 in fp registers,
3060 and not playing with subregs so much, will help the register allocator. */
3063 expand_copysign_absneg (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3064 int bitpos
, bool op0_is_abs
)
3066 enum machine_mode imode
;
3067 HOST_WIDE_INT hi
, lo
;
3076 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3083 if (target
== NULL_RTX
)
3084 target
= copy_to_reg (op0
);
3086 emit_move_insn (target
, op0
);
3089 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3091 imode
= int_mode_for_mode (mode
);
3092 if (imode
== BLKmode
)
3094 op1
= gen_lowpart (imode
, op1
);
3099 if (FLOAT_WORDS_BIG_ENDIAN
)
3100 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3102 word
= bitpos
/ BITS_PER_WORD
;
3103 bitpos
= bitpos
% BITS_PER_WORD
;
3104 op1
= operand_subword_force (op1
, word
, mode
);
3107 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
3110 lo
= (HOST_WIDE_INT
) 1 << bitpos
;
3114 hi
= (HOST_WIDE_INT
) 1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
3118 op1
= expand_binop (imode
, and_optab
, op1
,
3119 immed_double_const (lo
, hi
, imode
),
3120 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3122 label
= gen_label_rtx ();
3123 emit_cmp_and_jump_insns (op1
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3125 if (GET_CODE (op0
) == CONST_DOUBLE
)
3126 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3128 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3130 emit_move_insn (target
, op0
);
3138 /* A subroutine of expand_copysign, perform the entire copysign operation
3139 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3140 is true if op0 is known to have its sign bit clear. */
3143 expand_copysign_bit (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3144 int bitpos
, bool op0_is_abs
)
3146 enum machine_mode imode
;
3147 HOST_WIDE_INT hi
, lo
;
3148 int word
, nwords
, i
;
3151 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3153 imode
= int_mode_for_mode (mode
);
3154 if (imode
== BLKmode
)
3163 if (FLOAT_WORDS_BIG_ENDIAN
)
3164 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3166 word
= bitpos
/ BITS_PER_WORD
;
3167 bitpos
= bitpos
% BITS_PER_WORD
;
3168 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3171 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
3174 lo
= (HOST_WIDE_INT
) 1 << bitpos
;
3178 hi
= (HOST_WIDE_INT
) 1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
3182 if (target
== 0 || target
== op0
|| target
== op1
)
3183 target
= gen_reg_rtx (mode
);
3189 for (i
= 0; i
< nwords
; ++i
)
3191 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3192 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3197 op0_piece
= expand_binop (imode
, and_optab
, op0_piece
,
3198 immed_double_const (~lo
, ~hi
, imode
),
3199 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3201 op1
= expand_binop (imode
, and_optab
,
3202 operand_subword_force (op1
, i
, mode
),
3203 immed_double_const (lo
, hi
, imode
),
3204 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3206 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3207 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3208 if (temp
!= targ_piece
)
3209 emit_move_insn (targ_piece
, temp
);
3212 emit_move_insn (targ_piece
, op0_piece
);
3215 insns
= get_insns ();
3218 emit_no_conflict_block (insns
, target
, op0
, op1
, NULL_RTX
);
3222 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3223 immed_double_const (lo
, hi
, imode
),
3224 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3226 op0
= gen_lowpart (imode
, op0
);
3228 op0
= expand_binop (imode
, and_optab
, op0
,
3229 immed_double_const (~lo
, ~hi
, imode
),
3230 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3232 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3233 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3234 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3240 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3241 scalar floating point mode. Return NULL if we do not know how to
3242 expand the operation inline. */
3245 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3247 enum machine_mode mode
= GET_MODE (op0
);
3248 const struct real_format
*fmt
;
3252 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3253 gcc_assert (GET_MODE (op1
) == mode
);
3255 /* First try to do it with a special instruction. */
3256 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3257 target
, 0, OPTAB_DIRECT
);
3261 fmt
= REAL_MODE_FORMAT (mode
);
3262 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3266 if (GET_CODE (op0
) == CONST_DOUBLE
)
3268 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3269 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3273 if (fmt
->signbit_ro
>= 0
3274 && (GET_CODE (op0
) == CONST_DOUBLE
3275 || (neg_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
3276 && abs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)))
3278 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3279 fmt
->signbit_ro
, op0_is_abs
);
3284 if (fmt
->signbit_rw
< 0)
3286 return expand_copysign_bit (mode
, op0
, op1
, target
,
3287 fmt
->signbit_rw
, op0_is_abs
);
3290 /* Generate an instruction whose insn-code is INSN_CODE,
3291 with two operands: an output TARGET and an input OP0.
3292 TARGET *must* be nonzero, and the output is always stored there.
3293 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3294 the value that is stored into TARGET. */
3297 emit_unop_insn (int icode
, rtx target
, rtx op0
, enum rtx_code code
)
3300 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
3305 /* Now, if insn does not accept our operands, put them into pseudos. */
3307 if (!insn_data
[icode
].operand
[1].predicate (op0
, mode0
))
3308 op0
= copy_to_mode_reg (mode0
, op0
);
3310 if (!insn_data
[icode
].operand
[0].predicate (temp
, GET_MODE (temp
)))
3311 temp
= gen_reg_rtx (GET_MODE (temp
));
3313 pat
= GEN_FCN (icode
) (temp
, op0
);
3315 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
&& code
!= UNKNOWN
)
3316 add_equal_note (pat
, temp
, code
, op0
, NULL_RTX
);
3321 emit_move_insn (target
, temp
);
3324 struct no_conflict_data
3326 rtx target
, first
, insn
;
3330 /* Called via note_stores by emit_no_conflict_block and emit_libcall_block.
3331 Set P->must_stay if the currently examined clobber / store has to stay
3332 in the list of insns that constitute the actual no_conflict block /
3335 no_conflict_move_test (rtx dest
, rtx set
, void *p0
)
3337 struct no_conflict_data
*p
= p0
;
3339 /* If this inns directly contributes to setting the target, it must stay. */
3340 if (reg_overlap_mentioned_p (p
->target
, dest
))
3341 p
->must_stay
= true;
3342 /* If we haven't committed to keeping any other insns in the list yet,
3343 there is nothing more to check. */
3344 else if (p
->insn
== p
->first
)
3346 /* If this insn sets / clobbers a register that feeds one of the insns
3347 already in the list, this insn has to stay too. */
3348 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3349 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3350 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3351 /* Likewise if this insn depends on a register set by a previous
3352 insn in the list, or if it sets a result (presumably a hard
3353 register) that is set or clobbered by a previous insn.
3354 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3355 SET_DEST perform the former check on the address, and the latter
3356 check on the MEM. */
3357 || (GET_CODE (set
) == SET
3358 && (modified_in_p (SET_SRC (set
), p
->first
)
3359 || modified_in_p (SET_DEST (set
), p
->first
)
3360 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3361 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3362 p
->must_stay
= true;
3365 /* Encapsulate the block starting at FIRST and ending with LAST, which is
3366 logically equivalent to EQUIV, so it gets manipulated as a unit if it
3367 is possible to do so. */
3370 maybe_encapsulate_block (rtx first
, rtx last
, rtx equiv
)
3372 if (!flag_non_call_exceptions
|| !may_trap_p (equiv
))
3374 /* We can't attach the REG_LIBCALL and REG_RETVAL notes when the
3375 encapsulated region would not be in one basic block, i.e. when
3376 there is a control_flow_insn_p insn between FIRST and LAST. */
3377 bool attach_libcall_retval_notes
= true;
3378 rtx insn
, next
= NEXT_INSN (last
);
3380 for (insn
= first
; insn
!= next
; insn
= NEXT_INSN (insn
))
3381 if (control_flow_insn_p (insn
))
3383 attach_libcall_retval_notes
= false;
3387 if (attach_libcall_retval_notes
)
3389 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
3391 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
,
3397 /* Emit code to perform a series of operations on a multi-word quantity, one
3400 Such a block is preceded by a CLOBBER of the output, consists of multiple
3401 insns, each setting one word of the output, and followed by a SET copying
3402 the output to itself.
3404 Each of the insns setting words of the output receives a REG_NO_CONFLICT
3405 note indicating that it doesn't conflict with the (also multi-word)
3406 inputs. The entire block is surrounded by REG_LIBCALL and REG_RETVAL
3409 INSNS is a block of code generated to perform the operation, not including
3410 the CLOBBER and final copy. All insns that compute intermediate values
3411 are first emitted, followed by the block as described above.
3413 TARGET, OP0, and OP1 are the output and inputs of the operations,
3414 respectively. OP1 may be zero for a unary operation.
3416 EQUIV, if nonzero, is an expression to be placed into a REG_EQUAL note
3419 If TARGET is not a register, INSNS is simply emitted with no special
3420 processing. Likewise if anything in INSNS is not an INSN or if
3421 there is a libcall block inside INSNS.
3423 The final insn emitted is returned. */
3426 emit_no_conflict_block (rtx insns
, rtx target
, rtx op0
, rtx op1
, rtx equiv
)
3428 rtx prev
, next
, first
, last
, insn
;
3430 if (!REG_P (target
) || reload_in_progress
)
3431 return emit_insn (insns
);
3433 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3434 if (!NONJUMP_INSN_P (insn
)
3435 || find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
))
3436 return emit_insn (insns
);
3438 /* First emit all insns that do not store into words of the output and remove
3439 these from the list. */
3440 for (insn
= insns
; insn
; insn
= next
)
3443 struct no_conflict_data data
;
3445 next
= NEXT_INSN (insn
);
3447 /* Some ports (cris) create a libcall regions at their own. We must
3448 avoid any potential nesting of LIBCALLs. */
3449 if ((note
= find_reg_note (insn
, REG_LIBCALL
, NULL
)) != NULL
)
3450 remove_note (insn
, note
);
3451 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL
)) != NULL
)
3452 remove_note (insn
, note
);
3454 data
.target
= target
;
3458 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3459 if (! data
.must_stay
)
3461 if (PREV_INSN (insn
))
3462 NEXT_INSN (PREV_INSN (insn
)) = next
;
3467 PREV_INSN (next
) = PREV_INSN (insn
);
3473 prev
= get_last_insn ();
3475 /* Now write the CLOBBER of the output, followed by the setting of each
3476 of the words, followed by the final copy. */
3477 if (target
!= op0
&& target
!= op1
)
3478 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
3480 for (insn
= insns
; insn
; insn
= next
)
3482 next
= NEXT_INSN (insn
);
3485 if (op1
&& REG_P (op1
))
3486 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT
, op1
,
3489 if (op0
&& REG_P (op0
))
3490 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT
, op0
,
3494 if (mov_optab
->handlers
[(int) GET_MODE (target
)].insn_code
3495 != CODE_FOR_nothing
)
3497 last
= emit_move_insn (target
, target
);
3499 set_unique_reg_note (last
, REG_EQUAL
, equiv
);
3503 last
= get_last_insn ();
3505 /* Remove any existing REG_EQUAL note from "last", or else it will
3506 be mistaken for a note referring to the full contents of the
3507 alleged libcall value when found together with the REG_RETVAL
3508 note added below. An existing note can come from an insn
3509 expansion at "last". */
3510 remove_note (last
, find_reg_note (last
, REG_EQUAL
, NULL_RTX
));
3514 first
= get_insns ();
3516 first
= NEXT_INSN (prev
);
3518 maybe_encapsulate_block (first
, last
, equiv
);
3523 /* Emit code to make a call to a constant function or a library call.
3525 INSNS is a list containing all insns emitted in the call.
3526 These insns leave the result in RESULT. Our block is to copy RESULT
3527 to TARGET, which is logically equivalent to EQUIV.
3529 We first emit any insns that set a pseudo on the assumption that these are
3530 loading constants into registers; doing so allows them to be safely cse'ed
3531 between blocks. Then we emit all the other insns in the block, followed by
3532 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3533 note with an operand of EQUIV.
3535 Moving assignments to pseudos outside of the block is done to improve
3536 the generated code, but is not required to generate correct code,
3537 hence being unable to move an assignment is not grounds for not making
3538 a libcall block. There are two reasons why it is safe to leave these
3539 insns inside the block: First, we know that these pseudos cannot be
3540 used in generated RTL outside the block since they are created for
3541 temporary purposes within the block. Second, CSE will not record the
3542 values of anything set inside a libcall block, so we know they must
3543 be dead at the end of the block.
3545 Except for the first group of insns (the ones setting pseudos), the
3546 block is delimited by REG_RETVAL and REG_LIBCALL notes. */
3549 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
3551 rtx final_dest
= target
;
3552 rtx prev
, next
, first
, last
, insn
;
3554 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3555 into a MEM later. Protect the libcall block from this change. */
3556 if (! REG_P (target
) || REG_USERVAR_P (target
))
3557 target
= gen_reg_rtx (GET_MODE (target
));
3559 /* If we're using non-call exceptions, a libcall corresponding to an
3560 operation that may trap may also trap. */
3561 if (flag_non_call_exceptions
&& may_trap_p (equiv
))
3563 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3566 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3568 if (note
!= 0 && INTVAL (XEXP (note
, 0)) <= 0)
3569 remove_note (insn
, note
);
3573 /* look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3574 reg note to indicate that this call cannot throw or execute a nonlocal
3575 goto (unless there is already a REG_EH_REGION note, in which case
3577 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3580 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3583 XEXP (note
, 0) = constm1_rtx
;
3585 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EH_REGION
, constm1_rtx
,
3589 /* First emit all insns that set pseudos. Remove them from the list as
3590 we go. Avoid insns that set pseudos which were referenced in previous
3591 insns. These can be generated by move_by_pieces, for example,
3592 to update an address. Similarly, avoid insns that reference things
3593 set in previous insns. */
3595 for (insn
= insns
; insn
; insn
= next
)
3597 rtx set
= single_set (insn
);
3600 /* Some ports (cris) create a libcall regions at their own. We must
3601 avoid any potential nesting of LIBCALLs. */
3602 if ((note
= find_reg_note (insn
, REG_LIBCALL
, NULL
)) != NULL
)
3603 remove_note (insn
, note
);
3604 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL
)) != NULL
)
3605 remove_note (insn
, note
);
3607 next
= NEXT_INSN (insn
);
3609 if (set
!= 0 && REG_P (SET_DEST (set
))
3610 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3612 struct no_conflict_data data
;
3614 data
.target
= const0_rtx
;
3618 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3619 if (! data
.must_stay
)
3621 if (PREV_INSN (insn
))
3622 NEXT_INSN (PREV_INSN (insn
)) = next
;
3627 PREV_INSN (next
) = PREV_INSN (insn
);
3633 /* Some ports use a loop to copy large arguments onto the stack.
3634 Don't move anything outside such a loop. */
3639 prev
= get_last_insn ();
3641 /* Write the remaining insns followed by the final copy. */
3643 for (insn
= insns
; insn
; insn
= next
)
3645 next
= NEXT_INSN (insn
);
3650 last
= emit_move_insn (target
, result
);
3651 if (mov_optab
->handlers
[(int) GET_MODE (target
)].insn_code
3652 != CODE_FOR_nothing
)
3653 set_unique_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
));
3656 /* Remove any existing REG_EQUAL note from "last", or else it will
3657 be mistaken for a note referring to the full contents of the
3658 libcall value when found together with the REG_RETVAL note added
3659 below. An existing note can come from an insn expansion at
3661 remove_note (last
, find_reg_note (last
, REG_EQUAL
, NULL_RTX
));
3664 if (final_dest
!= target
)
3665 emit_move_insn (final_dest
, target
);
3668 first
= get_insns ();
3670 first
= NEXT_INSN (prev
);
3672 maybe_encapsulate_block (first
, last
, equiv
);
3675 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
3676 PURPOSE describes how this comparison will be used. CODE is the rtx
3677 comparison code we will be using.
3679 ??? Actually, CODE is slightly weaker than that. A target is still
3680 required to implement all of the normal bcc operations, but not
3681 required to implement all (or any) of the unordered bcc operations. */
3684 can_compare_p (enum rtx_code code
, enum machine_mode mode
,
3685 enum can_compare_purpose purpose
)
3689 if (cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3691 if (purpose
== ccp_jump
)
3692 return bcc_gen_fctn
[(int) code
] != NULL
;
3693 else if (purpose
== ccp_store_flag
)
3694 return setcc_gen_code
[(int) code
] != CODE_FOR_nothing
;
3696 /* There's only one cmov entry point, and it's allowed to fail. */
3699 if (purpose
== ccp_jump
3700 && cbranch_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3702 if (purpose
== ccp_cmov
3703 && cmov_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3705 if (purpose
== ccp_store_flag
3706 && cstore_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3708 mode
= GET_MODE_WIDER_MODE (mode
);
3710 while (mode
!= VOIDmode
);
3715 /* This function is called when we are going to emit a compare instruction that
3716 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
3718 *PMODE is the mode of the inputs (in case they are const_int).
3719 *PUNSIGNEDP nonzero says that the operands are unsigned;
3720 this matters if they need to be widened.
3722 If they have mode BLKmode, then SIZE specifies the size of both operands.
3724 This function performs all the setup necessary so that the caller only has
3725 to emit a single comparison insn. This setup can involve doing a BLKmode
3726 comparison or emitting a library call to perform the comparison if no insn
3727 is available to handle it.
3728 The values which are passed in through pointers can be modified; the caller
3729 should perform the comparison on the modified values. Constant
3730 comparisons must have already been folded. */
3733 prepare_cmp_insn (rtx
*px
, rtx
*py
, enum rtx_code
*pcomparison
, rtx size
,
3734 enum machine_mode
*pmode
, int *punsignedp
,
3735 enum can_compare_purpose purpose
)
3737 enum machine_mode mode
= *pmode
;
3738 rtx x
= *px
, y
= *py
;
3739 int unsignedp
= *punsignedp
;
3741 /* If we are inside an appropriately-short loop and we are optimizing,
3742 force expensive constants into a register. */
3743 if (CONSTANT_P (x
) && optimize
3744 && rtx_cost (x
, COMPARE
) > COSTS_N_INSNS (1))
3745 x
= force_reg (mode
, x
);
3747 if (CONSTANT_P (y
) && optimize
3748 && rtx_cost (y
, COMPARE
) > COSTS_N_INSNS (1))
3749 y
= force_reg (mode
, y
);
3752 /* Make sure if we have a canonical comparison. The RTL
3753 documentation states that canonical comparisons are required only
3754 for targets which have cc0. */
3755 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
3758 /* Don't let both operands fail to indicate the mode. */
3759 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
3760 x
= force_reg (mode
, x
);
3762 /* Handle all BLKmode compares. */
3764 if (mode
== BLKmode
)
3766 enum machine_mode cmp_mode
, result_mode
;
3767 enum insn_code cmp_code
;
3772 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
3776 /* Try to use a memory block compare insn - either cmpstr
3777 or cmpmem will do. */
3778 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
3779 cmp_mode
!= VOIDmode
;
3780 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
3782 cmp_code
= cmpmem_optab
[cmp_mode
];
3783 if (cmp_code
== CODE_FOR_nothing
)
3784 cmp_code
= cmpstr_optab
[cmp_mode
];
3785 if (cmp_code
== CODE_FOR_nothing
)
3786 cmp_code
= cmpstrn_optab
[cmp_mode
];
3787 if (cmp_code
== CODE_FOR_nothing
)
3790 /* Must make sure the size fits the insn's mode. */
3791 if ((GET_CODE (size
) == CONST_INT
3792 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
3793 || (GET_MODE_BITSIZE (GET_MODE (size
))
3794 > GET_MODE_BITSIZE (cmp_mode
)))
3797 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
3798 result
= gen_reg_rtx (result_mode
);
3799 size
= convert_to_mode (cmp_mode
, size
, 1);
3800 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
3804 *pmode
= result_mode
;
3808 /* Otherwise call a library function, memcmp. */
3809 libfunc
= memcmp_libfunc
;
3810 length_type
= sizetype
;
3811 result_mode
= TYPE_MODE (integer_type_node
);
3812 cmp_mode
= TYPE_MODE (length_type
);
3813 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
3814 TYPE_UNSIGNED (length_type
));
3816 result
= emit_library_call_value (libfunc
, 0, LCT_PURE_MAKE_BLOCK
,
3823 *pmode
= result_mode
;
3827 /* Don't allow operands to the compare to trap, as that can put the
3828 compare and branch in different basic blocks. */
3829 if (flag_non_call_exceptions
)
3832 x
= force_reg (mode
, x
);
3834 y
= force_reg (mode
, y
);
3839 if (can_compare_p (*pcomparison
, mode
, purpose
))
3842 /* Handle a lib call just for the mode we are using. */
3844 if (cmp_optab
->handlers
[(int) mode
].libfunc
&& !SCALAR_FLOAT_MODE_P (mode
))
3846 rtx libfunc
= cmp_optab
->handlers
[(int) mode
].libfunc
;
3849 /* If we want unsigned, and this mode has a distinct unsigned
3850 comparison routine, use that. */
3851 if (unsignedp
&& ucmp_optab
->handlers
[(int) mode
].libfunc
)
3852 libfunc
= ucmp_optab
->handlers
[(int) mode
].libfunc
;
3854 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST_MAKE_BLOCK
,
3855 word_mode
, 2, x
, mode
, y
, mode
);
3857 /* There are two kinds of comparison routines. Biased routines
3858 return 0/1/2, and unbiased routines return -1/0/1. Other parts
3859 of gcc expect that the comparison operation is equivalent
3860 to the modified comparison. For signed comparisons compare the
3861 result against 1 in the biased case, and zero in the unbiased
3862 case. For unsigned comparisons always compare against 1 after
3863 biasing the unbiased result by adding 1. This gives us a way to
3869 if (!TARGET_LIB_INT_CMP_BIASED
)
3872 *px
= plus_constant (result
, 1);
3879 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3880 prepare_float_lib_cmp (px
, py
, pcomparison
, pmode
, punsignedp
);
3883 /* Before emitting an insn with code ICODE, make sure that X, which is going
3884 to be used for operand OPNUM of the insn, is converted from mode MODE to
3885 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
3886 that it is accepted by the operand predicate. Return the new value. */
3889 prepare_operand (int icode
, rtx x
, int opnum
, enum machine_mode mode
,
3890 enum machine_mode wider_mode
, int unsignedp
)
3892 if (mode
!= wider_mode
)
3893 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
3895 if (!insn_data
[icode
].operand
[opnum
].predicate
3896 (x
, insn_data
[icode
].operand
[opnum
].mode
))
3900 x
= copy_to_mode_reg (insn_data
[icode
].operand
[opnum
].mode
, x
);
3906 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
3907 we can do the comparison.
3908 The arguments are the same as for emit_cmp_and_jump_insns; but LABEL may
3909 be NULL_RTX which indicates that only a comparison is to be generated. */
3912 emit_cmp_and_jump_insn_1 (rtx x
, rtx y
, enum machine_mode mode
,
3913 enum rtx_code comparison
, int unsignedp
, rtx label
)
3915 rtx test
= gen_rtx_fmt_ee (comparison
, mode
, x
, y
);
3916 enum mode_class
class = GET_MODE_CLASS (mode
);
3917 enum machine_mode wider_mode
= mode
;
3919 /* Try combined insns first. */
3922 enum insn_code icode
;
3923 PUT_MODE (test
, wider_mode
);
3927 icode
= cbranch_optab
->handlers
[(int) wider_mode
].insn_code
;
3929 if (icode
!= CODE_FOR_nothing
3930 && insn_data
[icode
].operand
[0].predicate (test
, wider_mode
))
3932 x
= prepare_operand (icode
, x
, 1, mode
, wider_mode
, unsignedp
);
3933 y
= prepare_operand (icode
, y
, 2, mode
, wider_mode
, unsignedp
);
3934 emit_jump_insn (GEN_FCN (icode
) (test
, x
, y
, label
));
3939 /* Handle some compares against zero. */
3940 icode
= (int) tst_optab
->handlers
[(int) wider_mode
].insn_code
;
3941 if (y
== CONST0_RTX (mode
) && icode
!= CODE_FOR_nothing
)
3943 x
= prepare_operand (icode
, x
, 0, mode
, wider_mode
, unsignedp
);
3944 emit_insn (GEN_FCN (icode
) (x
));
3946 emit_jump_insn (bcc_gen_fctn
[(int) comparison
] (label
));
3950 /* Handle compares for which there is a directly suitable insn. */
3952 icode
= (int) cmp_optab
->handlers
[(int) wider_mode
].insn_code
;
3953 if (icode
!= CODE_FOR_nothing
)
3955 x
= prepare_operand (icode
, x
, 0, mode
, wider_mode
, unsignedp
);
3956 y
= prepare_operand (icode
, y
, 1, mode
, wider_mode
, unsignedp
);
3957 emit_insn (GEN_FCN (icode
) (x
, y
));
3959 emit_jump_insn (bcc_gen_fctn
[(int) comparison
] (label
));
3963 if (!CLASS_HAS_WIDER_MODES_P (class))
3966 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
);
3968 while (wider_mode
!= VOIDmode
);
3973 /* Generate code to compare X with Y so that the condition codes are
3974 set and to jump to LABEL if the condition is true. If X is a
3975 constant and Y is not a constant, then the comparison is swapped to
3976 ensure that the comparison RTL has the canonical form.
3978 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
3979 need to be widened by emit_cmp_insn. UNSIGNEDP is also used to select
3980 the proper branch condition code.
3982 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
3984 MODE is the mode of the inputs (in case they are const_int).
3986 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). It will
3987 be passed unchanged to emit_cmp_insn, then potentially converted into an
3988 unsigned variant based on UNSIGNEDP to select a proper jump instruction. */
3991 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
3992 enum machine_mode mode
, int unsignedp
, rtx label
)
3994 rtx op0
= x
, op1
= y
;
3996 /* Swap operands and condition to ensure canonical RTL. */
3997 if (swap_commutative_operands_p (x
, y
))
3999 /* If we're not emitting a branch, this means some caller
4004 comparison
= swap_condition (comparison
);
4008 /* If OP0 is still a constant, then both X and Y must be constants.
4009 Force X into a register to create canonical RTL. */
4010 if (CONSTANT_P (op0
))
4011 op0
= force_reg (mode
, op0
);
4015 comparison
= unsigned_condition (comparison
);
4017 prepare_cmp_insn (&op0
, &op1
, &comparison
, size
, &mode
, &unsignedp
,
4019 emit_cmp_and_jump_insn_1 (op0
, op1
, mode
, comparison
, unsignedp
, label
);
4022 /* Like emit_cmp_and_jump_insns, but generate only the comparison. */
4025 emit_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4026 enum machine_mode mode
, int unsignedp
)
4028 emit_cmp_and_jump_insns (x
, y
, comparison
, size
, mode
, unsignedp
, 0);
4031 /* Emit a library call comparison between floating point X and Y.
4032 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4035 prepare_float_lib_cmp (rtx
*px
, rtx
*py
, enum rtx_code
*pcomparison
,
4036 enum machine_mode
*pmode
, int *punsignedp
)
4038 enum rtx_code comparison
= *pcomparison
;
4039 enum rtx_code swapped
= swap_condition (comparison
);
4040 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4043 enum machine_mode orig_mode
= GET_MODE (x
);
4044 enum machine_mode mode
;
4045 rtx value
, target
, insns
, equiv
;
4047 bool reversed_p
= false;
4049 for (mode
= orig_mode
;
4051 mode
= GET_MODE_WIDER_MODE (mode
))
4053 if ((libfunc
= code_to_optab
[comparison
]->handlers
[mode
].libfunc
))
4056 if ((libfunc
= code_to_optab
[swapped
]->handlers
[mode
].libfunc
))
4059 tmp
= x
; x
= y
; y
= tmp
;
4060 comparison
= swapped
;
4064 if ((libfunc
= code_to_optab
[reversed
]->handlers
[mode
].libfunc
)
4065 && FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, reversed
))
4067 comparison
= reversed
;
4073 gcc_assert (mode
!= VOIDmode
);
4075 if (mode
!= orig_mode
)
4077 x
= convert_to_mode (mode
, x
, 0);
4078 y
= convert_to_mode (mode
, y
, 0);
4081 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4082 the RTL. The allows the RTL optimizers to delete the libcall if the
4083 condition can be determined at compile-time. */
4084 if (comparison
== UNORDERED
)
4086 rtx temp
= simplify_gen_relational (NE
, word_mode
, mode
, x
, x
);
4087 equiv
= simplify_gen_relational (NE
, word_mode
, mode
, y
, y
);
4088 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, word_mode
, word_mode
,
4089 temp
, const_true_rtx
, equiv
);
4093 equiv
= simplify_gen_relational (comparison
, word_mode
, mode
, x
, y
);
4094 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4096 rtx true_rtx
, false_rtx
;
4101 true_rtx
= const0_rtx
;
4102 false_rtx
= const_true_rtx
;
4106 true_rtx
= const_true_rtx
;
4107 false_rtx
= const0_rtx
;
4111 true_rtx
= const1_rtx
;
4112 false_rtx
= const0_rtx
;
4116 true_rtx
= const0_rtx
;
4117 false_rtx
= constm1_rtx
;
4121 true_rtx
= constm1_rtx
;
4122 false_rtx
= const0_rtx
;
4126 true_rtx
= const0_rtx
;
4127 false_rtx
= const1_rtx
;
4133 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, word_mode
, word_mode
,
4134 equiv
, true_rtx
, false_rtx
);
4139 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4140 word_mode
, 2, x
, mode
, y
, mode
);
4141 insns
= get_insns ();
4144 target
= gen_reg_rtx (word_mode
);
4145 emit_libcall_block (insns
, target
, value
, equiv
);
4147 if (comparison
== UNORDERED
4148 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4149 comparison
= reversed_p
? EQ
: NE
;
4154 *pcomparison
= comparison
;
4158 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4161 emit_indirect_jump (rtx loc
)
4163 if (!insn_data
[(int) CODE_FOR_indirect_jump
].operand
[0].predicate
4165 loc
= copy_to_mode_reg (Pmode
, loc
);
4167 emit_jump_insn (gen_indirect_jump (loc
));
4171 #ifdef HAVE_conditional_move
4173 /* Emit a conditional move instruction if the machine supports one for that
4174 condition and machine mode.
4176 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4177 the mode to use should they be constants. If it is VOIDmode, they cannot
4180 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4181 should be stored there. MODE is the mode to use should they be constants.
4182 If it is VOIDmode, they cannot both be constants.
4184 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4185 is not supported. */
4188 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4189 enum machine_mode cmode
, rtx op2
, rtx op3
,
4190 enum machine_mode mode
, int unsignedp
)
4192 rtx tem
, subtarget
, comparison
, insn
;
4193 enum insn_code icode
;
4194 enum rtx_code reversed
;
4196 /* If one operand is constant, make it the second one. Only do this
4197 if the other operand is not constant as well. */
4199 if (swap_commutative_operands_p (op0
, op1
))
4204 code
= swap_condition (code
);
4207 /* get_condition will prefer to generate LT and GT even if the old
4208 comparison was against zero, so undo that canonicalization here since
4209 comparisons against zero are cheaper. */
4210 if (code
== LT
&& op1
== const1_rtx
)
4211 code
= LE
, op1
= const0_rtx
;
4212 else if (code
== GT
&& op1
== constm1_rtx
)
4213 code
= GE
, op1
= const0_rtx
;
4215 if (cmode
== VOIDmode
)
4216 cmode
= GET_MODE (op0
);
4218 if (swap_commutative_operands_p (op2
, op3
)
4219 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4228 if (mode
== VOIDmode
)
4229 mode
= GET_MODE (op2
);
4231 icode
= movcc_gen_code
[mode
];
4233 if (icode
== CODE_FOR_nothing
)
4237 target
= gen_reg_rtx (mode
);
4241 /* If the insn doesn't accept these operands, put them in pseudos. */
4243 if (!insn_data
[icode
].operand
[0].predicate
4244 (subtarget
, insn_data
[icode
].operand
[0].mode
))
4245 subtarget
= gen_reg_rtx (insn_data
[icode
].operand
[0].mode
);
4247 if (!insn_data
[icode
].operand
[2].predicate
4248 (op2
, insn_data
[icode
].operand
[2].mode
))
4249 op2
= copy_to_mode_reg (insn_data
[icode
].operand
[2].mode
, op2
);
4251 if (!insn_data
[icode
].operand
[3].predicate
4252 (op3
, insn_data
[icode
].operand
[3].mode
))
4253 op3
= copy_to_mode_reg (insn_data
[icode
].operand
[3].mode
, op3
);
4255 /* Everything should now be in the suitable form, so emit the compare insn
4256 and then the conditional move. */
4259 = compare_from_rtx (op0
, op1
, code
, unsignedp
, cmode
, NULL_RTX
);
4261 /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */
4262 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4263 return NULL and let the caller figure out how best to deal with this
4265 if (GET_CODE (comparison
) != code
)
4268 insn
= GEN_FCN (icode
) (subtarget
, comparison
, op2
, op3
);
4270 /* If that failed, then give up. */
4276 if (subtarget
!= target
)
4277 convert_move (target
, subtarget
, 0);
4282 /* Return nonzero if a conditional move of mode MODE is supported.
4284 This function is for combine so it can tell whether an insn that looks
4285 like a conditional move is actually supported by the hardware. If we
4286 guess wrong we lose a bit on optimization, but that's it. */
4287 /* ??? sparc64 supports conditionally moving integers values based on fp
4288 comparisons, and vice versa. How do we handle them? */
4291 can_conditionally_move_p (enum machine_mode mode
)
4293 if (movcc_gen_code
[mode
] != CODE_FOR_nothing
)
4299 #endif /* HAVE_conditional_move */
4301 /* Emit a conditional addition instruction if the machine supports one for that
4302 condition and machine mode.
4304 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4305 the mode to use should they be constants. If it is VOIDmode, they cannot
4308 OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3
4309 should be stored there. MODE is the mode to use should they be constants.
4310 If it is VOIDmode, they cannot both be constants.
4312 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4313 is not supported. */
4316 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4317 enum machine_mode cmode
, rtx op2
, rtx op3
,
4318 enum machine_mode mode
, int unsignedp
)
4320 rtx tem
, subtarget
, comparison
, insn
;
4321 enum insn_code icode
;
4322 enum rtx_code reversed
;
4324 /* If one operand is constant, make it the second one. Only do this
4325 if the other operand is not constant as well. */
4327 if (swap_commutative_operands_p (op0
, op1
))
4332 code
= swap_condition (code
);
4335 /* get_condition will prefer to generate LT and GT even if the old
4336 comparison was against zero, so undo that canonicalization here since
4337 comparisons against zero are cheaper. */
4338 if (code
== LT
&& op1
== const1_rtx
)
4339 code
= LE
, op1
= const0_rtx
;
4340 else if (code
== GT
&& op1
== constm1_rtx
)
4341 code
= GE
, op1
= const0_rtx
;
4343 if (cmode
== VOIDmode
)
4344 cmode
= GET_MODE (op0
);
4346 if (swap_commutative_operands_p (op2
, op3
)
4347 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4356 if (mode
== VOIDmode
)
4357 mode
= GET_MODE (op2
);
4359 icode
= addcc_optab
->handlers
[(int) mode
].insn_code
;
4361 if (icode
== CODE_FOR_nothing
)
4365 target
= gen_reg_rtx (mode
);
4367 /* If the insn doesn't accept these operands, put them in pseudos. */
4369 if (!insn_data
[icode
].operand
[0].predicate
4370 (target
, insn_data
[icode
].operand
[0].mode
))
4371 subtarget
= gen_reg_rtx (insn_data
[icode
].operand
[0].mode
);
4375 if (!insn_data
[icode
].operand
[2].predicate
4376 (op2
, insn_data
[icode
].operand
[2].mode
))
4377 op2
= copy_to_mode_reg (insn_data
[icode
].operand
[2].mode
, op2
);
4379 if (!insn_data
[icode
].operand
[3].predicate
4380 (op3
, insn_data
[icode
].operand
[3].mode
))
4381 op3
= copy_to_mode_reg (insn_data
[icode
].operand
[3].mode
, op3
);
4383 /* Everything should now be in the suitable form, so emit the compare insn
4384 and then the conditional move. */
4387 = compare_from_rtx (op0
, op1
, code
, unsignedp
, cmode
, NULL_RTX
);
4389 /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */
4390 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4391 return NULL and let the caller figure out how best to deal with this
4393 if (GET_CODE (comparison
) != code
)
4396 insn
= GEN_FCN (icode
) (subtarget
, comparison
, op2
, op3
);
4398 /* If that failed, then give up. */
4404 if (subtarget
!= target
)
4405 convert_move (target
, subtarget
, 0);
4410 /* These functions attempt to generate an insn body, rather than
4411 emitting the insn, but if the gen function already emits them, we
4412 make no attempt to turn them back into naked patterns. */
4414 /* Generate and return an insn body to add Y to X. */
4417 gen_add2_insn (rtx x
, rtx y
)
4419 int icode
= (int) add_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
4421 gcc_assert (insn_data
[icode
].operand
[0].predicate
4422 (x
, insn_data
[icode
].operand
[0].mode
));
4423 gcc_assert (insn_data
[icode
].operand
[1].predicate
4424 (x
, insn_data
[icode
].operand
[1].mode
));
4425 gcc_assert (insn_data
[icode
].operand
[2].predicate
4426 (y
, insn_data
[icode
].operand
[2].mode
));
4428 return GEN_FCN (icode
) (x
, x
, y
);
4431 /* Generate and return an insn body to add r1 and c,
4432 storing the result in r0. */
4434 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4436 int icode
= (int) add_optab
->handlers
[(int) GET_MODE (r0
)].insn_code
;
4438 if (icode
== CODE_FOR_nothing
4439 || !(insn_data
[icode
].operand
[0].predicate
4440 (r0
, insn_data
[icode
].operand
[0].mode
))
4441 || !(insn_data
[icode
].operand
[1].predicate
4442 (r1
, insn_data
[icode
].operand
[1].mode
))
4443 || !(insn_data
[icode
].operand
[2].predicate
4444 (c
, insn_data
[icode
].operand
[2].mode
)))
4447 return GEN_FCN (icode
) (r0
, r1
, c
);
4451 have_add2_insn (rtx x
, rtx y
)
4455 gcc_assert (GET_MODE (x
) != VOIDmode
);
4457 icode
= (int) add_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
4459 if (icode
== CODE_FOR_nothing
)
4462 if (!(insn_data
[icode
].operand
[0].predicate
4463 (x
, insn_data
[icode
].operand
[0].mode
))
4464 || !(insn_data
[icode
].operand
[1].predicate
4465 (x
, insn_data
[icode
].operand
[1].mode
))
4466 || !(insn_data
[icode
].operand
[2].predicate
4467 (y
, insn_data
[icode
].operand
[2].mode
)))
4473 /* Generate and return an insn body to subtract Y from X. */
4476 gen_sub2_insn (rtx x
, rtx y
)
4478 int icode
= (int) sub_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
4480 gcc_assert (insn_data
[icode
].operand
[0].predicate
4481 (x
, insn_data
[icode
].operand
[0].mode
));
4482 gcc_assert (insn_data
[icode
].operand
[1].predicate
4483 (x
, insn_data
[icode
].operand
[1].mode
));
4484 gcc_assert (insn_data
[icode
].operand
[2].predicate
4485 (y
, insn_data
[icode
].operand
[2].mode
));
4487 return GEN_FCN (icode
) (x
, x
, y
);
4490 /* Generate and return an insn body to subtract r1 and c,
4491 storing the result in r0. */
4493 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4495 int icode
= (int) sub_optab
->handlers
[(int) GET_MODE (r0
)].insn_code
;
4497 if (icode
== CODE_FOR_nothing
4498 || !(insn_data
[icode
].operand
[0].predicate
4499 (r0
, insn_data
[icode
].operand
[0].mode
))
4500 || !(insn_data
[icode
].operand
[1].predicate
4501 (r1
, insn_data
[icode
].operand
[1].mode
))
4502 || !(insn_data
[icode
].operand
[2].predicate
4503 (c
, insn_data
[icode
].operand
[2].mode
)))
4506 return GEN_FCN (icode
) (r0
, r1
, c
);
4510 have_sub2_insn (rtx x
, rtx y
)
4514 gcc_assert (GET_MODE (x
) != VOIDmode
);
4516 icode
= (int) sub_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
4518 if (icode
== CODE_FOR_nothing
)
4521 if (!(insn_data
[icode
].operand
[0].predicate
4522 (x
, insn_data
[icode
].operand
[0].mode
))
4523 || !(insn_data
[icode
].operand
[1].predicate
4524 (x
, insn_data
[icode
].operand
[1].mode
))
4525 || !(insn_data
[icode
].operand
[2].predicate
4526 (y
, insn_data
[icode
].operand
[2].mode
)))
4532 /* Generate the body of an instruction to copy Y into X.
4533 It may be a list of insns, if one insn isn't enough. */
4536 gen_move_insn (rtx x
, rtx y
)
4541 emit_move_insn_1 (x
, y
);
4547 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4548 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4549 no such operation exists, CODE_FOR_nothing will be returned. */
4552 can_extend_p (enum machine_mode to_mode
, enum machine_mode from_mode
,
4556 #ifdef HAVE_ptr_extend
4558 return CODE_FOR_ptr_extend
;
4561 tab
= unsignedp
? zext_optab
: sext_optab
;
4562 return tab
->handlers
[to_mode
][from_mode
].insn_code
;
4565 /* Generate the body of an insn to extend Y (with mode MFROM)
4566 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4569 gen_extend_insn (rtx x
, rtx y
, enum machine_mode mto
,
4570 enum machine_mode mfrom
, int unsignedp
)
4572 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4573 return GEN_FCN (icode
) (x
, y
);
4576 /* can_fix_p and can_float_p say whether the target machine
4577 can directly convert a given fixed point type to
4578 a given floating point type, or vice versa.
4579 The returned value is the CODE_FOR_... value to use,
4580 or CODE_FOR_nothing if these modes cannot be directly converted.
4582 *TRUNCP_PTR is set to 1 if it is necessary to output
4583 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4585 static enum insn_code
4586 can_fix_p (enum machine_mode fixmode
, enum machine_mode fltmode
,
4587 int unsignedp
, int *truncp_ptr
)
4590 enum insn_code icode
;
4592 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4593 icode
= tab
->handlers
[fixmode
][fltmode
].insn_code
;
4594 if (icode
!= CODE_FOR_nothing
)
4600 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4601 for this to work. We need to rework the fix* and ftrunc* patterns
4602 and documentation. */
4603 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4604 icode
= tab
->handlers
[fixmode
][fltmode
].insn_code
;
4605 if (icode
!= CODE_FOR_nothing
4606 && ftrunc_optab
->handlers
[fltmode
].insn_code
!= CODE_FOR_nothing
)
4613 return CODE_FOR_nothing
;
4616 static enum insn_code
4617 can_float_p (enum machine_mode fltmode
, enum machine_mode fixmode
,
4622 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4623 return tab
->handlers
[fltmode
][fixmode
].insn_code
;
4626 /* Generate code to convert FROM to floating point
4627 and store in TO. FROM must be fixed point and not VOIDmode.
4628 UNSIGNEDP nonzero means regard FROM as unsigned.
4629 Normally this is done by correcting the final value
4630 if it is negative. */
4633 expand_float (rtx to
, rtx from
, int unsignedp
)
4635 enum insn_code icode
;
4637 enum machine_mode fmode
, imode
;
4638 bool can_do_signed
= false;
4640 /* Crash now, because we won't be able to decide which mode to use. */
4641 gcc_assert (GET_MODE (from
) != VOIDmode
);
4643 /* Look for an insn to do the conversion. Do it in the specified
4644 modes if possible; otherwise convert either input, output or both to
4645 wider mode. If the integer mode is wider than the mode of FROM,
4646 we can do the conversion signed even if the input is unsigned. */
4648 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
4649 fmode
= GET_MODE_WIDER_MODE (fmode
))
4650 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
4651 imode
= GET_MODE_WIDER_MODE (imode
))
4653 int doing_unsigned
= unsignedp
;
4655 if (fmode
!= GET_MODE (to
)
4656 && significand_size (fmode
) < GET_MODE_BITSIZE (GET_MODE (from
)))
4659 icode
= can_float_p (fmode
, imode
, unsignedp
);
4660 if (icode
== CODE_FOR_nothing
&& unsignedp
)
4662 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
4663 if (scode
!= CODE_FOR_nothing
)
4664 can_do_signed
= true;
4665 if (imode
!= GET_MODE (from
))
4666 icode
= scode
, doing_unsigned
= 0;
4669 if (icode
!= CODE_FOR_nothing
)
4671 if (imode
!= GET_MODE (from
))
4672 from
= convert_to_mode (imode
, from
, unsignedp
);
4674 if (fmode
!= GET_MODE (to
))
4675 target
= gen_reg_rtx (fmode
);
4677 emit_unop_insn (icode
, target
, from
,
4678 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
4681 convert_move (to
, target
, 0);
4686 /* Unsigned integer, and no way to convert directly. For binary
4687 floating point modes, convert as signed, then conditionally adjust
4689 if (unsignedp
&& can_do_signed
&& !DECIMAL_FLOAT_MODE_P (GET_MODE (to
)))
4691 rtx label
= gen_label_rtx ();
4693 REAL_VALUE_TYPE offset
;
4695 /* Look for a usable floating mode FMODE wider than the source and at
4696 least as wide as the target. Using FMODE will avoid rounding woes
4697 with unsigned values greater than the signed maximum value. */
4699 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
4700 fmode
= GET_MODE_WIDER_MODE (fmode
))
4701 if (GET_MODE_BITSIZE (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
4702 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
4705 if (fmode
== VOIDmode
)
4707 /* There is no such mode. Pretend the target is wide enough. */
4708 fmode
= GET_MODE (to
);
4710 /* Avoid double-rounding when TO is narrower than FROM. */
4711 if ((significand_size (fmode
) + 1)
4712 < GET_MODE_BITSIZE (GET_MODE (from
)))
4715 rtx neglabel
= gen_label_rtx ();
4717 /* Don't use TARGET if it isn't a register, is a hard register,
4718 or is the wrong mode. */
4720 || REGNO (target
) < FIRST_PSEUDO_REGISTER
4721 || GET_MODE (target
) != fmode
)
4722 target
= gen_reg_rtx (fmode
);
4724 imode
= GET_MODE (from
);
4725 do_pending_stack_adjust ();
4727 /* Test whether the sign bit is set. */
4728 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
4731 /* The sign bit is not set. Convert as signed. */
4732 expand_float (target
, from
, 0);
4733 emit_jump_insn (gen_jump (label
));
4736 /* The sign bit is set.
4737 Convert to a usable (positive signed) value by shifting right
4738 one bit, while remembering if a nonzero bit was shifted
4739 out; i.e., compute (from & 1) | (from >> 1). */
4741 emit_label (neglabel
);
4742 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
4743 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4744 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, integer_one_node
,
4746 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
4748 expand_float (target
, temp
, 0);
4750 /* Multiply by 2 to undo the shift above. */
4751 temp
= expand_binop (fmode
, add_optab
, target
, target
,
4752 target
, 0, OPTAB_LIB_WIDEN
);
4754 emit_move_insn (target
, temp
);
4756 do_pending_stack_adjust ();
4762 /* If we are about to do some arithmetic to correct for an
4763 unsigned operand, do it in a pseudo-register. */
4765 if (GET_MODE (to
) != fmode
4766 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
4767 target
= gen_reg_rtx (fmode
);
4769 /* Convert as signed integer to floating. */
4770 expand_float (target
, from
, 0);
4772 /* If FROM is negative (and therefore TO is negative),
4773 correct its value by 2**bitwidth. */
4775 do_pending_stack_adjust ();
4776 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
4780 real_2expN (&offset
, GET_MODE_BITSIZE (GET_MODE (from
)));
4781 temp
= expand_binop (fmode
, add_optab
, target
,
4782 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
4783 target
, 0, OPTAB_LIB_WIDEN
);
4785 emit_move_insn (target
, temp
);
4787 do_pending_stack_adjust ();
4792 /* No hardware instruction available; call a library routine. */
4797 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4799 if (GET_MODE_SIZE (GET_MODE (from
)) < GET_MODE_SIZE (SImode
))
4800 from
= convert_to_mode (SImode
, from
, unsignedp
);
4802 libfunc
= tab
->handlers
[GET_MODE (to
)][GET_MODE (from
)].libfunc
;
4803 gcc_assert (libfunc
);
4807 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4808 GET_MODE (to
), 1, from
,
4810 insns
= get_insns ();
4813 emit_libcall_block (insns
, target
, value
,
4814 gen_rtx_FLOAT (GET_MODE (to
), from
));
4819 /* Copy result to requested destination
4820 if we have been computing in a temp location. */
4824 if (GET_MODE (target
) == GET_MODE (to
))
4825 emit_move_insn (to
, target
);
4827 convert_move (to
, target
, 0);
4831 /* Generate code to convert FROM to fixed point and store in TO. FROM
4832 must be floating point. */
4835 expand_fix (rtx to
, rtx from
, int unsignedp
)
4837 enum insn_code icode
;
4839 enum machine_mode fmode
, imode
;
4842 /* We first try to find a pair of modes, one real and one integer, at
4843 least as wide as FROM and TO, respectively, in which we can open-code
4844 this conversion. If the integer mode is wider than the mode of TO,
4845 we can do the conversion either signed or unsigned. */
4847 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
4848 fmode
= GET_MODE_WIDER_MODE (fmode
))
4849 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
4850 imode
= GET_MODE_WIDER_MODE (imode
))
4852 int doing_unsigned
= unsignedp
;
4854 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
4855 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
4856 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
4858 if (icode
!= CODE_FOR_nothing
)
4860 if (fmode
!= GET_MODE (from
))
4861 from
= convert_to_mode (fmode
, from
, 0);
4865 rtx temp
= gen_reg_rtx (GET_MODE (from
));
4866 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
4870 if (imode
!= GET_MODE (to
))
4871 target
= gen_reg_rtx (imode
);
4873 emit_unop_insn (icode
, target
, from
,
4874 doing_unsigned
? UNSIGNED_FIX
: FIX
);
4876 convert_move (to
, target
, unsignedp
);
4881 /* For an unsigned conversion, there is one more way to do it.
4882 If we have a signed conversion, we generate code that compares
4883 the real value to the largest representable positive number. If if
4884 is smaller, the conversion is done normally. Otherwise, subtract
4885 one plus the highest signed number, convert, and add it back.
4887 We only need to check all real modes, since we know we didn't find
4888 anything with a wider integer mode.
4890 This code used to extend FP value into mode wider than the destination.
4891 This is not needed. Consider, for instance conversion from SFmode
4894 The hot path through the code is dealing with inputs smaller than 2^63
4895 and doing just the conversion, so there is no bits to lose.
4897 In the other path we know the value is positive in the range 2^63..2^64-1
4898 inclusive. (as for other imput overflow happens and result is undefined)
4899 So we know that the most important bit set in mantissa corresponds to
4900 2^63. The subtraction of 2^63 should not generate any rounding as it
4901 simply clears out that bit. The rest is trivial. */
4903 if (unsignedp
&& GET_MODE_BITSIZE (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
4904 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
4905 fmode
= GET_MODE_WIDER_MODE (fmode
))
4906 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0,
4910 REAL_VALUE_TYPE offset
;
4911 rtx limit
, lab1
, lab2
, insn
;
4913 bitsize
= GET_MODE_BITSIZE (GET_MODE (to
));
4914 real_2expN (&offset
, bitsize
- 1);
4915 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
4916 lab1
= gen_label_rtx ();
4917 lab2
= gen_label_rtx ();
4919 if (fmode
!= GET_MODE (from
))
4920 from
= convert_to_mode (fmode
, from
, 0);
4922 /* See if we need to do the subtraction. */
4923 do_pending_stack_adjust ();
4924 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
4927 /* If not, do the signed "fix" and branch around fixup code. */
4928 expand_fix (to
, from
, 0);
4929 emit_jump_insn (gen_jump (lab2
));
4932 /* Otherwise, subtract 2**(N-1), convert to signed number,
4933 then add 2**(N-1). Do the addition using XOR since this
4934 will often generate better code. */
4936 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
4937 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
4938 expand_fix (to
, target
, 0);
4939 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
4941 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
4943 to
, 1, OPTAB_LIB_WIDEN
);
4946 emit_move_insn (to
, target
);
4950 if (mov_optab
->handlers
[(int) GET_MODE (to
)].insn_code
4951 != CODE_FOR_nothing
)
4953 /* Make a place for a REG_NOTE and add it. */
4954 insn
= emit_move_insn (to
, to
);
4955 set_unique_reg_note (insn
,
4957 gen_rtx_fmt_e (UNSIGNED_FIX
,
4965 /* We can't do it with an insn, so use a library call. But first ensure
4966 that the mode of TO is at least as wide as SImode, since those are the
4967 only library calls we know about. */
4969 if (GET_MODE_SIZE (GET_MODE (to
)) < GET_MODE_SIZE (SImode
))
4971 target
= gen_reg_rtx (SImode
);
4973 expand_fix (target
, from
, unsignedp
);
4981 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
4982 libfunc
= tab
->handlers
[GET_MODE (to
)][GET_MODE (from
)].libfunc
;
4983 gcc_assert (libfunc
);
4987 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4988 GET_MODE (to
), 1, from
,
4990 insns
= get_insns ();
4993 emit_libcall_block (insns
, target
, value
,
4994 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
4995 GET_MODE (to
), from
));
5000 if (GET_MODE (to
) == GET_MODE (target
))
5001 emit_move_insn (to
, target
);
5003 convert_move (to
, target
, 0);
5007 /* Generate code to convert FROM to fixed point and store in TO. FROM
5008 must be floating point, TO must be signed. Use the conversion optab
5009 TAB to do the conversion. */
5012 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5014 enum insn_code icode
;
5016 enum machine_mode fmode
, imode
;
5018 /* We first try to find a pair of modes, one real and one integer, at
5019 least as wide as FROM and TO, respectively, in which we can open-code
5020 this conversion. If the integer mode is wider than the mode of TO,
5021 we can do the conversion either signed or unsigned. */
5023 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5024 fmode
= GET_MODE_WIDER_MODE (fmode
))
5025 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5026 imode
= GET_MODE_WIDER_MODE (imode
))
5028 icode
= tab
->handlers
[imode
][fmode
].insn_code
;
5029 if (icode
!= CODE_FOR_nothing
)
5031 if (fmode
!= GET_MODE (from
))
5032 from
= convert_to_mode (fmode
, from
, 0);
5034 if (imode
!= GET_MODE (to
))
5035 target
= gen_reg_rtx (imode
);
5037 emit_unop_insn (icode
, target
, from
, UNKNOWN
);
5039 convert_move (to
, target
, 0);
5047 /* Report whether we have an instruction to perform the operation
5048 specified by CODE on operands of mode MODE. */
5050 have_insn_for (enum rtx_code code
, enum machine_mode mode
)
5052 return (code_to_optab
[(int) code
] != 0
5053 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
5054 != CODE_FOR_nothing
));
5057 /* Create a blank optab. */
5062 optab op
= ggc_alloc (sizeof (struct optab
));
5063 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5065 op
->handlers
[i
].insn_code
= CODE_FOR_nothing
;
5066 op
->handlers
[i
].libfunc
= 0;
5072 static convert_optab
5073 new_convert_optab (void)
5076 convert_optab op
= ggc_alloc (sizeof (struct convert_optab
));
5077 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5078 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
5080 op
->handlers
[i
][j
].insn_code
= CODE_FOR_nothing
;
5081 op
->handlers
[i
][j
].libfunc
= 0;
5086 /* Same, but fill in its code as CODE, and write it into the
5087 code_to_optab table. */
5089 init_optab (enum rtx_code code
)
5091 optab op
= new_optab ();
5093 code_to_optab
[(int) code
] = op
;
5097 /* Same, but fill in its code as CODE, and do _not_ write it into
5098 the code_to_optab table. */
5100 init_optabv (enum rtx_code code
)
5102 optab op
= new_optab ();
5107 /* Conversion optabs never go in the code_to_optab table. */
5108 static inline convert_optab
5109 init_convert_optab (enum rtx_code code
)
5111 convert_optab op
= new_convert_optab ();
5116 /* Initialize the libfunc fields of an entire group of entries in some
5117 optab. Each entry is set equal to a string consisting of a leading
5118 pair of underscores followed by a generic operation name followed by
5119 a mode name (downshifted to lowercase) followed by a single character
5120 representing the number of operands for the given operation (which is
5121 usually one of the characters '2', '3', or '4').
5123 OPTABLE is the table in which libfunc fields are to be initialized.
5124 FIRST_MODE is the first machine mode index in the given optab to
5126 LAST_MODE is the last machine mode index in the given optab to
5128 OPNAME is the generic (string) name of the operation.
5129 SUFFIX is the character which specifies the number of operands for
5130 the given generic operation.
5134 init_libfuncs (optab optable
, int first_mode
, int last_mode
,
5135 const char *opname
, int suffix
)
5138 unsigned opname_len
= strlen (opname
);
5140 for (mode
= first_mode
; (int) mode
<= (int) last_mode
;
5141 mode
= (enum machine_mode
) ((int) mode
+ 1))
5143 const char *mname
= GET_MODE_NAME (mode
);
5144 unsigned mname_len
= strlen (mname
);
5145 char *libfunc_name
= alloca (2 + opname_len
+ mname_len
+ 1 + 1);
5152 for (q
= opname
; *q
; )
5154 for (q
= mname
; *q
; q
++)
5155 *p
++ = TOLOWER (*q
);
5159 optable
->handlers
[(int) mode
].libfunc
5160 = init_one_libfunc (ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5164 /* Initialize the libfunc fields of an entire group of entries in some
5165 optab which correspond to all integer mode operations. The parameters
5166 have the same meaning as similarly named ones for the `init_libfuncs'
5167 routine. (See above). */
5170 init_integral_libfuncs (optab optable
, const char *opname
, int suffix
)
5172 int maxsize
= 2*BITS_PER_WORD
;
5173 if (maxsize
< LONG_LONG_TYPE_SIZE
)
5174 maxsize
= LONG_LONG_TYPE_SIZE
;
5175 init_libfuncs (optable
, word_mode
,
5176 mode_for_size (maxsize
, MODE_INT
, 0),
5180 /* Initialize the libfunc fields of an entire group of entries in some
5181 optab which correspond to all real mode operations. The parameters
5182 have the same meaning as similarly named ones for the `init_libfuncs'
5183 routine. (See above). */
5186 init_floating_libfuncs (optab optable
, const char *opname
, int suffix
)
5188 char *dec_opname
= alloca (sizeof (DECIMAL_PREFIX
) + strlen (opname
));
5190 /* For BID support, change the name to have either a bid_ or dpd_ prefix
5191 depending on the low level floating format used. */
5192 memcpy (dec_opname
, DECIMAL_PREFIX
, sizeof (DECIMAL_PREFIX
) - 1);
5193 strcpy (dec_opname
+ sizeof (DECIMAL_PREFIX
) - 1, opname
);
5195 init_libfuncs (optable
, MIN_MODE_FLOAT
, MAX_MODE_FLOAT
, opname
, suffix
);
5196 init_libfuncs (optable
, MIN_MODE_DECIMAL_FLOAT
, MAX_MODE_DECIMAL_FLOAT
,
5197 dec_opname
, suffix
);
5200 /* Initialize the libfunc fields of an entire group of entries of an
5201 inter-mode-class conversion optab. The string formation rules are
5202 similar to the ones for init_libfuncs, above, but instead of having
5203 a mode name and an operand count these functions have two mode names
5204 and no operand count. */
5206 init_interclass_conv_libfuncs (convert_optab tab
, const char *opname
,
5207 enum mode_class from_class
,
5208 enum mode_class to_class
)
5210 enum machine_mode first_from_mode
= GET_CLASS_NARROWEST_MODE (from_class
);
5211 enum machine_mode first_to_mode
= GET_CLASS_NARROWEST_MODE (to_class
);
5212 size_t opname_len
= strlen (opname
);
5213 size_t max_mname_len
= 0;
5215 enum machine_mode fmode
, tmode
;
5216 const char *fname
, *tname
;
5218 char *libfunc_name
, *suffix
;
5219 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5222 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5223 depends on which underlying decimal floating point format is used. */
5224 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5226 for (fmode
= first_from_mode
;
5228 fmode
= GET_MODE_WIDER_MODE (fmode
))
5229 max_mname_len
= MAX (max_mname_len
, strlen (GET_MODE_NAME (fmode
)));
5231 for (tmode
= first_to_mode
;
5233 tmode
= GET_MODE_WIDER_MODE (tmode
))
5234 max_mname_len
= MAX (max_mname_len
, strlen (GET_MODE_NAME (tmode
)));
5236 nondec_name
= alloca (2 + opname_len
+ 2*max_mname_len
+ 1 + 1);
5237 nondec_name
[0] = '_';
5238 nondec_name
[1] = '_';
5239 memcpy (&nondec_name
[2], opname
, opname_len
);
5240 nondec_suffix
= nondec_name
+ opname_len
+ 2;
5242 dec_name
= alloca (2 + dec_len
+ opname_len
+ 2*max_mname_len
+ 1 + 1);
5245 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5246 memcpy (&dec_name
[2+dec_len
], opname
, opname_len
);
5247 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5249 for (fmode
= first_from_mode
; fmode
!= VOIDmode
;
5250 fmode
= GET_MODE_WIDER_MODE (fmode
))
5251 for (tmode
= first_to_mode
; tmode
!= VOIDmode
;
5252 tmode
= GET_MODE_WIDER_MODE (tmode
))
5254 fname
= GET_MODE_NAME (fmode
);
5255 tname
= GET_MODE_NAME (tmode
);
5257 if (DECIMAL_FLOAT_MODE_P(fmode
) || DECIMAL_FLOAT_MODE_P(tmode
))
5259 libfunc_name
= dec_name
;
5260 suffix
= dec_suffix
;
5264 libfunc_name
= nondec_name
;
5265 suffix
= nondec_suffix
;
5269 for (q
= fname
; *q
; p
++, q
++)
5271 for (q
= tname
; *q
; p
++, q
++)
5276 tab
->handlers
[tmode
][fmode
].libfunc
5277 = init_one_libfunc (ggc_alloc_string (libfunc_name
,
5282 /* Initialize the libfunc fields of an entire group of entries of an
5283 intra-mode-class conversion optab. The string formation rules are
5284 similar to the ones for init_libfunc, above. WIDENING says whether
5285 the optab goes from narrow to wide modes or vice versa. These functions
5286 have two mode names _and_ an operand count. */
5288 init_intraclass_conv_libfuncs (convert_optab tab
, const char *opname
,
5289 enum mode_class
class, bool widening
)
5291 enum machine_mode first_mode
= GET_CLASS_NARROWEST_MODE (class);
5292 size_t opname_len
= strlen (opname
);
5293 size_t max_mname_len
= 0;
5295 enum machine_mode nmode
, wmode
;
5296 const char *nname
, *wname
;
5298 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5299 char *libfunc_name
, *suffix
;
5302 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5303 depends on which underlying decimal floating point format is used. */
5304 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5306 for (nmode
= first_mode
; nmode
!= VOIDmode
;
5307 nmode
= GET_MODE_WIDER_MODE (nmode
))
5308 max_mname_len
= MAX (max_mname_len
, strlen (GET_MODE_NAME (nmode
)));
5310 nondec_name
= alloca (2 + opname_len
+ 2*max_mname_len
+ 1 + 1);
5311 nondec_name
[0] = '_';
5312 nondec_name
[1] = '_';
5313 memcpy (&nondec_name
[2], opname
, opname_len
);
5314 nondec_suffix
= nondec_name
+ opname_len
+ 2;
5316 dec_name
= alloca (2 + dec_len
+ opname_len
+ 2*max_mname_len
+ 1 + 1);
5319 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5320 memcpy (&dec_name
[2 + dec_len
], opname
, opname_len
);
5321 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5323 for (nmode
= first_mode
; nmode
!= VOIDmode
;
5324 nmode
= GET_MODE_WIDER_MODE (nmode
))
5325 for (wmode
= GET_MODE_WIDER_MODE (nmode
); wmode
!= VOIDmode
;
5326 wmode
= GET_MODE_WIDER_MODE (wmode
))
5328 nname
= GET_MODE_NAME (nmode
);
5329 wname
= GET_MODE_NAME (wmode
);
5331 if (DECIMAL_FLOAT_MODE_P(nmode
) || DECIMAL_FLOAT_MODE_P(wmode
))
5333 libfunc_name
= dec_name
;
5334 suffix
= dec_suffix
;
5338 libfunc_name
= nondec_name
;
5339 suffix
= nondec_suffix
;
5343 for (q
= widening
? nname
: wname
; *q
; p
++, q
++)
5345 for (q
= widening
? wname
: nname
; *q
; p
++, q
++)
5351 tab
->handlers
[widening
? wmode
: nmode
]
5352 [widening
? nmode
: wmode
].libfunc
5353 = init_one_libfunc (ggc_alloc_string (libfunc_name
,
5360 init_one_libfunc (const char *name
)
5364 /* Create a FUNCTION_DECL that can be passed to
5365 targetm.encode_section_info. */
5366 /* ??? We don't have any type information except for this is
5367 a function. Pretend this is "int foo()". */
5368 tree decl
= build_decl (FUNCTION_DECL
, get_identifier (name
),
5369 build_function_type (integer_type_node
, NULL_TREE
));
5370 DECL_ARTIFICIAL (decl
) = 1;
5371 DECL_EXTERNAL (decl
) = 1;
5372 TREE_PUBLIC (decl
) = 1;
5374 symbol
= XEXP (DECL_RTL (decl
), 0);
5376 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
5377 are the flags assigned by targetm.encode_section_info. */
5378 SET_SYMBOL_REF_DECL (symbol
, 0);
5383 /* Call this to reset the function entry for one optab (OPTABLE) in mode
5384 MODE to NAME, which should be either 0 or a string constant. */
5386 set_optab_libfunc (optab optable
, enum machine_mode mode
, const char *name
)
5389 optable
->handlers
[mode
].libfunc
= init_one_libfunc (name
);
5391 optable
->handlers
[mode
].libfunc
= 0;
5394 /* Call this to reset the function entry for one conversion optab
5395 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
5396 either 0 or a string constant. */
5398 set_conv_libfunc (convert_optab optable
, enum machine_mode tmode
,
5399 enum machine_mode fmode
, const char *name
)
5402 optable
->handlers
[tmode
][fmode
].libfunc
= init_one_libfunc (name
);
5404 optable
->handlers
[tmode
][fmode
].libfunc
= 0;
5407 /* Call this once to initialize the contents of the optabs
5408 appropriately for the current target machine. */
5414 enum machine_mode int_mode
;
5416 /* Start by initializing all tables to contain CODE_FOR_nothing. */
5418 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5419 setcc_gen_code
[i
] = CODE_FOR_nothing
;
5421 #ifdef HAVE_conditional_move
5422 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5423 movcc_gen_code
[i
] = CODE_FOR_nothing
;
5426 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5428 vcond_gen_code
[i
] = CODE_FOR_nothing
;
5429 vcondu_gen_code
[i
] = CODE_FOR_nothing
;
5432 add_optab
= init_optab (PLUS
);
5433 addv_optab
= init_optabv (PLUS
);
5434 sub_optab
= init_optab (MINUS
);
5435 subv_optab
= init_optabv (MINUS
);
5436 smul_optab
= init_optab (MULT
);
5437 smulv_optab
= init_optabv (MULT
);
5438 smul_highpart_optab
= init_optab (UNKNOWN
);
5439 umul_highpart_optab
= init_optab (UNKNOWN
);
5440 smul_widen_optab
= init_optab (UNKNOWN
);
5441 umul_widen_optab
= init_optab (UNKNOWN
);
5442 usmul_widen_optab
= init_optab (UNKNOWN
);
5443 smadd_widen_optab
= init_optab (UNKNOWN
);
5444 umadd_widen_optab
= init_optab (UNKNOWN
);
5445 sdiv_optab
= init_optab (DIV
);
5446 sdivv_optab
= init_optabv (DIV
);
5447 sdivmod_optab
= init_optab (UNKNOWN
);
5448 udiv_optab
= init_optab (UDIV
);
5449 udivmod_optab
= init_optab (UNKNOWN
);
5450 smod_optab
= init_optab (MOD
);
5451 umod_optab
= init_optab (UMOD
);
5452 fmod_optab
= init_optab (UNKNOWN
);
5453 remainder_optab
= init_optab (UNKNOWN
);
5454 ftrunc_optab
= init_optab (UNKNOWN
);
5455 and_optab
= init_optab (AND
);
5456 ior_optab
= init_optab (IOR
);
5457 xor_optab
= init_optab (XOR
);
5458 ashl_optab
= init_optab (ASHIFT
);
5459 ashr_optab
= init_optab (ASHIFTRT
);
5460 lshr_optab
= init_optab (LSHIFTRT
);
5461 rotl_optab
= init_optab (ROTATE
);
5462 rotr_optab
= init_optab (ROTATERT
);
5463 smin_optab
= init_optab (SMIN
);
5464 smax_optab
= init_optab (SMAX
);
5465 umin_optab
= init_optab (UMIN
);
5466 umax_optab
= init_optab (UMAX
);
5467 pow_optab
= init_optab (UNKNOWN
);
5468 atan2_optab
= init_optab (UNKNOWN
);
5470 /* These three have codes assigned exclusively for the sake of
5472 mov_optab
= init_optab (SET
);
5473 movstrict_optab
= init_optab (STRICT_LOW_PART
);
5474 cmp_optab
= init_optab (COMPARE
);
5476 ucmp_optab
= init_optab (UNKNOWN
);
5477 tst_optab
= init_optab (UNKNOWN
);
5479 eq_optab
= init_optab (EQ
);
5480 ne_optab
= init_optab (NE
);
5481 gt_optab
= init_optab (GT
);
5482 ge_optab
= init_optab (GE
);
5483 lt_optab
= init_optab (LT
);
5484 le_optab
= init_optab (LE
);
5485 unord_optab
= init_optab (UNORDERED
);
5487 neg_optab
= init_optab (NEG
);
5488 negv_optab
= init_optabv (NEG
);
5489 abs_optab
= init_optab (ABS
);
5490 absv_optab
= init_optabv (ABS
);
5491 addcc_optab
= init_optab (UNKNOWN
);
5492 one_cmpl_optab
= init_optab (NOT
);
5493 bswap_optab
= init_optab (BSWAP
);
5494 ffs_optab
= init_optab (FFS
);
5495 clz_optab
= init_optab (CLZ
);
5496 ctz_optab
= init_optab (CTZ
);
5497 popcount_optab
= init_optab (POPCOUNT
);
5498 parity_optab
= init_optab (PARITY
);
5499 sqrt_optab
= init_optab (SQRT
);
5500 floor_optab
= init_optab (UNKNOWN
);
5501 ceil_optab
= init_optab (UNKNOWN
);
5502 round_optab
= init_optab (UNKNOWN
);
5503 btrunc_optab
= init_optab (UNKNOWN
);
5504 nearbyint_optab
= init_optab (UNKNOWN
);
5505 rint_optab
= init_optab (UNKNOWN
);
5506 sincos_optab
= init_optab (UNKNOWN
);
5507 sin_optab
= init_optab (UNKNOWN
);
5508 asin_optab
= init_optab (UNKNOWN
);
5509 cos_optab
= init_optab (UNKNOWN
);
5510 acos_optab
= init_optab (UNKNOWN
);
5511 exp_optab
= init_optab (UNKNOWN
);
5512 exp10_optab
= init_optab (UNKNOWN
);
5513 exp2_optab
= init_optab (UNKNOWN
);
5514 expm1_optab
= init_optab (UNKNOWN
);
5515 ldexp_optab
= init_optab (UNKNOWN
);
5516 scalb_optab
= init_optab (UNKNOWN
);
5517 logb_optab
= init_optab (UNKNOWN
);
5518 ilogb_optab
= init_optab (UNKNOWN
);
5519 log_optab
= init_optab (UNKNOWN
);
5520 log10_optab
= init_optab (UNKNOWN
);
5521 log2_optab
= init_optab (UNKNOWN
);
5522 log1p_optab
= init_optab (UNKNOWN
);
5523 tan_optab
= init_optab (UNKNOWN
);
5524 atan_optab
= init_optab (UNKNOWN
);
5525 copysign_optab
= init_optab (UNKNOWN
);
5527 isinf_optab
= init_optab (UNKNOWN
);
5529 strlen_optab
= init_optab (UNKNOWN
);
5530 cbranch_optab
= init_optab (UNKNOWN
);
5531 cmov_optab
= init_optab (UNKNOWN
);
5532 cstore_optab
= init_optab (UNKNOWN
);
5533 push_optab
= init_optab (UNKNOWN
);
5535 reduc_smax_optab
= init_optab (UNKNOWN
);
5536 reduc_umax_optab
= init_optab (UNKNOWN
);
5537 reduc_smin_optab
= init_optab (UNKNOWN
);
5538 reduc_umin_optab
= init_optab (UNKNOWN
);
5539 reduc_splus_optab
= init_optab (UNKNOWN
);
5540 reduc_uplus_optab
= init_optab (UNKNOWN
);
5542 ssum_widen_optab
= init_optab (UNKNOWN
);
5543 usum_widen_optab
= init_optab (UNKNOWN
);
5544 sdot_prod_optab
= init_optab (UNKNOWN
);
5545 udot_prod_optab
= init_optab (UNKNOWN
);
5547 vec_extract_optab
= init_optab (UNKNOWN
);
5548 vec_extract_even_optab
= init_optab (UNKNOWN
);
5549 vec_extract_odd_optab
= init_optab (UNKNOWN
);
5550 vec_interleave_high_optab
= init_optab (UNKNOWN
);
5551 vec_interleave_low_optab
= init_optab (UNKNOWN
);
5552 vec_set_optab
= init_optab (UNKNOWN
);
5553 vec_init_optab
= init_optab (UNKNOWN
);
5554 vec_shl_optab
= init_optab (UNKNOWN
);
5555 vec_shr_optab
= init_optab (UNKNOWN
);
5556 vec_realign_load_optab
= init_optab (UNKNOWN
);
5557 movmisalign_optab
= init_optab (UNKNOWN
);
5558 vec_widen_umult_hi_optab
= init_optab (UNKNOWN
);
5559 vec_widen_umult_lo_optab
= init_optab (UNKNOWN
);
5560 vec_widen_smult_hi_optab
= init_optab (UNKNOWN
);
5561 vec_widen_smult_lo_optab
= init_optab (UNKNOWN
);
5562 vec_unpacks_hi_optab
= init_optab (UNKNOWN
);
5563 vec_unpacks_lo_optab
= init_optab (UNKNOWN
);
5564 vec_unpacku_hi_optab
= init_optab (UNKNOWN
);
5565 vec_unpacku_lo_optab
= init_optab (UNKNOWN
);
5566 vec_pack_trunc_optab
= init_optab (UNKNOWN
);
5567 vec_pack_usat_optab
= init_optab (UNKNOWN
);
5568 vec_pack_ssat_optab
= init_optab (UNKNOWN
);
5570 powi_optab
= init_optab (UNKNOWN
);
5573 sext_optab
= init_convert_optab (SIGN_EXTEND
);
5574 zext_optab
= init_convert_optab (ZERO_EXTEND
);
5575 trunc_optab
= init_convert_optab (TRUNCATE
);
5576 sfix_optab
= init_convert_optab (FIX
);
5577 ufix_optab
= init_convert_optab (UNSIGNED_FIX
);
5578 sfixtrunc_optab
= init_convert_optab (UNKNOWN
);
5579 ufixtrunc_optab
= init_convert_optab (UNKNOWN
);
5580 sfloat_optab
= init_convert_optab (FLOAT
);
5581 ufloat_optab
= init_convert_optab (UNSIGNED_FLOAT
);
5582 lrint_optab
= init_convert_optab (UNKNOWN
);
5583 lround_optab
= init_convert_optab (UNKNOWN
);
5584 lfloor_optab
= init_convert_optab (UNKNOWN
);
5585 lceil_optab
= init_convert_optab (UNKNOWN
);
5587 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5589 movmem_optab
[i
] = CODE_FOR_nothing
;
5590 cmpstr_optab
[i
] = CODE_FOR_nothing
;
5591 cmpstrn_optab
[i
] = CODE_FOR_nothing
;
5592 cmpmem_optab
[i
] = CODE_FOR_nothing
;
5593 setmem_optab
[i
] = CODE_FOR_nothing
;
5595 sync_add_optab
[i
] = CODE_FOR_nothing
;
5596 sync_sub_optab
[i
] = CODE_FOR_nothing
;
5597 sync_ior_optab
[i
] = CODE_FOR_nothing
;
5598 sync_and_optab
[i
] = CODE_FOR_nothing
;
5599 sync_xor_optab
[i
] = CODE_FOR_nothing
;
5600 sync_nand_optab
[i
] = CODE_FOR_nothing
;
5601 sync_old_add_optab
[i
] = CODE_FOR_nothing
;
5602 sync_old_sub_optab
[i
] = CODE_FOR_nothing
;
5603 sync_old_ior_optab
[i
] = CODE_FOR_nothing
;
5604 sync_old_and_optab
[i
] = CODE_FOR_nothing
;
5605 sync_old_xor_optab
[i
] = CODE_FOR_nothing
;
5606 sync_old_nand_optab
[i
] = CODE_FOR_nothing
;
5607 sync_new_add_optab
[i
] = CODE_FOR_nothing
;
5608 sync_new_sub_optab
[i
] = CODE_FOR_nothing
;
5609 sync_new_ior_optab
[i
] = CODE_FOR_nothing
;
5610 sync_new_and_optab
[i
] = CODE_FOR_nothing
;
5611 sync_new_xor_optab
[i
] = CODE_FOR_nothing
;
5612 sync_new_nand_optab
[i
] = CODE_FOR_nothing
;
5613 sync_compare_and_swap
[i
] = CODE_FOR_nothing
;
5614 sync_compare_and_swap_cc
[i
] = CODE_FOR_nothing
;
5615 sync_lock_test_and_set
[i
] = CODE_FOR_nothing
;
5616 sync_lock_release
[i
] = CODE_FOR_nothing
;
5618 reload_in_optab
[i
] = reload_out_optab
[i
] = CODE_FOR_nothing
;
5621 /* Fill in the optabs with the insns we support. */
5624 /* The ffs function operates on `int'. Fall back on it if we do not
5625 have a libgcc2 function for that width. */
5626 int_mode
= mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0);
5627 ffs_optab
->handlers
[(int) int_mode
].libfunc
= init_one_libfunc ("ffs");
5629 /* Initialize the optabs with the names of the library functions. */
5630 init_integral_libfuncs (add_optab
, "add", '3');
5631 init_floating_libfuncs (add_optab
, "add", '3');
5632 init_integral_libfuncs (addv_optab
, "addv", '3');
5633 init_floating_libfuncs (addv_optab
, "add", '3');
5634 init_integral_libfuncs (sub_optab
, "sub", '3');
5635 init_floating_libfuncs (sub_optab
, "sub", '3');
5636 init_integral_libfuncs (subv_optab
, "subv", '3');
5637 init_floating_libfuncs (subv_optab
, "sub", '3');
5638 init_integral_libfuncs (smul_optab
, "mul", '3');
5639 init_floating_libfuncs (smul_optab
, "mul", '3');
5640 init_integral_libfuncs (smulv_optab
, "mulv", '3');
5641 init_floating_libfuncs (smulv_optab
, "mul", '3');
5642 init_integral_libfuncs (sdiv_optab
, "div", '3');
5643 init_floating_libfuncs (sdiv_optab
, "div", '3');
5644 init_integral_libfuncs (sdivv_optab
, "divv", '3');
5645 init_integral_libfuncs (udiv_optab
, "udiv", '3');
5646 init_integral_libfuncs (sdivmod_optab
, "divmod", '4');
5647 init_integral_libfuncs (udivmod_optab
, "udivmod", '4');
5648 init_integral_libfuncs (smod_optab
, "mod", '3');
5649 init_integral_libfuncs (umod_optab
, "umod", '3');
5650 init_floating_libfuncs (ftrunc_optab
, "ftrunc", '2');
5651 init_integral_libfuncs (and_optab
, "and", '3');
5652 init_integral_libfuncs (ior_optab
, "ior", '3');
5653 init_integral_libfuncs (xor_optab
, "xor", '3');
5654 init_integral_libfuncs (ashl_optab
, "ashl", '3');
5655 init_integral_libfuncs (ashr_optab
, "ashr", '3');
5656 init_integral_libfuncs (lshr_optab
, "lshr", '3');
5657 init_integral_libfuncs (smin_optab
, "min", '3');
5658 init_floating_libfuncs (smin_optab
, "min", '3');
5659 init_integral_libfuncs (smax_optab
, "max", '3');
5660 init_floating_libfuncs (smax_optab
, "max", '3');
5661 init_integral_libfuncs (umin_optab
, "umin", '3');
5662 init_integral_libfuncs (umax_optab
, "umax", '3');
5663 init_integral_libfuncs (neg_optab
, "neg", '2');
5664 init_floating_libfuncs (neg_optab
, "neg", '2');
5665 init_integral_libfuncs (negv_optab
, "negv", '2');
5666 init_floating_libfuncs (negv_optab
, "neg", '2');
5667 init_integral_libfuncs (one_cmpl_optab
, "one_cmpl", '2');
5668 init_integral_libfuncs (ffs_optab
, "ffs", '2');
5669 init_integral_libfuncs (clz_optab
, "clz", '2');
5670 init_integral_libfuncs (ctz_optab
, "ctz", '2');
5671 init_integral_libfuncs (popcount_optab
, "popcount", '2');
5672 init_integral_libfuncs (parity_optab
, "parity", '2');
5674 /* Comparison libcalls for integers MUST come in pairs,
5676 init_integral_libfuncs (cmp_optab
, "cmp", '2');
5677 init_integral_libfuncs (ucmp_optab
, "ucmp", '2');
5678 init_floating_libfuncs (cmp_optab
, "cmp", '2');
5680 /* EQ etc are floating point only. */
5681 init_floating_libfuncs (eq_optab
, "eq", '2');
5682 init_floating_libfuncs (ne_optab
, "ne", '2');
5683 init_floating_libfuncs (gt_optab
, "gt", '2');
5684 init_floating_libfuncs (ge_optab
, "ge", '2');
5685 init_floating_libfuncs (lt_optab
, "lt", '2');
5686 init_floating_libfuncs (le_optab
, "le", '2');
5687 init_floating_libfuncs (unord_optab
, "unord", '2');
5689 init_floating_libfuncs (powi_optab
, "powi", '2');
5692 init_interclass_conv_libfuncs (sfloat_optab
, "float",
5693 MODE_INT
, MODE_FLOAT
);
5694 init_interclass_conv_libfuncs (sfloat_optab
, "float",
5695 MODE_INT
, MODE_DECIMAL_FLOAT
);
5696 init_interclass_conv_libfuncs (ufloat_optab
, "floatun",
5697 MODE_INT
, MODE_FLOAT
);
5698 init_interclass_conv_libfuncs (ufloat_optab
, "floatun",
5699 MODE_INT
, MODE_DECIMAL_FLOAT
);
5700 init_interclass_conv_libfuncs (sfix_optab
, "fix",
5701 MODE_FLOAT
, MODE_INT
);
5702 init_interclass_conv_libfuncs (sfix_optab
, "fix",
5703 MODE_DECIMAL_FLOAT
, MODE_INT
);
5704 init_interclass_conv_libfuncs (ufix_optab
, "fixuns",
5705 MODE_FLOAT
, MODE_INT
);
5706 init_interclass_conv_libfuncs (ufix_optab
, "fixuns",
5707 MODE_DECIMAL_FLOAT
, MODE_INT
);
5708 init_interclass_conv_libfuncs (ufloat_optab
, "floatuns",
5709 MODE_INT
, MODE_DECIMAL_FLOAT
);
5710 init_interclass_conv_libfuncs (lrint_optab
, "lrint",
5711 MODE_INT
, MODE_FLOAT
);
5712 init_interclass_conv_libfuncs (lround_optab
, "lround",
5713 MODE_INT
, MODE_FLOAT
);
5714 init_interclass_conv_libfuncs (lfloor_optab
, "lfloor",
5715 MODE_INT
, MODE_FLOAT
);
5716 init_interclass_conv_libfuncs (lceil_optab
, "lceil",
5717 MODE_INT
, MODE_FLOAT
);
5719 /* sext_optab is also used for FLOAT_EXTEND. */
5720 init_intraclass_conv_libfuncs (sext_optab
, "extend", MODE_FLOAT
, true);
5721 init_intraclass_conv_libfuncs (sext_optab
, "extend", MODE_DECIMAL_FLOAT
, true);
5722 init_interclass_conv_libfuncs (sext_optab
, "extend", MODE_FLOAT
, MODE_DECIMAL_FLOAT
);
5723 init_interclass_conv_libfuncs (sext_optab
, "extend", MODE_DECIMAL_FLOAT
, MODE_FLOAT
);
5724 init_intraclass_conv_libfuncs (trunc_optab
, "trunc", MODE_FLOAT
, false);
5725 init_intraclass_conv_libfuncs (trunc_optab
, "trunc", MODE_DECIMAL_FLOAT
, false);
5726 init_interclass_conv_libfuncs (trunc_optab
, "trunc", MODE_FLOAT
, MODE_DECIMAL_FLOAT
);
5727 init_interclass_conv_libfuncs (trunc_optab
, "trunc", MODE_DECIMAL_FLOAT
, MODE_FLOAT
);
5729 /* Explicitly initialize the bswap libfuncs since we need them to be
5730 valid for things other than word_mode. */
5731 set_optab_libfunc (bswap_optab
, SImode
, "__bswapsi2");
5732 set_optab_libfunc (bswap_optab
, DImode
, "__bswapdi2");
5734 /* Use cabs for double complex abs, since systems generally have cabs.
5735 Don't define any libcall for float complex, so that cabs will be used. */
5736 if (complex_double_type_node
)
5737 abs_optab
->handlers
[TYPE_MODE (complex_double_type_node
)].libfunc
5738 = init_one_libfunc ("cabs");
5740 abort_libfunc
= init_one_libfunc ("abort");
5741 memcpy_libfunc
= init_one_libfunc ("memcpy");
5742 memmove_libfunc
= init_one_libfunc ("memmove");
5743 memcmp_libfunc
= init_one_libfunc ("memcmp");
5744 memset_libfunc
= init_one_libfunc ("memset");
5745 setbits_libfunc
= init_one_libfunc ("__setbits");
5747 #ifndef DONT_USE_BUILTIN_SETJMP
5748 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
5749 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
5751 setjmp_libfunc
= init_one_libfunc ("setjmp");
5752 longjmp_libfunc
= init_one_libfunc ("longjmp");
5754 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
5755 unwind_sjlj_unregister_libfunc
5756 = init_one_libfunc ("_Unwind_SjLj_Unregister");
5758 /* For function entry/exit instrumentation. */
5759 profile_function_entry_libfunc
5760 = init_one_libfunc ("__cyg_profile_func_enter");
5761 profile_function_exit_libfunc
5762 = init_one_libfunc ("__cyg_profile_func_exit");
5764 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
5766 if (HAVE_conditional_trap
)
5767 trap_rtx
= gen_rtx_fmt_ee (EQ
, VOIDmode
, NULL_RTX
, NULL_RTX
);
5769 /* Allow the target to add more libcalls or rename some, etc. */
5770 targetm
.init_libfuncs ();
5775 /* Print information about the current contents of the optabs on
5779 debug_optab_libfuncs (void)
5785 /* Dump the arithmetic optabs. */
5786 for (i
= 0; i
!= (int) OTI_MAX
; i
++)
5787 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
5790 struct optab_handlers
*h
;
5793 h
= &o
->handlers
[j
];
5796 gcc_assert (GET_CODE (h
->libfunc
) = SYMBOL_REF
);
5797 fprintf (stderr
, "%s\t%s:\t%s\n",
5798 GET_RTX_NAME (o
->code
),
5800 XSTR (h
->libfunc
, 0));
5804 /* Dump the conversion optabs. */
5805 for (i
= 0; i
< (int) COI_MAX
; ++i
)
5806 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
5807 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
5810 struct optab_handlers
*h
;
5812 o
= &convert_optab_table
[i
];
5813 h
= &o
->handlers
[j
][k
];
5816 gcc_assert (GET_CODE (h
->libfunc
) = SYMBOL_REF
);
5817 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
5818 GET_RTX_NAME (o
->code
),
5821 XSTR (h
->libfunc
, 0));
5829 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
5830 CODE. Return 0 on failure. */
5833 gen_cond_trap (enum rtx_code code ATTRIBUTE_UNUSED
, rtx op1
,
5834 rtx op2 ATTRIBUTE_UNUSED
, rtx tcode ATTRIBUTE_UNUSED
)
5836 enum machine_mode mode
= GET_MODE (op1
);
5837 enum insn_code icode
;
5840 if (!HAVE_conditional_trap
)
5843 if (mode
== VOIDmode
)
5846 icode
= cmp_optab
->handlers
[(int) mode
].insn_code
;
5847 if (icode
== CODE_FOR_nothing
)
5851 op1
= prepare_operand (icode
, op1
, 0, mode
, mode
, 0);
5852 op2
= prepare_operand (icode
, op2
, 1, mode
, mode
, 0);
5858 emit_insn (GEN_FCN (icode
) (op1
, op2
));
5860 PUT_CODE (trap_rtx
, code
);
5861 gcc_assert (HAVE_conditional_trap
);
5862 insn
= gen_conditional_trap (trap_rtx
, tcode
);
5866 insn
= get_insns ();
5873 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
5874 or unsigned operation code. */
5876 static enum rtx_code
5877 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
5889 code
= unsignedp
? LTU
: LT
;
5892 code
= unsignedp
? LEU
: LE
;
5895 code
= unsignedp
? GTU
: GT
;
5898 code
= unsignedp
? GEU
: GE
;
5901 case UNORDERED_EXPR
:
5932 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
5933 unsigned operators. Do not generate compare instruction. */
5936 vector_compare_rtx (tree cond
, bool unsignedp
, enum insn_code icode
)
5938 enum rtx_code rcode
;
5940 rtx rtx_op0
, rtx_op1
;
5942 /* This is unlikely. While generating VEC_COND_EXPR, auto vectorizer
5943 ensures that condition is a relational operation. */
5944 gcc_assert (COMPARISON_CLASS_P (cond
));
5946 rcode
= get_rtx_code (TREE_CODE (cond
), unsignedp
);
5947 t_op0
= TREE_OPERAND (cond
, 0);
5948 t_op1
= TREE_OPERAND (cond
, 1);
5950 /* Expand operands. */
5951 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)), 1);
5952 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)), 1);
5954 if (!insn_data
[icode
].operand
[4].predicate (rtx_op0
, GET_MODE (rtx_op0
))
5955 && GET_MODE (rtx_op0
) != VOIDmode
)
5956 rtx_op0
= force_reg (GET_MODE (rtx_op0
), rtx_op0
);
5958 if (!insn_data
[icode
].operand
[5].predicate (rtx_op1
, GET_MODE (rtx_op1
))
5959 && GET_MODE (rtx_op1
) != VOIDmode
)
5960 rtx_op1
= force_reg (GET_MODE (rtx_op1
), rtx_op1
);
5962 return gen_rtx_fmt_ee (rcode
, VOIDmode
, rtx_op0
, rtx_op1
);
5965 /* Return insn code for VEC_COND_EXPR EXPR. */
5967 static inline enum insn_code
5968 get_vcond_icode (tree expr
, enum machine_mode mode
)
5970 enum insn_code icode
= CODE_FOR_nothing
;
5972 if (TYPE_UNSIGNED (TREE_TYPE (expr
)))
5973 icode
= vcondu_gen_code
[mode
];
5975 icode
= vcond_gen_code
[mode
];
5979 /* Return TRUE iff, appropriate vector insns are available
5980 for vector cond expr expr in VMODE mode. */
5983 expand_vec_cond_expr_p (tree expr
, enum machine_mode vmode
)
5985 if (get_vcond_icode (expr
, vmode
) == CODE_FOR_nothing
)
5990 /* Generate insns for VEC_COND_EXPR. */
5993 expand_vec_cond_expr (tree vec_cond_expr
, rtx target
)
5995 enum insn_code icode
;
5996 rtx comparison
, rtx_op1
, rtx_op2
, cc_op0
, cc_op1
;
5997 enum machine_mode mode
= TYPE_MODE (TREE_TYPE (vec_cond_expr
));
5998 bool unsignedp
= TYPE_UNSIGNED (TREE_TYPE (vec_cond_expr
));
6000 icode
= get_vcond_icode (vec_cond_expr
, mode
);
6001 if (icode
== CODE_FOR_nothing
)
6004 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
6005 target
= gen_reg_rtx (mode
);
6007 /* Get comparison rtx. First expand both cond expr operands. */
6008 comparison
= vector_compare_rtx (TREE_OPERAND (vec_cond_expr
, 0),
6010 cc_op0
= XEXP (comparison
, 0);
6011 cc_op1
= XEXP (comparison
, 1);
6012 /* Expand both operands and force them in reg, if required. */
6013 rtx_op1
= expand_expr (TREE_OPERAND (vec_cond_expr
, 1),
6014 NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6015 if (!insn_data
[icode
].operand
[1].predicate (rtx_op1
, mode
)
6016 && mode
!= VOIDmode
)
6017 rtx_op1
= force_reg (mode
, rtx_op1
);
6019 rtx_op2
= expand_expr (TREE_OPERAND (vec_cond_expr
, 2),
6020 NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6021 if (!insn_data
[icode
].operand
[2].predicate (rtx_op2
, mode
)
6022 && mode
!= VOIDmode
)
6023 rtx_op2
= force_reg (mode
, rtx_op2
);
6025 /* Emit instruction! */
6026 emit_insn (GEN_FCN (icode
) (target
, rtx_op1
, rtx_op2
,
6027 comparison
, cc_op0
, cc_op1
));
6033 /* This is an internal subroutine of the other compare_and_swap expanders.
6034 MEM, OLD_VAL and NEW_VAL are as you'd expect for a compare-and-swap
6035 operation. TARGET is an optional place to store the value result of
6036 the operation. ICODE is the particular instruction to expand. Return
6037 the result of the operation. */
6040 expand_val_compare_and_swap_1 (rtx mem
, rtx old_val
, rtx new_val
,
6041 rtx target
, enum insn_code icode
)
6043 enum machine_mode mode
= GET_MODE (mem
);
6046 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
6047 target
= gen_reg_rtx (mode
);
6049 if (GET_MODE (old_val
) != VOIDmode
&& GET_MODE (old_val
) != mode
)
6050 old_val
= convert_modes (mode
, GET_MODE (old_val
), old_val
, 1);
6051 if (!insn_data
[icode
].operand
[2].predicate (old_val
, mode
))
6052 old_val
= force_reg (mode
, old_val
);
6054 if (GET_MODE (new_val
) != VOIDmode
&& GET_MODE (new_val
) != mode
)
6055 new_val
= convert_modes (mode
, GET_MODE (new_val
), new_val
, 1);
6056 if (!insn_data
[icode
].operand
[3].predicate (new_val
, mode
))
6057 new_val
= force_reg (mode
, new_val
);
6059 insn
= GEN_FCN (icode
) (target
, mem
, old_val
, new_val
);
6060 if (insn
== NULL_RTX
)
6067 /* Expand a compare-and-swap operation and return its value. */
6070 expand_val_compare_and_swap (rtx mem
, rtx old_val
, rtx new_val
, rtx target
)
6072 enum machine_mode mode
= GET_MODE (mem
);
6073 enum insn_code icode
= sync_compare_and_swap
[mode
];
6075 if (icode
== CODE_FOR_nothing
)
6078 return expand_val_compare_and_swap_1 (mem
, old_val
, new_val
, target
, icode
);
6081 /* Expand a compare-and-swap operation and store true into the result if
6082 the operation was successful and false otherwise. Return the result.
6083 Unlike other routines, TARGET is not optional. */
6086 expand_bool_compare_and_swap (rtx mem
, rtx old_val
, rtx new_val
, rtx target
)
6088 enum machine_mode mode
= GET_MODE (mem
);
6089 enum insn_code icode
;
6090 rtx subtarget
, label0
, label1
;
6092 /* If the target supports a compare-and-swap pattern that simultaneously
6093 sets some flag for success, then use it. Otherwise use the regular
6094 compare-and-swap and follow that immediately with a compare insn. */
6095 icode
= sync_compare_and_swap_cc
[mode
];
6099 subtarget
= expand_val_compare_and_swap_1 (mem
, old_val
, new_val
,
6101 if (subtarget
!= NULL_RTX
)
6105 case CODE_FOR_nothing
:
6106 icode
= sync_compare_and_swap
[mode
];
6107 if (icode
== CODE_FOR_nothing
)
6110 /* Ensure that if old_val == mem, that we're not comparing
6111 against an old value. */
6112 if (MEM_P (old_val
))
6113 old_val
= force_reg (mode
, old_val
);
6115 subtarget
= expand_val_compare_and_swap_1 (mem
, old_val
, new_val
,
6117 if (subtarget
== NULL_RTX
)
6120 emit_cmp_insn (subtarget
, old_val
, EQ
, const0_rtx
, mode
, true);
6123 /* If the target has a sane STORE_FLAG_VALUE, then go ahead and use a
6124 setcc instruction from the beginning. We don't work too hard here,
6125 but it's nice to not be stupid about initial code gen either. */
6126 if (STORE_FLAG_VALUE
== 1)
6128 icode
= setcc_gen_code
[EQ
];
6129 if (icode
!= CODE_FOR_nothing
)
6131 enum machine_mode cmode
= insn_data
[icode
].operand
[0].mode
;
6135 if (!insn_data
[icode
].operand
[0].predicate (target
, cmode
))
6136 subtarget
= gen_reg_rtx (cmode
);
6138 insn
= GEN_FCN (icode
) (subtarget
);
6142 if (GET_MODE (target
) != GET_MODE (subtarget
))
6144 convert_move (target
, subtarget
, 1);
6152 /* Without an appropriate setcc instruction, use a set of branches to
6153 get 1 and 0 stored into target. Presumably if the target has a
6154 STORE_FLAG_VALUE that isn't 1, then this will get cleaned up by ifcvt. */
6156 label0
= gen_label_rtx ();
6157 label1
= gen_label_rtx ();
6159 emit_jump_insn (bcc_gen_fctn
[EQ
] (label0
));
6160 emit_move_insn (target
, const0_rtx
);
6161 emit_jump_insn (gen_jump (label1
));
6163 emit_label (label0
);
6164 emit_move_insn (target
, const1_rtx
);
6165 emit_label (label1
);
6170 /* This is a helper function for the other atomic operations. This function
6171 emits a loop that contains SEQ that iterates until a compare-and-swap
6172 operation at the end succeeds. MEM is the memory to be modified. SEQ is
6173 a set of instructions that takes a value from OLD_REG as an input and
6174 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
6175 set to the current contents of MEM. After SEQ, a compare-and-swap will
6176 attempt to update MEM with NEW_REG. The function returns true when the
6177 loop was generated successfully. */
6180 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
6182 enum machine_mode mode
= GET_MODE (mem
);
6183 enum insn_code icode
;
6184 rtx label
, cmp_reg
, subtarget
;
6186 /* The loop we want to generate looks like
6192 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
6193 if (cmp_reg != old_reg)
6196 Note that we only do the plain load from memory once. Subsequent
6197 iterations use the value loaded by the compare-and-swap pattern. */
6199 label
= gen_label_rtx ();
6200 cmp_reg
= gen_reg_rtx (mode
);
6202 emit_move_insn (cmp_reg
, mem
);
6204 emit_move_insn (old_reg
, cmp_reg
);
6208 /* If the target supports a compare-and-swap pattern that simultaneously
6209 sets some flag for success, then use it. Otherwise use the regular
6210 compare-and-swap and follow that immediately with a compare insn. */
6211 icode
= sync_compare_and_swap_cc
[mode
];
6215 subtarget
= expand_val_compare_and_swap_1 (mem
, old_reg
, new_reg
,
6217 if (subtarget
!= NULL_RTX
)
6219 gcc_assert (subtarget
== cmp_reg
);
6224 case CODE_FOR_nothing
:
6225 icode
= sync_compare_and_swap
[mode
];
6226 if (icode
== CODE_FOR_nothing
)
6229 subtarget
= expand_val_compare_and_swap_1 (mem
, old_reg
, new_reg
,
6231 if (subtarget
== NULL_RTX
)
6233 if (subtarget
!= cmp_reg
)
6234 emit_move_insn (cmp_reg
, subtarget
);
6236 emit_cmp_insn (cmp_reg
, old_reg
, EQ
, const0_rtx
, mode
, true);
6239 /* ??? Mark this jump predicted not taken? */
6240 emit_jump_insn (bcc_gen_fctn
[NE
] (label
));
6245 /* This function generates the atomic operation MEM CODE= VAL. In this
6246 case, we do not care about any resulting value. Returns NULL if we
6247 cannot generate the operation. */
6250 expand_sync_operation (rtx mem
, rtx val
, enum rtx_code code
)
6252 enum machine_mode mode
= GET_MODE (mem
);
6253 enum insn_code icode
;
6256 /* Look to see if the target supports the operation directly. */
6260 icode
= sync_add_optab
[mode
];
6263 icode
= sync_ior_optab
[mode
];
6266 icode
= sync_xor_optab
[mode
];
6269 icode
= sync_and_optab
[mode
];
6272 icode
= sync_nand_optab
[mode
];
6276 icode
= sync_sub_optab
[mode
];
6277 if (icode
== CODE_FOR_nothing
)
6279 icode
= sync_add_optab
[mode
];
6280 if (icode
!= CODE_FOR_nothing
)
6282 val
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, 1);
6292 /* Generate the direct operation, if present. */
6293 if (icode
!= CODE_FOR_nothing
)
6295 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
6296 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
6297 if (!insn_data
[icode
].operand
[1].predicate (val
, mode
))
6298 val
= force_reg (mode
, val
);
6300 insn
= GEN_FCN (icode
) (mem
, val
);
6308 /* Failing that, generate a compare-and-swap loop in which we perform the
6309 operation with normal arithmetic instructions. */
6310 if (sync_compare_and_swap
[mode
] != CODE_FOR_nothing
)
6312 rtx t0
= gen_reg_rtx (mode
), t1
;
6319 t1
= expand_simple_unop (mode
, NOT
, t1
, NULL_RTX
, true);
6322 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
,
6323 true, OPTAB_LIB_WIDEN
);
6325 insn
= get_insns ();
6328 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
6335 /* This function generates the atomic operation MEM CODE= VAL. In this
6336 case, we do care about the resulting value: if AFTER is true then
6337 return the value MEM holds after the operation, if AFTER is false
6338 then return the value MEM holds before the operation. TARGET is an
6339 optional place for the result value to be stored. */
6342 expand_sync_fetch_operation (rtx mem
, rtx val
, enum rtx_code code
,
6343 bool after
, rtx target
)
6345 enum machine_mode mode
= GET_MODE (mem
);
6346 enum insn_code old_code
, new_code
, icode
;
6350 /* Look to see if the target supports the operation directly. */
6354 old_code
= sync_old_add_optab
[mode
];
6355 new_code
= sync_new_add_optab
[mode
];
6358 old_code
= sync_old_ior_optab
[mode
];
6359 new_code
= sync_new_ior_optab
[mode
];
6362 old_code
= sync_old_xor_optab
[mode
];
6363 new_code
= sync_new_xor_optab
[mode
];
6366 old_code
= sync_old_and_optab
[mode
];
6367 new_code
= sync_new_and_optab
[mode
];
6370 old_code
= sync_old_nand_optab
[mode
];
6371 new_code
= sync_new_nand_optab
[mode
];
6375 old_code
= sync_old_sub_optab
[mode
];
6376 new_code
= sync_new_sub_optab
[mode
];
6377 if (old_code
== CODE_FOR_nothing
&& new_code
== CODE_FOR_nothing
)
6379 old_code
= sync_old_add_optab
[mode
];
6380 new_code
= sync_new_add_optab
[mode
];
6381 if (old_code
!= CODE_FOR_nothing
|| new_code
!= CODE_FOR_nothing
)
6383 val
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, 1);
6393 /* If the target does supports the proper new/old operation, great. But
6394 if we only support the opposite old/new operation, check to see if we
6395 can compensate. In the case in which the old value is supported, then
6396 we can always perform the operation again with normal arithmetic. In
6397 the case in which the new value is supported, then we can only handle
6398 this in the case the operation is reversible. */
6403 if (icode
== CODE_FOR_nothing
)
6406 if (icode
!= CODE_FOR_nothing
)
6413 if (icode
== CODE_FOR_nothing
6414 && (code
== PLUS
|| code
== MINUS
|| code
== XOR
))
6417 if (icode
!= CODE_FOR_nothing
)
6422 /* If we found something supported, great. */
6423 if (icode
!= CODE_FOR_nothing
)
6425 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
6426 target
= gen_reg_rtx (mode
);
6428 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
6429 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
6430 if (!insn_data
[icode
].operand
[2].predicate (val
, mode
))
6431 val
= force_reg (mode
, val
);
6433 insn
= GEN_FCN (icode
) (target
, mem
, val
);
6438 /* If we need to compensate for using an operation with the
6439 wrong return value, do so now. */
6446 else if (code
== MINUS
)
6451 target
= expand_simple_unop (mode
, NOT
, target
, NULL_RTX
, true);
6452 target
= expand_simple_binop (mode
, code
, target
, val
, NULL_RTX
,
6453 true, OPTAB_LIB_WIDEN
);
6460 /* Failing that, generate a compare-and-swap loop in which we perform the
6461 operation with normal arithmetic instructions. */
6462 if (sync_compare_and_swap
[mode
] != CODE_FOR_nothing
)
6464 rtx t0
= gen_reg_rtx (mode
), t1
;
6466 if (!target
|| !register_operand (target
, mode
))
6467 target
= gen_reg_rtx (mode
);
6472 emit_move_insn (target
, t0
);
6476 t1
= expand_simple_unop (mode
, NOT
, t1
, NULL_RTX
, true);
6479 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
,
6480 true, OPTAB_LIB_WIDEN
);
6482 emit_move_insn (target
, t1
);
6484 insn
= get_insns ();
6487 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
6494 /* This function expands a test-and-set operation. Ideally we atomically
6495 store VAL in MEM and return the previous value in MEM. Some targets
6496 may not support this operation and only support VAL with the constant 1;
6497 in this case while the return value will be 0/1, but the exact value
6498 stored in MEM is target defined. TARGET is an option place to stick
6499 the return value. */
6502 expand_sync_lock_test_and_set (rtx mem
, rtx val
, rtx target
)
6504 enum machine_mode mode
= GET_MODE (mem
);
6505 enum insn_code icode
;
6508 /* If the target supports the test-and-set directly, great. */
6509 icode
= sync_lock_test_and_set
[mode
];
6510 if (icode
!= CODE_FOR_nothing
)
6512 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
6513 target
= gen_reg_rtx (mode
);
6515 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
6516 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
6517 if (!insn_data
[icode
].operand
[2].predicate (val
, mode
))
6518 val
= force_reg (mode
, val
);
6520 insn
= GEN_FCN (icode
) (target
, mem
, val
);
6528 /* Otherwise, use a compare-and-swap loop for the exchange. */
6529 if (sync_compare_and_swap
[mode
] != CODE_FOR_nothing
)
6531 if (!target
|| !register_operand (target
, mode
))
6532 target
= gen_reg_rtx (mode
);
6533 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
6534 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
6535 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
6542 #include "gt-optabs.h"