| blob | 300bd3698d6521306d762b66e52cf8dc26657693 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 ])
61 ;;
62 ;; UNSPEC usage
63 ;;
65 (define_c_enum "unspec"
66 [UNSPEC_FRSP ; frsp for POWER machines
67 UNSPEC_PROBE_STACK ; probe stack memory reference
68 UNSPEC_TOCPTR ; address of a word pointing to the TOC
69 UNSPEC_TOC ; address of the TOC (more-or-less)
70 UNSPEC_MOVSI_GOT
71 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
72 UNSPEC_FCTIWZ
73 UNSPEC_FRIM
74 UNSPEC_FRIN
75 UNSPEC_FRIP
76 UNSPEC_FRIZ
77 UNSPEC_LD_MPIC ; load_macho_picbase
78 UNSPEC_RELD_MPIC ; re-load_macho_picbase
79 UNSPEC_MPIC_CORRECT ; macho_correct_pic
80 UNSPEC_TLSGD
81 UNSPEC_TLSLD
82 UNSPEC_MOVESI_FROM_CR
83 UNSPEC_MOVESI_TO_CR
84 UNSPEC_TLSDTPREL
85 UNSPEC_TLSDTPRELHA
86 UNSPEC_TLSDTPRELLO
87 UNSPEC_TLSGOTDTPREL
88 UNSPEC_TLSTPREL
89 UNSPEC_TLSTPRELHA
90 UNSPEC_TLSTPRELLO
91 UNSPEC_TLSGOTTPREL
92 UNSPEC_TLSTLS
93 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
94 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
95 UNSPEC_STFIWX
96 UNSPEC_POPCNTB
97 UNSPEC_FRES
98 UNSPEC_SP_SET
99 UNSPEC_SP_TEST
100 UNSPEC_SYNC
101 UNSPEC_LWSYNC
102 UNSPEC_SYNC_OP
103 UNSPEC_ATOMIC
104 UNSPEC_CMPXCHG
105 UNSPEC_XCHG
106 UNSPEC_AND
107 UNSPEC_DLMZB
108 UNSPEC_DLMZB_CR
109 UNSPEC_DLMZB_STRLEN
110 UNSPEC_RSQRT
111 UNSPEC_TOCREL
112 UNSPEC_MACHOPIC_OFFSET
113 UNSPEC_BPERM
114 UNSPEC_COPYSIGN
115 UNSPEC_PARITY
116 UNSPEC_FCTIW
117 UNSPEC_FCTID
118 UNSPEC_LFIWAX
119 UNSPEC_LFIWZX
120 UNSPEC_FCTIWUZ
121 UNSPEC_GRP_END_NOP
122 UNSPEC_P8V_FMRGOW
123 UNSPEC_P8V_MTVSRWZ
124 UNSPEC_P8V_RELOAD_FROM_GPR
125 UNSPEC_P8V_MTVSRD
126 UNSPEC_P8V_XXPERMDI
127 UNSPEC_P8V_RELOAD_FROM_VSX
128 UNSPEC_ADDG6S
129 UNSPEC_CDTBCD
130 UNSPEC_CBCDTD
131 UNSPEC_DIVE
132 UNSPEC_DIVEO
133 UNSPEC_DIVEU
134 UNSPEC_DIVEUO
135 UNSPEC_UNPACK_128BIT
136 UNSPEC_PACK_128BIT
137 UNSPEC_LSQ
138 ])
140 ;;
141 ;; UNSPEC_VOLATILE usage
142 ;;
144 (define_c_enum "unspecv"
145 [UNSPECV_BLOCK
146 UNSPECV_LL ; load-locked
147 UNSPECV_SC ; store-conditional
148 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
149 UNSPECV_EH_RR ; eh_reg_restore
150 UNSPECV_ISYNC ; isync instruction
151 UNSPECV_MFTB ; move from time base
152 UNSPECV_NLGR ; non-local goto receiver
153 UNSPECV_MFFS ; Move from FPSCR
154 UNSPECV_MTFSF ; Move to FPSCR Fields
155 ])
157 \f
158 ;; Define an insn type attribute. This is used in function unit delay
159 ;; computations.
160 (define_attr "type" "integer,two,three,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"
161 (const_string "integer"))
163 ;; Does this instruction sign-extend its result?
164 ;; This is used for load insns.
165 (define_attr "sign_extend" "no,yes" (const_string "no"))
167 ;; Does this instruction use indexed (that is, reg+reg) addressing?
168 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
169 ;; it is automatically set based on that. If a load or store instruction
170 ;; has fewer than two operands it needs to set this attribute manually
171 ;; or the compiler will crash.
172 (define_attr "indexed" "no,yes"
173 (if_then_else (ior (match_operand 0 "indexed_address_mem")
174 (match_operand 1 "indexed_address_mem"))
175 (const_string "yes")
176 (const_string "no")))
178 ;; Does this instruction use update addressing?
179 ;; This is used for load and store insns. See the comments for "indexed".
180 (define_attr "update" "no,yes"
181 (if_then_else (ior (match_operand 0 "update_address_mem")
182 (match_operand 1 "update_address_mem"))
183 (const_string "yes")
184 (const_string "no")))
186 ;; Define floating point instruction sub-types for use with Xfpu.md
187 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
189 ;; Length (in bytes).
190 ; '(pc)' in the following doesn't include the instruction itself; it is
191 ; calculated as if the instruction had zero size.
192 (define_attr "length" ""
193 (if_then_else (eq_attr "type" "branch")
194 (if_then_else (and (ge (minus (match_dup 0) (pc))
195 (const_int -32768))
196 (lt (minus (match_dup 0) (pc))
197 (const_int 32764)))
198 (const_int 4)
199 (const_int 8))
200 (const_int 4)))
202 ;; Processor type -- this attribute must exactly match the processor_type
203 ;; enumeration in rs6000-opts.h.
204 (define_attr "cpu"
205 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
206 ppc750,ppc7400,ppc7450,
207 ppc403,ppc405,ppc440,ppc476,
208 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
209 power4,power5,power6,power7,power8,
210 rs64a,mpccore,cell,ppca2,titan"
211 (const (symbol_ref "rs6000_cpu_attr")))
214 ;; If this instruction is microcoded on the CELL processor
215 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
216 (define_attr "cell_micro" "not,conditional,always"
217 (if_then_else (ior (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,var_shift_rotate,var_delayed_compare")
218 (and (eq_attr "type" "load")
219 (eq_attr "sign_extend" "yes")))
220 (const_string "always")
221 (const_string "not")))
223 (automata_option "ndfa")
225 (include "rs64.md")
226 (include "mpc.md")
227 (include "40x.md")
228 (include "440.md")
229 (include "476.md")
230 (include "601.md")
231 (include "603.md")
232 (include "6xx.md")
233 (include "7xx.md")
234 (include "7450.md")
235 (include "8540.md")
236 (include "e300c2c3.md")
237 (include "e500mc.md")
238 (include "e500mc64.md")
239 (include "e5500.md")
240 (include "e6500.md")
241 (include "power4.md")
242 (include "power5.md")
243 (include "power6.md")
244 (include "power7.md")
245 (include "power8.md")
246 (include "cell.md")
247 (include "xfpu.md")
248 (include "a2.md")
249 (include "titan.md")
251 (include "predicates.md")
252 (include "constraints.md")
254 (include "darwin.md")
256 \f
257 ;; Mode iterators
259 ; This mode iterator allows :GPR to be used to indicate the allowable size
260 ; of whole values in GPRs.
261 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
263 ; Any supported integer mode.
264 (define_mode_iterator INT [QI HI SI DI TI PTI])
266 ; Any supported integer mode that fits in one register.
267 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
269 ; extend modes for DImode
270 (define_mode_iterator QHSI [QI HI SI])
272 ; QImode or HImode for small atomic ops
273 (define_mode_iterator QHI [QI HI])
275 ; HImode or SImode for sign extended fusion ops
276 (define_mode_iterator HSI [HI SI])
278 ; SImode or DImode, even if DImode doesn't fit in GPRs.
279 (define_mode_iterator SDI [SI DI])
281 ; The size of a pointer. Also, the size of the value that a record-condition
282 ; (one with a '.') will compare; and the size used for arithmetic carries.
283 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
285 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
286 ; PTImode is GPR only)
287 (define_mode_iterator TI2 [TI PTI])
289 ; Any hardware-supported floating-point mode
290 (define_mode_iterator FP [
291 (SF "TARGET_HARD_FLOAT
292 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
293 (DF "TARGET_HARD_FLOAT
294 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
295 (TF "!TARGET_IEEEQUAD
296 && TARGET_HARD_FLOAT
297 && (TARGET_FPRS || TARGET_E500_DOUBLE)
298 && TARGET_LONG_DOUBLE_128")
299 (DD "TARGET_DFP")
300 (TD "TARGET_DFP")])
302 ; Any fma capable floating-point mode.
303 (define_mode_iterator FMA_F [
304 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
305 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
306 || VECTOR_UNIT_VSX_P (DFmode)")
307 (V2SF "TARGET_PAIRED_FLOAT")
308 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
309 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
310 ])
312 ; Floating point move iterators to combine binary and decimal moves
313 (define_mode_iterator FMOVE32 [SF SD])
314 (define_mode_iterator FMOVE64 [DF DD])
315 (define_mode_iterator FMOVE64X [DI DF DD])
316 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
317 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
319 ; Iterators for 128 bit types for direct move
320 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
321 (V16QI "")
322 (V8HI "")
323 (V4SI "")
324 (V4SF "")
325 (V2DI "")
326 (V2DF "")
327 (V1TI "")])
329 ; Whether a floating point move is ok, don't allow SD without hardware FP
330 (define_mode_attr fmove_ok [(SF "")
331 (DF "")
332 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
333 (DD "")])
335 ; Convert REAL_VALUE to the appropriate bits
336 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
337 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
338 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
339 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
341 ; Definitions for load to 32-bit fpr register
342 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
343 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
344 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
345 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
347 ; Definitions for store from 32-bit fpr register
348 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
349 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
350 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
351 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
353 ; Definitions for 32-bit fpr direct move
354 (define_mode_attr f32_dm [(SF "wn") (SD "wm")])
356 ; These modes do not fit in integer registers in 32-bit mode.
357 ; but on e500v2, the gpr are 64 bit registers
358 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
360 ; Iterator for reciprocal estimate instructions
361 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
363 ; Iterator for just SF/DF
364 (define_mode_iterator SFDF [SF DF])
366 ; SF/DF suffix for traditional floating instructions
367 (define_mode_attr Ftrad [(SF "s") (DF "")])
369 ; SF/DF suffix for VSX instructions
370 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
372 ; SF/DF constraint for arithmetic on traditional floating point registers
373 (define_mode_attr Ff [(SF "f") (DF "d")])
375 ; SF/DF constraint for arithmetic on VSX registers
376 (define_mode_attr Fv [(SF "wy") (DF "ws")])
378 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
379 (define_mode_attr Fs [(SF "s") (DF "d")])
381 ; FRE/FRES support
382 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
383 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
385 ; Conditional returns.
386 (define_code_iterator any_return [return simple_return])
387 (define_code_attr return_pred [(return "direct_return ()")
388 (simple_return "1")])
389 (define_code_attr return_str [(return "") (simple_return "simple_")])
391 ; Various instructions that come in SI and DI forms.
392 ; A generic w/d attribute, for things like cmpw/cmpd.
393 (define_mode_attr wd [(QI "b")
394 (HI "h")
395 (SI "w")
396 (DI "d")
397 (V16QI "b")
398 (V8HI "h")
399 (V4SI "w")
400 (V2DI "d")])
402 ; DImode bits
403 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
405 ;; ISEL/ISEL64 target selection
406 (define_mode_attr sel [(SI "") (DI "64")])
408 ;; Suffix for reload patterns
409 (define_mode_attr ptrsize [(SI "32bit")
410 (DI "64bit")])
412 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
413 (DI "TARGET_64BIT")])
415 (define_mode_attr mptrsize [(SI "si")
416 (DI "di")])
418 (define_mode_attr ptrload [(SI "lwz")
419 (DI "ld")])
421 (define_mode_attr ptrm [(SI "m")
422 (DI "Y")])
424 (define_mode_attr rreg [(SF "f")
425 (DF "ws")
426 (TF "f")
427 (TD "f")
428 (V4SF "wf")
429 (V2DF "wd")])
431 (define_mode_attr rreg2 [(SF "f")
432 (DF "d")])
434 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
435 (DF "TARGET_FCFID")])
437 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
438 (DF "TARGET_E500_DOUBLE")])
440 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
441 (DF "TARGET_DOUBLE_FLOAT")])
443 ;; Mode iterator for logical operations on 128-bit types
444 (define_mode_iterator BOOL_128 [TI
445 PTI
446 (V16QI "TARGET_ALTIVEC")
447 (V8HI "TARGET_ALTIVEC")
448 (V4SI "TARGET_ALTIVEC")
449 (V4SF "TARGET_ALTIVEC")
450 (V2DI "TARGET_ALTIVEC")
451 (V2DF "TARGET_ALTIVEC")
452 (V1TI "TARGET_ALTIVEC")])
454 ;; For the GPRs we use 3 constraints for register outputs, two that are the
455 ;; same as the output register, and a third where the output register is an
456 ;; early clobber, so we don't have to deal with register overlaps. For the
457 ;; vector types, we prefer to use the vector registers. For TI mode, allow
458 ;; either.
460 ;; Mode attribute for boolean operation register constraints for output
461 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
462 (PTI "&r,r,r")
463 (V16QI "wa,v,&?r,?r,?r")
464 (V8HI "wa,v,&?r,?r,?r")
465 (V4SI "wa,v,&?r,?r,?r")
466 (V4SF "wa,v,&?r,?r,?r")
467 (V2DI "wa,v,&?r,?r,?r")
468 (V2DF "wa,v,&?r,?r,?r")
469 (V1TI "wa,v,&?r,?r,?r")])
471 ;; Mode attribute for boolean operation register constraints for operand1
472 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
473 (PTI "r,0,r")
474 (V16QI "wa,v,r,0,r")
475 (V8HI "wa,v,r,0,r")
476 (V4SI "wa,v,r,0,r")
477 (V4SF "wa,v,r,0,r")
478 (V2DI "wa,v,r,0,r")
479 (V2DF "wa,v,r,0,r")
480 (V1TI "wa,v,r,0,r")])
482 ;; Mode attribute for boolean operation register constraints for operand2
483 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
484 (PTI "r,r,0")
485 (V16QI "wa,v,r,r,0")
486 (V8HI "wa,v,r,r,0")
487 (V4SI "wa,v,r,r,0")
488 (V4SF "wa,v,r,r,0")
489 (V2DI "wa,v,r,r,0")
490 (V2DF "wa,v,r,r,0")
491 (V1TI "wa,v,r,r,0")])
493 ;; Mode attribute for boolean operation register constraints for operand1
494 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
495 ;; is used for operand1 or operand2
496 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
497 (PTI "r,0,0")
498 (V16QI "wa,v,r,0,0")
499 (V8HI "wa,v,r,0,0")
500 (V4SI "wa,v,r,0,0")
501 (V4SF "wa,v,r,0,0")
502 (V2DI "wa,v,r,0,0")
503 (V2DF "wa,v,r,0,0")
504 (V1TI "wa,v,r,0,0")])
506 ;; Mode attribute for the clobber of CC0 for AND expansion.
507 ;; For the 128-bit types, we never do AND immediate, but we need to
508 ;; get the correct number of X's for the number of operands.
509 (define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
510 (PTI "X,X,X")
511 (V16QI "X,X,X,X,X")
512 (V8HI "X,X,X,X,X")
513 (V4SI "X,X,X,X,X")
514 (V4SF "X,X,X,X,X")
515 (V2DI "X,X,X,X,X")
516 (V2DF "X,X,X,X,X")
517 (V1TI "X,X,X,X,X")])
519 ;; Mode attribute to give the correct type for integer divides
520 (define_mode_attr idiv_ldiv [(SI "idiv")
521 (DI "ldiv")])
523 \f
524 ;; Start with fixed-point load and store insns. Here we put only the more
525 ;; complex forms. Basic data transfer is done later.
527 (define_expand "zero_extend<mode>di2"
528 [(set (match_operand:DI 0 "gpc_reg_operand" "")
529 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
530 "TARGET_POWERPC64"
531 "")
533 (define_insn "*zero_extend<mode>di2_internal1"
534 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
535 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
536 "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
537 "@
538 l<wd>z%U1%X1 %0,%1
539 rldicl %0,%1,0,<dbits>"
540 [(set_attr "type" "load,*")])
542 (define_insn "*zero_extend<mode>di2_internal2"
543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
544 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
545 (const_int 0)))
546 (clobber (match_scratch:DI 2 "=r,r"))]
547 "TARGET_64BIT"
548 "@
549 rldicl. %2,%1,0,<dbits>
550 #"
551 [(set_attr "type" "compare")
552 (set_attr "length" "4,8")])
554 (define_split
555 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
556 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
557 (const_int 0)))
558 (clobber (match_scratch:DI 2 ""))]
559 "TARGET_POWERPC64 && reload_completed"
560 [(set (match_dup 2)
561 (zero_extend:DI (match_dup 1)))
562 (set (match_dup 0)
563 (compare:CC (match_dup 2)
564 (const_int 0)))]
565 "")
567 (define_insn "*zero_extend<mode>di2_internal3"
568 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
569 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
570 (const_int 0)))
571 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
572 (zero_extend:DI (match_dup 1)))]
573 "TARGET_64BIT"
574 "@
575 rldicl. %0,%1,0,<dbits>
576 #"
577 [(set_attr "type" "compare")
578 (set_attr "length" "4,8")])
580 (define_split
581 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
582 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
583 (const_int 0)))
584 (set (match_operand:DI 0 "gpc_reg_operand" "")
585 (zero_extend:DI (match_dup 1)))]
586 "TARGET_POWERPC64 && reload_completed"
587 [(set (match_dup 0)
588 (zero_extend:DI (match_dup 1)))
589 (set (match_dup 2)
590 (compare:CC (match_dup 0)
591 (const_int 0)))]
592 "")
594 (define_insn "*zero_extendsidi2_lfiwzx"
595 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
596 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
597 "TARGET_POWERPC64 && TARGET_LFIWZX"
598 "@
599 lwz%U1%X1 %0,%1
600 rldicl %0,%1,0,32
601 mtvsrwz %x0,%1
602 lfiwzx %0,%y1
603 lxsiwzx %x0,%y1"
604 [(set_attr "type" "load,*,mffgpr,fpload,fpload")])
606 (define_insn "extendqidi2"
607 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
608 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
609 "TARGET_POWERPC64"
610 "extsb %0,%1"
611 [(set_attr "type" "exts")])
613 (define_insn ""
614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
615 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
616 (const_int 0)))
617 (clobber (match_scratch:DI 2 "=r,r"))]
618 "TARGET_64BIT"
619 "@
620 extsb. %2,%1
621 #"
622 [(set_attr "type" "compare")
623 (set_attr "length" "4,8")])
625 (define_split
626 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
627 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
628 (const_int 0)))
629 (clobber (match_scratch:DI 2 ""))]
630 "TARGET_POWERPC64 && reload_completed"
631 [(set (match_dup 2)
632 (sign_extend:DI (match_dup 1)))
633 (set (match_dup 0)
634 (compare:CC (match_dup 2)
635 (const_int 0)))]
636 "")
638 (define_insn ""
639 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
640 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
641 (const_int 0)))
642 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
643 (sign_extend:DI (match_dup 1)))]
644 "TARGET_64BIT"
645 "@
646 extsb. %0,%1
647 #"
648 [(set_attr "type" "compare")
649 (set_attr "length" "4,8")])
651 (define_split
652 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
653 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
654 (const_int 0)))
655 (set (match_operand:DI 0 "gpc_reg_operand" "")
656 (sign_extend:DI (match_dup 1)))]
657 "TARGET_POWERPC64 && reload_completed"
658 [(set (match_dup 0)
659 (sign_extend:DI (match_dup 1)))
660 (set (match_dup 2)
661 (compare:CC (match_dup 0)
662 (const_int 0)))]
663 "")
665 (define_expand "extendhidi2"
666 [(set (match_operand:DI 0 "gpc_reg_operand" "")
667 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
668 "TARGET_POWERPC64"
669 "")
671 (define_insn ""
672 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
673 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
674 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
675 "@
676 lha%U1%X1 %0,%1
677 extsh %0,%1"
678 [(set_attr "type" "load,exts")
679 (set_attr "sign_extend" "yes")])
681 (define_insn ""
682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
683 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
684 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
685 "extsh %0,%1"
686 [(set_attr "type" "exts")])
688 (define_insn ""
689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
690 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (clobber (match_scratch:DI 2 "=r,r"))]
693 "TARGET_64BIT"
694 "@
695 extsh. %2,%1
696 #"
697 [(set_attr "type" "compare")
698 (set_attr "length" "4,8")])
700 (define_split
701 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
702 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
703 (const_int 0)))
704 (clobber (match_scratch:DI 2 ""))]
705 "TARGET_POWERPC64 && reload_completed"
706 [(set (match_dup 2)
707 (sign_extend:DI (match_dup 1)))
708 (set (match_dup 0)
709 (compare:CC (match_dup 2)
710 (const_int 0)))]
711 "")
713 (define_insn ""
714 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
715 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
716 (const_int 0)))
717 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
718 (sign_extend:DI (match_dup 1)))]
719 "TARGET_64BIT"
720 "@
721 extsh. %0,%1
722 #"
723 [(set_attr "type" "compare")
724 (set_attr "length" "4,8")])
726 (define_split
727 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
728 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
729 (const_int 0)))
730 (set (match_operand:DI 0 "gpc_reg_operand" "")
731 (sign_extend:DI (match_dup 1)))]
732 "TARGET_POWERPC64 && reload_completed"
733 [(set (match_dup 0)
734 (sign_extend:DI (match_dup 1)))
735 (set (match_dup 2)
736 (compare:CC (match_dup 0)
737 (const_int 0)))]
738 "")
740 (define_expand "extendsidi2"
741 [(set (match_operand:DI 0 "gpc_reg_operand" "")
742 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
743 "TARGET_POWERPC64"
744 "")
746 (define_insn "*extendsidi2_lfiwax"
747 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
748 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]
749 "TARGET_POWERPC64 && TARGET_LFIWAX"
750 "@
751 lwa%U1%X1 %0,%1
752 extsw %0,%1
753 mtvsrwa %x0,%1
754 lfiwax %0,%y1
755 lxsiwax %x0,%y1"
756 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
757 (set_attr "sign_extend" "yes")])
759 (define_insn "*extendsidi2_nocell"
760 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
761 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
762 "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
763 "@
764 lwa%U1%X1 %0,%1
765 extsw %0,%1"
766 [(set_attr "type" "load,exts")
767 (set_attr "sign_extend" "yes")])
769 (define_insn "*extendsidi2_nocell"
770 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
771 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
772 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
773 "extsw %0,%1"
774 [(set_attr "type" "exts")])
776 (define_insn ""
777 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
778 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
779 (const_int 0)))
780 (clobber (match_scratch:DI 2 "=r,r"))]
781 "TARGET_64BIT"
782 "@
783 extsw. %2,%1
784 #"
785 [(set_attr "type" "compare")
786 (set_attr "length" "4,8")])
788 (define_split
789 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
790 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
791 (const_int 0)))
792 (clobber (match_scratch:DI 2 ""))]
793 "TARGET_POWERPC64 && reload_completed"
794 [(set (match_dup 2)
795 (sign_extend:DI (match_dup 1)))
796 (set (match_dup 0)
797 (compare:CC (match_dup 2)
798 (const_int 0)))]
799 "")
801 (define_insn ""
802 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
803 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
804 (const_int 0)))
805 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
806 (sign_extend:DI (match_dup 1)))]
807 "TARGET_64BIT"
808 "@
809 extsw. %0,%1
810 #"
811 [(set_attr "type" "compare")
812 (set_attr "length" "4,8")])
814 (define_split
815 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
816 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
817 (const_int 0)))
818 (set (match_operand:DI 0 "gpc_reg_operand" "")
819 (sign_extend:DI (match_dup 1)))]
820 "TARGET_POWERPC64 && reload_completed"
821 [(set (match_dup 0)
822 (sign_extend:DI (match_dup 1)))
823 (set (match_dup 2)
824 (compare:CC (match_dup 0)
825 (const_int 0)))]
826 "")
828 (define_expand "zero_extendqisi2"
829 [(set (match_operand:SI 0 "gpc_reg_operand" "")
830 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
831 ""
832 "")
834 (define_insn ""
835 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
836 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
837 ""
838 "@
839 lbz%U1%X1 %0,%1
840 rlwinm %0,%1,0,0xff"
841 [(set_attr "type" "load,*")])
843 (define_insn ""
844 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
845 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
846 (const_int 0)))
847 (clobber (match_scratch:SI 2 "=r,r"))]
848 ""
849 "@
850 andi. %2,%1,0xff
851 #"
852 [(set_attr "type" "fast_compare,compare")
853 (set_attr "length" "4,8")])
855 (define_split
856 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
857 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
858 (const_int 0)))
859 (clobber (match_scratch:SI 2 ""))]
860 "reload_completed"
861 [(set (match_dup 2)
862 (zero_extend:SI (match_dup 1)))
863 (set (match_dup 0)
864 (compare:CC (match_dup 2)
865 (const_int 0)))]
866 "")
868 (define_insn ""
869 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
870 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
871 (const_int 0)))
872 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
873 (zero_extend:SI (match_dup 1)))]
874 ""
875 "@
876 andi. %0,%1,0xff
877 #"
878 [(set_attr "type" "fast_compare,compare")
879 (set_attr "length" "4,8")])
881 (define_split
882 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
883 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
884 (const_int 0)))
885 (set (match_operand:SI 0 "gpc_reg_operand" "")
886 (zero_extend:SI (match_dup 1)))]
887 "reload_completed"
888 [(set (match_dup 0)
889 (zero_extend:SI (match_dup 1)))
890 (set (match_dup 2)
891 (compare:CC (match_dup 0)
892 (const_int 0)))]
893 "")
895 (define_insn "extendqisi2"
896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
897 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
898 ""
899 "extsb %0,%1"
900 [(set_attr "type" "exts")])
902 (define_insn ""
903 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
904 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
905 (const_int 0)))
906 (clobber (match_scratch:SI 2 "=r,r"))]
907 ""
908 "@
909 extsb. %2,%1
910 #"
911 [(set_attr "type" "compare")
912 (set_attr "length" "4,8")])
914 (define_split
915 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
916 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
917 (const_int 0)))
918 (clobber (match_scratch:SI 2 ""))]
919 "reload_completed"
920 [(set (match_dup 2)
921 (sign_extend:SI (match_dup 1)))
922 (set (match_dup 0)
923 (compare:CC (match_dup 2)
924 (const_int 0)))]
925 "")
927 (define_insn ""
928 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
929 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
930 (const_int 0)))
931 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
932 (sign_extend:SI (match_dup 1)))]
933 ""
934 "@
935 extsb. %0,%1
936 #"
937 [(set_attr "type" "compare")
938 (set_attr "length" "4,8")])
940 (define_split
941 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
942 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
943 (const_int 0)))
944 (set (match_operand:SI 0 "gpc_reg_operand" "")
945 (sign_extend:SI (match_dup 1)))]
946 "reload_completed"
947 [(set (match_dup 0)
948 (sign_extend:SI (match_dup 1)))
949 (set (match_dup 2)
950 (compare:CC (match_dup 0)
951 (const_int 0)))]
952 "")
954 (define_insn ""
955 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
956 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
957 ""
958 "@
959 lbz%U1%X1 %0,%1
960 rlwinm %0,%1,0,0xff"
961 [(set_attr "type" "load,*")])
963 (define_insn ""
964 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
965 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
966 (const_int 0)))
967 (clobber (match_scratch:HI 2 "=r,r"))]
968 ""
969 "@
970 andi. %2,%1,0xff
971 #"
972 [(set_attr "type" "fast_compare,compare")
973 (set_attr "length" "4,8")])
975 (define_split
976 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
977 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
978 (const_int 0)))
979 (clobber (match_scratch:HI 2 ""))]
980 "reload_completed"
981 [(set (match_dup 2)
982 (zero_extend:HI (match_dup 1)))
983 (set (match_dup 0)
984 (compare:CC (match_dup 2)
985 (const_int 0)))]
986 "")
988 (define_insn ""
989 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
990 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
991 (const_int 0)))
992 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
993 (zero_extend:HI (match_dup 1)))]
994 ""
995 "@
996 andi. %0,%1,0xff
997 #"
998 [(set_attr "type" "fast_compare,compare")
999 (set_attr "length" "4,8")])
1001 (define_split
1002 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1003 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1004 (const_int 0)))
1005 (set (match_operand:HI 0 "gpc_reg_operand" "")
1006 (zero_extend:HI (match_dup 1)))]
1007 "reload_completed"
1008 [(set (match_dup 0)
1009 (zero_extend:HI (match_dup 1)))
1010 (set (match_dup 2)
1011 (compare:CC (match_dup 0)
1012 (const_int 0)))]
1013 "")
1015 (define_insn "extendqihi2"
1016 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1017 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1018 ""
1019 "extsb %0,%1"
1020 [(set_attr "type" "exts")])
1022 (define_insn ""
1023 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1024 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1025 (const_int 0)))
1026 (clobber (match_scratch:HI 2 "=r,r"))]
1027 ""
1028 "@
1029 extsb. %2,%1
1030 #"
1031 [(set_attr "type" "compare")
1032 (set_attr "length" "4,8")])
1034 (define_split
1035 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1036 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1037 (const_int 0)))
1038 (clobber (match_scratch:HI 2 ""))]
1039 "reload_completed"
1040 [(set (match_dup 2)
1041 (sign_extend:HI (match_dup 1)))
1042 (set (match_dup 0)
1043 (compare:CC (match_dup 2)
1044 (const_int 0)))]
1045 "")
1047 (define_insn ""
1048 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1049 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1050 (const_int 0)))
1051 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1052 (sign_extend:HI (match_dup 1)))]
1053 ""
1054 "@
1055 extsb. %0,%1
1056 #"
1057 [(set_attr "type" "compare")
1058 (set_attr "length" "4,8")])
1060 (define_split
1061 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1062 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1063 (const_int 0)))
1064 (set (match_operand:HI 0 "gpc_reg_operand" "")
1065 (sign_extend:HI (match_dup 1)))]
1066 "reload_completed"
1067 [(set (match_dup 0)
1068 (sign_extend:HI (match_dup 1)))
1069 (set (match_dup 2)
1070 (compare:CC (match_dup 0)
1071 (const_int 0)))]
1072 "")
1074 (define_expand "zero_extendhisi2"
1075 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1076 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1077 ""
1078 "")
1080 (define_insn ""
1081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1082 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1083 ""
1084 "@
1085 lhz%U1%X1 %0,%1
1086 rlwinm %0,%1,0,0xffff"
1087 [(set_attr "type" "load,*")])
1089 (define_insn ""
1090 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1091 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1092 (const_int 0)))
1093 (clobber (match_scratch:SI 2 "=r,r"))]
1094 ""
1095 "@
1096 andi. %2,%1,0xffff
1097 #"
1098 [(set_attr "type" "fast_compare,compare")
1099 (set_attr "length" "4,8")])
1101 (define_split
1102 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1103 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1104 (const_int 0)))
1105 (clobber (match_scratch:SI 2 ""))]
1106 "reload_completed"
1107 [(set (match_dup 2)
1108 (zero_extend:SI (match_dup 1)))
1109 (set (match_dup 0)
1110 (compare:CC (match_dup 2)
1111 (const_int 0)))]
1112 "")
1114 (define_insn ""
1115 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1116 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1117 (const_int 0)))
1118 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1119 (zero_extend:SI (match_dup 1)))]
1120 ""
1121 "@
1122 andi. %0,%1,0xffff
1123 #"
1124 [(set_attr "type" "fast_compare,compare")
1125 (set_attr "length" "4,8")])
1127 (define_split
1128 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1129 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1130 (const_int 0)))
1131 (set (match_operand:SI 0 "gpc_reg_operand" "")
1132 (zero_extend:SI (match_dup 1)))]
1133 "reload_completed"
1134 [(set (match_dup 0)
1135 (zero_extend:SI (match_dup 1)))
1136 (set (match_dup 2)
1137 (compare:CC (match_dup 0)
1138 (const_int 0)))]
1139 "")
1141 (define_expand "extendhisi2"
1142 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1143 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1144 ""
1145 "")
1147 (define_insn ""
1148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1149 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1150 "rs6000_gen_cell_microcode"
1151 "@
1152 lha%U1%X1 %0,%1
1153 extsh %0,%1"
1154 [(set_attr "type" "load,exts")
1155 (set_attr "sign_extend" "yes")])
1157 (define_insn ""
1158 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1159 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1160 "!rs6000_gen_cell_microcode"
1161 "extsh %0,%1"
1162 [(set_attr "type" "exts")])
1164 (define_insn ""
1165 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1166 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1167 (const_int 0)))
1168 (clobber (match_scratch:SI 2 "=r,r"))]
1169 ""
1170 "@
1171 extsh. %2,%1
1172 #"
1173 [(set_attr "type" "compare")
1174 (set_attr "length" "4,8")])
1176 (define_split
1177 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1178 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1179 (const_int 0)))
1180 (clobber (match_scratch:SI 2 ""))]
1181 "reload_completed"
1182 [(set (match_dup 2)
1183 (sign_extend:SI (match_dup 1)))
1184 (set (match_dup 0)
1185 (compare:CC (match_dup 2)
1186 (const_int 0)))]
1187 "")
1189 (define_insn ""
1190 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1191 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1192 (const_int 0)))
1193 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1194 (sign_extend:SI (match_dup 1)))]
1195 ""
1196 "@
1197 extsh. %0,%1
1198 #"
1199 [(set_attr "type" "compare")
1200 (set_attr "length" "4,8")])
1202 (define_split
1203 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1204 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1205 (const_int 0)))
1206 (set (match_operand:SI 0 "gpc_reg_operand" "")
1207 (sign_extend:SI (match_dup 1)))]
1208 "reload_completed"
1209 [(set (match_dup 0)
1210 (sign_extend:SI (match_dup 1)))
1211 (set (match_dup 2)
1212 (compare:CC (match_dup 0)
1213 (const_int 0)))]
1214 "")
1215 \f
1216 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1218 (define_insn "*macchwc"
1219 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1220 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1221 (match_operand:SI 2 "gpc_reg_operand" "r")
1222 (const_int 16))
1223 (sign_extend:SI
1224 (match_operand:HI 1 "gpc_reg_operand" "r")))
1225 (match_operand:SI 4 "gpc_reg_operand" "0"))
1226 (const_int 0)))
1227 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1228 (plus:SI (mult:SI (ashiftrt:SI
1229 (match_dup 2)
1230 (const_int 16))
1231 (sign_extend:SI
1232 (match_dup 1)))
1233 (match_dup 4)))]
1234 "TARGET_MULHW"
1235 "macchw. %0,%1,%2"
1236 [(set_attr "type" "imul3")])
1238 (define_insn "*macchw"
1239 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1240 (plus:SI (mult:SI (ashiftrt:SI
1241 (match_operand:SI 2 "gpc_reg_operand" "r")
1242 (const_int 16))
1243 (sign_extend:SI
1244 (match_operand:HI 1 "gpc_reg_operand" "r")))
1245 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1246 "TARGET_MULHW"
1247 "macchw %0,%1,%2"
1248 [(set_attr "type" "imul3")])
1250 (define_insn "*macchwuc"
1251 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1252 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1253 (match_operand:SI 2 "gpc_reg_operand" "r")
1254 (const_int 16))
1255 (zero_extend:SI
1256 (match_operand:HI 1 "gpc_reg_operand" "r")))
1257 (match_operand:SI 4 "gpc_reg_operand" "0"))
1258 (const_int 0)))
1259 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1260 (plus:SI (mult:SI (lshiftrt:SI
1261 (match_dup 2)
1262 (const_int 16))
1263 (zero_extend:SI
1264 (match_dup 1)))
1265 (match_dup 4)))]
1266 "TARGET_MULHW"
1267 "macchwu. %0,%1,%2"
1268 [(set_attr "type" "imul3")])
1270 (define_insn "*macchwu"
1271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1272 (plus:SI (mult:SI (lshiftrt:SI
1273 (match_operand:SI 2 "gpc_reg_operand" "r")
1274 (const_int 16))
1275 (zero_extend:SI
1276 (match_operand:HI 1 "gpc_reg_operand" "r")))
1277 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1278 "TARGET_MULHW"
1279 "macchwu %0,%1,%2"
1280 [(set_attr "type" "imul3")])
1282 (define_insn "*machhwc"
1283 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1284 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1285 (match_operand:SI 1 "gpc_reg_operand" "%r")
1286 (const_int 16))
1287 (ashiftrt:SI
1288 (match_operand:SI 2 "gpc_reg_operand" "r")
1289 (const_int 16)))
1290 (match_operand:SI 4 "gpc_reg_operand" "0"))
1291 (const_int 0)))
1292 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1293 (plus:SI (mult:SI (ashiftrt:SI
1294 (match_dup 1)
1295 (const_int 16))
1296 (ashiftrt:SI
1297 (match_dup 2)
1298 (const_int 16)))
1299 (match_dup 4)))]
1300 "TARGET_MULHW"
1301 "machhw. %0,%1,%2"
1302 [(set_attr "type" "imul3")])
1304 (define_insn "*machhw"
1305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1306 (plus:SI (mult:SI (ashiftrt:SI
1307 (match_operand:SI 1 "gpc_reg_operand" "%r")
1308 (const_int 16))
1309 (ashiftrt:SI
1310 (match_operand:SI 2 "gpc_reg_operand" "r")
1311 (const_int 16)))
1312 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1313 "TARGET_MULHW"
1314 "machhw %0,%1,%2"
1315 [(set_attr "type" "imul3")])
1317 (define_insn "*machhwuc"
1318 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1319 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1320 (match_operand:SI 1 "gpc_reg_operand" "%r")
1321 (const_int 16))
1322 (lshiftrt:SI
1323 (match_operand:SI 2 "gpc_reg_operand" "r")
1324 (const_int 16)))
1325 (match_operand:SI 4 "gpc_reg_operand" "0"))
1326 (const_int 0)))
1327 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1328 (plus:SI (mult:SI (lshiftrt:SI
1329 (match_dup 1)
1330 (const_int 16))
1331 (lshiftrt:SI
1332 (match_dup 2)
1333 (const_int 16)))
1334 (match_dup 4)))]
1335 "TARGET_MULHW"
1336 "machhwu. %0,%1,%2"
1337 [(set_attr "type" "imul3")])
1339 (define_insn "*machhwu"
1340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1341 (plus:SI (mult:SI (lshiftrt:SI
1342 (match_operand:SI 1 "gpc_reg_operand" "%r")
1343 (const_int 16))
1344 (lshiftrt:SI
1345 (match_operand:SI 2 "gpc_reg_operand" "r")
1346 (const_int 16)))
1347 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1348 "TARGET_MULHW"
1349 "machhwu %0,%1,%2"
1350 [(set_attr "type" "imul3")])
1352 (define_insn "*maclhwc"
1353 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1354 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1355 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1356 (sign_extend:SI
1357 (match_operand:HI 2 "gpc_reg_operand" "r")))
1358 (match_operand:SI 4 "gpc_reg_operand" "0"))
1359 (const_int 0)))
1360 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1361 (plus:SI (mult:SI (sign_extend:SI
1362 (match_dup 1))
1363 (sign_extend:SI
1364 (match_dup 2)))
1365 (match_dup 4)))]
1366 "TARGET_MULHW"
1367 "maclhw. %0,%1,%2"
1368 [(set_attr "type" "imul3")])
1370 (define_insn "*maclhw"
1371 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1372 (plus:SI (mult:SI (sign_extend:SI
1373 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1374 (sign_extend:SI
1375 (match_operand:HI 2 "gpc_reg_operand" "r")))
1376 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1377 "TARGET_MULHW"
1378 "maclhw %0,%1,%2"
1379 [(set_attr "type" "imul3")])
1381 (define_insn "*maclhwuc"
1382 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1383 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1384 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1385 (zero_extend:SI
1386 (match_operand:HI 2 "gpc_reg_operand" "r")))
1387 (match_operand:SI 4 "gpc_reg_operand" "0"))
1388 (const_int 0)))
1389 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1390 (plus:SI (mult:SI (zero_extend:SI
1391 (match_dup 1))
1392 (zero_extend:SI
1393 (match_dup 2)))
1394 (match_dup 4)))]
1395 "TARGET_MULHW"
1396 "maclhwu. %0,%1,%2"
1397 [(set_attr "type" "imul3")])
1399 (define_insn "*maclhwu"
1400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1401 (plus:SI (mult:SI (zero_extend:SI
1402 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1403 (zero_extend:SI
1404 (match_operand:HI 2 "gpc_reg_operand" "r")))
1405 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1406 "TARGET_MULHW"
1407 "maclhwu %0,%1,%2"
1408 [(set_attr "type" "imul3")])
1410 (define_insn "*nmacchwc"
1411 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1412 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1413 (mult:SI (ashiftrt:SI
1414 (match_operand:SI 2 "gpc_reg_operand" "r")
1415 (const_int 16))
1416 (sign_extend:SI
1417 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1418 (const_int 0)))
1419 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1420 (minus:SI (match_dup 4)
1421 (mult:SI (ashiftrt:SI
1422 (match_dup 2)
1423 (const_int 16))
1424 (sign_extend:SI
1425 (match_dup 1)))))]
1426 "TARGET_MULHW"
1427 "nmacchw. %0,%1,%2"
1428 [(set_attr "type" "imul3")])
1430 (define_insn "*nmacchw"
1431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1432 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1433 (mult:SI (ashiftrt:SI
1434 (match_operand:SI 2 "gpc_reg_operand" "r")
1435 (const_int 16))
1436 (sign_extend:SI
1437 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1438 "TARGET_MULHW"
1439 "nmacchw %0,%1,%2"
1440 [(set_attr "type" "imul3")])
1442 (define_insn "*nmachhwc"
1443 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1444 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1445 (mult:SI (ashiftrt:SI
1446 (match_operand:SI 1 "gpc_reg_operand" "%r")
1447 (const_int 16))
1448 (ashiftrt:SI
1449 (match_operand:SI 2 "gpc_reg_operand" "r")
1450 (const_int 16))))
1451 (const_int 0)))
1452 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1453 (minus:SI (match_dup 4)
1454 (mult:SI (ashiftrt:SI
1455 (match_dup 1)
1456 (const_int 16))
1457 (ashiftrt:SI
1458 (match_dup 2)
1459 (const_int 16)))))]
1460 "TARGET_MULHW"
1461 "nmachhw. %0,%1,%2"
1462 [(set_attr "type" "imul3")])
1464 (define_insn "*nmachhw"
1465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1466 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1467 (mult:SI (ashiftrt:SI
1468 (match_operand:SI 1 "gpc_reg_operand" "%r")
1469 (const_int 16))
1470 (ashiftrt:SI
1471 (match_operand:SI 2 "gpc_reg_operand" "r")
1472 (const_int 16)))))]
1473 "TARGET_MULHW"
1474 "nmachhw %0,%1,%2"
1475 [(set_attr "type" "imul3")])
1477 (define_insn "*nmaclhwc"
1478 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1479 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1480 (mult:SI (sign_extend:SI
1481 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1482 (sign_extend:SI
1483 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1484 (const_int 0)))
1485 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1486 (minus:SI (match_dup 4)
1487 (mult:SI (sign_extend:SI
1488 (match_dup 1))
1489 (sign_extend:SI
1490 (match_dup 2)))))]
1491 "TARGET_MULHW"
1492 "nmaclhw. %0,%1,%2"
1493 [(set_attr "type" "imul3")])
1495 (define_insn "*nmaclhw"
1496 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1497 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1498 (mult:SI (sign_extend:SI
1499 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1500 (sign_extend:SI
1501 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1502 "TARGET_MULHW"
1503 "nmaclhw %0,%1,%2"
1504 [(set_attr "type" "imul3")])
1506 (define_insn "*mulchwc"
1507 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1508 (compare:CC (mult:SI (ashiftrt:SI
1509 (match_operand:SI 2 "gpc_reg_operand" "r")
1510 (const_int 16))
1511 (sign_extend:SI
1512 (match_operand:HI 1 "gpc_reg_operand" "r")))
1513 (const_int 0)))
1514 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1515 (mult:SI (ashiftrt:SI
1516 (match_dup 2)
1517 (const_int 16))
1518 (sign_extend:SI
1519 (match_dup 1))))]
1520 "TARGET_MULHW"
1521 "mulchw. %0,%1,%2"
1522 [(set_attr "type" "imul3")])
1524 (define_insn "*mulchw"
1525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1526 (mult:SI (ashiftrt:SI
1527 (match_operand:SI 2 "gpc_reg_operand" "r")
1528 (const_int 16))
1529 (sign_extend:SI
1530 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1531 "TARGET_MULHW"
1532 "mulchw %0,%1,%2"
1533 [(set_attr "type" "imul3")])
1535 (define_insn "*mulchwuc"
1536 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1537 (compare:CC (mult:SI (lshiftrt:SI
1538 (match_operand:SI 2 "gpc_reg_operand" "r")
1539 (const_int 16))
1540 (zero_extend:SI
1541 (match_operand:HI 1 "gpc_reg_operand" "r")))
1542 (const_int 0)))
1543 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1544 (mult:SI (lshiftrt:SI
1545 (match_dup 2)
1546 (const_int 16))
1547 (zero_extend:SI
1548 (match_dup 1))))]
1549 "TARGET_MULHW"
1550 "mulchwu. %0,%1,%2"
1551 [(set_attr "type" "imul3")])
1553 (define_insn "*mulchwu"
1554 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1555 (mult:SI (lshiftrt:SI
1556 (match_operand:SI 2 "gpc_reg_operand" "r")
1557 (const_int 16))
1558 (zero_extend:SI
1559 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1560 "TARGET_MULHW"
1561 "mulchwu %0,%1,%2"
1562 [(set_attr "type" "imul3")])
1564 (define_insn "*mulhhwc"
1565 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1566 (compare:CC (mult:SI (ashiftrt:SI
1567 (match_operand:SI 1 "gpc_reg_operand" "%r")
1568 (const_int 16))
1569 (ashiftrt:SI
1570 (match_operand:SI 2 "gpc_reg_operand" "r")
1571 (const_int 16)))
1572 (const_int 0)))
1573 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1574 (mult:SI (ashiftrt:SI
1575 (match_dup 1)
1576 (const_int 16))
1577 (ashiftrt:SI
1578 (match_dup 2)
1579 (const_int 16))))]
1580 "TARGET_MULHW"
1581 "mulhhw. %0,%1,%2"
1582 [(set_attr "type" "imul3")])
1584 (define_insn "*mulhhw"
1585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1586 (mult:SI (ashiftrt:SI
1587 (match_operand:SI 1 "gpc_reg_operand" "%r")
1588 (const_int 16))
1589 (ashiftrt:SI
1590 (match_operand:SI 2 "gpc_reg_operand" "r")
1591 (const_int 16))))]
1592 "TARGET_MULHW"
1593 "mulhhw %0,%1,%2"
1594 [(set_attr "type" "imul3")])
1596 (define_insn "*mulhhwuc"
1597 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1598 (compare:CC (mult:SI (lshiftrt:SI
1599 (match_operand:SI 1 "gpc_reg_operand" "%r")
1600 (const_int 16))
1601 (lshiftrt:SI
1602 (match_operand:SI 2 "gpc_reg_operand" "r")
1603 (const_int 16)))
1604 (const_int 0)))
1605 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1606 (mult:SI (lshiftrt:SI
1607 (match_dup 1)
1608 (const_int 16))
1609 (lshiftrt:SI
1610 (match_dup 2)
1611 (const_int 16))))]
1612 "TARGET_MULHW"
1613 "mulhhwu. %0,%1,%2"
1614 [(set_attr "type" "imul3")])
1616 (define_insn "*mulhhwu"
1617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1618 (mult:SI (lshiftrt:SI
1619 (match_operand:SI 1 "gpc_reg_operand" "%r")
1620 (const_int 16))
1621 (lshiftrt:SI
1622 (match_operand:SI 2 "gpc_reg_operand" "r")
1623 (const_int 16))))]
1624 "TARGET_MULHW"
1625 "mulhhwu %0,%1,%2"
1626 [(set_attr "type" "imul3")])
1628 (define_insn "*mullhwc"
1629 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1630 (compare:CC (mult:SI (sign_extend:SI
1631 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1632 (sign_extend:SI
1633 (match_operand:HI 2 "gpc_reg_operand" "r")))
1634 (const_int 0)))
1635 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1636 (mult:SI (sign_extend:SI
1637 (match_dup 1))
1638 (sign_extend:SI
1639 (match_dup 2))))]
1640 "TARGET_MULHW"
1641 "mullhw. %0,%1,%2"
1642 [(set_attr "type" "imul3")])
1644 (define_insn "*mullhw"
1645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1646 (mult:SI (sign_extend:SI
1647 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1648 (sign_extend:SI
1649 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1650 "TARGET_MULHW"
1651 "mullhw %0,%1,%2"
1652 [(set_attr "type" "imul3")])
1654 (define_insn "*mullhwuc"
1655 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1656 (compare:CC (mult:SI (zero_extend:SI
1657 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1658 (zero_extend:SI
1659 (match_operand:HI 2 "gpc_reg_operand" "r")))
1660 (const_int 0)))
1661 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1662 (mult:SI (zero_extend:SI
1663 (match_dup 1))
1664 (zero_extend:SI
1665 (match_dup 2))))]
1666 "TARGET_MULHW"
1667 "mullhwu. %0,%1,%2"
1668 [(set_attr "type" "imul3")])
1670 (define_insn "*mullhwu"
1671 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1672 (mult:SI (zero_extend:SI
1673 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1674 (zero_extend:SI
1675 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1676 "TARGET_MULHW"
1677 "mullhwu %0,%1,%2"
1678 [(set_attr "type" "imul3")])
1679 \f
1680 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1681 (define_insn "dlmzb"
1682 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1683 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1684 (match_operand:SI 2 "gpc_reg_operand" "r")]
1685 UNSPEC_DLMZB_CR))
1686 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1687 (unspec:SI [(match_dup 1)
1688 (match_dup 2)]
1689 UNSPEC_DLMZB))]
1690 "TARGET_DLMZB"
1691 "dlmzb. %0,%1,%2")
1693 (define_expand "strlensi"
1694 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1695 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1696 (match_operand:QI 2 "const_int_operand" "")
1697 (match_operand 3 "const_int_operand" "")]
1698 UNSPEC_DLMZB_STRLEN))
1699 (clobber (match_scratch:CC 4 "=x"))]
1700 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1701 {
1702 rtx result = operands[0];
1703 rtx src = operands[1];
1704 rtx search_char = operands[2];
1705 rtx align = operands[3];
1706 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1707 rtx loop_label, end_label, mem, cr0, cond;
1708 if (search_char != const0_rtx
1709 || GET_CODE (align) != CONST_INT
1710 || INTVAL (align) < 8)
1711 FAIL;
1712 word1 = gen_reg_rtx (SImode);
1713 word2 = gen_reg_rtx (SImode);
1714 scratch_dlmzb = gen_reg_rtx (SImode);
1715 scratch_string = gen_reg_rtx (Pmode);
1716 loop_label = gen_label_rtx ();
1717 end_label = gen_label_rtx ();
1718 addr = force_reg (Pmode, XEXP (src, 0));
1719 emit_move_insn (scratch_string, addr);
1720 emit_label (loop_label);
1721 mem = change_address (src, SImode, scratch_string);
1722 emit_move_insn (word1, mem);
1723 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1724 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1725 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1726 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1727 emit_jump_insn (gen_rtx_SET (VOIDmode,
1728 pc_rtx,
1729 gen_rtx_IF_THEN_ELSE (VOIDmode,
1730 cond,
1731 gen_rtx_LABEL_REF
1732 (VOIDmode,
1733 end_label),
1734 pc_rtx)));
1735 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1736 emit_jump_insn (gen_rtx_SET (VOIDmode,
1737 pc_rtx,
1738 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1739 emit_barrier ();
1740 emit_label (end_label);
1741 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1742 emit_insn (gen_subsi3 (result, scratch_string, addr));
1743 emit_insn (gen_subsi3 (result, result, const1_rtx));
1744 DONE;
1745 })
1746 \f
1747 ;; Fixed-point arithmetic insns.
1749 (define_expand "add<mode>3"
1750 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1751 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1752 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1753 ""
1754 {
1755 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1756 {
1757 if (non_short_cint_operand (operands[2], DImode))
1758 FAIL;
1759 }
1760 else if (GET_CODE (operands[2]) == CONST_INT
1761 && ! add_operand (operands[2], <MODE>mode))
1762 {
1763 rtx tmp = ((!can_create_pseudo_p ()
1764 || rtx_equal_p (operands[0], operands[1]))
1765 ? operands[0] : gen_reg_rtx (<MODE>mode));
1767 HOST_WIDE_INT val = INTVAL (operands[2]);
1768 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1769 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1771 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1772 FAIL;
1774 /* The ordering here is important for the prolog expander.
1775 When space is allocated from the stack, adding 'low' first may
1776 produce a temporary deallocation (which would be bad). */
1777 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1778 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1779 DONE;
1780 }
1781 })
1783 ;; Discourage ai/addic because of carry but provide it in an alternative
1784 ;; allowing register zero as source.
1785 (define_insn "*add<mode>3_internal1"
1786 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1787 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1788 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1789 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1790 "@
1791 add %0,%1,%2
1792 addi %0,%1,%2
1793 addic %0,%1,%2
1794 addis %0,%1,%v2"
1795 [(set_attr "length" "4,4,4,4")])
1797 (define_insn "addsi3_high"
1798 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1799 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1800 (high:SI (match_operand 2 "" ""))))]
1801 "TARGET_MACHO && !TARGET_64BIT"
1802 "addis %0,%1,ha16(%2)"
1803 [(set_attr "length" "4")])
1805 (define_insn "*add<mode>3_internal2"
1806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1807 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1808 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1809 (const_int 0)))
1810 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1811 ""
1812 "@
1813 add. %3,%1,%2
1814 addic. %3,%1,%2
1815 #
1816 #"
1817 [(set_attr "type" "fast_compare,compare,compare,compare")
1818 (set_attr "length" "4,4,8,8")])
1820 (define_split
1821 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1822 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1823 (match_operand:GPR 2 "reg_or_short_operand" ""))
1824 (const_int 0)))
1825 (clobber (match_scratch:GPR 3 ""))]
1826 "reload_completed"
1827 [(set (match_dup 3)
1828 (plus:GPR (match_dup 1)
1829 (match_dup 2)))
1830 (set (match_dup 0)
1831 (compare:CC (match_dup 3)
1832 (const_int 0)))]
1833 "")
1835 (define_insn "*add<mode>3_internal3"
1836 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1837 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1838 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1839 (const_int 0)))
1840 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1841 (plus:P (match_dup 1)
1842 (match_dup 2)))]
1843 ""
1844 "@
1845 add. %0,%1,%2
1846 addic. %0,%1,%2
1847 #
1848 #"
1849 [(set_attr "type" "fast_compare,compare,compare,compare")
1850 (set_attr "length" "4,4,8,8")])
1852 (define_split
1853 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1854 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1855 (match_operand:P 2 "reg_or_short_operand" ""))
1856 (const_int 0)))
1857 (set (match_operand:P 0 "gpc_reg_operand" "")
1858 (plus:P (match_dup 1) (match_dup 2)))]
1859 "reload_completed"
1860 [(set (match_dup 0)
1861 (plus:P (match_dup 1)
1862 (match_dup 2)))
1863 (set (match_dup 3)
1864 (compare:CC (match_dup 0)
1865 (const_int 0)))]
1866 "")
1868 ;; Split an add that we can't do in one insn into two insns, each of which
1869 ;; does one 16-bit part. This is used by combine. Note that the low-order
1870 ;; add should be last in case the result gets used in an address.
1872 (define_split
1873 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1874 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1875 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1876 ""
1877 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1878 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1879 {
1880 HOST_WIDE_INT val = INTVAL (operands[2]);
1881 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1882 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1884 operands[4] = GEN_INT (low);
1885 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1886 operands[3] = GEN_INT (rest);
1887 else if (can_create_pseudo_p ())
1888 {
1889 operands[3] = gen_reg_rtx (DImode);
1890 emit_move_insn (operands[3], operands[2]);
1891 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1892 DONE;
1893 }
1894 else
1895 FAIL;
1896 })
1898 (define_expand "one_cmpl<mode>2"
1899 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1900 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1901 ""
1902 {
1903 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1904 {
1905 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
1906 DONE;
1907 }
1908 })
1910 (define_insn "*one_cmpl<mode>2"
1911 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1912 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1913 ""
1914 "nor %0,%1,%1")
1916 (define_insn ""
1917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1918 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1919 (const_int 0)))
1920 (clobber (match_scratch:P 2 "=r,r"))]
1921 ""
1922 "@
1923 nor. %2,%1,%1
1924 #"
1925 [(set_attr "type" "fast_compare,compare")
1926 (set_attr "length" "4,8")])
1928 (define_split
1929 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1930 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1931 (const_int 0)))
1932 (clobber (match_scratch:P 2 ""))]
1933 "reload_completed"
1934 [(set (match_dup 2)
1935 (not:P (match_dup 1)))
1936 (set (match_dup 0)
1937 (compare:CC (match_dup 2)
1938 (const_int 0)))]
1939 "")
1941 (define_insn ""
1942 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1943 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1944 (const_int 0)))
1945 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1946 (not:P (match_dup 1)))]
1947 ""
1948 "@
1949 nor. %0,%1,%1
1950 #"
1951 [(set_attr "type" "fast_compare,compare")
1952 (set_attr "length" "4,8")])
1954 (define_split
1955 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1956 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1957 (const_int 0)))
1958 (set (match_operand:P 0 "gpc_reg_operand" "")
1959 (not:P (match_dup 1)))]
1960 "reload_completed"
1961 [(set (match_dup 0)
1962 (not:P (match_dup 1)))
1963 (set (match_dup 2)
1964 (compare:CC (match_dup 0)
1965 (const_int 0)))]
1966 "")
1968 (define_insn ""
1969 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1970 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1971 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1972 ""
1973 "@
1974 subf %0,%2,%1
1975 subfic %0,%2,%1")
1977 (define_insn ""
1978 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1979 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1980 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1981 (const_int 0)))
1982 (clobber (match_scratch:P 3 "=r,r"))]
1983 ""
1984 "@
1985 subf. %3,%2,%1
1986 #"
1987 [(set_attr "type" "fast_compare")
1988 (set_attr "length" "4,8")])
1990 (define_split
1991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1992 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1993 (match_operand:P 2 "gpc_reg_operand" ""))
1994 (const_int 0)))
1995 (clobber (match_scratch:P 3 ""))]
1996 "reload_completed"
1997 [(set (match_dup 3)
1998 (minus:P (match_dup 1)
1999 (match_dup 2)))
2000 (set (match_dup 0)
2001 (compare:CC (match_dup 3)
2002 (const_int 0)))]
2003 "")
2005 (define_insn ""
2006 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2007 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2008 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2009 (const_int 0)))
2010 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2011 (minus:P (match_dup 1)
2012 (match_dup 2)))]
2013 ""
2014 "@
2015 subf. %0,%2,%1
2016 #"
2017 [(set_attr "type" "fast_compare")
2018 (set_attr "length" "4,8")])
2020 (define_split
2021 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2022 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2023 (match_operand:P 2 "gpc_reg_operand" ""))
2024 (const_int 0)))
2025 (set (match_operand:P 0 "gpc_reg_operand" "")
2026 (minus:P (match_dup 1)
2027 (match_dup 2)))]
2028 "reload_completed"
2029 [(set (match_dup 0)
2030 (minus:P (match_dup 1)
2031 (match_dup 2)))
2032 (set (match_dup 3)
2033 (compare:CC (match_dup 0)
2034 (const_int 0)))]
2035 "")
2037 (define_expand "sub<mode>3"
2038 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2039 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
2040 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
2041 ""
2042 "
2043 {
2044 if (GET_CODE (operands[2]) == CONST_INT)
2045 {
2046 emit_insn (gen_add<mode>3 (operands[0], operands[1],
2047 negate_rtx (<MODE>mode, operands[2])));
2048 DONE;
2049 }
2050 }")
2052 (define_expand "neg<mode>2"
2053 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2054 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2055 ""
2056 "")
2058 (define_insn "*neg<mode>2_internal"
2059 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2060 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2061 ""
2062 "neg %0,%1")
2064 (define_insn ""
2065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2066 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2067 (const_int 0)))
2068 (clobber (match_scratch:P 2 "=r,r"))]
2069 ""
2070 "@
2071 neg. %2,%1
2072 #"
2073 [(set_attr "type" "fast_compare")
2074 (set_attr "length" "4,8")])
2076 (define_split
2077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2078 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2079 (const_int 0)))
2080 (clobber (match_scratch:P 2 ""))]
2081 "reload_completed"
2082 [(set (match_dup 2)
2083 (neg:P (match_dup 1)))
2084 (set (match_dup 0)
2085 (compare:CC (match_dup 2)
2086 (const_int 0)))]
2087 "")
2089 (define_insn ""
2090 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2091 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2092 (const_int 0)))
2093 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2094 (neg:P (match_dup 1)))]
2095 ""
2096 "@
2097 neg. %0,%1
2098 #"
2099 [(set_attr "type" "fast_compare")
2100 (set_attr "length" "4,8")])
2102 (define_split
2103 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2104 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2105 (const_int 0)))
2106 (set (match_operand:P 0 "gpc_reg_operand" "")
2107 (neg:P (match_dup 1)))]
2108 "reload_completed"
2109 [(set (match_dup 0)
2110 (neg:P (match_dup 1)))
2111 (set (match_dup 2)
2112 (compare:CC (match_dup 0)
2113 (const_int 0)))]
2114 "")
2116 (define_insn "clz<mode>2"
2117 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2118 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2119 ""
2120 "cntlz<wd> %0,%1"
2121 [(set_attr "type" "cntlz")])
2123 (define_expand "ctz<mode>2"
2124 [(set (match_dup 2)
2125 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2126 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2127 (match_dup 2)))
2128 (clobber (scratch:CC))])
2129 (set (match_dup 4) (clz:GPR (match_dup 3)))
2130 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2131 (minus:GPR (match_dup 5) (match_dup 4)))]
2132 ""
2133 {
2134 operands[2] = gen_reg_rtx (<MODE>mode);
2135 operands[3] = gen_reg_rtx (<MODE>mode);
2136 operands[4] = gen_reg_rtx (<MODE>mode);
2137 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2138 })
2140 (define_expand "ffs<mode>2"
2141 [(set (match_dup 2)
2142 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2143 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2144 (match_dup 2)))
2145 (clobber (scratch:CC))])
2146 (set (match_dup 4) (clz:GPR (match_dup 3)))
2147 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2148 (minus:GPR (match_dup 5) (match_dup 4)))]
2149 ""
2150 {
2151 operands[2] = gen_reg_rtx (<MODE>mode);
2152 operands[3] = gen_reg_rtx (<MODE>mode);
2153 operands[4] = gen_reg_rtx (<MODE>mode);
2154 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2155 })
2157 (define_insn "popcntb<mode>2"
2158 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2159 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2160 UNSPEC_POPCNTB))]
2161 "TARGET_POPCNTB"
2162 "popcntb %0,%1"
2163 [(set_attr "length" "4")
2164 (set_attr "type" "popcnt")])
2166 (define_insn "popcntd<mode>2"
2167 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2168 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2169 "TARGET_POPCNTD"
2170 "popcnt<wd> %0,%1"
2171 [(set_attr "length" "4")
2172 (set_attr "type" "popcnt")])
2174 (define_expand "popcount<mode>2"
2175 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2176 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2177 "TARGET_POPCNTB || TARGET_POPCNTD"
2178 {
2179 rs6000_emit_popcount (operands[0], operands[1]);
2180 DONE;
2181 })
2183 (define_insn "parity<mode>2_cmpb"
2184 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2185 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2186 "TARGET_CMPB && TARGET_POPCNTB"
2187 "prty<wd> %0,%1"
2188 [(set_attr "length" "4")
2189 (set_attr "type" "popcnt")])
2191 (define_expand "parity<mode>2"
2192 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2193 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2194 "TARGET_POPCNTB"
2195 {
2196 rs6000_emit_parity (operands[0], operands[1]);
2197 DONE;
2198 })
2200 ;; Since the hardware zeros the upper part of the register, save generating the
2201 ;; AND immediate if we are converting to unsigned
2202 (define_insn "*bswaphi2_extenddi"
2203 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2204 (zero_extend:DI
2205 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2206 "TARGET_POWERPC64"
2207 "lhbrx %0,%y1"
2208 [(set_attr "length" "4")
2209 (set_attr "type" "load")])
2211 (define_insn "*bswaphi2_extendsi"
2212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2213 (zero_extend:SI
2214 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2215 ""
2216 "lhbrx %0,%y1"
2217 [(set_attr "length" "4")
2218 (set_attr "type" "load")])
2220 (define_expand "bswaphi2"
2221 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2222 (bswap:HI
2223 (match_operand:HI 1 "reg_or_mem_operand" "")))
2224 (clobber (match_scratch:SI 2 ""))])]
2225 ""
2226 {
2227 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2228 operands[1] = force_reg (HImode, operands[1]);
2229 })
2231 (define_insn "bswaphi2_internal"
2232 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2233 (bswap:HI
2234 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2235 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2236 ""
2237 "@
2238 lhbrx %0,%y1
2239 sthbrx %1,%y0
2240 #"
2241 [(set_attr "length" "4,4,12")
2242 (set_attr "type" "load,store,*")])
2244 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2245 ;; correct for -mlittle as well as -mbig.
2246 (define_split
2247 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2248 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2249 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2250 "reload_completed"
2251 [(set (match_dup 3)
2252 (zero_extract:SI (match_dup 4)
2253 (const_int 8)
2254 (const_int 16)))
2255 (set (match_dup 2)
2256 (and:SI (ashift:SI (match_dup 4)
2257 (const_int 8))
2258 (const_int 65280))) ;; 0xff00
2259 (set (match_dup 3)
2260 (ior:SI (match_dup 3)
2261 (match_dup 2)))]
2262 "
2263 {
2264 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2265 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2266 }")
2268 (define_insn "*bswapsi2_extenddi"
2269 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2270 (zero_extend:DI
2271 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2272 "TARGET_POWERPC64"
2273 "lwbrx %0,%y1"
2274 [(set_attr "length" "4")
2275 (set_attr "type" "load")])
2277 (define_expand "bswapsi2"
2278 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2279 (bswap:SI
2280 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2281 ""
2282 {
2283 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2284 operands[1] = force_reg (SImode, operands[1]);
2285 })
2287 (define_insn "*bswapsi2_internal"
2288 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2289 (bswap:SI
2290 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2291 ""
2292 "@
2293 lwbrx %0,%y1
2294 stwbrx %1,%y0
2295 #"
2296 [(set_attr "length" "4,4,12")
2297 (set_attr "type" "load,store,*")])
2299 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2300 ;; zero_extract insns do not change for -mlittle.
2301 (define_split
2302 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2303 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2304 "reload_completed"
2305 [(set (match_dup 0)
2306 (rotate:SI (match_dup 1) (const_int 8)))
2307 (set (zero_extract:SI (match_dup 0)
2308 (const_int 8)
2309 (const_int 0))
2310 (match_dup 1))
2311 (set (zero_extract:SI (match_dup 0)
2312 (const_int 8)
2313 (const_int 16))
2314 (rotate:SI (match_dup 1)
2315 (const_int 16)))]
2316 "")
2318 (define_expand "bswapdi2"
2319 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2320 (bswap:DI
2321 (match_operand:DI 1 "reg_or_mem_operand" "")))
2322 (clobber (match_scratch:DI 2 ""))
2323 (clobber (match_scratch:DI 3 ""))
2324 (clobber (match_scratch:DI 4 ""))])]
2325 ""
2326 {
2327 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2328 operands[1] = force_reg (DImode, operands[1]);
2330 if (!TARGET_POWERPC64)
2331 {
2332 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2333 that uses 64-bit registers needs the same scratch registers as 64-bit
2334 mode. */
2335 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2336 DONE;
2337 }
2338 })
2340 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2341 (define_insn "*bswapdi2_ldbrx"
2342 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2343 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2344 (clobber (match_scratch:DI 2 "=X,X,&r"))
2345 (clobber (match_scratch:DI 3 "=X,X,&r"))
2346 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2347 "TARGET_POWERPC64 && TARGET_LDBRX
2348 && (REG_P (operands[0]) || REG_P (operands[1]))"
2349 "@
2350 ldbrx %0,%y1
2351 stdbrx %1,%y0
2352 #"
2353 [(set_attr "length" "4,4,36")
2354 (set_attr "type" "load,store,*")])
2356 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2357 (define_insn "*bswapdi2_64bit"
2358 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2359 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2360 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2361 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2362 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2363 "TARGET_POWERPC64 && !TARGET_LDBRX
2364 && (REG_P (operands[0]) || REG_P (operands[1]))
2365 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2366 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2367 "#"
2368 [(set_attr "length" "16,12,36")])
2370 (define_split
2371 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2372 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2373 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2374 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2375 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2376 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2377 [(const_int 0)]
2378 "
2379 {
2380 rtx dest = operands[0];
2381 rtx src = operands[1];
2382 rtx op2 = operands[2];
2383 rtx op3 = operands[3];
2384 rtx op4 = operands[4];
2385 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2386 BYTES_BIG_ENDIAN ? 4 : 0);
2387 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2388 BYTES_BIG_ENDIAN ? 4 : 0);
2389 rtx addr1;
2390 rtx addr2;
2391 rtx word_high;
2392 rtx word_low;
2394 addr1 = XEXP (src, 0);
2395 if (GET_CODE (addr1) == PLUS)
2396 {
2397 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2398 if (TARGET_AVOID_XFORM)
2399 {
2400 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2401 addr2 = op2;
2402 }
2403 else
2404 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2405 }
2406 else if (TARGET_AVOID_XFORM)
2407 {
2408 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2409 addr2 = op2;
2410 }
2411 else
2412 {
2413 emit_move_insn (op2, GEN_INT (4));
2414 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2415 }
2417 if (BYTES_BIG_ENDIAN)
2418 {
2419 word_high = change_address (src, SImode, addr1);
2420 word_low = change_address (src, SImode, addr2);
2421 }
2422 else
2423 {
2424 word_high = change_address (src, SImode, addr2);
2425 word_low = change_address (src, SImode, addr1);
2426 }
2428 emit_insn (gen_bswapsi2 (op3_32, word_low));
2429 emit_insn (gen_bswapsi2 (op4_32, word_high));
2430 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2431 emit_insn (gen_iordi3 (dest, dest, op4));
2432 }")
2434 (define_split
2435 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2436 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2437 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2438 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2439 (clobber (match_operand:DI 4 "" ""))]
2440 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2441 [(const_int 0)]
2442 "
2443 {
2444 rtx dest = operands[0];
2445 rtx src = operands[1];
2446 rtx op2 = operands[2];
2447 rtx op3 = operands[3];
2448 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2449 BYTES_BIG_ENDIAN ? 4 : 0);
2450 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2451 BYTES_BIG_ENDIAN ? 4 : 0);
2452 rtx addr1;
2453 rtx addr2;
2454 rtx word_high;
2455 rtx word_low;
2457 addr1 = XEXP (dest, 0);
2458 if (GET_CODE (addr1) == PLUS)
2459 {
2460 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2461 if (TARGET_AVOID_XFORM)
2462 {
2463 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2464 addr2 = op2;
2465 }
2466 else
2467 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2468 }
2469 else if (TARGET_AVOID_XFORM)
2470 {
2471 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2472 addr2 = op2;
2473 }
2474 else
2475 {
2476 emit_move_insn (op2, GEN_INT (4));
2477 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2478 }
2480 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2481 if (BYTES_BIG_ENDIAN)
2482 {
2483 word_high = change_address (dest, SImode, addr1);
2484 word_low = change_address (dest, SImode, addr2);
2485 }
2486 else
2487 {
2488 word_high = change_address (dest, SImode, addr2);
2489 word_low = change_address (dest, SImode, addr1);
2490 }
2491 emit_insn (gen_bswapsi2 (word_high, src_si));
2492 emit_insn (gen_bswapsi2 (word_low, op3_si));
2493 }")
2495 (define_split
2496 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2497 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2498 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2499 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2500 (clobber (match_operand:DI 4 "" ""))]
2501 "TARGET_POWERPC64 && reload_completed"
2502 [(const_int 0)]
2503 "
2504 {
2505 rtx dest = operands[0];
2506 rtx src = operands[1];
2507 rtx op2 = operands[2];
2508 rtx op3 = operands[3];
2509 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2510 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2511 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2512 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2513 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2515 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2516 emit_insn (gen_bswapsi2 (dest_si, src_si));
2517 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2518 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2519 emit_insn (gen_iordi3 (dest, dest, op3));
2520 }")
2522 (define_insn "bswapdi2_32bit"
2523 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2524 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2525 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2526 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2527 "#"
2528 [(set_attr "length" "16,12,36")])
2530 (define_split
2531 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2532 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2533 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2534 "!TARGET_POWERPC64 && reload_completed"
2535 [(const_int 0)]
2536 "
2537 {
2538 rtx dest = operands[0];
2539 rtx src = operands[1];
2540 rtx op2 = operands[2];
2541 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2542 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2543 rtx addr1;
2544 rtx addr2;
2545 rtx word1;
2546 rtx word2;
2548 addr1 = XEXP (src, 0);
2549 if (GET_CODE (addr1) == PLUS)
2550 {
2551 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2552 if (TARGET_AVOID_XFORM)
2553 {
2554 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2555 addr2 = op2;
2556 }
2557 else
2558 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2559 }
2560 else if (TARGET_AVOID_XFORM)
2561 {
2562 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2563 addr2 = op2;
2564 }
2565 else
2566 {
2567 emit_move_insn (op2, GEN_INT (4));
2568 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2569 }
2571 word1 = change_address (src, SImode, addr1);
2572 word2 = change_address (src, SImode, addr2);
2574 emit_insn (gen_bswapsi2 (dest2, word1));
2575 emit_insn (gen_bswapsi2 (dest1, word2));
2576 }")
2578 (define_split
2579 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2580 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2581 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2582 "!TARGET_POWERPC64 && reload_completed"
2583 [(const_int 0)]
2584 "
2585 {
2586 rtx dest = operands[0];
2587 rtx src = operands[1];
2588 rtx op2 = operands[2];
2589 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2590 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2591 rtx addr1;
2592 rtx addr2;
2593 rtx word1;
2594 rtx word2;
2596 addr1 = XEXP (dest, 0);
2597 if (GET_CODE (addr1) == PLUS)
2598 {
2599 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2600 if (TARGET_AVOID_XFORM)
2601 {
2602 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2603 addr2 = op2;
2604 }
2605 else
2606 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2607 }
2608 else if (TARGET_AVOID_XFORM)
2609 {
2610 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2611 addr2 = op2;
2612 }
2613 else
2614 {
2615 emit_move_insn (op2, GEN_INT (4));
2616 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2617 }
2619 word1 = change_address (dest, SImode, addr1);
2620 word2 = change_address (dest, SImode, addr2);
2622 emit_insn (gen_bswapsi2 (word2, src1));
2623 emit_insn (gen_bswapsi2 (word1, src2));
2624 }")
2626 (define_split
2627 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2628 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2629 (clobber (match_operand:SI 2 "" ""))]
2630 "!TARGET_POWERPC64 && reload_completed"
2631 [(const_int 0)]
2632 "
2633 {
2634 rtx dest = operands[0];
2635 rtx src = operands[1];
2636 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2637 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2638 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2639 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2641 emit_insn (gen_bswapsi2 (dest1, src2));
2642 emit_insn (gen_bswapsi2 (dest2, src1));
2643 }")
2645 (define_insn "mulsi3"
2646 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2647 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2648 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2649 ""
2650 "@
2651 mullw %0,%1,%2
2652 mulli %0,%1,%2"
2653 [(set (attr "type")
2654 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2655 (const_string "imul3")
2656 (match_operand:SI 2 "short_cint_operand" "")
2657 (const_string "imul2")]
2658 (const_string "imul")))])
2660 (define_insn "*mulsi3_internal1"
2661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2662 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2663 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2664 (const_int 0)))
2665 (clobber (match_scratch:SI 3 "=r,r"))]
2666 "TARGET_32BIT"
2667 "@
2668 mullw. %3,%1,%2
2669 #"
2670 [(set_attr "type" "imul_compare")
2671 (set_attr "length" "4,8")])
2673 (define_split
2674 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2675 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2676 (match_operand:SI 2 "gpc_reg_operand" ""))
2677 (const_int 0)))
2678 (clobber (match_scratch:SI 3 ""))]
2679 "TARGET_32BIT && reload_completed"
2680 [(set (match_dup 3)
2681 (mult:SI (match_dup 1) (match_dup 2)))
2682 (set (match_dup 0)
2683 (compare:CC (match_dup 3)
2684 (const_int 0)))]
2685 "")
2687 (define_insn "*mulsi3_internal2"
2688 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2689 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2690 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2691 (const_int 0)))
2692 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2693 (mult:SI (match_dup 1) (match_dup 2)))]
2694 "TARGET_32BIT"
2695 "@
2696 mullw. %0,%1,%2
2697 #"
2698 [(set_attr "type" "imul_compare")
2699 (set_attr "length" "4,8")])
2701 (define_split
2702 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2703 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2704 (match_operand:SI 2 "gpc_reg_operand" ""))
2705 (const_int 0)))
2706 (set (match_operand:SI 0 "gpc_reg_operand" "")
2707 (mult:SI (match_dup 1) (match_dup 2)))]
2708 "TARGET_32BIT && reload_completed"
2709 [(set (match_dup 0)
2710 (mult:SI (match_dup 1) (match_dup 2)))
2711 (set (match_dup 3)
2712 (compare:CC (match_dup 0)
2713 (const_int 0)))]
2714 "")
2717 (define_insn "udiv<mode>3"
2718 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2719 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2720 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2721 ""
2722 "div<wd>u %0,%1,%2"
2723 [(set_attr "type" "<idiv_ldiv>")])
2726 ;; For powers of two we can do srai/aze for divide and then adjust for
2727 ;; modulus. If it isn't a power of two, force operands into register and do
2728 ;; a normal divide.
2729 (define_expand "div<mode>3"
2730 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2731 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2732 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2733 ""
2734 {
2735 if (GET_CODE (operands[2]) != CONST_INT
2736 || INTVAL (operands[2]) <= 0
2737 || exact_log2 (INTVAL (operands[2])) < 0)
2738 operands[2] = force_reg (<MODE>mode, operands[2]);
2739 })
2741 (define_insn "*div<mode>3"
2742 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2743 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2744 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2745 ""
2746 "div<wd> %0,%1,%2"
2747 [(set_attr "type" "<idiv_ldiv>")])
2749 (define_expand "mod<mode>3"
2750 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2751 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2752 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2753 ""
2754 "
2755 {
2756 int i;
2757 rtx temp1;
2758 rtx temp2;
2760 if (GET_CODE (operands[2]) != CONST_INT
2761 || INTVAL (operands[2]) <= 0
2762 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2763 FAIL;
2765 temp1 = gen_reg_rtx (<MODE>mode);
2766 temp2 = gen_reg_rtx (<MODE>mode);
2768 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2769 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2770 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2771 DONE;
2772 }")
2774 (define_insn ""
2775 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2776 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2777 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2778 ""
2779 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2780 [(set_attr "type" "two")
2781 (set_attr "length" "8")])
2783 (define_insn ""
2784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2785 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2786 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2787 (const_int 0)))
2788 (clobber (match_scratch:P 3 "=r,r"))]
2789 ""
2790 "@
2791 sra<wd>i %3,%1,%p2\;addze. %3,%3
2792 #"
2793 [(set_attr "type" "compare")
2794 (set_attr "length" "8,12")
2795 (set_attr "cell_micro" "not")])
2797 (define_split
2798 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2799 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2800 (match_operand:GPR 2 "exact_log2_cint_operand"
2801 ""))
2802 (const_int 0)))
2803 (clobber (match_scratch:GPR 3 ""))]
2804 "reload_completed"
2805 [(set (match_dup 3)
2806 (div:<MODE> (match_dup 1) (match_dup 2)))
2807 (set (match_dup 0)
2808 (compare:CC (match_dup 3)
2809 (const_int 0)))]
2810 "")
2812 (define_insn ""
2813 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2814 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2815 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2816 (const_int 0)))
2817 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2818 (div:P (match_dup 1) (match_dup 2)))]
2819 ""
2820 "@
2821 sra<wd>i %0,%1,%p2\;addze. %0,%0
2822 #"
2823 [(set_attr "type" "compare")
2824 (set_attr "length" "8,12")
2825 (set_attr "cell_micro" "not")])
2827 (define_split
2828 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2829 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2830 (match_operand:GPR 2 "exact_log2_cint_operand"
2831 ""))
2832 (const_int 0)))
2833 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2834 (div:GPR (match_dup 1) (match_dup 2)))]
2835 "reload_completed"
2836 [(set (match_dup 0)
2837 (div:<MODE> (match_dup 1) (match_dup 2)))
2838 (set (match_dup 3)
2839 (compare:CC (match_dup 0)
2840 (const_int 0)))]
2841 "")
2842 \f
2843 ;; Logical instructions
2844 ;; The logical instructions are mostly combined by using match_operator,
2845 ;; but the plain AND insns are somewhat different because there is no
2846 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2847 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2849 (define_expand "andsi3"
2850 [(parallel
2851 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2852 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2853 (match_operand:SI 2 "and_operand" "")))
2854 (clobber (match_scratch:CC 3 ""))])]
2855 ""
2856 "")
2858 (define_insn "andsi3_mc"
2859 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2860 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2861 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2862 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2863 "rs6000_gen_cell_microcode"
2864 "@
2865 and %0,%1,%2
2866 rlwinm %0,%1,0,%m2,%M2
2867 andi. %0,%1,%b2
2868 andis. %0,%1,%u2"
2869 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2871 (define_insn "andsi3_nomc"
2872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2873 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2874 (match_operand:SI 2 "and_operand" "?r,T")))
2875 (clobber (match_scratch:CC 3 "=X,X"))]
2876 "!rs6000_gen_cell_microcode"
2877 "@
2878 and %0,%1,%2
2879 rlwinm %0,%1,0,%m2,%M2")
2881 (define_insn "andsi3_internal0_nomc"
2882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2883 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2884 (match_operand:SI 2 "and_operand" "?r,T")))]
2885 "!rs6000_gen_cell_microcode"
2886 "@
2887 and %0,%1,%2
2888 rlwinm %0,%1,0,%m2,%M2")
2891 ;; Note to set cr's other than cr0 we do the and immediate and then
2892 ;; the test again -- this avoids a mfcr which on the higher end
2893 ;; machines causes an execution serialization
2895 (define_insn "*andsi3_internal2_mc"
2896 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2897 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2898 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2899 (const_int 0)))
2900 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2901 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2902 "TARGET_32BIT && rs6000_gen_cell_microcode"
2903 "@
2904 and. %3,%1,%2
2905 andi. %3,%1,%b2
2906 andis. %3,%1,%u2
2907 rlwinm. %3,%1,0,%m2,%M2
2908 #
2909 #
2910 #
2911 #"
2912 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2913 compare,compare,compare,compare")
2914 (set_attr "length" "4,4,4,4,8,8,8,8")])
2916 (define_insn "*andsi3_internal3_mc"
2917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2918 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2919 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2920 (const_int 0)))
2921 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2922 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2923 "TARGET_64BIT && rs6000_gen_cell_microcode"
2924 "@
2925 #
2926 andi. %3,%1,%b2
2927 andis. %3,%1,%u2
2928 rlwinm. %3,%1,0,%m2,%M2
2929 #
2930 #
2931 #
2932 #"
2933 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2934 compare,compare,compare")
2935 (set_attr "length" "8,4,4,4,8,8,8,8")])
2937 (define_split
2938 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2939 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2940 (match_operand:GPR 2 "and_operand" ""))
2941 (const_int 0)))
2942 (clobber (match_scratch:GPR 3 ""))
2943 (clobber (match_scratch:CC 4 ""))]
2944 "reload_completed"
2945 [(parallel [(set (match_dup 3)
2946 (and:<MODE> (match_dup 1)
2947 (match_dup 2)))
2948 (clobber (match_dup 4))])
2949 (set (match_dup 0)
2950 (compare:CC (match_dup 3)
2951 (const_int 0)))]
2952 "")
2954 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2955 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2957 (define_split
2958 [(set (match_operand:CC 0 "cc_reg_operand" "")
2959 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2960 (match_operand:SI 2 "gpc_reg_operand" ""))
2961 (const_int 0)))
2962 (clobber (match_scratch:SI 3 ""))
2963 (clobber (match_scratch:CC 4 ""))]
2964 "TARGET_POWERPC64 && reload_completed"
2965 [(parallel [(set (match_dup 3)
2966 (and:SI (match_dup 1)
2967 (match_dup 2)))
2968 (clobber (match_dup 4))])
2969 (set (match_dup 0)
2970 (compare:CC (match_dup 3)
2971 (const_int 0)))]
2972 "")
2974 (define_insn "*andsi3_internal4"
2975 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2976 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2977 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2978 (const_int 0)))
2979 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2980 (and:SI (match_dup 1)
2981 (match_dup 2)))
2982 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2983 "TARGET_32BIT && rs6000_gen_cell_microcode"
2984 "@
2985 and. %0,%1,%2
2986 andi. %0,%1,%b2
2987 andis. %0,%1,%u2
2988 rlwinm. %0,%1,0,%m2,%M2
2989 #
2990 #
2991 #
2992 #"
2993 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2994 compare,compare,compare,compare")
2995 (set_attr "length" "4,4,4,4,8,8,8,8")])
2997 (define_insn "*andsi3_internal5_mc"
2998 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2999 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3000 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3001 (const_int 0)))
3002 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3003 (and:SI (match_dup 1)
3004 (match_dup 2)))
3005 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3006 "TARGET_64BIT && rs6000_gen_cell_microcode"
3007 "@
3008 #
3009 andi. %0,%1,%b2
3010 andis. %0,%1,%u2
3011 rlwinm. %0,%1,0,%m2,%M2
3012 #
3013 #
3014 #
3015 #"
3016 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3017 compare,compare,compare")
3018 (set_attr "length" "8,4,4,4,8,8,8,8")])
3020 (define_split
3021 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3022 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3023 (match_operand:SI 2 "and_operand" ""))
3024 (const_int 0)))
3025 (set (match_operand:SI 0 "gpc_reg_operand" "")
3026 (and:SI (match_dup 1)
3027 (match_dup 2)))
3028 (clobber (match_scratch:CC 4 ""))]
3029 "reload_completed"
3030 [(parallel [(set (match_dup 0)
3031 (and:SI (match_dup 1)
3032 (match_dup 2)))
3033 (clobber (match_dup 4))])
3034 (set (match_dup 3)
3035 (compare:CC (match_dup 0)
3036 (const_int 0)))]
3037 "")
3039 (define_split
3040 [(set (match_operand:CC 3 "cc_reg_operand" "")
3041 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3042 (match_operand:SI 2 "gpc_reg_operand" ""))
3043 (const_int 0)))
3044 (set (match_operand:SI 0 "gpc_reg_operand" "")
3045 (and:SI (match_dup 1)
3046 (match_dup 2)))
3047 (clobber (match_scratch:CC 4 ""))]
3048 "TARGET_POWERPC64 && reload_completed"
3049 [(parallel [(set (match_dup 0)
3050 (and:SI (match_dup 1)
3051 (match_dup 2)))
3052 (clobber (match_dup 4))])
3053 (set (match_dup 3)
3054 (compare:CC (match_dup 0)
3055 (const_int 0)))]
3056 "")
3058 ;; Handle the PowerPC64 rlwinm corner case
3060 (define_insn_and_split "*andsi3_internal6"
3061 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3062 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3063 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3064 "TARGET_POWERPC64"
3065 "#"
3066 "TARGET_POWERPC64"
3067 [(set (match_dup 0)
3068 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3069 (match_dup 4)))
3070 (set (match_dup 0)
3071 (rotate:SI (match_dup 0) (match_dup 5)))]
3072 "
3073 {
3074 int mb = extract_MB (operands[2]);
3075 int me = extract_ME (operands[2]);
3076 operands[3] = GEN_INT (me + 1);
3077 operands[5] = GEN_INT (32 - (me + 1));
3078 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3079 }"
3080 [(set_attr "length" "8")])
3082 (define_expand "iorsi3"
3083 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3084 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3085 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3086 ""
3087 "
3088 {
3089 if (GET_CODE (operands[2]) == CONST_INT
3090 && ! logical_operand (operands[2], SImode))
3091 {
3092 HOST_WIDE_INT value = INTVAL (operands[2]);
3093 rtx tmp = ((!can_create_pseudo_p ()
3094 || rtx_equal_p (operands[0], operands[1]))
3095 ? operands[0] : gen_reg_rtx (SImode));
3097 emit_insn (gen_iorsi3 (tmp, operands[1],
3098 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3099 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3100 DONE;
3101 }
3102 }")
3104 (define_expand "xorsi3"
3105 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3106 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3107 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3108 ""
3109 "
3110 {
3111 if (GET_CODE (operands[2]) == CONST_INT
3112 && ! logical_operand (operands[2], SImode))
3113 {
3114 HOST_WIDE_INT value = INTVAL (operands[2]);
3115 rtx tmp = ((!can_create_pseudo_p ()
3116 || rtx_equal_p (operands[0], operands[1]))
3117 ? operands[0] : gen_reg_rtx (SImode));
3119 emit_insn (gen_xorsi3 (tmp, operands[1],
3120 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3121 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3122 DONE;
3123 }
3124 }")
3126 (define_insn "*boolsi3_internal1"
3127 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3128 (match_operator:SI 3 "boolean_or_operator"
3129 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3130 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3131 ""
3132 "@
3133 %q3 %0,%1,%2
3134 %q3i %0,%1,%b2
3135 %q3is %0,%1,%u2")
3137 (define_insn "*boolsi3_internal2"
3138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3139 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3140 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3141 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3142 (const_int 0)))
3143 (clobber (match_scratch:SI 3 "=r,r"))]
3144 "TARGET_32BIT"
3145 "@
3146 %q4. %3,%1,%2
3147 #"
3148 [(set_attr "type" "fast_compare,compare")
3149 (set_attr "length" "4,8")])
3151 (define_split
3152 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3153 (compare:CC (match_operator:SI 4 "boolean_operator"
3154 [(match_operand:SI 1 "gpc_reg_operand" "")
3155 (match_operand:SI 2 "gpc_reg_operand" "")])
3156 (const_int 0)))
3157 (clobber (match_scratch:SI 3 ""))]
3158 "TARGET_32BIT && reload_completed"
3159 [(set (match_dup 3) (match_dup 4))
3160 (set (match_dup 0)
3161 (compare:CC (match_dup 3)
3162 (const_int 0)))]
3163 "")
3165 (define_insn "*boolsi3_internal3"
3166 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3167 (compare:CC (match_operator:SI 4 "boolean_operator"
3168 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3169 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3170 (const_int 0)))
3171 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3172 (match_dup 4))]
3173 "TARGET_32BIT"
3174 "@
3175 %q4. %0,%1,%2
3176 #"
3177 [(set_attr "type" "fast_compare,compare")
3178 (set_attr "length" "4,8")])
3180 (define_split
3181 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3182 (compare:CC (match_operator:SI 4 "boolean_operator"
3183 [(match_operand:SI 1 "gpc_reg_operand" "")
3184 (match_operand:SI 2 "gpc_reg_operand" "")])
3185 (const_int 0)))
3186 (set (match_operand:SI 0 "gpc_reg_operand" "")
3187 (match_dup 4))]
3188 "TARGET_32BIT && reload_completed"
3189 [(set (match_dup 0) (match_dup 4))
3190 (set (match_dup 3)
3191 (compare:CC (match_dup 0)
3192 (const_int 0)))]
3193 "")
3195 ;; Split a logical operation that we can't do in one insn into two insns,
3196 ;; each of which does one 16-bit part. This is used by combine.
3198 (define_split
3199 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3200 (match_operator:SI 3 "boolean_or_operator"
3201 [(match_operand:SI 1 "gpc_reg_operand" "")
3202 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3203 ""
3204 [(set (match_dup 0) (match_dup 4))
3205 (set (match_dup 0) (match_dup 5))]
3206 "
3207 {
3208 rtx i;
3209 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3210 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3211 operands[1], i);
3212 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3213 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3214 operands[0], i);
3215 }")
3217 (define_insn "*boolcsi3_internal1"
3218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3219 (match_operator:SI 3 "boolean_operator"
3220 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3221 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3222 ""
3223 "%q3 %0,%2,%1")
3225 (define_insn "*boolcsi3_internal2"
3226 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3227 (compare:CC (match_operator:SI 4 "boolean_operator"
3228 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3229 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3230 (const_int 0)))
3231 (clobber (match_scratch:SI 3 "=r,r"))]
3232 "TARGET_32BIT"
3233 "@
3234 %q4. %3,%2,%1
3235 #"
3236 [(set_attr "type" "compare")
3237 (set_attr "length" "4,8")])
3239 (define_split
3240 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3241 (compare:CC (match_operator:SI 4 "boolean_operator"
3242 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3243 (match_operand:SI 2 "gpc_reg_operand" "")])
3244 (const_int 0)))
3245 (clobber (match_scratch:SI 3 ""))]
3246 "TARGET_32BIT && reload_completed"
3247 [(set (match_dup 3) (match_dup 4))
3248 (set (match_dup 0)
3249 (compare:CC (match_dup 3)
3250 (const_int 0)))]
3251 "")
3253 (define_insn "*boolcsi3_internal3"
3254 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3255 (compare:CC (match_operator:SI 4 "boolean_operator"
3256 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3257 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3258 (const_int 0)))
3259 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3260 (match_dup 4))]
3261 "TARGET_32BIT"
3262 "@
3263 %q4. %0,%2,%1
3264 #"
3265 [(set_attr "type" "compare")
3266 (set_attr "length" "4,8")])
3268 (define_split
3269 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3270 (compare:CC (match_operator:SI 4 "boolean_operator"
3271 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3272 (match_operand:SI 2 "gpc_reg_operand" "")])
3273 (const_int 0)))
3274 (set (match_operand:SI 0 "gpc_reg_operand" "")
3275 (match_dup 4))]
3276 "TARGET_32BIT && reload_completed"
3277 [(set (match_dup 0) (match_dup 4))
3278 (set (match_dup 3)
3279 (compare:CC (match_dup 0)
3280 (const_int 0)))]
3281 "")
3283 (define_insn "*boolccsi3_internal1"
3284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3285 (match_operator:SI 3 "boolean_operator"
3286 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3287 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3288 ""
3289 "%q3 %0,%1,%2")
3291 (define_insn "*boolccsi3_internal2"
3292 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3293 (compare:CC (match_operator:SI 4 "boolean_operator"
3294 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3295 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3296 (const_int 0)))
3297 (clobber (match_scratch:SI 3 "=r,r"))]
3298 "TARGET_32BIT"
3299 "@
3300 %q4. %3,%1,%2
3301 #"
3302 [(set_attr "type" "fast_compare,compare")
3303 (set_attr "length" "4,8")])
3305 (define_split
3306 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3307 (compare:CC (match_operator:SI 4 "boolean_operator"
3308 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3309 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3310 (const_int 0)))
3311 (clobber (match_scratch:SI 3 ""))]
3312 "TARGET_32BIT && reload_completed"
3313 [(set (match_dup 3) (match_dup 4))
3314 (set (match_dup 0)
3315 (compare:CC (match_dup 3)
3316 (const_int 0)))]
3317 "")
3319 (define_insn "*boolccsi3_internal3"
3320 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3321 (compare:CC (match_operator:SI 4 "boolean_operator"
3322 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3323 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3324 (const_int 0)))
3325 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3326 (match_dup 4))]
3327 "TARGET_32BIT"
3328 "@
3329 %q4. %0,%1,%2
3330 #"
3331 [(set_attr "type" "fast_compare,compare")
3332 (set_attr "length" "4,8")])
3334 (define_split
3335 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3336 (compare:CC (match_operator:SI 4 "boolean_operator"
3337 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3338 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3339 (const_int 0)))
3340 (set (match_operand:SI 0 "gpc_reg_operand" "")
3341 (match_dup 4))]
3342 "TARGET_32BIT && reload_completed"
3343 [(set (match_dup 0) (match_dup 4))
3344 (set (match_dup 3)
3345 (compare:CC (match_dup 0)
3346 (const_int 0)))]
3347 "")
3348 \f
3349 ;; Rotate and shift insns, in all their variants. These support shifts,
3350 ;; field inserts and extracts, and various combinations thereof.
3351 (define_expand "insv"
3352 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3353 (match_operand:SI 1 "const_int_operand" "")
3354 (match_operand:SI 2 "const_int_operand" ""))
3355 (match_operand 3 "gpc_reg_operand" ""))]
3356 ""
3357 "
3358 {
3359 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3360 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3361 compiler if the address of the structure is taken later. Likewise, do
3362 not handle invalid E500 subregs. */
3363 if (GET_CODE (operands[0]) == SUBREG
3364 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3365 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3366 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3367 FAIL;
3369 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3370 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3371 operands[3]));
3372 else
3373 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3374 operands[3]));
3375 DONE;
3376 }")
3378 (define_insn "insvsi_internal"
3379 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3380 (match_operand:SI 1 "const_int_operand" "i")
3381 (match_operand:SI 2 "const_int_operand" "i"))
3382 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3383 ""
3384 "*
3385 {
3386 int start = INTVAL (operands[2]) & 31;
3387 int size = INTVAL (operands[1]) & 31;
3389 operands[4] = GEN_INT (32 - start - size);
3390 operands[1] = GEN_INT (start + size - 1);
3391 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3392 }"
3393 [(set_attr "type" "insert_word")])
3395 (define_insn "*insvsi_internal1"
3396 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3397 (match_operand:SI 1 "const_int_operand" "i")
3398 (match_operand:SI 2 "const_int_operand" "i"))
3399 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3400 (match_operand:SI 4 "const_int_operand" "i")))]
3401 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3402 "*
3403 {
3404 int shift = INTVAL (operands[4]) & 31;
3405 int start = INTVAL (operands[2]) & 31;
3406 int size = INTVAL (operands[1]) & 31;
3408 operands[4] = GEN_INT (shift - start - size);
3409 operands[1] = GEN_INT (start + size - 1);
3410 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3411 }"
3412 [(set_attr "type" "insert_word")])
3414 (define_insn "*insvsi_internal2"
3415 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3416 (match_operand:SI 1 "const_int_operand" "i")
3417 (match_operand:SI 2 "const_int_operand" "i"))
3418 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3419 (match_operand:SI 4 "const_int_operand" "i")))]
3420 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3421 "*
3422 {
3423 int shift = INTVAL (operands[4]) & 31;
3424 int start = INTVAL (operands[2]) & 31;
3425 int size = INTVAL (operands[1]) & 31;
3427 operands[4] = GEN_INT (32 - shift - start - size);
3428 operands[1] = GEN_INT (start + size - 1);
3429 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3430 }"
3431 [(set_attr "type" "insert_word")])
3433 (define_insn "*insvsi_internal3"
3434 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3435 (match_operand:SI 1 "const_int_operand" "i")
3436 (match_operand:SI 2 "const_int_operand" "i"))
3437 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3438 (match_operand:SI 4 "const_int_operand" "i")))]
3439 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3440 "*
3441 {
3442 int shift = INTVAL (operands[4]) & 31;
3443 int start = INTVAL (operands[2]) & 31;
3444 int size = INTVAL (operands[1]) & 31;
3446 operands[4] = GEN_INT (32 - shift - start - size);
3447 operands[1] = GEN_INT (start + size - 1);
3448 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3449 }"
3450 [(set_attr "type" "insert_word")])
3452 (define_insn "*insvsi_internal4"
3453 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3454 (match_operand:SI 1 "const_int_operand" "i")
3455 (match_operand:SI 2 "const_int_operand" "i"))
3456 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3457 (match_operand:SI 4 "const_int_operand" "i")
3458 (match_operand:SI 5 "const_int_operand" "i")))]
3459 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3460 "*
3461 {
3462 int extract_start = INTVAL (operands[5]) & 31;
3463 int extract_size = INTVAL (operands[4]) & 31;
3464 int insert_start = INTVAL (operands[2]) & 31;
3465 int insert_size = INTVAL (operands[1]) & 31;
3467 /* Align extract field with insert field */
3468 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3469 operands[1] = GEN_INT (insert_start + insert_size - 1);
3470 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3471 }"
3472 [(set_attr "type" "insert_word")])
3474 ;; combine patterns for rlwimi
3475 (define_insn "*insvsi_internal5"
3476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3477 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3478 (match_operand:SI 1 "mask_operand" "i"))
3479 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3480 (match_operand:SI 2 "const_int_operand" "i"))
3481 (match_operand:SI 5 "mask_operand" "i"))))]
3482 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3483 "*
3484 {
3485 int me = extract_ME(operands[5]);
3486 int mb = extract_MB(operands[5]);
3487 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3488 operands[2] = GEN_INT(mb);
3489 operands[1] = GEN_INT(me);
3490 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3491 }"
3492 [(set_attr "type" "insert_word")])
3494 (define_insn "*insvsi_internal6"
3495 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3496 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3497 (match_operand:SI 2 "const_int_operand" "i"))
3498 (match_operand:SI 5 "mask_operand" "i"))
3499 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3500 (match_operand:SI 1 "mask_operand" "i"))))]
3501 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3502 "*
3503 {
3504 int me = extract_ME(operands[5]);
3505 int mb = extract_MB(operands[5]);
3506 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3507 operands[2] = GEN_INT(mb);
3508 operands[1] = GEN_INT(me);
3509 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3510 }"
3511 [(set_attr "type" "insert_word")])
3513 (define_insn "insvdi_internal"
3514 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3515 (match_operand:SI 1 "const_int_operand" "i")
3516 (match_operand:SI 2 "const_int_operand" "i"))
3517 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3518 "TARGET_POWERPC64"
3519 "*
3520 {
3521 int start = INTVAL (operands[2]) & 63;
3522 int size = INTVAL (operands[1]) & 63;
3524 operands[1] = GEN_INT (64 - start - size);
3525 return \"rldimi %0,%3,%H1,%H2\";
3526 }"
3527 [(set_attr "type" "insert_dword")])
3529 (define_insn "*insvdi_internal2"
3530 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3531 (match_operand:SI 1 "const_int_operand" "i")
3532 (match_operand:SI 2 "const_int_operand" "i"))
3533 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3534 (match_operand:SI 4 "const_int_operand" "i")))]
3535 "TARGET_POWERPC64
3536 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3537 "*
3538 {
3539 int shift = INTVAL (operands[4]) & 63;
3540 int start = (INTVAL (operands[2]) & 63) - 32;
3541 int size = INTVAL (operands[1]) & 63;
3543 operands[4] = GEN_INT (64 - shift - start - size);
3544 operands[2] = GEN_INT (start);
3545 operands[1] = GEN_INT (start + size - 1);
3546 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3547 }")
3549 (define_insn "*insvdi_internal3"
3550 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3551 (match_operand:SI 1 "const_int_operand" "i")
3552 (match_operand:SI 2 "const_int_operand" "i"))
3553 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3554 (match_operand:SI 4 "const_int_operand" "i")))]
3555 "TARGET_POWERPC64
3556 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3557 "*
3558 {
3559 int shift = INTVAL (operands[4]) & 63;
3560 int start = (INTVAL (operands[2]) & 63) - 32;
3561 int size = INTVAL (operands[1]) & 63;
3563 operands[4] = GEN_INT (64 - shift - start - size);
3564 operands[2] = GEN_INT (start);
3565 operands[1] = GEN_INT (start + size - 1);
3566 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3567 }")
3569 (define_expand "extzv"
3570 [(set (match_operand 0 "gpc_reg_operand" "")
3571 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3572 (match_operand:SI 2 "const_int_operand" "")
3573 (match_operand:SI 3 "const_int_operand" "")))]
3574 ""
3575 "
3576 {
3577 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3578 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3579 compiler if the address of the structure is taken later. */
3580 if (GET_CODE (operands[0]) == SUBREG
3581 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3582 FAIL;
3584 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3585 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3586 operands[3]));
3587 else
3588 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3589 operands[3]));
3590 DONE;
3591 }")
3593 (define_insn "extzvsi_internal"
3594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3595 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3596 (match_operand:SI 2 "const_int_operand" "i")
3597 (match_operand:SI 3 "const_int_operand" "i")))]
3598 ""
3599 "*
3600 {
3601 int start = INTVAL (operands[3]) & 31;
3602 int size = INTVAL (operands[2]) & 31;
3604 if (start + size >= 32)
3605 operands[3] = const0_rtx;
3606 else
3607 operands[3] = GEN_INT (start + size);
3608 return \"rlwinm %0,%1,%3,%s2,31\";
3609 }")
3611 (define_insn "*extzvsi_internal1"
3612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3613 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3614 (match_operand:SI 2 "const_int_operand" "i,i")
3615 (match_operand:SI 3 "const_int_operand" "i,i"))
3616 (const_int 0)))
3617 (clobber (match_scratch:SI 4 "=r,r"))]
3618 ""
3619 "*
3620 {
3621 int start = INTVAL (operands[3]) & 31;
3622 int size = INTVAL (operands[2]) & 31;
3624 /* Force split for non-cc0 compare. */
3625 if (which_alternative == 1)
3626 return \"#\";
3628 /* If the bit-field being tested fits in the upper or lower half of a
3629 word, it is possible to use andiu. or andil. to test it. This is
3630 useful because the condition register set-use delay is smaller for
3631 andi[ul]. than for rlinm. This doesn't work when the starting bit
3632 position is 0 because the LT and GT bits may be set wrong. */
3634 if ((start > 0 && start + size <= 16) || start >= 16)
3635 {
3636 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3637 - (1 << (16 - (start & 15) - size))));
3638 if (start < 16)
3639 return \"andis. %4,%1,%3\";
3640 else
3641 return \"andi. %4,%1,%3\";
3642 }
3644 if (start + size >= 32)
3645 operands[3] = const0_rtx;
3646 else
3647 operands[3] = GEN_INT (start + size);
3648 return \"rlwinm. %4,%1,%3,%s2,31\";
3649 }"
3650 [(set_attr "type" "delayed_compare")
3651 (set_attr "length" "4,8")])
3653 (define_split
3654 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3655 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3656 (match_operand:SI 2 "const_int_operand" "")
3657 (match_operand:SI 3 "const_int_operand" ""))
3658 (const_int 0)))
3659 (clobber (match_scratch:SI 4 ""))]
3660 "reload_completed"
3661 [(set (match_dup 4)
3662 (zero_extract:SI (match_dup 1) (match_dup 2)
3663 (match_dup 3)))
3664 (set (match_dup 0)
3665 (compare:CC (match_dup 4)
3666 (const_int 0)))]
3667 "")
3669 (define_insn "*extzvsi_internal2"
3670 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3671 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3672 (match_operand:SI 2 "const_int_operand" "i,i")
3673 (match_operand:SI 3 "const_int_operand" "i,i"))
3674 (const_int 0)))
3675 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3676 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3677 ""
3678 "*
3679 {
3680 int start = INTVAL (operands[3]) & 31;
3681 int size = INTVAL (operands[2]) & 31;
3683 /* Force split for non-cc0 compare. */
3684 if (which_alternative == 1)
3685 return \"#\";
3687 /* Since we are using the output value, we can't ignore any need for
3688 a shift. The bit-field must end at the LSB. */
3689 if (start >= 16 && start + size == 32)
3690 {
3691 operands[3] = GEN_INT ((1 << size) - 1);
3692 return \"andi. %0,%1,%3\";
3693 }
3695 if (start + size >= 32)
3696 operands[3] = const0_rtx;
3697 else
3698 operands[3] = GEN_INT (start + size);
3699 return \"rlwinm. %0,%1,%3,%s2,31\";
3700 }"
3701 [(set_attr "type" "delayed_compare")
3702 (set_attr "length" "4,8")])
3704 (define_split
3705 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3706 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3707 (match_operand:SI 2 "const_int_operand" "")
3708 (match_operand:SI 3 "const_int_operand" ""))
3709 (const_int 0)))
3710 (set (match_operand:SI 0 "gpc_reg_operand" "")
3711 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3712 "reload_completed"
3713 [(set (match_dup 0)
3714 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3715 (set (match_dup 4)
3716 (compare:CC (match_dup 0)
3717 (const_int 0)))]
3718 "")
3720 (define_insn "extzvdi_internal"
3721 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3722 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3723 (match_operand:SI 2 "const_int_operand" "i")
3724 (match_operand:SI 3 "const_int_operand" "i")))]
3725 "TARGET_POWERPC64"
3726 "*
3727 {
3728 int start = INTVAL (operands[3]) & 63;
3729 int size = INTVAL (operands[2]) & 63;
3731 if (start + size >= 64)
3732 operands[3] = const0_rtx;
3733 else
3734 operands[3] = GEN_INT (start + size);
3735 operands[2] = GEN_INT (64 - size);
3736 return \"rldicl %0,%1,%3,%2\";
3737 }")
3739 (define_insn "*extzvdi_internal1"
3740 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3741 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3742 (match_operand:SI 2 "const_int_operand" "i")
3743 (match_operand:SI 3 "const_int_operand" "i"))
3744 (const_int 0)))
3745 (clobber (match_scratch:DI 4 "=r"))]
3746 "TARGET_64BIT && rs6000_gen_cell_microcode"
3747 "*
3748 {
3749 int start = INTVAL (operands[3]) & 63;
3750 int size = INTVAL (operands[2]) & 63;
3752 if (start + size >= 64)
3753 operands[3] = const0_rtx;
3754 else
3755 operands[3] = GEN_INT (start + size);
3756 operands[2] = GEN_INT (64 - size);
3757 return \"rldicl. %4,%1,%3,%2\";
3758 }"
3759 [(set_attr "type" "compare")])
3761 (define_insn "*extzvdi_internal2"
3762 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3763 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3764 (match_operand:SI 2 "const_int_operand" "i")
3765 (match_operand:SI 3 "const_int_operand" "i"))
3766 (const_int 0)))
3767 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3768 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3769 "TARGET_64BIT && rs6000_gen_cell_microcode"
3770 "*
3771 {
3772 int start = INTVAL (operands[3]) & 63;
3773 int size = INTVAL (operands[2]) & 63;
3775 if (start + size >= 64)
3776 operands[3] = const0_rtx;
3777 else
3778 operands[3] = GEN_INT (start + size);
3779 operands[2] = GEN_INT (64 - size);
3780 return \"rldicl. %0,%1,%3,%2\";
3781 }"
3782 [(set_attr "type" "compare")])
3784 (define_insn "rotlsi3"
3785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3786 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3787 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3788 ""
3789 "@
3790 rlwnm %0,%1,%2,0xffffffff
3791 rlwinm %0,%1,%h2,0xffffffff"
3792 [(set_attr "type" "var_shift_rotate,integer")])
3794 (define_insn "*rotlsi3_64"
3795 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3796 (zero_extend:DI
3797 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3798 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3799 "TARGET_64BIT"
3800 "@
3801 rlwnm %0,%1,%2,0xffffffff
3802 rlwinm %0,%1,%h2,0xffffffff"
3803 [(set_attr "type" "var_shift_rotate,integer")])
3805 (define_insn "*rotlsi3_internal2"
3806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3807 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3808 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3809 (const_int 0)))
3810 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3811 ""
3812 "@
3813 rlwnm. %3,%1,%2,0xffffffff
3814 rlwinm. %3,%1,%h2,0xffffffff
3815 #
3816 #"
3817 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3818 (set_attr "length" "4,4,8,8")])
3820 (define_split
3821 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3822 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3823 (match_operand:SI 2 "reg_or_cint_operand" ""))
3824 (const_int 0)))
3825 (clobber (match_scratch:SI 3 ""))]
3826 "reload_completed"
3827 [(set (match_dup 3)
3828 (rotate:SI (match_dup 1) (match_dup 2)))
3829 (set (match_dup 0)
3830 (compare:CC (match_dup 3)
3831 (const_int 0)))]
3832 "")
3834 (define_insn "*rotlsi3_internal3"
3835 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3836 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3837 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3838 (const_int 0)))
3839 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3840 (rotate:SI (match_dup 1) (match_dup 2)))]
3841 ""
3842 "@
3843 rlwnm. %0,%1,%2,0xffffffff
3844 rlwinm. %0,%1,%h2,0xffffffff
3845 #
3846 #"
3847 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3848 (set_attr "length" "4,4,8,8")])
3850 (define_split
3851 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3852 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3853 (match_operand:SI 2 "reg_or_cint_operand" ""))
3854 (const_int 0)))
3855 (set (match_operand:SI 0 "gpc_reg_operand" "")
3856 (rotate:SI (match_dup 1) (match_dup 2)))]
3857 "reload_completed"
3858 [(set (match_dup 0)
3859 (rotate:SI (match_dup 1) (match_dup 2)))
3860 (set (match_dup 3)
3861 (compare:CC (match_dup 0)
3862 (const_int 0)))]
3863 "")
3865 (define_insn "*rotlsi3_internal4"
3866 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3867 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3868 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3869 (match_operand:SI 3 "mask_operand" "n,n")))]
3870 ""
3871 "@
3872 rlwnm %0,%1,%2,%m3,%M3
3873 rlwinm %0,%1,%h2,%m3,%M3"
3874 [(set_attr "type" "var_shift_rotate,integer")])
3876 (define_insn "*rotlsi3_internal5"
3877 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3878 (compare:CC (and:SI
3879 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3880 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3881 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3882 (const_int 0)))
3883 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3884 ""
3885 "@
3886 rlwnm. %4,%1,%2,%m3,%M3
3887 rlwinm. %4,%1,%h2,%m3,%M3
3888 #
3889 #"
3890 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3891 (set_attr "length" "4,4,8,8")])
3893 (define_split
3894 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3895 (compare:CC (and:SI
3896 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3897 (match_operand:SI 2 "reg_or_cint_operand" ""))
3898 (match_operand:SI 3 "mask_operand" ""))
3899 (const_int 0)))
3900 (clobber (match_scratch:SI 4 ""))]
3901 "reload_completed"
3902 [(set (match_dup 4)
3903 (and:SI (rotate:SI (match_dup 1)
3904 (match_dup 2))
3905 (match_dup 3)))
3906 (set (match_dup 0)
3907 (compare:CC (match_dup 4)
3908 (const_int 0)))]
3909 "")
3911 (define_insn "*rotlsi3_internal6"
3912 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3913 (compare:CC (and:SI
3914 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3915 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3916 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3917 (const_int 0)))
3918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3919 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3920 ""
3921 "@
3922 rlwnm. %0,%1,%2,%m3,%M3
3923 rlwinm. %0,%1,%h2,%m3,%M3
3924 #
3925 #"
3926 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3927 (set_attr "length" "4,4,8,8")])
3929 (define_split
3930 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3931 (compare:CC (and:SI
3932 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3933 (match_operand:SI 2 "reg_or_cint_operand" ""))
3934 (match_operand:SI 3 "mask_operand" ""))
3935 (const_int 0)))
3936 (set (match_operand:SI 0 "gpc_reg_operand" "")
3937 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3938 "reload_completed"
3939 [(set (match_dup 0)
3940 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3941 (set (match_dup 4)
3942 (compare:CC (match_dup 0)
3943 (const_int 0)))]
3944 "")
3946 (define_insn "*rotlsi3_internal7le"
3947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3948 (zero_extend:SI
3949 (subreg:QI
3950 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3951 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3952 "!BYTES_BIG_ENDIAN"
3953 "rlw%I2nm %0,%1,%h2,0xff"
3954 [(set (attr "cell_micro")
3955 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3956 (const_string "not")
3957 (const_string "always")))])
3959 (define_insn "*rotlsi3_internal7be"
3960 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3961 (zero_extend:SI
3962 (subreg:QI
3963 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3964 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3965 "BYTES_BIG_ENDIAN"
3966 "rlw%I2nm %0,%1,%h2,0xff"
3967 [(set (attr "cell_micro")
3968 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3969 (const_string "not")
3970 (const_string "always")))])
3972 (define_insn "*rotlsi3_internal8le"
3973 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3974 (compare:CC (zero_extend:SI
3975 (subreg:QI
3976 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3977 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3978 (const_int 0)))
3979 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3980 "!BYTES_BIG_ENDIAN"
3981 "@
3982 rlwnm. %3,%1,%2,0xff
3983 rlwinm. %3,%1,%h2,0xff
3984 #
3985 #"
3986 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3987 (set_attr "length" "4,4,8,8")])
3989 (define_insn "*rotlsi3_internal8be"
3990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3991 (compare:CC (zero_extend:SI
3992 (subreg:QI
3993 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3994 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
3995 (const_int 0)))
3996 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3997 "BYTES_BIG_ENDIAN"
3998 "@
3999 rlwnm. %3,%1,%2,0xff
4000 rlwinm. %3,%1,%h2,0xff
4001 #
4002 #"
4003 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4004 (set_attr "length" "4,4,8,8")])
4006 (define_split
4007 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4008 (compare:CC (zero_extend:SI
4009 (subreg:QI
4010 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4011 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4012 (const_int 0)))
4013 (clobber (match_scratch:SI 3 ""))]
4014 "!BYTES_BIG_ENDIAN && reload_completed"
4015 [(set (match_dup 3)
4016 (zero_extend:SI (subreg:QI
4017 (rotate:SI (match_dup 1)
4018 (match_dup 2)) 0)))
4019 (set (match_dup 0)
4020 (compare:CC (match_dup 3)
4021 (const_int 0)))]
4022 "")
4024 (define_split
4025 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4026 (compare:CC (zero_extend:SI
4027 (subreg:QI
4028 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4029 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4030 (const_int 0)))
4031 (clobber (match_scratch:SI 3 ""))]
4032 "BYTES_BIG_ENDIAN && reload_completed"
4033 [(set (match_dup 3)
4034 (zero_extend:SI (subreg:QI
4035 (rotate:SI (match_dup 1)
4036 (match_dup 2)) 3)))
4037 (set (match_dup 0)
4038 (compare:CC (match_dup 3)
4039 (const_int 0)))]
4040 "")
4042 (define_insn "*rotlsi3_internal9le"
4043 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4044 (compare:CC (zero_extend:SI
4045 (subreg:QI
4046 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4047 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4048 (const_int 0)))
4049 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4050 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4051 "!BYTES_BIG_ENDIAN"
4052 "@
4053 rlwnm. %0,%1,%2,0xff
4054 rlwinm. %0,%1,%h2,0xff
4055 #
4056 #"
4057 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4058 (set_attr "length" "4,4,8,8")])
4060 (define_insn "*rotlsi3_internal9be"
4061 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4062 (compare:CC (zero_extend:SI
4063 (subreg:QI
4064 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4065 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
4066 (const_int 0)))
4067 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4068 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4069 "BYTES_BIG_ENDIAN"
4070 "@
4071 rlwnm. %0,%1,%2,0xff
4072 rlwinm. %0,%1,%h2,0xff
4073 #
4074 #"
4075 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4076 (set_attr "length" "4,4,8,8")])
4078 (define_split
4079 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4080 (compare:CC (zero_extend:SI
4081 (subreg:QI
4082 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4083 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4084 (const_int 0)))
4085 (set (match_operand:SI 0 "gpc_reg_operand" "")
4086 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4087 "!BYTES_BIG_ENDIAN && reload_completed"
4088 [(set (match_dup 0)
4089 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4090 (set (match_dup 3)
4091 (compare:CC (match_dup 0)
4092 (const_int 0)))]
4093 "")
4095 (define_split
4096 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4097 (compare:CC (zero_extend:SI
4098 (subreg:QI
4099 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4100 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4101 (const_int 0)))
4102 (set (match_operand:SI 0 "gpc_reg_operand" "")
4103 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4104 "BYTES_BIG_ENDIAN && reload_completed"
4105 [(set (match_dup 0)
4106 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
4107 (set (match_dup 3)
4108 (compare:CC (match_dup 0)
4109 (const_int 0)))]
4110 "")
4112 (define_insn "*rotlsi3_internal10le"
4113 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4114 (zero_extend:SI
4115 (subreg:HI
4116 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4117 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4118 "!BYTES_BIG_ENDIAN"
4119 "@
4120 rlwnm %0,%1,%2,0xffff
4121 rlwinm %0,%1,%h2,0xffff"
4122 [(set_attr "type" "var_shift_rotate,integer")])
4124 (define_insn "*rotlsi3_internal10be"
4125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4126 (zero_extend:SI
4127 (subreg:HI
4128 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4129 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
4130 "BYTES_BIG_ENDIAN"
4131 "@
4132 rlwnm %0,%1,%2,0xffff
4133 rlwinm %0,%1,%h2,0xffff"
4134 [(set_attr "type" "var_shift_rotate,integer")])
4136 (define_insn "*rotlsi3_internal11le"
4137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4138 (compare:CC (zero_extend:SI
4139 (subreg:HI
4140 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4141 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4142 (const_int 0)))
4143 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4144 "!BYTES_BIG_ENDIAN"
4145 "@
4146 rlwnm. %3,%1,%2,0xffff
4147 rlwinm. %3,%1,%h2,0xffff
4148 #
4149 #"
4150 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4151 (set_attr "length" "4,4,8,8")])
4153 (define_insn "*rotlsi3_internal11be"
4154 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4155 (compare:CC (zero_extend:SI
4156 (subreg:HI
4157 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4158 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4159 (const_int 0)))
4160 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4161 "BYTES_BIG_ENDIAN"
4162 "@
4163 rlwnm. %3,%1,%2,0xffff
4164 rlwinm. %3,%1,%h2,0xffff
4165 #
4166 #"
4167 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4168 (set_attr "length" "4,4,8,8")])
4170 (define_split
4171 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4172 (compare:CC (zero_extend:SI
4173 (subreg:HI
4174 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4175 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4176 (const_int 0)))
4177 (clobber (match_scratch:SI 3 ""))]
4178 "!BYTES_BIG_ENDIAN && reload_completed"
4179 [(set (match_dup 3)
4180 (zero_extend:SI (subreg:HI
4181 (rotate:SI (match_dup 1)
4182 (match_dup 2)) 0)))
4183 (set (match_dup 0)
4184 (compare:CC (match_dup 3)
4185 (const_int 0)))]
4186 "")
4188 (define_split
4189 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4190 (compare:CC (zero_extend:SI
4191 (subreg:HI
4192 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4193 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4194 (const_int 0)))
4195 (clobber (match_scratch:SI 3 ""))]
4196 "BYTES_BIG_ENDIAN && reload_completed"
4197 [(set (match_dup 3)
4198 (zero_extend:SI (subreg:HI
4199 (rotate:SI (match_dup 1)
4200 (match_dup 2)) 2)))
4201 (set (match_dup 0)
4202 (compare:CC (match_dup 3)
4203 (const_int 0)))]
4204 "")
4206 (define_insn "*rotlsi3_internal12le"
4207 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4208 (compare:CC (zero_extend:SI
4209 (subreg:HI
4210 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4211 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4212 (const_int 0)))
4213 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4214 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4215 "!BYTES_BIG_ENDIAN"
4216 "@
4217 rlwnm. %0,%1,%2,0xffff
4218 rlwinm. %0,%1,%h2,0xffff
4219 #
4220 #"
4221 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4222 (set_attr "length" "4,4,8,8")])
4224 (define_insn "*rotlsi3_internal12be"
4225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4226 (compare:CC (zero_extend:SI
4227 (subreg:HI
4228 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4229 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4230 (const_int 0)))
4231 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4232 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4233 "BYTES_BIG_ENDIAN"
4234 "@
4235 rlwnm. %0,%1,%2,0xffff
4236 rlwinm. %0,%1,%h2,0xffff
4237 #
4238 #"
4239 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4240 (set_attr "length" "4,4,8,8")])
4242 (define_split
4243 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4244 (compare:CC (zero_extend:SI
4245 (subreg:HI
4246 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4247 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4248 (const_int 0)))
4249 (set (match_operand:SI 0 "gpc_reg_operand" "")
4250 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4251 "!BYTES_BIG_ENDIAN && reload_completed"
4252 [(set (match_dup 0)
4253 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4254 (set (match_dup 3)
4255 (compare:CC (match_dup 0)
4256 (const_int 0)))]
4257 "")
4259 (define_split
4260 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4261 (compare:CC (zero_extend:SI
4262 (subreg:HI
4263 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4264 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4265 (const_int 0)))
4266 (set (match_operand:SI 0 "gpc_reg_operand" "")
4267 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4268 "BYTES_BIG_ENDIAN && reload_completed"
4269 [(set (match_dup 0)
4270 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4271 (set (match_dup 3)
4272 (compare:CC (match_dup 0)
4273 (const_int 0)))]
4274 "")
4276 (define_insn "ashlsi3"
4277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4278 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4279 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4280 ""
4281 "@
4282 slw %0,%1,%2
4283 slwi %0,%1,%h2"
4284 [(set_attr "type" "var_shift_rotate,shift")])
4286 (define_insn "*ashlsi3_64"
4287 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4288 (zero_extend:DI
4289 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4290 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4291 "TARGET_POWERPC64"
4292 "@
4293 slw %0,%1,%2
4294 slwi %0,%1,%h2"
4295 [(set_attr "type" "var_shift_rotate,shift")])
4297 (define_insn ""
4298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4299 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4300 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4301 (const_int 0)))
4302 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4303 "TARGET_32BIT"
4304 "@
4305 slw. %3,%1,%2
4306 slwi. %3,%1,%h2
4307 #
4308 #"
4309 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4310 (set_attr "length" "4,4,8,8")])
4312 (define_split
4313 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4314 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4315 (match_operand:SI 2 "reg_or_cint_operand" ""))
4316 (const_int 0)))
4317 (clobber (match_scratch:SI 3 ""))]
4318 "TARGET_32BIT && reload_completed"
4319 [(set (match_dup 3)
4320 (ashift:SI (match_dup 1) (match_dup 2)))
4321 (set (match_dup 0)
4322 (compare:CC (match_dup 3)
4323 (const_int 0)))]
4324 "")
4326 (define_insn ""
4327 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4328 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4329 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4330 (const_int 0)))
4331 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4332 (ashift:SI (match_dup 1) (match_dup 2)))]
4333 "TARGET_32BIT"
4334 "@
4335 slw. %0,%1,%2
4336 slwi. %0,%1,%h2
4337 #
4338 #"
4339 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4340 (set_attr "length" "4,4,8,8")])
4342 (define_split
4343 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4344 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4345 (match_operand:SI 2 "reg_or_cint_operand" ""))
4346 (const_int 0)))
4347 (set (match_operand:SI 0 "gpc_reg_operand" "")
4348 (ashift:SI (match_dup 1) (match_dup 2)))]
4349 "TARGET_32BIT && reload_completed"
4350 [(set (match_dup 0)
4351 (ashift:SI (match_dup 1) (match_dup 2)))
4352 (set (match_dup 3)
4353 (compare:CC (match_dup 0)
4354 (const_int 0)))]
4355 "")
4357 (define_insn "rlwinm"
4358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4359 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4360 (match_operand:SI 2 "const_int_operand" "i"))
4361 (match_operand:SI 3 "mask_operand" "n")))]
4362 "includes_lshift_p (operands[2], operands[3])"
4363 "rlwinm %0,%1,%h2,%m3,%M3")
4365 (define_insn ""
4366 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4367 (compare:CC
4368 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4369 (match_operand:SI 2 "const_int_operand" "i,i"))
4370 (match_operand:SI 3 "mask_operand" "n,n"))
4371 (const_int 0)))
4372 (clobber (match_scratch:SI 4 "=r,r"))]
4373 "includes_lshift_p (operands[2], operands[3])"
4374 "@
4375 rlwinm. %4,%1,%h2,%m3,%M3
4376 #"
4377 [(set_attr "type" "delayed_compare")
4378 (set_attr "length" "4,8")])
4380 (define_split
4381 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4382 (compare:CC
4383 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4384 (match_operand:SI 2 "const_int_operand" ""))
4385 (match_operand:SI 3 "mask_operand" ""))
4386 (const_int 0)))
4387 (clobber (match_scratch:SI 4 ""))]
4388 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4389 [(set (match_dup 4)
4390 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4391 (match_dup 3)))
4392 (set (match_dup 0)
4393 (compare:CC (match_dup 4)
4394 (const_int 0)))]
4395 "")
4397 (define_insn ""
4398 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4399 (compare:CC
4400 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4401 (match_operand:SI 2 "const_int_operand" "i,i"))
4402 (match_operand:SI 3 "mask_operand" "n,n"))
4403 (const_int 0)))
4404 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4405 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4406 "includes_lshift_p (operands[2], operands[3])"
4407 "@
4408 rlwinm. %0,%1,%h2,%m3,%M3
4409 #"
4410 [(set_attr "type" "delayed_compare")
4411 (set_attr "length" "4,8")])
4413 (define_split
4414 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4415 (compare:CC
4416 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4417 (match_operand:SI 2 "const_int_operand" ""))
4418 (match_operand:SI 3 "mask_operand" ""))
4419 (const_int 0)))
4420 (set (match_operand:SI 0 "gpc_reg_operand" "")
4421 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4422 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4423 [(set (match_dup 0)
4424 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4425 (set (match_dup 4)
4426 (compare:CC (match_dup 0)
4427 (const_int 0)))]
4428 "")
4430 (define_insn "lshrsi3"
4431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4432 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4433 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4434 ""
4435 "@
4436 mr %0,%1
4437 srw %0,%1,%2
4438 srwi %0,%1,%h2"
4439 [(set_attr "type" "integer,var_shift_rotate,shift")])
4441 (define_insn "*lshrsi3_64"
4442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4443 (zero_extend:DI
4444 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4445 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4446 "TARGET_POWERPC64"
4447 "@
4448 srw %0,%1,%2
4449 srwi %0,%1,%h2"
4450 [(set_attr "type" "var_shift_rotate,shift")])
4452 (define_insn ""
4453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4454 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4455 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4456 (const_int 0)))
4457 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4458 "TARGET_32BIT"
4459 "@
4460 mr. %1,%1
4461 srw. %3,%1,%2
4462 srwi. %3,%1,%h2
4463 #
4464 #
4465 #"
4466 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4467 (set_attr "length" "4,4,4,8,8,8")])
4469 (define_split
4470 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4471 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4472 (match_operand:SI 2 "reg_or_cint_operand" ""))
4473 (const_int 0)))
4474 (clobber (match_scratch:SI 3 ""))]
4475 "TARGET_32BIT && reload_completed"
4476 [(set (match_dup 3)
4477 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4478 (set (match_dup 0)
4479 (compare:CC (match_dup 3)
4480 (const_int 0)))]
4481 "")
4483 (define_insn ""
4484 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4485 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4486 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4487 (const_int 0)))
4488 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4489 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4490 "TARGET_32BIT"
4491 "@
4492 mr. %0,%1
4493 srw. %0,%1,%2
4494 srwi. %0,%1,%h2
4495 #
4496 #
4497 #"
4498 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4499 (set_attr "length" "4,4,4,8,8,8")])
4501 (define_split
4502 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4503 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4504 (match_operand:SI 2 "reg_or_cint_operand" ""))
4505 (const_int 0)))
4506 (set (match_operand:SI 0 "gpc_reg_operand" "")
4507 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4508 "TARGET_32BIT && reload_completed"
4509 [(set (match_dup 0)
4510 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4511 (set (match_dup 3)
4512 (compare:CC (match_dup 0)
4513 (const_int 0)))]
4514 "")
4516 (define_insn ""
4517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4518 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4519 (match_operand:SI 2 "const_int_operand" "i"))
4520 (match_operand:SI 3 "mask_operand" "n")))]
4521 "includes_rshift_p (operands[2], operands[3])"
4522 "rlwinm %0,%1,%s2,%m3,%M3")
4524 (define_insn ""
4525 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4526 (compare:CC
4527 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4528 (match_operand:SI 2 "const_int_operand" "i,i"))
4529 (match_operand:SI 3 "mask_operand" "n,n"))
4530 (const_int 0)))
4531 (clobber (match_scratch:SI 4 "=r,r"))]
4532 "includes_rshift_p (operands[2], operands[3])"
4533 "@
4534 rlwinm. %4,%1,%s2,%m3,%M3
4535 #"
4536 [(set_attr "type" "delayed_compare")
4537 (set_attr "length" "4,8")])
4539 (define_split
4540 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4541 (compare:CC
4542 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4543 (match_operand:SI 2 "const_int_operand" ""))
4544 (match_operand:SI 3 "mask_operand" ""))
4545 (const_int 0)))
4546 (clobber (match_scratch:SI 4 ""))]
4547 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4548 [(set (match_dup 4)
4549 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4550 (match_dup 3)))
4551 (set (match_dup 0)
4552 (compare:CC (match_dup 4)
4553 (const_int 0)))]
4554 "")
4556 (define_insn ""
4557 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4558 (compare:CC
4559 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4560 (match_operand:SI 2 "const_int_operand" "i,i"))
4561 (match_operand:SI 3 "mask_operand" "n,n"))
4562 (const_int 0)))
4563 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4564 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4565 "includes_rshift_p (operands[2], operands[3])"
4566 "@
4567 rlwinm. %0,%1,%s2,%m3,%M3
4568 #"
4569 [(set_attr "type" "delayed_compare")
4570 (set_attr "length" "4,8")])
4572 (define_split
4573 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4574 (compare:CC
4575 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4576 (match_operand:SI 2 "const_int_operand" ""))
4577 (match_operand:SI 3 "mask_operand" ""))
4578 (const_int 0)))
4579 (set (match_operand:SI 0 "gpc_reg_operand" "")
4580 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4581 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4582 [(set (match_dup 0)
4583 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4584 (set (match_dup 4)
4585 (compare:CC (match_dup 0)
4586 (const_int 0)))]
4587 "")
4589 (define_insn "*lshiftrt_internal1le"
4590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4591 (zero_extend:SI
4592 (subreg:QI
4593 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4594 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4595 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4596 "rlwinm %0,%1,%s2,0xff")
4598 (define_insn "*lshiftrt_internal1be"
4599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4600 (zero_extend:SI
4601 (subreg:QI
4602 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4603 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4604 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4605 "rlwinm %0,%1,%s2,0xff")
4607 (define_insn "*lshiftrt_internal2le"
4608 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4609 (compare:CC
4610 (zero_extend:SI
4611 (subreg:QI
4612 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4613 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4614 (const_int 0)))
4615 (clobber (match_scratch:SI 3 "=r,r"))]
4616 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4617 "@
4618 rlwinm. %3,%1,%s2,0xff
4619 #"
4620 [(set_attr "type" "delayed_compare")
4621 (set_attr "length" "4,8")])
4623 (define_insn "*lshiftrt_internal2be"
4624 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4625 (compare:CC
4626 (zero_extend:SI
4627 (subreg:QI
4628 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4629 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4630 (const_int 0)))
4631 (clobber (match_scratch:SI 3 "=r,r"))]
4632 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4633 "@
4634 rlwinm. %3,%1,%s2,0xff
4635 #"
4636 [(set_attr "type" "delayed_compare")
4637 (set_attr "length" "4,8")])
4639 (define_split
4640 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4641 (compare:CC
4642 (zero_extend:SI
4643 (subreg:QI
4644 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4645 (match_operand:SI 2 "const_int_operand" "")) 0))
4646 (const_int 0)))
4647 (clobber (match_scratch:SI 3 ""))]
4648 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4649 [(set (match_dup 3)
4650 (zero_extend:SI (subreg:QI
4651 (lshiftrt:SI (match_dup 1)
4652 (match_dup 2)) 0)))
4653 (set (match_dup 0)
4654 (compare:CC (match_dup 3)
4655 (const_int 0)))]
4656 "")
4658 (define_split
4659 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4660 (compare:CC
4661 (zero_extend:SI
4662 (subreg:QI
4663 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4664 (match_operand:SI 2 "const_int_operand" "")) 3))
4665 (const_int 0)))
4666 (clobber (match_scratch:SI 3 ""))]
4667 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4668 [(set (match_dup 3)
4669 (zero_extend:SI (subreg:QI
4670 (lshiftrt:SI (match_dup 1)
4671 (match_dup 2)) 3)))
4672 (set (match_dup 0)
4673 (compare:CC (match_dup 3)
4674 (const_int 0)))]
4675 "")
4677 (define_insn "*lshiftrt_internal3le"
4678 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4679 (compare:CC
4680 (zero_extend:SI
4681 (subreg:QI
4682 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4683 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4684 (const_int 0)))
4685 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4686 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4687 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4688 "@
4689 rlwinm. %0,%1,%s2,0xff
4690 #"
4691 [(set_attr "type" "delayed_compare")
4692 (set_attr "length" "4,8")])
4694 (define_insn "*lshiftrt_internal3be"
4695 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4696 (compare:CC
4697 (zero_extend:SI
4698 (subreg:QI
4699 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4700 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4701 (const_int 0)))
4702 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4703 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4704 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4705 "@
4706 rlwinm. %0,%1,%s2,0xff
4707 #"
4708 [(set_attr "type" "delayed_compare")
4709 (set_attr "length" "4,8")])
4711 (define_split
4712 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4713 (compare:CC
4714 (zero_extend:SI
4715 (subreg:QI
4716 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4717 (match_operand:SI 2 "const_int_operand" "")) 0))
4718 (const_int 0)))
4719 (set (match_operand:SI 0 "gpc_reg_operand" "")
4720 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4721 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4722 [(set (match_dup 0)
4723 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4724 (set (match_dup 3)
4725 (compare:CC (match_dup 0)
4726 (const_int 0)))]
4727 "")
4729 (define_split
4730 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4731 (compare:CC
4732 (zero_extend:SI
4733 (subreg:QI
4734 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4735 (match_operand:SI 2 "const_int_operand" "")) 3))
4736 (const_int 0)))
4737 (set (match_operand:SI 0 "gpc_reg_operand" "")
4738 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4739 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4740 [(set (match_dup 0)
4741 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4742 (set (match_dup 3)
4743 (compare:CC (match_dup 0)
4744 (const_int 0)))]
4745 "")
4747 (define_insn "*lshiftrt_internal4le"
4748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4749 (zero_extend:SI
4750 (subreg:HI
4751 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4752 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4753 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4754 "rlwinm %0,%1,%s2,0xffff")
4756 (define_insn "*lshiftrt_internal4be"
4757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4758 (zero_extend:SI
4759 (subreg:HI
4760 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4761 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4762 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4763 "rlwinm %0,%1,%s2,0xffff")
4765 (define_insn "*lshiftrt_internal5le"
4766 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4767 (compare:CC
4768 (zero_extend:SI
4769 (subreg:HI
4770 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4771 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4772 (const_int 0)))
4773 (clobber (match_scratch:SI 3 "=r,r"))]
4774 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4775 "@
4776 rlwinm. %3,%1,%s2,0xffff
4777 #"
4778 [(set_attr "type" "delayed_compare")
4779 (set_attr "length" "4,8")])
4781 (define_insn "*lshiftrt_internal5be"
4782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4783 (compare:CC
4784 (zero_extend:SI
4785 (subreg:HI
4786 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4787 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4788 (const_int 0)))
4789 (clobber (match_scratch:SI 3 "=r,r"))]
4790 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4791 "@
4792 rlwinm. %3,%1,%s2,0xffff
4793 #"
4794 [(set_attr "type" "delayed_compare")
4795 (set_attr "length" "4,8")])
4797 (define_split
4798 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4799 (compare:CC
4800 (zero_extend:SI
4801 (subreg:HI
4802 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4803 (match_operand:SI 2 "const_int_operand" "")) 0))
4804 (const_int 0)))
4805 (clobber (match_scratch:SI 3 ""))]
4806 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4807 [(set (match_dup 3)
4808 (zero_extend:SI (subreg:HI
4809 (lshiftrt:SI (match_dup 1)
4810 (match_dup 2)) 0)))
4811 (set (match_dup 0)
4812 (compare:CC (match_dup 3)
4813 (const_int 0)))]
4814 "")
4816 (define_split
4817 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4818 (compare:CC
4819 (zero_extend:SI
4820 (subreg:HI
4821 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4822 (match_operand:SI 2 "const_int_operand" "")) 2))
4823 (const_int 0)))
4824 (clobber (match_scratch:SI 3 ""))]
4825 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4826 [(set (match_dup 3)
4827 (zero_extend:SI (subreg:HI
4828 (lshiftrt:SI (match_dup 1)
4829 (match_dup 2)) 2)))
4830 (set (match_dup 0)
4831 (compare:CC (match_dup 3)
4832 (const_int 0)))]
4833 "")
4835 (define_insn "*lshiftrt_internal5le"
4836 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4837 (compare:CC
4838 (zero_extend:SI
4839 (subreg:HI
4840 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4841 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4842 (const_int 0)))
4843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4844 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4845 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4846 "@
4847 rlwinm. %0,%1,%s2,0xffff
4848 #"
4849 [(set_attr "type" "delayed_compare")
4850 (set_attr "length" "4,8")])
4852 (define_insn "*lshiftrt_internal5be"
4853 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4854 (compare:CC
4855 (zero_extend:SI
4856 (subreg:HI
4857 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4858 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4859 (const_int 0)))
4860 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4861 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4862 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4863 "@
4864 rlwinm. %0,%1,%s2,0xffff
4865 #"
4866 [(set_attr "type" "delayed_compare")
4867 (set_attr "length" "4,8")])
4869 (define_split
4870 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4871 (compare:CC
4872 (zero_extend:SI
4873 (subreg:HI
4874 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4875 (match_operand:SI 2 "const_int_operand" "")) 0))
4876 (const_int 0)))
4877 (set (match_operand:SI 0 "gpc_reg_operand" "")
4878 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4879 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4880 [(set (match_dup 0)
4881 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4882 (set (match_dup 3)
4883 (compare:CC (match_dup 0)
4884 (const_int 0)))]
4885 "")
4887 (define_split
4888 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4889 (compare:CC
4890 (zero_extend:SI
4891 (subreg:HI
4892 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4893 (match_operand:SI 2 "const_int_operand" "")) 2))
4894 (const_int 0)))
4895 (set (match_operand:SI 0 "gpc_reg_operand" "")
4896 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4897 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4898 [(set (match_dup 0)
4899 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4900 (set (match_dup 3)
4901 (compare:CC (match_dup 0)
4902 (const_int 0)))]
4903 "")
4905 (define_insn "ashrsi3"
4906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4907 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4908 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4909 ""
4910 "@
4911 sraw %0,%1,%2
4912 srawi %0,%1,%h2"
4913 [(set_attr "type" "var_shift_rotate,shift")])
4915 (define_insn "*ashrsi3_64"
4916 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4917 (sign_extend:DI
4918 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4919 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4920 "TARGET_POWERPC64"
4921 "@
4922 sraw %0,%1,%2
4923 srawi %0,%1,%h2"
4924 [(set_attr "type" "var_shift_rotate,shift")])
4926 (define_insn ""
4927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4928 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4929 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4930 (const_int 0)))
4931 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4932 ""
4933 "@
4934 sraw. %3,%1,%2
4935 srawi. %3,%1,%h2
4936 #
4937 #"
4938 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4939 (set_attr "length" "4,4,8,8")])
4941 (define_split
4942 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4943 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4944 (match_operand:SI 2 "reg_or_cint_operand" ""))
4945 (const_int 0)))
4946 (clobber (match_scratch:SI 3 ""))]
4947 "reload_completed"
4948 [(set (match_dup 3)
4949 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4950 (set (match_dup 0)
4951 (compare:CC (match_dup 3)
4952 (const_int 0)))]
4953 "")
4955 (define_insn ""
4956 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4957 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4958 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4959 (const_int 0)))
4960 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4961 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4962 ""
4963 "@
4964 sraw. %0,%1,%2
4965 srawi. %0,%1,%h2
4966 #
4967 #"
4968 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4969 (set_attr "length" "4,4,8,8")])
4970 \f
4971 ;; Builtins to replace a division to generate FRE reciprocal estimate
4972 ;; instructions and the necessary fixup instructions
4973 (define_expand "recip<mode>3"
4974 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4975 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4976 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4977 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4978 {
4979 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4980 DONE;
4981 })
4983 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4984 ;; hardware division. This is only done before register allocation and with
4985 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4986 (define_split
4987 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4988 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4989 (match_operand 2 "gpc_reg_operand" "")))]
4990 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4991 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4992 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4993 [(const_int 0)]
4994 {
4995 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4996 DONE;
4997 })
4999 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5000 ;; appropriate fixup.
5001 (define_expand "rsqrt<mode>2"
5002 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5003 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5004 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5005 {
5006 rs6000_emit_swrsqrt (operands[0], operands[1]);
5007 DONE;
5008 })
5009 \f
5010 (define_split
5011 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5012 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5013 (match_operand:SI 2 "reg_or_cint_operand" ""))
5014 (const_int 0)))
5015 (set (match_operand:SI 0 "gpc_reg_operand" "")
5016 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5017 "reload_completed"
5018 [(set (match_dup 0)
5019 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5020 (set (match_dup 3)
5021 (compare:CC (match_dup 0)
5022 (const_int 0)))]
5023 "")
5025 \f
5026 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
5027 ;; modes here, and also add in conditional vsx/power8-vector support to access
5028 ;; values in the traditional Altivec registers if the appropriate
5029 ;; -mupper-regs-{df,sf} option is enabled.
5031 (define_expand "abs<mode>2"
5032 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5033 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5034 "TARGET_<MODE>_INSN"
5035 "")
5037 (define_insn "*abs<mode>2_fpr"
5038 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5039 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5040 "TARGET_<MODE>_FPR"
5041 "@
5042 fabs %0,%1
5043 xsabsdp %x0,%x1"
5044 [(set_attr "type" "fp")
5045 (set_attr "fp_type" "fp_addsub_<Fs>")])
5047 (define_insn "*nabs<mode>2_fpr"
5048 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5049 (neg:SFDF
5050 (abs:SFDF
5051 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
5052 "TARGET_<MODE>_FPR"
5053 "@
5054 fnabs %0,%1
5055 xsnabsdp %x0,%x1"
5056 [(set_attr "type" "fp")
5057 (set_attr "fp_type" "fp_addsub_<Fs>")])
5059 (define_expand "neg<mode>2"
5060 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5061 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5062 "TARGET_<MODE>_INSN"
5063 "")
5065 (define_insn "*neg<mode>2_fpr"
5066 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5067 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5068 "TARGET_<MODE>_FPR"
5069 "@
5070 fneg %0,%1
5071 xsnegdp %x0,%x1"
5072 [(set_attr "type" "fp")
5073 (set_attr "fp_type" "fp_addsub_<Fs>")])
5075 (define_expand "add<mode>3"
5076 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5077 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5078 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5079 "TARGET_<MODE>_INSN"
5080 "")
5082 (define_insn "*add<mode>3_fpr"
5083 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5084 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5085 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5086 "TARGET_<MODE>_FPR"
5087 "@
5088 fadd<Ftrad> %0,%1,%2
5089 xsadd<Fvsx> %x0,%x1,%x2"
5090 [(set_attr "type" "fp")
5091 (set_attr "fp_type" "fp_addsub_<Fs>")])
5093 (define_expand "sub<mode>3"
5094 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5095 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5096 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5097 "TARGET_<MODE>_INSN"
5098 "")
5100 (define_insn "*sub<mode>3_fpr"
5101 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5102 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5103 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5104 "TARGET_<MODE>_FPR"
5105 "@
5106 fsub<Ftrad> %0,%1,%2
5107 xssub<Fvsx> %x0,%x1,%x2"
5108 [(set_attr "type" "fp")
5109 (set_attr "fp_type" "fp_addsub_<Fs>")])
5111 (define_expand "mul<mode>3"
5112 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5113 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5114 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5115 "TARGET_<MODE>_INSN"
5116 "")
5118 (define_insn "*mul<mode>3_fpr"
5119 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5120 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5121 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5122 "TARGET_<MODE>_FPR"
5123 "@
5124 fmul<Ftrad> %0,%1,%2
5125 xsmul<Fvsx> %x0,%x1,%x2"
5126 [(set_attr "type" "dmul")
5127 (set_attr "fp_type" "fp_mul_<Fs>")])
5129 (define_expand "div<mode>3"
5130 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5131 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5132 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5133 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
5134 "")
5136 (define_insn "*div<mode>3_fpr"
5137 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5138 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5139 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5140 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
5141 "@
5142 fdiv<Ftrad> %0,%1,%2
5143 xsdiv<Fvsx> %x0,%x1,%x2"
5144 [(set_attr "type" "<Fs>div")
5145 (set_attr "fp_type" "fp_div_<Fs>")])
5147 (define_insn "sqrt<mode>2"
5148 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5149 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5150 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
5151 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
5152 "@
5153 fsqrt<Ftrad> %0,%1
5154 xssqrt<Fvsx> %x0,%x1"
5155 [(set_attr "type" "<Fs>sqrt")
5156 (set_attr "fp_type" "fp_sqrt_<Fs>")])
5158 ;; Floating point reciprocal approximation
5159 (define_insn "fre<Fs>"
5160 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5161 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5162 UNSPEC_FRES))]
5163 "TARGET_<FFRE>"
5164 "@
5165 fre<Ftrad> %0,%1
5166 xsre<Fvsx> %x0,%x1"
5167 [(set_attr "type" "fp")])
5169 (define_insn "*rsqrt<mode>2"
5170 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5171 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5172 UNSPEC_RSQRT))]
5173 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5174 "@
5175 frsqrte<Ftrad> %0,%1
5176 xsrsqrte<Fvsx> %x0,%x1"
5177 [(set_attr "type" "fp")])
5179 ;; Floating point comparisons
5180 (define_insn "*cmp<mode>_fpr"
5181 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
5182 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5183 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5184 "TARGET_<MODE>_FPR"
5185 "@
5186 fcmpu %0,%1,%2
5187 xscmpudp %0,%x1,%x2"
5188 [(set_attr "type" "fpcompare")])
5190 ;; Floating point conversions
5191 (define_expand "extendsfdf2"
5192 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5193 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5194 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5195 "")
5197 (define_insn_and_split "*extendsfdf2_fpr"
5198 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
5199 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
5200 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5201 "@
5202 #
5203 fmr %0,%1
5204 lfs%U1%X1 %0,%1
5205 #
5206 xxlor %x0,%x1,%x1
5207 lxsspx %x0,%y1"
5208 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5209 [(const_int 0)]
5210 {
5211 emit_note (NOTE_INSN_DELETED);
5212 DONE;
5213 }
5214 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
5216 (define_expand "truncdfsf2"
5217 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5218 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5219 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5220 "")
5222 (define_insn "*truncdfsf2_fpr"
5223 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5224 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5225 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5226 "frsp %0,%1"
5227 [(set_attr "type" "fp")])
5229 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5230 ;; builtins.c and optabs.c that are not correct for IBM long double
5231 ;; when little-endian.
5232 (define_expand "signbittf2"
5233 [(set (match_dup 2)
5234 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5235 (set (match_dup 3)
5236 (subreg:DI (match_dup 2) 0))
5237 (set (match_dup 4)
5238 (match_dup 5))
5239 (set (match_operand:SI 0 "gpc_reg_operand" "")
5240 (match_dup 6))]
5241 "!TARGET_IEEEQUAD
5242 && TARGET_HARD_FLOAT
5243 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5244 && TARGET_LONG_DOUBLE_128"
5245 {
5246 operands[2] = gen_reg_rtx (DFmode);
5247 operands[3] = gen_reg_rtx (DImode);
5248 if (TARGET_POWERPC64)
5249 {
5250 operands[4] = gen_reg_rtx (DImode);
5251 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5252 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5253 WORDS_BIG_ENDIAN ? 4 : 0);
5254 }
5255 else
5256 {
5257 operands[4] = gen_reg_rtx (SImode);
5258 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5259 WORDS_BIG_ENDIAN ? 0 : 4);
5260 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5261 }
5262 })
5264 (define_expand "copysign<mode>3"
5265 [(set (match_dup 3)
5266 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5267 (set (match_dup 4)
5268 (neg:SFDF (abs:SFDF (match_dup 1))))
5269 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5270 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5271 (match_dup 5))
5272 (match_dup 3)
5273 (match_dup 4)))]
5274 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5275 && ((TARGET_PPC_GFXOPT
5276 && !HONOR_NANS (<MODE>mode)
5277 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5278 || TARGET_CMPB
5279 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5280 {
5281 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5282 {
5283 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5284 operands[2]));
5285 DONE;
5286 }
5288 operands[3] = gen_reg_rtx (<MODE>mode);
5289 operands[4] = gen_reg_rtx (<MODE>mode);
5290 operands[5] = CONST0_RTX (<MODE>mode);
5291 })
5293 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5294 ;; compiler from optimizing -0.0
5295 (define_insn "copysign<mode>3_fcpsgn"
5296 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5297 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5298 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5299 UNSPEC_COPYSIGN))]
5300 "TARGET_<MODE>_FPR && TARGET_CMPB"
5301 "@
5302 fcpsgn %0,%2,%1
5303 xscpsgn<Fvsx> %x0,%x2,%x1"
5304 [(set_attr "type" "fp")])
5306 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5307 ;; fsel instruction and some auxiliary computations. Then we just have a
5308 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5309 ;; combine.
5310 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5311 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5312 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5313 ;; define_splits to make them if made by combine. On VSX machines we have the
5314 ;; min/max instructions.
5315 ;;
5316 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5317 ;; to allow either DF/SF to use only traditional registers.
5319 (define_expand "smax<mode>3"
5320 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5321 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5322 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5323 (match_dup 1)
5324 (match_dup 2)))]
5325 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5326 {
5327 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5328 DONE;
5329 })
5331 (define_insn "*smax<mode>3_vsx"
5332 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5333 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5334 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5335 "TARGET_<MODE>_FPR && TARGET_VSX"
5336 "xsmaxdp %x0,%x1,%x2"
5337 [(set_attr "type" "fp")])
5339 (define_expand "smin<mode>3"
5340 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5341 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5342 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5343 (match_dup 2)
5344 (match_dup 1)))]
5345 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5346 {
5347 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5348 DONE;
5349 })
5351 (define_insn "*smin<mode>3_vsx"
5352 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5353 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5354 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5355 "TARGET_<MODE>_FPR && TARGET_VSX"
5356 "xsmindp %x0,%x1,%x2"
5357 [(set_attr "type" "fp")])
5359 (define_split
5360 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5361 (match_operator:SFDF 3 "min_max_operator"
5362 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5363 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5364 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5365 && !TARGET_VSX"
5366 [(const_int 0)]
5367 {
5368 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5369 operands[2]);
5370 DONE;
5371 })
5373 (define_split
5374 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5375 (match_operator:SF 3 "min_max_operator"
5376 [(match_operand:SF 1 "gpc_reg_operand" "")
5377 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5378 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5379 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5380 [(const_int 0)]
5381 "
5382 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5383 operands[1], operands[2]);
5384 DONE;
5385 }")
5387 (define_expand "mov<mode>cc"
5388 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5389 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5390 (match_operand:GPR 2 "gpc_reg_operand" "")
5391 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5392 "TARGET_ISEL<sel>"
5393 "
5394 {
5395 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5396 DONE;
5397 else
5398 FAIL;
5399 }")
5401 ;; We use the BASE_REGS for the isel input operands because, if rA is
5402 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5403 ;; because we may switch the operands and rB may end up being rA.
5404 ;;
5405 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5406 ;; leave out the mode in operand 4 and use one pattern, but reload can
5407 ;; change the mode underneath our feet and then gets confused trying
5408 ;; to reload the value.
5409 (define_insn "isel_signed_<mode>"
5410 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5411 (if_then_else:GPR
5412 (match_operator 1 "scc_comparison_operator"
5413 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5414 (const_int 0)])
5415 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5416 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5417 "TARGET_ISEL<sel>"
5418 "*
5419 { return output_isel (operands); }"
5420 [(set_attr "type" "isel")
5421 (set_attr "length" "4")])
5423 (define_insn "isel_unsigned_<mode>"
5424 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5425 (if_then_else:GPR
5426 (match_operator 1 "scc_comparison_operator"
5427 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5428 (const_int 0)])
5429 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5430 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5431 "TARGET_ISEL<sel>"
5432 "*
5433 { return output_isel (operands); }"
5434 [(set_attr "type" "isel")
5435 (set_attr "length" "4")])
5437 ;; These patterns can be useful for combine; they let combine know that
5438 ;; isel can handle reversed comparisons so long as the operands are
5439 ;; registers.
5441 (define_insn "*isel_reversed_signed_<mode>"
5442 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5443 (if_then_else:GPR
5444 (match_operator 1 "scc_rev_comparison_operator"
5445 [(match_operand:CC 4 "cc_reg_operand" "y")
5446 (const_int 0)])
5447 (match_operand:GPR 2 "gpc_reg_operand" "b")
5448 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5449 "TARGET_ISEL<sel>"
5450 "*
5451 { return output_isel (operands); }"
5452 [(set_attr "type" "isel")
5453 (set_attr "length" "4")])
5455 (define_insn "*isel_reversed_unsigned_<mode>"
5456 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5457 (if_then_else:GPR
5458 (match_operator 1 "scc_rev_comparison_operator"
5459 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5460 (const_int 0)])
5461 (match_operand:GPR 2 "gpc_reg_operand" "b")
5462 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5463 "TARGET_ISEL<sel>"
5464 "*
5465 { return output_isel (operands); }"
5466 [(set_attr "type" "isel")
5467 (set_attr "length" "4")])
5469 (define_expand "movsfcc"
5470 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5471 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5472 (match_operand:SF 2 "gpc_reg_operand" "")
5473 (match_operand:SF 3 "gpc_reg_operand" "")))]
5474 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5475 "
5476 {
5477 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5478 DONE;
5479 else
5480 FAIL;
5481 }")
5483 (define_insn "*fselsfsf4"
5484 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5485 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5486 (match_operand:SF 4 "zero_fp_constant" "F"))
5487 (match_operand:SF 2 "gpc_reg_operand" "f")
5488 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5489 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5490 "fsel %0,%1,%2,%3"
5491 [(set_attr "type" "fp")])
5493 (define_insn "*fseldfsf4"
5494 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5495 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5496 (match_operand:DF 4 "zero_fp_constant" "F"))
5497 (match_operand:SF 2 "gpc_reg_operand" "f")
5498 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5499 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5500 "fsel %0,%1,%2,%3"
5501 [(set_attr "type" "fp")])
5503 ;; The conditional move instructions allow us to perform max and min
5504 ;; operations even when
5506 (define_split
5507 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5508 (match_operator:DF 3 "min_max_operator"
5509 [(match_operand:DF 1 "gpc_reg_operand" "")
5510 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5511 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5512 && !flag_trapping_math"
5513 [(const_int 0)]
5514 "
5515 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5516 operands[1], operands[2]);
5517 DONE;
5518 }")
5520 (define_expand "movdfcc"
5521 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5522 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5523 (match_operand:DF 2 "gpc_reg_operand" "")
5524 (match_operand:DF 3 "gpc_reg_operand" "")))]
5525 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5526 "
5527 {
5528 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5529 DONE;
5530 else
5531 FAIL;
5532 }")
5534 (define_insn "*fseldfdf4"
5535 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5536 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5537 (match_operand:DF 4 "zero_fp_constant" "F"))
5538 (match_operand:DF 2 "gpc_reg_operand" "d")
5539 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5540 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5541 "fsel %0,%1,%2,%3"
5542 [(set_attr "type" "fp")])
5544 (define_insn "*fselsfdf4"
5545 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5546 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5547 (match_operand:SF 4 "zero_fp_constant" "F"))
5548 (match_operand:DF 2 "gpc_reg_operand" "d")
5549 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5550 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5551 "fsel %0,%1,%2,%3"
5552 [(set_attr "type" "fp")])
5553 \f
5554 ;; Conversions to and from floating-point.
5556 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5557 ; don't want to support putting SImode in FPR registers.
5558 (define_insn "lfiwax"
5559 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5560 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5561 UNSPEC_LFIWAX))]
5562 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5563 "@
5564 lfiwax %0,%y1
5565 lxsiwax %x0,%y1
5566 mtvsrwa %x0,%1"
5567 [(set_attr "type" "fpload,fpload,mffgpr")])
5569 ; This split must be run before register allocation because it allocates the
5570 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5571 ; it earlier to allow for the combiner to merge insns together where it might
5572 ; not be needed and also in case the insns are deleted as dead code.
5574 (define_insn_and_split "floatsi<mode>2_lfiwax"
5575 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5576 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5577 (clobber (match_scratch:DI 2 "=d"))]
5578 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5579 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5580 "#"
5581 ""
5582 [(pc)]
5583 "
5584 {
5585 rtx dest = operands[0];
5586 rtx src = operands[1];
5587 rtx tmp;
5589 if (!MEM_P (src) && TARGET_POWERPC64
5590 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5591 tmp = convert_to_mode (DImode, src, false);
5592 else
5593 {
5594 tmp = operands[2];
5595 if (GET_CODE (tmp) == SCRATCH)
5596 tmp = gen_reg_rtx (DImode);
5597 if (MEM_P (src))
5598 {
5599 src = rs6000_address_for_fpconvert (src);
5600 emit_insn (gen_lfiwax (tmp, src));
5601 }
5602 else
5603 {
5604 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5605 emit_move_insn (stack, src);
5606 emit_insn (gen_lfiwax (tmp, stack));
5607 }
5608 }
5609 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5610 DONE;
5611 }"
5612 [(set_attr "length" "12")
5613 (set_attr "type" "fpload")])
5615 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5616 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5617 (float:SFDF
5618 (sign_extend:DI
5619 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5620 (clobber (match_scratch:DI 2 "=0,d"))]
5621 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5622 && <SI_CONVERT_FP>"
5623 "#"
5624 ""
5625 [(pc)]
5626 "
5627 {
5628 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5629 if (GET_CODE (operands[2]) == SCRATCH)
5630 operands[2] = gen_reg_rtx (DImode);
5631 emit_insn (gen_lfiwax (operands[2], operands[1]));
5632 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5633 DONE;
5634 }"
5635 [(set_attr "length" "8")
5636 (set_attr "type" "fpload")])
5638 (define_insn "lfiwzx"
5639 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5640 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5641 UNSPEC_LFIWZX))]
5642 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5643 "@
5644 lfiwzx %0,%y1
5645 lxsiwzx %x0,%y1
5646 mtvsrwz %x0,%1"
5647 [(set_attr "type" "fpload,fpload,mftgpr")])
5649 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5650 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5651 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5652 (clobber (match_scratch:DI 2 "=d"))]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5654 && <SI_CONVERT_FP>"
5655 "#"
5656 ""
5657 [(pc)]
5658 "
5659 {
5660 rtx dest = operands[0];
5661 rtx src = operands[1];
5662 rtx tmp;
5664 if (!MEM_P (src) && TARGET_POWERPC64
5665 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5666 tmp = convert_to_mode (DImode, src, true);
5667 else
5668 {
5669 tmp = operands[2];
5670 if (GET_CODE (tmp) == SCRATCH)
5671 tmp = gen_reg_rtx (DImode);
5672 if (MEM_P (src))
5673 {
5674 src = rs6000_address_for_fpconvert (src);
5675 emit_insn (gen_lfiwzx (tmp, src));
5676 }
5677 else
5678 {
5679 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5680 emit_move_insn (stack, src);
5681 emit_insn (gen_lfiwzx (tmp, stack));
5682 }
5683 }
5684 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5685 DONE;
5686 }"
5687 [(set_attr "length" "12")
5688 (set_attr "type" "fpload")])
5690 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5691 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5692 (unsigned_float:SFDF
5693 (zero_extend:DI
5694 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5695 (clobber (match_scratch:DI 2 "=0,d"))]
5696 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5697 && <SI_CONVERT_FP>"
5698 "#"
5699 ""
5700 [(pc)]
5701 "
5702 {
5703 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5704 if (GET_CODE (operands[2]) == SCRATCH)
5705 operands[2] = gen_reg_rtx (DImode);
5706 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5707 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5708 DONE;
5709 }"
5710 [(set_attr "length" "8")
5711 (set_attr "type" "fpload")])
5713 ; For each of these conversions, there is a define_expand, a define_insn
5714 ; with a '#' template, and a define_split (with C code). The idea is
5715 ; to allow constant folding with the template of the define_insn,
5716 ; then to have the insns split later (between sched1 and final).
5718 (define_expand "floatsidf2"
5719 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5720 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5721 (use (match_dup 2))
5722 (use (match_dup 3))
5723 (clobber (match_dup 4))
5724 (clobber (match_dup 5))
5725 (clobber (match_dup 6))])]
5726 "TARGET_HARD_FLOAT
5727 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5728 "
5729 {
5730 if (TARGET_E500_DOUBLE)
5731 {
5732 if (!REG_P (operands[1]))
5733 operands[1] = force_reg (SImode, operands[1]);
5734 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5735 DONE;
5736 }
5737 else if (TARGET_LFIWAX && TARGET_FCFID)
5738 {
5739 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5740 DONE;
5741 }
5742 else if (TARGET_FCFID)
5743 {
5744 rtx dreg = operands[1];
5745 if (!REG_P (dreg))
5746 dreg = force_reg (SImode, dreg);
5747 dreg = convert_to_mode (DImode, dreg, false);
5748 emit_insn (gen_floatdidf2 (operands[0], dreg));
5749 DONE;
5750 }
5752 if (!REG_P (operands[1]))
5753 operands[1] = force_reg (SImode, operands[1]);
5754 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5755 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5756 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5757 operands[5] = gen_reg_rtx (DFmode);
5758 operands[6] = gen_reg_rtx (SImode);
5759 }")
5761 (define_insn_and_split "*floatsidf2_internal"
5762 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5763 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5764 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5765 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5766 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5767 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5768 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5769 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5770 "#"
5771 ""
5772 [(pc)]
5773 "
5774 {
5775 rtx lowword, highword;
5776 gcc_assert (MEM_P (operands[4]));
5777 highword = adjust_address (operands[4], SImode, 0);
5778 lowword = adjust_address (operands[4], SImode, 4);
5779 if (! WORDS_BIG_ENDIAN)
5780 {
5781 rtx tmp;
5782 tmp = highword; highword = lowword; lowword = tmp;
5783 }
5785 emit_insn (gen_xorsi3 (operands[6], operands[1],
5786 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5787 emit_move_insn (lowword, operands[6]);
5788 emit_move_insn (highword, operands[2]);
5789 emit_move_insn (operands[5], operands[4]);
5790 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5791 DONE;
5792 }"
5793 [(set_attr "length" "24")
5794 (set_attr "type" "fp")])
5796 ;; If we don't have a direct conversion to single precision, don't enable this
5797 ;; conversion for 32-bit without fast math, because we don't have the insn to
5798 ;; generate the fixup swizzle to avoid double rounding problems.
5799 (define_expand "floatunssisf2"
5800 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5801 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5802 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5803 && (!TARGET_FPRS
5804 || (TARGET_FPRS
5805 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5806 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5807 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5808 "
5809 {
5810 if (!TARGET_FPRS)
5811 {
5812 if (!REG_P (operands[1]))
5813 operands[1] = force_reg (SImode, operands[1]);
5814 }
5815 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5816 {
5817 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5818 DONE;
5819 }
5820 else
5821 {
5822 rtx dreg = operands[1];
5823 if (!REG_P (dreg))
5824 dreg = force_reg (SImode, dreg);
5825 dreg = convert_to_mode (DImode, dreg, true);
5826 emit_insn (gen_floatdisf2 (operands[0], dreg));
5827 DONE;
5828 }
5829 }")
5831 (define_expand "floatunssidf2"
5832 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5833 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5834 (use (match_dup 2))
5835 (use (match_dup 3))
5836 (clobber (match_dup 4))
5837 (clobber (match_dup 5))])]
5838 "TARGET_HARD_FLOAT
5839 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5840 "
5841 {
5842 if (TARGET_E500_DOUBLE)
5843 {
5844 if (!REG_P (operands[1]))
5845 operands[1] = force_reg (SImode, operands[1]);
5846 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5847 DONE;
5848 }
5849 else if (TARGET_LFIWZX && TARGET_FCFID)
5850 {
5851 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5852 DONE;
5853 }
5854 else if (TARGET_FCFID)
5855 {
5856 rtx dreg = operands[1];
5857 if (!REG_P (dreg))
5858 dreg = force_reg (SImode, dreg);
5859 dreg = convert_to_mode (DImode, dreg, true);
5860 emit_insn (gen_floatdidf2 (operands[0], dreg));
5861 DONE;
5862 }
5864 if (!REG_P (operands[1]))
5865 operands[1] = force_reg (SImode, operands[1]);
5866 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5867 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5868 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5869 operands[5] = gen_reg_rtx (DFmode);
5870 }")
5872 (define_insn_and_split "*floatunssidf2_internal"
5873 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5874 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5875 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5876 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5877 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5878 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5879 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5880 && !(TARGET_FCFID && TARGET_POWERPC64)"
5881 "#"
5882 ""
5883 [(pc)]
5884 "
5885 {
5886 rtx lowword, highword;
5887 gcc_assert (MEM_P (operands[4]));
5888 highword = adjust_address (operands[4], SImode, 0);
5889 lowword = adjust_address (operands[4], SImode, 4);
5890 if (! WORDS_BIG_ENDIAN)
5891 {
5892 rtx tmp;
5893 tmp = highword; highword = lowword; lowword = tmp;
5894 }
5896 emit_move_insn (lowword, operands[1]);
5897 emit_move_insn (highword, operands[2]);
5898 emit_move_insn (operands[5], operands[4]);
5899 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5900 DONE;
5901 }"
5902 [(set_attr "length" "20")
5903 (set_attr "type" "fp")])
5905 (define_expand "fix_trunc<mode>si2"
5906 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5907 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5908 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5909 "
5910 {
5911 if (!<E500_CONVERT>)
5912 {
5913 rtx tmp, stack;
5915 if (TARGET_STFIWX)
5916 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5917 else
5918 {
5919 tmp = gen_reg_rtx (DImode);
5920 stack = rs6000_allocate_stack_temp (DImode, true, false);
5921 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5922 tmp, stack));
5923 }
5924 DONE;
5925 }
5926 }")
5928 ; Like the convert to float patterns, this insn must be split before
5929 ; register allocation so that it can allocate the memory slot if it
5930 ; needed
5931 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5932 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5933 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5934 (clobber (match_scratch:DI 2 "=d"))]
5935 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5936 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5937 && TARGET_STFIWX && can_create_pseudo_p ()"
5938 "#"
5939 ""
5940 [(pc)]
5941 {
5942 rtx dest = operands[0];
5943 rtx src = operands[1];
5944 rtx tmp = operands[2];
5946 if (GET_CODE (tmp) == SCRATCH)
5947 tmp = gen_reg_rtx (DImode);
5949 emit_insn (gen_fctiwz_<mode> (tmp, src));
5950 if (MEM_P (dest))
5951 {
5952 dest = rs6000_address_for_fpconvert (dest);
5953 emit_insn (gen_stfiwx (dest, tmp));
5954 DONE;
5955 }
5956 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5957 {
5958 dest = gen_lowpart (DImode, dest);
5959 emit_move_insn (dest, tmp);
5960 DONE;
5961 }
5962 else
5963 {
5964 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5965 emit_insn (gen_stfiwx (stack, tmp));
5966 emit_move_insn (dest, stack);
5967 DONE;
5968 }
5969 }
5970 [(set_attr "length" "12")
5971 (set_attr "type" "fp")])
5973 (define_insn_and_split "fix_trunc<mode>si2_internal"
5974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5975 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5976 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5977 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5978 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5979 "#"
5980 ""
5981 [(pc)]
5982 "
5983 {
5984 rtx lowword;
5985 gcc_assert (MEM_P (operands[3]));
5986 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5988 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5989 emit_move_insn (operands[3], operands[2]);
5990 emit_move_insn (operands[0], lowword);
5991 DONE;
5992 }"
5993 [(set_attr "length" "16")
5994 (set_attr "type" "fp")])
5996 (define_expand "fix_trunc<mode>di2"
5997 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5998 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5999 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6000 && TARGET_FCFID"
6001 "")
6003 (define_insn "*fix_trunc<mode>di2_fctidz"
6004 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6005 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6006 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6007 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6008 "fctidz %0,%1"
6009 [(set_attr "type" "fp")])
6011 (define_expand "fixuns_trunc<mode>si2"
6012 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6013 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6014 "TARGET_HARD_FLOAT
6015 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6016 || <E500_CONVERT>)"
6017 "
6018 {
6019 if (!<E500_CONVERT>)
6020 {
6021 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6022 DONE;
6023 }
6024 }")
6026 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6027 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6028 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6029 (clobber (match_scratch:DI 2 "=d"))]
6030 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6031 && TARGET_STFIWX && can_create_pseudo_p ()"
6032 "#"
6033 ""
6034 [(pc)]
6035 {
6036 rtx dest = operands[0];
6037 rtx src = operands[1];
6038 rtx tmp = operands[2];
6040 if (GET_CODE (tmp) == SCRATCH)
6041 tmp = gen_reg_rtx (DImode);
6043 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6044 if (MEM_P (dest))
6045 {
6046 dest = rs6000_address_for_fpconvert (dest);
6047 emit_insn (gen_stfiwx (dest, tmp));
6048 DONE;
6049 }
6050 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6051 {
6052 dest = gen_lowpart (DImode, dest);
6053 emit_move_insn (dest, tmp);
6054 DONE;
6055 }
6056 else
6057 {
6058 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6059 emit_insn (gen_stfiwx (stack, tmp));
6060 emit_move_insn (dest, stack);
6061 DONE;
6062 }
6063 }
6064 [(set_attr "length" "12")
6065 (set_attr "type" "fp")])
6067 (define_expand "fixuns_trunc<mode>di2"
6068 [(set (match_operand:DI 0 "register_operand" "")
6069 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6070 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6071 "")
6073 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6074 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6075 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6076 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6077 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6078 "fctiduz %0,%1"
6079 [(set_attr "type" "fp")])
6081 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6082 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6083 ; because the first makes it clear that operand 0 is not live
6084 ; before the instruction.
6085 (define_insn "fctiwz_<mode>"
6086 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6087 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6088 UNSPEC_FCTIWZ))]
6089 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6090 "fctiwz %0,%1"
6091 [(set_attr "type" "fp")])
6093 (define_insn "fctiwuz_<mode>"
6094 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6095 (unspec:DI [(unsigned_fix:SI
6096 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6097 UNSPEC_FCTIWUZ))]
6098 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6099 "fctiwuz %0,%1"
6100 [(set_attr "type" "fp")])
6102 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6103 ;; since the friz instruction does not truncate the value if the floating
6104 ;; point value is < LONG_MIN or > LONG_MAX.
6105 (define_insn "*friz"
6106 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6107 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6108 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6109 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6110 && !flag_trapping_math && TARGET_FRIZ"
6111 "friz %0,%1"
6112 [(set_attr "type" "fp")])
6114 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6115 ;; load to properly sign extend the value, but at least doing a store, load
6116 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6117 ;; if we have 32-bit memory ops
6118 (define_insn_and_split "*round32<mode>2_fprs"
6119 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6120 (float:SFDF
6121 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6122 (clobber (match_scratch:DI 2 "=d"))
6123 (clobber (match_scratch:DI 3 "=d"))]
6124 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6125 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6126 && can_create_pseudo_p ()"
6127 "#"
6128 ""
6129 [(pc)]
6130 {
6131 rtx dest = operands[0];
6132 rtx src = operands[1];
6133 rtx tmp1 = operands[2];
6134 rtx tmp2 = operands[3];
6135 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6137 if (GET_CODE (tmp1) == SCRATCH)
6138 tmp1 = gen_reg_rtx (DImode);
6139 if (GET_CODE (tmp2) == SCRATCH)
6140 tmp2 = gen_reg_rtx (DImode);
6142 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6143 emit_insn (gen_stfiwx (stack, tmp1));
6144 emit_insn (gen_lfiwax (tmp2, stack));
6145 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6146 DONE;
6147 }
6148 [(set_attr "type" "fpload")
6149 (set_attr "length" "16")])
6151 (define_insn_and_split "*roundu32<mode>2_fprs"
6152 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6153 (unsigned_float:SFDF
6154 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6155 (clobber (match_scratch:DI 2 "=d"))
6156 (clobber (match_scratch:DI 3 "=d"))]
6157 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6158 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6159 && can_create_pseudo_p ()"
6160 "#"
6161 ""
6162 [(pc)]
6163 {
6164 rtx dest = operands[0];
6165 rtx src = operands[1];
6166 rtx tmp1 = operands[2];
6167 rtx tmp2 = operands[3];
6168 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6170 if (GET_CODE (tmp1) == SCRATCH)
6171 tmp1 = gen_reg_rtx (DImode);
6172 if (GET_CODE (tmp2) == SCRATCH)
6173 tmp2 = gen_reg_rtx (DImode);
6175 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6176 emit_insn (gen_stfiwx (stack, tmp1));
6177 emit_insn (gen_lfiwzx (tmp2, stack));
6178 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6179 DONE;
6180 }
6181 [(set_attr "type" "fpload")
6182 (set_attr "length" "16")])
6184 ;; No VSX equivalent to fctid
6185 (define_insn "lrint<mode>di2"
6186 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6187 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6188 UNSPEC_FCTID))]
6189 "TARGET_<MODE>_FPR && TARGET_FPRND"
6190 "fctid %0,%1"
6191 [(set_attr "type" "fp")])
6193 (define_insn "btrunc<mode>2"
6194 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6195 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6196 UNSPEC_FRIZ))]
6197 "TARGET_<MODE>_FPR && TARGET_FPRND"
6198 "@
6199 friz %0,%1
6200 xsrdpiz %x0,%x1"
6201 [(set_attr "type" "fp")
6202 (set_attr "fp_type" "fp_addsub_<Fs>")])
6204 (define_insn "ceil<mode>2"
6205 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6206 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6207 UNSPEC_FRIP))]
6208 "TARGET_<MODE>_FPR && TARGET_FPRND"
6209 "@
6210 frip %0,%1
6211 xsrdpip %x0,%x1"
6212 [(set_attr "type" "fp")
6213 (set_attr "fp_type" "fp_addsub_<Fs>")])
6215 (define_insn "floor<mode>2"
6216 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6217 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6218 UNSPEC_FRIM))]
6219 "TARGET_<MODE>_FPR && TARGET_FPRND"
6220 "@
6221 frim %0,%1
6222 xsrdpim %x0,%x1"
6223 [(set_attr "type" "fp")
6224 (set_attr "fp_type" "fp_addsub_<Fs>")])
6226 ;; No VSX equivalent to frin
6227 (define_insn "round<mode>2"
6228 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6229 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6230 UNSPEC_FRIN))]
6231 "TARGET_<MODE>_FPR && TARGET_FPRND"
6232 "frin %0,%1"
6233 [(set_attr "type" "fp")
6234 (set_attr "fp_type" "fp_addsub_<Fs>")])
6236 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6237 (define_insn "stfiwx"
6238 [(set (match_operand:SI 0 "memory_operand" "=Z")
6239 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6240 UNSPEC_STFIWX))]
6241 "TARGET_PPC_GFXOPT"
6242 "stfiwx %1,%y0"
6243 [(set_attr "type" "fpstore")])
6245 ;; If we don't have a direct conversion to single precision, don't enable this
6246 ;; conversion for 32-bit without fast math, because we don't have the insn to
6247 ;; generate the fixup swizzle to avoid double rounding problems.
6248 (define_expand "floatsisf2"
6249 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6250 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6251 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6252 && (!TARGET_FPRS
6253 || (TARGET_FPRS
6254 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6255 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6256 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6257 "
6258 {
6259 if (!TARGET_FPRS)
6260 {
6261 if (!REG_P (operands[1]))
6262 operands[1] = force_reg (SImode, operands[1]);
6263 }
6264 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6265 {
6266 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6267 DONE;
6268 }
6269 else if (TARGET_FCFID && TARGET_LFIWAX)
6270 {
6271 rtx dfreg = gen_reg_rtx (DFmode);
6272 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6273 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6274 DONE;
6275 }
6276 else
6277 {
6278 rtx dreg = operands[1];
6279 if (!REG_P (dreg))
6280 dreg = force_reg (SImode, dreg);
6281 dreg = convert_to_mode (DImode, dreg, false);
6282 emit_insn (gen_floatdisf2 (operands[0], dreg));
6283 DONE;
6284 }
6285 }")
6287 (define_expand "floatdidf2"
6288 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6289 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6290 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6291 "")
6293 (define_insn "*floatdidf2_fpr"
6294 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6295 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6296 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6297 && !VECTOR_UNIT_VSX_P (DFmode)"
6298 "fcfid %0,%1"
6299 [(set_attr "type" "fp")])
6301 ; Allow the combiner to merge source memory operands to the conversion so that
6302 ; the optimizer/register allocator doesn't try to load the value too early in a
6303 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6304 ; hit. We will split after reload to avoid the trip through the GPRs
6306 (define_insn_and_split "*floatdidf2_mem"
6307 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6308 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6309 (clobber (match_scratch:DI 2 "=d"))]
6310 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6311 "#"
6312 "&& reload_completed"
6313 [(set (match_dup 2) (match_dup 1))
6314 (set (match_dup 0) (float:DF (match_dup 2)))]
6315 ""
6316 [(set_attr "length" "8")
6317 (set_attr "type" "fpload")])
6319 (define_expand "floatunsdidf2"
6320 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6321 (unsigned_float:DF
6322 (match_operand:DI 1 "gpc_reg_operand" "")))]
6323 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6324 "")
6326 (define_insn "*floatunsdidf2_fcfidu"
6327 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6328 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6329 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6330 "fcfidu %0,%1"
6331 [(set_attr "type" "fp")
6332 (set_attr "length" "4")])
6334 (define_insn_and_split "*floatunsdidf2_mem"
6335 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6336 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6337 (clobber (match_scratch:DI 2 "=d"))]
6338 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6339 "#"
6340 "&& reload_completed"
6341 [(set (match_dup 2) (match_dup 1))
6342 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6343 ""
6344 [(set_attr "length" "8")
6345 (set_attr "type" "fpload")])
6347 (define_expand "floatdisf2"
6348 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6349 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6350 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6351 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6352 "
6353 {
6354 if (!TARGET_FCFIDS)
6355 {
6356 rtx val = operands[1];
6357 if (!flag_unsafe_math_optimizations)
6358 {
6359 rtx label = gen_label_rtx ();
6360 val = gen_reg_rtx (DImode);
6361 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6362 emit_label (label);
6363 }
6364 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6365 DONE;
6366 }
6367 }")
6369 (define_insn "floatdisf2_fcfids"
6370 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6371 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6372 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6373 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6374 "fcfids %0,%1"
6375 [(set_attr "type" "fp")])
6377 (define_insn_and_split "*floatdisf2_mem"
6378 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6379 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6380 (clobber (match_scratch:DI 2 "=f"))]
6381 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6382 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6383 "#"
6384 "&& reload_completed"
6385 [(pc)]
6386 "
6387 {
6388 emit_move_insn (operands[2], operands[1]);
6389 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6390 DONE;
6391 }"
6392 [(set_attr "length" "8")])
6394 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6395 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6396 ;; from double rounding.
6397 ;; Instead of creating a new cpu type for two FP operations, just use fp
6398 (define_insn_and_split "floatdisf2_internal1"
6399 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6400 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6401 (clobber (match_scratch:DF 2 "=d"))]
6402 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6403 "#"
6404 "&& reload_completed"
6405 [(set (match_dup 2)
6406 (float:DF (match_dup 1)))
6407 (set (match_dup 0)
6408 (float_truncate:SF (match_dup 2)))]
6409 ""
6410 [(set_attr "length" "8")
6411 (set_attr "type" "fp")])
6413 ;; Twiddles bits to avoid double rounding.
6414 ;; Bits that might be truncated when converting to DFmode are replaced
6415 ;; by a bit that won't be lost at that stage, but is below the SFmode
6416 ;; rounding position.
6417 (define_expand "floatdisf2_internal2"
6418 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6419 (const_int 53)))
6420 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6421 (const_int 2047)))
6422 (clobber (scratch:CC))])
6423 (set (match_dup 3) (plus:DI (match_dup 3)
6424 (const_int 1)))
6425 (set (match_dup 0) (plus:DI (match_dup 0)
6426 (const_int 2047)))
6427 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6428 (const_int 2)))
6429 (set (match_dup 0) (ior:DI (match_dup 0)
6430 (match_dup 1)))
6431 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6432 (const_int -2048)))
6433 (clobber (scratch:CC))])
6434 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6435 (label_ref (match_operand:DI 2 "" ""))
6436 (pc)))
6437 (set (match_dup 0) (match_dup 1))]
6438 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6439 "
6440 {
6441 operands[3] = gen_reg_rtx (DImode);
6442 operands[4] = gen_reg_rtx (CCUNSmode);
6443 }")
6445 (define_expand "floatunsdisf2"
6446 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6447 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6448 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6449 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6450 "")
6452 (define_insn "floatunsdisf2_fcfidus"
6453 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6454 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6455 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6456 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6457 "fcfidus %0,%1"
6458 [(set_attr "type" "fp")])
6460 (define_insn_and_split "*floatunsdisf2_mem"
6461 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6462 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6463 (clobber (match_scratch:DI 2 "=f"))]
6464 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6465 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6466 "#"
6467 "&& reload_completed"
6468 [(pc)]
6469 "
6470 {
6471 emit_move_insn (operands[2], operands[1]);
6472 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6473 DONE;
6474 }"
6475 [(set_attr "length" "8")
6476 (set_attr "type" "fpload")])
6477 \f
6478 ;; Define the TImode operations that can be done in a small number
6479 ;; of instructions. The & constraints are to prevent the register
6480 ;; allocator from allocating registers that overlap with the inputs
6481 ;; (for example, having an input in 7,8 and an output in 6,7). We
6482 ;; also allow for the output being the same as one of the inputs.
6484 (define_insn "addti3"
6485 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6486 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6487 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6488 "TARGET_64BIT"
6489 {
6490 if (WORDS_BIG_ENDIAN)
6491 return (GET_CODE (operands[2])) != CONST_INT
6492 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6493 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6494 else
6495 return (GET_CODE (operands[2])) != CONST_INT
6496 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6497 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6498 }
6499 [(set_attr "type" "two")
6500 (set_attr "length" "8")])
6502 (define_insn "subti3"
6503 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6504 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6505 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6506 "TARGET_64BIT"
6507 {
6508 if (WORDS_BIG_ENDIAN)
6509 return (GET_CODE (operands[1]) != CONST_INT)
6510 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6511 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6512 else
6513 return (GET_CODE (operands[1]) != CONST_INT)
6514 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6515 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6516 }
6517 [(set_attr "type" "two")
6518 (set_attr "length" "8")])
6521 ;; Define the DImode operations that can be done in a small number
6522 ;; of instructions. The & constraints are to prevent the register
6523 ;; allocator from allocating registers that overlap with the inputs
6524 ;; (for example, having an input in 7,8 and an output in 6,7). We
6525 ;; also allow for the output being the same as one of the inputs.
6527 (define_insn "*adddi3_noppc64"
6528 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6529 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6530 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6531 "! TARGET_POWERPC64"
6532 "*
6533 {
6534 if (WORDS_BIG_ENDIAN)
6535 return (GET_CODE (operands[2])) != CONST_INT
6536 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6537 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6538 else
6539 return (GET_CODE (operands[2])) != CONST_INT
6540 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6541 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6542 }"
6543 [(set_attr "type" "two")
6544 (set_attr "length" "8")])
6546 (define_insn "*subdi3_noppc64"
6547 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6548 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6549 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6550 "! TARGET_POWERPC64"
6551 "*
6552 {
6553 if (WORDS_BIG_ENDIAN)
6554 return (GET_CODE (operands[1]) != CONST_INT)
6555 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6556 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6557 else
6558 return (GET_CODE (operands[1]) != CONST_INT)
6559 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6560 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6561 }"
6562 [(set_attr "type" "two")
6563 (set_attr "length" "8")])
6565 (define_insn "*negdi2_noppc64"
6566 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6567 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6568 "! TARGET_POWERPC64"
6569 "*
6570 {
6571 return (WORDS_BIG_ENDIAN)
6572 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6573 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6574 }"
6575 [(set_attr "type" "two")
6576 (set_attr "length" "8")])
6578 (define_insn "mulsidi3"
6579 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6580 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6581 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6582 "! TARGET_POWERPC64"
6583 {
6584 return (WORDS_BIG_ENDIAN)
6585 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6586 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6587 }
6588 [(set_attr "type" "imul")
6589 (set_attr "length" "8")])
6591 (define_split
6592 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6593 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6594 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6595 "! TARGET_POWERPC64 && reload_completed"
6596 [(set (match_dup 3)
6597 (truncate:SI
6598 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6599 (sign_extend:DI (match_dup 2)))
6600 (const_int 32))))
6601 (set (match_dup 4)
6602 (mult:SI (match_dup 1)
6603 (match_dup 2)))]
6604 "
6605 {
6606 int endian = (WORDS_BIG_ENDIAN == 0);
6607 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6608 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6609 }")
6611 (define_insn "umulsidi3"
6612 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6613 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6614 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6615 "! TARGET_POWERPC64"
6616 "*
6617 {
6618 return (WORDS_BIG_ENDIAN)
6619 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6620 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6621 }"
6622 [(set_attr "type" "imul")
6623 (set_attr "length" "8")])
6625 (define_split
6626 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6627 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6628 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6629 "! TARGET_POWERPC64 && reload_completed"
6630 [(set (match_dup 3)
6631 (truncate:SI
6632 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6633 (zero_extend:DI (match_dup 2)))
6634 (const_int 32))))
6635 (set (match_dup 4)
6636 (mult:SI (match_dup 1)
6637 (match_dup 2)))]
6638 "
6639 {
6640 int endian = (WORDS_BIG_ENDIAN == 0);
6641 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6642 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6643 }")
6645 (define_insn "smulsi3_highpart"
6646 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6647 (truncate:SI
6648 (lshiftrt:DI (mult:DI (sign_extend:DI
6649 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6650 (sign_extend:DI
6651 (match_operand:SI 2 "gpc_reg_operand" "r")))
6652 (const_int 32))))]
6653 ""
6654 "mulhw %0,%1,%2"
6655 [(set_attr "type" "imul")])
6657 (define_insn "umulsi3_highpart"
6658 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6659 (truncate:SI
6660 (lshiftrt:DI (mult:DI (zero_extend:DI
6661 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6662 (zero_extend:DI
6663 (match_operand:SI 2 "gpc_reg_operand" "r")))
6664 (const_int 32))))]
6665 ""
6666 "mulhwu %0,%1,%2"
6667 [(set_attr "type" "imul")])
6669 ;; Shift by a variable amount is too complex to be worth open-coding. We
6670 ;; just handle shifts by constants.
6671 (define_insn "ashrdi3_no_power"
6672 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6673 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6674 (match_operand:SI 2 "const_int_operand" "M,i")))]
6675 "!TARGET_POWERPC64"
6676 "*
6677 {
6678 switch (which_alternative)
6679 {
6680 default:
6681 gcc_unreachable ();
6682 case 0:
6683 if (WORDS_BIG_ENDIAN)
6684 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6685 else
6686 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6687 case 1:
6688 if (WORDS_BIG_ENDIAN)
6689 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6690 else
6691 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6692 }
6693 }"
6694 [(set_attr "type" "two,three")
6695 (set_attr "length" "8,12")])
6697 (define_insn "*ashrdisi3_noppc64be"
6698 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6699 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6700 (const_int 32)) 4))]
6701 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6702 "*
6703 {
6704 if (REGNO (operands[0]) == REGNO (operands[1]))
6705 return \"\";
6706 else
6707 return \"mr %0,%1\";
6708 }"
6709 [(set_attr "length" "4")])
6711 \f
6712 ;; PowerPC64 DImode operations.
6714 (define_insn "muldi3"
6715 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6716 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6717 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6718 "TARGET_POWERPC64"
6719 "@
6720 mulld %0,%1,%2
6721 mulli %0,%1,%2"
6722 [(set (attr "type")
6723 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6724 (const_string "imul3")
6725 (match_operand:SI 2 "short_cint_operand" "")
6726 (const_string "imul2")]
6727 (const_string "lmul")))])
6729 (define_insn "*muldi3_internal1"
6730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6731 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6732 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6733 (const_int 0)))
6734 (clobber (match_scratch:DI 3 "=r,r"))]
6735 "TARGET_POWERPC64"
6736 "@
6737 mulld. %3,%1,%2
6738 #"
6739 [(set_attr "type" "lmul_compare")
6740 (set_attr "length" "4,8")])
6742 (define_split
6743 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6744 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6745 (match_operand:DI 2 "gpc_reg_operand" ""))
6746 (const_int 0)))
6747 (clobber (match_scratch:DI 3 ""))]
6748 "TARGET_POWERPC64 && reload_completed"
6749 [(set (match_dup 3)
6750 (mult:DI (match_dup 1) (match_dup 2)))
6751 (set (match_dup 0)
6752 (compare:CC (match_dup 3)
6753 (const_int 0)))]
6754 "")
6756 (define_insn "*muldi3_internal2"
6757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6758 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6759 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6760 (const_int 0)))
6761 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6762 (mult:DI (match_dup 1) (match_dup 2)))]
6763 "TARGET_POWERPC64"
6764 "@
6765 mulld. %0,%1,%2
6766 #"
6767 [(set_attr "type" "lmul_compare")
6768 (set_attr "length" "4,8")])
6770 (define_split
6771 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6772 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6773 (match_operand:DI 2 "gpc_reg_operand" ""))
6774 (const_int 0)))
6775 (set (match_operand:DI 0 "gpc_reg_operand" "")
6776 (mult:DI (match_dup 1) (match_dup 2)))]
6777 "TARGET_POWERPC64 && reload_completed"
6778 [(set (match_dup 0)
6779 (mult:DI (match_dup 1) (match_dup 2)))
6780 (set (match_dup 3)
6781 (compare:CC (match_dup 0)
6782 (const_int 0)))]
6783 "")
6785 (define_insn "smuldi3_highpart"
6786 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6787 (truncate:DI
6788 (lshiftrt:TI (mult:TI (sign_extend:TI
6789 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6790 (sign_extend:TI
6791 (match_operand:DI 2 "gpc_reg_operand" "r")))
6792 (const_int 64))))]
6793 "TARGET_POWERPC64"
6794 "mulhd %0,%1,%2"
6795 [(set_attr "type" "lmul")])
6797 (define_insn "umuldi3_highpart"
6798 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6799 (truncate:DI
6800 (lshiftrt:TI (mult:TI (zero_extend:TI
6801 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6802 (zero_extend:TI
6803 (match_operand:DI 2 "gpc_reg_operand" "r")))
6804 (const_int 64))))]
6805 "TARGET_POWERPC64"
6806 "mulhdu %0,%1,%2"
6807 [(set_attr "type" "lmul")])
6809 (define_expand "mulditi3"
6810 [(set (match_operand:TI 0 "gpc_reg_operand")
6811 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6812 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6813 "TARGET_POWERPC64"
6814 {
6815 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6816 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6817 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
6818 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6819 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6820 DONE;
6821 })
6823 (define_expand "umulditi3"
6824 [(set (match_operand:TI 0 "gpc_reg_operand")
6825 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6826 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6827 "TARGET_POWERPC64"
6828 {
6829 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6830 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6831 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
6832 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6833 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6834 DONE;
6835 })
6837 (define_insn "rotldi3"
6838 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6839 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6840 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6841 "TARGET_POWERPC64"
6842 "@
6843 rldcl %0,%1,%2,0
6844 rldicl %0,%1,%H2,0"
6845 [(set_attr "type" "var_shift_rotate,integer")])
6847 (define_insn "*rotldi3_internal2"
6848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6849 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6850 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6851 (const_int 0)))
6852 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6853 "TARGET_64BIT"
6854 "@
6855 rldcl. %3,%1,%2,0
6856 rldicl. %3,%1,%H2,0
6857 #
6858 #"
6859 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6860 (set_attr "length" "4,4,8,8")])
6862 (define_split
6863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6864 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6865 (match_operand:DI 2 "reg_or_cint_operand" ""))
6866 (const_int 0)))
6867 (clobber (match_scratch:DI 3 ""))]
6868 "TARGET_POWERPC64 && reload_completed"
6869 [(set (match_dup 3)
6870 (rotate:DI (match_dup 1) (match_dup 2)))
6871 (set (match_dup 0)
6872 (compare:CC (match_dup 3)
6873 (const_int 0)))]
6874 "")
6876 (define_insn "*rotldi3_internal3"
6877 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6878 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6879 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6880 (const_int 0)))
6881 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6882 (rotate:DI (match_dup 1) (match_dup 2)))]
6883 "TARGET_64BIT"
6884 "@
6885 rldcl. %0,%1,%2,0
6886 rldicl. %0,%1,%H2,0
6887 #
6888 #"
6889 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6890 (set_attr "length" "4,4,8,8")])
6892 (define_split
6893 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6894 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6895 (match_operand:DI 2 "reg_or_cint_operand" ""))
6896 (const_int 0)))
6897 (set (match_operand:DI 0 "gpc_reg_operand" "")
6898 (rotate:DI (match_dup 1) (match_dup 2)))]
6899 "TARGET_POWERPC64 && reload_completed"
6900 [(set (match_dup 0)
6901 (rotate:DI (match_dup 1) (match_dup 2)))
6902 (set (match_dup 3)
6903 (compare:CC (match_dup 0)
6904 (const_int 0)))]
6905 "")
6907 (define_insn "*rotldi3_internal4"
6908 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6909 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6910 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6911 (match_operand:DI 3 "mask64_operand" "n,n")))]
6912 "TARGET_POWERPC64"
6913 "@
6914 rldc%B3 %0,%1,%2,%S3
6915 rldic%B3 %0,%1,%H2,%S3"
6916 [(set_attr "type" "var_shift_rotate,integer")])
6918 (define_insn "*rotldi3_internal5"
6919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6920 (compare:CC (and:DI
6921 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6922 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6923 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6924 (const_int 0)))
6925 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6926 "TARGET_64BIT"
6927 "@
6928 rldc%B3. %4,%1,%2,%S3
6929 rldic%B3. %4,%1,%H2,%S3
6930 #
6931 #"
6932 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6933 (set_attr "length" "4,4,8,8")])
6935 (define_split
6936 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6937 (compare:CC (and:DI
6938 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6939 (match_operand:DI 2 "reg_or_cint_operand" ""))
6940 (match_operand:DI 3 "mask64_operand" ""))
6941 (const_int 0)))
6942 (clobber (match_scratch:DI 4 ""))]
6943 "TARGET_POWERPC64 && reload_completed"
6944 [(set (match_dup 4)
6945 (and:DI (rotate:DI (match_dup 1)
6946 (match_dup 2))
6947 (match_dup 3)))
6948 (set (match_dup 0)
6949 (compare:CC (match_dup 4)
6950 (const_int 0)))]
6951 "")
6953 (define_insn "*rotldi3_internal6"
6954 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6955 (compare:CC (and:DI
6956 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6957 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6958 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6959 (const_int 0)))
6960 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6961 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6962 "TARGET_64BIT"
6963 "@
6964 rldc%B3. %0,%1,%2,%S3
6965 rldic%B3. %0,%1,%H2,%S3
6966 #
6967 #"
6968 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6969 (set_attr "length" "4,4,8,8")])
6971 (define_split
6972 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6973 (compare:CC (and:DI
6974 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6975 (match_operand:DI 2 "reg_or_cint_operand" ""))
6976 (match_operand:DI 3 "mask64_operand" ""))
6977 (const_int 0)))
6978 (set (match_operand:DI 0 "gpc_reg_operand" "")
6979 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6980 "TARGET_POWERPC64 && reload_completed"
6981 [(set (match_dup 0)
6982 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6983 (set (match_dup 4)
6984 (compare:CC (match_dup 0)
6985 (const_int 0)))]
6986 "")
6988 (define_insn "*rotldi3_internal7le"
6989 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6990 (zero_extend:DI
6991 (subreg:QI
6992 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6993 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6994 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6995 "@
6996 rldcl %0,%1,%2,56
6997 rldicl %0,%1,%H2,56"
6998 [(set_attr "type" "var_shift_rotate,integer")])
7000 (define_insn "*rotldi3_internal7be"
7001 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7002 (zero_extend:DI
7003 (subreg:QI
7004 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7005 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
7006 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7007 "@
7008 rldcl %0,%1,%2,56
7009 rldicl %0,%1,%H2,56"
7010 [(set_attr "type" "var_shift_rotate,integer")])
7012 (define_insn "*rotldi3_internal8le"
7013 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7014 (compare:CC (zero_extend:DI
7015 (subreg:QI
7016 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7017 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7018 (const_int 0)))
7019 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7020 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7021 "@
7022 rldcl. %3,%1,%2,56
7023 rldicl. %3,%1,%H2,56
7024 #
7025 #"
7026 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7027 (set_attr "length" "4,4,8,8")])
7029 (define_insn "*rotldi3_internal8be"
7030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7031 (compare:CC (zero_extend:DI
7032 (subreg:QI
7033 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7034 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7035 (const_int 0)))
7036 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7037 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7038 "@
7039 rldcl. %3,%1,%2,56
7040 rldicl. %3,%1,%H2,56
7041 #
7042 #"
7043 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7044 (set_attr "length" "4,4,8,8")])
7046 (define_split
7047 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7048 (compare:CC (zero_extend:DI
7049 (subreg:QI
7050 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7051 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7052 (const_int 0)))
7053 (clobber (match_scratch:DI 3 ""))]
7054 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7055 [(set (match_dup 3)
7056 (zero_extend:DI (subreg:QI
7057 (rotate:DI (match_dup 1)
7058 (match_dup 2)) 0)))
7059 (set (match_dup 0)
7060 (compare:CC (match_dup 3)
7061 (const_int 0)))]
7062 "")
7064 (define_split
7065 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7066 (compare:CC (zero_extend:DI
7067 (subreg:QI
7068 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7069 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7070 (const_int 0)))
7071 (clobber (match_scratch:DI 3 ""))]
7072 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7073 [(set (match_dup 3)
7074 (zero_extend:DI (subreg:QI
7075 (rotate:DI (match_dup 1)
7076 (match_dup 2)) 7)))
7077 (set (match_dup 0)
7078 (compare:CC (match_dup 3)
7079 (const_int 0)))]
7080 "")
7082 (define_insn "*rotldi3_internal9le"
7083 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7084 (compare:CC (zero_extend:DI
7085 (subreg:QI
7086 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7087 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7088 (const_int 0)))
7089 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7090 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7091 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7092 "@
7093 rldcl. %0,%1,%2,56
7094 rldicl. %0,%1,%H2,56
7095 #
7096 #"
7097 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7098 (set_attr "length" "4,4,8,8")])
7100 (define_insn "*rotldi3_internal9be"
7101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7102 (compare:CC (zero_extend:DI
7103 (subreg:QI
7104 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7105 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7106 (const_int 0)))
7107 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7108 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7109 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7110 "@
7111 rldcl. %0,%1,%2,56
7112 rldicl. %0,%1,%H2,56
7113 #
7114 #"
7115 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7116 (set_attr "length" "4,4,8,8")])
7118 (define_split
7119 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7120 (compare:CC (zero_extend:DI
7121 (subreg:QI
7122 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7123 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7124 (const_int 0)))
7125 (set (match_operand:DI 0 "gpc_reg_operand" "")
7126 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7127 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7128 [(set (match_dup 0)
7129 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7130 (set (match_dup 3)
7131 (compare:CC (match_dup 0)
7132 (const_int 0)))]
7133 "")
7135 (define_split
7136 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7137 (compare:CC (zero_extend:DI
7138 (subreg:QI
7139 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7140 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7141 (const_int 0)))
7142 (set (match_operand:DI 0 "gpc_reg_operand" "")
7143 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7144 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7145 [(set (match_dup 0)
7146 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7147 (set (match_dup 3)
7148 (compare:CC (match_dup 0)
7149 (const_int 0)))]
7150 "")
7152 (define_insn "*rotldi3_internal10le"
7153 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7154 (zero_extend:DI
7155 (subreg:HI
7156 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7157 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7158 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7159 "@
7160 rldcl %0,%1,%2,48
7161 rldicl %0,%1,%H2,48"
7162 [(set_attr "type" "var_shift_rotate,integer")])
7164 (define_insn "*rotldi3_internal10be"
7165 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7166 (zero_extend:DI
7167 (subreg:HI
7168 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7169 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
7170 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7171 "@
7172 rldcl %0,%1,%2,48
7173 rldicl %0,%1,%H2,48"
7174 [(set_attr "type" "var_shift_rotate,integer")])
7176 (define_insn "*rotldi3_internal11le"
7177 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7178 (compare:CC (zero_extend:DI
7179 (subreg:HI
7180 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7181 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7182 (const_int 0)))
7183 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7184 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7185 "@
7186 rldcl. %3,%1,%2,48
7187 rldicl. %3,%1,%H2,48
7188 #
7189 #"
7190 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7191 (set_attr "length" "4,4,8,8")])
7193 (define_insn "*rotldi3_internal11be"
7194 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7195 (compare:CC (zero_extend:DI
7196 (subreg:HI
7197 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7198 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7199 (const_int 0)))
7200 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7201 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7202 "@
7203 rldcl. %3,%1,%2,48
7204 rldicl. %3,%1,%H2,48
7205 #
7206 #"
7207 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7208 (set_attr "length" "4,4,8,8")])
7210 (define_split
7211 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7212 (compare:CC (zero_extend:DI
7213 (subreg:HI
7214 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7215 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7216 (const_int 0)))
7217 (clobber (match_scratch:DI 3 ""))]
7218 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7219 [(set (match_dup 3)
7220 (zero_extend:DI (subreg:HI
7221 (rotate:DI (match_dup 1)
7222 (match_dup 2)) 0)))
7223 (set (match_dup 0)
7224 (compare:CC (match_dup 3)
7225 (const_int 0)))]
7226 "")
7228 (define_split
7229 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7230 (compare:CC (zero_extend:DI
7231 (subreg:HI
7232 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7233 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7234 (const_int 0)))
7235 (clobber (match_scratch:DI 3 ""))]
7236 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7237 [(set (match_dup 3)
7238 (zero_extend:DI (subreg:HI
7239 (rotate:DI (match_dup 1)
7240 (match_dup 2)) 6)))
7241 (set (match_dup 0)
7242 (compare:CC (match_dup 3)
7243 (const_int 0)))]
7244 "")
7246 (define_insn "*rotldi3_internal12le"
7247 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7248 (compare:CC (zero_extend:DI
7249 (subreg:HI
7250 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7251 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7252 (const_int 0)))
7253 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7254 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7255 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7256 "@
7257 rldcl. %0,%1,%2,48
7258 rldicl. %0,%1,%H2,48
7259 #
7260 #"
7261 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7262 (set_attr "length" "4,4,8,8")])
7264 (define_insn "*rotldi3_internal12be"
7265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7266 (compare:CC (zero_extend:DI
7267 (subreg:HI
7268 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7269 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7270 (const_int 0)))
7271 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7272 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7273 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7274 "@
7275 rldcl. %0,%1,%2,48
7276 rldicl. %0,%1,%H2,48
7277 #
7278 #"
7279 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7280 (set_attr "length" "4,4,8,8")])
7282 (define_split
7283 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7284 (compare:CC (zero_extend:DI
7285 (subreg:HI
7286 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7287 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7288 (const_int 0)))
7289 (set (match_operand:DI 0 "gpc_reg_operand" "")
7290 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7291 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7292 [(set (match_dup 0)
7293 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7294 (set (match_dup 3)
7295 (compare:CC (match_dup 0)
7296 (const_int 0)))]
7297 "")
7299 (define_split
7300 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7301 (compare:CC (zero_extend:DI
7302 (subreg:HI
7303 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7304 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7305 (const_int 0)))
7306 (set (match_operand:DI 0 "gpc_reg_operand" "")
7307 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7308 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7309 [(set (match_dup 0)
7310 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7311 (set (match_dup 3)
7312 (compare:CC (match_dup 0)
7313 (const_int 0)))]
7314 "")
7316 (define_insn "*rotldi3_internal13le"
7317 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7318 (zero_extend:DI
7319 (subreg:SI
7320 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7321 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7322 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7323 "@
7324 rldcl %0,%1,%2,32
7325 rldicl %0,%1,%H2,32"
7326 [(set_attr "type" "var_shift_rotate,integer")])
7328 (define_insn "*rotldi3_internal13be"
7329 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7330 (zero_extend:DI
7331 (subreg:SI
7332 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7333 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
7334 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7335 "@
7336 rldcl %0,%1,%2,32
7337 rldicl %0,%1,%H2,32"
7338 [(set_attr "type" "var_shift_rotate,integer")])
7340 (define_insn "*rotldi3_internal14le"
7341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7342 (compare:CC (zero_extend:DI
7343 (subreg:SI
7344 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7345 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7346 (const_int 0)))
7347 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7348 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7349 "@
7350 rldcl. %3,%1,%2,32
7351 rldicl. %3,%1,%H2,32
7352 #
7353 #"
7354 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7355 (set_attr "length" "4,4,8,8")])
7357 (define_insn "*rotldi3_internal14be"
7358 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7359 (compare:CC (zero_extend:DI
7360 (subreg:SI
7361 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7362 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7363 (const_int 0)))
7364 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7365 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7366 "@
7367 rldcl. %3,%1,%2,32
7368 rldicl. %3,%1,%H2,32
7369 #
7370 #"
7371 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7372 (set_attr "length" "4,4,8,8")])
7374 (define_split
7375 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7376 (compare:CC (zero_extend:DI
7377 (subreg:SI
7378 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7379 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7380 (const_int 0)))
7381 (clobber (match_scratch:DI 3 ""))]
7382 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7383 [(set (match_dup 3)
7384 (zero_extend:DI (subreg:SI
7385 (rotate:DI (match_dup 1)
7386 (match_dup 2)) 0)))
7387 (set (match_dup 0)
7388 (compare:CC (match_dup 3)
7389 (const_int 0)))]
7390 "")
7392 (define_split
7393 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7394 (compare:CC (zero_extend:DI
7395 (subreg:SI
7396 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7397 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7398 (const_int 0)))
7399 (clobber (match_scratch:DI 3 ""))]
7400 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7401 [(set (match_dup 3)
7402 (zero_extend:DI (subreg:SI
7403 (rotate:DI (match_dup 1)
7404 (match_dup 2)) 4)))
7405 (set (match_dup 0)
7406 (compare:CC (match_dup 3)
7407 (const_int 0)))]
7408 "")
7410 (define_insn "*rotldi3_internal15le"
7411 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7412 (compare:CC (zero_extend:DI
7413 (subreg:SI
7414 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7415 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7416 (const_int 0)))
7417 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7418 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7419 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7420 "@
7421 rldcl. %0,%1,%2,32
7422 rldicl. %0,%1,%H2,32
7423 #
7424 #"
7425 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7426 (set_attr "length" "4,4,8,8")])
7428 (define_insn "*rotldi3_internal15be"
7429 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7430 (compare:CC (zero_extend:DI
7431 (subreg:SI
7432 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7433 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7434 (const_int 0)))
7435 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7436 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7437 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7438 "@
7439 rldcl. %0,%1,%2,32
7440 rldicl. %0,%1,%H2,32
7441 #
7442 #"
7443 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7444 (set_attr "length" "4,4,8,8")])
7446 (define_split
7447 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7448 (compare:CC (zero_extend:DI
7449 (subreg:SI
7450 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7451 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7452 (const_int 0)))
7453 (set (match_operand:DI 0 "gpc_reg_operand" "")
7454 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7455 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7456 [(set (match_dup 0)
7457 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7458 (set (match_dup 3)
7459 (compare:CC (match_dup 0)
7460 (const_int 0)))]
7461 "")
7463 (define_split
7464 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7465 (compare:CC (zero_extend:DI
7466 (subreg:SI
7467 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7468 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7469 (const_int 0)))
7470 (set (match_operand:DI 0 "gpc_reg_operand" "")
7471 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7472 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7473 [(set (match_dup 0)
7474 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7475 (set (match_dup 3)
7476 (compare:CC (match_dup 0)
7477 (const_int 0)))]
7478 "")
7480 (define_expand "ashldi3"
7481 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7482 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7483 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7484 "TARGET_POWERPC64"
7485 "")
7487 (define_insn "*ashldi3_internal1"
7488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7489 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7490 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7491 "TARGET_POWERPC64"
7492 "@
7493 sld %0,%1,%2
7494 sldi %0,%1,%H2"
7495 [(set_attr "type" "var_shift_rotate,shift")])
7497 (define_insn "*ashldi3_internal2"
7498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7499 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7500 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7501 (const_int 0)))
7502 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7503 "TARGET_64BIT"
7504 "@
7505 sld. %3,%1,%2
7506 sldi. %3,%1,%H2
7507 #
7508 #"
7509 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7510 (set_attr "length" "4,4,8,8")])
7512 (define_split
7513 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7514 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7515 (match_operand:SI 2 "reg_or_cint_operand" ""))
7516 (const_int 0)))
7517 (clobber (match_scratch:DI 3 ""))]
7518 "TARGET_POWERPC64 && reload_completed"
7519 [(set (match_dup 3)
7520 (ashift:DI (match_dup 1) (match_dup 2)))
7521 (set (match_dup 0)
7522 (compare:CC (match_dup 3)
7523 (const_int 0)))]
7524 "")
7526 (define_insn "*ashldi3_internal3"
7527 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7528 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7529 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7530 (const_int 0)))
7531 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7532 (ashift:DI (match_dup 1) (match_dup 2)))]
7533 "TARGET_64BIT"
7534 "@
7535 sld. %0,%1,%2
7536 sldi. %0,%1,%H2
7537 #
7538 #"
7539 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7540 (set_attr "length" "4,4,8,8")])
7542 (define_split
7543 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7544 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7545 (match_operand:SI 2 "reg_or_cint_operand" ""))
7546 (const_int 0)))
7547 (set (match_operand:DI 0 "gpc_reg_operand" "")
7548 (ashift:DI (match_dup 1) (match_dup 2)))]
7549 "TARGET_POWERPC64 && reload_completed"
7550 [(set (match_dup 0)
7551 (ashift:DI (match_dup 1) (match_dup 2)))
7552 (set (match_dup 3)
7553 (compare:CC (match_dup 0)
7554 (const_int 0)))]
7555 "")
7557 (define_insn "*ashldi3_internal4"
7558 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7559 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7560 (match_operand:SI 2 "const_int_operand" "i"))
7561 (match_operand:DI 3 "const_int_operand" "n")))]
7562 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7563 "rldic %0,%1,%H2,%W3")
7565 (define_insn "ashldi3_internal5"
7566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7567 (compare:CC
7568 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7569 (match_operand:SI 2 "const_int_operand" "i,i"))
7570 (match_operand:DI 3 "const_int_operand" "n,n"))
7571 (const_int 0)))
7572 (clobber (match_scratch:DI 4 "=r,r"))]
7573 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7574 "@
7575 rldic. %4,%1,%H2,%W3
7576 #"
7577 [(set_attr "type" "compare")
7578 (set_attr "length" "4,8")])
7580 (define_split
7581 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7582 (compare:CC
7583 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7584 (match_operand:SI 2 "const_int_operand" ""))
7585 (match_operand:DI 3 "const_int_operand" ""))
7586 (const_int 0)))
7587 (clobber (match_scratch:DI 4 ""))]
7588 "TARGET_POWERPC64 && reload_completed
7589 && includes_rldic_lshift_p (operands[2], operands[3])"
7590 [(set (match_dup 4)
7591 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7592 (match_dup 3)))
7593 (set (match_dup 0)
7594 (compare:CC (match_dup 4)
7595 (const_int 0)))]
7596 "")
7598 (define_insn "*ashldi3_internal6"
7599 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7600 (compare:CC
7601 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7602 (match_operand:SI 2 "const_int_operand" "i,i"))
7603 (match_operand:DI 3 "const_int_operand" "n,n"))
7604 (const_int 0)))
7605 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7606 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7607 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7608 "@
7609 rldic. %0,%1,%H2,%W3
7610 #"
7611 [(set_attr "type" "compare")
7612 (set_attr "length" "4,8")])
7614 (define_split
7615 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7616 (compare:CC
7617 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7618 (match_operand:SI 2 "const_int_operand" ""))
7619 (match_operand:DI 3 "const_int_operand" ""))
7620 (const_int 0)))
7621 (set (match_operand:DI 0 "gpc_reg_operand" "")
7622 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7623 "TARGET_POWERPC64 && reload_completed
7624 && includes_rldic_lshift_p (operands[2], operands[3])"
7625 [(set (match_dup 0)
7626 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7627 (match_dup 3)))
7628 (set (match_dup 4)
7629 (compare:CC (match_dup 0)
7630 (const_int 0)))]
7631 "")
7633 (define_insn "*ashldi3_internal7"
7634 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7635 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7636 (match_operand:SI 2 "const_int_operand" "i"))
7637 (match_operand:DI 3 "mask64_operand" "n")))]
7638 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7639 "rldicr %0,%1,%H2,%S3")
7641 (define_insn "ashldi3_internal8"
7642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7643 (compare:CC
7644 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7645 (match_operand:SI 2 "const_int_operand" "i,i"))
7646 (match_operand:DI 3 "mask64_operand" "n,n"))
7647 (const_int 0)))
7648 (clobber (match_scratch:DI 4 "=r,r"))]
7649 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7650 "@
7651 rldicr. %4,%1,%H2,%S3
7652 #"
7653 [(set_attr "type" "compare")
7654 (set_attr "length" "4,8")])
7656 (define_split
7657 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7658 (compare:CC
7659 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7660 (match_operand:SI 2 "const_int_operand" ""))
7661 (match_operand:DI 3 "mask64_operand" ""))
7662 (const_int 0)))
7663 (clobber (match_scratch:DI 4 ""))]
7664 "TARGET_POWERPC64 && reload_completed
7665 && includes_rldicr_lshift_p (operands[2], operands[3])"
7666 [(set (match_dup 4)
7667 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7668 (match_dup 3)))
7669 (set (match_dup 0)
7670 (compare:CC (match_dup 4)
7671 (const_int 0)))]
7672 "")
7674 (define_insn "*ashldi3_internal9"
7675 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7676 (compare:CC
7677 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7678 (match_operand:SI 2 "const_int_operand" "i,i"))
7679 (match_operand:DI 3 "mask64_operand" "n,n"))
7680 (const_int 0)))
7681 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7682 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7683 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7684 "@
7685 rldicr. %0,%1,%H2,%S3
7686 #"
7687 [(set_attr "type" "compare")
7688 (set_attr "length" "4,8")])
7690 (define_split
7691 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7692 (compare:CC
7693 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7694 (match_operand:SI 2 "const_int_operand" ""))
7695 (match_operand:DI 3 "mask64_operand" ""))
7696 (const_int 0)))
7697 (set (match_operand:DI 0 "gpc_reg_operand" "")
7698 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7699 "TARGET_POWERPC64 && reload_completed
7700 && includes_rldicr_lshift_p (operands[2], operands[3])"
7701 [(set (match_dup 0)
7702 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7703 (match_dup 3)))
7704 (set (match_dup 4)
7705 (compare:CC (match_dup 0)
7706 (const_int 0)))]
7707 "")
7709 (define_expand "lshrdi3"
7710 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7711 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7712 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7713 "TARGET_POWERPC64"
7714 "")
7716 (define_insn "*lshrdi3_internal1"
7717 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7718 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7719 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7720 "TARGET_POWERPC64"
7721 "@
7722 srd %0,%1,%2
7723 srdi %0,%1,%H2"
7724 [(set_attr "type" "var_shift_rotate,shift")])
7726 (define_insn "*lshrdi3_internal2"
7727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7728 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7729 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7730 (const_int 0)))
7731 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7732 "TARGET_64BIT "
7733 "@
7734 srd. %3,%1,%2
7735 srdi. %3,%1,%H2
7736 #
7737 #"
7738 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7739 (set_attr "length" "4,4,8,8")])
7741 (define_split
7742 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7743 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7744 (match_operand:SI 2 "reg_or_cint_operand" ""))
7745 (const_int 0)))
7746 (clobber (match_scratch:DI 3 ""))]
7747 "TARGET_POWERPC64 && reload_completed"
7748 [(set (match_dup 3)
7749 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7750 (set (match_dup 0)
7751 (compare:CC (match_dup 3)
7752 (const_int 0)))]
7753 "")
7755 (define_insn "*lshrdi3_internal3"
7756 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7757 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7758 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7759 (const_int 0)))
7760 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7761 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7762 "TARGET_64BIT"
7763 "@
7764 srd. %0,%1,%2
7765 srdi. %0,%1,%H2
7766 #
7767 #"
7768 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7769 (set_attr "length" "4,4,8,8")])
7771 (define_split
7772 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7773 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7774 (match_operand:SI 2 "reg_or_cint_operand" ""))
7775 (const_int 0)))
7776 (set (match_operand:DI 0 "gpc_reg_operand" "")
7777 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7778 "TARGET_POWERPC64 && reload_completed"
7779 [(set (match_dup 0)
7780 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7781 (set (match_dup 3)
7782 (compare:CC (match_dup 0)
7783 (const_int 0)))]
7784 "")
7786 (define_expand "ashrdi3"
7787 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7788 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7789 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7790 ""
7791 "
7792 {
7793 if (TARGET_POWERPC64)
7794 ;
7795 else if (GET_CODE (operands[2]) == CONST_INT)
7796 {
7797 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7798 DONE;
7799 }
7800 else
7801 FAIL;
7802 }")
7804 (define_insn "*ashrdi3_internal1"
7805 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7806 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7807 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7808 "TARGET_POWERPC64"
7809 "@
7810 srad %0,%1,%2
7811 sradi %0,%1,%H2"
7812 [(set_attr "type" "var_shift_rotate,shift")])
7814 (define_insn "*ashrdi3_internal2"
7815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7816 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7817 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7818 (const_int 0)))
7819 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7820 "TARGET_64BIT"
7821 "@
7822 srad. %3,%1,%2
7823 sradi. %3,%1,%H2
7824 #
7825 #"
7826 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7827 (set_attr "length" "4,4,8,8")])
7829 (define_split
7830 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7831 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7832 (match_operand:SI 2 "reg_or_cint_operand" ""))
7833 (const_int 0)))
7834 (clobber (match_scratch:DI 3 ""))]
7835 "TARGET_POWERPC64 && reload_completed"
7836 [(set (match_dup 3)
7837 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7838 (set (match_dup 0)
7839 (compare:CC (match_dup 3)
7840 (const_int 0)))]
7841 "")
7843 (define_insn "*ashrdi3_internal3"
7844 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7845 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7846 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7847 (const_int 0)))
7848 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7849 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7850 "TARGET_64BIT"
7851 "@
7852 srad. %0,%1,%2
7853 sradi. %0,%1,%H2
7854 #
7855 #"
7856 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7857 (set_attr "length" "4,4,8,8")])
7859 (define_split
7860 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7861 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7862 (match_operand:SI 2 "reg_or_cint_operand" ""))
7863 (const_int 0)))
7864 (set (match_operand:DI 0 "gpc_reg_operand" "")
7865 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7866 "TARGET_POWERPC64 && reload_completed"
7867 [(set (match_dup 0)
7868 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7869 (set (match_dup 3)
7870 (compare:CC (match_dup 0)
7871 (const_int 0)))]
7872 "")
7874 (define_expand "anddi3"
7875 [(parallel
7876 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7877 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7878 (match_operand:DI 2 "reg_or_cint_operand" "")))
7879 (clobber (match_scratch:CC 3 ""))])]
7880 ""
7881 {
7882 if (!TARGET_POWERPC64)
7883 {
7884 rtx cc = gen_rtx_SCRATCH (CCmode);
7885 rs6000_split_logical (operands, AND, false, false, false, cc);
7886 DONE;
7887 }
7888 else if (!and64_2_operand (operands[2], DImode))
7889 operands[2] = force_reg (DImode, operands[2]);
7890 })
7892 (define_insn "anddi3_mc"
7893 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7894 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7895 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7896 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7897 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7898 "@
7899 and %0,%1,%2
7900 rldic%B2 %0,%1,0,%S2
7901 rlwinm %0,%1,0,%m2,%M2
7902 andi. %0,%1,%b2
7903 andis. %0,%1,%u2
7904 #"
7905 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7906 (set_attr "length" "4,4,4,4,4,8")])
7908 (define_insn "anddi3_nomc"
7909 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7910 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7911 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7912 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7913 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7914 "@
7915 and %0,%1,%2
7916 rldic%B2 %0,%1,0,%S2
7917 rlwinm %0,%1,0,%m2,%M2
7918 #"
7919 [(set_attr "length" "4,4,4,8")])
7921 (define_split
7922 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7923 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7924 (match_operand:DI 2 "mask64_2_operand" "")))
7925 (clobber (match_scratch:CC 3 ""))]
7926 "TARGET_POWERPC64
7927 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7928 && !mask_operand (operands[2], DImode)
7929 && !mask64_operand (operands[2], DImode)"
7930 [(set (match_dup 0)
7931 (and:DI (rotate:DI (match_dup 1)
7932 (match_dup 4))
7933 (match_dup 5)))
7934 (set (match_dup 0)
7935 (and:DI (rotate:DI (match_dup 0)
7936 (match_dup 6))
7937 (match_dup 7)))]
7938 {
7939 build_mask64_2_operands (operands[2], &operands[4]);
7940 })
7942 (define_insn "*anddi3_internal2_mc"
7943 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7944 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7945 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7946 (const_int 0)))
7947 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7948 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7949 "TARGET_64BIT && rs6000_gen_cell_microcode"
7950 "@
7951 and. %3,%1,%2
7952 rldic%B2. %3,%1,0,%S2
7953 rlwinm. %3,%1,0,%m2,%M2
7954 andi. %3,%1,%b2
7955 andis. %3,%1,%u2
7956 #
7957 #
7958 #
7959 #
7960 #
7961 #
7962 #"
7963 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7964 fast_compare,compare,compare,compare,compare,compare,\
7965 compare,compare")
7966 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7968 (define_split
7969 [(set (match_operand:CC 0 "cc_reg_operand" "")
7970 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7971 (match_operand:DI 2 "mask64_2_operand" ""))
7972 (const_int 0)))
7973 (clobber (match_scratch:DI 3 ""))
7974 (clobber (match_scratch:CC 4 ""))]
7975 "TARGET_64BIT && reload_completed
7976 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7977 && !mask_operand (operands[2], DImode)
7978 && !mask64_operand (operands[2], DImode)"
7979 [(set (match_dup 3)
7980 (and:DI (rotate:DI (match_dup 1)
7981 (match_dup 5))
7982 (match_dup 6)))
7983 (parallel [(set (match_dup 0)
7984 (compare:CC (and:DI (rotate:DI (match_dup 3)
7985 (match_dup 7))
7986 (match_dup 8))
7987 (const_int 0)))
7988 (clobber (match_dup 3))])]
7989 "
7990 {
7991 build_mask64_2_operands (operands[2], &operands[5]);
7992 }")
7994 (define_insn "*anddi3_internal3_mc"
7995 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7996 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7997 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7998 (const_int 0)))
7999 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8000 (and:DI (match_dup 1) (match_dup 2)))
8001 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8002 "TARGET_64BIT && rs6000_gen_cell_microcode"
8003 "@
8004 and. %0,%1,%2
8005 rldic%B2. %0,%1,0,%S2
8006 rlwinm. %0,%1,0,%m2,%M2
8007 andi. %0,%1,%b2
8008 andis. %0,%1,%u2
8009 #
8010 #
8011 #
8012 #
8013 #
8014 #
8015 #"
8016 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8017 fast_compare,compare,compare,compare,compare,compare,\
8018 compare,compare")
8019 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8021 (define_split
8022 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8023 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8024 (match_operand:DI 2 "and64_2_operand" ""))
8025 (const_int 0)))
8026 (set (match_operand:DI 0 "gpc_reg_operand" "")
8027 (and:DI (match_dup 1) (match_dup 2)))
8028 (clobber (match_scratch:CC 4 ""))]
8029 "TARGET_64BIT && reload_completed"
8030 [(parallel [(set (match_dup 0)
8031 (and:DI (match_dup 1) (match_dup 2)))
8032 (clobber (match_dup 4))])
8033 (set (match_dup 3)
8034 (compare:CC (match_dup 0)
8035 (const_int 0)))]
8036 "")
8038 (define_split
8039 [(set (match_operand:CC 3 "cc_reg_operand" "")
8040 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8041 (match_operand:DI 2 "mask64_2_operand" ""))
8042 (const_int 0)))
8043 (set (match_operand:DI 0 "gpc_reg_operand" "")
8044 (and:DI (match_dup 1) (match_dup 2)))
8045 (clobber (match_scratch:CC 4 ""))]
8046 "TARGET_64BIT && reload_completed
8047 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8048 && !mask_operand (operands[2], DImode)
8049 && !mask64_operand (operands[2], DImode)"
8050 [(set (match_dup 0)
8051 (and:DI (rotate:DI (match_dup 1)
8052 (match_dup 5))
8053 (match_dup 6)))
8054 (parallel [(set (match_dup 3)
8055 (compare:CC (and:DI (rotate:DI (match_dup 0)
8056 (match_dup 7))
8057 (match_dup 8))
8058 (const_int 0)))
8059 (set (match_dup 0)
8060 (and:DI (rotate:DI (match_dup 0)
8061 (match_dup 7))
8062 (match_dup 8)))])]
8063 "
8064 {
8065 build_mask64_2_operands (operands[2], &operands[5]);
8066 }")
8068 (define_expand "iordi3"
8069 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8070 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8071 (match_operand:DI 2 "reg_or_cint_operand" "")))]
8072 ""
8073 {
8074 if (!TARGET_POWERPC64)
8075 {
8076 rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
8077 DONE;
8078 }
8079 else if (!reg_or_logical_cint_operand (operands[2], DImode))
8080 operands[2] = force_reg (DImode, operands[2]);
8081 else if (non_logical_cint_operand (operands[2], DImode))
8082 {
8083 HOST_WIDE_INT value;
8084 rtx tmp = ((!can_create_pseudo_p ()
8085 || rtx_equal_p (operands[0], operands[1]))
8086 ? operands[0] : gen_reg_rtx (DImode));
8088 value = INTVAL (operands[2]);
8089 emit_insn (gen_iordi3 (tmp, operands[1],
8090 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8092 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8093 DONE;
8094 }
8095 })
8097 (define_expand "xordi3"
8098 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8099 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8100 (match_operand:DI 2 "reg_or_cint_operand" "")))]
8101 ""
8102 {
8103 if (!TARGET_POWERPC64)
8104 {
8105 rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
8106 DONE;
8107 }
8108 else if (!reg_or_logical_cint_operand (operands[2], DImode))
8109 operands[2] = force_reg (DImode, operands[2]);
8110 if (non_logical_cint_operand (operands[2], DImode))
8111 {
8112 HOST_WIDE_INT value;
8113 rtx tmp = ((!can_create_pseudo_p ()
8114 || rtx_equal_p (operands[0], operands[1]))
8115 ? operands[0] : gen_reg_rtx (DImode));
8117 value = INTVAL (operands[2]);
8118 emit_insn (gen_xordi3 (tmp, operands[1],
8119 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8121 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8122 DONE;
8123 }
8124 })
8126 (define_insn "*booldi3_internal1"
8127 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8128 (match_operator:DI 3 "boolean_or_operator"
8129 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8130 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8131 "TARGET_POWERPC64"
8132 "@
8133 %q3 %0,%1,%2
8134 %q3i %0,%1,%b2
8135 %q3is %0,%1,%u2")
8137 (define_insn "*booldi3_internal2"
8138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8139 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8140 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8141 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8142 (const_int 0)))
8143 (clobber (match_scratch:DI 3 "=r,r"))]
8144 "TARGET_64BIT"
8145 "@
8146 %q4. %3,%1,%2
8147 #"
8148 [(set_attr "type" "fast_compare,compare")
8149 (set_attr "length" "4,8")])
8151 (define_split
8152 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8153 (compare:CC (match_operator:DI 4 "boolean_operator"
8154 [(match_operand:DI 1 "gpc_reg_operand" "")
8155 (match_operand:DI 2 "gpc_reg_operand" "")])
8156 (const_int 0)))
8157 (clobber (match_scratch:DI 3 ""))]
8158 "TARGET_POWERPC64 && reload_completed"
8159 [(set (match_dup 3) (match_dup 4))
8160 (set (match_dup 0)
8161 (compare:CC (match_dup 3)
8162 (const_int 0)))]
8163 "")
8165 (define_insn "*booldi3_internal3"
8166 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8167 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8168 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8169 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8170 (const_int 0)))
8171 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8172 (match_dup 4))]
8173 "TARGET_64BIT"
8174 "@
8175 %q4. %0,%1,%2
8176 #"
8177 [(set_attr "type" "fast_compare,compare")
8178 (set_attr "length" "4,8")])
8180 (define_split
8181 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8182 (compare:CC (match_operator:DI 4 "boolean_operator"
8183 [(match_operand:DI 1 "gpc_reg_operand" "")
8184 (match_operand:DI 2 "gpc_reg_operand" "")])
8185 (const_int 0)))
8186 (set (match_operand:DI 0 "gpc_reg_operand" "")
8187 (match_dup 4))]
8188 "TARGET_POWERPC64 && reload_completed"
8189 [(set (match_dup 0) (match_dup 4))
8190 (set (match_dup 3)
8191 (compare:CC (match_dup 0)
8192 (const_int 0)))]
8193 "")
8195 ;; Split a logical operation that we can't do in one insn into two insns,
8196 ;; each of which does one 16-bit part. This is used by combine.
8198 (define_split
8199 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8200 (match_operator:DI 3 "boolean_or_operator"
8201 [(match_operand:DI 1 "gpc_reg_operand" "")
8202 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8203 "TARGET_POWERPC64"
8204 [(set (match_dup 0) (match_dup 4))
8205 (set (match_dup 0) (match_dup 5))]
8206 "
8207 {
8208 rtx i3,i4;
8210 i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
8211 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8212 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8213 operands[1], i3);
8214 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8215 operands[0], i4);
8216 }")
8218 (define_insn "*boolcdi3_internal1"
8219 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8220 (match_operator:DI 3 "boolean_operator"
8221 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8222 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8223 "TARGET_POWERPC64"
8224 "%q3 %0,%2,%1")
8226 (define_insn "*boolcdi3_internal2"
8227 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8228 (compare:CC (match_operator:DI 4 "boolean_operator"
8229 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8230 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8231 (const_int 0)))
8232 (clobber (match_scratch:DI 3 "=r,r"))]
8233 "TARGET_64BIT"
8234 "@
8235 %q4. %3,%2,%1
8236 #"
8237 [(set_attr "type" "fast_compare,compare")
8238 (set_attr "length" "4,8")])
8240 (define_split
8241 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8242 (compare:CC (match_operator:DI 4 "boolean_operator"
8243 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8244 (match_operand:DI 2 "gpc_reg_operand" "")])
8245 (const_int 0)))
8246 (clobber (match_scratch:DI 3 ""))]
8247 "TARGET_POWERPC64 && reload_completed"
8248 [(set (match_dup 3) (match_dup 4))
8249 (set (match_dup 0)
8250 (compare:CC (match_dup 3)
8251 (const_int 0)))]
8252 "")
8254 (define_insn "*boolcdi3_internal3"
8255 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8256 (compare:CC (match_operator:DI 4 "boolean_operator"
8257 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8258 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8259 (const_int 0)))
8260 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8261 (match_dup 4))]
8262 "TARGET_64BIT"
8263 "@
8264 %q4. %0,%2,%1
8265 #"
8266 [(set_attr "type" "fast_compare,compare")
8267 (set_attr "length" "4,8")])
8269 (define_split
8270 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8271 (compare:CC (match_operator:DI 4 "boolean_operator"
8272 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8273 (match_operand:DI 2 "gpc_reg_operand" "")])
8274 (const_int 0)))
8275 (set (match_operand:DI 0 "gpc_reg_operand" "")
8276 (match_dup 4))]
8277 "TARGET_POWERPC64 && reload_completed"
8278 [(set (match_dup 0) (match_dup 4))
8279 (set (match_dup 3)
8280 (compare:CC (match_dup 0)
8281 (const_int 0)))]
8282 "")
8284 (define_insn "*boolccdi3_internal1"
8285 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8286 (match_operator:DI 3 "boolean_operator"
8287 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8288 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8289 "TARGET_POWERPC64"
8290 "%q3 %0,%1,%2")
8292 (define_insn "*boolccdi3_internal2"
8293 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8294 (compare:CC (match_operator:DI 4 "boolean_operator"
8295 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8296 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8297 (const_int 0)))
8298 (clobber (match_scratch:DI 3 "=r,r"))]
8299 "TARGET_64BIT"
8300 "@
8301 %q4. %3,%1,%2
8302 #"
8303 [(set_attr "type" "fast_compare,compare")
8304 (set_attr "length" "4,8")])
8306 (define_split
8307 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8308 (compare:CC (match_operator:DI 4 "boolean_operator"
8309 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8310 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8311 (const_int 0)))
8312 (clobber (match_scratch:DI 3 ""))]
8313 "TARGET_POWERPC64 && reload_completed"
8314 [(set (match_dup 3) (match_dup 4))
8315 (set (match_dup 0)
8316 (compare:CC (match_dup 3)
8317 (const_int 0)))]
8318 "")
8320 (define_insn "*boolccdi3_internal3"
8321 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8322 (compare:CC (match_operator:DI 4 "boolean_operator"
8323 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8324 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8325 (const_int 0)))
8326 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8327 (match_dup 4))]
8328 "TARGET_64BIT"
8329 "@
8330 %q4. %0,%1,%2
8331 #"
8332 [(set_attr "type" "fast_compare,compare")
8333 (set_attr "length" "4,8")])
8335 (define_split
8336 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8337 (compare:CC (match_operator:DI 4 "boolean_operator"
8338 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8339 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8340 (const_int 0)))
8341 (set (match_operand:DI 0 "gpc_reg_operand" "")
8342 (match_dup 4))]
8343 "TARGET_POWERPC64 && reload_completed"
8344 [(set (match_dup 0) (match_dup 4))
8345 (set (match_dup 3)
8346 (compare:CC (match_dup 0)
8347 (const_int 0)))]
8348 "")
8350 ;; Eqv operation.
8351 (define_insn "*eqv<mode>3"
8352 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
8353 (not:GPR
8354 (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
8355 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
8356 ""
8357 "eqv %0,%1,%2"
8358 [(set_attr "type" "integer")
8359 (set_attr "length" "4")])
8361 \f
8362 ;; 128-bit logical operations expanders
8364 (define_expand "and<mode>3"
8365 [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8366 (and:BOOL_128
8367 (match_operand:BOOL_128 1 "vlogical_operand" "")
8368 (match_operand:BOOL_128 2 "vlogical_operand" "")))
8369 (clobber (match_scratch:CC 3 ""))])]
8370 ""
8371 "")
8373 (define_expand "ior<mode>3"
8374 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8375 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8376 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8377 ""
8378 "")
8380 (define_expand "xor<mode>3"
8381 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8382 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8383 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8384 ""
8385 "")
8387 (define_expand "one_cmpl<mode>2"
8388 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8389 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8390 ""
8391 "")
8393 (define_expand "nor<mode>3"
8394 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8395 (and:BOOL_128
8396 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8397 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8398 ""
8399 "")
8401 (define_expand "andc<mode>3"
8402 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8403 (and:BOOL_128
8404 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8405 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8406 ""
8407 "")
8409 ;; Power8 vector logical instructions.
8410 (define_expand "eqv<mode>3"
8411 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8412 (not:BOOL_128
8413 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8414 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8415 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8416 "")
8418 ;; Rewrite nand into canonical form
8419 (define_expand "nand<mode>3"
8420 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8421 (ior:BOOL_128
8422 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8423 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8424 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8425 "")
8427 ;; The canonical form is to have the negated element first, so we need to
8428 ;; reverse arguments.
8429 (define_expand "orc<mode>3"
8430 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8431 (ior:BOOL_128
8432 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8433 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8434 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8435 "")
8437 ;; 128-bit logical operations insns and split operations
8438 (define_insn_and_split "*and<mode>3_internal"
8439 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8440 (and:BOOL_128
8441 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8442 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
8443 (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
8444 ""
8445 {
8446 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8447 return "xxland %x0,%x1,%x2";
8449 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8450 return "vand %0,%1,%2";
8452 return "#";
8453 }
8454 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8455 [(const_int 0)]
8456 {
8457 rs6000_split_logical (operands, AND, false, false, false, operands[3]);
8458 DONE;
8459 }
8460 [(set (attr "type")
8461 (if_then_else
8462 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8463 (const_string "vecsimple")
8464 (const_string "integer")))
8465 (set (attr "length")
8466 (if_then_else
8467 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8468 (const_string "4")
8469 (if_then_else
8470 (match_test "TARGET_POWERPC64")
8471 (const_string "8")
8472 (const_string "16"))))])
8474 ;; 128-bit IOR/XOR
8475 (define_insn_and_split "*bool<mode>3_internal"
8476 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8477 (match_operator:BOOL_128 3 "boolean_or_operator"
8478 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8479 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8480 ""
8481 {
8482 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8483 return "xxl%q3 %x0,%x1,%x2";
8485 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8486 return "v%q3 %0,%1,%2";
8488 return "#";
8489 }
8490 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8491 [(const_int 0)]
8492 {
8493 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
8494 NULL_RTX);
8495 DONE;
8496 }
8497 [(set (attr "type")
8498 (if_then_else
8499 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8500 (const_string "vecsimple")
8501 (const_string "integer")))
8502 (set (attr "length")
8503 (if_then_else
8504 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8505 (const_string "4")
8506 (if_then_else
8507 (match_test "TARGET_POWERPC64")
8508 (const_string "8")
8509 (const_string "16"))))])
8511 ;; 128-bit ANDC/ORC
8512 (define_insn_and_split "*boolc<mode>3_internal1"
8513 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8514 (match_operator:BOOL_128 3 "boolean_operator"
8515 [(not:BOOL_128
8516 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
8517 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8518 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8519 {
8520 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8521 return "xxl%q3 %x0,%x1,%x2";
8523 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8524 return "v%q3 %0,%1,%2";
8526 return "#";
8527 }
8528 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8529 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8530 [(const_int 0)]
8531 {
8532 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8533 NULL_RTX);
8534 DONE;
8535 }
8536 [(set (attr "type")
8537 (if_then_else
8538 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8539 (const_string "vecsimple")
8540 (const_string "integer")))
8541 (set (attr "length")
8542 (if_then_else
8543 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8544 (const_string "4")
8545 (if_then_else
8546 (match_test "TARGET_POWERPC64")
8547 (const_string "8")
8548 (const_string "16"))))])
8550 (define_insn_and_split "*boolc<mode>3_internal2"
8551 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8552 (match_operator:TI2 3 "boolean_operator"
8553 [(not:TI2
8554 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8555 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
8556 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8557 "#"
8558 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8559 [(const_int 0)]
8560 {
8561 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8562 NULL_RTX);
8563 DONE;
8564 }
8565 [(set_attr "type" "integer")
8566 (set (attr "length")
8567 (if_then_else
8568 (match_test "TARGET_POWERPC64")
8569 (const_string "8")
8570 (const_string "16")))])
8572 ;; 128-bit NAND/NOR
8573 (define_insn_and_split "*boolcc<mode>3_internal1"
8574 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8575 (match_operator:BOOL_128 3 "boolean_operator"
8576 [(not:BOOL_128
8577 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
8578 (not:BOOL_128
8579 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
8580 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8581 {
8582 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8583 return "xxl%q3 %x0,%x1,%x2";
8585 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8586 return "v%q3 %0,%1,%2";
8588 return "#";
8589 }
8590 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8591 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8592 [(const_int 0)]
8593 {
8594 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8595 NULL_RTX);
8596 DONE;
8597 }
8598 [(set (attr "type")
8599 (if_then_else
8600 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8601 (const_string "vecsimple")
8602 (const_string "integer")))
8603 (set (attr "length")
8604 (if_then_else
8605 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8606 (const_string "4")
8607 (if_then_else
8608 (match_test "TARGET_POWERPC64")
8609 (const_string "8")
8610 (const_string "16"))))])
8612 (define_insn_and_split "*boolcc<mode>3_internal2"
8613 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8614 (match_operator:TI2 3 "boolean_operator"
8615 [(not:TI2
8616 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8617 (not:TI2
8618 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
8619 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8620 "#"
8621 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8622 [(const_int 0)]
8623 {
8624 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8625 NULL_RTX);
8626 DONE;
8627 }
8628 [(set_attr "type" "integer")
8629 (set (attr "length")
8630 (if_then_else
8631 (match_test "TARGET_POWERPC64")
8632 (const_string "8")
8633 (const_string "16")))])
8636 ;; 128-bit EQV
8637 (define_insn_and_split "*eqv<mode>3_internal1"
8638 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8639 (not:BOOL_128
8640 (xor:BOOL_128
8641 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
8642 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
8643 "TARGET_P8_VECTOR"
8644 {
8645 if (vsx_register_operand (operands[0], <MODE>mode))
8646 return "xxleqv %x0,%x1,%x2";
8648 return "#";
8649 }
8650 "TARGET_P8_VECTOR && reload_completed
8651 && int_reg_operand (operands[0], <MODE>mode)"
8652 [(const_int 0)]
8653 {
8654 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8655 DONE;
8656 }
8657 [(set (attr "type")
8658 (if_then_else
8659 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8660 (const_string "vecsimple")
8661 (const_string "integer")))
8662 (set (attr "length")
8663 (if_then_else
8664 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8665 (const_string "4")
8666 (if_then_else
8667 (match_test "TARGET_POWERPC64")
8668 (const_string "8")
8669 (const_string "16"))))])
8671 (define_insn_and_split "*eqv<mode>3_internal2"
8672 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8673 (not:TI2
8674 (xor:TI2
8675 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
8676 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
8677 "!TARGET_P8_VECTOR"
8678 "#"
8679 "reload_completed && !TARGET_P8_VECTOR"
8680 [(const_int 0)]
8681 {
8682 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8683 DONE;
8684 }
8685 [(set_attr "type" "integer")
8686 (set (attr "length")
8687 (if_then_else
8688 (match_test "TARGET_POWERPC64")
8689 (const_string "8")
8690 (const_string "16")))])
8692 ;; 128-bit one's complement
8693 (define_insn_and_split "*one_cmpl<mode>3_internal"
8694 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8695 (not:BOOL_128
8696 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
8697 ""
8698 {
8699 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8700 return "xxlnor %x0,%x1,%x1";
8702 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8703 return "vnor %0,%1,%1";
8705 return "#";
8706 }
8707 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8708 [(const_int 0)]
8709 {
8710 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
8711 DONE;
8712 }
8713 [(set (attr "type")
8714 (if_then_else
8715 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8716 (const_string "vecsimple")
8717 (const_string "integer")))
8718 (set (attr "length")
8719 (if_then_else
8720 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8721 (const_string "4")
8722 (if_then_else
8723 (match_test "TARGET_POWERPC64")
8724 (const_string "8")
8725 (const_string "16"))))])
8727 \f
8728 ;; Now define ways of moving data around.
8730 ;; Set up a register with a value from the GOT table
8732 (define_expand "movsi_got"
8733 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8734 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8735 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8736 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8737 "
8738 {
8739 if (GET_CODE (operands[1]) == CONST)
8740 {
8741 rtx offset = const0_rtx;
8742 HOST_WIDE_INT value;
8744 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8745 value = INTVAL (offset);
8746 if (value != 0)
8747 {
8748 rtx tmp = (!can_create_pseudo_p ()
8749 ? operands[0]
8750 : gen_reg_rtx (Pmode));
8751 emit_insn (gen_movsi_got (tmp, operands[1]));
8752 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8753 DONE;
8754 }
8755 }
8757 operands[2] = rs6000_got_register (operands[1]);
8758 }")
8760 (define_insn "*movsi_got_internal"
8761 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8762 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8763 (match_operand:SI 2 "gpc_reg_operand" "b")]
8764 UNSPEC_MOVSI_GOT))]
8765 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8766 "lwz %0,%a1@got(%2)"
8767 [(set_attr "type" "load")])
8769 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8770 ;; didn't get allocated to a hard register.
8771 (define_split
8772 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8773 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8774 (match_operand:SI 2 "memory_operand" "")]
8775 UNSPEC_MOVSI_GOT))]
8776 "DEFAULT_ABI == ABI_V4
8777 && flag_pic == 1
8778 && (reload_in_progress || reload_completed)"
8779 [(set (match_dup 0) (match_dup 2))
8780 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8781 UNSPEC_MOVSI_GOT))]
8782 "")
8784 ;; For SI, we special-case integers that can't be loaded in one insn. We
8785 ;; do the load 16-bits at a time. We could do this by loading from memory,
8786 ;; and this is even supposed to be faster, but it is simpler not to get
8787 ;; integers in the TOC.
8788 (define_insn "movsi_low"
8789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8790 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8791 (match_operand 2 "" ""))))]
8792 "TARGET_MACHO && ! TARGET_64BIT"
8793 "lwz %0,lo16(%2)(%1)"
8794 [(set_attr "type" "load")
8795 (set_attr "length" "4")])
8797 (define_insn "*movsi_internal1"
8798 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8799 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8800 "!TARGET_SINGLE_FPU &&
8801 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8802 "@
8803 mr %0,%1
8804 la %0,%a1
8805 lwz%U1%X1 %0,%1
8806 stw%U0%X0 %1,%0
8807 li %0,%1
8808 lis %0,%v1
8809 #
8810 mf%1 %0
8811 mt%0 %1
8812 mt%0 %1
8813 nop"
8814 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
8815 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
8817 (define_insn "*movsi_internal1_single"
8818 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
8819 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
8820 "TARGET_SINGLE_FPU &&
8821 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8822 "@
8823 mr %0,%1
8824 la %0,%a1
8825 lwz%U1%X1 %0,%1
8826 stw%U0%X0 %1,%0
8827 li %0,%1
8828 lis %0,%v1
8829 #
8830 mf%1 %0
8831 mt%0 %1
8832 mt%0 %1
8833 nop
8834 stfs%U0%X0 %1,%0
8835 lfs%U1%X1 %0,%1"
8836 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
8837 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8839 ;; Split a load of a large constant into the appropriate two-insn
8840 ;; sequence.
8842 (define_split
8843 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8844 (match_operand:SI 1 "const_int_operand" ""))]
8845 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8846 && (INTVAL (operands[1]) & 0xffff) != 0"
8847 [(set (match_dup 0)
8848 (match_dup 2))
8849 (set (match_dup 0)
8850 (ior:SI (match_dup 0)
8851 (match_dup 3)))]
8852 "
8853 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8855 if (tem == operands[0])
8856 DONE;
8857 else
8858 FAIL;
8859 }")
8861 (define_insn "*mov<mode>_internal2"
8862 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8863 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8864 (const_int 0)))
8865 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8866 ""
8867 "@
8868 cmp<wd>i %2,%0,0
8869 mr. %0,%1
8870 #"
8871 [(set_attr "type" "cmp,fast_compare,cmp")
8872 (set_attr "length" "4,4,8")])
8874 (define_split
8875 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8876 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8877 (const_int 0)))
8878 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8879 "reload_completed"
8880 [(set (match_dup 0) (match_dup 1))
8881 (set (match_dup 2)
8882 (compare:CC (match_dup 0)
8883 (const_int 0)))]
8884 "")
8885 \f
8886 (define_insn "*movhi_internal"
8887 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8888 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8889 "gpc_reg_operand (operands[0], HImode)
8890 || gpc_reg_operand (operands[1], HImode)"
8891 "@
8892 mr %0,%1
8893 lhz%U1%X1 %0,%1
8894 sth%U0%X0 %1,%0
8895 li %0,%w1
8896 mf%1 %0
8897 mt%0 %1
8898 nop"
8899 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
8901 (define_expand "mov<mode>"
8902 [(set (match_operand:INT 0 "general_operand" "")
8903 (match_operand:INT 1 "any_operand" ""))]
8904 ""
8905 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8907 (define_insn "*movqi_internal"
8908 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8909 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8910 "gpc_reg_operand (operands[0], QImode)
8911 || gpc_reg_operand (operands[1], QImode)"
8912 "@
8913 mr %0,%1
8914 lbz%U1%X1 %0,%1
8915 stb%U0%X0 %1,%0
8916 li %0,%1
8917 mf%1 %0
8918 mt%0 %1
8919 nop"
8920 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
8921 \f
8922 ;; Here is how to move condition codes around. When we store CC data in
8923 ;; an integer register or memory, we store just the high-order 4 bits.
8924 ;; This lets us not shift in the most common case of CR0.
8925 (define_expand "movcc"
8926 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8927 (match_operand:CC 1 "nonimmediate_operand" ""))]
8928 ""
8929 "")
8931 (define_insn "*movcc_internal1"
8932 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
8933 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
8934 "register_operand (operands[0], CCmode)
8935 || register_operand (operands[1], CCmode)"
8936 "@
8937 mcrf %0,%1
8938 mtcrf 128,%1
8939 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
8940 crxor %0,%0,%0
8941 mfcr %0%Q1
8942 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
8943 mr %0,%1
8944 li %0,%1
8945 mf%1 %0
8946 mt%0 %1
8947 lwz%U1%X1 %0,%1
8948 stw%U0%X0 %1,%0"
8949 [(set (attr "type")
8950 (cond [(eq_attr "alternative" "0,3")
8951 (const_string "cr_logical")
8952 (eq_attr "alternative" "1,2")
8953 (const_string "mtcr")
8954 (eq_attr "alternative" "6,7")
8955 (const_string "integer")
8956 (eq_attr "alternative" "8")
8957 (const_string "mfjmpr")
8958 (eq_attr "alternative" "9")
8959 (const_string "mtjmpr")
8960 (eq_attr "alternative" "10")
8961 (const_string "load")
8962 (eq_attr "alternative" "11")
8963 (const_string "store")
8964 (match_test "TARGET_MFCRF")
8965 (const_string "mfcrf")
8966 ]
8967 (const_string "mfcr")))
8968 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
8969 \f
8970 ;; For floating-point, we normally deal with the floating-point registers
8971 ;; unless -msoft-float is used. The sole exception is that parameter passing
8972 ;; can produce floating-point values in fixed-point registers. Unless the
8973 ;; value is a simple constant or already in memory, we deal with this by
8974 ;; allocating memory and copying the value explicitly via that memory location.
8976 ;; Move 32-bit binary/decimal floating point
8977 (define_expand "mov<mode>"
8978 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
8979 (match_operand:FMOVE32 1 "any_operand" ""))]
8980 "<fmove_ok>"
8981 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8983 (define_split
8984 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
8985 (match_operand:FMOVE32 1 "const_double_operand" ""))]
8986 "reload_completed
8987 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8988 || (GET_CODE (operands[0]) == SUBREG
8989 && GET_CODE (SUBREG_REG (operands[0])) == REG
8990 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8991 [(set (match_dup 2) (match_dup 3))]
8992 "
8993 {
8994 long l;
8995 REAL_VALUE_TYPE rv;
8997 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8998 <real_value_to_target> (rv, l);
9000 if (! TARGET_POWERPC64)
9001 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
9002 else
9003 operands[2] = gen_lowpart (SImode, operands[0]);
9005 operands[3] = gen_int_mode (l, SImode);
9006 }")
9008 (define_insn "mov<mode>_hardfloat"
9009 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
9010 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
9011 "(gpc_reg_operand (operands[0], <MODE>mode)
9012 || gpc_reg_operand (operands[1], <MODE>mode))
9013 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9014 "@
9015 mr %0,%1
9016 lwz%U1%X1 %0,%1
9017 stw%U0%X0 %1,%0
9018 fmr %0,%1
9019 xxlor %x0,%x1,%x1
9020 xxlxor %x0,%x0,%x0
9021 <f32_li>
9022 <f32_si>
9023 <f32_lv>
9024 <f32_sv>
9025 mtvsrwz %x0,%1
9026 mfvsrwz %0,%x1
9027 mt%0 %1
9028 mf%1 %0
9029 nop
9030 #
9031 #"
9032 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
9033 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
9035 (define_insn "*mov<mode>_softfloat"
9036 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
9037 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
9038 "(gpc_reg_operand (operands[0], <MODE>mode)
9039 || gpc_reg_operand (operands[1], <MODE>mode))
9040 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9041 "@
9042 mr %0,%1
9043 mt%0 %1
9044 mf%1 %0
9045 lwz%U1%X1 %0,%1
9046 stw%U0%X0 %1,%0
9047 li %0,%1
9048 lis %0,%v1
9049 #
9050 #
9051 nop"
9052 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
9053 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
9055 \f
9056 ;; Move 64-bit binary/decimal floating point
9057 (define_expand "mov<mode>"
9058 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
9059 (match_operand:FMOVE64 1 "any_operand" ""))]
9060 ""
9061 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9063 (define_split
9064 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9065 (match_operand:FMOVE64 1 "const_int_operand" ""))]
9066 "! TARGET_POWERPC64 && reload_completed
9067 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9068 || (GET_CODE (operands[0]) == SUBREG
9069 && GET_CODE (SUBREG_REG (operands[0])) == REG
9070 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9071 [(set (match_dup 2) (match_dup 4))
9072 (set (match_dup 3) (match_dup 1))]
9073 "
9074 {
9075 int endian = (WORDS_BIG_ENDIAN == 0);
9076 HOST_WIDE_INT value = INTVAL (operands[1]);
9078 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
9079 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
9080 operands[4] = GEN_INT (value >> 32);
9081 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9082 }")
9084 (define_split
9085 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9086 (match_operand:FMOVE64 1 "const_double_operand" ""))]
9087 "! TARGET_POWERPC64 && reload_completed
9088 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9089 || (GET_CODE (operands[0]) == SUBREG
9090 && GET_CODE (SUBREG_REG (operands[0])) == REG
9091 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9092 [(set (match_dup 2) (match_dup 4))
9093 (set (match_dup 3) (match_dup 5))]
9094 "
9095 {
9096 int endian = (WORDS_BIG_ENDIAN == 0);
9097 long l[2];
9098 REAL_VALUE_TYPE rv;
9100 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9101 <real_value_to_target> (rv, l);
9103 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
9104 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
9105 operands[4] = gen_int_mode (l[endian], SImode);
9106 operands[5] = gen_int_mode (l[1 - endian], SImode);
9107 }")
9109 (define_split
9110 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9111 (match_operand:FMOVE64 1 "const_double_operand" ""))]
9112 "TARGET_POWERPC64 && reload_completed
9113 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9114 || (GET_CODE (operands[0]) == SUBREG
9115 && GET_CODE (SUBREG_REG (operands[0])) == REG
9116 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9117 [(set (match_dup 2) (match_dup 3))]
9118 "
9119 {
9120 int endian = (WORDS_BIG_ENDIAN == 0);
9121 long l[2];
9122 REAL_VALUE_TYPE rv;
9123 HOST_WIDE_INT val;
9125 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9126 <real_value_to_target> (rv, l);
9128 operands[2] = gen_lowpart (DImode, operands[0]);
9129 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9130 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9131 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9133 operands[3] = gen_int_mode (val, DImode);
9134 }")
9136 ;; Don't have reload use general registers to load a constant. It is
9137 ;; less efficient than loading the constant into an FP register, since
9138 ;; it will probably be used there.
9140 ;; The move constraints are ordered to prefer floating point registers before
9141 ;; general purpose registers to avoid doing a store and a load to get the value
9142 ;; into a floating point register when it is needed for a floating point
9143 ;; operation. Prefer traditional floating point registers over VSX registers,
9144 ;; since the D-form version of the memory instructions does not need a GPR for
9145 ;; reloading.
9147 (define_insn "*mov<mode>_hardfloat32"
9148 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
9149 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
9150 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9151 && (gpc_reg_operand (operands[0], <MODE>mode)
9152 || gpc_reg_operand (operands[1], <MODE>mode))"
9153 "@
9154 stfd%U0%X0 %1,%0
9155 lfd%U1%X1 %0,%1
9156 fmr %0,%1
9157 lxsd%U1x %x0,%y1
9158 stxsd%U0x %x1,%y0
9159 xxlor %x0,%x1,%x1
9160 xxlxor %x0,%x0,%x0
9161 #
9162 #
9163 #
9164 #
9165 #
9166 #"
9167 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
9168 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
9170 (define_insn "*mov<mode>_softfloat32"
9171 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
9172 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
9173 "! TARGET_POWERPC64
9174 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9175 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
9176 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
9177 && (gpc_reg_operand (operands[0], <MODE>mode)
9178 || gpc_reg_operand (operands[1], <MODE>mode))"
9179 "#"
9180 [(set_attr "type" "store,load,two,*,*,*")
9181 (set_attr "length" "8,8,8,8,12,16")])
9183 ; ld/std require word-aligned displacements -> 'Y' constraint.
9184 ; List Y->r and r->Y before r->r for reload.
9185 (define_insn "*mov<mode>_hardfloat64"
9186 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
9187 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
9188 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9189 && (gpc_reg_operand (operands[0], <MODE>mode)
9190 || gpc_reg_operand (operands[1], <MODE>mode))"
9191 "@
9192 stfd%U0%X0 %1,%0
9193 lfd%U1%X1 %0,%1
9194 fmr %0,%1
9195 lxsd%U1x %x0,%y1
9196 stxsd%U0x %x1,%y0
9197 xxlor %x0,%x1,%x1
9198 xxlxor %x0,%x0,%x0
9199 std%U0%X0 %1,%0
9200 ld%U1%X1 %0,%1
9201 mr %0,%1
9202 mt%0 %1
9203 mf%1 %0
9204 nop
9205 #
9206 #
9207 #
9208 mftgpr %0,%1
9209 mffgpr %0,%1
9210 mfvsrd %0,%x1
9211 mtvsrd %x0,%1"
9212 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
9213 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
9215 (define_insn "*mov<mode>_softfloat64"
9216 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
9217 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
9218 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9219 && (gpc_reg_operand (operands[0], <MODE>mode)
9220 || gpc_reg_operand (operands[1], <MODE>mode))"
9221 "@
9222 std%U0%X0 %1,%0
9223 ld%U1%X1 %0,%1
9224 mr %0,%1
9225 mt%0 %1
9226 mf%1 %0
9227 #
9228 #
9229 #
9230 nop"
9231 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
9232 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9233 \f
9234 (define_expand "mov<mode>"
9235 [(set (match_operand:FMOVE128 0 "general_operand" "")
9236 (match_operand:FMOVE128 1 "any_operand" ""))]
9237 ""
9238 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9240 ;; It's important to list Y->r and r->Y before r->r because otherwise
9241 ;; reload, given m->r, will try to pick r->r and reload it, which
9242 ;; doesn't make progress.
9244 ;; We can't split little endian direct moves of TDmode, because the words are
9245 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
9246 ;; problematical. Don't allow direct move for this case.
9248 (define_insn_and_split "*mov<mode>_64bit_dm"
9249 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
9250 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
9251 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
9252 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
9253 && (gpc_reg_operand (operands[0], <MODE>mode)
9254 || gpc_reg_operand (operands[1], <MODE>mode))"
9255 "#"
9256 "&& reload_completed"
9257 [(pc)]
9258 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9259 [(set_attr "length" "8,8,8,12,12,8,8,8")])
9261 (define_insn_and_split "*movtd_64bit_nodm"
9262 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9263 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
9264 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
9265 && (gpc_reg_operand (operands[0], TDmode)
9266 || gpc_reg_operand (operands[1], TDmode))"
9267 "#"
9268 "&& reload_completed"
9269 [(pc)]
9270 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9271 [(set_attr "length" "8,8,8,12,12,8")])
9273 (define_insn_and_split "*mov<mode>_32bit"
9274 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9275 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
9276 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
9277 && (gpc_reg_operand (operands[0], <MODE>mode)
9278 || gpc_reg_operand (operands[1], <MODE>mode))"
9279 "#"
9280 "&& reload_completed"
9281 [(pc)]
9282 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9283 [(set_attr "length" "8,8,8,20,20,16")])
9285 (define_insn_and_split "*mov<mode>_softfloat"
9286 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9287 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
9288 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
9289 && (gpc_reg_operand (operands[0], <MODE>mode)
9290 || gpc_reg_operand (operands[1], <MODE>mode))"
9291 "#"
9292 "&& reload_completed"
9293 [(pc)]
9294 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9295 [(set_attr "length" "20,20,16")])
9297 (define_expand "extenddftf2"
9298 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9299 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9300 "!TARGET_IEEEQUAD
9301 && TARGET_HARD_FLOAT
9302 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9303 && TARGET_LONG_DOUBLE_128"
9304 {
9305 if (TARGET_E500_DOUBLE)
9306 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9307 else
9308 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9309 DONE;
9310 })
9312 (define_expand "extenddftf2_fprs"
9313 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9314 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9315 (use (match_dup 2))])]
9316 "!TARGET_IEEEQUAD
9317 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9318 && TARGET_LONG_DOUBLE_128"
9319 {
9320 operands[2] = CONST0_RTX (DFmode);
9321 /* Generate GOT reference early for SVR4 PIC. */
9322 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9323 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9324 })
9326 (define_insn_and_split "*extenddftf2_internal"
9327 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9328 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9329 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9330 "!TARGET_IEEEQUAD
9331 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9332 && TARGET_LONG_DOUBLE_128"
9333 "#"
9334 "&& reload_completed"
9335 [(pc)]
9336 {
9337 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9338 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9339 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9340 operands[1]);
9341 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9342 operands[2]);
9343 DONE;
9344 })
9346 (define_expand "extendsftf2"
9347 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9348 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9349 "!TARGET_IEEEQUAD
9350 && TARGET_HARD_FLOAT
9351 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9352 && TARGET_LONG_DOUBLE_128"
9353 {
9354 rtx tmp = gen_reg_rtx (DFmode);
9355 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9356 emit_insn (gen_extenddftf2 (operands[0], tmp));
9357 DONE;
9358 })
9360 (define_expand "trunctfdf2"
9361 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9362 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9363 "!TARGET_IEEEQUAD
9364 && TARGET_HARD_FLOAT
9365 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9366 && TARGET_LONG_DOUBLE_128"
9367 "")
9369 (define_insn_and_split "trunctfdf2_internal1"
9370 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9371 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9372 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9373 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9374 "@
9375 #
9376 fmr %0,%1"
9377 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9378 [(const_int 0)]
9379 {
9380 emit_note (NOTE_INSN_DELETED);
9381 DONE;
9382 }
9383 [(set_attr "type" "fp")])
9385 (define_insn "trunctfdf2_internal2"
9386 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9387 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9388 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9389 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9390 && TARGET_LONG_DOUBLE_128"
9391 "fadd %0,%1,%L1"
9392 [(set_attr "type" "fp")
9393 (set_attr "fp_type" "fp_addsub_d")])
9395 (define_expand "trunctfsf2"
9396 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9397 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9398 "!TARGET_IEEEQUAD
9399 && TARGET_HARD_FLOAT
9400 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9401 && TARGET_LONG_DOUBLE_128"
9402 {
9403 if (TARGET_E500_DOUBLE)
9404 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9405 else
9406 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9407 DONE;
9408 })
9410 (define_insn_and_split "trunctfsf2_fprs"
9411 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9412 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9413 (clobber (match_scratch:DF 2 "=d"))]
9414 "!TARGET_IEEEQUAD
9415 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9416 && TARGET_LONG_DOUBLE_128"
9417 "#"
9418 "&& reload_completed"
9419 [(set (match_dup 2)
9420 (float_truncate:DF (match_dup 1)))
9421 (set (match_dup 0)
9422 (float_truncate:SF (match_dup 2)))]
9423 "")
9425 (define_expand "floatsitf2"
9426 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9427 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9428 "!TARGET_IEEEQUAD
9429 && TARGET_HARD_FLOAT
9430 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9431 && TARGET_LONG_DOUBLE_128"
9432 {
9433 rtx tmp = gen_reg_rtx (DFmode);
9434 expand_float (tmp, operands[1], false);
9435 emit_insn (gen_extenddftf2 (operands[0], tmp));
9436 DONE;
9437 })
9439 ; fadd, but rounding towards zero.
9440 ; This is probably not the optimal code sequence.
9441 (define_insn "fix_trunc_helper"
9442 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9443 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9444 UNSPEC_FIX_TRUNC_TF))
9445 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9446 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9447 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9448 [(set_attr "type" "fp")
9449 (set_attr "length" "20")])
9451 (define_expand "fix_trunctfsi2"
9452 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9453 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9454 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9455 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9456 {
9457 if (TARGET_E500_DOUBLE)
9458 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9459 else
9460 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9461 DONE;
9462 })
9464 (define_expand "fix_trunctfsi2_fprs"
9465 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9466 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9467 (clobber (match_dup 2))
9468 (clobber (match_dup 3))
9469 (clobber (match_dup 4))
9470 (clobber (match_dup 5))])]
9471 "!TARGET_IEEEQUAD
9472 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9473 {
9474 operands[2] = gen_reg_rtx (DFmode);
9475 operands[3] = gen_reg_rtx (DFmode);
9476 operands[4] = gen_reg_rtx (DImode);
9477 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9478 })
9480 (define_insn_and_split "*fix_trunctfsi2_internal"
9481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9482 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9483 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9484 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9485 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9486 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9487 "!TARGET_IEEEQUAD
9488 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9489 "#"
9490 ""
9491 [(pc)]
9492 {
9493 rtx lowword;
9494 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9496 gcc_assert (MEM_P (operands[5]));
9497 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9499 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9500 emit_move_insn (operands[5], operands[4]);
9501 emit_move_insn (operands[0], lowword);
9502 DONE;
9503 })
9505 (define_expand "negtf2"
9506 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9507 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9508 "!TARGET_IEEEQUAD
9509 && TARGET_HARD_FLOAT
9510 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9511 && TARGET_LONG_DOUBLE_128"
9512 "")
9514 (define_insn "negtf2_internal"
9515 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9516 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9517 "!TARGET_IEEEQUAD
9518 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9519 "*
9520 {
9521 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9522 return \"fneg %L0,%L1\;fneg %0,%1\";
9523 else
9524 return \"fneg %0,%1\;fneg %L0,%L1\";
9525 }"
9526 [(set_attr "type" "fp")
9527 (set_attr "length" "8")])
9529 (define_expand "abstf2"
9530 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9531 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9532 "!TARGET_IEEEQUAD
9533 && TARGET_HARD_FLOAT
9534 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9535 && TARGET_LONG_DOUBLE_128"
9536 "
9537 {
9538 rtx label = gen_label_rtx ();
9539 if (TARGET_E500_DOUBLE)
9540 {
9541 if (flag_finite_math_only && !flag_trapping_math)
9542 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9543 else
9544 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9545 }
9546 else
9547 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9548 emit_label (label);
9549 DONE;
9550 }")
9552 (define_expand "abstf2_internal"
9553 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9554 (match_operand:TF 1 "gpc_reg_operand" ""))
9555 (set (match_dup 3) (match_dup 5))
9556 (set (match_dup 5) (abs:DF (match_dup 5)))
9557 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9558 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9559 (label_ref (match_operand 2 "" ""))
9560 (pc)))
9561 (set (match_dup 6) (neg:DF (match_dup 6)))]
9562 "!TARGET_IEEEQUAD
9563 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9564 && TARGET_LONG_DOUBLE_128"
9565 "
9566 {
9567 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9568 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9569 operands[3] = gen_reg_rtx (DFmode);
9570 operands[4] = gen_reg_rtx (CCFPmode);
9571 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9572 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9573 }")
9574 \f
9575 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9576 ;; must have 3 arguments, and scratch register constraint must be a single
9577 ;; constraint.
9579 ;; Reload patterns to support gpr load/store with misaligned mem.
9580 ;; and multiple gpr load/store at offset >= 0xfffc
9581 (define_expand "reload_<mode>_store"
9582 [(parallel [(match_operand 0 "memory_operand" "=m")
9583 (match_operand 1 "gpc_reg_operand" "r")
9584 (match_operand:GPR 2 "register_operand" "=&b")])]
9585 ""
9586 {
9587 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9588 DONE;
9589 })
9591 (define_expand "reload_<mode>_load"
9592 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9593 (match_operand 1 "memory_operand" "m")
9594 (match_operand:GPR 2 "register_operand" "=b")])]
9595 ""
9596 {
9597 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9598 DONE;
9599 })
9601 \f
9602 ;; Power8 merge instructions to allow direct move to/from floating point
9603 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
9604 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
9605 ;; value, since it is allocated in reload and not all of the flow information
9606 ;; is setup for it. We have two patterns to do the two moves between gprs and
9607 ;; fprs. There isn't a dependancy between the two, but we could potentially
9608 ;; schedule other instructions between the two instructions. TFmode is
9609 ;; currently limited to traditional FPR registers. If/when this is changed, we
9610 ;; will need to revist %L to make sure it works with VSX registers, or add an
9611 ;; %x version of %L.
9613 (define_insn "p8_fmrgow_<mode>"
9614 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
9615 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
9616 UNSPEC_P8V_FMRGOW))]
9617 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9618 "fmrgow %0,%1,%L1"
9619 [(set_attr "type" "vecperm")])
9621 (define_insn "p8_mtvsrwz_1"
9622 [(set (match_operand:TF 0 "register_operand" "=d")
9623 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
9624 UNSPEC_P8V_MTVSRWZ))]
9625 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9626 "mtvsrwz %x0,%1"
9627 [(set_attr "type" "mftgpr")])
9629 (define_insn "p8_mtvsrwz_2"
9630 [(set (match_operand:TF 0 "register_operand" "+d")
9631 (unspec:TF [(match_dup 0)
9632 (match_operand:SI 1 "register_operand" "r")]
9633 UNSPEC_P8V_MTVSRWZ))]
9634 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9635 "mtvsrwz %L0,%1"
9636 [(set_attr "type" "mftgpr")])
9638 (define_insn_and_split "reload_fpr_from_gpr<mode>"
9639 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
9640 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
9641 UNSPEC_P8V_RELOAD_FROM_GPR))
9642 (clobber (match_operand:TF 2 "register_operand" "=d"))]
9643 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9644 "#"
9645 "&& reload_completed"
9646 [(const_int 0)]
9647 {
9648 rtx dest = operands[0];
9649 rtx src = operands[1];
9650 rtx tmp = operands[2];
9651 rtx gpr_hi_reg = gen_highpart (SImode, src);
9652 rtx gpr_lo_reg = gen_lowpart (SImode, src);
9654 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
9655 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
9656 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
9657 DONE;
9658 }
9659 [(set_attr "length" "12")
9660 (set_attr "type" "three")])
9662 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
9663 (define_insn "p8_mtvsrd_1"
9664 [(set (match_operand:TF 0 "register_operand" "=ws")
9665 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
9666 UNSPEC_P8V_MTVSRD))]
9667 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9668 "mtvsrd %0,%1"
9669 [(set_attr "type" "mftgpr")])
9671 (define_insn "p8_mtvsrd_2"
9672 [(set (match_operand:TF 0 "register_operand" "+ws")
9673 (unspec:TF [(match_dup 0)
9674 (match_operand:DI 1 "register_operand" "r")]
9675 UNSPEC_P8V_MTVSRD))]
9676 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9677 "mtvsrd %L0,%1"
9678 [(set_attr "type" "mftgpr")])
9680 (define_insn "p8_xxpermdi_<mode>"
9681 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9682 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
9683 UNSPEC_P8V_XXPERMDI))]
9684 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9685 "xxpermdi %x0,%1,%L1,0"
9686 [(set_attr "type" "vecperm")])
9688 (define_insn_and_split "reload_vsx_from_gpr<mode>"
9689 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9690 (unspec:FMOVE128_GPR
9691 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
9692 UNSPEC_P8V_RELOAD_FROM_GPR))
9693 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
9694 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9695 "#"
9696 "&& reload_completed"
9697 [(const_int 0)]
9698 {
9699 rtx dest = operands[0];
9700 rtx src = operands[1];
9701 rtx tmp = operands[2];
9702 rtx gpr_hi_reg = gen_highpart (DImode, src);
9703 rtx gpr_lo_reg = gen_lowpart (DImode, src);
9705 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
9706 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
9707 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
9708 }
9709 [(set_attr "length" "12")
9710 (set_attr "type" "three")])
9712 (define_split
9713 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
9714 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
9715 "reload_completed
9716 && (int_reg_operand (operands[0], <MODE>mode)
9717 || int_reg_operand (operands[1], <MODE>mode))"
9718 [(pc)]
9719 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9721 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
9722 ;; type is stored internally as double precision in the VSX registers, we have
9723 ;; to convert it from the vector format.
9725 (define_insn_and_split "reload_vsx_from_gprsf"
9726 [(set (match_operand:SF 0 "register_operand" "=wa")
9727 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
9728 UNSPEC_P8V_RELOAD_FROM_GPR))
9729 (clobber (match_operand:DI 2 "register_operand" "=r"))]
9730 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9731 "#"
9732 "&& reload_completed"
9733 [(const_int 0)]
9734 {
9735 rtx op0 = operands[0];
9736 rtx op1 = operands[1];
9737 rtx op2 = operands[2];
9738 /* Also use the destination register to hold the unconverted DImode value.
9739 This is conceptually a separate value from OP0, so we use gen_rtx_REG
9740 rather than simplify_gen_subreg. */
9741 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
9742 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
9744 /* Move SF value to upper 32-bits for xscvspdpn. */
9745 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
9746 emit_move_insn (op0_di, op2);
9747 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
9748 DONE;
9749 }
9750 [(set_attr "length" "8")
9751 (set_attr "type" "two")])
9753 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
9754 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
9755 ;; and then doing a move of that.
9756 (define_insn "p8_mfvsrd_3_<mode>"
9757 [(set (match_operand:DF 0 "register_operand" "=r")
9758 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9759 UNSPEC_P8V_RELOAD_FROM_VSX))]
9760 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9761 "mfvsrd %0,%x1"
9762 [(set_attr "type" "mftgpr")])
9764 (define_insn_and_split "reload_gpr_from_vsx<mode>"
9765 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
9766 (unspec:FMOVE128_GPR
9767 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9768 UNSPEC_P8V_RELOAD_FROM_VSX))
9769 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
9770 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9771 "#"
9772 "&& reload_completed"
9773 [(const_int 0)]
9774 {
9775 rtx dest = operands[0];
9776 rtx src = operands[1];
9777 rtx tmp = operands[2];
9778 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
9779 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
9781 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
9782 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
9783 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
9784 }
9785 [(set_attr "length" "12")
9786 (set_attr "type" "three")])
9788 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
9789 ;; type is stored internally as double precision, we have to convert it to the
9790 ;; vector format.
9792 (define_insn_and_split "reload_gpr_from_vsxsf"
9793 [(set (match_operand:SF 0 "register_operand" "=r")
9794 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
9795 UNSPEC_P8V_RELOAD_FROM_VSX))
9796 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
9797 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9798 "#"
9799 "&& reload_completed"
9800 [(const_int 0)]
9801 {
9802 rtx op0 = operands[0];
9803 rtx op1 = operands[1];
9804 rtx op2 = operands[2];
9805 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
9807 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
9808 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
9809 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
9810 DONE;
9811 }
9812 [(set_attr "length" "12")
9813 (set_attr "type" "three")])
9815 (define_insn "p8_mfvsrd_4_disf"
9816 [(set (match_operand:DI 0 "register_operand" "=r")
9817 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
9818 UNSPEC_P8V_RELOAD_FROM_VSX))]
9819 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9820 "mfvsrd %0,%x1"
9821 [(set_attr "type" "mftgpr")])
9823 \f
9824 ;; Next come the multi-word integer load and store and the load and store
9825 ;; multiple insns.
9827 ;; List r->r after r->Y, otherwise reload will try to reload a
9828 ;; non-offsettable address by using r->r which won't make progress.
9829 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
9830 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
9831 (define_insn "*movdi_internal32"
9832 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
9833 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
9834 "! TARGET_POWERPC64
9835 && (gpc_reg_operand (operands[0], DImode)
9836 || gpc_reg_operand (operands[1], DImode))"
9837 "@
9838 #
9839 #
9840 #
9841 stfd%U0%X0 %1,%0
9842 lfd%U1%X1 %0,%1
9843 fmr %0,%1
9844 #"
9845 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
9847 (define_split
9848 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9849 (match_operand:DI 1 "const_int_operand" ""))]
9850 "! TARGET_POWERPC64 && reload_completed
9851 && gpr_or_gpr_p (operands[0], operands[1])
9852 && !direct_move_p (operands[0], operands[1])"
9853 [(set (match_dup 2) (match_dup 4))
9854 (set (match_dup 3) (match_dup 1))]
9855 "
9856 {
9857 HOST_WIDE_INT value = INTVAL (operands[1]);
9858 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9859 DImode);
9860 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9861 DImode);
9862 operands[4] = GEN_INT (value >> 32);
9863 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9864 }")
9866 (define_split
9867 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9868 (match_operand:DIFD 1 "input_operand" ""))]
9869 "reload_completed && !TARGET_POWERPC64
9870 && gpr_or_gpr_p (operands[0], operands[1])
9871 && !direct_move_p (operands[0], operands[1])"
9872 [(pc)]
9873 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9875 (define_insn "*movdi_internal64"
9876 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
9877 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
9878 "TARGET_POWERPC64
9879 && (gpc_reg_operand (operands[0], DImode)
9880 || gpc_reg_operand (operands[1], DImode))"
9881 "@
9882 std%U0%X0 %1,%0
9883 ld%U1%X1 %0,%1
9884 mr %0,%1
9885 li %0,%1
9886 lis %0,%v1
9887 #
9888 stfd%U0%X0 %1,%0
9889 lfd%U1%X1 %0,%1
9890 fmr %0,%1
9891 mf%1 %0
9892 mt%0 %1
9893 nop
9894 mftgpr %0,%1
9895 mffgpr %0,%1
9896 mfvsrd %0,%x1
9897 mtvsrd %x0,%1"
9898 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
9899 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
9901 ;; Generate all one-bits and clear left or right.
9902 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9903 (define_split
9904 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9905 (match_operand:DI 1 "mask64_operand" ""))]
9906 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9907 [(set (match_dup 0) (const_int -1))
9908 (set (match_dup 0)
9909 (and:DI (rotate:DI (match_dup 0)
9910 (const_int 0))
9911 (match_dup 1)))]
9912 "")
9914 ;; Split a load of a large constant into the appropriate five-instruction
9915 ;; sequence. Handle anything in a constant number of insns.
9916 ;; When non-easy constants can go in the TOC, this should use
9917 ;; easy_fp_constant predicate.
9918 (define_split
9919 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9920 (match_operand:DI 1 "const_int_operand" ""))]
9921 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9922 [(set (match_dup 0) (match_dup 2))
9923 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9924 "
9925 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9927 if (tem == operands[0])
9928 DONE;
9929 else
9930 FAIL;
9931 }")
9933 (define_split
9934 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9935 (match_operand:DI 1 "const_scalar_int_operand" ""))]
9936 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9937 [(set (match_dup 0) (match_dup 2))
9938 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9939 "
9940 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9942 if (tem == operands[0])
9943 DONE;
9944 else
9945 FAIL;
9946 }")
9947 \f
9948 ;; TImode/PTImode is similar, except that we usually want to compute the
9949 ;; address into a register and use lsi/stsi (the exception is during reload).
9951 (define_insn "*mov<mode>_string"
9952 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
9953 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
9954 "! TARGET_POWERPC64
9955 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9956 && (gpc_reg_operand (operands[0], <MODE>mode)
9957 || gpc_reg_operand (operands[1], <MODE>mode))"
9958 "*
9959 {
9960 switch (which_alternative)
9961 {
9962 default:
9963 gcc_unreachable ();
9964 case 0:
9965 if (TARGET_STRING)
9966 return \"stswi %1,%P0,16\";
9967 case 1:
9968 return \"#\";
9969 case 2:
9970 /* If the address is not used in the output, we can use lsi. Otherwise,
9971 fall through to generating four loads. */
9972 if (TARGET_STRING
9973 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9974 return \"lswi %0,%P1,16\";
9975 /* ... fall through ... */
9976 case 3:
9977 case 4:
9978 case 5:
9979 return \"#\";
9980 }
9981 }"
9982 [(set_attr "type" "store,store,load,load,*,*")
9983 (set_attr "update" "yes")
9984 (set_attr "indexed" "yes")
9985 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
9986 (const_string "always")
9987 (const_string "conditional")))])
9989 (define_insn "*mov<mode>_ppc64"
9990 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
9991 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
9992 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
9993 && (gpc_reg_operand (operands[0], <MODE>mode)
9994 || gpc_reg_operand (operands[1], <MODE>mode)))"
9995 {
9996 return rs6000_output_move_128bit (operands);
9997 }
9998 [(set_attr "type" "store,store,load,load,*,*")
9999 (set_attr "length" "8")])
10001 (define_split
10002 [(set (match_operand:TI2 0 "int_reg_operand" "")
10003 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
10004 "TARGET_POWERPC64
10005 && (VECTOR_MEM_NONE_P (<MODE>mode)
10006 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
10007 [(set (match_dup 2) (match_dup 4))
10008 (set (match_dup 3) (match_dup 5))]
10009 "
10010 {
10011 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10012 <MODE>mode);
10013 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10014 <MODE>mode);
10015 if (CONST_WIDE_INT_P (operands[1]))
10016 {
10017 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
10018 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
10019 }
10020 else if (CONST_INT_P (operands[1]))
10021 {
10022 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10023 operands[5] = operands[1];
10024 }
10025 else
10026 FAIL;
10027 }")
10029 (define_split
10030 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
10031 (match_operand:TI2 1 "input_operand" ""))]
10032 "reload_completed
10033 && gpr_or_gpr_p (operands[0], operands[1])
10034 && !direct_move_p (operands[0], operands[1])
10035 && !quad_load_store_p (operands[0], operands[1])"
10036 [(pc)]
10037 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10038 \f
10039 (define_expand "load_multiple"
10040 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10041 (match_operand:SI 1 "" ""))
10042 (use (match_operand:SI 2 "" ""))])]
10043 "TARGET_STRING && !TARGET_POWERPC64"
10044 "
10045 {
10046 int regno;
10047 int count;
10048 rtx op1;
10049 int i;
10051 /* Support only loading a constant number of fixed-point registers from
10052 memory and only bother with this if more than two; the machine
10053 doesn't support more than eight. */
10054 if (GET_CODE (operands[2]) != CONST_INT
10055 || INTVAL (operands[2]) <= 2
10056 || INTVAL (operands[2]) > 8
10057 || GET_CODE (operands[1]) != MEM
10058 || GET_CODE (operands[0]) != REG
10059 || REGNO (operands[0]) >= 32)
10060 FAIL;
10062 count = INTVAL (operands[2]);
10063 regno = REGNO (operands[0]);
10065 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10066 op1 = replace_equiv_address (operands[1],
10067 force_reg (SImode, XEXP (operands[1], 0)));
10069 for (i = 0; i < count; i++)
10070 XVECEXP (operands[3], 0, i)
10071 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10072 adjust_address_nv (op1, SImode, i * 4));
10073 }")
10075 (define_insn "*ldmsi8"
10076 [(match_parallel 0 "load_multiple_operation"
10077 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10078 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10079 (set (match_operand:SI 3 "gpc_reg_operand" "")
10080 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10081 (set (match_operand:SI 4 "gpc_reg_operand" "")
10082 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10083 (set (match_operand:SI 5 "gpc_reg_operand" "")
10084 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10085 (set (match_operand:SI 6 "gpc_reg_operand" "")
10086 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10087 (set (match_operand:SI 7 "gpc_reg_operand" "")
10088 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10089 (set (match_operand:SI 8 "gpc_reg_operand" "")
10090 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10091 (set (match_operand:SI 9 "gpc_reg_operand" "")
10092 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10093 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10094 "*
10095 { return rs6000_output_load_multiple (operands); }"
10096 [(set_attr "type" "load")
10097 (set_attr "update" "yes")
10098 (set_attr "indexed" "yes")
10099 (set_attr "length" "32")])
10101 (define_insn "*ldmsi7"
10102 [(match_parallel 0 "load_multiple_operation"
10103 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10104 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10105 (set (match_operand:SI 3 "gpc_reg_operand" "")
10106 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10107 (set (match_operand:SI 4 "gpc_reg_operand" "")
10108 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10109 (set (match_operand:SI 5 "gpc_reg_operand" "")
10110 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10111 (set (match_operand:SI 6 "gpc_reg_operand" "")
10112 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10113 (set (match_operand:SI 7 "gpc_reg_operand" "")
10114 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10115 (set (match_operand:SI 8 "gpc_reg_operand" "")
10116 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10117 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10118 "*
10119 { return rs6000_output_load_multiple (operands); }"
10120 [(set_attr "type" "load")
10121 (set_attr "update" "yes")
10122 (set_attr "indexed" "yes")
10123 (set_attr "length" "32")])
10125 (define_insn "*ldmsi6"
10126 [(match_parallel 0 "load_multiple_operation"
10127 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10128 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10129 (set (match_operand:SI 3 "gpc_reg_operand" "")
10130 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10131 (set (match_operand:SI 4 "gpc_reg_operand" "")
10132 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10133 (set (match_operand:SI 5 "gpc_reg_operand" "")
10134 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10135 (set (match_operand:SI 6 "gpc_reg_operand" "")
10136 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10137 (set (match_operand:SI 7 "gpc_reg_operand" "")
10138 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10139 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10140 "*
10141 { return rs6000_output_load_multiple (operands); }"
10142 [(set_attr "type" "load")
10143 (set_attr "update" "yes")
10144 (set_attr "indexed" "yes")
10145 (set_attr "length" "32")])
10147 (define_insn "*ldmsi5"
10148 [(match_parallel 0 "load_multiple_operation"
10149 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10150 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10151 (set (match_operand:SI 3 "gpc_reg_operand" "")
10152 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10153 (set (match_operand:SI 4 "gpc_reg_operand" "")
10154 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10155 (set (match_operand:SI 5 "gpc_reg_operand" "")
10156 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10157 (set (match_operand:SI 6 "gpc_reg_operand" "")
10158 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10159 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10160 "*
10161 { return rs6000_output_load_multiple (operands); }"
10162 [(set_attr "type" "load")
10163 (set_attr "update" "yes")
10164 (set_attr "indexed" "yes")
10165 (set_attr "length" "32")])
10167 (define_insn "*ldmsi4"
10168 [(match_parallel 0 "load_multiple_operation"
10169 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10170 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10171 (set (match_operand:SI 3 "gpc_reg_operand" "")
10172 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10173 (set (match_operand:SI 4 "gpc_reg_operand" "")
10174 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10175 (set (match_operand:SI 5 "gpc_reg_operand" "")
10176 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10177 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10178 "*
10179 { return rs6000_output_load_multiple (operands); }"
10180 [(set_attr "type" "load")
10181 (set_attr "update" "yes")
10182 (set_attr "indexed" "yes")
10183 (set_attr "length" "32")])
10185 (define_insn "*ldmsi3"
10186 [(match_parallel 0 "load_multiple_operation"
10187 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10188 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10189 (set (match_operand:SI 3 "gpc_reg_operand" "")
10190 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10191 (set (match_operand:SI 4 "gpc_reg_operand" "")
10192 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10193 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10194 "*
10195 { return rs6000_output_load_multiple (operands); }"
10196 [(set_attr "type" "load")
10197 (set_attr "update" "yes")
10198 (set_attr "indexed" "yes")
10199 (set_attr "length" "32")])
10201 (define_expand "store_multiple"
10202 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10203 (match_operand:SI 1 "" ""))
10204 (clobber (scratch:SI))
10205 (use (match_operand:SI 2 "" ""))])]
10206 "TARGET_STRING && !TARGET_POWERPC64"
10207 "
10208 {
10209 int regno;
10210 int count;
10211 rtx to;
10212 rtx op0;
10213 int i;
10215 /* Support only storing a constant number of fixed-point registers to
10216 memory and only bother with this if more than two; the machine
10217 doesn't support more than eight. */
10218 if (GET_CODE (operands[2]) != CONST_INT
10219 || INTVAL (operands[2]) <= 2
10220 || INTVAL (operands[2]) > 8
10221 || GET_CODE (operands[0]) != MEM
10222 || GET_CODE (operands[1]) != REG
10223 || REGNO (operands[1]) >= 32)
10224 FAIL;
10226 count = INTVAL (operands[2]);
10227 regno = REGNO (operands[1]);
10229 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10230 to = force_reg (SImode, XEXP (operands[0], 0));
10231 op0 = replace_equiv_address (operands[0], to);
10233 XVECEXP (operands[3], 0, 0)
10234 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10235 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10236 gen_rtx_SCRATCH (SImode));
10238 for (i = 1; i < count; i++)
10239 XVECEXP (operands[3], 0, i + 1)
10240 = gen_rtx_SET (VOIDmode,
10241 adjust_address_nv (op0, SImode, i * 4),
10242 gen_rtx_REG (SImode, regno + i));
10243 }")
10245 (define_insn "*stmsi8"
10246 [(match_parallel 0 "store_multiple_operation"
10247 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10248 (match_operand:SI 2 "gpc_reg_operand" "r"))
10249 (clobber (match_scratch:SI 3 "=X"))
10250 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10251 (match_operand:SI 4 "gpc_reg_operand" "r"))
10252 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10253 (match_operand:SI 5 "gpc_reg_operand" "r"))
10254 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10255 (match_operand:SI 6 "gpc_reg_operand" "r"))
10256 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10257 (match_operand:SI 7 "gpc_reg_operand" "r"))
10258 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10259 (match_operand:SI 8 "gpc_reg_operand" "r"))
10260 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10261 (match_operand:SI 9 "gpc_reg_operand" "r"))
10262 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10263 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10264 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
10265 "stswi %2,%1,%O0"
10266 [(set_attr "type" "store")
10267 (set_attr "update" "yes")
10268 (set_attr "indexed" "yes")
10269 (set_attr "cell_micro" "always")])
10271 (define_insn "*stmsi7"
10272 [(match_parallel 0 "store_multiple_operation"
10273 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10274 (match_operand:SI 2 "gpc_reg_operand" "r"))
10275 (clobber (match_scratch:SI 3 "=X"))
10276 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10277 (match_operand:SI 4 "gpc_reg_operand" "r"))
10278 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10279 (match_operand:SI 5 "gpc_reg_operand" "r"))
10280 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10281 (match_operand:SI 6 "gpc_reg_operand" "r"))
10282 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10283 (match_operand:SI 7 "gpc_reg_operand" "r"))
10284 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10285 (match_operand:SI 8 "gpc_reg_operand" "r"))
10286 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10287 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10288 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10289 "stswi %2,%1,%O0"
10290 [(set_attr "type" "store")
10291 (set_attr "update" "yes")
10292 (set_attr "indexed" "yes")
10293 (set_attr "cell_micro" "always")])
10295 (define_insn "*stmsi6"
10296 [(match_parallel 0 "store_multiple_operation"
10297 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10298 (match_operand:SI 2 "gpc_reg_operand" "r"))
10299 (clobber (match_scratch:SI 3 "=X"))
10300 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10301 (match_operand:SI 4 "gpc_reg_operand" "r"))
10302 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10303 (match_operand:SI 5 "gpc_reg_operand" "r"))
10304 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10305 (match_operand:SI 6 "gpc_reg_operand" "r"))
10306 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10307 (match_operand:SI 7 "gpc_reg_operand" "r"))
10308 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10309 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10310 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10311 "stswi %2,%1,%O0"
10312 [(set_attr "type" "store")
10313 (set_attr "update" "yes")
10314 (set_attr "indexed" "yes")
10315 (set_attr "cell_micro" "always")])
10317 (define_insn "*stmsi5"
10318 [(match_parallel 0 "store_multiple_operation"
10319 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10320 (match_operand:SI 2 "gpc_reg_operand" "r"))
10321 (clobber (match_scratch:SI 3 "=X"))
10322 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10323 (match_operand:SI 4 "gpc_reg_operand" "r"))
10324 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10325 (match_operand:SI 5 "gpc_reg_operand" "r"))
10326 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10327 (match_operand:SI 6 "gpc_reg_operand" "r"))
10328 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10329 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10330 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10331 "stswi %2,%1,%O0"
10332 [(set_attr "type" "store")
10333 (set_attr "update" "yes")
10334 (set_attr "indexed" "yes")
10335 (set_attr "cell_micro" "always")])
10337 (define_insn "*stmsi4"
10338 [(match_parallel 0 "store_multiple_operation"
10339 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10340 (match_operand:SI 2 "gpc_reg_operand" "r"))
10341 (clobber (match_scratch:SI 3 "=X"))
10342 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10343 (match_operand:SI 4 "gpc_reg_operand" "r"))
10344 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10345 (match_operand:SI 5 "gpc_reg_operand" "r"))
10346 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10347 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10348 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10349 "stswi %2,%1,%O0"
10350 [(set_attr "type" "store")
10351 (set_attr "update" "yes")
10352 (set_attr "indexed" "yes")
10353 (set_attr "cell_micro" "always")])
10355 (define_insn "*stmsi3"
10356 [(match_parallel 0 "store_multiple_operation"
10357 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10358 (match_operand:SI 2 "gpc_reg_operand" "r"))
10359 (clobber (match_scratch:SI 3 "=X"))
10360 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10361 (match_operand:SI 4 "gpc_reg_operand" "r"))
10362 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10363 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10364 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10365 "stswi %2,%1,%O0"
10366 [(set_attr "type" "store")
10367 (set_attr "update" "yes")
10368 (set_attr "indexed" "yes")
10369 (set_attr "cell_micro" "always")])
10370 \f
10371 (define_expand "setmemsi"
10372 [(parallel [(set (match_operand:BLK 0 "" "")
10373 (match_operand 2 "const_int_operand" ""))
10374 (use (match_operand:SI 1 "" ""))
10375 (use (match_operand:SI 3 "" ""))])]
10376 ""
10377 "
10378 {
10379 /* If value to set is not zero, use the library routine. */
10380 if (operands[2] != const0_rtx)
10381 FAIL;
10383 if (expand_block_clear (operands))
10384 DONE;
10385 else
10386 FAIL;
10387 }")
10389 ;; String/block move insn.
10390 ;; Argument 0 is the destination
10391 ;; Argument 1 is the source
10392 ;; Argument 2 is the length
10393 ;; Argument 3 is the alignment
10395 (define_expand "movmemsi"
10396 [(parallel [(set (match_operand:BLK 0 "" "")
10397 (match_operand:BLK 1 "" ""))
10398 (use (match_operand:SI 2 "" ""))
10399 (use (match_operand:SI 3 "" ""))])]
10400 ""
10401 "
10402 {
10403 if (expand_block_move (operands))
10404 DONE;
10405 else
10406 FAIL;
10407 }")
10409 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10410 ;; register allocator doesn't have a clue about allocating 8 word registers.
10411 ;; rD/rS = r5 is preferred, efficient form.
10412 (define_expand "movmemsi_8reg"
10413 [(parallel [(set (match_operand 0 "" "")
10414 (match_operand 1 "" ""))
10415 (use (match_operand 2 "" ""))
10416 (use (match_operand 3 "" ""))
10417 (clobber (reg:SI 5))
10418 (clobber (reg:SI 6))
10419 (clobber (reg:SI 7))
10420 (clobber (reg:SI 8))
10421 (clobber (reg:SI 9))
10422 (clobber (reg:SI 10))
10423 (clobber (reg:SI 11))
10424 (clobber (reg:SI 12))
10425 (clobber (match_scratch:SI 4 ""))])]
10426 "TARGET_STRING"
10427 "")
10429 (define_insn ""
10430 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10431 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10432 (use (match_operand:SI 2 "immediate_operand" "i"))
10433 (use (match_operand:SI 3 "immediate_operand" "i"))
10434 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10435 (clobber (reg:SI 6))
10436 (clobber (reg:SI 7))
10437 (clobber (reg:SI 8))
10438 (clobber (reg:SI 9))
10439 (clobber (reg:SI 10))
10440 (clobber (reg:SI 11))
10441 (clobber (reg:SI 12))
10442 (clobber (match_scratch:SI 5 "=X"))]
10443 "TARGET_STRING
10444 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10445 || INTVAL (operands[2]) == 0)
10446 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10447 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10448 && REGNO (operands[4]) == 5"
10449 "lswi %4,%1,%2\;stswi %4,%0,%2"
10450 [(set_attr "type" "store")
10451 (set_attr "update" "yes")
10452 (set_attr "indexed" "yes")
10453 (set_attr "cell_micro" "always")
10454 (set_attr "length" "8")])
10456 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10457 ;; register allocator doesn't have a clue about allocating 6 word registers.
10458 ;; rD/rS = r5 is preferred, efficient form.
10459 (define_expand "movmemsi_6reg"
10460 [(parallel [(set (match_operand 0 "" "")
10461 (match_operand 1 "" ""))
10462 (use (match_operand 2 "" ""))
10463 (use (match_operand 3 "" ""))
10464 (clobber (reg:SI 5))
10465 (clobber (reg:SI 6))
10466 (clobber (reg:SI 7))
10467 (clobber (reg:SI 8))
10468 (clobber (reg:SI 9))
10469 (clobber (reg:SI 10))
10470 (clobber (match_scratch:SI 4 ""))])]
10471 "TARGET_STRING"
10472 "")
10474 (define_insn ""
10475 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10476 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10477 (use (match_operand:SI 2 "immediate_operand" "i"))
10478 (use (match_operand:SI 3 "immediate_operand" "i"))
10479 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10480 (clobber (reg:SI 6))
10481 (clobber (reg:SI 7))
10482 (clobber (reg:SI 8))
10483 (clobber (reg:SI 9))
10484 (clobber (reg:SI 10))
10485 (clobber (match_scratch:SI 5 "=X"))]
10486 "TARGET_STRING
10487 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10488 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10489 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10490 && REGNO (operands[4]) == 5"
10491 "lswi %4,%1,%2\;stswi %4,%0,%2"
10492 [(set_attr "type" "store")
10493 (set_attr "update" "yes")
10494 (set_attr "indexed" "yes")
10495 (set_attr "cell_micro" "always")
10496 (set_attr "length" "8")])
10498 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10499 ;; problems with TImode.
10500 ;; rD/rS = r5 is preferred, efficient form.
10501 (define_expand "movmemsi_4reg"
10502 [(parallel [(set (match_operand 0 "" "")
10503 (match_operand 1 "" ""))
10504 (use (match_operand 2 "" ""))
10505 (use (match_operand 3 "" ""))
10506 (clobber (reg:SI 5))
10507 (clobber (reg:SI 6))
10508 (clobber (reg:SI 7))
10509 (clobber (reg:SI 8))
10510 (clobber (match_scratch:SI 4 ""))])]
10511 "TARGET_STRING"
10512 "")
10514 (define_insn ""
10515 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10516 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10517 (use (match_operand:SI 2 "immediate_operand" "i"))
10518 (use (match_operand:SI 3 "immediate_operand" "i"))
10519 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10520 (clobber (reg:SI 6))
10521 (clobber (reg:SI 7))
10522 (clobber (reg:SI 8))
10523 (clobber (match_scratch:SI 5 "=X"))]
10524 "TARGET_STRING
10525 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10526 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10527 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10528 && REGNO (operands[4]) == 5"
10529 "lswi %4,%1,%2\;stswi %4,%0,%2"
10530 [(set_attr "type" "store")
10531 (set_attr "update" "yes")
10532 (set_attr "indexed" "yes")
10533 (set_attr "cell_micro" "always")
10534 (set_attr "length" "8")])
10536 ;; Move up to 8 bytes at a time.
10537 (define_expand "movmemsi_2reg"
10538 [(parallel [(set (match_operand 0 "" "")
10539 (match_operand 1 "" ""))
10540 (use (match_operand 2 "" ""))
10541 (use (match_operand 3 "" ""))
10542 (clobber (match_scratch:DI 4 ""))
10543 (clobber (match_scratch:SI 5 ""))])]
10544 "TARGET_STRING && ! TARGET_POWERPC64"
10545 "")
10547 (define_insn ""
10548 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10549 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10550 (use (match_operand:SI 2 "immediate_operand" "i"))
10551 (use (match_operand:SI 3 "immediate_operand" "i"))
10552 (clobber (match_scratch:DI 4 "=&r"))
10553 (clobber (match_scratch:SI 5 "=X"))]
10554 "TARGET_STRING && ! TARGET_POWERPC64
10555 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10556 "lswi %4,%1,%2\;stswi %4,%0,%2"
10557 [(set_attr "type" "store")
10558 (set_attr "update" "yes")
10559 (set_attr "indexed" "yes")
10560 (set_attr "cell_micro" "always")
10561 (set_attr "length" "8")])
10563 ;; Move up to 4 bytes at a time.
10564 (define_expand "movmemsi_1reg"
10565 [(parallel [(set (match_operand 0 "" "")
10566 (match_operand 1 "" ""))
10567 (use (match_operand 2 "" ""))
10568 (use (match_operand 3 "" ""))
10569 (clobber (match_scratch:SI 4 ""))
10570 (clobber (match_scratch:SI 5 ""))])]
10571 "TARGET_STRING"
10572 "")
10574 (define_insn ""
10575 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10576 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10577 (use (match_operand:SI 2 "immediate_operand" "i"))
10578 (use (match_operand:SI 3 "immediate_operand" "i"))
10579 (clobber (match_scratch:SI 4 "=&r"))
10580 (clobber (match_scratch:SI 5 "=X"))]
10581 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10582 "lswi %4,%1,%2\;stswi %4,%0,%2"
10583 [(set_attr "type" "store")
10584 (set_attr "update" "yes")
10585 (set_attr "indexed" "yes")
10586 (set_attr "cell_micro" "always")
10587 (set_attr "length" "8")])
10588 \f
10589 ;; Define insns that do load or store with update. Some of these we can
10590 ;; get by using pre-decrement or pre-increment, but the hardware can also
10591 ;; do cases where the increment is not the size of the object.
10592 ;;
10593 ;; In all these cases, we use operands 0 and 1 for the register being
10594 ;; incremented because those are the operands that local-alloc will
10595 ;; tie and these are the pair most likely to be tieable (and the ones
10596 ;; that will benefit the most).
10598 (define_insn "*movdi_update1"
10599 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10600 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10601 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10602 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10603 (plus:DI (match_dup 1) (match_dup 2)))]
10604 "TARGET_POWERPC64 && TARGET_UPDATE
10605 && (!avoiding_indexed_address_p (DImode)
10606 || !gpc_reg_operand (operands[2], DImode))"
10607 "@
10608 ldux %3,%0,%2
10609 ldu %3,%2(%0)"
10610 [(set_attr "type" "load")
10611 (set_attr "update" "yes")
10612 (set_attr "indexed" "yes,no")])
10614 (define_insn "movdi_<mode>_update"
10615 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10616 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10617 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10618 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10619 (plus:P (match_dup 1) (match_dup 2)))]
10620 "TARGET_POWERPC64 && TARGET_UPDATE
10621 && (!avoiding_indexed_address_p (Pmode)
10622 || !gpc_reg_operand (operands[2], Pmode)
10623 || (REG_P (operands[0])
10624 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10625 "@
10626 stdux %3,%0,%2
10627 stdu %3,%2(%0)"
10628 [(set_attr "type" "store")
10629 (set_attr "update" "yes")
10630 (set_attr "indexed" "yes,no")])
10632 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10633 ;; needed for stack allocation, even if the user passes -mno-update.
10634 (define_insn "movdi_<mode>_update_stack"
10635 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10636 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10637 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10638 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10639 (plus:P (match_dup 1) (match_dup 2)))]
10640 "TARGET_POWERPC64"
10641 "@
10642 stdux %3,%0,%2
10643 stdu %3,%2(%0)"
10644 [(set_attr "type" "store")
10645 (set_attr "update" "yes")
10646 (set_attr "indexed" "yes,no")])
10648 (define_insn "*movsi_update1"
10649 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10650 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10651 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10652 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10653 (plus:SI (match_dup 1) (match_dup 2)))]
10654 "TARGET_UPDATE
10655 && (!avoiding_indexed_address_p (SImode)
10656 || !gpc_reg_operand (operands[2], SImode))"
10657 "@
10658 lwzux %3,%0,%2
10659 lwzu %3,%2(%0)"
10660 [(set_attr "type" "load")
10661 (set_attr "update" "yes")
10662 (set_attr "indexed" "yes,no")])
10664 (define_insn "*movsi_update2"
10665 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10666 (sign_extend:DI
10667 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10668 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10669 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10670 (plus:DI (match_dup 1) (match_dup 2)))]
10671 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10672 && !avoiding_indexed_address_p (DImode)"
10673 "lwaux %3,%0,%2"
10674 [(set_attr "type" "load")
10675 (set_attr "sign_extend" "yes")
10676 (set_attr "update" "yes")
10677 (set_attr "indexed" "yes")])
10679 (define_insn "movsi_update"
10680 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10681 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10682 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10683 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10684 (plus:SI (match_dup 1) (match_dup 2)))]
10685 "TARGET_UPDATE
10686 && (!avoiding_indexed_address_p (SImode)
10687 || !gpc_reg_operand (operands[2], SImode)
10688 || (REG_P (operands[0])
10689 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10690 "@
10691 stwux %3,%0,%2
10692 stwu %3,%2(%0)"
10693 [(set_attr "type" "store")
10694 (set_attr "update" "yes")
10695 (set_attr "indexed" "yes,no")])
10697 ;; This is an unconditional pattern; needed for stack allocation, even
10698 ;; if the user passes -mno-update.
10699 (define_insn "movsi_update_stack"
10700 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10701 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10702 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10703 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10704 (plus:SI (match_dup 1) (match_dup 2)))]
10705 ""
10706 "@
10707 stwux %3,%0,%2
10708 stwu %3,%2(%0)"
10709 [(set_attr "type" "store")
10710 (set_attr "update" "yes")
10711 (set_attr "indexed" "yes,no")])
10713 (define_insn "*movhi_update1"
10714 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10715 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10716 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10717 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10718 (plus:SI (match_dup 1) (match_dup 2)))]
10719 "TARGET_UPDATE
10720 && (!avoiding_indexed_address_p (SImode)
10721 || !gpc_reg_operand (operands[2], SImode))"
10722 "@
10723 lhzux %3,%0,%2
10724 lhzu %3,%2(%0)"
10725 [(set_attr "type" "load")
10726 (set_attr "update" "yes")
10727 (set_attr "indexed" "yes,no")])
10729 (define_insn "*movhi_update2"
10730 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10731 (zero_extend:SI
10732 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10733 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10734 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10735 (plus:SI (match_dup 1) (match_dup 2)))]
10736 "TARGET_UPDATE
10737 && (!avoiding_indexed_address_p (SImode)
10738 || !gpc_reg_operand (operands[2], SImode))"
10739 "@
10740 lhzux %3,%0,%2
10741 lhzu %3,%2(%0)"
10742 [(set_attr "type" "load")
10743 (set_attr "update" "yes")
10744 (set_attr "indexed" "yes,no")])
10746 (define_insn "*movhi_update3"
10747 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10748 (sign_extend:SI
10749 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10750 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10751 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10752 (plus:SI (match_dup 1) (match_dup 2)))]
10753 "TARGET_UPDATE && rs6000_gen_cell_microcode
10754 && (!avoiding_indexed_address_p (SImode)
10755 || !gpc_reg_operand (operands[2], SImode))"
10756 "@
10757 lhaux %3,%0,%2
10758 lhau %3,%2(%0)"
10759 [(set_attr "type" "load")
10760 (set_attr "sign_extend" "yes")
10761 (set_attr "update" "yes")
10762 (set_attr "indexed" "yes,no")])
10764 (define_insn "*movhi_update4"
10765 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10766 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10767 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10768 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10769 (plus:SI (match_dup 1) (match_dup 2)))]
10770 "TARGET_UPDATE
10771 && (!avoiding_indexed_address_p (SImode)
10772 || !gpc_reg_operand (operands[2], SImode))"
10773 "@
10774 sthux %3,%0,%2
10775 sthu %3,%2(%0)"
10776 [(set_attr "type" "store")
10777 (set_attr "update" "yes")
10778 (set_attr "indexed" "yes,no")])
10780 (define_insn "*movqi_update1"
10781 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10782 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10783 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10784 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10785 (plus:SI (match_dup 1) (match_dup 2)))]
10786 "TARGET_UPDATE
10787 && (!avoiding_indexed_address_p (SImode)
10788 || !gpc_reg_operand (operands[2], SImode))"
10789 "@
10790 lbzux %3,%0,%2
10791 lbzu %3,%2(%0)"
10792 [(set_attr "type" "load")
10793 (set_attr "update" "yes")
10794 (set_attr "indexed" "yes,no")])
10796 (define_insn "*movqi_update2"
10797 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10798 (zero_extend:SI
10799 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10800 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10801 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10802 (plus:SI (match_dup 1) (match_dup 2)))]
10803 "TARGET_UPDATE
10804 && (!avoiding_indexed_address_p (SImode)
10805 || !gpc_reg_operand (operands[2], SImode))"
10806 "@
10807 lbzux %3,%0,%2
10808 lbzu %3,%2(%0)"
10809 [(set_attr "type" "load")
10810 (set_attr "update" "yes")
10811 (set_attr "indexed" "yes,no")])
10813 (define_insn "*movqi_update3"
10814 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10815 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10816 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10817 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10818 (plus:SI (match_dup 1) (match_dup 2)))]
10819 "TARGET_UPDATE
10820 && (!avoiding_indexed_address_p (SImode)
10821 || !gpc_reg_operand (operands[2], SImode))"
10822 "@
10823 stbux %3,%0,%2
10824 stbu %3,%2(%0)"
10825 [(set_attr "type" "store")
10826 (set_attr "update" "yes")
10827 (set_attr "indexed" "yes,no")])
10829 (define_insn "*movsf_update1"
10830 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10831 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10832 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10833 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10834 (plus:SI (match_dup 1) (match_dup 2)))]
10835 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10836 && (!avoiding_indexed_address_p (SImode)
10837 || !gpc_reg_operand (operands[2], SImode))"
10838 "@
10839 lfsux %3,%0,%2
10840 lfsu %3,%2(%0)"
10841 [(set_attr "type" "fpload")
10842 (set_attr "update" "yes")
10843 (set_attr "indexed" "yes,no")])
10845 (define_insn "*movsf_update2"
10846 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10847 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10848 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10849 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10850 (plus:SI (match_dup 1) (match_dup 2)))]
10851 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10852 && (!avoiding_indexed_address_p (SImode)
10853 || !gpc_reg_operand (operands[2], SImode))"
10854 "@
10855 stfsux %3,%0,%2
10856 stfsu %3,%2(%0)"
10857 [(set_attr "type" "fpstore")
10858 (set_attr "update" "yes")
10859 (set_attr "indexed" "yes,no")])
10861 (define_insn "*movsf_update3"
10862 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10863 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10864 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10865 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10866 (plus:SI (match_dup 1) (match_dup 2)))]
10867 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10868 && (!avoiding_indexed_address_p (SImode)
10869 || !gpc_reg_operand (operands[2], SImode))"
10870 "@
10871 lwzux %3,%0,%2
10872 lwzu %3,%2(%0)"
10873 [(set_attr "type" "load")
10874 (set_attr "update" "yes")
10875 (set_attr "indexed" "yes,no")])
10877 (define_insn "*movsf_update4"
10878 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10879 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10880 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10881 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10882 (plus:SI (match_dup 1) (match_dup 2)))]
10883 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10884 && (!avoiding_indexed_address_p (SImode)
10885 || !gpc_reg_operand (operands[2], SImode))"
10886 "@
10887 stwux %3,%0,%2
10888 stwu %3,%2(%0)"
10889 [(set_attr "type" "store")
10890 (set_attr "update" "yes")
10891 (set_attr "indexed" "yes,no")])
10893 (define_insn "*movdf_update1"
10894 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10895 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10896 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10897 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10898 (plus:SI (match_dup 1) (match_dup 2)))]
10899 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10900 && (!avoiding_indexed_address_p (SImode)
10901 || !gpc_reg_operand (operands[2], SImode))"
10902 "@
10903 lfdux %3,%0,%2
10904 lfdu %3,%2(%0)"
10905 [(set_attr "type" "fpload")
10906 (set_attr "update" "yes")
10907 (set_attr "indexed" "yes,no")])
10909 (define_insn "*movdf_update2"
10910 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10911 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10912 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10913 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10914 (plus:SI (match_dup 1) (match_dup 2)))]
10915 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10916 && (!avoiding_indexed_address_p (SImode)
10917 || !gpc_reg_operand (operands[2], SImode))"
10918 "@
10919 stfdux %3,%0,%2
10920 stfdu %3,%2(%0)"
10921 [(set_attr "type" "fpstore")
10922 (set_attr "update" "yes")
10923 (set_attr "indexed" "yes,no")])
10926 ;; After inserting conditional returns we can sometimes have
10927 ;; unnecessary register moves. Unfortunately we cannot have a
10928 ;; modeless peephole here, because some single SImode sets have early
10929 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10930 ;; sequences, using get_attr_length here will smash the operands
10931 ;; array. Neither is there an early_cobbler_p predicate.
10932 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10933 (define_peephole2
10934 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10935 (match_operand:DF 1 "any_operand" ""))
10936 (set (match_operand:DF 2 "gpc_reg_operand" "")
10937 (match_dup 0))]
10938 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10939 && peep2_reg_dead_p (2, operands[0])"
10940 [(set (match_dup 2) (match_dup 1))])
10942 (define_peephole2
10943 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10944 (match_operand:SF 1 "any_operand" ""))
10945 (set (match_operand:SF 2 "gpc_reg_operand" "")
10946 (match_dup 0))]
10947 "peep2_reg_dead_p (2, operands[0])"
10948 [(set (match_dup 2) (match_dup 1))])
10950 \f
10951 ;; TLS support.
10953 ;; Mode attributes for different ABIs.
10954 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10955 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10956 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10957 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10959 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10960 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10961 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10962 (match_operand 4 "" "g")))
10963 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10964 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10965 UNSPEC_TLSGD)
10966 (clobber (reg:SI LR_REGNO))]
10967 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10968 {
10969 if (TARGET_CMODEL != CMODEL_SMALL)
10970 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
10971 "bl %z3\;nop";
10972 else
10973 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
10974 }
10975 "&& TARGET_TLS_MARKERS"
10976 [(set (match_dup 0)
10977 (unspec:TLSmode [(match_dup 1)
10978 (match_dup 2)]
10979 UNSPEC_TLSGD))
10980 (parallel [(set (match_dup 0)
10981 (call (mem:TLSmode (match_dup 3))
10982 (match_dup 4)))
10983 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10984 (clobber (reg:SI LR_REGNO))])]
10985 ""
10986 [(set_attr "type" "two")
10987 (set (attr "length")
10988 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10989 (const_int 16)
10990 (const_int 12)))])
10992 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10993 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10994 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10995 (match_operand 4 "" "g")))
10996 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10997 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10998 UNSPEC_TLSGD)
10999 (clobber (reg:SI LR_REGNO))]
11000 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11001 {
11002 if (flag_pic)
11003 {
11004 if (TARGET_SECURE_PLT && flag_pic == 2)
11005 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11006 else
11007 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11008 }
11009 else
11010 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11011 }
11012 "&& TARGET_TLS_MARKERS"
11013 [(set (match_dup 0)
11014 (unspec:TLSmode [(match_dup 1)
11015 (match_dup 2)]
11016 UNSPEC_TLSGD))
11017 (parallel [(set (match_dup 0)
11018 (call (mem:TLSmode (match_dup 3))
11019 (match_dup 4)))
11020 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11021 (clobber (reg:SI LR_REGNO))])]
11022 ""
11023 [(set_attr "type" "two")
11024 (set_attr "length" "8")])
11026 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11027 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11028 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11029 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11030 UNSPEC_TLSGD))]
11031 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11032 "addi %0,%1,%2@got@tlsgd"
11033 "&& TARGET_CMODEL != CMODEL_SMALL"
11034 [(set (match_dup 3)
11035 (high:TLSmode
11036 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
11037 (set (match_dup 0)
11038 (lo_sum:TLSmode (match_dup 3)
11039 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
11040 "
11041 {
11042 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11043 }"
11044 [(set (attr "length")
11045 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11046 (const_int 8)
11047 (const_int 4)))])
11049 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11050 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11051 (high:TLSmode
11052 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11053 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11054 UNSPEC_TLSGD)))]
11055 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11056 "addis %0,%1,%2@got@tlsgd@ha"
11057 [(set_attr "length" "4")])
11059 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11060 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11061 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11062 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11063 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11064 UNSPEC_TLSGD)))]
11065 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11066 "addi %0,%1,%2@got@tlsgd@l"
11067 [(set_attr "length" "4")])
11069 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11070 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11071 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11072 (match_operand 2 "" "g")))
11073 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11074 UNSPEC_TLSGD)
11075 (clobber (reg:SI LR_REGNO))]
11076 "HAVE_AS_TLS && TARGET_TLS_MARKERS
11077 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11078 "bl %z1(%3@tlsgd)\;nop"
11079 [(set_attr "type" "branch")
11080 (set_attr "length" "8")])
11082 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11083 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11084 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11085 (match_operand 2 "" "g")))
11086 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11087 UNSPEC_TLSGD)
11088 (clobber (reg:SI LR_REGNO))]
11089 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11090 {
11091 if (flag_pic)
11092 {
11093 if (TARGET_SECURE_PLT && flag_pic == 2)
11094 return "bl %z1+32768(%3@tlsgd)@plt";
11095 return "bl %z1(%3@tlsgd)@plt";
11096 }
11097 return "bl %z1(%3@tlsgd)";
11098 }
11099 [(set_attr "type" "branch")
11100 (set_attr "length" "4")])
11102 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11103 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11104 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11105 (match_operand 3 "" "g")))
11106 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11107 UNSPEC_TLSLD)
11108 (clobber (reg:SI LR_REGNO))]
11109 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11110 {
11111 if (TARGET_CMODEL != CMODEL_SMALL)
11112 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
11113 "bl %z2\;nop";
11114 else
11115 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
11116 }
11117 "&& TARGET_TLS_MARKERS"
11118 [(set (match_dup 0)
11119 (unspec:TLSmode [(match_dup 1)]
11120 UNSPEC_TLSLD))
11121 (parallel [(set (match_dup 0)
11122 (call (mem:TLSmode (match_dup 2))
11123 (match_dup 3)))
11124 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11125 (clobber (reg:SI LR_REGNO))])]
11126 ""
11127 [(set_attr "type" "two")
11128 (set (attr "length")
11129 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11130 (const_int 16)
11131 (const_int 12)))])
11133 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11134 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11135 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11136 (match_operand 3 "" "g")))
11137 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11138 UNSPEC_TLSLD)
11139 (clobber (reg:SI LR_REGNO))]
11140 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11141 {
11142 if (flag_pic)
11143 {
11144 if (TARGET_SECURE_PLT && flag_pic == 2)
11145 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11146 else
11147 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11148 }
11149 else
11150 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11151 }
11152 "&& TARGET_TLS_MARKERS"
11153 [(set (match_dup 0)
11154 (unspec:TLSmode [(match_dup 1)]
11155 UNSPEC_TLSLD))
11156 (parallel [(set (match_dup 0)
11157 (call (mem:TLSmode (match_dup 2))
11158 (match_dup 3)))
11159 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11160 (clobber (reg:SI LR_REGNO))])]
11161 ""
11162 [(set_attr "length" "8")])
11164 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11165 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11166 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11167 UNSPEC_TLSLD))]
11168 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11169 "addi %0,%1,%&@got@tlsld"
11170 "&& TARGET_CMODEL != CMODEL_SMALL"
11171 [(set (match_dup 2)
11172 (high:TLSmode
11173 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
11174 (set (match_dup 0)
11175 (lo_sum:TLSmode (match_dup 2)
11176 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
11177 "
11178 {
11179 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11180 }"
11181 [(set (attr "length")
11182 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11183 (const_int 8)
11184 (const_int 4)))])
11186 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11187 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11188 (high:TLSmode
11189 (unspec:TLSmode [(const_int 0)
11190 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11191 UNSPEC_TLSLD)))]
11192 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11193 "addis %0,%1,%&@got@tlsld@ha"
11194 [(set_attr "length" "4")])
11196 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11197 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11198 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11199 (unspec:TLSmode [(const_int 0)
11200 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
11201 UNSPEC_TLSLD)))]
11202 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11203 "addi %0,%1,%&@got@tlsld@l"
11204 [(set_attr "length" "4")])
11206 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11207 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11208 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11209 (match_operand 2 "" "g")))
11210 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11211 (clobber (reg:SI LR_REGNO))]
11212 "HAVE_AS_TLS && TARGET_TLS_MARKERS
11213 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11214 "bl %z1(%&@tlsld)\;nop"
11215 [(set_attr "type" "branch")
11216 (set_attr "length" "8")])
11218 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11219 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11220 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11221 (match_operand 2 "" "g")))
11222 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11223 (clobber (reg:SI LR_REGNO))]
11224 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11225 {
11226 if (flag_pic)
11227 {
11228 if (TARGET_SECURE_PLT && flag_pic == 2)
11229 return "bl %z1+32768(%&@tlsld)@plt";
11230 return "bl %z1(%&@tlsld)@plt";
11231 }
11232 return "bl %z1(%&@tlsld)";
11233 }
11234 [(set_attr "type" "branch")
11235 (set_attr "length" "4")])
11237 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11238 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11239 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11240 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11241 UNSPEC_TLSDTPREL))]
11242 "HAVE_AS_TLS"
11243 "addi %0,%1,%2@dtprel")
11245 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11246 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11247 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11248 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11249 UNSPEC_TLSDTPRELHA))]
11250 "HAVE_AS_TLS"
11251 "addis %0,%1,%2@dtprel@ha")
11253 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11254 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11255 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11256 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11257 UNSPEC_TLSDTPRELLO))]
11258 "HAVE_AS_TLS"
11259 "addi %0,%1,%2@dtprel@l")
11261 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11262 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11263 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11264 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11265 UNSPEC_TLSGOTDTPREL))]
11266 "HAVE_AS_TLS"
11267 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11268 "&& TARGET_CMODEL != CMODEL_SMALL"
11269 [(set (match_dup 3)
11270 (high:TLSmode
11271 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
11272 (set (match_dup 0)
11273 (lo_sum:TLSmode (match_dup 3)
11274 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11275 "
11276 {
11277 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11278 }"
11279 [(set (attr "length")
11280 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11281 (const_int 8)
11282 (const_int 4)))])
11284 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11285 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11286 (high:TLSmode
11287 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11288 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11289 UNSPEC_TLSGOTDTPREL)))]
11290 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11291 "addis %0,%1,%2@got@dtprel@ha"
11292 [(set_attr "length" "4")])
11294 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11295 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11296 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11297 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11298 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11299 UNSPEC_TLSGOTDTPREL)))]
11300 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11301 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11302 [(set_attr "length" "4")])
11304 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11305 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11306 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11307 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11308 UNSPEC_TLSTPREL))]
11309 "HAVE_AS_TLS"
11310 "addi %0,%1,%2@tprel")
11312 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11313 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11314 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11315 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11316 UNSPEC_TLSTPRELHA))]
11317 "HAVE_AS_TLS"
11318 "addis %0,%1,%2@tprel@ha")
11320 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11321 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11322 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11323 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11324 UNSPEC_TLSTPRELLO))]
11325 "HAVE_AS_TLS"
11326 "addi %0,%1,%2@tprel@l")
11328 ;; "b" output constraint here and on tls_tls input to support linker tls
11329 ;; optimization. The linker may edit the instructions emitted by a
11330 ;; tls_got_tprel/tls_tls pair to addis,addi.
11331 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11332 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11333 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11334 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11335 UNSPEC_TLSGOTTPREL))]
11336 "HAVE_AS_TLS"
11337 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11338 "&& TARGET_CMODEL != CMODEL_SMALL"
11339 [(set (match_dup 3)
11340 (high:TLSmode
11341 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
11342 (set (match_dup 0)
11343 (lo_sum:TLSmode (match_dup 3)
11344 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11345 "
11346 {
11347 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11348 }"
11349 [(set (attr "length")
11350 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11351 (const_int 8)
11352 (const_int 4)))])
11354 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11355 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11356 (high:TLSmode
11357 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11358 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11359 UNSPEC_TLSGOTTPREL)))]
11360 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11361 "addis %0,%1,%2@got@tprel@ha"
11362 [(set_attr "length" "4")])
11364 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11365 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11366 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11367 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11368 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11369 UNSPEC_TLSGOTTPREL)))]
11370 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11371 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11372 [(set_attr "length" "4")])
11374 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11375 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11376 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11377 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11378 UNSPEC_TLSTLS))]
11379 "TARGET_ELF && HAVE_AS_TLS"
11380 "add %0,%1,%2@tls")
11382 (define_expand "tls_get_tpointer"
11383 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11384 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
11385 "TARGET_XCOFF && HAVE_AS_TLS"
11386 "
11387 {
11388 emit_insn (gen_tls_get_tpointer_internal ());
11389 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
11390 DONE;
11391 }")
11393 (define_insn "tls_get_tpointer_internal"
11394 [(set (reg:SI 3)
11395 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
11396 (clobber (reg:SI LR_REGNO))]
11397 "TARGET_XCOFF && HAVE_AS_TLS"
11398 "bla __get_tpointer")
11400 (define_expand "tls_get_addr<mode>"
11401 [(set (match_operand:P 0 "gpc_reg_operand" "")
11402 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
11403 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
11404 "TARGET_XCOFF && HAVE_AS_TLS"
11405 "
11406 {
11407 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
11408 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
11409 emit_insn (gen_tls_get_addr_internal<mode> ());
11410 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
11411 DONE;
11412 }")
11414 (define_insn "tls_get_addr_internal<mode>"
11415 [(set (reg:P 3)
11416 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
11417 (clobber (reg:P 0))
11418 (clobber (reg:P 4))
11419 (clobber (reg:P 5))
11420 (clobber (reg:P 11))
11421 (clobber (reg:CC CR0_REGNO))
11422 (clobber (reg:P LR_REGNO))]
11423 "TARGET_XCOFF && HAVE_AS_TLS"
11424 "bla __tls_get_addr")
11425 \f
11426 ;; Next come insns related to the calling sequence.
11427 ;;
11428 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11429 ;; We move the back-chain and decrement the stack pointer.
11431 (define_expand "allocate_stack"
11432 [(set (match_operand 0 "gpc_reg_operand" "")
11433 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11434 (set (reg 1)
11435 (minus (reg 1) (match_dup 1)))]
11436 ""
11437 "
11438 { rtx chain = gen_reg_rtx (Pmode);
11439 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11440 rtx neg_op0;
11441 rtx insn, par, set, mem;
11443 emit_move_insn (chain, stack_bot);
11445 /* Check stack bounds if necessary. */
11446 if (crtl->limit_stack)
11447 {
11448 rtx available;
11449 available = expand_binop (Pmode, sub_optab,
11450 stack_pointer_rtx, stack_limit_rtx,
11451 NULL_RTX, 1, OPTAB_WIDEN);
11452 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11453 }
11455 if (GET_CODE (operands[1]) != CONST_INT
11456 || INTVAL (operands[1]) < -32767
11457 || INTVAL (operands[1]) > 32768)
11458 {
11459 neg_op0 = gen_reg_rtx (Pmode);
11460 if (TARGET_32BIT)
11461 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11462 else
11463 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11464 }
11465 else
11466 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11468 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11469 : gen_movdi_di_update_stack))
11470 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11471 chain));
11472 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11473 it now and set the alias set/attributes. The above gen_*_update
11474 calls will generate a PARALLEL with the MEM set being the first
11475 operation. */
11476 par = PATTERN (insn);
11477 gcc_assert (GET_CODE (par) == PARALLEL);
11478 set = XVECEXP (par, 0, 0);
11479 gcc_assert (GET_CODE (set) == SET);
11480 mem = SET_DEST (set);
11481 gcc_assert (MEM_P (mem));
11482 MEM_NOTRAP_P (mem) = 1;
11483 set_mem_alias_set (mem, get_frame_alias_set ());
11485 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11486 DONE;
11487 }")
11489 ;; These patterns say how to save and restore the stack pointer. We need not
11490 ;; save the stack pointer at function level since we are careful to
11491 ;; preserve the backchain. At block level, we have to restore the backchain
11492 ;; when we restore the stack pointer.
11493 ;;
11494 ;; For nonlocal gotos, we must save both the stack pointer and its
11495 ;; backchain and restore both. Note that in the nonlocal case, the
11496 ;; save area is a memory location.
11498 (define_expand "save_stack_function"
11499 [(match_operand 0 "any_operand" "")
11500 (match_operand 1 "any_operand" "")]
11501 ""
11502 "DONE;")
11504 (define_expand "restore_stack_function"
11505 [(match_operand 0 "any_operand" "")
11506 (match_operand 1 "any_operand" "")]
11507 ""
11508 "DONE;")
11510 ;; Adjust stack pointer (op0) to a new value (op1).
11511 ;; First copy old stack backchain to new location, and ensure that the
11512 ;; scheduler won't reorder the sp assignment before the backchain write.
11513 (define_expand "restore_stack_block"
11514 [(set (match_dup 2) (match_dup 3))
11515 (set (match_dup 4) (match_dup 2))
11516 (match_dup 5)
11517 (set (match_operand 0 "register_operand" "")
11518 (match_operand 1 "register_operand" ""))]
11519 ""
11520 "
11521 {
11522 rtvec p;
11524 operands[1] = force_reg (Pmode, operands[1]);
11525 operands[2] = gen_reg_rtx (Pmode);
11526 operands[3] = gen_frame_mem (Pmode, operands[0]);
11527 operands[4] = gen_frame_mem (Pmode, operands[1]);
11528 p = rtvec_alloc (1);
11529 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11530 gen_frame_mem (BLKmode, operands[0]),
11531 const0_rtx);
11532 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11533 }")
11535 (define_expand "save_stack_nonlocal"
11536 [(set (match_dup 3) (match_dup 4))
11537 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11538 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11539 ""
11540 "
11541 {
11542 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11544 /* Copy the backchain to the first word, sp to the second. */
11545 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11546 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11547 operands[3] = gen_reg_rtx (Pmode);
11548 operands[4] = gen_frame_mem (Pmode, operands[1]);
11549 }")
11551 (define_expand "restore_stack_nonlocal"
11552 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11553 (set (match_dup 3) (match_dup 4))
11554 (set (match_dup 5) (match_dup 2))
11555 (match_dup 6)
11556 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11557 ""
11558 "
11559 {
11560 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11561 rtvec p;
11563 /* Restore the backchain from the first word, sp from the second. */
11564 operands[2] = gen_reg_rtx (Pmode);
11565 operands[3] = gen_reg_rtx (Pmode);
11566 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11567 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11568 operands[5] = gen_frame_mem (Pmode, operands[3]);
11569 p = rtvec_alloc (1);
11570 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11571 gen_frame_mem (BLKmode, operands[0]),
11572 const0_rtx);
11573 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11574 }")
11575 \f
11576 ;; TOC register handling.
11578 ;; Code to initialize the TOC register...
11580 (define_insn "load_toc_aix_si"
11581 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11582 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11583 (use (reg:SI 2))])]
11584 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
11585 "*
11586 {
11587 char buf[30];
11588 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11589 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11590 operands[2] = gen_rtx_REG (Pmode, 2);
11591 return \"lwz %0,%1(%2)\";
11592 }"
11593 [(set_attr "type" "load")
11594 (set_attr "update" "no")
11595 (set_attr "indexed" "no")])
11597 (define_insn "load_toc_aix_di"
11598 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11599 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11600 (use (reg:DI 2))])]
11601 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
11602 "*
11603 {
11604 char buf[30];
11605 #ifdef TARGET_RELOCATABLE
11606 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11607 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11608 #else
11609 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11610 #endif
11611 if (TARGET_ELF)
11612 strcat (buf, \"@toc\");
11613 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11614 operands[2] = gen_rtx_REG (Pmode, 2);
11615 return \"ld %0,%1(%2)\";
11616 }"
11617 [(set_attr "type" "load")
11618 (set_attr "update" "no")
11619 (set_attr "indexed" "no")])
11621 (define_insn "load_toc_v4_pic_si"
11622 [(set (reg:SI LR_REGNO)
11623 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11624 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11625 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11626 [(set_attr "type" "branch")
11627 (set_attr "length" "4")])
11629 (define_expand "load_toc_v4_PIC_1"
11630 [(parallel [(set (reg:SI LR_REGNO)
11631 (match_operand:SI 0 "immediate_operand" "s"))
11632 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
11633 "TARGET_ELF && DEFAULT_ABI == ABI_V4
11634 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11635 "")
11637 (define_insn "load_toc_v4_PIC_1_normal"
11638 [(set (reg:SI LR_REGNO)
11639 (match_operand:SI 0 "immediate_operand" "s"))
11640 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11641 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11642 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11643 "bcl 20,31,%0\\n%0:"
11644 [(set_attr "type" "branch")
11645 (set_attr "length" "4")])
11647 (define_insn "load_toc_v4_PIC_1_476"
11648 [(set (reg:SI LR_REGNO)
11649 (match_operand:SI 0 "immediate_operand" "s"))
11650 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11651 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11652 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11653 "*
11654 {
11655 char name[32];
11656 static char templ[32];
11658 get_ppc476_thunk_name (name);
11659 sprintf (templ, \"bl %s\\n%%0:\", name);
11660 return templ;
11661 }"
11662 [(set_attr "type" "branch")
11663 (set_attr "length" "4")])
11665 (define_expand "load_toc_v4_PIC_1b"
11666 [(parallel [(set (reg:SI LR_REGNO)
11667 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11668 (label_ref (match_operand 1 "" ""))]
11669 UNSPEC_TOCPTR))
11670 (match_dup 1)])]
11671 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11672 "")
11674 (define_insn "load_toc_v4_PIC_1b_normal"
11675 [(set (reg:SI LR_REGNO)
11676 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11677 (label_ref (match_operand 1 "" ""))]
11678 UNSPEC_TOCPTR))
11679 (match_dup 1)]
11680 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11681 "bcl 20,31,$+8\;.long %0-$"
11682 [(set_attr "type" "branch")
11683 (set_attr "length" "8")])
11685 (define_insn "load_toc_v4_PIC_1b_476"
11686 [(set (reg:SI LR_REGNO)
11687 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11688 (label_ref (match_operand 1 "" ""))]
11689 UNSPEC_TOCPTR))
11690 (match_dup 1)]
11691 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11692 "*
11693 {
11694 char name[32];
11695 static char templ[32];
11697 get_ppc476_thunk_name (name);
11698 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
11699 return templ;
11700 }"
11701 [(set_attr "type" "branch")
11702 (set_attr "length" "16")])
11704 (define_insn "load_toc_v4_PIC_2"
11705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11706 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11707 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11708 (match_operand:SI 3 "immediate_operand" "s")))))]
11709 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11710 "lwz %0,%2-%3(%1)"
11711 [(set_attr "type" "load")])
11713 (define_insn "load_toc_v4_PIC_3b"
11714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11715 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11716 (high:SI
11717 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11718 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11719 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11720 "addis %0,%1,%2-%3@ha")
11722 (define_insn "load_toc_v4_PIC_3c"
11723 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11724 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11725 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11726 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11727 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11728 "addi %0,%1,%2-%3@l")
11730 ;; If the TOC is shared over a translation unit, as happens with all
11731 ;; the kinds of PIC that we support, we need to restore the TOC
11732 ;; pointer only when jumping over units of translation.
11733 ;; On Darwin, we need to reload the picbase.
11735 (define_expand "builtin_setjmp_receiver"
11736 [(use (label_ref (match_operand 0 "" "")))]
11737 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11738 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11739 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11740 "
11741 {
11742 #if TARGET_MACHO
11743 if (DEFAULT_ABI == ABI_DARWIN)
11744 {
11745 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11746 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11747 rtx tmplabrtx;
11748 char tmplab[20];
11750 crtl->uses_pic_offset_table = 1;
11751 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11752 CODE_LABEL_NUMBER (operands[0]));
11753 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11755 emit_insn (gen_load_macho_picbase (tmplabrtx));
11756 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11757 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11758 }
11759 else
11760 #endif
11761 rs6000_emit_load_toc_table (FALSE);
11762 DONE;
11763 }")
11765 ;; Largetoc support
11766 (define_insn "*largetoc_high"
11767 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11768 (high:DI
11769 (unspec [(match_operand:DI 1 "" "")
11770 (match_operand:DI 2 "gpc_reg_operand" "b")]
11771 UNSPEC_TOCREL)))]
11772 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11773 "addis %0,%2,%1@toc@ha")
11775 (define_insn "*largetoc_high_aix<mode>"
11776 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11777 (high:P
11778 (unspec [(match_operand:P 1 "" "")
11779 (match_operand:P 2 "gpc_reg_operand" "b")]
11780 UNSPEC_TOCREL)))]
11781 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11782 "addis %0,%1@u(%2)")
11784 (define_insn "*largetoc_high_plus"
11785 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11786 (high:DI
11787 (plus:DI
11788 (unspec [(match_operand:DI 1 "" "")
11789 (match_operand:DI 2 "gpc_reg_operand" "b")]
11790 UNSPEC_TOCREL)
11791 (match_operand:DI 3 "add_cint_operand" "n"))))]
11792 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11793 "addis %0,%2,%1+%3@toc@ha")
11795 (define_insn "*largetoc_high_plus_aix<mode>"
11796 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11797 (high:P
11798 (plus:P
11799 (unspec [(match_operand:P 1 "" "")
11800 (match_operand:P 2 "gpc_reg_operand" "b")]
11801 UNSPEC_TOCREL)
11802 (match_operand:P 3 "add_cint_operand" "n"))))]
11803 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11804 "addis %0,%1+%3@u(%2)")
11806 (define_insn "*largetoc_low"
11807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11808 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
11809 (match_operand:DI 2 "" "")))]
11810 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11811 "@
11812 addi %0,%1,%2@l
11813 addic %0,%1,%2@l")
11815 (define_insn "*largetoc_low_aix<mode>"
11816 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11817 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
11818 (match_operand:P 2 "" "")))]
11819 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11820 "la %0,%2@l(%1)")
11822 (define_insn_and_split "*tocref<mode>"
11823 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11824 (match_operand:P 1 "small_toc_ref" "R"))]
11825 "TARGET_TOC"
11826 "la %0,%a1"
11827 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
11828 [(set (match_dup 0) (high:P (match_dup 1)))
11829 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
11831 ;; Elf specific ways of loading addresses for non-PIC code.
11832 ;; The output of this could be r0, but we make a very strong
11833 ;; preference for a base register because it will usually
11834 ;; be needed there.
11835 (define_insn "elf_high"
11836 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11837 (high:SI (match_operand 1 "" "")))]
11838 "TARGET_ELF && ! TARGET_64BIT"
11839 "lis %0,%1@ha")
11841 (define_insn "elf_low"
11842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11843 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11844 (match_operand 2 "" "")))]
11845 "TARGET_ELF && ! TARGET_64BIT"
11846 "@
11847 la %0,%2@l(%1)
11848 addic %0,%1,%K2")
11849 \f
11850 ;; Call and call_value insns
11851 (define_expand "call"
11852 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11853 (match_operand 1 "" ""))
11854 (use (match_operand 2 "" ""))
11855 (clobber (reg:SI LR_REGNO))])]
11856 ""
11857 "
11858 {
11859 #if TARGET_MACHO
11860 if (MACHOPIC_INDIRECT)
11861 operands[0] = machopic_indirect_call_target (operands[0]);
11862 #endif
11864 gcc_assert (GET_CODE (operands[0]) == MEM);
11865 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11867 operands[0] = XEXP (operands[0], 0);
11869 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11870 {
11871 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11872 DONE;
11873 }
11875 if (GET_CODE (operands[0]) != SYMBOL_REF
11876 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11877 {
11878 if (INTVAL (operands[2]) & CALL_LONG)
11879 operands[0] = rs6000_longcall_ref (operands[0]);
11881 switch (DEFAULT_ABI)
11882 {
11883 case ABI_V4:
11884 case ABI_DARWIN:
11885 operands[0] = force_reg (Pmode, operands[0]);
11886 break;
11888 default:
11889 gcc_unreachable ();
11890 }
11891 }
11892 }")
11894 (define_expand "call_value"
11895 [(parallel [(set (match_operand 0 "" "")
11896 (call (mem:SI (match_operand 1 "address_operand" ""))
11897 (match_operand 2 "" "")))
11898 (use (match_operand 3 "" ""))
11899 (clobber (reg:SI LR_REGNO))])]
11900 ""
11901 "
11902 {
11903 #if TARGET_MACHO
11904 if (MACHOPIC_INDIRECT)
11905 operands[1] = machopic_indirect_call_target (operands[1]);
11906 #endif
11908 gcc_assert (GET_CODE (operands[1]) == MEM);
11909 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11911 operands[1] = XEXP (operands[1], 0);
11913 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11914 {
11915 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
11916 DONE;
11917 }
11919 if (GET_CODE (operands[1]) != SYMBOL_REF
11920 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11921 {
11922 if (INTVAL (operands[3]) & CALL_LONG)
11923 operands[1] = rs6000_longcall_ref (operands[1]);
11925 switch (DEFAULT_ABI)
11926 {
11927 case ABI_V4:
11928 case ABI_DARWIN:
11929 operands[1] = force_reg (Pmode, operands[1]);
11930 break;
11932 default:
11933 gcc_unreachable ();
11934 }
11935 }
11936 }")
11938 ;; Call to function in current module. No TOC pointer reload needed.
11939 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11940 ;; either the function was not prototyped, or it was prototyped as a
11941 ;; variable argument function. It is > 0 if FP registers were passed
11942 ;; and < 0 if they were not.
11944 (define_insn "*call_local32"
11945 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11946 (match_operand 1 "" "g,g"))
11947 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11948 (clobber (reg:SI LR_REGNO))]
11949 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11950 "*
11951 {
11952 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11953 output_asm_insn (\"crxor 6,6,6\", operands);
11955 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11956 output_asm_insn (\"creqv 6,6,6\", operands);
11958 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11959 }"
11960 [(set_attr "type" "branch")
11961 (set_attr "length" "4,8")])
11963 (define_insn "*call_local64"
11964 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11965 (match_operand 1 "" "g,g"))
11966 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11967 (clobber (reg:SI LR_REGNO))]
11968 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11969 "*
11970 {
11971 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11972 output_asm_insn (\"crxor 6,6,6\", operands);
11974 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11975 output_asm_insn (\"creqv 6,6,6\", operands);
11977 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11978 }"
11979 [(set_attr "type" "branch")
11980 (set_attr "length" "4,8")])
11982 (define_insn "*call_value_local32"
11983 [(set (match_operand 0 "" "")
11984 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11985 (match_operand 2 "" "g,g")))
11986 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11987 (clobber (reg:SI LR_REGNO))]
11988 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11989 "*
11990 {
11991 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11992 output_asm_insn (\"crxor 6,6,6\", operands);
11994 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11995 output_asm_insn (\"creqv 6,6,6\", operands);
11997 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11998 }"
11999 [(set_attr "type" "branch")
12000 (set_attr "length" "4,8")])
12003 (define_insn "*call_value_local64"
12004 [(set (match_operand 0 "" "")
12005 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12006 (match_operand 2 "" "g,g")))
12007 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12008 (clobber (reg:SI LR_REGNO))]
12009 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12010 "*
12011 {
12012 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12013 output_asm_insn (\"crxor 6,6,6\", operands);
12015 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12016 output_asm_insn (\"creqv 6,6,6\", operands);
12018 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12019 }"
12020 [(set_attr "type" "branch")
12021 (set_attr "length" "4,8")])
12024 ;; A function pointer under System V is just a normal pointer
12025 ;; operands[0] is the function pointer
12026 ;; operands[1] is the stack size to clean up
12027 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12028 ;; which indicates how to set cr1
12030 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12031 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12032 (match_operand 1 "" "g,g,g,g"))
12033 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12034 (clobber (reg:SI LR_REGNO))]
12035 "DEFAULT_ABI == ABI_V4
12036 || DEFAULT_ABI == ABI_DARWIN"
12037 {
12038 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12039 output_asm_insn ("crxor 6,6,6", operands);
12041 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12042 output_asm_insn ("creqv 6,6,6", operands);
12044 return "b%T0l";
12045 }
12046 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12047 (set_attr "length" "4,4,8,8")])
12049 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12050 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12051 (match_operand 1 "" "g,g"))
12052 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12053 (clobber (reg:SI LR_REGNO))]
12054 "(DEFAULT_ABI == ABI_DARWIN
12055 || (DEFAULT_ABI == ABI_V4
12056 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12057 {
12058 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12059 output_asm_insn ("crxor 6,6,6", operands);
12061 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12062 output_asm_insn ("creqv 6,6,6", operands);
12064 #if TARGET_MACHO
12065 return output_call(insn, operands, 0, 2);
12066 #else
12067 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12068 {
12069 gcc_assert (!TARGET_SECURE_PLT);
12070 return "bl %z0@plt";
12071 }
12072 else
12073 return "bl %z0";
12074 #endif
12075 }
12076 "DEFAULT_ABI == ABI_V4
12077 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12078 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12079 [(parallel [(call (mem:SI (match_dup 0))
12080 (match_dup 1))
12081 (use (match_dup 2))
12082 (use (match_dup 3))
12083 (clobber (reg:SI LR_REGNO))])]
12084 {
12085 operands[3] = pic_offset_table_rtx;
12086 }
12087 [(set_attr "type" "branch,branch")
12088 (set_attr "length" "4,8")])
12090 (define_insn "*call_nonlocal_sysv_secure<mode>"
12091 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12092 (match_operand 1 "" "g,g"))
12093 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12094 (use (match_operand:SI 3 "register_operand" "r,r"))
12095 (clobber (reg:SI LR_REGNO))]
12096 "(DEFAULT_ABI == ABI_V4
12097 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12098 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12099 {
12100 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12101 output_asm_insn ("crxor 6,6,6", operands);
12103 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12104 output_asm_insn ("creqv 6,6,6", operands);
12106 if (flag_pic == 2)
12107 /* The magic 32768 offset here and in the other sysv call insns
12108 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12109 See sysv4.h:toc_section. */
12110 return "bl %z0+32768@plt";
12111 else
12112 return "bl %z0@plt";
12113 }
12114 [(set_attr "type" "branch,branch")
12115 (set_attr "length" "4,8")])
12117 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12118 [(set (match_operand 0 "" "")
12119 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12120 (match_operand 2 "" "g,g,g,g")))
12121 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12122 (clobber (reg:SI LR_REGNO))]
12123 "DEFAULT_ABI == ABI_V4
12124 || DEFAULT_ABI == ABI_DARWIN"
12125 {
12126 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12127 output_asm_insn ("crxor 6,6,6", operands);
12129 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12130 output_asm_insn ("creqv 6,6,6", operands);
12132 return "b%T1l";
12133 }
12134 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12135 (set_attr "length" "4,4,8,8")])
12137 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12138 [(set (match_operand 0 "" "")
12139 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12140 (match_operand 2 "" "g,g")))
12141 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12142 (clobber (reg:SI LR_REGNO))]
12143 "(DEFAULT_ABI == ABI_DARWIN
12144 || (DEFAULT_ABI == ABI_V4
12145 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12146 {
12147 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12148 output_asm_insn ("crxor 6,6,6", operands);
12150 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12151 output_asm_insn ("creqv 6,6,6", operands);
12153 #if TARGET_MACHO
12154 return output_call(insn, operands, 1, 3);
12155 #else
12156 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12157 {
12158 gcc_assert (!TARGET_SECURE_PLT);
12159 return "bl %z1@plt";
12160 }
12161 else
12162 return "bl %z1";
12163 #endif
12164 }
12165 "DEFAULT_ABI == ABI_V4
12166 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12167 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12168 [(parallel [(set (match_dup 0)
12169 (call (mem:SI (match_dup 1))
12170 (match_dup 2)))
12171 (use (match_dup 3))
12172 (use (match_dup 4))
12173 (clobber (reg:SI LR_REGNO))])]
12174 {
12175 operands[4] = pic_offset_table_rtx;
12176 }
12177 [(set_attr "type" "branch,branch")
12178 (set_attr "length" "4,8")])
12180 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12181 [(set (match_operand 0 "" "")
12182 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12183 (match_operand 2 "" "g,g")))
12184 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12185 (use (match_operand:SI 4 "register_operand" "r,r"))
12186 (clobber (reg:SI LR_REGNO))]
12187 "(DEFAULT_ABI == ABI_V4
12188 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12189 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12190 {
12191 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12192 output_asm_insn ("crxor 6,6,6", operands);
12194 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12195 output_asm_insn ("creqv 6,6,6", operands);
12197 if (flag_pic == 2)
12198 return "bl %z1+32768@plt";
12199 else
12200 return "bl %z1@plt";
12201 }
12202 [(set_attr "type" "branch,branch")
12203 (set_attr "length" "4,8")])
12206 ;; Call to AIX abi function in the same module.
12208 (define_insn "*call_local_aix<mode>"
12209 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
12210 (match_operand 1 "" "g"))
12211 (clobber (reg:P LR_REGNO))]
12212 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12213 "bl %z0"
12214 [(set_attr "type" "branch")
12215 (set_attr "length" "4")])
12217 (define_insn "*call_value_local_aix<mode>"
12218 [(set (match_operand 0 "" "")
12219 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
12220 (match_operand 2 "" "g")))
12221 (clobber (reg:P LR_REGNO))]
12222 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12223 "bl %z1"
12224 [(set_attr "type" "branch")
12225 (set_attr "length" "4")])
12227 ;; Call to AIX abi function which may be in another module.
12228 ;; Restore the TOC pointer (r2) after the call.
12230 (define_insn "*call_nonlocal_aix<mode>"
12231 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
12232 (match_operand 1 "" "g"))
12233 (clobber (reg:P LR_REGNO))]
12234 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12235 "bl %z0\;nop"
12236 [(set_attr "type" "branch")
12237 (set_attr "length" "8")])
12239 (define_insn "*call_value_nonlocal_aix<mode>"
12240 [(set (match_operand 0 "" "")
12241 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
12242 (match_operand 2 "" "g")))
12243 (clobber (reg:P LR_REGNO))]
12244 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12245 "bl %z1\;nop"
12246 [(set_attr "type" "branch")
12247 (set_attr "length" "8")])
12249 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
12250 ;; Operand0 is the addresss of the function to call
12251 ;; Operand2 is the location in the function descriptor to load r2 from
12252 ;; Operand3 is the stack location to hold the current TOC pointer
12254 (define_insn "*call_indirect_aix<mode>"
12255 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12256 (match_operand 1 "" "g,g"))
12257 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12258 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12259 (clobber (reg:P LR_REGNO))]
12260 "DEFAULT_ABI == ABI_AIX"
12261 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12262 [(set_attr "type" "jmpreg")
12263 (set_attr "length" "12")])
12265 (define_insn "*call_value_indirect_aix<mode>"
12266 [(set (match_operand 0 "" "")
12267 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12268 (match_operand 2 "" "g,g")))
12269 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12270 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
12271 (clobber (reg:P LR_REGNO))]
12272 "DEFAULT_ABI == ABI_AIX"
12273 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12274 [(set_attr "type" "jmpreg")
12275 (set_attr "length" "12")])
12277 ;; Call to indirect functions with the ELFv2 ABI.
12278 ;; Operand0 is the addresss of the function to call
12279 ;; Operand2 is the stack location to hold the current TOC pointer
12281 (define_insn "*call_indirect_elfv2<mode>"
12282 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12283 (match_operand 1 "" "g,g"))
12284 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12285 (clobber (reg:P LR_REGNO))]
12286 "DEFAULT_ABI == ABI_ELFv2"
12287 "b%T0l\;<ptrload> 2,%2"
12288 [(set_attr "type" "jmpreg")
12289 (set_attr "length" "8")])
12291 (define_insn "*call_value_indirect_elfv2<mode>"
12292 [(set (match_operand 0 "" "")
12293 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12294 (match_operand 2 "" "g,g")))
12295 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12296 (clobber (reg:P LR_REGNO))]
12297 "DEFAULT_ABI == ABI_ELFv2"
12298 "b%T1l\;<ptrload> 2,%3"
12299 [(set_attr "type" "jmpreg")
12300 (set_attr "length" "8")])
12303 ;; Call subroutine returning any type.
12304 (define_expand "untyped_call"
12305 [(parallel [(call (match_operand 0 "" "")
12306 (const_int 0))
12307 (match_operand 1 "" "")
12308 (match_operand 2 "" "")])]
12309 ""
12310 "
12311 {
12312 int i;
12314 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12316 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12317 {
12318 rtx set = XVECEXP (operands[2], 0, i);
12319 emit_move_insn (SET_DEST (set), SET_SRC (set));
12320 }
12322 /* The optimizer does not know that the call sets the function value
12323 registers we stored in the result block. We avoid problems by
12324 claiming that all hard registers are used and clobbered at this
12325 point. */
12326 emit_insn (gen_blockage ());
12328 DONE;
12329 }")
12331 ;; sibling call patterns
12332 (define_expand "sibcall"
12333 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12334 (match_operand 1 "" ""))
12335 (use (match_operand 2 "" ""))
12336 (use (reg:SI LR_REGNO))
12337 (simple_return)])]
12338 ""
12339 "
12340 {
12341 #if TARGET_MACHO
12342 if (MACHOPIC_INDIRECT)
12343 operands[0] = machopic_indirect_call_target (operands[0]);
12344 #endif
12346 gcc_assert (GET_CODE (operands[0]) == MEM);
12347 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12349 operands[0] = XEXP (operands[0], 0);
12351 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12352 {
12353 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
12354 DONE;
12355 }
12356 }")
12358 (define_expand "sibcall_value"
12359 [(parallel [(set (match_operand 0 "register_operand" "")
12360 (call (mem:SI (match_operand 1 "address_operand" ""))
12361 (match_operand 2 "" "")))
12362 (use (match_operand 3 "" ""))
12363 (use (reg:SI LR_REGNO))
12364 (simple_return)])]
12365 ""
12366 "
12367 {
12368 #if TARGET_MACHO
12369 if (MACHOPIC_INDIRECT)
12370 operands[1] = machopic_indirect_call_target (operands[1]);
12371 #endif
12373 gcc_assert (GET_CODE (operands[1]) == MEM);
12374 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12376 operands[1] = XEXP (operands[1], 0);
12378 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12379 {
12380 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
12381 DONE;
12382 }
12383 }")
12385 ;; this and similar patterns must be marked as using LR, otherwise
12386 ;; dataflow will try to delete the store into it. This is true
12387 ;; even when the actual reg to jump to is in CTR, when LR was
12388 ;; saved and restored around the PIC-setting BCL.
12389 (define_insn "*sibcall_local32"
12390 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12391 (match_operand 1 "" "g,g"))
12392 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12393 (use (reg:SI LR_REGNO))
12394 (simple_return)]
12395 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12396 "*
12397 {
12398 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12399 output_asm_insn (\"crxor 6,6,6\", operands);
12401 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12402 output_asm_insn (\"creqv 6,6,6\", operands);
12404 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12405 }"
12406 [(set_attr "type" "branch")
12407 (set_attr "length" "4,8")])
12409 (define_insn "*sibcall_local64"
12410 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12411 (match_operand 1 "" "g,g"))
12412 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12413 (use (reg:SI LR_REGNO))
12414 (simple_return)]
12415 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12416 "*
12417 {
12418 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12419 output_asm_insn (\"crxor 6,6,6\", operands);
12421 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12422 output_asm_insn (\"creqv 6,6,6\", operands);
12424 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12425 }"
12426 [(set_attr "type" "branch")
12427 (set_attr "length" "4,8")])
12429 (define_insn "*sibcall_value_local32"
12430 [(set (match_operand 0 "" "")
12431 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12432 (match_operand 2 "" "g,g")))
12433 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12434 (use (reg:SI LR_REGNO))
12435 (simple_return)]
12436 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12437 "*
12438 {
12439 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12440 output_asm_insn (\"crxor 6,6,6\", operands);
12442 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12443 output_asm_insn (\"creqv 6,6,6\", operands);
12445 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12446 }"
12447 [(set_attr "type" "branch")
12448 (set_attr "length" "4,8")])
12450 (define_insn "*sibcall_value_local64"
12451 [(set (match_operand 0 "" "")
12452 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12453 (match_operand 2 "" "g,g")))
12454 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12455 (use (reg:SI LR_REGNO))
12456 (simple_return)]
12457 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12458 "*
12459 {
12460 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12461 output_asm_insn (\"crxor 6,6,6\", operands);
12463 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12464 output_asm_insn (\"creqv 6,6,6\", operands);
12466 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12467 }"
12468 [(set_attr "type" "branch")
12469 (set_attr "length" "4,8")])
12471 (define_insn "*sibcall_nonlocal_sysv<mode>"
12472 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12473 (match_operand 1 "" ""))
12474 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12475 (use (reg:SI LR_REGNO))
12476 (simple_return)]
12477 "(DEFAULT_ABI == ABI_DARWIN
12478 || DEFAULT_ABI == ABI_V4)
12479 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12480 "*
12481 {
12482 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12483 output_asm_insn (\"crxor 6,6,6\", operands);
12485 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12486 output_asm_insn (\"creqv 6,6,6\", operands);
12488 if (which_alternative >= 2)
12489 return \"b%T0\";
12490 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12491 {
12492 gcc_assert (!TARGET_SECURE_PLT);
12493 return \"b %z0@plt\";
12494 }
12495 else
12496 return \"b %z0\";
12497 }"
12498 [(set_attr "type" "branch")
12499 (set_attr "length" "4,8,4,8")])
12501 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12502 [(set (match_operand 0 "" "")
12503 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12504 (match_operand 2 "" "")))
12505 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12506 (use (reg:SI LR_REGNO))
12507 (simple_return)]
12508 "(DEFAULT_ABI == ABI_DARWIN
12509 || DEFAULT_ABI == ABI_V4)
12510 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12511 "*
12512 {
12513 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12514 output_asm_insn (\"crxor 6,6,6\", operands);
12516 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12517 output_asm_insn (\"creqv 6,6,6\", operands);
12519 if (which_alternative >= 2)
12520 return \"b%T1\";
12521 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12522 {
12523 gcc_assert (!TARGET_SECURE_PLT);
12524 return \"b %z1@plt\";
12525 }
12526 else
12527 return \"b %z1\";
12528 }"
12529 [(set_attr "type" "branch")
12530 (set_attr "length" "4,8,4,8")])
12532 ;; AIX ABI sibling call patterns.
12534 (define_insn "*sibcall_aix<mode>"
12535 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12536 (match_operand 1 "" "g,g"))
12537 (simple_return)]
12538 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12539 "@
12540 b %z0
12541 b%T0"
12542 [(set_attr "type" "branch")
12543 (set_attr "length" "4")])
12545 (define_insn "*sibcall_value_aix<mode>"
12546 [(set (match_operand 0 "" "")
12547 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12548 (match_operand 2 "" "g,g")))
12549 (simple_return)]
12550 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12551 "@
12552 b %z1
12553 b%T1"
12554 [(set_attr "type" "branch")
12555 (set_attr "length" "4")])
12557 (define_expand "sibcall_epilogue"
12558 [(use (const_int 0))]
12559 ""
12560 {
12561 if (!TARGET_SCHED_PROLOG)
12562 emit_insn (gen_blockage ());
12563 rs6000_emit_epilogue (TRUE);
12564 DONE;
12565 })
12567 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12568 ;; all of memory. This blocks insns from being moved across this point.
12570 (define_insn "blockage"
12571 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12572 ""
12573 "")
12575 (define_expand "probe_stack"
12576 [(set (match_operand 0 "memory_operand" "=m")
12577 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12578 ""
12579 {
12580 if (TARGET_64BIT)
12581 emit_insn (gen_probe_stack_di (operands[0]));
12582 else
12583 emit_insn (gen_probe_stack_si (operands[0]));
12584 DONE;
12585 })
12587 (define_insn "probe_stack_<mode>"
12588 [(set (match_operand:P 0 "memory_operand" "=m")
12589 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
12590 ""
12591 {
12592 operands[1] = gen_rtx_REG (Pmode, 0);
12593 return "st<wd>%U0%X0 %1,%0";
12594 }
12595 [(set_attr "type" "store")
12596 (set (attr "update")
12597 (if_then_else (match_operand 0 "update_address_mem")
12598 (const_string "yes")
12599 (const_string "no")))
12600 (set (attr "indexed")
12601 (if_then_else (match_operand 0 "indexed_address_mem")
12602 (const_string "yes")
12603 (const_string "no")))
12604 (set_attr "length" "4")])
12606 (define_insn "probe_stack_range<P:mode>"
12607 [(set (match_operand:P 0 "register_operand" "=r")
12608 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
12609 (match_operand:P 2 "register_operand" "r")]
12610 UNSPECV_PROBE_STACK_RANGE))]
12611 ""
12612 "* return output_probe_stack_range (operands[0], operands[2]);"
12613 [(set_attr "type" "three")])
12614 \f
12615 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12616 ;; signed & unsigned, and one type of branch.
12617 ;;
12618 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12619 ;; insns, and branches.
12621 (define_expand "cbranch<mode>4"
12622 [(use (match_operator 0 "rs6000_cbranch_operator"
12623 [(match_operand:GPR 1 "gpc_reg_operand" "")
12624 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12625 (use (match_operand 3 ""))]
12626 ""
12627 "
12628 {
12629 /* Take care of the possibility that operands[2] might be negative but
12630 this might be a logical operation. That insn doesn't exist. */
12631 if (GET_CODE (operands[2]) == CONST_INT
12632 && INTVAL (operands[2]) < 0)
12633 {
12634 operands[2] = force_reg (<MODE>mode, operands[2]);
12635 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12636 GET_MODE (operands[0]),
12637 operands[1], operands[2]);
12638 }
12640 rs6000_emit_cbranch (<MODE>mode, operands);
12641 DONE;
12642 }")
12644 (define_expand "cbranch<mode>4"
12645 [(use (match_operator 0 "rs6000_cbranch_operator"
12646 [(match_operand:FP 1 "gpc_reg_operand" "")
12647 (match_operand:FP 2 "gpc_reg_operand" "")]))
12648 (use (match_operand 3 ""))]
12649 ""
12650 "
12651 {
12652 rs6000_emit_cbranch (<MODE>mode, operands);
12653 DONE;
12654 }")
12656 (define_expand "cstore<mode>4"
12657 [(use (match_operator 1 "rs6000_cbranch_operator"
12658 [(match_operand:GPR 2 "gpc_reg_operand" "")
12659 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12660 (clobber (match_operand:SI 0 "register_operand"))]
12661 ""
12662 "
12663 {
12664 /* Take care of the possibility that operands[3] might be negative but
12665 this might be a logical operation. That insn doesn't exist. */
12666 if (GET_CODE (operands[3]) == CONST_INT
12667 && INTVAL (operands[3]) < 0)
12668 {
12669 operands[3] = force_reg (<MODE>mode, operands[3]);
12670 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12671 GET_MODE (operands[1]),
12672 operands[2], operands[3]);
12673 }
12675 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12676 For SEQ, likewise, except that comparisons with zero should be done
12677 with an scc insns. However, due to the order that combine see the
12678 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12679 the cases we don't want to handle or are best handled by portable
12680 code. */
12681 if (GET_CODE (operands[1]) == NE)
12682 FAIL;
12683 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12684 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12685 && operands[3] == const0_rtx)
12686 FAIL;
12687 rs6000_emit_sCOND (<MODE>mode, operands);
12688 DONE;
12689 }")
12691 (define_expand "cstore<mode>4"
12692 [(use (match_operator 1 "rs6000_cbranch_operator"
12693 [(match_operand:FP 2 "gpc_reg_operand" "")
12694 (match_operand:FP 3 "gpc_reg_operand" "")]))
12695 (clobber (match_operand:SI 0 "register_operand"))]
12696 ""
12697 "
12698 {
12699 rs6000_emit_sCOND (<MODE>mode, operands);
12700 DONE;
12701 }")
12704 (define_expand "stack_protect_set"
12705 [(match_operand 0 "memory_operand" "")
12706 (match_operand 1 "memory_operand" "")]
12707 ""
12708 {
12709 #ifdef TARGET_THREAD_SSP_OFFSET
12710 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12711 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12712 operands[1] = gen_rtx_MEM (Pmode, addr);
12713 #endif
12714 if (TARGET_64BIT)
12715 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12716 else
12717 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12718 DONE;
12719 })
12721 (define_insn "stack_protect_setsi"
12722 [(set (match_operand:SI 0 "memory_operand" "=m")
12723 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12724 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12725 "TARGET_32BIT"
12726 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
12727 [(set_attr "type" "three")
12728 (set_attr "length" "12")])
12730 (define_insn "stack_protect_setdi"
12731 [(set (match_operand:DI 0 "memory_operand" "=Y")
12732 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
12733 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12734 "TARGET_64BIT"
12735 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
12736 [(set_attr "type" "three")
12737 (set_attr "length" "12")])
12739 (define_expand "stack_protect_test"
12740 [(match_operand 0 "memory_operand" "")
12741 (match_operand 1 "memory_operand" "")
12742 (match_operand 2 "" "")]
12743 ""
12744 {
12745 rtx test, op0, op1;
12746 #ifdef TARGET_THREAD_SSP_OFFSET
12747 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12748 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12749 operands[1] = gen_rtx_MEM (Pmode, addr);
12750 #endif
12751 op0 = operands[0];
12752 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12753 test = gen_rtx_EQ (VOIDmode, op0, op1);
12754 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12755 DONE;
12756 })
12758 (define_insn "stack_protect_testsi"
12759 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12760 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12761 (match_operand:SI 2 "memory_operand" "m,m")]
12762 UNSPEC_SP_TEST))
12763 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12764 (clobber (match_scratch:SI 3 "=&r,&r"))]
12765 "TARGET_32BIT"
12766 "@
12767 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12768 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
12769 [(set_attr "length" "16,20")])
12771 (define_insn "stack_protect_testdi"
12772 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12773 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
12774 (match_operand:DI 2 "memory_operand" "Y,Y")]
12775 UNSPEC_SP_TEST))
12776 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12777 (clobber (match_scratch:DI 3 "=&r,&r"))]
12778 "TARGET_64BIT"
12779 "@
12780 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12781 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
12782 [(set_attr "length" "16,20")])
12784 \f
12785 ;; Here are the actual compare insns.
12786 (define_insn "*cmp<mode>_internal1"
12787 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12788 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12789 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12790 ""
12791 "cmp<wd>%I2 %0,%1,%2"
12792 [(set_attr "type" "cmp")])
12794 ;; If we are comparing a register for equality with a large constant,
12795 ;; we can do this with an XOR followed by a compare. But this is profitable
12796 ;; only if the large constant is only used for the comparison (and in this
12797 ;; case we already have a register to reuse as scratch).
12798 ;;
12799 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12800 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12802 (define_peephole2
12803 [(set (match_operand:SI 0 "register_operand")
12804 (match_operand:SI 1 "logical_const_operand" ""))
12805 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12806 [(match_dup 0)
12807 (match_operand:SI 2 "logical_const_operand" "")]))
12808 (set (match_operand:CC 4 "cc_reg_operand" "")
12809 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12810 (match_dup 0)))
12811 (set (pc)
12812 (if_then_else (match_operator 6 "equality_operator"
12813 [(match_dup 4) (const_int 0)])
12814 (match_operand 7 "" "")
12815 (match_operand 8 "" "")))]
12816 "peep2_reg_dead_p (3, operands[0])
12817 && peep2_reg_dead_p (4, operands[4])"
12818 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12819 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12820 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12822 {
12823 /* Get the constant we are comparing against, and see what it looks like
12824 when sign-extended from 16 to 32 bits. Then see what constant we could
12825 XOR with SEXTC to get the sign-extended value. */
12826 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12827 SImode,
12828 operands[1], operands[2]);
12829 HOST_WIDE_INT c = INTVAL (cnst);
12830 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12831 HOST_WIDE_INT xorv = c ^ sextc;
12833 operands[9] = GEN_INT (xorv);
12834 operands[10] = GEN_INT (sextc);
12835 })
12837 (define_insn "*cmpsi_internal2"
12838 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12839 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12840 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12841 ""
12842 "cmplw%I2 %0,%1,%b2"
12843 [(set_attr "type" "cmp")])
12845 (define_insn "*cmpdi_internal2"
12846 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12847 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12848 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12849 ""
12850 "cmpld%I2 %0,%1,%b2"
12851 [(set_attr "type" "cmp")])
12853 ;; The following two insns don't exist as single insns, but if we provide
12854 ;; them, we can swap an add and compare, which will enable us to overlap more
12855 ;; of the required delay between a compare and branch. We generate code for
12856 ;; them by splitting.
12858 (define_insn ""
12859 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12860 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12861 (match_operand:SI 2 "short_cint_operand" "i")))
12862 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12863 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12864 ""
12865 "#"
12866 [(set_attr "length" "8")])
12868 (define_insn ""
12869 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12870 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12871 (match_operand:SI 2 "u_short_cint_operand" "i")))
12872 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12873 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12874 ""
12875 "#"
12876 [(set_attr "length" "8")])
12878 (define_split
12879 [(set (match_operand:CC 3 "cc_reg_operand" "")
12880 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12881 (match_operand:SI 2 "short_cint_operand" "")))
12882 (set (match_operand:SI 0 "gpc_reg_operand" "")
12883 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12884 ""
12885 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12886 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12888 (define_split
12889 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12890 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12891 (match_operand:SI 2 "u_short_cint_operand" "")))
12892 (set (match_operand:SI 0 "gpc_reg_operand" "")
12893 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12894 ""
12895 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12896 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12898 ;; Only need to compare second words if first words equal
12899 (define_insn "*cmptf_internal1"
12900 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12901 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12902 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12903 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12904 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12905 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12906 [(set_attr "type" "fpcompare")
12907 (set_attr "length" "12")])
12909 (define_insn_and_split "*cmptf_internal2"
12910 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12911 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12912 (match_operand:TF 2 "gpc_reg_operand" "d")))
12913 (clobber (match_scratch:DF 3 "=d"))
12914 (clobber (match_scratch:DF 4 "=d"))
12915 (clobber (match_scratch:DF 5 "=d"))
12916 (clobber (match_scratch:DF 6 "=d"))
12917 (clobber (match_scratch:DF 7 "=d"))
12918 (clobber (match_scratch:DF 8 "=d"))
12919 (clobber (match_scratch:DF 9 "=d"))
12920 (clobber (match_scratch:DF 10 "=d"))
12921 (clobber (match_scratch:GPR 11 "=b"))]
12922 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12923 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12924 "#"
12925 "&& reload_completed"
12926 [(set (match_dup 3) (match_dup 14))
12927 (set (match_dup 4) (match_dup 15))
12928 (set (match_dup 9) (abs:DF (match_dup 5)))
12929 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12930 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12931 (label_ref (match_dup 12))
12932 (pc)))
12933 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12934 (set (pc) (label_ref (match_dup 13)))
12935 (match_dup 12)
12936 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12937 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12938 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12939 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12940 (match_dup 13)]
12941 {
12942 REAL_VALUE_TYPE rv;
12943 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
12944 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
12946 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12947 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12948 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12949 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12950 operands[12] = gen_label_rtx ();
12951 operands[13] = gen_label_rtx ();
12952 real_inf (&rv);
12953 operands[14] = force_const_mem (DFmode,
12954 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12955 operands[15] = force_const_mem (DFmode,
12956 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12957 DFmode));
12958 if (TARGET_TOC)
12959 {
12960 rtx tocref;
12961 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
12962 operands[14] = gen_const_mem (DFmode, tocref);
12963 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
12964 operands[15] = gen_const_mem (DFmode, tocref);
12965 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12966 set_mem_alias_set (operands[15], get_TOC_alias_set ());
12967 }
12968 })
12969 \f
12970 ;; Now we have the scc insns. We can do some combinations because of the
12971 ;; way the machine works.
12972 ;;
12973 ;; Note that this is probably faster if we can put an insn between the
12974 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12975 ;; cases the insns below which don't use an intermediate CR field will
12976 ;; be used instead.
12977 (define_insn ""
12978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12979 (match_operator:SI 1 "scc_comparison_operator"
12980 [(match_operand 2 "cc_reg_operand" "y")
12981 (const_int 0)]))]
12982 ""
12983 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12984 [(set (attr "type")
12985 (cond [(match_test "TARGET_MFCRF")
12986 (const_string "mfcrf")
12987 ]
12988 (const_string "mfcr")))
12989 (set_attr "length" "8")])
12991 ;; Same as above, but get the GT bit.
12992 (define_insn "move_from_CR_gt_bit"
12993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12994 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12995 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12996 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
12997 [(set_attr "type" "mfcr")
12998 (set_attr "length" "8")])
13000 ;; Same as above, but get the OV/ORDERED bit.
13001 (define_insn "move_from_CR_ov_bit"
13002 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13003 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
13004 UNSPEC_MV_CR_OV))]
13005 "TARGET_ISEL"
13006 "mfcr %0\;rlwinm %0,%0,%t1,1"
13007 [(set_attr "type" "mfcr")
13008 (set_attr "length" "8")])
13010 (define_insn ""
13011 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13012 (match_operator:DI 1 "scc_comparison_operator"
13013 [(match_operand 2 "cc_reg_operand" "y")
13014 (const_int 0)]))]
13015 "TARGET_POWERPC64"
13016 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
13017 [(set (attr "type")
13018 (cond [(match_test "TARGET_MFCRF")
13019 (const_string "mfcrf")
13020 ]
13021 (const_string "mfcr")))
13022 (set_attr "length" "8")])
13024 (define_insn ""
13025 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13026 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13027 [(match_operand 2 "cc_reg_operand" "y,y")
13028 (const_int 0)])
13029 (const_int 0)))
13030 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13031 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13032 "TARGET_32BIT"
13033 "@
13034 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
13035 #"
13036 [(set_attr "type" "delayed_compare")
13037 (set_attr "length" "8,16")])
13039 (define_split
13040 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13041 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13042 [(match_operand 2 "cc_reg_operand" "")
13043 (const_int 0)])
13044 (const_int 0)))
13045 (set (match_operand:SI 3 "gpc_reg_operand" "")
13046 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13047 "TARGET_32BIT && reload_completed"
13048 [(set (match_dup 3)
13049 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13050 (set (match_dup 0)
13051 (compare:CC (match_dup 3)
13052 (const_int 0)))]
13053 "")
13055 (define_insn ""
13056 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13057 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13058 [(match_operand 2 "cc_reg_operand" "y")
13059 (const_int 0)])
13060 (match_operand:SI 3 "const_int_operand" "n")))]
13061 ""
13062 "*
13063 {
13064 int is_bit = ccr_bit (operands[1], 1);
13065 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13066 int count;
13068 if (is_bit >= put_bit)
13069 count = is_bit - put_bit;
13070 else
13071 count = 32 - (put_bit - is_bit);
13073 operands[4] = GEN_INT (count);
13074 operands[5] = GEN_INT (put_bit);
13076 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
13077 }"
13078 [(set (attr "type")
13079 (cond [(match_test "TARGET_MFCRF")
13080 (const_string "mfcrf")
13081 ]
13082 (const_string "mfcr")))
13083 (set_attr "length" "8")])
13085 (define_insn ""
13086 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13087 (compare:CC
13088 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13089 [(match_operand 2 "cc_reg_operand" "y,y")
13090 (const_int 0)])
13091 (match_operand:SI 3 "const_int_operand" "n,n"))
13092 (const_int 0)))
13093 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13094 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13095 (match_dup 3)))]
13096 ""
13097 "*
13098 {
13099 int is_bit = ccr_bit (operands[1], 1);
13100 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13101 int count;
13103 /* Force split for non-cc0 compare. */
13104 if (which_alternative == 1)
13105 return \"#\";
13107 if (is_bit >= put_bit)
13108 count = is_bit - put_bit;
13109 else
13110 count = 32 - (put_bit - is_bit);
13112 operands[5] = GEN_INT (count);
13113 operands[6] = GEN_INT (put_bit);
13115 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
13116 }"
13117 [(set_attr "type" "delayed_compare")
13118 (set_attr "length" "8,16")])
13120 (define_split
13121 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13122 (compare:CC
13123 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13124 [(match_operand 2 "cc_reg_operand" "")
13125 (const_int 0)])
13126 (match_operand:SI 3 "const_int_operand" ""))
13127 (const_int 0)))
13128 (set (match_operand:SI 4 "gpc_reg_operand" "")
13129 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13130 (match_dup 3)))]
13131 "reload_completed"
13132 [(set (match_dup 4)
13133 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13134 (match_dup 3)))
13135 (set (match_dup 0)
13136 (compare:CC (match_dup 4)
13137 (const_int 0)))]
13138 "")
13140 ;; There is a 3 cycle delay between consecutive mfcr instructions
13141 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13143 (define_peephole
13144 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13145 (match_operator:SI 1 "scc_comparison_operator"
13146 [(match_operand 2 "cc_reg_operand" "y")
13147 (const_int 0)]))
13148 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13149 (match_operator:SI 4 "scc_comparison_operator"
13150 [(match_operand 5 "cc_reg_operand" "y")
13151 (const_int 0)]))]
13152 "REGNO (operands[2]) != REGNO (operands[5])"
13153 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13154 [(set_attr "type" "mfcr")
13155 (set_attr "length" "12")])
13157 (define_peephole
13158 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13159 (match_operator:DI 1 "scc_comparison_operator"
13160 [(match_operand 2 "cc_reg_operand" "y")
13161 (const_int 0)]))
13162 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13163 (match_operator:DI 4 "scc_comparison_operator"
13164 [(match_operand 5 "cc_reg_operand" "y")
13165 (const_int 0)]))]
13166 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13167 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13168 [(set_attr "type" "mfcr")
13169 (set_attr "length" "12")])
13171 ;; There are some scc insns that can be done directly, without a compare.
13172 ;; These are faster because they don't involve the communications between
13173 ;; the FXU and branch units. In fact, we will be replacing all of the
13174 ;; integer scc insns here or in the portable methods in emit_store_flag.
13175 ;;
13176 ;; Also support (neg (scc ..)) since that construct is used to replace
13177 ;; branches, (plus (scc ..) ..) since that construct is common and
13178 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13179 ;; cases where it is no more expensive than (neg (scc ..)).
13181 ;; Have reload force a constant into a register for the simple insns that
13182 ;; otherwise won't accept constants. We do this because it is faster than
13183 ;; the cmp/mfcr sequence we would otherwise generate.
13185 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13186 (DI "rKJI")])
13188 (define_insn_and_split "*eq<mode>"
13189 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13190 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13191 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13192 ""
13193 "#"
13194 ""
13195 [(set (match_dup 0)
13196 (clz:GPR (match_dup 3)))
13197 (set (match_dup 0)
13198 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13199 {
13200 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13201 {
13202 /* Use output operand as intermediate. */
13203 operands[3] = operands[0];
13205 if (logical_operand (operands[2], <MODE>mode))
13206 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13207 gen_rtx_XOR (<MODE>mode,
13208 operands[1], operands[2])));
13209 else
13210 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13211 gen_rtx_PLUS (<MODE>mode, operands[1],
13212 negate_rtx (<MODE>mode,
13213 operands[2]))));
13214 }
13215 else
13216 operands[3] = operands[1];
13218 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13219 })
13221 (define_insn_and_split "*eq<mode>_compare"
13222 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13223 (compare:CC
13224 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13225 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13226 (const_int 0)))
13227 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13228 (eq:P (match_dup 1) (match_dup 2)))]
13229 "optimize_size"
13230 "#"
13231 "optimize_size"
13232 [(set (match_dup 0)
13233 (clz:P (match_dup 4)))
13234 (parallel [(set (match_dup 3)
13235 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13236 (const_int 0)))
13237 (set (match_dup 0)
13238 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13239 {
13240 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13241 {
13242 /* Use output operand as intermediate. */
13243 operands[4] = operands[0];
13245 if (logical_operand (operands[2], <MODE>mode))
13246 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13247 gen_rtx_XOR (<MODE>mode,
13248 operands[1], operands[2])));
13249 else
13250 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13251 gen_rtx_PLUS (<MODE>mode, operands[1],
13252 negate_rtx (<MODE>mode,
13253 operands[2]))));
13254 }
13255 else
13256 operands[4] = operands[1];
13258 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13259 })
13261 ;; We have insns of the form shown by the first define_insn below. If
13262 ;; there is something inside the comparison operation, we must split it.
13263 (define_split
13264 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13265 (plus:SI (match_operator 1 "comparison_operator"
13266 [(match_operand:SI 2 "" "")
13267 (match_operand:SI 3
13268 "reg_or_cint_operand" "")])
13269 (match_operand:SI 4 "gpc_reg_operand" "")))
13270 (clobber (match_operand:SI 5 "register_operand" ""))]
13271 "! gpc_reg_operand (operands[2], SImode)"
13272 [(set (match_dup 5) (match_dup 2))
13273 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
13274 (match_dup 4)))])
13276 (define_insn "*plus_eqsi"
13277 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13278 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13279 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13280 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13281 "TARGET_32BIT"
13282 "@
13283 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
13284 subfic %0,%1,0\;addze %0,%3
13285 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
13286 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
13287 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
13288 [(set_attr "type" "three,two,three,three,three")
13289 (set_attr "length" "12,8,12,12,12")])
13291 (define_insn "*compare_plus_eqsi"
13292 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13293 (compare:CC
13294 (plus:SI
13295 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13296 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13297 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13298 (const_int 0)))
13299 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13300 "TARGET_32BIT && optimize_size"
13301 "@
13302 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13303 subfic %4,%1,0\;addze. %4,%3
13304 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
13305 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
13306 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13307 #
13308 #
13309 #
13310 #
13311 #"
13312 [(set_attr "type" "compare")
13313 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13315 (define_split
13316 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13317 (compare:CC
13318 (plus:SI
13319 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13320 (match_operand:SI 2 "scc_eq_operand" ""))
13321 (match_operand:SI 3 "gpc_reg_operand" ""))
13322 (const_int 0)))
13323 (clobber (match_scratch:SI 4 ""))]
13324 "TARGET_32BIT && optimize_size && reload_completed"
13325 [(set (match_dup 4)
13326 (plus:SI (eq:SI (match_dup 1)
13327 (match_dup 2))
13328 (match_dup 3)))
13329 (set (match_dup 0)
13330 (compare:CC (match_dup 4)
13331 (const_int 0)))]
13332 "")
13334 (define_insn "*plus_eqsi_compare"
13335 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13336 (compare:CC
13337 (plus:SI
13338 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13339 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13340 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13341 (const_int 0)))
13342 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13343 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13344 "TARGET_32BIT && optimize_size"
13345 "@
13346 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13347 subfic %0,%1,0\;addze. %0,%3
13348 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
13349 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
13350 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13351 #
13352 #
13353 #
13354 #
13355 #"
13356 [(set_attr "type" "compare")
13357 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13359 (define_split
13360 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13361 (compare:CC
13362 (plus:SI
13363 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13364 (match_operand:SI 2 "scc_eq_operand" ""))
13365 (match_operand:SI 3 "gpc_reg_operand" ""))
13366 (const_int 0)))
13367 (set (match_operand:SI 0 "gpc_reg_operand" "")
13368 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13369 "TARGET_32BIT && optimize_size && reload_completed"
13370 [(set (match_dup 0)
13371 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13372 (set (match_dup 4)
13373 (compare:CC (match_dup 0)
13374 (const_int 0)))]
13375 "")
13377 (define_insn "*neg_eq0<mode>"
13378 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13379 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13380 (const_int 0))))]
13381 ""
13382 "addic %0,%1,-1\;subfe %0,%0,%0"
13383 [(set_attr "type" "two")
13384 (set_attr "length" "8")])
13386 (define_insn_and_split "*neg_eq<mode>"
13387 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13388 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13389 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13390 ""
13391 "#"
13392 ""
13393 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13394 {
13395 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13396 {
13397 /* Use output operand as intermediate. */
13398 operands[3] = operands[0];
13400 if (logical_operand (operands[2], <MODE>mode))
13401 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13402 gen_rtx_XOR (<MODE>mode,
13403 operands[1], operands[2])));
13404 else
13405 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13406 gen_rtx_PLUS (<MODE>mode, operands[1],
13407 negate_rtx (<MODE>mode,
13408 operands[2]))));
13409 }
13410 else
13411 operands[3] = operands[1];
13412 })
13414 (define_insn "*ne0_<mode>"
13415 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13416 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13417 (const_int 0)))
13418 (clobber (match_scratch:P 2 "=&r"))]
13419 "!(TARGET_32BIT && TARGET_ISEL)"
13420 "addic %2,%1,-1\;subfe %0,%2,%1"
13421 [(set_attr "type" "two")
13422 (set_attr "length" "8")])
13424 (define_insn "*plus_ne0_<mode>"
13425 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13426 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13427 (const_int 0))
13428 (match_operand:P 2 "gpc_reg_operand" "r")))
13429 (clobber (match_scratch:P 3 "=&r"))]
13430 ""
13431 "addic %3,%1,-1\;addze %0,%2"
13432 [(set_attr "type" "two")
13433 (set_attr "length" "8")])
13435 (define_insn "*compare_plus_ne0_<mode>"
13436 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13437 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13438 (const_int 0))
13439 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13440 (const_int 0)))
13441 (clobber (match_scratch:P 3 "=&r,&r"))
13442 (clobber (match_scratch:P 4 "=X,&r"))]
13443 ""
13444 "@
13445 addic %3,%1,-1\;addze. %3,%2
13446 #"
13447 [(set_attr "type" "compare")
13448 (set_attr "length" "8,12")])
13450 (define_split
13451 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13452 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13453 (const_int 0))
13454 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13455 (clobber (match_scratch:P 3 ""))
13456 (clobber (match_scratch:P 4 ""))]
13457 "reload_completed"
13458 [(parallel [(set (match_dup 3)
13459 (plus:P (ne:P (match_dup 1)
13460 (const_int 0))
13461 (match_dup 2)))
13462 (clobber (match_dup 4))])
13463 (set (match_dup 0)
13464 (compare:CC (match_dup 3)
13465 (const_int 0)))]
13466 "")
13468 ; For combine.
13469 (define_insn "*compare_plus_ne0_<mode>_1"
13470 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13471 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13472 (const_int 0))
13473 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13474 (clobber (match_scratch:P 3 "=&r,&r"))
13475 (clobber (match_scratch:P 4 "=X,&r"))]
13476 ""
13477 "@
13478 addic %3,%1,-1\;addze. %3,%2
13479 #"
13480 [(set_attr "type" "compare")
13481 (set_attr "length" "8,12")])
13483 (define_split
13484 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13485 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13486 (const_int 0))
13487 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13488 (clobber (match_scratch:P 3 ""))
13489 (clobber (match_scratch:P 4 ""))]
13490 "reload_completed"
13491 [(parallel [(set (match_dup 3)
13492 (plus:P (ne:P (match_dup 1)
13493 (const_int 0))
13494 (match_dup 2)))
13495 (clobber (match_dup 4))])
13496 (set (match_dup 0)
13497 (compare:CC (match_dup 3)
13498 (const_int 0)))]
13499 "")
13501 (define_insn "*plus_ne0_<mode>_compare"
13502 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13503 (compare:CC
13504 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13505 (const_int 0))
13506 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13507 (const_int 0)))
13508 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13509 (plus:P (ne:P (match_dup 1)
13510 (const_int 0))
13511 (match_dup 2)))
13512 (clobber (match_scratch:P 3 "=&r,&r"))]
13513 ""
13514 "@
13515 addic %3,%1,-1\;addze. %0,%2
13516 #"
13517 [(set_attr "type" "compare")
13518 (set_attr "length" "8,12")])
13520 (define_split
13521 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13522 (compare:CC
13523 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13524 (const_int 0))
13525 (match_operand:P 2 "gpc_reg_operand" ""))
13526 (const_int 0)))
13527 (set (match_operand:P 0 "gpc_reg_operand" "")
13528 (plus:P (ne:P (match_dup 1)
13529 (const_int 0))
13530 (match_dup 2)))
13531 (clobber (match_scratch:P 3 ""))]
13532 "reload_completed"
13533 [(parallel [(set (match_dup 0)
13534 (plus:P (ne:P (match_dup 1)
13535 (const_int 0))
13536 (match_dup 2)))
13537 (clobber (match_dup 3))])
13538 (set (match_dup 4)
13539 (compare:CC (match_dup 0)
13540 (const_int 0)))]
13541 "")
13543 (define_insn "*leu<mode>"
13544 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13545 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13546 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13547 ""
13548 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
13549 [(set_attr "type" "three")
13550 (set_attr "length" "12")])
13552 (define_insn "*leu<mode>_compare"
13553 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13554 (compare:CC
13555 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13556 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13557 (const_int 0)))
13558 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13559 (leu:P (match_dup 1) (match_dup 2)))]
13560 ""
13561 "@
13562 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
13563 #"
13564 [(set_attr "type" "compare")
13565 (set_attr "length" "12,16")])
13567 (define_split
13568 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13569 (compare:CC
13570 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13571 (match_operand:P 2 "reg_or_short_operand" ""))
13572 (const_int 0)))
13573 (set (match_operand:P 0 "gpc_reg_operand" "")
13574 (leu:P (match_dup 1) (match_dup 2)))]
13575 "reload_completed"
13576 [(set (match_dup 0)
13577 (leu:P (match_dup 1) (match_dup 2)))
13578 (set (match_dup 3)
13579 (compare:CC (match_dup 0)
13580 (const_int 0)))]
13581 "")
13583 (define_insn "*plus_leu<mode>"
13584 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13585 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13586 (match_operand:P 2 "reg_or_short_operand" "rI"))
13587 (match_operand:P 3 "gpc_reg_operand" "r")))]
13588 ""
13589 "subf%I2c %0,%1,%2\;addze %0,%3"
13590 [(set_attr "type" "two")
13591 (set_attr "length" "8")])
13593 (define_insn ""
13594 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13595 (compare:CC
13596 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13597 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13598 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13599 (const_int 0)))
13600 (clobber (match_scratch:SI 4 "=&r,&r"))]
13601 "TARGET_32BIT"
13602 "@
13603 subf%I2c %4,%1,%2\;addze. %4,%3
13604 #"
13605 [(set_attr "type" "compare")
13606 (set_attr "length" "8,12")])
13608 (define_split
13609 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13610 (compare:CC
13611 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13612 (match_operand:SI 2 "reg_or_short_operand" ""))
13613 (match_operand:SI 3 "gpc_reg_operand" ""))
13614 (const_int 0)))
13615 (clobber (match_scratch:SI 4 ""))]
13616 "TARGET_32BIT && reload_completed"
13617 [(set (match_dup 4)
13618 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13619 (match_dup 3)))
13620 (set (match_dup 0)
13621 (compare:CC (match_dup 4)
13622 (const_int 0)))]
13623 "")
13625 (define_insn ""
13626 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13627 (compare:CC
13628 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13629 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13630 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13631 (const_int 0)))
13632 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13633 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13634 "TARGET_32BIT"
13635 "@
13636 subf%I2c %0,%1,%2\;addze. %0,%3
13637 #"
13638 [(set_attr "type" "compare")
13639 (set_attr "length" "8,12")])
13641 (define_split
13642 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13643 (compare:CC
13644 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13645 (match_operand:SI 2 "reg_or_short_operand" ""))
13646 (match_operand:SI 3 "gpc_reg_operand" ""))
13647 (const_int 0)))
13648 (set (match_operand:SI 0 "gpc_reg_operand" "")
13649 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13650 "TARGET_32BIT && reload_completed"
13651 [(set (match_dup 0)
13652 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13653 (set (match_dup 4)
13654 (compare:CC (match_dup 0)
13655 (const_int 0)))]
13656 "")
13658 (define_insn "*neg_leu<mode>"
13659 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13660 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13661 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13662 ""
13663 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
13664 [(set_attr "type" "three")
13665 (set_attr "length" "12")])
13667 (define_insn "*and_neg_leu<mode>"
13668 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13669 (and:P (neg:P
13670 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13671 (match_operand:P 2 "reg_or_short_operand" "rI")))
13672 (match_operand:P 3 "gpc_reg_operand" "r")))]
13673 ""
13674 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
13675 [(set_attr "type" "three")
13676 (set_attr "length" "12")])
13678 (define_insn ""
13679 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13680 (compare:CC
13681 (and:SI (neg:SI
13682 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13683 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13684 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13685 (const_int 0)))
13686 (clobber (match_scratch:SI 4 "=&r,&r"))]
13687 "TARGET_32BIT"
13688 "@
13689 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
13690 #"
13691 [(set_attr "type" "compare")
13692 (set_attr "length" "12,16")])
13694 (define_split
13695 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13696 (compare:CC
13697 (and:SI (neg:SI
13698 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13699 (match_operand:SI 2 "reg_or_short_operand" "")))
13700 (match_operand:SI 3 "gpc_reg_operand" ""))
13701 (const_int 0)))
13702 (clobber (match_scratch:SI 4 ""))]
13703 "TARGET_32BIT && reload_completed"
13704 [(set (match_dup 4)
13705 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13706 (match_dup 3)))
13707 (set (match_dup 0)
13708 (compare:CC (match_dup 4)
13709 (const_int 0)))]
13710 "")
13712 (define_insn ""
13713 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13714 (compare:CC
13715 (and:SI (neg:SI
13716 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13717 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13718 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13719 (const_int 0)))
13720 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13721 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13722 "TARGET_32BIT"
13723 "@
13724 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
13725 #"
13726 [(set_attr "type" "compare")
13727 (set_attr "length" "12,16")])
13729 (define_split
13730 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13731 (compare:CC
13732 (and:SI (neg:SI
13733 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13734 (match_operand:SI 2 "reg_or_short_operand" "")))
13735 (match_operand:SI 3 "gpc_reg_operand" ""))
13736 (const_int 0)))
13737 (set (match_operand:SI 0 "gpc_reg_operand" "")
13738 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13739 "TARGET_32BIT && reload_completed"
13740 [(set (match_dup 0)
13741 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13742 (match_dup 3)))
13743 (set (match_dup 4)
13744 (compare:CC (match_dup 0)
13745 (const_int 0)))]
13746 "")
13748 (define_insn_and_split "*ltu<mode>"
13749 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13750 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13751 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13752 ""
13753 "#"
13754 ""
13755 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13756 (set (match_dup 0) (neg:P (match_dup 0)))]
13757 "")
13759 (define_insn_and_split "*ltu<mode>_compare"
13760 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13761 (compare:CC
13762 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13763 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13764 (const_int 0)))
13765 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13766 (ltu:P (match_dup 1) (match_dup 2)))]
13767 ""
13768 "#"
13769 ""
13770 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13771 (parallel [(set (match_dup 3)
13772 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13773 (set (match_dup 0) (neg:P (match_dup 0)))])]
13774 "")
13776 (define_insn_and_split "*plus_ltu<mode>"
13777 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13778 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13779 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13780 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13781 ""
13782 "#"
13783 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13784 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13785 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13786 "")
13788 (define_insn_and_split "*plus_ltu<mode>_compare"
13789 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13790 (compare:CC
13791 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13792 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13793 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13794 (const_int 0)))
13795 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13796 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13797 ""
13798 "#"
13799 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13800 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13801 (parallel [(set (match_dup 4)
13802 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13803 (const_int 0)))
13804 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13805 "")
13807 (define_insn "*neg_ltu<mode>"
13808 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13809 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13810 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13811 ""
13812 "@
13813 subfc %0,%2,%1\;subfe %0,%0,%0
13814 addic %0,%1,%n2\;subfe %0,%0,%0"
13815 [(set_attr "type" "two")
13816 (set_attr "length" "8")])
13818 (define_insn "*geu<mode>"
13819 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13820 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13821 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13822 ""
13823 "@
13824 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
13825 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
13826 [(set_attr "type" "three")
13827 (set_attr "length" "12")])
13829 (define_insn "*geu<mode>_compare"
13830 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13831 (compare:CC
13832 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13833 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13834 (const_int 0)))
13835 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13836 (geu:P (match_dup 1) (match_dup 2)))]
13837 ""
13838 "@
13839 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
13840 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
13841 #
13842 #"
13843 [(set_attr "type" "compare")
13844 (set_attr "length" "12,12,16,16")])
13846 (define_split
13847 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13848 (compare:CC
13849 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13850 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13851 (const_int 0)))
13852 (set (match_operand:P 0 "gpc_reg_operand" "")
13853 (geu:P (match_dup 1) (match_dup 2)))]
13854 "reload_completed"
13855 [(set (match_dup 0)
13856 (geu:P (match_dup 1) (match_dup 2)))
13857 (set (match_dup 3)
13858 (compare:CC (match_dup 0)
13859 (const_int 0)))]
13860 "")
13862 (define_insn "*plus_geu<mode>"
13863 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13864 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13865 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13866 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13867 ""
13868 "@
13869 subfc %0,%2,%1\;addze %0,%3
13870 addic %0,%1,%n2\;addze %0,%3"
13871 [(set_attr "type" "two")
13872 (set_attr "length" "8")])
13874 (define_insn ""
13875 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13876 (compare:CC
13877 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13878 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13879 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13880 (const_int 0)))
13881 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13882 "TARGET_32BIT"
13883 "@
13884 subfc %4,%2,%1\;addze. %4,%3
13885 addic %4,%1,%n2\;addze. %4,%3
13886 #
13887 #"
13888 [(set_attr "type" "compare")
13889 (set_attr "length" "8,8,12,12")])
13891 (define_split
13892 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13893 (compare:CC
13894 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13895 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13896 (match_operand:SI 3 "gpc_reg_operand" ""))
13897 (const_int 0)))
13898 (clobber (match_scratch:SI 4 ""))]
13899 "TARGET_32BIT && reload_completed"
13900 [(set (match_dup 4)
13901 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13902 (match_dup 3)))
13903 (set (match_dup 0)
13904 (compare:CC (match_dup 4)
13905 (const_int 0)))]
13906 "")
13908 (define_insn ""
13909 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13910 (compare:CC
13911 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13912 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13913 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13914 (const_int 0)))
13915 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13916 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13917 "TARGET_32BIT"
13918 "@
13919 subfc %0,%2,%1\;addze. %0,%3
13920 addic %0,%1,%n2\;addze. %0,%3
13921 #
13922 #"
13923 [(set_attr "type" "compare")
13924 (set_attr "length" "8,8,12,12")])
13926 (define_split
13927 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13928 (compare:CC
13929 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13930 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13931 (match_operand:SI 3 "gpc_reg_operand" ""))
13932 (const_int 0)))
13933 (set (match_operand:SI 0 "gpc_reg_operand" "")
13934 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13935 "TARGET_32BIT && reload_completed"
13936 [(set (match_dup 0)
13937 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13938 (set (match_dup 4)
13939 (compare:CC (match_dup 0)
13940 (const_int 0)))]
13941 "")
13943 (define_insn "*neg_geu<mode>"
13944 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13945 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13946 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13947 ""
13948 "@
13949 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
13950 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
13951 [(set_attr "type" "three")
13952 (set_attr "length" "12")])
13954 (define_insn "*and_neg_geu<mode>"
13955 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13956 (and:P (neg:P
13957 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13958 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13959 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13960 ""
13961 "@
13962 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
13963 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
13964 [(set_attr "type" "three")
13965 (set_attr "length" "12")])
13967 (define_insn ""
13968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13969 (compare:CC
13970 (and:SI (neg:SI
13971 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13972 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13973 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13974 (const_int 0)))
13975 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13976 "TARGET_32BIT"
13977 "@
13978 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
13979 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
13980 #
13981 #"
13982 [(set_attr "type" "compare")
13983 (set_attr "length" "12,12,16,16")])
13985 (define_split
13986 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13987 (compare:CC
13988 (and:SI (neg:SI
13989 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13990 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13991 (match_operand:SI 3 "gpc_reg_operand" ""))
13992 (const_int 0)))
13993 (clobber (match_scratch:SI 4 ""))]
13994 "TARGET_32BIT && reload_completed"
13995 [(set (match_dup 4)
13996 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13997 (match_dup 3)))
13998 (set (match_dup 0)
13999 (compare:CC (match_dup 4)
14000 (const_int 0)))]
14001 "")
14003 (define_insn ""
14004 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14005 (compare:CC
14006 (and:SI (neg:SI
14007 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14008 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14009 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14010 (const_int 0)))
14011 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14012 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14013 "TARGET_32BIT"
14014 "@
14015 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
14016 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
14017 #
14018 #"
14019 [(set_attr "type" "compare")
14020 (set_attr "length" "12,12,16,16")])
14022 (define_split
14023 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14024 (compare:CC
14025 (and:SI (neg:SI
14026 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14027 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14028 (match_operand:SI 3 "gpc_reg_operand" ""))
14029 (const_int 0)))
14030 (set (match_operand:SI 0 "gpc_reg_operand" "")
14031 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14032 "TARGET_32BIT && reload_completed"
14033 [(set (match_dup 0)
14034 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14035 (set (match_dup 4)
14036 (compare:CC (match_dup 0)
14037 (const_int 0)))]
14038 "")
14040 (define_insn "*plus_gt0<mode>"
14041 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14042 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14043 (const_int 0))
14044 (match_operand:P 2 "gpc_reg_operand" "r")))]
14045 ""
14046 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
14047 [(set_attr "type" "three")
14048 (set_attr "length" "12")])
14050 (define_insn ""
14051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14052 (compare:CC
14053 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14054 (const_int 0))
14055 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14056 (const_int 0)))
14057 (clobber (match_scratch:SI 3 "=&r,&r"))]
14058 "TARGET_32BIT"
14059 "@
14060 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14061 #"
14062 [(set_attr "type" "compare")
14063 (set_attr "length" "12,16")])
14065 (define_split
14066 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14067 (compare:CC
14068 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14069 (const_int 0))
14070 (match_operand:SI 2 "gpc_reg_operand" ""))
14071 (const_int 0)))
14072 (clobber (match_scratch:SI 3 ""))]
14073 "TARGET_32BIT && reload_completed"
14074 [(set (match_dup 3)
14075 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14076 (match_dup 2)))
14077 (set (match_dup 0)
14078 (compare:CC (match_dup 3)
14079 (const_int 0)))]
14080 "")
14082 (define_insn ""
14083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14084 (compare:CC
14085 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14086 (const_int 0))
14087 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14088 (const_int 0)))
14089 (clobber (match_scratch:DI 3 "=&r,&r"))]
14090 "TARGET_64BIT"
14091 "@
14092 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14093 #"
14094 [(set_attr "type" "compare")
14095 (set_attr "length" "12,16")])
14097 (define_split
14098 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14099 (compare:CC
14100 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14101 (const_int 0))
14102 (match_operand:DI 2 "gpc_reg_operand" ""))
14103 (const_int 0)))
14104 (clobber (match_scratch:DI 3 ""))]
14105 "TARGET_64BIT && reload_completed"
14106 [(set (match_dup 3)
14107 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14108 (match_dup 2)))
14109 (set (match_dup 0)
14110 (compare:CC (match_dup 3)
14111 (const_int 0)))]
14112 "")
14114 (define_insn ""
14115 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14116 (compare:CC
14117 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14118 (const_int 0))
14119 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14120 (const_int 0)))
14121 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14122 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14123 "TARGET_32BIT"
14124 "@
14125 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14126 #"
14127 [(set_attr "type" "compare")
14128 (set_attr "length" "12,16")])
14130 (define_split
14131 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14132 (compare:CC
14133 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14134 (const_int 0))
14135 (match_operand:SI 2 "gpc_reg_operand" ""))
14136 (const_int 0)))
14137 (set (match_operand:SI 0 "gpc_reg_operand" "")
14138 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14139 "TARGET_32BIT && reload_completed"
14140 [(set (match_dup 0)
14141 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14142 (set (match_dup 3)
14143 (compare:CC (match_dup 0)
14144 (const_int 0)))]
14145 "")
14147 (define_insn ""
14148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14149 (compare:CC
14150 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14151 (const_int 0))
14152 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14153 (const_int 0)))
14154 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14155 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14156 "TARGET_64BIT"
14157 "@
14158 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14159 #"
14160 [(set_attr "type" "compare")
14161 (set_attr "length" "12,16")])
14163 (define_split
14164 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14165 (compare:CC
14166 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14167 (const_int 0))
14168 (match_operand:DI 2 "gpc_reg_operand" ""))
14169 (const_int 0)))
14170 (set (match_operand:DI 0 "gpc_reg_operand" "")
14171 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14172 "TARGET_64BIT && reload_completed"
14173 [(set (match_dup 0)
14174 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14175 (set (match_dup 3)
14176 (compare:CC (match_dup 0)
14177 (const_int 0)))]
14178 "")
14180 (define_insn_and_split "*gtu<mode>"
14181 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14182 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14183 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14184 ""
14185 "#"
14186 ""
14187 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14188 (set (match_dup 0) (neg:P (match_dup 0)))]
14189 "")
14191 (define_insn_and_split "*gtu<mode>_compare"
14192 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14193 (compare:CC
14194 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14195 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14196 (const_int 0)))
14197 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14198 (gtu:P (match_dup 1) (match_dup 2)))]
14199 ""
14200 "#"
14201 ""
14202 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14203 (parallel [(set (match_dup 3)
14204 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14205 (set (match_dup 0) (neg:P (match_dup 0)))])]
14206 "")
14208 (define_insn_and_split "*plus_gtu<mode>"
14209 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14210 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14211 (match_operand:P 2 "reg_or_short_operand" "rI"))
14212 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14213 ""
14214 "#"
14215 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14216 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14217 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14218 "")
14220 (define_insn_and_split "*plus_gtu<mode>_compare"
14221 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14222 (compare:CC
14223 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14224 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14225 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14226 (const_int 0)))
14227 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14228 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14229 ""
14230 "#"
14231 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14232 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14233 (parallel [(set (match_dup 4)
14234 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14235 (const_int 0)))
14236 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14237 "")
14239 (define_insn "*neg_gtu<mode>"
14240 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14241 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14242 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14243 ""
14244 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
14245 [(set_attr "type" "two")
14246 (set_attr "length" "8")])
14248 \f
14249 ;; Define both directions of branch and return. If we need a reload
14250 ;; register, we'd rather use CR0 since it is much easier to copy a
14251 ;; register CC value to there.
14253 (define_insn ""
14254 [(set (pc)
14255 (if_then_else (match_operator 1 "branch_comparison_operator"
14256 [(match_operand 2
14257 "cc_reg_operand" "y")
14258 (const_int 0)])
14259 (label_ref (match_operand 0 "" ""))
14260 (pc)))]
14261 ""
14262 "*
14263 {
14264 return output_cbranch (operands[1], \"%l0\", 0, insn);
14265 }"
14266 [(set_attr "type" "branch")])
14268 (define_insn ""
14269 [(set (pc)
14270 (if_then_else (match_operator 0 "branch_comparison_operator"
14271 [(match_operand 1
14272 "cc_reg_operand" "y")
14273 (const_int 0)])
14274 (any_return)
14275 (pc)))]
14276 "<return_pred>"
14277 "*
14278 {
14279 return output_cbranch (operands[0], NULL, 0, insn);
14280 }"
14281 [(set_attr "type" "jmpreg")
14282 (set_attr "length" "4")])
14284 (define_insn ""
14285 [(set (pc)
14286 (if_then_else (match_operator 1 "branch_comparison_operator"
14287 [(match_operand 2
14288 "cc_reg_operand" "y")
14289 (const_int 0)])
14290 (pc)
14291 (label_ref (match_operand 0 "" ""))))]
14292 ""
14293 "*
14294 {
14295 return output_cbranch (operands[1], \"%l0\", 1, insn);
14296 }"
14297 [(set_attr "type" "branch")])
14299 (define_insn ""
14300 [(set (pc)
14301 (if_then_else (match_operator 0 "branch_comparison_operator"
14302 [(match_operand 1
14303 "cc_reg_operand" "y")
14304 (const_int 0)])
14305 (pc)
14306 (any_return)))]
14307 "<return_pred>"
14308 "*
14309 {
14310 return output_cbranch (operands[0], NULL, 1, insn);
14311 }"
14312 [(set_attr "type" "jmpreg")
14313 (set_attr "length" "4")])
14315 ;; Logic on condition register values.
14317 ; This pattern matches things like
14318 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14319 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14320 ; (const_int 1)))
14321 ; which are generated by the branch logic.
14322 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14324 (define_insn "*cceq_ior_compare"
14325 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14326 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14327 [(match_operator:SI 2
14328 "branch_positive_comparison_operator"
14329 [(match_operand 3
14330 "cc_reg_operand" "y,y")
14331 (const_int 0)])
14332 (match_operator:SI 4
14333 "branch_positive_comparison_operator"
14334 [(match_operand 5
14335 "cc_reg_operand" "0,y")
14336 (const_int 0)])])
14337 (const_int 1)))]
14338 ""
14339 "cr%q1 %E0,%j2,%j4"
14340 [(set_attr "type" "cr_logical,delayed_cr")])
14342 ; Why is the constant -1 here, but 1 in the previous pattern?
14343 ; Because ~1 has all but the low bit set.
14344 (define_insn ""
14345 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14346 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14347 [(not:SI (match_operator:SI 2
14348 "branch_positive_comparison_operator"
14349 [(match_operand 3
14350 "cc_reg_operand" "y,y")
14351 (const_int 0)]))
14352 (match_operator:SI 4
14353 "branch_positive_comparison_operator"
14354 [(match_operand 5
14355 "cc_reg_operand" "0,y")
14356 (const_int 0)])])
14357 (const_int -1)))]
14358 ""
14359 "cr%q1 %E0,%j2,%j4"
14360 [(set_attr "type" "cr_logical,delayed_cr")])
14362 (define_insn "*cceq_rev_compare"
14363 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14364 (compare:CCEQ (match_operator:SI 1
14365 "branch_positive_comparison_operator"
14366 [(match_operand 2
14367 "cc_reg_operand" "0,y")
14368 (const_int 0)])
14369 (const_int 0)))]
14370 ""
14371 "crnot %E0,%j1"
14372 [(set_attr "type" "cr_logical,delayed_cr")])
14374 ;; If we are comparing the result of two comparisons, this can be done
14375 ;; using creqv or crxor.
14377 (define_insn_and_split ""
14378 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14379 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14380 [(match_operand 2 "cc_reg_operand" "y")
14381 (const_int 0)])
14382 (match_operator 3 "branch_comparison_operator"
14383 [(match_operand 4 "cc_reg_operand" "y")
14384 (const_int 0)])))]
14385 ""
14386 "#"
14387 ""
14388 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14389 (match_dup 5)))]
14390 "
14391 {
14392 int positive_1, positive_2;
14394 positive_1 = branch_positive_comparison_operator (operands[1],
14395 GET_MODE (operands[1]));
14396 positive_2 = branch_positive_comparison_operator (operands[3],
14397 GET_MODE (operands[3]));
14399 if (! positive_1)
14400 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14401 GET_CODE (operands[1])),
14402 SImode,
14403 operands[2], const0_rtx);
14404 else if (GET_MODE (operands[1]) != SImode)
14405 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14406 operands[2], const0_rtx);
14408 if (! positive_2)
14409 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14410 GET_CODE (operands[3])),
14411 SImode,
14412 operands[4], const0_rtx);
14413 else if (GET_MODE (operands[3]) != SImode)
14414 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14415 operands[4], const0_rtx);
14417 if (positive_1 == positive_2)
14418 {
14419 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14420 operands[5] = constm1_rtx;
14421 }
14422 else
14423 {
14424 operands[5] = const1_rtx;
14425 }
14426 }")
14428 ;; Unconditional branch and return.
14430 (define_insn "jump"
14431 [(set (pc)
14432 (label_ref (match_operand 0 "" "")))]
14433 ""
14434 "b %l0"
14435 [(set_attr "type" "branch")])
14437 (define_insn "<return_str>return"
14438 [(any_return)]
14439 "<return_pred>"
14440 "blr"
14441 [(set_attr "type" "jmpreg")])
14443 (define_expand "indirect_jump"
14444 [(set (pc) (match_operand 0 "register_operand" ""))])
14446 (define_insn "*indirect_jump<mode>"
14447 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14448 ""
14449 "@
14450 bctr
14451 blr"
14452 [(set_attr "type" "jmpreg")])
14454 ;; Table jump for switch statements:
14455 (define_expand "tablejump"
14456 [(use (match_operand 0 "" ""))
14457 (use (label_ref (match_operand 1 "" "")))]
14458 ""
14459 "
14460 {
14461 if (TARGET_32BIT)
14462 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14463 else
14464 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14465 DONE;
14466 }")
14468 (define_expand "tablejumpsi"
14469 [(set (match_dup 3)
14470 (plus:SI (match_operand:SI 0 "" "")
14471 (match_dup 2)))
14472 (parallel [(set (pc) (match_dup 3))
14473 (use (label_ref (match_operand 1 "" "")))])]
14474 "TARGET_32BIT"
14475 "
14476 { operands[0] = force_reg (SImode, operands[0]);
14477 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14478 operands[3] = gen_reg_rtx (SImode);
14479 }")
14481 (define_expand "tablejumpdi"
14482 [(set (match_dup 4)
14483 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14484 (set (match_dup 3)
14485 (plus:DI (match_dup 4)
14486 (match_dup 2)))
14487 (parallel [(set (pc) (match_dup 3))
14488 (use (label_ref (match_operand 1 "" "")))])]
14489 "TARGET_64BIT"
14490 "
14491 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14492 operands[3] = gen_reg_rtx (DImode);
14493 operands[4] = gen_reg_rtx (DImode);
14494 }")
14496 (define_insn "*tablejump<mode>_internal1"
14497 [(set (pc)
14498 (match_operand:P 0 "register_operand" "c,*l"))
14499 (use (label_ref (match_operand 1 "" "")))]
14500 ""
14501 "@
14502 bctr
14503 blr"
14504 [(set_attr "type" "jmpreg")])
14506 (define_insn "nop"
14507 [(const_int 0)]
14508 ""
14509 "nop")
14511 (define_insn "group_ending_nop"
14512 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14513 ""
14514 "*
14515 {
14516 if (rs6000_cpu_attr == CPU_POWER6)
14517 return \"ori 1,1,0\";
14518 return \"ori 2,2,0\";
14519 }")
14520 \f
14521 ;; Define the subtract-one-and-jump insns, starting with the template
14522 ;; so loop.c knows what to generate.
14524 (define_expand "doloop_end"
14525 [(use (match_operand 0 "" "")) ; loop pseudo
14526 (use (match_operand 1 "" ""))] ; label
14527 ""
14528 "
14529 {
14530 if (TARGET_64BIT)
14531 {
14532 if (GET_MODE (operands[0]) != DImode)
14533 FAIL;
14534 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
14535 }
14536 else
14537 {
14538 if (GET_MODE (operands[0]) != SImode)
14539 FAIL;
14540 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
14541 }
14542 DONE;
14543 }")
14545 (define_expand "ctr<mode>"
14546 [(parallel [(set (pc)
14547 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14548 (const_int 1))
14549 (label_ref (match_operand 1 "" ""))
14550 (pc)))
14551 (set (match_dup 0)
14552 (plus:P (match_dup 0)
14553 (const_int -1)))
14554 (clobber (match_scratch:CC 2 ""))
14555 (clobber (match_scratch:P 3 ""))])]
14556 ""
14557 "")
14559 ;; We need to be able to do this for any operand, including MEM, or we
14560 ;; will cause reload to blow up since we don't allow output reloads on
14561 ;; JUMP_INSNs.
14562 ;; For the length attribute to be calculated correctly, the
14563 ;; label MUST be operand 0.
14565 (define_insn "*ctr<mode>_internal1"
14566 [(set (pc)
14567 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14568 (const_int 1))
14569 (label_ref (match_operand 0 "" ""))
14570 (pc)))
14571 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14572 (plus:P (match_dup 1)
14573 (const_int -1)))
14574 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14575 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14576 ""
14577 "*
14578 {
14579 if (which_alternative != 0)
14580 return \"#\";
14581 else if (get_attr_length (insn) == 4)
14582 return \"bdnz %l0\";
14583 else
14584 return \"bdz $+8\;b %l0\";
14585 }"
14586 [(set_attr "type" "branch")
14587 (set_attr "length" "*,12,16,16")])
14589 (define_insn "*ctr<mode>_internal2"
14590 [(set (pc)
14591 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14592 (const_int 1))
14593 (pc)
14594 (label_ref (match_operand 0 "" ""))))
14595 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14596 (plus:P (match_dup 1)
14597 (const_int -1)))
14598 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14599 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14600 ""
14601 "*
14602 {
14603 if (which_alternative != 0)
14604 return \"#\";
14605 else if (get_attr_length (insn) == 4)
14606 return \"bdz %l0\";
14607 else
14608 return \"bdnz $+8\;b %l0\";
14609 }"
14610 [(set_attr "type" "branch")
14611 (set_attr "length" "*,12,16,16")])
14613 ;; Similar but use EQ
14615 (define_insn "*ctr<mode>_internal5"
14616 [(set (pc)
14617 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14618 (const_int 1))
14619 (label_ref (match_operand 0 "" ""))
14620 (pc)))
14621 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14622 (plus:P (match_dup 1)
14623 (const_int -1)))
14624 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14625 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14626 ""
14627 "*
14628 {
14629 if (which_alternative != 0)
14630 return \"#\";
14631 else if (get_attr_length (insn) == 4)
14632 return \"bdz %l0\";
14633 else
14634 return \"bdnz $+8\;b %l0\";
14635 }"
14636 [(set_attr "type" "branch")
14637 (set_attr "length" "*,12,16,16")])
14639 (define_insn "*ctr<mode>_internal6"
14640 [(set (pc)
14641 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14642 (const_int 1))
14643 (pc)
14644 (label_ref (match_operand 0 "" ""))))
14645 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14646 (plus:P (match_dup 1)
14647 (const_int -1)))
14648 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14649 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14650 ""
14651 "*
14652 {
14653 if (which_alternative != 0)
14654 return \"#\";
14655 else if (get_attr_length (insn) == 4)
14656 return \"bdnz %l0\";
14657 else
14658 return \"bdz $+8\;b %l0\";
14659 }"
14660 [(set_attr "type" "branch")
14661 (set_attr "length" "*,12,16,16")])
14663 ;; Now the splitters if we could not allocate the CTR register
14665 (define_split
14666 [(set (pc)
14667 (if_then_else (match_operator 2 "comparison_operator"
14668 [(match_operand:P 1 "gpc_reg_operand" "")
14669 (const_int 1)])
14670 (match_operand 5 "" "")
14671 (match_operand 6 "" "")))
14672 (set (match_operand:P 0 "gpc_reg_operand" "")
14673 (plus:P (match_dup 1) (const_int -1)))
14674 (clobber (match_scratch:CC 3 ""))
14675 (clobber (match_scratch:P 4 ""))]
14676 "reload_completed"
14677 [(parallel [(set (match_dup 3)
14678 (compare:CC (plus:P (match_dup 1)
14679 (const_int -1))
14680 (const_int 0)))
14681 (set (match_dup 0)
14682 (plus:P (match_dup 1)
14683 (const_int -1)))])
14684 (set (pc) (if_then_else (match_dup 7)
14685 (match_dup 5)
14686 (match_dup 6)))]
14687 "
14688 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14689 operands[3], const0_rtx); }")
14691 (define_split
14692 [(set (pc)
14693 (if_then_else (match_operator 2 "comparison_operator"
14694 [(match_operand:P 1 "gpc_reg_operand" "")
14695 (const_int 1)])
14696 (match_operand 5 "" "")
14697 (match_operand 6 "" "")))
14698 (set (match_operand:P 0 "nonimmediate_operand" "")
14699 (plus:P (match_dup 1) (const_int -1)))
14700 (clobber (match_scratch:CC 3 ""))
14701 (clobber (match_scratch:P 4 ""))]
14702 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14703 [(parallel [(set (match_dup 3)
14704 (compare:CC (plus:P (match_dup 1)
14705 (const_int -1))
14706 (const_int 0)))
14707 (set (match_dup 4)
14708 (plus:P (match_dup 1)
14709 (const_int -1)))])
14710 (set (match_dup 0)
14711 (match_dup 4))
14712 (set (pc) (if_then_else (match_dup 7)
14713 (match_dup 5)
14714 (match_dup 6)))]
14715 "
14716 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14717 operands[3], const0_rtx); }")
14718 \f
14719 (define_insn "trap"
14720 [(trap_if (const_int 1) (const_int 0))]
14721 ""
14722 "trap"
14723 [(set_attr "type" "trap")])
14725 (define_expand "ctrap<mode>4"
14726 [(trap_if (match_operator 0 "ordered_comparison_operator"
14727 [(match_operand:GPR 1 "register_operand")
14728 (match_operand:GPR 2 "reg_or_short_operand")])
14729 (match_operand 3 "zero_constant" ""))]
14730 ""
14731 "")
14733 (define_insn ""
14734 [(trap_if (match_operator 0 "ordered_comparison_operator"
14735 [(match_operand:GPR 1 "register_operand" "r")
14736 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14737 (const_int 0))]
14738 ""
14739 "t<wd>%V0%I2 %1,%2"
14740 [(set_attr "type" "trap")])
14741 \f
14742 ;; Insns related to generating the function prologue and epilogue.
14744 (define_expand "prologue"
14745 [(use (const_int 0))]
14746 ""
14747 {
14748 rs6000_emit_prologue ();
14749 if (!TARGET_SCHED_PROLOG)
14750 emit_insn (gen_blockage ());
14751 DONE;
14752 })
14754 (define_insn "*movesi_from_cr_one"
14755 [(match_parallel 0 "mfcr_operation"
14756 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14757 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14758 (match_operand 3 "immediate_operand" "n")]
14759 UNSPEC_MOVESI_FROM_CR))])]
14760 "TARGET_MFCRF"
14761 "*
14762 {
14763 int mask = 0;
14764 int i;
14765 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14766 {
14767 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14768 operands[4] = GEN_INT (mask);
14769 output_asm_insn (\"mfcr %1,%4\", operands);
14770 }
14771 return \"\";
14772 }"
14773 [(set_attr "type" "mfcrf")])
14775 (define_insn "movesi_from_cr"
14776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14777 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14778 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14779 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14780 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14781 UNSPEC_MOVESI_FROM_CR))]
14782 ""
14783 "mfcr %0"
14784 [(set_attr "type" "mfcr")])
14786 (define_insn "*crsave"
14787 [(match_parallel 0 "crsave_operation"
14788 [(set (match_operand:SI 1 "memory_operand" "=m")
14789 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14790 ""
14791 "stw %2,%1"
14792 [(set_attr "type" "store")])
14794 (define_insn "*stmw"
14795 [(match_parallel 0 "stmw_operation"
14796 [(set (match_operand:SI 1 "memory_operand" "=m")
14797 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14798 "TARGET_MULTIPLE"
14799 "stmw %2,%1"
14800 [(set_attr "type" "store")
14801 (set_attr "update" "yes")
14802 (set_attr "indexed" "yes")])
14804 ; The following comment applies to:
14805 ; save_gpregs_*
14806 ; save_fpregs_*
14807 ; restore_gpregs*
14808 ; return_and_restore_gpregs*
14809 ; return_and_restore_fpregs*
14810 ; return_and_restore_fpregs_aix*
14811 ;
14812 ; The out-of-line save / restore functions expects one input argument.
14813 ; Since those are not standard call_insn's, we must avoid using
14814 ; MATCH_OPERAND for that argument. That way the register rename
14815 ; optimization will not try to rename this register.
14816 ; Each pattern is repeated for each possible register number used in
14817 ; various ABIs (r11, r1, and for some functions r12)
14819 (define_insn "*save_gpregs_<mode>_r11"
14820 [(match_parallel 0 "any_parallel_operand"
14821 [(clobber (reg:P 65))
14822 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14823 (use (reg:P 11))
14824 (set (match_operand:P 2 "memory_operand" "=m")
14825 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14826 ""
14827 "bl %1"
14828 [(set_attr "type" "branch")
14829 (set_attr "length" "4")])
14831 (define_insn "*save_gpregs_<mode>_r12"
14832 [(match_parallel 0 "any_parallel_operand"
14833 [(clobber (reg:P 65))
14834 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14835 (use (reg:P 12))
14836 (set (match_operand:P 2 "memory_operand" "=m")
14837 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14838 ""
14839 "bl %1"
14840 [(set_attr "type" "branch")
14841 (set_attr "length" "4")])
14843 (define_insn "*save_gpregs_<mode>_r1"
14844 [(match_parallel 0 "any_parallel_operand"
14845 [(clobber (reg:P 65))
14846 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14847 (use (reg:P 1))
14848 (set (match_operand:P 2 "memory_operand" "=m")
14849 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14850 ""
14851 "bl %1"
14852 [(set_attr "type" "branch")
14853 (set_attr "length" "4")])
14855 (define_insn "*save_fpregs_<mode>_r11"
14856 [(match_parallel 0 "any_parallel_operand"
14857 [(clobber (reg:P 65))
14858 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14859 (use (reg:P 11))
14860 (set (match_operand:DF 2 "memory_operand" "=m")
14861 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14862 ""
14863 "bl %1"
14864 [(set_attr "type" "branch")
14865 (set_attr "length" "4")])
14867 (define_insn "*save_fpregs_<mode>_r12"
14868 [(match_parallel 0 "any_parallel_operand"
14869 [(clobber (reg:P 65))
14870 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14871 (use (reg:P 12))
14872 (set (match_operand:DF 2 "memory_operand" "=m")
14873 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14874 ""
14875 "bl %1"
14876 [(set_attr "type" "branch")
14877 (set_attr "length" "4")])
14879 (define_insn "*save_fpregs_<mode>_r1"
14880 [(match_parallel 0 "any_parallel_operand"
14881 [(clobber (reg:P 65))
14882 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14883 (use (reg:P 1))
14884 (set (match_operand:DF 2 "memory_operand" "=m")
14885 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14886 ""
14887 "bl %1"
14888 [(set_attr "type" "branch")
14889 (set_attr "length" "4")])
14891 ; This is to explain that changes to the stack pointer should
14892 ; not be moved over loads from or stores to stack memory.
14893 (define_insn "stack_tie"
14894 [(match_parallel 0 "tie_operand"
14895 [(set (mem:BLK (reg 1)) (const_int 0))])]
14896 ""
14897 ""
14898 [(set_attr "length" "0")])
14900 (define_expand "epilogue"
14901 [(use (const_int 0))]
14902 ""
14903 {
14904 if (!TARGET_SCHED_PROLOG)
14905 emit_insn (gen_blockage ());
14906 rs6000_emit_epilogue (FALSE);
14907 DONE;
14908 })
14910 ; On some processors, doing the mtcrf one CC register at a time is
14911 ; faster (like on the 604e). On others, doing them all at once is
14912 ; faster; for instance, on the 601 and 750.
14914 (define_expand "movsi_to_cr_one"
14915 [(set (match_operand:CC 0 "cc_reg_operand" "")
14916 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14917 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14918 ""
14919 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14921 (define_insn "*movsi_to_cr"
14922 [(match_parallel 0 "mtcrf_operation"
14923 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14924 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14925 (match_operand 3 "immediate_operand" "n")]
14926 UNSPEC_MOVESI_TO_CR))])]
14927 ""
14928 "*
14929 {
14930 int mask = 0;
14931 int i;
14932 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14933 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14934 operands[4] = GEN_INT (mask);
14935 return \"mtcrf %4,%2\";
14936 }"
14937 [(set_attr "type" "mtcr")])
14939 (define_insn "*mtcrfsi"
14940 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14941 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14942 (match_operand 2 "immediate_operand" "n")]
14943 UNSPEC_MOVESI_TO_CR))]
14944 "GET_CODE (operands[0]) == REG
14945 && CR_REGNO_P (REGNO (operands[0]))
14946 && GET_CODE (operands[2]) == CONST_INT
14947 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14948 "mtcrf %R0,%1"
14949 [(set_attr "type" "mtcr")])
14951 ; The load-multiple instructions have similar properties.
14952 ; Note that "load_multiple" is a name known to the machine-independent
14953 ; code that actually corresponds to the PowerPC load-string.
14955 (define_insn "*lmw"
14956 [(match_parallel 0 "lmw_operation"
14957 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14958 (match_operand:SI 2 "memory_operand" "m"))])]
14959 "TARGET_MULTIPLE"
14960 "lmw %1,%2"
14961 [(set_attr "type" "load")
14962 (set_attr "update" "yes")
14963 (set_attr "indexed" "yes")
14964 (set_attr "cell_micro" "always")])
14966 (define_insn "*return_internal_<mode>"
14967 [(simple_return)
14968 (use (match_operand:P 0 "register_operand" "lc"))]
14969 ""
14970 "b%T0"
14971 [(set_attr "type" "jmpreg")])
14973 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14974 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14976 ; The following comment applies to:
14977 ; save_gpregs_*
14978 ; save_fpregs_*
14979 ; restore_gpregs*
14980 ; return_and_restore_gpregs*
14981 ; return_and_restore_fpregs*
14982 ; return_and_restore_fpregs_aix*
14983 ;
14984 ; The out-of-line save / restore functions expects one input argument.
14985 ; Since those are not standard call_insn's, we must avoid using
14986 ; MATCH_OPERAND for that argument. That way the register rename
14987 ; optimization will not try to rename this register.
14988 ; Each pattern is repeated for each possible register number used in
14989 ; various ABIs (r11, r1, and for some functions r12)
14991 (define_insn "*restore_gpregs_<mode>_r11"
14992 [(match_parallel 0 "any_parallel_operand"
14993 [(clobber (match_operand:P 1 "register_operand" "=l"))
14994 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14995 (use (reg:P 11))
14996 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14997 (match_operand:P 4 "memory_operand" "m"))])]
14998 ""
14999 "bl %2"
15000 [(set_attr "type" "branch")
15001 (set_attr "length" "4")])
15003 (define_insn "*restore_gpregs_<mode>_r12"
15004 [(match_parallel 0 "any_parallel_operand"
15005 [(clobber (match_operand:P 1 "register_operand" "=l"))
15006 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15007 (use (reg:P 12))
15008 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15009 (match_operand:P 4 "memory_operand" "m"))])]
15010 ""
15011 "bl %2"
15012 [(set_attr "type" "branch")
15013 (set_attr "length" "4")])
15015 (define_insn "*restore_gpregs_<mode>_r1"
15016 [(match_parallel 0 "any_parallel_operand"
15017 [(clobber (match_operand:P 1 "register_operand" "=l"))
15018 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15019 (use (reg:P 1))
15020 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15021 (match_operand:P 4 "memory_operand" "m"))])]
15022 ""
15023 "bl %2"
15024 [(set_attr "type" "branch")
15025 (set_attr "length" "4")])
15027 (define_insn "*return_and_restore_gpregs_<mode>_r11"
15028 [(match_parallel 0 "any_parallel_operand"
15029 [(return)
15030 (clobber (match_operand:P 1 "register_operand" "=l"))
15031 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15032 (use (reg:P 11))
15033 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15034 (match_operand:P 4 "memory_operand" "m"))])]
15035 ""
15036 "b %2"
15037 [(set_attr "type" "branch")
15038 (set_attr "length" "4")])
15040 (define_insn "*return_and_restore_gpregs_<mode>_r12"
15041 [(match_parallel 0 "any_parallel_operand"
15042 [(return)
15043 (clobber (match_operand:P 1 "register_operand" "=l"))
15044 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15045 (use (reg:P 12))
15046 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15047 (match_operand:P 4 "memory_operand" "m"))])]
15048 ""
15049 "b %2"
15050 [(set_attr "type" "branch")
15051 (set_attr "length" "4")])
15053 (define_insn "*return_and_restore_gpregs_<mode>_r1"
15054 [(match_parallel 0 "any_parallel_operand"
15055 [(return)
15056 (clobber (match_operand:P 1 "register_operand" "=l"))
15057 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15058 (use (reg:P 1))
15059 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15060 (match_operand:P 4 "memory_operand" "m"))])]
15061 ""
15062 "b %2"
15063 [(set_attr "type" "branch")
15064 (set_attr "length" "4")])
15066 (define_insn "*return_and_restore_fpregs_<mode>_r11"
15067 [(match_parallel 0 "any_parallel_operand"
15068 [(return)
15069 (clobber (match_operand:P 1 "register_operand" "=l"))
15070 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15071 (use (reg:P 11))
15072 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15073 (match_operand:DF 4 "memory_operand" "m"))])]
15074 ""
15075 "b %2"
15076 [(set_attr "type" "branch")
15077 (set_attr "length" "4")])
15079 (define_insn "*return_and_restore_fpregs_<mode>_r12"
15080 [(match_parallel 0 "any_parallel_operand"
15081 [(return)
15082 (clobber (match_operand:P 1 "register_operand" "=l"))
15083 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15084 (use (reg:P 12))
15085 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15086 (match_operand:DF 4 "memory_operand" "m"))])]
15087 ""
15088 "b %2"
15089 [(set_attr "type" "branch")
15090 (set_attr "length" "4")])
15092 (define_insn "*return_and_restore_fpregs_<mode>_r1"
15093 [(match_parallel 0 "any_parallel_operand"
15094 [(return)
15095 (clobber (match_operand:P 1 "register_operand" "=l"))
15096 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15097 (use (reg:P 1))
15098 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15099 (match_operand:DF 4 "memory_operand" "m"))])]
15100 ""
15101 "b %2"
15102 [(set_attr "type" "branch")
15103 (set_attr "length" "4")])
15105 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
15106 [(match_parallel 0 "any_parallel_operand"
15107 [(return)
15108 (use (match_operand:P 1 "register_operand" "l"))
15109 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15110 (use (reg:P 11))
15111 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15112 (match_operand:DF 4 "memory_operand" "m"))])]
15113 ""
15114 "b %2"
15115 [(set_attr "type" "branch")
15116 (set_attr "length" "4")])
15118 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
15119 [(match_parallel 0 "any_parallel_operand"
15120 [(return)
15121 (use (match_operand:P 1 "register_operand" "l"))
15122 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15123 (use (reg:P 1))
15124 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15125 (match_operand:DF 4 "memory_operand" "m"))])]
15126 ""
15127 "b %2"
15128 [(set_attr "type" "branch")
15129 (set_attr "length" "4")])
15131 ; This is used in compiling the unwind routines.
15132 (define_expand "eh_return"
15133 [(use (match_operand 0 "general_operand" ""))]
15134 ""
15135 "
15136 {
15137 if (TARGET_32BIT)
15138 emit_insn (gen_eh_set_lr_si (operands[0]));
15139 else
15140 emit_insn (gen_eh_set_lr_di (operands[0]));
15141 DONE;
15142 }")
15144 ; We can't expand this before we know where the link register is stored.
15145 (define_insn "eh_set_lr_<mode>"
15146 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15147 UNSPECV_EH_RR)
15148 (clobber (match_scratch:P 1 "=&b"))]
15149 ""
15150 "#")
15152 (define_split
15153 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15154 (clobber (match_scratch 1 ""))]
15155 "reload_completed"
15156 [(const_int 0)]
15157 "
15158 {
15159 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15160 DONE;
15161 }")
15163 (define_insn "prefetch"
15164 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15165 (match_operand:SI 1 "const_int_operand" "n")
15166 (match_operand:SI 2 "const_int_operand" "n"))]
15167 ""
15168 "*
15169 {
15170 if (GET_CODE (operands[0]) == REG)
15171 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15172 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15173 }"
15174 [(set_attr "type" "load")])
15175 \f
15176 (define_insn "bpermd_<mode>"
15177 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15178 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15179 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15180 "TARGET_POPCNTD"
15181 "bpermd %0,%1,%2"
15182 [(set_attr "type" "popcnt")])
15184 \f
15185 ;; Builtin fma support. Handle
15186 ;; Note that the conditions for expansion are in the FMA_F iterator.
15188 (define_expand "fma<mode>4"
15189 [(set (match_operand:FMA_F 0 "register_operand" "")
15190 (fma:FMA_F
15191 (match_operand:FMA_F 1 "register_operand" "")
15192 (match_operand:FMA_F 2 "register_operand" "")
15193 (match_operand:FMA_F 3 "register_operand" "")))]
15194 ""
15195 "")
15197 (define_insn "*fma<mode>4_fpr"
15198 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15199 (fma:SFDF
15200 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
15201 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15202 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
15203 "TARGET_<MODE>_FPR"
15204 "@
15205 fmadd<Ftrad> %0,%1,%2,%3
15206 xsmadda<Fvsx> %x0,%x1,%x2
15207 xsmaddm<Fvsx> %x0,%x1,%x3"
15208 [(set_attr "type" "fp")
15209 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15211 ; Altivec only has fma and nfms.
15212 (define_expand "fms<mode>4"
15213 [(set (match_operand:FMA_F 0 "register_operand" "")
15214 (fma:FMA_F
15215 (match_operand:FMA_F 1 "register_operand" "")
15216 (match_operand:FMA_F 2 "register_operand" "")
15217 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
15218 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15219 "")
15221 (define_insn "*fms<mode>4_fpr"
15222 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15223 (fma:SFDF
15224 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15225 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15226 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
15227 "TARGET_<MODE>_FPR"
15228 "@
15229 fmsub<Ftrad> %0,%1,%2,%3
15230 xsmsuba<Fvsx> %x0,%x1,%x2
15231 xsmsubm<Fvsx> %x0,%x1,%x3"
15232 [(set_attr "type" "fp")
15233 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15235 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
15236 (define_expand "fnma<mode>4"
15237 [(set (match_operand:FMA_F 0 "register_operand" "")
15238 (neg:FMA_F
15239 (fma:FMA_F
15240 (match_operand:FMA_F 1 "register_operand" "")
15241 (match_operand:FMA_F 2 "register_operand" "")
15242 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15243 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
15244 "")
15246 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
15247 (define_expand "fnms<mode>4"
15248 [(set (match_operand:FMA_F 0 "register_operand" "")
15249 (neg:FMA_F
15250 (fma:FMA_F
15251 (match_operand:FMA_F 1 "register_operand" "")
15252 (match_operand:FMA_F 2 "register_operand" "")
15253 (match_operand:FMA_F 3 "register_operand" ""))))]
15254 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15255 "")
15257 ; Not an official optab name, but used from builtins.
15258 (define_expand "nfma<mode>4"
15259 [(set (match_operand:FMA_F 0 "register_operand" "")
15260 (neg:FMA_F
15261 (fma:FMA_F
15262 (match_operand:FMA_F 1 "register_operand" "")
15263 (match_operand:FMA_F 2 "register_operand" "")
15264 (match_operand:FMA_F 3 "register_operand" ""))))]
15265 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15266 "")
15268 (define_insn "*nfma<mode>4_fpr"
15269 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15270 (neg:SFDF
15271 (fma:SFDF
15272 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15273 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15274 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
15275 "TARGET_<MODE>_FPR"
15276 "@
15277 fnmadd<Ftrad> %0,%1,%2,%3
15278 xsnmadda<Fvsx> %x0,%x1,%x2
15279 xsnmaddm<Fvsx> %x0,%x1,%x3"
15280 [(set_attr "type" "fp")
15281 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15283 ; Not an official optab name, but used from builtins.
15284 (define_expand "nfms<mode>4"
15285 [(set (match_operand:FMA_F 0 "register_operand" "")
15286 (neg:FMA_F
15287 (fma:FMA_F
15288 (match_operand:FMA_F 1 "register_operand" "")
15289 (match_operand:FMA_F 2 "register_operand" "")
15290 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15291 ""
15292 "")
15294 (define_insn "*nfmssf4_fpr"
15295 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15296 (neg:SFDF
15297 (fma:SFDF
15298 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15299 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15300 (neg:SFDF
15301 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
15302 "TARGET_<MODE>_FPR"
15303 "@
15304 fnmsub<Ftrad> %0,%1,%2,%3
15305 xsnmsuba<Fvsx> %x0,%x1,%x2
15306 xsnmsubm<Fvsx> %x0,%x1,%x3"
15307 [(set_attr "type" "fp")
15308 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15310 \f
15311 (define_expand "rs6000_get_timebase"
15312 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
15313 ""
15314 {
15315 if (TARGET_POWERPC64)
15316 emit_insn (gen_rs6000_mftb_di (operands[0]));
15317 else
15318 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
15319 DONE;
15320 })
15322 (define_insn "rs6000_get_timebase_ppc32"
15323 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
15324 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
15325 (clobber (match_scratch:SI 1 "=r"))
15326 (clobber (match_scratch:CC 2 "=y"))]
15327 "!TARGET_POWERPC64"
15328 {
15329 if (WORDS_BIG_ENDIAN)
15330 if (TARGET_MFCRF)
15331 {
15332 return "mfspr %0,269\;"
15333 "mfspr %L0,268\;"
15334 "mfspr %1,269\;"
15335 "cmpw %2,%0,%1\;"
15336 "bne- %2,$-16";
15337 }
15338 else
15339 {
15340 return "mftbu %0\;"
15341 "mftb %L0\;"
15342 "mftbu %1\;"
15343 "cmpw %2,%0,%1\;"
15344 "bne- %2,$-16";
15345 }
15346 else
15347 if (TARGET_MFCRF)
15348 {
15349 return "mfspr %L0,269\;"
15350 "mfspr %0,268\;"
15351 "mfspr %1,269\;"
15352 "cmpw %2,%L0,%1\;"
15353 "bne- %2,$-16";
15354 }
15355 else
15356 {
15357 return "mftbu %L0\;"
15358 "mftb %0\;"
15359 "mftbu %1\;"
15360 "cmpw %2,%L0,%1\;"
15361 "bne- %2,$-16";
15362 }
15363 }
15364 [(set_attr "length" "20")])
15366 (define_insn "rs6000_mftb_<mode>"
15367 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15368 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
15369 ""
15370 {
15371 if (TARGET_MFCRF)
15372 return "mfspr %0,268";
15373 else
15374 return "mftb %0";
15375 })
15377 \f
15378 (define_insn "rs6000_mffs"
15379 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
15380 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
15381 "TARGET_HARD_FLOAT && TARGET_FPRS"
15382 "mffs %0")
15384 (define_insn "rs6000_mtfsf"
15385 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
15386 (match_operand:DF 1 "gpc_reg_operand" "d")]
15387 UNSPECV_MTFSF)]
15388 "TARGET_HARD_FLOAT && TARGET_FPRS"
15389 "mtfsf %0,%1")
15391 \f
15392 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
15393 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
15394 ;; register that is being loaded. The fused ops must be physically adjacent.
15396 ;; We use define_peephole for the actual addis/load, and the register used to
15397 ;; hold the addis value must be the same as the register being loaded. We use
15398 ;; define_peephole2 to change the register used for addis to be the register
15399 ;; being loaded, since we can look at whether it is dead after the load insn.
15401 (define_peephole
15402 [(set (match_operand:P 0 "base_reg_operand" "")
15403 (match_operand:P 1 "fusion_gpr_addis" ""))
15404 (set (match_operand:INT1 2 "base_reg_operand" "")
15405 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15406 "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
15407 {
15408 return emit_fusion_gpr_load (operands);
15409 }
15410 [(set_attr "type" "load")
15411 (set_attr "length" "8")])
15413 (define_peephole2
15414 [(set (match_operand:P 0 "base_reg_operand" "")
15415 (match_operand:P 1 "fusion_gpr_addis" ""))
15416 (set (match_operand:INT1 2 "base_reg_operand" "")
15417 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15418 "TARGET_P8_FUSION
15419 && (REGNO (operands[0]) != REGNO (operands[2])
15420 || GET_CODE (operands[3]) == SIGN_EXTEND)
15421 && fusion_gpr_load_p (operands, true)"
15422 [(const_int 0)]
15423 {
15424 expand_fusion_gpr_load (operands);
15425 DONE;
15426 })
15428 \f
15429 ;; Miscellaneous ISA 2.06 (power7) instructions
15430 (define_insn "addg6s"
15431 [(set (match_operand:SI 0 "register_operand" "=r")
15432 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
15433 (match_operand:SI 2 "register_operand" "r")]
15434 UNSPEC_ADDG6S))]
15435 "TARGET_POPCNTD"
15436 "addg6s %0,%1,%2"
15437 [(set_attr "type" "integer")
15438 (set_attr "length" "4")])
15440 (define_insn "cdtbcd"
15441 [(set (match_operand:SI 0 "register_operand" "=r")
15442 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
15443 UNSPEC_CDTBCD))]
15444 "TARGET_POPCNTD"
15445 "cdtbcd %0,%1"
15446 [(set_attr "type" "integer")
15447 (set_attr "length" "4")])
15449 (define_insn "cbcdtd"
15450 [(set (match_operand:SI 0 "register_operand" "=r")
15451 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
15452 UNSPEC_CBCDTD))]
15453 "TARGET_POPCNTD"
15454 "cbcdtd %0,%1"
15455 [(set_attr "type" "integer")
15456 (set_attr "length" "4")])
15458 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
15459 UNSPEC_DIVEO
15460 UNSPEC_DIVEU
15461 UNSPEC_DIVEUO])
15463 (define_int_attr div_extend [(UNSPEC_DIVE "e")
15464 (UNSPEC_DIVEO "eo")
15465 (UNSPEC_DIVEU "eu")
15466 (UNSPEC_DIVEUO "euo")])
15468 (define_insn "div<div_extend>_<mode>"
15469 [(set (match_operand:GPR 0 "register_operand" "=r")
15470 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
15471 (match_operand:GPR 2 "register_operand" "r")]
15472 UNSPEC_DIV_EXTEND))]
15473 "TARGET_POPCNTD"
15474 "div<wd><div_extend> %0,%1,%2"
15475 [(set_attr "type" "<idiv_ldiv>")])
15477 \f
15478 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
15480 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
15481 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
15483 (define_expand "unpack<mode>"
15484 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
15485 (unspec:<FP128_64>
15486 [(match_operand:FMOVE128 1 "register_operand" "")
15487 (match_operand:QI 2 "const_0_to_1_operand" "")]
15488 UNSPEC_UNPACK_128BIT))]
15489 ""
15490 "")
15492 ;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0
15493 ;; and __builtin_longdouble_dw1 to optimize glibc. Add support for these
15494 ;; builtins here.
15496 (define_expand "unpacktf_0"
15497 [(set (match_operand:DF 0 "nonimmediate_operand" "")
15498 (unspec:DF [(match_operand:TF 1 "register_operand" "")
15499 (const_int 0)]
15500 UNSPEC_UNPACK_128BIT))]
15501 ""
15502 "")
15504 (define_expand "unpacktf_1"
15505 [(set (match_operand:DF 0 "nonimmediate_operand" "")
15506 (unspec:DF [(match_operand:TF 1 "register_operand" "")
15507 (const_int 1)]
15508 UNSPEC_UNPACK_128BIT))]
15509 ""
15510 "")
15512 (define_insn_and_split "unpack<mode>_dm"
15513 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
15514 (unspec:<FP128_64>
15515 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
15516 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
15517 UNSPEC_UNPACK_128BIT))]
15518 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
15519 "#"
15520 "&& reload_completed"
15521 [(set (match_dup 0) (match_dup 3))]
15522 {
15523 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
15525 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
15526 {
15527 emit_note (NOTE_INSN_DELETED);
15528 DONE;
15529 }
15531 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
15532 }
15533 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
15534 (set_attr "length" "4")])
15536 (define_insn_and_split "unpack<mode>_nodm"
15537 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
15538 (unspec:<FP128_64>
15539 [(match_operand:FMOVE128 1 "register_operand" "d,d")
15540 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
15541 UNSPEC_UNPACK_128BIT))]
15542 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
15543 "#"
15544 "&& reload_completed"
15545 [(set (match_dup 0) (match_dup 3))]
15546 {
15547 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
15549 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
15550 {
15551 emit_note (NOTE_INSN_DELETED);
15552 DONE;
15553 }
15555 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
15556 }
15557 [(set_attr "type" "fp,fpstore")
15558 (set_attr "length" "4")])
15560 (define_insn_and_split "pack<mode>"
15561 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
15562 (unspec:FMOVE128
15563 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
15564 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
15565 UNSPEC_PACK_128BIT))]
15566 ""
15567 "@
15568 fmr %L0,%2
15569 #"
15570 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
15571 [(set (match_dup 3) (match_dup 1))
15572 (set (match_dup 4) (match_dup 2))]
15573 {
15574 unsigned dest_hi = REGNO (operands[0]);
15575 unsigned dest_lo = dest_hi + 1;
15577 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
15578 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
15580 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
15581 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
15582 }
15583 [(set_attr "type" "fp,fp")
15584 (set_attr "length" "4,8")])
15586 (define_insn "unpackv1ti"
15587 [(set (match_operand:DI 0 "register_operand" "=d,d")
15588 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
15589 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
15590 UNSPEC_UNPACK_128BIT))]
15591 "TARGET_VSX"
15592 {
15593 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
15594 return ASM_COMMENT_START " xxpermdi to same register";
15596 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
15597 return "xxpermdi %x0,%x1,%x1,%3";
15598 }
15599 [(set_attr "type" "vecperm")
15600 (set_attr "length" "4")])
15602 (define_insn "packv1ti"
15603 [(set (match_operand:V1TI 0 "register_operand" "=wa")
15604 (unspec:V1TI
15605 [(match_operand:DI 1 "register_operand" "d")
15606 (match_operand:DI 2 "register_operand" "d")]
15607 UNSPEC_PACK_128BIT))]
15608 "TARGET_VSX"
15609 "xxpermdi %x0,%x1,%x2,0"
15610 [(set_attr "type" "vecperm")
15611 (set_attr "length" "4")])
15613 \f
15615 (include "sync.md")
15616 (include "vector.md")
15617 (include "vsx.md")
15618 (include "altivec.md")
15619 (include "spe.md")
15620 (include "dfp.md")
15621 (include "paired.md")
15622 (include "crypto.md")
15623 (include "htm.md")