1 ;; Scheduling description for IBM POWER8 processor.
2 ;; Copyright (C) 2013-2014 Free Software Foundation, Inc.
4 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 (define_automaton "power8fxu,power8lsu,power8vsu,power8misc")
24 (define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu")
25 (define_cpu_unit "lu0_power8,lu1_power8" "power8lsu")
26 (define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu")
27 (define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu")
28 (define_cpu_unit "bpu_power8,cru_power8" "power8misc")
29 (define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\
30 du5_power8,du6_power8" "power8misc")
33 ; Dispatch group reservations
34 (define_reservation "DU_any_power8"
35 "du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\
38 ; 2-way Cracked instructions go in slots 0-1
39 ; (can also have a second in slots 3-4 if insns are adjacent)
40 (define_reservation "DU_cracked_power8"
41 "du0_power8+du1_power8")
43 ; Insns that are first in group
44 (define_reservation "DU_first_power8"
47 ; Insns that are first and last in group
48 (define_reservation "DU_both_power8"
49 "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\
50 du5_power8+du6_power8")
52 ; Dispatch slots are allocated in order conforming to program order.
53 (absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\
54 du5_power8,du6_power8")
55 (absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\
57 (absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8")
58 (absence_set "du3_power8" "du4_power8,du5_power8,du6_power8")
59 (absence_set "du4_power8" "du5_power8,du6_power8")
60 (absence_set "du5_power8" "du6_power8")
63 ; Execution unit reservations
64 (define_reservation "FXU_power8"
65 "fxu0_power8|fxu1_power8")
67 (define_reservation "LU_power8"
68 "lu0_power8|lu1_power8")
70 (define_reservation "LSU_power8"
71 "lsu0_power8|lsu1_power8")
73 (define_reservation "LU_or_LSU_power8"
74 "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8")
76 (define_reservation "VSU_power8"
77 "vsu0_power8|vsu1_power8")
81 (define_insn_reservation "power8-load" 3
82 (and (eq_attr "type" "load")
83 (eq_attr "sign_extend" "no")
84 (eq_attr "update" "no")
85 (eq_attr "cpu" "power8"))
86 "DU_any_power8,LU_or_LSU_power8")
88 (define_insn_reservation "power8-load-update" 3
89 (and (eq_attr "type" "load")
90 (eq_attr "sign_extend" "no")
91 (eq_attr "update" "yes")
92 (eq_attr "cpu" "power8"))
93 "DU_cracked_power8,LU_or_LSU_power8+FXU_power8")
95 (define_insn_reservation "power8-load-ext" 3
96 (and (eq_attr "type" "load")
97 (eq_attr "sign_extend" "yes")
98 (eq_attr "update" "no")
99 (eq_attr "cpu" "power8"))
100 "DU_cracked_power8,LU_or_LSU_power8,FXU_power8")
102 (define_insn_reservation "power8-load-ext-update" 3
103 (and (eq_attr "type" "load")
104 (eq_attr "sign_extend" "yes")
105 (eq_attr "update" "yes")
106 (eq_attr "cpu" "power8"))
107 "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")
109 (define_insn_reservation "power8-fpload" 5
110 (and (ior (eq_attr "type" "vecload")
111 (and (eq_attr "type" "fpload")
112 (eq_attr "update" "no")))
113 (eq_attr "cpu" "power8"))
114 "DU_any_power8,LU_power8")
116 (define_insn_reservation "power8-fpload-update" 5
117 (and (eq_attr "type" "fpload")
118 (eq_attr "update" "yes")
119 (eq_attr "cpu" "power8"))
120 "DU_cracked_power8,LU_power8+FXU_power8")
122 (define_insn_reservation "power8-store" 5 ; store-forwarding latency
123 (and (eq_attr "type" "store")
124 (not (and (eq_attr "update" "yes")
125 (eq_attr "indexed" "yes")))
126 (eq_attr "cpu" "power8"))
127 "DU_any_power8,LSU_power8+LU_power8")
129 (define_insn_reservation "power8-store-update-indexed" 5
130 (and (eq_attr "type" "store")
131 (eq_attr "update" "yes")
132 (eq_attr "indexed" "yes")
133 (eq_attr "cpu" "power8"))
134 "DU_cracked_power8,LSU_power8+LU_power8")
136 (define_insn_reservation "power8-fpstore" 5
137 (and (eq_attr "type" "fpstore")
138 (eq_attr "update" "no")
139 (eq_attr "cpu" "power8"))
140 "DU_any_power8,LSU_power8+VSU_power8")
142 (define_insn_reservation "power8-fpstore-update" 5
143 (and (eq_attr "type" "fpstore")
144 (eq_attr "update" "yes")
145 (eq_attr "cpu" "power8"))
146 "DU_any_power8,LSU_power8+VSU_power8")
148 (define_insn_reservation "power8-vecstore" 5
149 (and (eq_attr "type" "vecstore")
150 (eq_attr "cpu" "power8"))
151 "DU_cracked_power8,LSU_power8+VSU_power8")
153 (define_insn_reservation "power8-larx" 3
154 (and (eq_attr "type" "load_l")
155 (eq_attr "cpu" "power8"))
156 "DU_both_power8,LU_or_LSU_power8")
158 (define_insn_reservation "power8-stcx" 10
159 (and (eq_attr "type" "store_c")
160 (eq_attr "cpu" "power8"))
161 "DU_both_power8,LSU_power8+LU_power8")
163 (define_insn_reservation "power8-sync" 1
164 (and (eq_attr "type" "sync,isync")
165 (eq_attr "cpu" "power8"))
166 "DU_both_power8,LSU_power8")
170 (define_insn_reservation "power8-1cyc" 1
171 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
172 var_shift_rotate,exts,isel")
173 (eq_attr "cpu" "power8"))
174 "DU_any_power8,FXU_power8")
176 ; Extra cycle to LU/LSU
177 (define_bypass 2 "power8-1cyc"
178 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
179 power8-vecstore,power8-larx,power8-stcx")
180 ; "power8-load,power8-load-update,power8-load-ext,\
181 ; power8-load-ext-update,power8-fpload,power8-fpload-update,\
182 ; power8-store,power8-store-update,power8-store-update-indexed,\
183 ; power8-fpstore,power8-fpstore-update,power8-vecstore,\
184 ; power8-larx,power8-stcx")
186 (define_insn_reservation "power8-2cyc" 2
187 (and (eq_attr "type" "cntlz,popcnt")
188 (eq_attr "cpu" "power8"))
189 "DU_any_power8,FXU_power8")
191 (define_insn_reservation "power8-two" 2
192 (and (eq_attr "type" "two")
193 (eq_attr "cpu" "power8"))
194 "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8")
196 (define_insn_reservation "power8-three" 3
197 (and (eq_attr "type" "three")
198 (eq_attr "cpu" "power8"))
199 "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8")
201 ; cmp - Normal compare insns
202 (define_insn_reservation "power8-cmp" 2
203 (and (eq_attr "type" "cmp")
204 (eq_attr "cpu" "power8"))
205 "DU_any_power8,FXU_power8")
207 ; fast_compare : add./and./nor./etc
208 (define_insn_reservation "power8-fast-compare" 2
209 (and (eq_attr "type" "fast_compare")
210 (eq_attr "cpu" "power8"))
211 "DU_any_power8,FXU_power8")
213 ; compare : rldicl./exts./etc
214 ; delayed_compare : rlwinm./slwi./etc
215 ; var_delayed_compare : rlwnm./slw./etc
216 (define_insn_reservation "power8-compare" 2
217 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
218 (eq_attr "cpu" "power8"))
219 "DU_cracked_power8,FXU_power8,FXU_power8")
221 ; Extra cycle to LU/LSU
222 (define_bypass 3 "power8-fast-compare,power8-compare"
223 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
224 power8-vecstore,power8-larx,power8-stcx")
227 (define_bypass 5 "power8-fast-compare,power8-compare"
228 "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
230 (define_insn_reservation "power8-mul" 4
231 (and (eq_attr "type" "imul,imul2,imul3,lmul")
232 (eq_attr "cpu" "power8"))
233 "DU_any_power8,FXU_power8")
235 (define_insn_reservation "power8-mul-compare" 4
236 (and (eq_attr "type" "imul_compare,lmul_compare")
237 (eq_attr "cpu" "power8"))
238 "DU_cracked_power8,FXU_power8")
240 ; Extra cycle to LU/LSU
241 (define_bypass 5 "power8-mul,power8-mul-compare"
242 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
243 power8-vecstore,power8-larx,power8-stcx")
246 (define_bypass 7 "power8-mul,power8-mul-compare"
247 "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
249 ; FXU divides are not pipelined
250 (define_insn_reservation "power8-idiv" 37
251 (and (eq_attr "type" "idiv")
252 (eq_attr "cpu" "power8"))
253 "DU_any_power8,fxu0_power8*37|fxu1_power8*37")
255 (define_insn_reservation "power8-ldiv" 68
256 (and (eq_attr "type" "ldiv")
257 (eq_attr "cpu" "power8"))
258 "DU_any_power8,fxu0_power8*68|fxu1_power8*68")
260 (define_insn_reservation "power8-mtjmpr" 5
261 (and (eq_attr "type" "mtjmpr")
262 (eq_attr "cpu" "power8"))
263 "DU_first_power8,FXU_power8")
265 ; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode
266 (define_insn_reservation "power8-mtcr" 3
267 (and (eq_attr "type" "mtcr")
268 (eq_attr "cpu" "power8"))
269 "DU_both_power8,FXU_power8")
273 (define_insn_reservation "power8-mfjmpr" 5
274 (and (eq_attr "type" "mfjmpr")
275 (eq_attr "cpu" "power8"))
276 "DU_first_power8,cru_power8+FXU_power8")
278 (define_insn_reservation "power8-crlogical" 3
279 (and (eq_attr "type" "cr_logical,delayed_cr")
280 (eq_attr "cpu" "power8"))
281 "DU_first_power8,cru_power8")
283 (define_insn_reservation "power8-mfcr" 5
284 (and (eq_attr "type" "mfcr")
285 (eq_attr "cpu" "power8"))
286 "DU_both_power8,cru_power8")
288 (define_insn_reservation "power8-mfcrf" 3
289 (and (eq_attr "type" "mfcrf")
290 (eq_attr "cpu" "power8"))
291 "DU_first_power8,cru_power8")
295 ; Branches take dispatch slot 7, but reserve any remaining prior slots to
296 ; prevent other insns from grabbing them once this is assigned.
297 (define_insn_reservation "power8-branch" 3
298 (and (eq_attr "type" "jmpreg,branch")
299 (eq_attr "cpu" "power8"))
301 |du5_power8+du6_power8\
302 |du4_power8+du5_power8+du6_power8\
303 |du3_power8+du4_power8+du5_power8+du6_power8\
304 |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
305 |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
306 |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\
307 du6_power8),bpu_power8")
309 ; Branch updating LR/CTR feeding mf[lr|ctr]
310 (define_bypass 4 "power8-branch" "power8-mfjmpr")
313 ; VS Unit (includes FP/VSX/VMX/DFP/Crypto)
314 (define_insn_reservation "power8-fp" 6
315 (and (eq_attr "type" "fp,dmul")
316 (eq_attr "cpu" "power8"))
317 "DU_any_power8,VSU_power8")
319 ; Additional 3 cycles for any CR result
320 (define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch")
322 (define_insn_reservation "power8-fpcompare" 8
323 (and (eq_attr "type" "fpcompare")
324 (eq_attr "cpu" "power8"))
325 "DU_any_power8,VSU_power8")
327 (define_insn_reservation "power8-sdiv" 27
328 (and (eq_attr "type" "sdiv")
329 (eq_attr "cpu" "power8"))
330 "DU_any_power8,VSU_power8")
332 (define_insn_reservation "power8-ddiv" 33
333 (and (eq_attr "type" "ddiv")
334 (eq_attr "cpu" "power8"))
335 "DU_any_power8,VSU_power8")
337 (define_insn_reservation "power8-sqrt" 32
338 (and (eq_attr "type" "ssqrt")
339 (eq_attr "cpu" "power8"))
340 "DU_any_power8,VSU_power8")
342 (define_insn_reservation "power8-dsqrt" 44
343 (and (eq_attr "type" "dsqrt")
344 (eq_attr "cpu" "power8"))
345 "DU_any_power8,VSU_power8")
347 (define_insn_reservation "power8-vecsimple" 2
348 (and (eq_attr "type" "vecperm,vecsimple,veccmp")
349 (eq_attr "cpu" "power8"))
350 "DU_any_power8,VSU_power8")
352 (define_insn_reservation "power8-vecnormal" 6
353 (and (eq_attr "type" "vecfloat,vecdouble")
354 (eq_attr "cpu" "power8"))
355 "DU_any_power8,VSU_power8")
357 (define_bypass 7 "power8-vecnormal"
358 "power8-vecsimple,power8-veccomplex,power8-fpstore*,\
361 (define_insn_reservation "power8-veccomplex" 7
362 (and (eq_attr "type" "veccomplex")
363 (eq_attr "cpu" "power8"))
364 "DU_any_power8,VSU_power8")
366 (define_insn_reservation "power8-vecfdiv" 25
367 (and (eq_attr "type" "vecfdiv")
368 (eq_attr "cpu" "power8"))
369 "DU_any_power8,VSU_power8")
371 (define_insn_reservation "power8-vecdiv" 31
372 (and (eq_attr "type" "vecdiv")
373 (eq_attr "cpu" "power8"))
374 "DU_any_power8,VSU_power8")
376 (define_insn_reservation "power8-mffgpr" 5
377 (and (eq_attr "type" "mffgpr")
378 (eq_attr "cpu" "power8"))
379 "DU_any_power8,VSU_power8")
381 (define_insn_reservation "power8-mftgpr" 6
382 (and (eq_attr "type" "mftgpr")
383 (eq_attr "cpu" "power8"))
384 "DU_any_power8,VSU_power8")
386 (define_insn_reservation "power8-crypto" 7
387 (and (eq_attr "type" "crypto")
388 (eq_attr "cpu" "power8"))
389 "DU_any_power8,VSU_power8")