1 ;; Scheduling description for IBM POWER6 processor.
2 ;; Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
23 ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
24 ;; (2 engines per chip). The chip can issue up to 5 internal ops
27 (define_automaton "power6iu,power6lsu,power6fpu,power6bu")
29 (define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
30 (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
31 (define_cpu_unit "bpu_power6" "power6bu")
32 (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
34 (define_reservation "LS2_power6"
35 "lsu1_power6+lsu2_power6")
37 (define_reservation "FPU_power6"
38 "fpu1_power6|fpu2_power6")
40 (define_reservation "BRU_power6"
43 (define_reservation "LSU_power6"
44 "lsu1_power6|lsu2_power6")
46 (define_reservation "LSF_power6"
47 "(lsu1_power6+fpu1_power6)\
48 |(lsu1_power6+fpu2_power6)\
49 |(lsu2_power6+fpu1_power6)\
50 |(lsu2_power6+fpu2_power6)")
52 (define_reservation "LX2_power6"
53 "(iu1_power6+iu2_power6+lsu1_power6)\
54 |(iu1_power6+iu2_power6+lsu2_power6)")
56 (define_reservation "FX2_power6"
57 "iu1_power6+iu2_power6")
59 (define_reservation "X2F_power6"
60 "(iu1_power6+iu2_power6+fpu1_power6)\
61 |(iu1_power6+iu2_power6+fpu2_power6)")
63 (define_reservation "BX2_power6"
64 "iu1_power6+iu2_power6+bpu_power6")
66 (define_reservation "LSX_power6"
67 "(iu1_power6+lsu1_power6)\
68 |(iu1_power6+lsu2_power6)\
69 |(iu2_power6+lsu1_power6)\
70 |(iu2_power6+lsu2_power6)")
72 (define_reservation "FXU_power6"
73 "iu1_power6|iu2_power6")
75 (define_reservation "XLF_power6"
76 "(iu1_power6+lsu1_power6+fpu1_power6)\
77 |(iu1_power6+lsu1_power6+fpu2_power6)\
78 |(iu1_power6+lsu2_power6+fpu1_power6)\
79 |(iu1_power6+lsu2_power6+fpu2_power6)\
80 |(iu2_power6+lsu1_power6+fpu1_power6)\
81 |(iu2_power6+lsu1_power6+fpu2_power6)\
82 |(iu2_power6+lsu2_power6+fpu1_power6)\
83 |(iu2_power6+lsu2_power6+fpu2_power6)")
85 (define_reservation "BRX_power6"
86 "(bpu_power6+iu1_power6)\
87 |(bpu_power6+iu2_power6)")
91 ; The default for a value written by a fixed point load
92 ; that is read/written by a subsequent fixed point op.
93 (define_insn_reservation "power6-load" 2 ; fx
94 (and (eq_attr "type" "load")
95 (eq_attr "sign_extend" "no")
96 (eq_attr "update" "no")
97 (eq_attr "cpu" "power6"))
100 ; define the bypass for the case where the value written
101 ; by a fixed point load is used as the source value on
103 (define_bypass 1 "power6-load,\
105 power6-load-update-indexed"
107 power6-store-update,\
108 power6-store-update-indexed,\
110 power6-fpstore-update"
111 "store_data_bypass_p")
113 (define_insn_reservation "power6-load-ext" 4 ; fx
114 (and (eq_attr "type" "load")
115 (eq_attr "sign_extend" "yes")
116 (eq_attr "update" "no")
117 (eq_attr "cpu" "power6"))
120 ; define the bypass for the case where the value written
121 ; by a fixed point load ext is used as the source value on
123 (define_bypass 1 "power6-load-ext,\
124 power6-load-ext-update,\
125 power6-load-ext-update-indexed"
127 power6-store-update,\
128 power6-store-update-indexed,\
130 power6-fpstore-update"
131 "store_data_bypass_p")
133 (define_insn_reservation "power6-load-update" 2 ; fx
134 (and (eq_attr "type" "load")
135 (eq_attr "sign_extend" "no")
136 (eq_attr "update" "yes")
137 (eq_attr "indexed" "no")
138 (eq_attr "cpu" "power6"))
141 (define_insn_reservation "power6-load-update-indexed" 2 ; fx
142 (and (eq_attr "type" "load")
143 (eq_attr "sign_extend" "no")
144 (eq_attr "update" "yes")
145 (eq_attr "indexed" "yes")
146 (eq_attr "cpu" "power6"))
149 (define_insn_reservation "power6-load-ext-update" 4 ; fx
150 (and (eq_attr "type" "load")
151 (eq_attr "sign_extend" "yes")
152 (eq_attr "update" "yes")
153 (eq_attr "indexed" "no")
154 (eq_attr "cpu" "power6"))
157 (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
158 (and (eq_attr "type" "load")
159 (eq_attr "sign_extend" "yes")
160 (eq_attr "update" "yes")
161 (eq_attr "indexed" "yes")
162 (eq_attr "cpu" "power6"))
165 (define_insn_reservation "power6-fpload" 1
166 (and (eq_attr "type" "fpload")
167 (eq_attr "update" "no")
168 (eq_attr "cpu" "power6"))
171 (define_insn_reservation "power6-fpload-update" 1
172 (and (eq_attr "type" "fpload")
173 (eq_attr "update" "yes")
174 (eq_attr "cpu" "power6"))
177 (define_insn_reservation "power6-store" 14
178 (and (eq_attr "type" "store")
179 (eq_attr "update" "no")
180 (eq_attr "cpu" "power6"))
183 (define_insn_reservation "power6-store-update" 14
184 (and (eq_attr "type" "store")
185 (eq_attr "update" "yes")
186 (eq_attr "indexed" "no")
187 (eq_attr "cpu" "power6"))
190 (define_insn_reservation "power6-store-update-indexed" 14
191 (and (eq_attr "type" "store")
192 (eq_attr "update" "yes")
193 (eq_attr "indexed" "yes")
194 (eq_attr "cpu" "power6"))
197 (define_insn_reservation "power6-fpstore" 14
198 (and (eq_attr "type" "fpstore")
199 (eq_attr "update" "no")
200 (eq_attr "cpu" "power6"))
203 (define_insn_reservation "power6-fpstore-update" 14
204 (and (eq_attr "type" "fpstore")
205 (eq_attr "update" "yes")
206 (eq_attr "cpu" "power6"))
209 (define_insn_reservation "power6-larx" 3
210 (and (eq_attr "type" "load_l")
211 (eq_attr "cpu" "power6"))
214 (define_insn_reservation "power6-stcx" 10 ; best case
215 (and (eq_attr "type" "store_c")
216 (eq_attr "cpu" "power6"))
219 (define_insn_reservation "power6-sync" 11 ; N/A
220 (and (eq_attr "type" "sync")
221 (eq_attr "cpu" "power6"))
224 (define_insn_reservation "power6-integer" 1
225 (and (eq_attr "type" "integer")
226 (eq_attr "cpu" "power6"))
229 (define_insn_reservation "power6-isel" 1
230 (and (eq_attr "type" "isel")
231 (eq_attr "cpu" "power6"))
234 (define_insn_reservation "power6-exts" 1
235 (and (eq_attr "type" "exts")
236 (eq_attr "cpu" "power6"))
239 (define_insn_reservation "power6-shift" 1
240 (and (eq_attr "type" "shift")
241 (eq_attr "cpu" "power6"))
244 (define_insn_reservation "power6-popcnt" 1
245 (and (eq_attr "type" "popcnt")
246 (eq_attr "cpu" "power6"))
249 (define_insn_reservation "power6-insert" 1
250 (and (eq_attr "type" "insert_word")
251 (eq_attr "cpu" "power6"))
254 (define_insn_reservation "power6-insert-dword" 1
255 (and (eq_attr "type" "insert_dword")
256 (eq_attr "cpu" "power6"))
259 ; define the bypass for the case where the value written
260 ; by a fixed point op is used as the source value on a
262 (define_bypass 1 "power6-integer,\
268 power6-store-update,\
269 power6-store-update-indexed,\
271 power6-fpstore-update"
272 "store_data_bypass_p")
274 (define_insn_reservation "power6-cntlz" 2
275 (and (eq_attr "type" "cntlz")
276 (eq_attr "cpu" "power6"))
279 (define_bypass 1 "power6-cntlz"
281 power6-store-update,\
282 power6-store-update-indexed,\
284 power6-fpstore-update"
285 "store_data_bypass_p")
287 (define_insn_reservation "power6-var-rotate" 4
288 (and (eq_attr "type" "var_shift_rotate")
289 (eq_attr "cpu" "power6"))
292 (define_insn_reservation "power6-trap" 1 ; N/A
293 (and (eq_attr "type" "trap")
294 (eq_attr "cpu" "power6"))
297 (define_insn_reservation "power6-two" 1
298 (and (eq_attr "type" "two")
299 (eq_attr "cpu" "power6"))
300 "(iu1_power6,iu1_power6)\
301 |(iu1_power6+iu2_power6,nothing)\
302 |(iu1_power6,iu2_power6)\
303 |(iu2_power6,iu1_power6)\
304 |(iu2_power6,iu2_power6)")
306 (define_insn_reservation "power6-three" 1
307 (and (eq_attr "type" "three")
308 (eq_attr "cpu" "power6"))
309 "(iu1_power6,iu1_power6,iu1_power6)\
310 |(iu1_power6,iu1_power6,iu2_power6)\
311 |(iu1_power6,iu2_power6,iu1_power6)\
312 |(iu1_power6,iu2_power6,iu2_power6)\
313 |(iu2_power6,iu1_power6,iu1_power6)\
314 |(iu2_power6,iu1_power6,iu2_power6)\
315 |(iu2_power6,iu2_power6,iu1_power6)\
316 |(iu2_power6,iu2_power6,iu2_power6)\
317 |(iu1_power6+iu2_power6,iu1_power6)\
318 |(iu1_power6+iu2_power6,iu2_power6)\
319 |(iu1_power6,iu1_power6+iu2_power6)\
320 |(iu2_power6,iu1_power6+iu2_power6)")
322 (define_insn_reservation "power6-cmp" 1
323 (and (eq_attr "type" "cmp")
324 (eq_attr "cpu" "power6"))
327 (define_insn_reservation "power6-compare" 1
328 (and (eq_attr "type" "compare")
329 (eq_attr "cpu" "power6"))
332 (define_insn_reservation "power6-fast-compare" 1
333 (and (eq_attr "type" "fast_compare")
334 (eq_attr "cpu" "power6"))
337 ; define the bypass for the case where the value written
338 ; by a fixed point rec form op is used as the source value
340 (define_bypass 1 "power6-compare,\
343 power6-store-update,\
344 power6-store-update-indexed,\
346 power6-fpstore-update"
347 "store_data_bypass_p")
349 (define_insn_reservation "power6-delayed-compare" 2 ; N/A
350 (and (eq_attr "type" "delayed_compare")
351 (eq_attr "cpu" "power6"))
354 (define_insn_reservation "power6-var-delayed-compare" 4
355 (and (eq_attr "type" "var_delayed_compare")
356 (eq_attr "cpu" "power6"))
359 (define_insn_reservation "power6-lmul-cmp" 16
360 (and (eq_attr "type" "lmul_compare")
361 (eq_attr "cpu" "power6"))
362 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
363 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
365 (define_insn_reservation "power6-imul-cmp" 16
366 (and (eq_attr "type" "imul_compare")
367 (eq_attr "cpu" "power6"))
368 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
369 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
371 (define_insn_reservation "power6-lmul" 16
372 (and (eq_attr "type" "lmul")
373 (eq_attr "cpu" "power6"))
374 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
375 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
377 (define_insn_reservation "power6-imul" 16
378 (and (eq_attr "type" "imul")
379 (eq_attr "cpu" "power6"))
380 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
381 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
383 (define_insn_reservation "power6-imul3" 16
384 (and (eq_attr "type" "imul2,imul3")
385 (eq_attr "cpu" "power6"))
386 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
387 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
389 (define_bypass 9 "power6-imul,\
395 power6-store-update,\
396 power6-store-update-indexed,\
398 power6-fpstore-update"
399 "store_data_bypass_p")
401 (define_insn_reservation "power6-idiv" 44
402 (and (eq_attr "type" "idiv")
403 (eq_attr "cpu" "power6"))
404 "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
405 |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
407 ; The latency for this bypass is yet to be defined
408 ;(define_bypass ? "power6-idiv"
410 ; power6-store-update,\
411 ; power6-store-update-indexed,\
413 ; power6-fpstore-update"
414 ; "store_data_bypass_p")
416 (define_insn_reservation "power6-ldiv" 56
417 (and (eq_attr "type" "ldiv")
418 (eq_attr "cpu" "power6"))
419 "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
420 |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
422 ; The latency for this bypass is yet to be defined
423 ;(define_bypass ? "power6-ldiv"
425 ; power6-store-update,\
426 ; power6-store-update-indexed,\
428 ; power6-fpstore-update"
429 ; "store_data_bypass_p")
431 (define_insn_reservation "power6-mtjmpr" 2
432 (and (eq_attr "type" "mtjmpr,mfjmpr")
433 (eq_attr "cpu" "power6"))
436 (define_bypass 5 "power6-mtjmpr" "power6-branch")
438 (define_insn_reservation "power6-branch" 2
439 (and (eq_attr "type" "jmpreg,branch")
440 (eq_attr "cpu" "power6"))
443 (define_bypass 5 "power6-branch" "power6-mtjmpr")
445 (define_insn_reservation "power6-crlogical" 3
446 (and (eq_attr "type" "cr_logical")
447 (eq_attr "cpu" "power6"))
450 (define_bypass 3 "power6-crlogical" "power6-branch")
452 (define_insn_reservation "power6-delayedcr" 3
453 (and (eq_attr "type" "delayed_cr")
454 (eq_attr "cpu" "power6"))
457 (define_insn_reservation "power6-mfcr" 6 ; N/A
458 (and (eq_attr "type" "mfcr")
459 (eq_attr "cpu" "power6"))
463 (define_insn_reservation "power6-mfcrf" 3 ; N/A
464 (and (eq_attr "type" "mfcrf")
465 (eq_attr "cpu" "power6"))
469 (define_insn_reservation "power6-mtcr" 4 ; N/A
470 (and (eq_attr "type" "mtcr")
471 (eq_attr "cpu" "power6"))
474 (define_bypass 9 "power6-mtcr" "power6-branch")
476 (define_insn_reservation "power6-fp" 6
477 (and (eq_attr "type" "fp,dmul")
478 (eq_attr "cpu" "power6"))
481 ; Any fp instruction that updates a CR has a latency
482 ; of 6 to a dependent branch
483 (define_bypass 6 "power6-fp" "power6-branch")
485 (define_bypass 1 "power6-fp"
486 "power6-fpstore,power6-fpstore-update"
487 "store_data_bypass_p")
489 (define_insn_reservation "power6-fpcompare" 8
490 (and (eq_attr "type" "fpcompare")
491 (eq_attr "cpu" "power6"))
494 (define_bypass 12 "power6-fpcompare"
495 "power6-branch,power6-crlogical")
497 (define_insn_reservation "power6-sdiv" 26
498 (and (eq_attr "type" "sdiv")
499 (eq_attr "cpu" "power6"))
502 (define_insn_reservation "power6-ddiv" 32
503 (and (eq_attr "type" "ddiv")
504 (eq_attr "cpu" "power6"))
507 (define_insn_reservation "power6-sqrt" 30
508 (and (eq_attr "type" "ssqrt")
509 (eq_attr "cpu" "power6"))
512 (define_insn_reservation "power6-dsqrt" 42
513 (and (eq_attr "type" "dsqrt")
514 (eq_attr "cpu" "power6"))
517 (define_insn_reservation "power6-isync" 2 ; N/A
518 (and (eq_attr "type" "isync")
519 (eq_attr "cpu" "power6"))
522 (define_insn_reservation "power6-vecload" 1
523 (and (eq_attr "type" "vecload")
524 (eq_attr "cpu" "power6"))
527 (define_insn_reservation "power6-vecstore" 1
528 (and (eq_attr "type" "vecstore")
529 (eq_attr "cpu" "power6"))
532 (define_insn_reservation "power6-vecsimple" 3
533 (and (eq_attr "type" "vecsimple")
534 (eq_attr "cpu" "power6"))
537 (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
540 (define_bypass 5 "power6-vecsimple" "power6-vecfloat")
542 (define_bypass 4 "power6-vecsimple" "power6-vecstore" )
544 (define_insn_reservation "power6-veccmp" 1
545 (and (eq_attr "type" "veccmp")
546 (eq_attr "cpu" "power6"))
549 (define_bypass 10 "power6-veccmp" "power6-branch")
551 (define_insn_reservation "power6-vecfloat" 7
552 (and (eq_attr "type" "vecfloat")
553 (eq_attr "cpu" "power6"))
556 (define_bypass 10 "power6-vecfloat" "power6-vecsimple")
558 (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
561 (define_bypass 9 "power6-vecfloat" "power6-vecstore" )
563 (define_insn_reservation "power6-veccomplex" 7
564 (and (eq_attr "type" "vecsimple")
565 (eq_attr "cpu" "power6"))
568 (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
571 (define_bypass 9 "power6-veccomplex" "power6-vecperm" )
573 (define_bypass 8 "power6-veccomplex" "power6-vecstore" )
575 (define_insn_reservation "power6-vecperm" 4
576 (and (eq_attr "type" "vecperm")
577 (eq_attr "cpu" "power6"))
580 (define_bypass 7 "power6-vecperm" "power6-vecsimple,\
583 (define_bypass 6 "power6-vecperm" "power6-veccomplex" )
585 (define_bypass 5 "power6-vecperm" "power6-vecstore" )
587 (define_insn_reservation "power6-mftgpr" 8
588 (and (eq_attr "type" "mftgpr")
589 (eq_attr "cpu" "power6"))
592 (define_insn_reservation "power6-mffgpr" 14
593 (and (eq_attr "type" "mffgpr")
594 (eq_attr "cpu" "power6"))
597 (define_bypass 4 "power6-mftgpr" "power6-imul,\